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Novasys Ingenierie c83a35f652 fpga: zynq: Correct fpga load when buf is not aligned 
When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is
not aligned, new_buf address became greater then buf_start address and the
load_word loop corrupts bit file data.

A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data
before buf but permits to load correctly.

Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 		2014-02-06 10:08:03 +01:00
..
ACEX1K.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
Makefile drivers: descend into sub directories only when it is necessary 2013-11-17 14:11:30 -05:00
altera.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
cyclon2.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
fpga.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
ivm_core.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
lattice.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
spartan2.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
spartan3.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
stratixII.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
virtex2.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
xilinx.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
zynqpl.c fpga: zynq: Correct fpga load when buf is not aligned 2014-02-06 10:08:03 +01:00