cfb37772a1
On the MX6Q the aclk_eim_slow_podf field is '1' after POR, while on the MX6DQP it is '3'. This makes the EIM clock to be only 66MHz on the mx6qp variant, instead of 132 MHz. Instead of relying on the POR values for the CSMR1 register, make sure to manually configure the clk_eim_slow_sel field as '00' so that EIM clock is derived from AXI clock and the aclk_eim_slow_podf field as '1' so that EIM clock can be AXI clock divided by 2. This way a consistent EIM clock frequency is configured for all the mx6 variants. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> |
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| .. | ||
| Kconfig | ||
| MAINTAINERS | ||
| Makefile | ||
| imximage.cfg | ||
| mx6dl.cfg | ||
| mx6qp.cfg | ||
| mx6qsabreauto.c | ||