Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org>
640 lines
14 KiB
C
640 lines
14 KiB
C
/*
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* Copyright (c) 2014 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <inttypes.h>
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#include <pci.h>
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#include <dm/lists.h>
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#include <dm/root.h>
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#include <dm/device-internal.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct pci_controller *pci_bus_to_hose(int busnum)
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{
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struct udevice *bus;
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int ret;
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ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
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if (ret) {
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debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
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return NULL;
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}
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return dev_get_uclass_priv(bus);
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}
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/**
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* pci_get_bus_max() - returns the bus number of the last active bus
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*
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* @return last bus number, or -1 if no active buses
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*/
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static int pci_get_bus_max(void)
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{
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struct udevice *bus;
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struct uclass *uc;
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int ret = -1;
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ret = uclass_get(UCLASS_PCI, &uc);
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uclass_foreach_dev(bus, uc) {
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if (bus->seq > ret)
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ret = bus->seq;
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}
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debug("%s: ret=%d\n", __func__, ret);
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return ret;
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}
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int pci_last_busno(void)
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{
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struct pci_controller *hose;
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struct udevice *bus;
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struct uclass *uc;
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int ret;
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debug("pci_last_busno\n");
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ret = uclass_get(UCLASS_PCI, &uc);
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if (ret || list_empty(&uc->dev_head))
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return -1;
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/* Probe the last bus */
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bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node);
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debug("bus = %p, %s\n", bus, bus->name);
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assert(bus);
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ret = device_probe(bus);
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if (ret)
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return ret;
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/* If that bus has bridges, we may have new buses now. Get the last */
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bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node);
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hose = dev_get_uclass_priv(bus);
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debug("bus = %s, hose = %p\n", bus->name, hose);
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return hose->last_busno;
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}
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int pci_get_ff(enum pci_size_t size)
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{
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switch (size) {
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case PCI_SIZE_8:
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return 0xff;
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case PCI_SIZE_16:
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return 0xffff;
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default:
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return 0xffffffff;
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}
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}
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int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
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struct udevice **devp)
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{
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struct udevice *dev;
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for (device_find_first_child(bus, &dev);
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dev;
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device_find_next_child(&dev)) {
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struct pci_child_platdata *pplat;
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pplat = dev_get_parent_platdata(dev);
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if (pplat && pplat->devfn == find_devfn) {
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*devp = dev;
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return 0;
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}
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}
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return -ENODEV;
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}
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int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
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{
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struct udevice *bus;
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int ret;
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ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
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if (ret)
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return ret;
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return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
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}
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static int pci_device_matches_ids(struct udevice *dev,
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struct pci_device_id *ids)
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{
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struct pci_child_platdata *pplat;
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int i;
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pplat = dev_get_parent_platdata(dev);
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if (!pplat)
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return -EINVAL;
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for (i = 0; ids[i].vendor != 0; i++) {
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if (pplat->vendor == ids[i].vendor &&
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pplat->device == ids[i].device)
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return i;
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}
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return -EINVAL;
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}
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int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
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int *indexp, struct udevice **devp)
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{
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struct udevice *dev;
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/* Scan all devices on this bus */
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for (device_find_first_child(bus, &dev);
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dev;
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device_find_next_child(&dev)) {
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if (pci_device_matches_ids(dev, ids) >= 0) {
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if ((*indexp)-- <= 0) {
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*devp = dev;
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return 0;
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}
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}
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}
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return -ENODEV;
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}
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int pci_find_device_id(struct pci_device_id *ids, int index,
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struct udevice **devp)
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{
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struct udevice *bus;
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/* Scan all known buses */
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for (uclass_first_device(UCLASS_PCI, &bus);
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bus;
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uclass_next_device(&bus)) {
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if (!pci_bus_find_devices(bus, ids, &index, devp))
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return 0;
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}
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*devp = NULL;
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return -ENODEV;
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}
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int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
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unsigned long value, enum pci_size_t size)
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{
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struct dm_pci_ops *ops;
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ops = pci_get_ops(bus);
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if (!ops->write_config)
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return -ENOSYS;
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return ops->write_config(bus, bdf, offset, value, size);
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}
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int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
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enum pci_size_t size)
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{
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struct udevice *bus;
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int ret;
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ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
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if (ret)
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return ret;
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return pci_bus_write_config(bus, PCI_MASK_BUS(bdf), offset, value,
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size);
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}
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int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
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{
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return pci_write_config(bdf, offset, value, PCI_SIZE_32);
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}
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int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
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{
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return pci_write_config(bdf, offset, value, PCI_SIZE_16);
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}
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int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
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{
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return pci_write_config(bdf, offset, value, PCI_SIZE_8);
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}
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int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
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unsigned long *valuep, enum pci_size_t size)
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{
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struct dm_pci_ops *ops;
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ops = pci_get_ops(bus);
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if (!ops->read_config)
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return -ENOSYS;
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return ops->read_config(bus, bdf, offset, valuep, size);
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}
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int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
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enum pci_size_t size)
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{
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struct udevice *bus;
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int ret;
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ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
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if (ret)
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return ret;
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return pci_bus_read_config(bus, PCI_MASK_BUS(bdf), offset, valuep,
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size);
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}
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int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
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{
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unsigned long value;
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int ret;
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ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
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if (ret)
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return ret;
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*valuep = value;
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return 0;
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}
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int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
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{
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unsigned long value;
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int ret;
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ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
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if (ret)
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return ret;
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*valuep = value;
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return 0;
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}
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int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
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{
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unsigned long value;
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int ret;
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ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
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if (ret)
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return ret;
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*valuep = value;
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return 0;
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}
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int pci_auto_config_devices(struct udevice *bus)
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{
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struct pci_controller *hose = bus->uclass_priv;
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unsigned int sub_bus;
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struct udevice *dev;
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int ret;
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sub_bus = bus->seq;
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debug("%s: start\n", __func__);
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pciauto_config_init(hose);
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for (ret = device_find_first_child(bus, &dev);
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!ret && dev;
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ret = device_find_next_child(&dev)) {
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struct pci_child_platdata *pplat;
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pplat = dev_get_parent_platdata(dev);
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unsigned int max_bus;
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pci_dev_t bdf;
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bdf = PCI_ADD_BUS(bus->seq, pplat->devfn);
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debug("%s: device %s\n", __func__, dev->name);
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max_bus = pciauto_config_device(hose, bdf);
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sub_bus = max(sub_bus, max_bus);
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}
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debug("%s: done\n", __func__);
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return sub_bus;
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}
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int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
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{
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struct udevice *parent, *bus;
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int sub_bus;
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int ret;
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debug("%s\n", __func__);
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parent = hose->bus;
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/* Find the bus within the parent */
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ret = pci_bus_find_devfn(parent, bdf, &bus);
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if (ret) {
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debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
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bdf, parent->name, ret);
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return ret;
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}
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sub_bus = pci_get_bus_max() + 1;
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debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
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pciauto_prescan_setup_bridge(hose, bdf, bus->seq);
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ret = device_probe(bus);
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if (ret) {
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debug("%s: Cannot probe bus bus %s: %d\n", __func__, bus->name,
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ret);
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return ret;
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}
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if (sub_bus != bus->seq) {
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printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
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__func__, bus->name, bus->seq, sub_bus);
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return -EPIPE;
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}
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sub_bus = pci_get_bus_max();
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pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
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return sub_bus;
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}
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int pci_bind_bus_devices(struct udevice *bus)
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{
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ulong vendor, device;
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ulong header_type;
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pci_dev_t devfn, end;
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bool found_multi;
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int ret;
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found_multi = false;
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end = PCI_DEVFN(PCI_MAX_PCI_DEVICES - 1, PCI_MAX_PCI_FUNCTIONS - 1);
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for (devfn = PCI_DEVFN(0, 0); devfn < end; devfn += PCI_DEVFN(0, 1)) {
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struct pci_child_platdata *pplat;
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struct udevice *dev;
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ulong class;
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if (PCI_FUNC(devfn) && !found_multi)
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continue;
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/* Check only the first access, we don't expect problems */
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ret = pci_bus_read_config(bus, devfn, PCI_HEADER_TYPE,
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&header_type, PCI_SIZE_8);
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if (ret)
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goto error;
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pci_bus_read_config(bus, devfn, PCI_VENDOR_ID, &vendor,
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PCI_SIZE_16);
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if (vendor == 0xffff || vendor == 0x0000)
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continue;
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if (!PCI_FUNC(devfn))
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found_multi = header_type & 0x80;
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debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
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bus->seq, bus->name, PCI_DEV(devfn), PCI_FUNC(devfn));
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pci_bus_read_config(bus, devfn, PCI_DEVICE_ID, &device,
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PCI_SIZE_16);
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pci_bus_read_config(bus, devfn, PCI_CLASS_DEVICE, &class,
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PCI_SIZE_16);
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/* Find this device in the device tree */
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ret = pci_bus_find_devfn(bus, devfn, &dev);
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/* If nothing in the device tree, bind a generic device */
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if (ret == -ENODEV) {
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char name[30], *str;
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const char *drv;
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sprintf(name, "pci_%x:%x.%x", bus->seq,
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PCI_DEV(devfn), PCI_FUNC(devfn));
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str = strdup(name);
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if (!str)
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return -ENOMEM;
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drv = class == PCI_CLASS_BRIDGE_PCI ?
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"pci_bridge_drv" : "pci_generic_drv";
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ret = device_bind_driver(bus, drv, str, &dev);
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}
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if (ret)
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return ret;
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/* Update the platform data */
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pplat = dev_get_parent_platdata(dev);
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pplat->devfn = devfn;
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pplat->vendor = vendor;
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pplat->device = device;
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pplat->class = class;
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}
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return 0;
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error:
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printf("Cannot read bus configuration: %d\n", ret);
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return ret;
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}
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static int pci_uclass_post_bind(struct udevice *bus)
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{
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/*
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* Scan the device tree for devices. This does not probe the PCI bus,
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* as this is not permitted while binding. It just finds devices
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* mentioned in the device tree.
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*
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* Before relocation, only bind devices marked for pre-relocation
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* use.
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*/
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return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
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gd->flags & GD_FLG_RELOC ? false : true);
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}
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static int decode_regions(struct pci_controller *hose, const void *blob,
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int parent_node, int node)
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{
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int pci_addr_cells, addr_cells, size_cells;
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int cells_per_record;
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const u32 *prop;
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int len;
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int i;
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prop = fdt_getprop(blob, node, "ranges", &len);
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if (!prop)
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return -EINVAL;
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pci_addr_cells = fdt_address_cells(blob, node);
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addr_cells = fdt_address_cells(blob, parent_node);
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size_cells = fdt_size_cells(blob, node);
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/* PCI addresses are always 3-cells */
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len /= sizeof(u32);
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cells_per_record = pci_addr_cells + addr_cells + size_cells;
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hose->region_count = 0;
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debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
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cells_per_record);
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for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
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u64 pci_addr, addr, size;
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int space_code;
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u32 flags;
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int type;
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if (len < cells_per_record)
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break;
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flags = fdt32_to_cpu(prop[0]);
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space_code = (flags >> 24) & 3;
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pci_addr = fdtdec_get_number(prop + 1, 2);
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prop += pci_addr_cells;
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addr = fdtdec_get_number(prop, addr_cells);
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prop += addr_cells;
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size = fdtdec_get_number(prop, size_cells);
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prop += size_cells;
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debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
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", size=%" PRIx64 ", space_code=%d\n", __func__,
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hose->region_count, pci_addr, addr, size, space_code);
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if (space_code & 2) {
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type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
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PCI_REGION_MEM;
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} else if (space_code & 1) {
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type = PCI_REGION_IO;
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} else {
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continue;
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}
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debug(" - type=%d\n", type);
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pci_set_region(hose->regions + hose->region_count++, pci_addr,
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addr, size, type);
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}
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/* Add a region for our local memory */
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pci_set_region(hose->regions + hose->region_count++, 0, 0,
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gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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return 0;
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}
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static int pci_uclass_pre_probe(struct udevice *bus)
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{
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struct pci_controller *hose;
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int ret;
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debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
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bus->parent->name);
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hose = bus->uclass_priv;
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/* For bridges, use the top-level PCI controller */
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if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
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hose->ctlr = bus;
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ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
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bus->of_offset);
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if (ret) {
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debug("%s: Cannot decode regions\n", __func__);
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return ret;
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}
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} else {
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struct pci_controller *parent_hose;
|
|
|
|
parent_hose = dev_get_uclass_priv(bus->parent);
|
|
hose->ctlr = parent_hose->bus;
|
|
}
|
|
hose->bus = bus;
|
|
hose->first_busno = bus->seq;
|
|
hose->last_busno = bus->seq;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pci_uclass_post_probe(struct udevice *bus)
|
|
{
|
|
int ret;
|
|
|
|
/* Don't scan buses before relocation */
|
|
if (!(gd->flags & GD_FLG_RELOC))
|
|
return 0;
|
|
|
|
debug("%s: probing bus %d\n", __func__, bus->seq);
|
|
ret = pci_bind_bus_devices(bus);
|
|
if (ret)
|
|
return ret;
|
|
|
|
#ifdef CONFIG_PCI_PNP
|
|
ret = pci_auto_config_devices(bus);
|
|
#endif
|
|
|
|
return ret < 0 ? ret : 0;
|
|
}
|
|
|
|
static int pci_uclass_child_post_bind(struct udevice *dev)
|
|
{
|
|
struct pci_child_platdata *pplat;
|
|
struct fdt_pci_addr addr;
|
|
int ret;
|
|
|
|
if (dev->of_offset == -1)
|
|
return 0;
|
|
|
|
/*
|
|
* We could read vendor, device, class if available. But for now we
|
|
* just check the address.
|
|
*/
|
|
pplat = dev_get_parent_platdata(dev);
|
|
ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
|
|
FDT_PCI_SPACE_CONFIG, "reg", &addr);
|
|
|
|
if (ret) {
|
|
if (ret != -ENOENT)
|
|
return -EINVAL;
|
|
} else {
|
|
/* extract the bdf from fdt_pci_addr */
|
|
pplat->devfn = addr.phys_hi & 0xffff00;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int pci_bridge_read_config(struct udevice *bus, pci_dev_t devfn, uint offset,
|
|
ulong *valuep, enum pci_size_t size)
|
|
{
|
|
struct pci_controller *hose = bus->uclass_priv;
|
|
pci_dev_t bdf = PCI_ADD_BUS(bus->seq, devfn);
|
|
|
|
return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
|
|
}
|
|
|
|
int pci_bridge_write_config(struct udevice *bus, pci_dev_t devfn, uint offset,
|
|
ulong value, enum pci_size_t size)
|
|
{
|
|
struct pci_controller *hose = bus->uclass_priv;
|
|
pci_dev_t bdf = PCI_ADD_BUS(bus->seq, devfn);
|
|
|
|
return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
|
|
}
|
|
|
|
UCLASS_DRIVER(pci) = {
|
|
.id = UCLASS_PCI,
|
|
.name = "pci",
|
|
.post_bind = pci_uclass_post_bind,
|
|
.pre_probe = pci_uclass_pre_probe,
|
|
.post_probe = pci_uclass_post_probe,
|
|
.child_post_bind = pci_uclass_child_post_bind,
|
|
.per_device_auto_alloc_size = sizeof(struct pci_controller),
|
|
.per_child_platdata_auto_alloc_size =
|
|
sizeof(struct pci_child_platdata),
|
|
};
|
|
|
|
static const struct dm_pci_ops pci_bridge_ops = {
|
|
.read_config = pci_bridge_read_config,
|
|
.write_config = pci_bridge_write_config,
|
|
};
|
|
|
|
static const struct udevice_id pci_bridge_ids[] = {
|
|
{ .compatible = "pci-bridge" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(pci_bridge_drv) = {
|
|
.name = "pci_bridge_drv",
|
|
.id = UCLASS_PCI,
|
|
.of_match = pci_bridge_ids,
|
|
.ops = &pci_bridge_ops,
|
|
};
|
|
|
|
UCLASS_DRIVER(pci_generic) = {
|
|
.id = UCLASS_PCI_GENERIC,
|
|
.name = "pci_generic",
|
|
};
|
|
|
|
static const struct udevice_id pci_generic_ids[] = {
|
|
{ .compatible = "pci-generic" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(pci_generic_drv) = {
|
|
.name = "pci_generic_drv",
|
|
.id = UCLASS_PCI_GENERIC,
|
|
.of_match = pci_generic_ids,
|
|
};
|