u-boot/board/freescale/p2041rdb
Shaohui Xie 4497861ae7 p2041rdb: fix serdes clock map
Description of SerDes clock Bank2 setting in p2041 hardware specification
is wrong, the clock map which based on it is wrong either, so fix the
serdes clock map.

wrong setting of SERDES Reference Clocks Bank2:
SW2[5:6] = ON OFF	=>100MHz for PCI mode
SW2[5:6] = OFF ON	=>125MHz for SGMII mode

right setting of SERDES Reference Clocks Bank2:
SW2[5:6] = OFF OFF	=>100MHz for PCI mode
SW2[5:6] = OFF ON	=>125MHz for SGMII mode
SW2[5:6] = ON OFF	=>156.25MHZ

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-12-06 21:44:33 -06:00
..
cpld.c powerpc/p2041rdb: remove watch dog related codes 2011-10-03 08:52:13 -05:00
cpld.h powerpc/p2041rdb: remove watch dog related codes 2011-10-03 08:52:13 -05:00
ddr.c powerpc/mpc8xxx: Merge entries in DDR speed table 2011-10-09 17:57:53 -05:00
eth.c powerpc/QorIQ: fix network frame manager TBI PHY address settings 2011-11-08 08:18:16 -06:00
Makefile punt unused clean/distclean targets 2011-10-15 22:20:36 +02:00
p2041rdb.c p2041rdb: fix serdes clock map 2011-12-06 21:44:33 -06:00