Clean up added ehci-omap.c and make it generic for re-use across omap-soc having same ehci ip block. Also pass the modes to be configured from board file and configure the ports accordingly. All usb layers are not cache aligned, till then keep cache off for usb ops as ehci will use internally dma for all usb ops. * Add a generic common header ehci-omap.h having common ip block data and reg shifts. * Rename and modify ehci-omap3 to ehci.h retain only conflicting sysc reg shifts remove others and move to common header file. * pass the board data for beagle/panda accordinly to use ehci ports. Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
256 lines
7 KiB
C
256 lines
7 KiB
C
/*
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* (C) Copyright 2011 Ilya Yanok, Emcraft Systems
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* (C) Copyright 2004-2008
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* Texas Instruments, <www.ti.com>
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*
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* Derived from Beagle Board code by
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* Sunil Kumar <sunilsaini05@gmail.com>
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* Shashi Ranjan <shashiranjanmca05@gmail.com>
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*
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <common.h>
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#include <usb.h>
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#include <usb/ulpi.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/ehci.h>
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#include <asm/ehci-omap.h>
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#include "ehci-core.h"
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static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
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static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
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static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
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static int omap_uhh_reset(void)
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{
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unsigned long init = get_timer(0);
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/* perform UHH soft reset, and wait until reset is complete */
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writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
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/* Wait for UHH reset to complete */
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while (!(readl(&uhh->syss) & OMAP_UHH_SYSSTATUS_EHCI_RESETDONE))
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if (get_timer(init) > CONFIG_SYS_HZ) {
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debug("OMAP UHH error: timeout resetting ehci\n");
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return -EL3RST;
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}
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return 0;
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}
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static int omap_ehci_tll_reset(void)
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{
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unsigned long init = get_timer(0);
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/* perform TLL soft reset, and wait until reset is complete */
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writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
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/* Wait for TLL reset to complete */
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while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
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if (get_timer(init) > CONFIG_SYS_HZ) {
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debug("OMAP EHCI error: timeout resetting TLL\n");
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return -EL3RST;
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}
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return 0;
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}
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static void omap_usbhs_hsic_init(int port)
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{
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unsigned int reg;
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/* Enable channels now */
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reg = readl(&usbtll->channel_conf + port);
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setbits_le32(®, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
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| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
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| OMAP_TLL_CHANNEL_CONF_DRVVBUS
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| OMAP_TLL_CHANNEL_CONF_CHRGVBUS
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| OMAP_TLL_CHANNEL_CONF_CHANEN));
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writel(reg, &usbtll->channel_conf + port);
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}
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static void omap_ehci_soft_phy_reset(int port)
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{
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struct ulpi_viewport ulpi_vp;
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ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
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ulpi_vp.port_num = port;
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ulpi_reset(&ulpi_vp);
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}
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inline int __board_usb_init(void)
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{
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return 0;
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}
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int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
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#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
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defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)
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/* controls PHY(s) reset signal(s) */
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static inline void omap_ehci_phy_reset(int on, int delay)
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{
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/*
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* Refer ISSUE1:
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* Hold the PHY in RESET for enough time till
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* PHY is settled and ready
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*/
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if (delay && !on)
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udelay(delay);
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#ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
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gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
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gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
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#endif
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#ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
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gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
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gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
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#endif
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/* Hold the PHY in RESET for enough time till DIR is high */
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/* Refer: ISSUE1 */
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if (delay && on)
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udelay(delay);
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}
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#else
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#define omap_ehci_phy_reset(on, delay) do {} while (0)
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#endif
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/* Reset is needed otherwise the kernel-driver will throw an error. */
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int omap_ehci_hcd_stop(void)
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{
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debug("Resetting OMAP EHCI\n");
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omap_ehci_phy_reset(1, 0);
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if (omap_uhh_reset() < 0)
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return -1;
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if (omap_ehci_tll_reset() < 0)
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return -1;
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return 0;
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}
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/*
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* Initialize the OMAP EHCI controller and PHY.
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* Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
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* See there for additional Copyrights.
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*/
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int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata)
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{
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int ret;
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unsigned int i, reg = 0, rev = 0;
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debug("Initializing OMAP EHCI\n");
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ret = board_usb_init();
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if (ret < 0)
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return ret;
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/* Put the PHY in RESET */
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omap_ehci_phy_reset(1, 10);
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ret = omap_uhh_reset();
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if (ret < 0)
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return ret;
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ret = omap_ehci_tll_reset();
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if (ret)
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return ret;
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writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
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OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
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OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
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/* Put UHH in NoIdle/NoStandby mode */
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writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
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/* setup ULPI bypass and burst configurations */
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clrsetbits_le32(®, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
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(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
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OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
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OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
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rev = readl(&uhh->rev);
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if (rev == OMAP_USBHS_REV1) {
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if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
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clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
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else
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setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
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if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
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clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
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else
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setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
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if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
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clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
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else
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setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
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} else if (rev == OMAP_USBHS_REV2) {
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clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
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OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
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/* Clear port mode fields for PHY mode*/
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if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
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setbits_le32(®, OMAP_P1_MODE_HSIC);
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if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
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setbits_le32(®, OMAP_P2_MODE_HSIC);
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if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
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setbits_le32(®, OMAP_P3_MODE_HSIC);
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}
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debug("OMAP UHH_REVISION 0x%x\n", rev);
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writel(reg, &uhh->hostconfig);
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for (i = 0; i < OMAP_HS_USB_PORTS; i++)
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if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
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omap_usbhs_hsic_init(i);
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omap_ehci_phy_reset(0, 10);
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/*
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* An undocumented "feature" in the OMAP3 EHCI controller,
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* causes suspended ports to be taken out of suspend when
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* the USBCMD.Run/Stop bit is cleared (for example when
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* we do ehci_bus_suspend).
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* This breaks suspend-resume if the root-hub is allowed
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* to suspend. Writing 1 to this undocumented register bit
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* disables this feature and restores normal behavior.
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*/
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writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
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for (i = 0; i < OMAP_HS_USB_PORTS; i++)
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if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
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omap_ehci_soft_phy_reset(i);
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dcache_disable();
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hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
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hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
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debug("OMAP EHCI init done\n");
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return 0;
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}
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