463 lines
12 KiB
C
463 lines
12 KiB
C
/*
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* Memory setup for SMDK5250 board based on EXYNOS5
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*
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* Copyright (C) 2012 Samsung Electronics
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/dmc.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include "setup.h"
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/* APLL : 1GHz */
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/* MCLK_CDREX: MCLK_CDREX_533*/
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/* LPDDR support: LPDDR2 */
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static void reset_phy_ctrl(void);
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static void config_zq(struct exynos5_phy_control *,
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struct exynos5_phy_control *);
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static void update_reset_dll(struct exynos5_dmc *);
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static void config_cdrex(void);
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static void config_mrs(struct exynos5_dmc *);
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static void sec_sdram_phy_init(struct exynos5_dmc *);
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static void config_prech(struct exynos5_dmc *);
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static void config_rdlvl(struct exynos5_dmc *,
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struct exynos5_phy_control *,
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struct exynos5_phy_control *);
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static void config_memory(struct exynos5_dmc *);
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static void config_offsets(unsigned int,
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struct exynos5_phy_control *,
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struct exynos5_phy_control *);
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static void reset_phy_ctrl(void)
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{
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struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
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writel(PHY_RESET_VAL, &clk->lpddr3phy_ctrl);
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sdelay(0x10000);
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}
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static void config_zq(struct exynos5_phy_control *phy0_ctrl,
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struct exynos5_phy_control *phy1_ctrl)
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{
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unsigned long val = 0;
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/*
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* ZQ Calibration:
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* Select Driver Strength,
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* long calibration for manual calibration
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*/
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val = PHY_CON16_RESET_VAL;
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SET_ZQ_MODE_DDS_VAL(val);
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SET_ZQ_MODE_TERM_VAL(val);
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val |= ZQ_CLK_DIV_EN;
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writel(val, &phy0_ctrl->phy_con16);
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writel(val, &phy1_ctrl->phy_con16);
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/* Disable termination */
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val |= ZQ_MODE_NOTERM;
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writel(val, &phy0_ctrl->phy_con16);
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writel(val, &phy1_ctrl->phy_con16);
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/* ZQ_MANUAL_START: Enable */
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val |= ZQ_MANUAL_STR;
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writel(val, &phy0_ctrl->phy_con16);
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writel(val, &phy1_ctrl->phy_con16);
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sdelay(0x10000);
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/* ZQ_MANUAL_START: Disable */
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val &= ~ZQ_MANUAL_STR;
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writel(val, &phy0_ctrl->phy_con16);
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writel(val, &phy1_ctrl->phy_con16);
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}
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static void update_reset_dll(struct exynos5_dmc *dmc)
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{
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unsigned long val;
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/*
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* Update DLL Information:
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* Force DLL Resyncronization
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*/
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val = readl(&dmc->phycontrol0);
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val |= FP_RSYNC;
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writel(val, &dmc->phycontrol0);
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/* Reset Force DLL Resyncronization */
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val = readl(&dmc->phycontrol0);
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val &= ~FP_RSYNC;
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writel(val, &dmc->phycontrol0);
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}
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static void config_mrs(struct exynos5_dmc *dmc)
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{
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unsigned long channel, chip, mask = 0, val;
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for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
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SET_CMD_CHANNEL(mask, channel);
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for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
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/*
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* NOP CMD:
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* Assert and hold CKE to logic high level
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*/
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SET_CMD_CHIP(mask, chip);
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val = DIRECT_CMD_NOP | mask;
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writel(val, &dmc->directcmd);
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sdelay(0x10000);
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/* EMRS, MRS Cmds(Mode Reg Settings) Using Direct Cmd */
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val = DIRECT_CMD_MRS1 | mask;
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writel(val, &dmc->directcmd);
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sdelay(0x10000);
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val = DIRECT_CMD_MRS2 | mask;
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writel(val, &dmc->directcmd);
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sdelay(0x10000);
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/* MCLK_CDREX_533 */
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val = DIRECT_CMD_MRS3 | mask;
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writel(val, &dmc->directcmd);
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sdelay(0x10000);
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val = DIRECT_CMD_MRS4 | mask;
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writel(val, &dmc->directcmd);
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sdelay(0x10000);
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}
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}
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}
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static void config_prech(struct exynos5_dmc *dmc)
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{
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unsigned long channel, chip, mask = 0, val;
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for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
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SET_CMD_CHANNEL(mask, channel);
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for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
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SET_CMD_CHIP(mask, chip);
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/* PALL (all banks precharge) CMD */
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val = DIRECT_CMD_PALL | mask;
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writel(val, &dmc->directcmd);
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sdelay(0x10000);
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}
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}
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}
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static void sec_sdram_phy_init(struct exynos5_dmc *dmc)
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{
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unsigned long val;
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val = readl(&dmc->concontrol);
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val |= DFI_INIT_START;
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writel(val, &dmc->concontrol);
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sdelay(0x10000);
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val = readl(&dmc->concontrol);
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val &= ~DFI_INIT_START;
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writel(val, &dmc->concontrol);
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}
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static void config_offsets(unsigned int state,
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struct exynos5_phy_control *phy0_ctrl,
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struct exynos5_phy_control *phy1_ctrl)
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{
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unsigned long val;
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/* Set Offsets to read DQS */
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val = (state == SET) ? SET_DQS_OFFSET_VAL : RESET_DQS_OFFSET_VAL;
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writel(val, &phy0_ctrl->phy_con4);
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writel(val, &phy1_ctrl->phy_con4);
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/* Set Offsets to read DQ */
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val = (state == SET) ? SET_DQ_OFFSET_VAL : RESET_DQ_OFFSET_VAL;
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writel(val, &phy0_ctrl->phy_con6);
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writel(val, &phy1_ctrl->phy_con6);
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/* Debug Offset */
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val = (state == SET) ? SET_DEBUG_OFFSET_VAL : RESET_DEBUG_OFFSET_VAL;
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writel(val, &phy0_ctrl->phy_con10);
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writel(val, &phy1_ctrl->phy_con10);
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}
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static void config_cdrex(void)
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{
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struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
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writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
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writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
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sdelay(0x30000);
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}
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static void config_ctrl_dll_on(unsigned int state,
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unsigned int ctrl_force_val,
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struct exynos5_phy_control *phy0_ctrl,
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struct exynos5_phy_control *phy1_ctrl)
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{
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unsigned long val;
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val = readl(&phy0_ctrl->phy_con12);
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CONFIG_CTRL_DLL_ON(val, state);
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SET_CTRL_FORCE_VAL(val, ctrl_force_val);
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writel(val, &phy0_ctrl->phy_con12);
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val = readl(&phy1_ctrl->phy_con12);
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CONFIG_CTRL_DLL_ON(val, state);
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SET_CTRL_FORCE_VAL(val, ctrl_force_val);
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writel(val, &phy1_ctrl->phy_con12);
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}
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static void config_ctrl_start(unsigned int state,
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struct exynos5_phy_control *phy0_ctrl,
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struct exynos5_phy_control *phy1_ctrl)
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{
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unsigned long val;
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val = readl(&phy0_ctrl->phy_con12);
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CONFIG_CTRL_START(val, state);
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writel(val, &phy0_ctrl->phy_con12);
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val = readl(&phy1_ctrl->phy_con12);
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CONFIG_CTRL_START(val, state);
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writel(val, &phy1_ctrl->phy_con12);
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}
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#if defined(CONFIG_RD_LVL)
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static void config_rdlvl(struct exynos5_dmc *dmc,
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struct exynos5_phy_control *phy0_ctrl,
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struct exynos5_phy_control *phy1_ctrl)
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{
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unsigned long val;
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/* Disable CTRL_DLL_ON and set ctrl_force */
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config_ctrl_dll_on(RESET, 0x2D, phy0_ctrl, phy1_ctrl);
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/*
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* Set ctrl_gateadj, ctrl_readadj
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* ctrl_gateduradj, rdlvl_pass_adj
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* rdlvl_rddataPadj
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*/
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val = SET_RDLVL_RDDATAPADJ;
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writel(val, &phy0_ctrl->phy_con1);
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writel(val, &phy1_ctrl->phy_con1);
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/* LPDDR2 Address */
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writel(LPDDR2_ADDR, &phy0_ctrl->phy_con22);
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writel(LPDDR2_ADDR, &phy1_ctrl->phy_con22);
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/* Enable Byte Read Leveling set ctrl_ddr_mode */
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val = readl(&phy0_ctrl->phy_con0);
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val |= BYTE_RDLVL_EN;
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writel(val, &phy0_ctrl->phy_con0);
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val = readl(&phy1_ctrl->phy_con0);
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val |= BYTE_RDLVL_EN;
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writel(val, &phy1_ctrl->phy_con0);
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/* rdlvl_en: Use levelling offset instead ctrl_shiftc */
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val = PHY_CON2_RESET_VAL | RDLVL_EN;
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writel(val, &phy0_ctrl->phy_con2);
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writel(val, &phy1_ctrl->phy_con2);
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sdelay(0x10000);
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/* Enable Data Eye Training */
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val = readl(&dmc->rdlvl_config);
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val |= CTRL_RDLVL_DATA_EN;
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writel(val, &dmc->rdlvl_config);
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sdelay(0x10000);
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/* Disable Data Eye Training */
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val = readl(&dmc->rdlvl_config);
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val &= ~CTRL_RDLVL_DATA_EN;
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writel(val, &dmc->rdlvl_config);
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/* RdDeSkew_clear: Clear */
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val = readl(&phy0_ctrl->phy_con2);
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val |= RDDSKEW_CLEAR;
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writel(val, &phy0_ctrl->phy_con2);
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val = readl(&phy1_ctrl->phy_con2);
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val |= RDDSKEW_CLEAR;
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writel(val, &phy1_ctrl->phy_con2);
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/* Enable CTRL_DLL_ON */
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config_ctrl_dll_on(SET, 0x0, phy0_ctrl, phy1_ctrl);
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update_reset_dll(dmc);
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sdelay(0x10000);
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/* ctrl_atgte: ctrl_gate_p*, ctrl_read_p* generated by PHY */
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val = readl(&phy0_ctrl->phy_con0);
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val &= ~CTRL_ATGATE;
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writel(val, &phy0_ctrl->phy_con0);
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val = readl(&phy1_ctrl->phy_con0);
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val &= ~CTRL_ATGATE;
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writel(val, &phy1_ctrl->phy_con0);
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}
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#endif
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static void config_memory(struct exynos5_dmc *dmc)
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{
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/*
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* Memory Configuration Chip 0
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* Address Mapping: Interleaved
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* Number of Column address Bits: 10 bits
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* Number of Rows Address Bits: 14
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* Number of Banks: 8
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*/
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writel(DMC_MEMCONFIG0_VAL, &dmc->memconfig0);
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/*
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* Memory Configuration Chip 1
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* Address Mapping: Interleaved
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* Number of Column address Bits: 10 bits
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* Number of Rows Address Bits: 14
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* Number of Banks: 8
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*/
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writel(DMC_MEMCONFIG1_VAL, &dmc->memconfig1);
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/*
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* Chip0: AXI
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* AXI Base Address: 0x40000000
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* AXI Base Address Mask: 0x780
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*/
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writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
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/*
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* Chip1: AXI
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* AXI Base Address: 0x80000000
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* AXI Base Address Mask: 0x780
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*/
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writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
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}
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void mem_ctrl_init()
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{
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struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
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struct exynos5_dmc *dmc;
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unsigned long val;
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phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
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phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
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dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
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/* Reset PHY Controllor: PHY_RESET[0] */
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reset_phy_ctrl();
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/*set Read Latancy and Burst Length for PHY0 and PHY1 */
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writel(PHY_CON42_VAL, &phy0_ctrl->phy_con42);
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writel(PHY_CON42_VAL, &phy1_ctrl->phy_con42);
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/* ZQ Cofiguration */
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config_zq(phy0_ctrl, phy1_ctrl);
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/* Operation Mode : LPDDR2 */
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val = PHY_CON0_RESET_VAL;
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SET_CTRL_DDR_MODE(val, DDR_MODE_LPDDR2);
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writel(val, &phy0_ctrl->phy_con0);
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writel(val, &phy1_ctrl->phy_con0);
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/* DQS, DQ: Signal, for LPDDR2: Always Set */
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val = CTRL_PULLD_DQ | CTRL_PULLD_DQS;
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writel(val, &phy0_ctrl->phy_con14);
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writel(val, &phy1_ctrl->phy_con14);
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/* Init SEC SDRAM PHY */
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sec_sdram_phy_init(dmc);
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sdelay(0x10000);
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update_reset_dll(dmc);
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/*
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* Dynamic Clock: Always Running
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* Memory Burst length: 4
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* Number of chips: 2
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* Memory Bus width: 32 bit
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* Memory Type: LPDDR2-S4
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* Additional Latancy for PLL: 1 Cycle
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*/
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writel(DMC_MEMCONTROL_VAL, &dmc->memcontrol);
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config_memory(dmc);
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/* Precharge Configuration */
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writel(DMC_PRECHCONFIG_VAL, &dmc->prechconfig);
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/* Power Down mode Configuration */
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writel(DMC_PWRDNCONFIG_VAL, &dmc->pwrdnconfig);
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/* Periodic Refrese Interval */
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writel(DMC_TIMINGREF_VAL, &dmc->timingref);
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/*
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* TimingRow, TimingData, TimingPower Setting:
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* Values as per Memory AC Parameters
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*/
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writel(DMC_TIMINGROW_VAL, &dmc->timingrow);
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writel(DMC_TIMINGDATA_VAL, &dmc->timingdata);
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writel(DMC_TIMINGPOWER_VAL, &dmc->timingpower);
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/* Memory Channel Inteleaving Size: 128 Bytes */
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writel(CONFIG_IV_SIZE, &dmc->ivcontrol);
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/* Set DQS, DQ and DEBUG offsets */
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config_offsets(SET, phy0_ctrl, phy1_ctrl);
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/* Disable CTRL_DLL_ON and set ctrl_force */
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config_ctrl_dll_on(RESET, 0x7F, phy0_ctrl, phy1_ctrl);
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sdelay(0x10000);
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update_reset_dll(dmc);
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/* Config MRS(Mode Register Settingg) */
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config_mrs(dmc);
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config_cdrex();
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/* Reset DQS DQ and DEBUG offsets */
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config_offsets(RESET, phy0_ctrl, phy1_ctrl);
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/* Enable CTRL_DLL_ON */
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config_ctrl_dll_on(SET, 0x0, phy0_ctrl, phy1_ctrl);
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/* Stop DLL Locking */
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config_ctrl_start(RESET, phy0_ctrl, phy1_ctrl);
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sdelay(0x10000);
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/* Start DLL Locking */
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config_ctrl_start(SET, phy0_ctrl, phy1_ctrl);
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sdelay(0x10000);
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update_reset_dll(dmc);
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#if defined(CONFIG_RD_LVL)
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config_rdlvl(dmc, phy0_ctrl, phy1_ctrl);
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#endif
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config_prech(dmc);
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/*
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* Dynamic Clock: Stops During Idle Period
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* Dynamic Power Down: Enable
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* Dynamic Self refresh: Enable
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*/
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val = readl(&dmc->memcontrol);
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val |= CLK_STOP_EN | DPWRDN_EN | DSREF_EN;
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writel(val, &dmc->memcontrol);
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/* Start Auto refresh */
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val = readl(&dmc->concontrol);
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val |= AREF_EN;
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writel(val, &dmc->concontrol);
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}
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