27 lines
525 B
C
27 lines
525 B
C
/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_SYS_PROTO_H
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#define _ASM_ARCH_SYS_PROTO_H
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#ifndef CONFIG_CLK_ZYNQMP
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/* Setup clk for network */
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static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
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{
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}
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#endif
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int zynq_slcr_get_mio_pin_status(const char *periph);
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unsigned int zynqmp_get_silicon_version(void);
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void psu_init(void);
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void handoff_setup(void);
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#endif /* _ASM_ARCH_SYS_PROTO_H */
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