137 lines
4.0 KiB
C
137 lines
4.0 KiB
C
/*
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* Copyright (C) 2012 sysmocom s.f.m.c. GmbH
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* Copyright (C) 2009 Lyrtech RD Inc. <www.lyrtech.com>
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*
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* Based on dvevm/dvevm.c, original copyright follows:
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Parts are shamelessly stolen from various TI sources, original copyright
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* follows:
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* -----------------------------------------------------------------
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*
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* Copyright (C) 2004 Texas Instruments.
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*
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* ----------------------------------------------------------------------------
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/davinci_misc.h>
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#define DAVINCI_PLLM (0x01C40910) /* PLL 1 Multiplier */
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#define DAVINCI_AWCCR (0x01E00004) /* EMIF-A async wait cycle config register. */
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#define DAVINCI_AWCCR_VAL (0x000000FF) /* EMIF-A async wait cycle config register value. */
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#define DAVINCI_A1CR (0x01E00010) /* EMIF-A CS2 config register. */
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#define DAVINCI_A1CR_VAL (0x44502280) /* EMIF-A CS2 value for NAND. */
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#define DAVINCI_A1CR_VAL8 (0x44502280) /* EMIF-A CS2 value for NAND. */
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#define DAVINCI_A2CR (0x01E00014) /* EMIF-A CS3 config register. */
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#define DAVINCI_A2CR_VAL (0x00430491) /* EMIF-A CS3 value for FPGA. */
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#define DAVINCI_A2CR_VAL8 (0x00630591) /* EMIF-A CS3 value for FPGA. */
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DECLARE_GLOBAL_DATA_PTR;
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/* Read ethernet MAC address from EEPROM.
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* Returns 1 if found, 0 otherwise.
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*/
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static int sysmobts_v2_read_mac_address(uint8_t *buf)
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{
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
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/* Read MAC address. */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x0000, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
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(uint8_t *) &buf[0], 6))
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goto i2cerr;
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/* Check that MAC address is valid. */
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if (!is_valid_ether_addr(buf))
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goto err;
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return 1; /* Found */
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i2cerr:
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printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
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err:
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#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
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return 0;
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}
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int board_init(void)
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{
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/* arch number of the board */
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gd->bd->bi_arch_number = MACH_TYPE_SYSMOBTS_V2;
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/* address of boot parameters */
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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/* Configure pins */
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REG(PINMUX0) = 0x8000000f;
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REG(PINMUX1) = 0x00050187;
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/* Configure AEMIF AWCCR */
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REG(DAVINCI_AWCCR) = DAVINCI_AWCCR_VAL;
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/* DM644X @ 594/297 MHz */
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if ( (REG(DAVINCI_PLLM) & 0x0FF) < 22 ) {
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/* Configure AEMIF CS2 (nand) */
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REG(DAVINCI_A1CR) = DAVINCI_A1CR_VAL;
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/* Configure AEMIF CS3 (fpga) */
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REG(DAVINCI_A2CR) = DAVINCI_A2CR_VAL;
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/* DM644X @ 810/405 MHz */
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} else {
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/* Configure AEMIF CS2 (nand) */
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REG(DAVINCI_A1CR) = DAVINCI_A1CR_VAL8;
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/* Configure AEMIF CS3 (fpga) */
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REG(DAVINCI_A2CR) = DAVINCI_A2CR_VAL8;
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}
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davinci_errata_workarounds();
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/* Power on required peripherals */
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lpsc_on(DAVINCI_LPSC_GPIO);
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/* Powerup the DSP */
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dsp_on();
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davinci_enable_uart0();
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davinci_enable_emac();
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davinci_enable_i2c();
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lpsc_on(DAVINCI_LPSC_TIMER1);
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timer_init();
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return(0);
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}
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int misc_init_r(void)
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{
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uint8_t eeprom_enetaddr[6];
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/* Read Ethernet MAC address from EEPROM if available. */
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if (sysmobts_v2_read_mac_address(eeprom_enetaddr))
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davinci_sync_env_enetaddr(eeprom_enetaddr);
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setenv("fwup", "dhcp;setenv filesize 0;tftp 85000000 ${tftp_serverip}:rootfs.ubi;mtdpart default;nand erase.part RootFs;nand write 85000000 100000 ${filesize}");
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return(0);
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}
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