Minor cleanups to confirm to the u-boot coding style. Some german expressions -> english. HCU5 enforces a unique IP adress for a given slot in the rack. Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
555 lines
18 KiB
C
555 lines
18 KiB
C
/*
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*(C) Copyright 2005-2007 Netstal Maschinen AG
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* Niklaus Giger (Niklaus.Giger@netstal.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <ppc440.h>
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#include <asm/mmu.h>
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#include <net.h>
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DECLARE_GLOBAL_DATA_PTR;
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void hcu_led_set(u32 value);
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extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
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#undef BOOTSTRAP_OPTION_A_ACTIVE
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#define SDR0_CP440 0x0180
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#define SYSTEM_RESET 0x30000000
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#define CHIP_RESET 0x20000000
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#define SDR0_ECID0 0x0080
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#define SDR0_ECID1 0x0081
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#define SDR0_ECID2 0x0082
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#define SDR0_ECID3 0x0083
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#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000)
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#define SYS_SLOT_ADDRESS (CFG_CPLD + 0x00400000)
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#define DEFAULT_ETH_ADDR "ethaddr"
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/* ethaddr for first or etha1ddr for second ethernet */
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enum {
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/* HW_GENERATION_HCU1 is no longer supported */
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HW_GENERATION_HCU2 = 0x10,
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HW_GENERATION_HCU3 = 0x10,
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HW_GENERATION_HCU4 = 0x20,
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HW_GENERATION_HCU5 = 0x30,
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HW_GENERATION_MCU = 0x08,
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HW_GENERATION_MCU20 = 0x0a,
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HW_GENERATION_MCU25 = 0x09,
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};
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/*
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* This function is run very early, out of flash, and before devices are
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* initialized. It is called by lib_ppc/board.c:board_init_f by virtue
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* of being in the init_sequence array.
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*
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* The SDRAM has been initialized already -- start.S:start called
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* init.S:init_sdram early on -- but it is not yet being used for
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* anything, not even stack. So be careful.
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*/
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int board_early_init_f(void)
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{
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u32 reg;
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#ifdef BOOTSTRAP_OPTION_A_ACTIVE
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/* Booting with Bootstrap Option A
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* First boot, with CPR0_ICFG_RLI_MASK == 0
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* no we setup varios boot strapping register,
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* then we do reset the PPC440 using a chip reset
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* Unfortunately, we cannot use this option, as Nto1 is not set
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* with Bootstrap Option A and cannot be changed later on by SW
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* There are no other possible boostrap options with a 8 bit ROM
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* See Errata (Version 1.04) CHIP_9
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*/
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u32 cpr0icfg;
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u32 dbcr;
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mfcpr(CPR0_ICFG, cpr0icfg);
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if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
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mtcpr(CPR0_MALD, 0x02000000);
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mtcpr(CPR0_OPBD, 0x02000000);
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mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */
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mtcpr(CPR0_PLLC, 0x40000238);
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mtcpr(CPR0_PLLD, 0x01010414);
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mtcpr(CPR0_PRIMAD, 0x01000000);
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mtcpr(CPR0_PRIMBD, 0x01000000);
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mtcpr(CPR0_SPCID, 0x03000000);
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mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
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mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
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mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
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/*
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* Initiate system reset in debug control register DBCR
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*/
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dbcr = mfspr(dbcr0);
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mtspr(dbcr0, dbcr | CHIP_RESET);
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}
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mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
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#endif
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mtdcr(ebccfga, xbcfg);
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mtdcr(ebccfgd, 0xb8400000);
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/*--------------------------------------------------------------------
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* Setup the GPIO pins
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*-------------------------------------------------------------------*/
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/* test-only: take GPIO init from pcs440ep ???? in config file */
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out32(GPIO0_OR, 0x00000000);
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out32(GPIO0_TCR, 0x7C2FF1CF);
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out32(GPIO0_OSRL, 0x40055000);
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out32(GPIO0_OSRH, 0x00000000);
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out32(GPIO0_TSRL, 0x40055000);
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out32(GPIO0_TSRH, 0x00000400);
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out32(GPIO0_ISR1L, 0x40000000);
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out32(GPIO0_ISR1H, 0x00000000);
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out32(GPIO0_ISR2L, 0x00000000);
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out32(GPIO0_ISR2H, 0x00000000);
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out32(GPIO0_ISR3L, 0x00000000);
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out32(GPIO0_ISR3H, 0x00000000);
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out32(GPIO1_OR, 0x00000000);
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out32(GPIO1_TCR, 0xC6007FFF);
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out32(GPIO1_OSRL, 0x00140000);
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out32(GPIO1_OSRH, 0x00000000);
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out32(GPIO1_TSRL, 0x00000000);
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out32(GPIO1_TSRH, 0x00000000);
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out32(GPIO1_ISR1L, 0x05415555);
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out32(GPIO1_ISR1H, 0x40000000);
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out32(GPIO1_ISR2L, 0x00000000);
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out32(GPIO1_ISR2H, 0x00000000);
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out32(GPIO1_ISR3L, 0x00000000);
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out32(GPIO1_ISR3H, 0x00000000);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
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mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
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mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
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mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic2sr, 0xffffffff); /* clear all */
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mtdcr(uic2er, 0x00000000); /* disable all */
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mtdcr(uic2cr, 0x00000000); /* all non-critical */
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mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
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mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic2sr, 0xffffffff); /* clear all */
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mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */
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mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
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/* PCI arbiter enabled */
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mfsdr(sdr_pci0, reg);
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mtsdr(sdr_pci0, 0x80000000 | reg);
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pci_pre_init(0);
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/* setup BOOT FLASH */
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mtsdr(SDR0_CUST0, 0xC0082350);
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return 0;
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}
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#ifdef CONFIG_BOARD_PRE_INIT
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int board_pre_init(void)
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{
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return board_early_init_f();
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}
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#endif
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int checkboard(void)
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{
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unsigned int j;
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u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
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u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
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u16 generation = *boardVersReg & 0xf0;
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u16 index = *boardVersReg & 0x0f;
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u32 ecid0, ecid1, ecid2, ecid3;
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printf("Netstal Maschinen AG: ");
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if (generation == HW_GENERATION_HCU3)
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printf("HCU3: index %d", index);
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else if (generation == HW_GENERATION_HCU4)
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printf("HCU4: index %d", index);
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else if (generation == HW_GENERATION_HCU5)
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printf("HCU5: index %d", index);
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printf(" HW 0x%02x\n", *hwVersReg & 0xff);
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mfsdr(SDR0_ECID0, ecid0);
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mfsdr(SDR0_ECID1, ecid1);
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mfsdr(SDR0_ECID2, ecid2);
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mfsdr(SDR0_ECID3, ecid3);
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printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
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for (j = 0;j < 6; j++) {
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hcu_led_set(1 << j);
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udelay(200 * 1000);
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}
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return 0;
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}
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u32 hcu_led_get(void)
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{
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return in16(SYS_IO_ADDRESS) & 0x3f;
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}
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/*---------------------------------------------------------------------------+
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* hcu_led_set value to be placed into the LEDs (max 6 bit)
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*---------------------------------------------------------------------------*/
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void hcu_led_set(u32 value)
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{
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out16(SYS_IO_ADDRESS, value);
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}
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/*---------------------------------------------------------------------------+
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* get_serial_number
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*---------------------------------------------------------------------------*/
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static u32 get_serial_number(void)
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{
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u32 *serial = (u32 *)CFG_FLASH_BASE;
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if (*serial == 0xffffffff)
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return 0;
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return *serial;
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}
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/*---------------------------------------------------------------------------+
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* hcu_get_slot
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*---------------------------------------------------------------------------*/
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u32 hcu_get_slot(void)
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{
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u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
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return (*slot) & 0x7f;
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}
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/*---------------------------------------------------------------------------+
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* misc_init_r.
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*---------------------------------------------------------------------------*/
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int misc_init_r(void)
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{
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char *s = getenv(DEFAULT_ETH_ADDR);
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char *e;
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int i;
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u32 serial = get_serial_number();
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unsigned long usb2d0cr = 0;
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unsigned long usb2phy0cr, usb2h0cr = 0;
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unsigned long sdr0_pfc1;
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for (i = 0; i < 6; ++i) {
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gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
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if (s)
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s = (*e) ? e + 1 : e;
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}
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if (gd->bd->bi_enetaddr[3] == 0 &&
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gd->bd->bi_enetaddr[4] == 0 &&
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gd->bd->bi_enetaddr[5] == 0) {
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char ethaddr[22];
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/* Must be in sync with CONFIG_ETHADDR */
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gd->bd->bi_enetaddr[0] = 0x00;
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gd->bd->bi_enetaddr[1] = 0x60;
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gd->bd->bi_enetaddr[2] = 0x13;
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gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
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gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
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gd->bd->bi_enetaddr[5] = hcu_get_slot();
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sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
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gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
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gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
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gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
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printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
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ethaddr, serial);
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setenv(DEFAULT_ETH_ADDR, ethaddr);
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}
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/* IP-Adress update */
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{
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IPaddr_t ipaddr;
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char *ipstring;
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ipstring = getenv("ipaddr");
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if (ipstring == 0)
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ipaddr = string_to_ip("172.25.1.99");
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else
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ipaddr = string_to_ip(ipstring);
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if ((ipaddr & 0xff) != (32 + hcu_get_slot())) {
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char tmp[22];
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ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot();
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ip_to_string (ipaddr, tmp);
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printf("%s: enforce %s\n", __FUNCTION__, tmp);
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setenv("ipaddr", tmp);
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}
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}
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#ifdef CFG_ENV_IS_IN_FLASH
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CFG_MONITOR_LEN,
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0xffffffff,
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&flash_info[0]);
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/* Env protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR_REDUND,
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CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
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&flash_info[0]);
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#endif
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/*
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* USB stuff...
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*/
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/* SDR Setting */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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mfsdr(SDR0_USB2D0CR, usb2d0cr);
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mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mfsdr(SDR0_USB2H0CR, usb2h0cr);
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
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/* An 8-bit/60MHz interface is the only possible alternative
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when connecting the Device to the PHY */
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usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
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usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
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/* To enable the USB 2.0 Device function through the UTMI interface */
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usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
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usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
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sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
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sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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mtsdr(SDR0_USB2D0CR, usb2d0cr);
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mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mtsdr(SDR0_USB2H0CR, usb2h0cr);
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/*clear resets*/
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udelay(1000);
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mtsdr(SDR0_SRST1, 0x00000000);
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udelay(1000);
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mtsdr(SDR0_SRST0, 0x00000000);
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printf("USB: Host(int phy) Device(ext phy)\n");
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return 0;
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}
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#if defined(CONFIG_PCI)
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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int pci_pre_init(struct pci_controller *hose)
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{
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unsigned long addr;
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/*-------------------------------------------------------------------+
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* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
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* Workaround: Disable write pipelining to DDR SDRAM by setting
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* PLB0_ACR[WRP] = 0.
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*-------------------------------------------------------------------*/
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/*-------------------------------------------------------------------+
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| Set priority for all PLB3 devices to 0.
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| Set PLB3 arbiter to fair mode.
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+-------------------------------------------------------------------*/
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mfsdr(sdr_amp1, addr);
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mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(plb3_acr);
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/* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
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mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
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/*-------------------------------------------------------------------+
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| Set priority for all PLB4 devices to 0.
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+-------------------------------------------------------------------*/
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mfsdr(sdr_amp0, addr);
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mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
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/* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
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mtdcr(plb4_acr, addr); /* Sequoia */
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/*-------------------------------------------------------------------+
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| Set Nebula PLB4 arbiter to fair mode.
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+-------------------------------------------------------------------*/
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/* Segment0 */
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addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
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addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
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addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
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/* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */
|
|
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */
|
|
|
|
/* mtdcr(plb0_acr, addr); */ /* Sequoia */
|
|
mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
|
|
|
|
/* Segment1 */
|
|
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
|
|
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
|
|
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
|
|
addr = (addr & ~plb1_acr_wrp_mask) ;
|
|
/* mtdcr(plb1_acr, addr); */ /* Sequoia */
|
|
mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
|
|
|
|
return 1;
|
|
}
|
|
|
|
/*************************************************************************
|
|
* pci_target_init
|
|
*
|
|
* The bootstrap configuration provides default settings for the pci
|
|
* inbound map (PIM). But the bootstrap config choices are limited and
|
|
* may not be sufficient for a given board.
|
|
*
|
|
************************************************************************/
|
|
void pci_target_init(struct pci_controller *hose)
|
|
{
|
|
/*-------------------------------------------------------------+
|
|
* Set up Direct MMIO registers
|
|
*-------------------------------------------------------------*/
|
|
/*-------------------------------------------------------------+
|
|
| PowerPC440EPX PCI Master configuration.
|
|
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
|
|
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
|
|
| 0xA0000000-0xDFFFFFFF
|
|
| Use byte reversed out routines to handle endianess.
|
|
| Make this region non-prefetchable.
|
|
+-------------------------------------------------------------*/
|
|
/* PMM0 Mask/Attribute - disabled b4 setting */
|
|
out32r(PCIX0_PMM0MA, 0x00000000);
|
|
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
|
|
/* PMM0 PCI Low Address */
|
|
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);
|
|
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
|
/* 512M + No prefetching, and enable region */
|
|
out32r(PCIX0_PMM0MA, 0xE0000001);
|
|
|
|
/* PMM0 Mask/Attribute - disabled b4 setting */
|
|
out32r(PCIX0_PMM1MA, 0x00000000);
|
|
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
|
|
/* PMM0 PCI Low Address */
|
|
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);
|
|
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
|
/* 512M + No prefetching, and enable region */
|
|
out32r(PCIX0_PMM1MA, 0xE0000001);
|
|
|
|
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
|
|
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
|
|
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
|
|
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
|
|
|
|
/*------------------------------------------------------------------+
|
|
* Set up Configuration registers
|
|
*------------------------------------------------------------------*/
|
|
|
|
/* Program the board's subsystem id/vendor id */
|
|
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
|
|
CFG_PCI_SUBSYS_VENDORID);
|
|
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
|
|
|
|
/* Configure command register as bus master */
|
|
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
|
|
|
|
/* 240nS PCI clock */
|
|
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
|
|
|
|
/* No error reporting */
|
|
pci_write_config_word(0, PCI_ERREN, 0);
|
|
|
|
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
|
|
}
|
|
|
|
/*************************************************************************
|
|
* pci_master_init
|
|
*
|
|
************************************************************************/
|
|
void pci_master_init(struct pci_controller *hose)
|
|
{
|
|
unsigned short temp_short;
|
|
|
|
/*---------------------------------------------------------------+
|
|
| Write the PowerPC440 EP PCI Configuration regs.
|
|
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
|
|
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
|
|
+--------------------------------------------------------------*/
|
|
pci_read_config_word(0, PCI_COMMAND, &temp_short);
|
|
pci_write_config_word(0, PCI_COMMAND,
|
|
temp_short | PCI_COMMAND_MASTER |
|
|
PCI_COMMAND_MEMORY);
|
|
}
|
|
|
|
/*************************************************************************
|
|
* is_pci_host
|
|
*
|
|
* This routine is called to determine if a pci scan should be
|
|
* performed. With various hardware environments (especially cPCI and
|
|
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
|
* bit in the strap register, or generic host/adapter assumptions.
|
|
*
|
|
* Rather than hard-code a bad assumption in the general 440 code, the
|
|
* 440 pci code requires the board to decide at runtime.
|
|
*
|
|
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
|
*
|
|
*
|
|
************************************************************************/
|
|
int is_pci_host(struct pci_controller *hose)
|
|
{
|
|
return 1;
|
|
}
|
|
#endif /* defined(CONFIG_PCI) */
|