The DMA transfers happen only if the transfered data are larger than 512 bytes. Otherwise PIO is used. This is a small speed optimization. The DMA transfer doesn't work if unaligned transfer is requested due to the limitation of the DMA controller. This has to be fixed by introducing generic bounce buffer. Therefore the DMA feature is now disabled by default. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
347 lines
8.7 KiB
C
347 lines
8.7 KiB
C
/*
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* Freescale i.MX28 SPI driver
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* NOTE: This driver only supports the SPI-controller chipselects,
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* GPIO driven chipselects are not supported.
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*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/dma.h>
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#define MXS_SPI_MAX_TIMEOUT 1000000
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#define MXS_SPI_PORT_OFFSET 0x2000
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#define MXS_SSP_CHIPSELECT_MASK 0x00300000
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#define MXS_SSP_CHIPSELECT_SHIFT 20
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#define MXSSSP_SMALL_TRANSFER 512
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/*
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* CONFIG_MXS_SPI_DMA_ENABLE: Experimental mixed PIO/DMA support for MXS SPI
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* host. Use with utmost caution!
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*
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* Enabling this is not yet recommended since this
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* still doesn't support transfers to/from unaligned
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* addresses. Therefore this driver will not work
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* for example with saving environment. This is
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* caused by DMA alignment constraints on MXS.
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*/
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struct mxs_spi_slave {
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struct spi_slave slave;
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uint32_t max_khz;
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uint32_t mode;
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struct mx28_ssp_regs *regs;
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struct mxs_dma_desc *desc;
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};
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static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
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{
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return container_of(slave, struct mxs_spi_slave, slave);
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}
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void spi_init(void)
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{
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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/* MXS SPI: 4 ports and 3 chip selects maximum */
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if (bus > 3 || cs > 2)
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return 0;
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else
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return 1;
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct mxs_spi_slave *mxs_slave;
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uint32_t addr;
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struct mx28_ssp_regs *ssp_regs;
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int reg;
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struct mxs_dma_desc *desc;
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if (!spi_cs_is_valid(bus, cs)) {
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printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
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return NULL;
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}
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mxs_slave = malloc(sizeof(struct mxs_spi_slave));
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if (!mxs_slave)
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return NULL;
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desc = mxs_dma_desc_alloc();
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if (!desc)
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goto err_desc;
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if (mxs_dma_init_channel(bus))
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goto err_init;
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addr = MXS_SSP0_BASE + (bus * MXS_SPI_PORT_OFFSET);
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mxs_slave->slave.bus = bus;
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mxs_slave->slave.cs = cs;
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mxs_slave->max_khz = max_hz / 1000;
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mxs_slave->mode = mode;
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mxs_slave->regs = (struct mx28_ssp_regs *)addr;
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mxs_slave->desc = desc;
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ssp_regs = mxs_slave->regs;
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reg = readl(&ssp_regs->hw_ssp_ctrl0);
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reg &= ~(MXS_SSP_CHIPSELECT_MASK);
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reg |= cs << MXS_SSP_CHIPSELECT_SHIFT;
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writel(reg, &ssp_regs->hw_ssp_ctrl0);
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return &mxs_slave->slave;
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err_init:
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mxs_dma_desc_free(desc);
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err_desc:
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free(mxs_slave);
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return NULL;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
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mxs_dma_desc_free(mxs_slave->desc);
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free(mxs_slave);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
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struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
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uint32_t reg = 0;
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mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
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writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
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reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
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reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
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reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
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writel(reg, &ssp_regs->hw_ssp_ctrl1);
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writel(0, &ssp_regs->hw_ssp_cmd0);
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mx28_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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}
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static void mxs_spi_start_xfer(struct mx28_ssp_regs *ssp_regs)
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{
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writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
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writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
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}
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static void mxs_spi_end_xfer(struct mx28_ssp_regs *ssp_regs)
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{
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writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
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writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
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}
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static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
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char *data, int length, int write, unsigned long flags)
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{
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struct mx28_ssp_regs *ssp_regs = slave->regs;
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if (flags & SPI_XFER_BEGIN)
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mxs_spi_start_xfer(ssp_regs);
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while (length--) {
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/* We transfer 1 byte */
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writel(1, &ssp_regs->hw_ssp_xfer_size);
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if ((flags & SPI_XFER_END) && !length)
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mxs_spi_end_xfer(ssp_regs);
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if (write)
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writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
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else
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writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
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writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
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if (mx28_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
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SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
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printf("MXS SPI: Timeout waiting for start\n");
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return -ETIMEDOUT;
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}
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if (write)
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writel(*data++, &ssp_regs->hw_ssp_data);
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writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
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if (!write) {
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if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
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SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
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printf("MXS SPI: Timeout waiting for data\n");
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return -ETIMEDOUT;
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}
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*data = readl(&ssp_regs->hw_ssp_data);
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data++;
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}
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if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
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SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
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printf("MXS SPI: Timeout waiting for finish\n");
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
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char *data, int length, int write, unsigned long flags)
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{
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struct mxs_dma_desc *desc = slave->desc;
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struct mx28_ssp_regs *ssp_regs = slave->regs;
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uint32_t ctrl0 = SSP_CTRL0_DATA_XFER;
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uint32_t cache_data_count;
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int dmach;
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memset(desc, 0, sizeof(struct mxs_dma_desc));
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desc->address = (dma_addr_t)desc;
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if (flags & SPI_XFER_BEGIN)
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ctrl0 |= SSP_CTRL0_LOCK_CS;
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if (flags & SPI_XFER_END)
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ctrl0 |= SSP_CTRL0_IGNORE_CRC;
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if (!write)
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ctrl0 |= SSP_CTRL0_READ;
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writel(length, &ssp_regs->hw_ssp_xfer_size);
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if (length % ARCH_DMA_MINALIGN)
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cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
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else
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cache_data_count = length;
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if (!write) {
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slave->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
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slave->desc->cmd.address = (dma_addr_t)data;
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} else {
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slave->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
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slave->desc->cmd.address = (dma_addr_t)data;
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/* Flush data to DRAM so DMA can pick them up */
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flush_dcache_range((uint32_t)data,
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(uint32_t)(data + cache_data_count));
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}
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slave->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
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(length << MXS_DMA_DESC_BYTES_OFFSET) |
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(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
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MXS_DMA_DESC_WAIT4END;
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slave->desc->cmd.pio_words[0] = ctrl0;
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dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
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mxs_dma_desc_append(dmach, slave->desc);
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if (mxs_dma_go(dmach))
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return -EINVAL;
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/* The data arrived into DRAM, invalidate cache over them */
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if (!write) {
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invalidate_dcache_range((uint32_t)data,
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(uint32_t)(data + cache_data_count));
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}
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return 0;
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
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struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
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int len = bitlen / 8;
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char dummy;
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int write = 0;
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char *data = NULL;
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#ifdef CONFIG_MXS_SPI_DMA_ENABLE
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int dma = 1;
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#else
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int dma = 0;
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#endif
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if (bitlen == 0) {
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if (flags & SPI_XFER_END) {
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din = (void *)&dummy;
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len = 1;
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} else
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return 0;
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}
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/* Half-duplex only */
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if (din && dout)
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return -EINVAL;
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/* No data */
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if (!din && !dout)
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return 0;
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if (dout) {
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data = (char *)dout;
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write = 1;
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} else if (din) {
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data = (char *)din;
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write = 0;
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}
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/*
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* Check for alignment, if the buffer is aligned, do DMA transfer,
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* PIO otherwise. This is a temporary workaround until proper bounce
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* buffer is in place.
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*/
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if (dma) {
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if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
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dma = 0;
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if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
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dma = 0;
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}
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if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
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writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
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return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
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} else {
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writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
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return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
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}
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}
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