Add i2c_clk_enable in the cpu specific code, since previous platform it, while new platform don't need. In the pantheon and armada100 platform, this function is defined as NULL one. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Lei Wen <leiwen@marvell.com>
331 lines
7.8 KiB
C
331 lines
7.8 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* CPU specific code
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*/
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#include <asm/io.h>
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#include <asm/system.h>
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#include <command.h>
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#include <common.h>
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#include <asm/arch/pxa-regs.h>
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static void cache_flush(void);
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int cleanup_before_linux (void)
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{
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/*
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* this function is called just before we call linux
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* it prepares the processor for linux
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*
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* just disable everything that can disturb booting linux
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*/
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disable_interrupts ();
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/* turn off I-cache */
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icache_disable();
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dcache_disable();
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/* flush I-cache */
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cache_flush();
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return (0);
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}
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/* flush I/D-cache */
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static void cache_flush (void)
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{
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unsigned long i = 0;
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asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
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}
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#ifndef CONFIG_CPU_MONAHANS
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void set_GPIO_mode(int gpio_mode)
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{
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int gpio = gpio_mode & GPIO_MD_MASK_NR;
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int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
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int val;
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/* This below changes direction setting of GPIO "gpio" */
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val = readl(GPDR(gpio));
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if (gpio_mode & GPIO_MD_MASK_DIR)
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val |= GPIO_bit(gpio);
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else
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val &= ~GPIO_bit(gpio);
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writel(val, GPDR(gpio));
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/* This below updates only AF of GPIO "gpio" */
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val = readl(GAFR(gpio));
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val &= ~(0x3 << (((gpio) & 0xf) * 2));
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val |= fn << (((gpio) & 0xf) * 2);
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writel(val, GAFR(gpio));
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}
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#endif /* CONFIG_CPU_MONAHANS */
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void pxa_wait_ticks(int ticks)
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{
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writel(0, OSCR);
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while (readl(OSCR) < ticks)
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asm volatile("":::"memory");
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}
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inline void writelrb(uint32_t val, uint32_t addr)
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{
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writel(val, addr);
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asm volatile("":::"memory");
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readl(addr);
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asm volatile("":::"memory");
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}
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void pxa_dram_init(void)
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{
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uint32_t tmp;
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int i;
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/*
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* 1) Initialize Asynchronous static memory controller
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*/
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writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
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writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
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writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
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/*
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* 2) Initialize Card Interface
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*/
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/* MECR: Memory Expansion Card Register */
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writelrb(CONFIG_SYS_MECR_VAL, MECR);
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/* MCMEM0: Card Interface slot 0 timing */
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writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
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/* MCMEM1: Card Interface slot 1 timing */
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writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
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/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
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writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
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/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
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writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
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/* MCIO0: Card Interface I/O Space Timing, slot 0 */
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writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
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/* MCIO1: Card Interface I/O Space Timing, slot 1 */
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writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
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/*
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* 3) Configure Fly-By DMA register
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*/
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writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
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/*
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* 4) Initialize Timing for Sync Memory (SDCLK0)
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*/
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/*
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* Before accessing MDREFR we need a valid DRI field, so we set
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* this to power on defaults + DRI field.
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*/
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/* Read current MDREFR config and zero out DRI */
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tmp = readl(MDREFR) & ~0xfff;
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/* Add user-specified DRI */
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tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
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/* Configure important bits */
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tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
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tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
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/* Write MDREFR back */
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writelrb(tmp, MDREFR);
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/*
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* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
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*/
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/* Initialize SXCNFG register. Assert the enable bits.
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*
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* Write SXMRS to cause an MRS command to all enabled banks of
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* synchronous static memory. Note that SXLCR need not be written
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* at this time.
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*/
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writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
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/*
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* 6) Initialize SDRAM
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*/
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writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
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writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
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/*
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* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
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* but not enable each SDRAM partition pair.
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*/
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writelrb(CONFIG_SYS_MDCNFG_VAL &
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~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
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/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
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pxa_wait_ticks(0x300);
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/*
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* 8) Trigger a number (usually 8) refresh cycles by attempting
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* non-burst read or write accesses to disabled SDRAM, as commonly
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* specified in the power up sequence documented in SDRAM data
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* sheets. The address(es) used for this purpose must not be
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* cacheable.
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*/
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for (i = 9; i >= 0; i--) {
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writel(i, 0xa0000000);
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asm volatile("":::"memory");
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}
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/*
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* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
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*/
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tmp = CONFIG_SYS_MDCNFG_VAL &
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(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
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tmp |= readl(MDCNFG);
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writelrb(tmp, MDCNFG);
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/*
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* 10) Write MDMRS.
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*/
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writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
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/*
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* 11) Enable APD
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*/
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if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
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tmp = readl(MDREFR);
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tmp |= MDREFR_APD;
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writelrb(tmp, MDREFR);
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}
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}
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void pxa_gpio_setup(void)
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{
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writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
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writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
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writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
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#endif
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writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
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writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
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writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
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#endif
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writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
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writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
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writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
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#endif
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writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
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writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
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writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
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writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
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writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
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writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
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writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
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#endif
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writel(CONFIG_SYS_PSSR_VAL, PSSR);
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}
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void pxa_interrupt_setup(void)
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{
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writel(0, ICLR);
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writel(0, ICMR);
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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writel(0, ICLR2);
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writel(0, ICMR2);
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#endif
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}
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void pxa_clock_setup(void)
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{
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#ifndef CONFIG_CPU_MONAHANS
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writel(CONFIG_SYS_CKEN, CKEN);
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writel(CONFIG_SYS_CCCR, CCCR);
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asm volatile("mcr p14, 0, %0, c6, c0, 0"::"r"(2));
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#else
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/* Set CKENA/CKENB/ACCR for MH */
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#endif
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/* enable the 32Khz oscillator for RTC and PowerManager */
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writel(OSCC_OON, OSCC);
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while(!(readl(OSCC) & OSCC_OOK))
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asm volatile("":::"memory");
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}
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void pxa_wakeup(void)
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{
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uint32_t rcsr;
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rcsr = readl(RCSR);
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writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
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/* Wakeup */
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if (rcsr & RCSR_SMR) {
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writel(PSSR_PH, PSSR);
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pxa_dram_init();
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icache_disable();
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dcache_disable();
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asm volatile("mov pc, %0"::"r"(readl(PSSR)));
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}
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}
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int arch_cpu_init(void)
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{
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pxa_gpio_setup();
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/* pxa_wait_ticks(0x8000); */
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pxa_wakeup();
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pxa_interrupt_setup();
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pxa_clock_setup();
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return 0;
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}
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void i2c_clk_enable(void)
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{
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/* set the global I2C clock on */
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#ifdef CONFIG_CPU_MONAHANS
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writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
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#else
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writel(readl(CKEN) | CKEN14_I2C, CKEN);
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#endif
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}
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