u-boot/board/jse
Mike Frysinger 464c79207c punt unused clean/distclean targets
The top level Makefile does not do any recursion into subdirs when
cleaning, so these clean/distclean targets in random arch/board dirs
never get used.  Punt them all.

MAKEALL didn't report any errors related to this that I could see.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-15 22:20:36 +02:00
..
flash.c ppc4xx: Move ppc4xx headers to powerpc include directory 2010-09-23 09:02:05 +02:00
host_bridge.c * Code cleanup, mostly for GCC-3.3.x 2004-12-31 09:32:47 +00:00
init.S ppc4xx: Move ppc4xx headers to powerpc include directory 2010-09-23 09:02:05 +02:00
jse.c ppc4xx: Move ppc4xx headers to powerpc include directory 2010-09-23 09:02:05 +02:00
jse_priv.h * Patch by Stephen Williams, 01 Apr 2004: 2004-04-15 23:14:49 +00:00
Makefile punt unused clean/distclean targets 2011-10-15 22:20:36 +02:00
README.txt * Patch by Stephen Williams, 01 Apr 2004: 2004-04-15 23:14:49 +00:00
sdram.c ppc4xx: Move ppc4xx headers to powerpc include directory 2010-09-23 09:02:05 +02:00

JSE Configuration Details

Memory Bank 0 -- Flash chip
---------------------------

0xfff00000 - 0xffffffff

The flash chip is really only 512Kbytes, but the high address bit of
the 1Meg region is ignored, so the flash is replicated through the
region. Thus, this is consistent with a flash base address 0xfff80000.

The placement at the end is to be consistent with reset behavior,
where the processor itself initially uses this bus to load the branch
vector and start running.

On-Chip Memory
--------------

0xf4000000 - 0xf4000fff

The 405GPr includes a 4K on-chip memory that can be placed however
software chooses. I choose to place the memory at this address, to
keep it out of the cachable areas.


Memory Bank 1 -- SystemACE Controller
-------------------------------------

0xf0000000 - 0xf00fffff

The SystemACE chip is along on peripheral bank CS#1. We don't need
much space, but 1Meg is the smallest we can configure the chip to
allocate. We need it far away from the flash region, because this
region is set to be non-cached.


Internal Peripherals
--------------------

0xef600300 - 0xef6008ff

These are scattered various peripherals internal to the PPC405GPr
chip.

SDRAM
-----

0x00000000 - 0x07ffffff  (128 MBytes)