f31cfd1925
When ECC is enabled, DDR controller needs to initialize the data and ecc. The wait time can be calcuated with total memory size, bus width, bus speed and interleaving mode. If it went wrong, it is bettert to timeout than waiting for D_INIT to clear, where it probably hangs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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| .. | ||
| ddr | ||
| Makefile | ||
| cpu.c | ||
| fdt.c | ||
| fsl_ifc.c | ||
| fsl_lbc.c | ||
| srio.c | ||