Each platform had its own version of the upmconfig, despite the init process being identical. Now that we have a spot for common lbc code, create a common upmconfig() there. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
242 lines
4.9 KiB
C
242 lines
4.9 KiB
C
/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* CPU specific code for the MPC83xx family.
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*
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* Derived from the MPC8260 and MPC85xx.
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <mpc83xx.h>
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#include <asm/processor.h>
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#include <libfdt.h>
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#include <tsec.h>
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#include <netdev.h>
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#include <fsl_esdhc.h>
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#ifdef CONFIG_BOOTCOUNT_LIMIT
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#include <asm/immap_qe.h>
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#include <asm/io.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int checkcpu(void)
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{
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volatile immap_t *immr;
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ulong clock = gd->cpu_clk;
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u32 pvr = get_pvr();
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u32 spridr;
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char buf[32];
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int i;
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const struct cpu_type {
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char name[15];
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u32 partid;
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} cpu_type_list [] = {
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CPU_TYPE_ENTRY(8308),
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CPU_TYPE_ENTRY(8311),
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CPU_TYPE_ENTRY(8313),
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CPU_TYPE_ENTRY(8314),
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CPU_TYPE_ENTRY(8315),
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CPU_TYPE_ENTRY(8321),
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CPU_TYPE_ENTRY(8323),
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CPU_TYPE_ENTRY(8343),
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CPU_TYPE_ENTRY(8347_TBGA_),
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CPU_TYPE_ENTRY(8347_PBGA_),
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CPU_TYPE_ENTRY(8349),
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CPU_TYPE_ENTRY(8358_TBGA_),
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CPU_TYPE_ENTRY(8358_PBGA_),
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CPU_TYPE_ENTRY(8360),
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CPU_TYPE_ENTRY(8377),
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CPU_TYPE_ENTRY(8378),
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CPU_TYPE_ENTRY(8379),
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};
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immr = (immap_t *)CONFIG_SYS_IMMR;
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puts("CPU: ");
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switch (pvr & 0xffff0000) {
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case PVR_E300C1:
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printf("e300c1, ");
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break;
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case PVR_E300C2:
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printf("e300c2, ");
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break;
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case PVR_E300C3:
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printf("e300c3, ");
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break;
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case PVR_E300C4:
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printf("e300c4, ");
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break;
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default:
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printf("Unknown core, ");
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}
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spridr = immr->sysconf.spridr;
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
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puts("MPC");
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puts(cpu_type_list[i].name);
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if (IS_E_PROCESSOR(spridr))
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puts("E");
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if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
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SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
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REVID_MAJOR(spridr) >= 2)
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puts("A");
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printf(", Rev: %d.%d", REVID_MAJOR(spridr),
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REVID_MINOR(spridr));
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break;
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}
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if (i == ARRAY_SIZE(cpu_type_list))
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printf("(SPRIDR %08x unknown), ", spridr);
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printf(" at %s MHz, ", strmhz(buf, clock));
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printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
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return 0;
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}
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int
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do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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ulong msr;
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#ifndef MPC83xx_RESET
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ulong addr;
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#endif
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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puts("Resetting the board.\n");
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#ifdef MPC83xx_RESET
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/* Interrupts and MMU off */
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__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
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msr &= ~( MSR_EE | MSR_IR | MSR_DR);
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__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
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/* enable Reset Control Reg */
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immap->reset.rpr = 0x52535445;
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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/* confirm Reset Control Reg is enabled */
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while(!((immap->reset.rcer) & RCER_CRE));
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udelay(200);
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/* perform reset, only one bit */
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immap->reset.rcr = RCR_SWHR;
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#else /* ! MPC83xx_RESET */
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immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
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/* Interrupts and MMU off */
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__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
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msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
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__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
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/*
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* Trying to execute the next instruction at a non-existing address
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* should cause a machine check, resulting in reset
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*/
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addr = CONFIG_SYS_RESET_ADDRESS;
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((void (*)(void)) addr) ();
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#endif /* MPC83xx_RESET */
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return 1;
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}
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/*
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* Get timebase clock frequency (like cpu_clk in Hz)
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*/
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unsigned long get_tbclk(void)
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{
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ulong tbclk;
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tbclk = (gd->bus_clk + 3L) / 4L;
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return tbclk;
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}
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#if defined(CONFIG_WATCHDOG)
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void watchdog_reset (void)
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{
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int re_enable = disable_interrupts();
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/* Reset the 83xx watchdog */
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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immr->wdt.swsrr = 0x556c;
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immr->wdt.swsrr = 0xaa39;
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if (re_enable)
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enable_interrupts ();
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}
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#endif
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int cpu_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_UEC_ETH)
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uec_standard_init(bis);
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#endif
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#if defined(CONFIG_TSEC_ENET)
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tsec_standard_init(bis);
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#endif
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return 0;
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}
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/*
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* Initializes on-chip MMC controllers.
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* to override, implement board_mmc_init()
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*/
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int cpu_mmc_init(bd_t *bis)
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{
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#ifdef CONFIG_FSL_ESDHC
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return fsl_esdhc_mmc_init(bis);
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#else
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return 0;
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#endif
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}
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