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u-boot/board/freescale/corenet_ds
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York Sun dea8bd627c powerpc/85xx: Update fixed DDR3 timing table for P4080DS 
Most of time U-boot doesn't get an exact clock number. For example, clock
900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the
table to align the desired clocks in the middle.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
 		2011-04-04 09:24:41 -05:00
..
Makefile Switch from archive libraries to partial linking 2010-11-17 21:02:18 +01:00
corenet_ds.c powerpc: Move cpu specific lmb reserve to arch_lmb_reserve 2011-04-04 09:24:40 -05:00
ddr.c powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board 2011-04-04 09:24:41 -05:00
law.c powerpc/p4080: Add support for the P4080DS board 2010-08-01 11:18:40 -05:00
p4080ds_ddr.c powerpc/85xx: Update fixed DDR3 timing table for P4080DS 2011-04-04 09:24:41 -05:00
pci.c powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe code 2011-01-14 01:32:21 -06:00
tlb.c powerpc/p4080: Add support for the P4080DS board 2010-08-01 11:18:40 -05:00