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@ -26,339 +26,12 @@
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#include <stdint.h> |
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#if defined(MICRON_MT47H32M16BN_3_171MHZ) |
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/* Micron MT47H32M16BN-3 @ 171 MHz settings:
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* TCK = 5.85 nS -> 1 / 171MHz |
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* T_REF = 7.8 uS (varies with commercial vs industrial) |
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* T_RFC = 105 nS (varies with capacity) |
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* T_RP = 15 nS |
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* T_RCD = 15 nS |
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* T_WR = 15 nS |
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* T_RAS = 40 nS |
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* T_RASMAX = 70 uS |
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* T_RTP = 7.5 nS |
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* T_RC = 55 nS |
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* T_RRD = 10 nS |
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* T_WTR = 7.5 nS |
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* T_XSRD = 200 nS |
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* T_XSNR = 115 nS -> T_RFC(MIN) + 10 |
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* T_CKE = 3 TCK |
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* T_XP = 2 TCK |
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*/ |
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static const uint8_t DDR_IBANK = 2; /* 4 banks. */ |
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static const uint16_t DDR_RR = 1336; /* DDRCLK * T_REF */ |
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static const uint8_t DDR_CL = 3; |
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static const uint8_t DDR_T_RFC = 17; /* (T_RFC * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RP = 2; /* (T_RP * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RCD = 2; /* (T_RCD * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_WR = 2; /* (T_WR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RAS = 6; /* (T_RAS * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RC = 9; /* (T_RC * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RRD = 1; /* [((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1 */ |
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/*
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* Only for 8 bank DDR2/mDDR memories. When interfacing to DDR2/mDDR memories |
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* with less than 8 banks the T_RRD field should be calculated using: |
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* (T_RRD * DDRCLK) - 1. |
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*/ |
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static const uint8_t DDR_T_WTR = 1; /* (T_WTR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RASMAX = 8; /*
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* (T_RASMAX(uS) / T_REF) - 1 |
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* Should be 17 but max. value |
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* is 15 (4 bits) |
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*/ |
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static const uint8_t DDR_T_XP = 2; /*
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* If T_XP > T_CKE then |
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* T_XP = T_XP - 1 |
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* else |
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* T_XP = T_CKE - 1 |
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*/ |
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static const uint8_t DDR_T_XSNR = 19; /* (T_XSNR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_XSRD = 199; /* T_XSRD - 1 */ |
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static const uint8_t DDR_T_RTP = 1; /* (T_RTP * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_CKE = 2; /* T_CKE - 1 */ |
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static const uint8_t DDR_READ_Latency = 4; /* Board specific */ |
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#elif defined(MICRON_MT47H32M16BN_3_162MHZ) /* SFFSDR */ |
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/* Micron MT47H32M16BN-3 @ 162 MHz settings:
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* TCK = 6.17 nS -> 1 / 162 MHz |
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* T_REF = 7.8 uS (varies with commercial vs industrial) |
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* T_RFC = 105 nS (varies with capacity) |
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* T_RP = 15 nS |
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* T_RCD = 15 nS |
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* T_WR = 15 nS |
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* T_RAS = 40 nS |
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* T_RASMAX = 70 uS |
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* T_RTP = 7.5 nS |
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* T_RC = 55 nS |
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* T_RRD = 10 nS |
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* T_WTR = 7.5 nS |
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* T_XSRD = 200 nS |
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* T_XSNR = 115 nS -> T_RFC(MIN) + 10 |
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* T_CKE = 3 TCK |
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* T_XP = 2 TCK |
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*/ |
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static const uint8_t DDR_IBANK = 2; /* 4 banks. */ |
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static const uint16_t DDR_RR = 1265; /* DDRCLK * T_REF */ |
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static const uint8_t DDR_CL = 3; |
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static const uint8_t DDR_T_RFC = 16; /* (T_RFC * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RP = 2; /* (T_RP * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RCD = 2; /* (T_RCD * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_WR = 2; /* (T_WR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RAS = 6; /* (T_RAS * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RC = 8; /* (T_RC * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RRD = 1; /* [((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1 */ |
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/*
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* Only for 8 bank DDR2/mDDR memories. When interfacing to DDR2/mDDR memories |
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* with less than 8 banks the T_RRD field should be calculated using: |
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* (T_RRD * DDRCLK) - 1. |
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*/ |
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static const uint8_t DDR_T_WTR = 1; /* (T_WTR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RASMAX = 8; /*
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* (T_RASMAX(uS) / T_REF) - 1 |
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* Should be 17 but max. value |
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* is 15 (4 bits) |
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*/ |
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static const uint8_t DDR_T_XP = 2; /*
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* If T_XP > T_CKE then |
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* T_XP = T_XP - 1 |
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* else |
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* T_XP = T_CKE - 1 |
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*/ |
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static const uint8_t DDR_T_XSNR = 18; /* (T_XSNR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_XSRD = 199; /* T_XSRD - 1 */ |
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static const uint8_t DDR_T_RTP = 1; /* (T_RTP * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_CKE = 2; /* T_CKE - 1 */ |
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static const uint8_t DDR_READ_Latency = 4; /* Board specific */ |
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#elif defined(MICRON_MT47H64M16BT_37E_171MHZ) /* EVM DM355 */ |
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/* Micron MT47H64M16BT-37E @ 171 MHz */ |
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static const uint8_t DDR_IBANK = 3; /* 8 banks. */ |
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static const uint16_t DDR_RR = 1336; |
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static const uint8_t DDR_CL = 3; |
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static const uint8_t DDR_T_RFC = 21; |
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static const uint8_t DDR_T_RP = 2; |
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static const uint8_t DDR_T_RCD = 2; |
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static const uint8_t DDR_T_WR = 2; |
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static const uint8_t DDR_T_RAS = 6; |
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static const uint8_t DDR_T_RC = 9; |
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static const uint8_t DDR_T_RRD = 1; |
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static const uint8_t DDR_T_WTR = 1; |
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static const uint8_t DDR_T_RASMAX = 7; |
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static const uint8_t DDR_T_XP = 2; |
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static const uint8_t DDR_T_XSNR = 23; |
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static const uint8_t DDR_T_XSRD = 199; |
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static const uint8_t DDR_T_RTP = 3; |
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static const uint8_t DDR_T_CKE = 3; |
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static const uint8_t DDR_READ_Latency = 4; /* Board specific */ |
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#elif defined(MICRON_MT47H64M16HR_3_162MHZ) /* DAS Commercial */ |
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/* Micron MT47H64M16HR-3 @ 162 MHz settings:
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* TCK = 6.17 nS -> 1 / 162 MHz |
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* T_REF = 7.8 uS (varies with commercial vs industrial) |
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* T_RFC = 127.5 nS (varies with capacity) |
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* T_RP = 15 nS |
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* T_RCD = 15 nS |
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* T_WR = 15 nS |
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* T_RAS = 40 nS |
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* T_RASMAX = 70 uS |
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* T_RTP = 7.5 nS |
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* T_RC = 55 nS |
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* T_RRD = 10 nS |
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* T_WTR = 7.5 nS |
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* T_XSRD = 200 nS |
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* T_XSNR = 138 nS -> T_RFC(MIN) + 10 |
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* T_CKE = 3 TCK |
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* T_XP = 2 TCK |
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*/ |
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static const uint8_t DDR_IBANK = 3; /* 8 banks. */ |
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static const uint16_t DDR_RR = 1265; /* DDRCLK * T_REF */ |
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static const uint8_t DDR_CL = 3; |
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static const uint8_t DDR_T_RFC = 20; /* (T_RFC * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RP = 2; /* (T_RP * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RCD = 2; /* (T_RCD * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_WR = 2; /* (T_WR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RAS = 6; /* (T_RAS * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RC = 8; /* (T_RC * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RRD = 2; /* [((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1 */ |
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/*
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* Only for 8 bank DDR2/mDDR memories. When interfacing to DDR2/mDDR memories |
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* with less than 8 banks the T_RRD field should be calculated using: |
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* (T_RRD * DDRCLK) - 1. |
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*/ |
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static const uint8_t DDR_T_WTR = 1; /* (T_WTR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RASMAX = 8; /*
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* (T_RASMAX(uS) / T_REF) - 1 |
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* Should be 17 but max. value |
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* is 15 (4 bits) |
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*/ |
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static const uint8_t DDR_T_XP = 2; /*
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* If T_XP > T_CKE then |
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* T_XP = T_XP - 1 |
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* else |
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* T_XP = T_CKE - 1 |
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*/ |
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static const uint8_t DDR_T_XSNR = 21; /* (T_XSNR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_XSRD = 199; /* T_XSRD - 1 */ |
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static const uint8_t DDR_T_RTP = 1; /* (T_RTP * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_CKE = 2; /* T_CKE - 1 */ |
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static const uint8_t DDR_READ_Latency = 4; /* Board specific */ |
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#elif defined(MICRON_MT47H64M16HR_3IT_162MHZ) /* DAS industrial */ |
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/* Micron MT47H64M16HR-3IT @ 162 MHz settings:
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* TCK = 6.17 nS -> 1 / 162 MHz |
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* T_REF = 3.9 uS (varies with commercial vs industrial) |
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* T_RFC = 127.5 nS (varies with capacity) |
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* T_RP = 15 nS |
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* T_RCD = 15 nS |
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* T_WR = 15 nS |
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* T_RAS = 40 nS |
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* T_RASMAX = 70 uS |
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* T_RTP = 7.5 nS |
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* T_RC = 55 nS |
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* T_RRD = 10 nS |
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* T_WTR = 7.5 nS |
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* T_XSRD = 200 nS |
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* T_XSNR = 138 nS -> T_RFC(MIN) + 10 |
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* T_CKE = 3 TCK |
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* T_XP = 2 TCK |
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*/ |
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static const uint8_t DDR_IBANK = 3; /* 8 banks. */ |
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static const uint16_t DDR_RR = 635; /* DDRCLK * T_REF */ |
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static const uint8_t DDR_CL = 3; |
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static const uint8_t DDR_T_RFC = 20; /* (T_RFC * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RP = 2; /* (T_RP * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RCD = 2; /* (T_RCD * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_WR = 2; /* (T_WR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RAS = 6; /* (T_RAS * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RC = 8; /* (T_RC * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RRD = 2; /* [((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1 */ |
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/*
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* Only for 8 bank DDR2/mDDR memories. When interfacing to DDR2/mDDR memories |
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|
|
|
* with less than 8 banks the T_RRD field should be calculated using: |
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* (T_RRD * DDRCLK) - 1. |
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*/ |
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static const uint8_t DDR_T_WTR = 1; /* (T_WTR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RASMAX = 15; /*
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* (T_RASMAX(uS) / T_REF) - 1 |
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* Should be 17 but max. value |
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* is 15 (4 bits) |
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*/ |
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static const uint8_t DDR_T_XP = 2; /*
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* If T_XP > T_CKE then |
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* T_XP = T_XP - 1 |
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* else |
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* T_XP = T_CKE - 1 |
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*/ |
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static const uint8_t DDR_T_XSNR = 21; /* (T_XSNR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_XSRD = 199; /* T_XSRD - 1 */ |
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static const uint8_t DDR_T_RTP = 1; /* (T_RTP * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_CKE = 2; /* T_CKE - 1 */ |
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static const uint8_t DDR_READ_Latency = 4; /* Board specific */ |
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#elif defined(MICRON_MT47H64M16BT_3_162MHZ) |
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/* Micron MT47H64M16HR-3IT @ 162 MHz settings:
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|
|
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* TCK = 5.85 nS -> 1 / 162 MHz |
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* T_REF = 3.9 uS (varies with commercial vs industrial) |
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* T_RFC = 198 nS (varies with capacity) |
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* T_RP = 15 nS |
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* T_RCD = 15 nS |
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* T_WR = 15 nS |
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* T_RAS = 40 nS |
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* T_RASMAX = 70 uS |
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* T_RTP = 7.5 nS |
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* T_RC = 55 nS |
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* T_RRD = 10 nS |
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* T_WTR = 7.5 nS |
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* T_XSRD = 200 nS |
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* T_XSNR = 208 nS -> T_RFC(MIN) + 10 |
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* T_CKE = 3 TCK |
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* T_XP = 2 TCK |
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*/ |
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static const uint8_t DDR_IBANK = 3; /* 8 banks. */ |
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static const uint16_t DDR_RR = 667; /* DDRCLK * T_REF */ |
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static const uint8_t DDR_CL = 3; |
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static const uint8_t DDR_T_RFC = 33; /* (T_RFC * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RP = 2; /* (T_RP * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RCD = 2; /* (T_RCD * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_WR = 2; /* (T_WR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RAS = 6; /* (T_RAS * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RC = 9; /* (T_RC * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RRD = 1; /* [((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1 */ |
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/*
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* Only for 8 bank DDR2/mDDR memories. When interfacing to DDR2/mDDR memories |
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|
|
|
* with less than 8 banks the T_RRD field should be calculated using: |
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* (T_RRD * DDRCLK) - 1. |
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*/ |
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static const uint8_t DDR_T_WTR = 1; /* (T_WTR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RASMAX = 15; /*
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* (T_RASMAX(uS) / T_REF) - 1 |
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* Should be 17 but max. value |
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* is 15 (4 bits) |
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*/ |
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static const uint8_t DDR_T_XP = 2; /*
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* If T_XP > T_CKE then |
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* T_XP = T_XP - 1 |
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* else |
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* T_XP = T_CKE - 1 |
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*/ |
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static const uint8_t DDR_T_XSNR = 34; /* (T_XSNR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_XSRD = 199; /* T_XSRD - 1 */ |
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static const uint8_t DDR_T_RTP = 1; /* (T_RTP * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_CKE = 2; /* T_CKE - 1 */ |
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static const uint8_t DDR_READ_Latency = 4; /* Board specific */ |
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#elif defined(MICRON_MT47H128M16HG_3IT_171MHZ) |
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/* Micron MT47H128M16HG-3IT @ 171 MHz settings:
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* TCK = 5.85 nS -> 1 / 171MHz |
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* T_REF = 3.9 uS (varies with commercial vs industrial) |
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* T_RFC = 198 nS (varies with capacity) |
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* T_RP = 15 nS |
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* T_RCD = 15 nS |
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* T_WR = 15 nS |
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* T_RAS = 40 nS |
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* T_RASMAX = 70 uS |
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* T_RTP = 7.5 nS |
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* T_RC = 55 nS |
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* T_RRD = 10 nS |
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* T_WTR = 7.5 nS |
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* T_XSRD = 200 nS |
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* T_XSNR = 208 nS -> T_RFC(MIN) + 10 |
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* T_CKE = 3 TCK |
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* T_XP = 2 TCK |
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*/ |
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static const uint8_t DDR_IBANK = 3; /* 8 banks. */ |
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static const uint16_t DDR_RR = 667; /* DDRCLK * T_REF */ |
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static const uint8_t DDR_CL = 3; |
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static const uint8_t DDR_T_RFC = 33; /* (T_RFC * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RP = 2; /* (T_RP * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RCD = 2; /* (T_RCD * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_WR = 2; /* (T_WR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RAS = 6; /* (T_RAS * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RC = 9; /* (T_RC * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RRD = 1; /* [((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1 */ |
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/*
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* Only for 8 bank DDR2/mDDR memories. When interfacing to DDR2/mDDR memories |
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* with less than 8 banks the T_RRD field should be calculated using: |
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* (T_RRD * DDRCLK) - 1. |
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*/ |
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static const uint8_t DDR_T_WTR = 1; /* (T_WTR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_RASMAX = 15; /*
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* (T_RASMAX(uS) / T_REF) - 1 |
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* Should be 17 but max. value |
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* is 15 (4 bits) |
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*/ |
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static const uint8_t DDR_T_XP = 2; /*
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* If T_XP > T_CKE then |
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* T_XP = T_XP - 1 |
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* else |
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* T_XP = T_CKE - 1 |
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*/ |
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static const uint8_t DDR_T_XSNR = 34; /* (T_XSNR * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_XSRD = 199; /* T_XSRD - 1 */ |
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static const uint8_t DDR_T_RTP = 1; /* (T_RTP * DDRCLK) - 1 */ |
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static const uint8_t DDR_T_CKE = 2; /* T_CKE - 1 */ |
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static const uint8_t DDR_READ_Latency = 4; /* Board specific */ |
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#endif |
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struct ddr_timing_infos_t { |
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uint32_t SDBCR; |
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uint32_t SDTIMR; |
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uint32_t SDTIMR2; |
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uint32_t SDRCR; |
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uint8_t READ_Latency; |
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}; |
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#endif /* _DDDR_H_ */ |
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