interrupt: Allow to interrupt the NAND boot by sending a command
Before doing the NAND boot the 'I_ME' message will be sent and the ubl will wait up to a second for a response. This interruption mode can be disabled, e.g. when deploying the system in a publically accessible system. Right now the possibility of easy recovery is more important.
This commit is contained in:
parent
77e016b643
commit
d04f24974a
2
Makefile
2
Makefile
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@ -48,7 +48,7 @@ ifneq ($(OLDBOARD),$(BOARD))
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$(shell echo "$(BOARD)" > config.h)
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$(shell echo "$(BOARD)" > config.h)
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endif
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endif
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CFLAGS += -D${PLATFORM} -D${FLASH_TYPE} -Dboard_$(BOARD)
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CFLAGS += -D${PLATFORM} -D${FLASH_TYPE} -Dboard_$(BOARD) -DENABLE_BOOT_INTERRUPT
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# Processor type setup
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# Processor type setup
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# The Instruction and Data accesses are differentiated via accessing different
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# The Instruction and Data accesses are differentiated via accessing different
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18
davinci.c
18
davinci.c
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@ -239,14 +239,14 @@ ivt_init(void)
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}
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}
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static int
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static int
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timer0_init(void)
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timer0_init(uint8_t timeout)
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{
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{
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TIMER0->TGCR = 0x00000000; /* Reset timer */
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TIMER0->TGCR = 0x00000000; /* Reset timer */
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TIMER0->TCR = 0x00000000; /* Disable timer */
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TIMER0->TCR = 0x00000000; /* Disable timer */
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TIMER0->TIM12 = 0x00000000; /* Reset timer count to zero */
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TIMER0->TIM12 = 0x00000000; /* Reset timer count to zero */
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/* Set timer period (5 seconds timeout) */
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/* Set timer period (5 seconds timeout) */
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TIMER0->PRD12 = SYSTEM_CLK_HZ * 5;
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TIMER0->PRD12 = SYSTEM_CLK_HZ * timeout;
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return E_PASS;
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return E_PASS;
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}
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}
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@ -261,6 +261,18 @@ timer0_start(void)
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TIMER0->TGCR = 0x00000005; /* Start TIMER12 in 32-bits mode. */
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TIMER0->TGCR = 0x00000005; /* Start TIMER12 in 32-bits mode. */
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}
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}
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void
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timer0_settimeout(uint8_t timeout)
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{
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timer0_init(timeout);
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}
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int
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timer0_setdefault_timeout()
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{
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return timer0_init(5);
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}
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uint32_t
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uint32_t
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timer0_status(void)
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timer0_status(void)
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{
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{
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@ -680,7 +692,7 @@ davinci_platform_init(char *version)
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status |= uart0_init();
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status |= uart0_init();
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if (status == E_PASS)
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if (status == E_PASS)
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status |= timer0_init();
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status |= timer0_setdefault_timeout();
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uart_send_lf();
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uart_send_lf();
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log_info(version);
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log_info(version);
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@ -459,5 +459,7 @@ void ddr_vtp_calibration(void);
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void timer0_start(void);
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void timer0_start(void);
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uint32_t timer0_status(void);
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uint32_t timer0_status(void);
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void timer0_settimeout(uint8_t timeout);
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int timer0_setdefault_timeout(void);
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#endif /* _DAVINCI_H_ */
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#endif /* _DAVINCI_H_ */
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29
ubl.c
29
ubl.c
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@ -85,6 +85,33 @@ icache_enable(void)
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write_p15_c1(reg | C1_IC);
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write_p15_c1(reg | C1_IC);
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}
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}
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/* Disable this for more secure boots */
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#ifdef ENABLE_BOOT_INTERRUPT
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static uint32_t boot_cmd;
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static void
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interrupt_me(void)
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{
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/* short for interrupt me */
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host_msg("I_ME");
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timer0_settimeout(1);
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if (uart_get_cmd(&boot_cmd) != E_PASS)
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return;
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if (boot_cmd != 0x23)
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return;
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timer0_setdefault_timeout();
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log_info("Boot interrupted");
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uart_boot(&jump_entry_point);
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}
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#else
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static void
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interrupt_me(void)
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{
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}
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#endif
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static int
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static int
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ubl_main(void)
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ubl_main(void)
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{
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{
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@ -119,6 +146,8 @@ ubl_main(void)
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case NON_SECURE_NAND:
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case NON_SECURE_NAND:
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log_info("NAND"); /* Report boot mode to host */
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log_info("NAND"); /* Report boot mode to host */
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interrupt_me();
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/* Copy binary application data from NAND to DDRAM */
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/* Copy binary application data from NAND to DDRAM */
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if (nand_copy(&jump_entry_point) != E_PASS) {
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if (nand_copy(&jump_entry_point) != E_PASS) {
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log_info("Boot failed.");
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log_info("Boot failed.");
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