diff --git a/davinci.c b/davinci.c
index 3fe0599..cc06a7b 100644
--- a/davinci.c
+++ b/davinci.c
@@ -252,13 +252,15 @@ timer0_init(uint8_t timeout)
 }
 
 void
-timer0_start(void)
+timer0_start(uint32_t period)
 {
-	AINTC->IRQ1  |= 0x00000001; /* Clear interrupt */
 	TIMER0->TGCR  = 0x00000000; /* Reset timer */
-	TIMER0->TIM12 = 0x00000000; /* Reset timer count to zero */
-	TIMER0->TCR   = 0x00000040; /* Setup for one-shot mode */
-	TIMER0->TGCR  = 0x00000005; /* Start TIMER12 in 32-bits mode. */
+	TIMER0->TCR   = 0x00000000; /* Disable timer */
+	TIMER0->PRD12 = period;
+	AINTC->IRQ1  |= 0x00000001; /* Clear interrupt */                   
+	TIMER0->TIM12 = 0x00000000; /* Reset timer count to zero */         
+	TIMER0->TCR   = 0x00000040; /* Setup for one-shot mode */           
+	TIMER0->TGCR  = 0x00000005; /* Start TIMER12 in 32-bits mode. */    
 }
 
 void
diff --git a/davinci.h b/davinci.h
index ba666f7..0e01dbc 100644
--- a/davinci.h
+++ b/davinci.h
@@ -457,7 +457,7 @@ struct gpio_controller {
 int davinci_platform_init(char *version);
 void ddr_vtp_calibration(void);
 
-void timer0_start(void);
+void timer0_start(uint32_t period);
 uint32_t timer0_status(void);
 void timer0_settimeout(uint8_t timeout);
 int timer0_setdefault_timeout(void);
diff --git a/dm644x.h b/dm644x.h
index 04de9f2..2dbec6f 100644
--- a/dm644x.h
+++ b/dm644x.h
@@ -27,6 +27,7 @@
 #include "common.h"
 
 #define SYSTEM_CLK_HZ 27000000
+#define SYSTEM_CLK_MHZ 27
 
 struct pll_settings_t {
     uint8_t mult;
diff --git a/nand.c b/nand.c
index 3beddf8..32d1e3d 100644
--- a/nand.c
+++ b/nand.c
@@ -37,7 +37,7 @@
 #define NAND_ALE_OFFSET     0x08
 #define NAND_CLE_OFFSET     0x10
 
-#define NAND_TIMEOUT       20480
+#define NAND_TIMEOUT       5000     /*us*/
 
 /* NAND flash commands */
 #define NAND_LO_PAGE        0x00
@@ -289,19 +289,19 @@ flash_read_bytes(uint8_t *dest, uint32_t numBytes)
 
 /* Poll bit of NANDFSR to indicate ready */
 static int
-nand_wait_for_ready(uint32_t timeout)
+nand_wait_for_ready(uint32_t timeout_us)
 {
-	volatile uint32_t cnt = timeout;
 	uint32_t ready;
+	uint32_t timerStatus;
 
 	waitloop(200);
-
+	timer0_start(SYSTEM_CLK_MHZ * timeout_us);
 	do {
 		ready = AEMIF->NANDFSR & NAND_NANDFSR_READY;
-		cnt--;
-	} while ((cnt > 0) && !ready);
+		timerStatus = timer0_status();
+	} while (!ready && timerStatus);
 
-	if (cnt == 0) {
+	if (timerStatus == 0) {
 		log_info("NAND busy timeout");
 		return E_FAIL;
 	}
diff --git a/uart.c b/uart.c
index f14fbfd..0253f2d 100644
--- a/uart.c
+++ b/uart.c
@@ -39,7 +39,7 @@ uart_recv_bytes(size_t count, uint8_t *dest)
 
 	for (i = 0; i < count; i++) {
 		/* Enable timer one time */
-		timer0_start();
+		timer0_start(SYSTEM_CLK_HZ * 5);
 		do {
 			status = (UART0->LSR)&(0x01);
 			timerStatus = timer0_status();
@@ -74,7 +74,7 @@ uart_send_bytes(char *string)
 
 	for (i = 0; i < count; i++) {
 		/* Enable Timer one time */
-		timer0_start();
+		timer0_start(SYSTEM_CLK_HZ * 5);
 		do {
 			status = (UART0->LSR)&(0x20);
 			timerStatus = timer0_status();