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762 lines
20 KiB
762 lines
20 KiB
/* |
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* davinci.c - common DaVinci platform initialization |
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* |
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* Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com> |
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* |
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* Based on TI DaVinci Flash and Boot Utilities, original copyright follows: |
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* Copyright 2008 Texas Instruments, Inc. <www.ti.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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*/ |
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#include "common.h" |
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#include "davinci.h" |
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#include "ddr.h" |
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#include "util.h" |
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#include "uart.h" |
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#include "gpio.h" |
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|
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extern enum bootmode_t bootmode; |
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extern const int8_t lpsc_en_list[]; |
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extern const int8_t lpsc_emurstie_list[]; |
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extern const size_t lpsc_en_list_len; |
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extern const size_t lpsc_emurstie_list_len; |
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|
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/* Table of supported PLL settings */ |
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#define PLL_DAVINCI_594_CFG 0 |
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#define PLL_DAVINCI_810_CFG 1 |
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static const struct pll_settings_t pll1_settings[] = { |
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{ 22 }, /* DSP=594 MHz ARM=297 MHz */ |
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{ 30 }, /* DSP=810 MHz ARM=405 MHz */ |
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}; |
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static const struct pll_settings_t pll2_settings[] = { |
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{ 24 }, /* DDRPHY=324 MHz DDRCLK=162 MHz */ |
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{ 28 }, /* DDRPHY=378 MHz DDRCLK=189 MHz */ |
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}; |
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|
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/* Table of supported DDR devices */ |
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#define DDR_MT47H32M16BN_3_162MHz_CFG 0 |
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#define DDR_MT47H64M16HR_3IT_162MHz_CFG 1 |
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#define DDR_MT47H64M16HR_3IT_189MHz_CFG 2 |
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static const struct ddr_timing_infos_t ddr_timing_infos[] = { |
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{ |
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/* Micron MT47H32M16BN-3 @ 162 MHz settings: |
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* TCK = 6.17 nS -> 1 / 162 MHz |
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* T_REF = 7.8 uS (varies with commercial vs industrial) |
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* T_RFC = 105 nS (varies with capacity) |
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* T_RP = 15 nS |
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* T_RCD = 15 nS |
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* T_WR = 15 nS |
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* T_RAS = 40 nS |
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* T_RASMAX = 70 uS |
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* T_RTP = 7.5 nS |
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* T_RC = 55 nS |
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* T_RRD = 10 nS |
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* T_WTR = 7.5 nS |
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* T_XSRD = 200 nS |
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* T_XSNR = 115 nS -> T_RFC(MIN) + 10 |
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* T_CKE = 3 TCK |
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* T_XP = 2 TCK |
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*/ |
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.SDBCR = SDBCR_DEFAULT |
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| (0 << 14) /* NM = 0; {32-bit bus with} */ |
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| (3 << 9) /* CL = 3; */ |
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| (2 << 4) /* IBANK = 2; {4 banks} */ |
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| (2 << 0), /* PAGESIZE = 2; {1024-word} */ |
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|
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.SDTIMR = (16 << 25) /* T_RFC = 16; {(T_RFC * DDRCLK) - 1} */ |
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| ( 2 << 22) /* T_RP = 2; {(T_RP * DDRCLK) - 1} */ |
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| ( 2 << 19) /* T_RCD = 2; {(T_RCD * DDRCLK) - 1} */ |
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| ( 2 << 16) /* T_WR = 2; {(T_WR * DDRCLK) - 1} */ |
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| ( 6 << 11) /* T_RAS = 6; {(T_RAS * DDRCLK) - 1} */ |
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| ( 8 << 6) /* T_RC = 8; {(T_RC * DDRCLK) - 1} */ |
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| ( 1 << 3) /* T_RRD = 1; {(T_RRD * DDRCLK) - 1} */ |
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| ( 1 << 0), /* T_WTR = 1; {(T_WTR * DDRCLK) - 1} */ |
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.SDTIMR2 = ( 18 << 16) /* T_XSNR = 18; {(T_XSNR * DDRCLK) - 1} */ |
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| (199 << 8) /* T_XSRD = 199; {T_XSRD - 1} */ |
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| ( 1 << 5) /* T_RTP = 1; {(T_RTP * DDRCLK) - 1} */ |
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| ( 2 << 0), /* T_CKE = 2; {T_CKE - 1} */ |
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.SDRCR = 1265, /* RR = 1265; {DDRCLK * T_REF} */ |
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.READ_Latency = 4, |
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}, |
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{ |
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/* Micron MT47H64M16HR-3IT @ 162 MHz settings: |
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* TCK = 6.17 nS -> 1 / 162 MHz |
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* T_REF = 3.9 uS (varies with commercial vs industrial) |
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* T_RFC = 127.5 nS (varies with capacity) |
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* T_RP = 15 nS |
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* T_RCD = 15 nS |
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* T_WR = 15 nS |
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* T_RAS = 40 nS |
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* T_RASMAX = 70 uS |
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* T_RTP = 7.5 nS |
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* T_RC = 55 nS |
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* T_RRD = 10 nS |
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* T_WTR = 7.5 nS |
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* T_XSRD = 200 nS |
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* T_XSNR = 138 nS -> T_RFC(MIN) + 10 |
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* T_CKE = 3 TCK |
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* T_XP = 2 TCK |
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*/ |
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.SDBCR = SDBCR_DEFAULT |
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| (0 << 14) /* NM = 0; {32-bit bus with} */ |
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| (3 << 9) /* CL = 3; */ |
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| (3 << 4) /* IBANK = 3; {8 banks} */ |
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| (2 << 0), /* PAGESIZE = 2; {1024-word} */ |
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.SDTIMR = (20 << 25) /* T_RFC = 20; {(T_RFC * DDRCLK) - 1} */ |
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| ( 2 << 22) /* T_RP = 2; {(T_RP * DDRCLK) - 1} */ |
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| ( 2 << 19) /* T_RCD = 2; {(T_RCD * DDRCLK) - 1} */ |
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| ( 2 << 16) /* T_WR = 2; {(T_WR * DDRCLK) - 1} */ |
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| ( 6 << 11) /* T_RAS = 6; {(T_RAS * DDRCLK) - 1} */ |
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| ( 8 << 6) /* T_RC = 8; {(T_RC * DDRCLK) - 1} */ |
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| ( 2 << 3) /* T_RRD = 2; {[((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1} */ |
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| ( 1 << 0), /* T_WTR = 1; {(T_WTR * DDRCLK) - 1} */ |
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.SDTIMR2 = ( 32 << 16) /* T_XSNR = 32; {(T_XSNR * DDRCLK) - 1} */ |
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| (199 << 8) /* T_XSRD = 199; {T_XSRD - 1} */ |
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| ( 1 << 5) /* T_RTP = 1; {(T_RTP * DDRCLK) - 1} */ |
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| ( 2 << 0), /* T_CKE = 2; {T_CKE - 1} */ |
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.SDRCR = 632, /* RR = 632; {DDRCLK * T_REF} */ |
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.READ_Latency = 4, |
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}, |
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{ |
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/* Micron MT47H64M16HR-3IT @ 189 MHz settings: |
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* TCK = 5.291 nS -> 1 / 189 MHz |
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* T_REF = 3.9 uS (varies with commercial vs industrial) |
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* T_RFC = 127.5 nS (varies with capacity) |
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* T_RP = 15 nS |
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* T_RCD = 15 nS |
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* T_WR = 15 nS |
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* T_RAS = 40 nS |
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* T_RASMAX = 70 uS |
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* T_RTP = 7.5 nS |
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* T_RC = 55 nS |
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* T_RRD = 10 nS |
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* T_WTR = 7.5 nS |
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* T_XSRD = 200 nS |
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* T_XSNR = 138 nS -> T_RFC(MIN) + 10 |
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* T_CKE = 3 TCK |
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* T_XP = 2 TCK |
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*/ |
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.SDBCR = SDBCR_DEFAULT |
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| (0 << 14) /* NM = 0; {32-bit bus with} */ |
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| (3 << 9) /* CL = 3; */ |
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| (3 << 4) /* IBANK = 3; {8 banks} */ |
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| (2 << 0), /* PAGESIZE = 2; {1024-word} */ |
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.SDTIMR = (24 << 25) /* T_RFC = 24; {(T_RFC * DDRCLK) - 1} */ |
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| ( 2 << 22) /* T_RP = 2; {(T_RP * DDRCLK) - 1} */ |
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| ( 2 << 19) /* T_RCD = 2; {(T_RCD * DDRCLK) - 1} */ |
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| ( 2 << 16) /* T_WR = 2; {(T_WR * DDRCLK) - 1} */ |
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| ( 7 << 11) /* T_RAS = 7; {(T_RAS * DDRCLK) - 1} */ |
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| (10 << 6) /* T_RC = 10; {(T_RC * DDRCLK) - 1} */ |
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| ( 2 << 3) /* T_RRD = 2; {[((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1} */ |
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| ( 1 << 0), /* T_WTR = 1; {(T_WTR * DDRCLK) - 1} */ |
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.SDTIMR2 = ( 26 << 16) /* T_XSNR = 26; {(T_XSNR * DDRCLK) - 1} */ |
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| (199 << 8) /* T_XSRD = 199; {T_XSRD - 1} */ |
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| ( 1 << 5) /* T_RTP = 1; {(T_RTP * DDRCLK) - 1} */ |
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| ( 2 << 0), /* T_CKE = 2; {T_CKE - 1} */ |
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.SDRCR = 738, /* RR = 738; {DDRCLK * T_REF} */ |
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.READ_Latency = 4, |
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} |
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}; |
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/* Symbol from linker script */ |
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extern uint32_t __DDR_START; |
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uint32_t DDR_SIZE = (128 << 20); |
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static void |
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pinmuxControl(uint32_t regOffset, uint32_t mask, uint32_t value) |
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{ |
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SYSTEM->PINMUX[regOffset] &= ~mask; |
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SYSTEM->PINMUX[regOffset] |= (mask & value); |
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} |
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static void |
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lpsc_tansition(uint8_t module, uint8_t domain, uint8_t state) |
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{ |
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/* Wait for any outstanding transition to complete */ |
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while ((PSC->PTSTAT) & (0x00000001 << domain)) |
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; |
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/* If we are already in that state, just return */ |
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if (((PSC->MDSTAT[module]) & 0x1F) == state) |
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return; |
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/* Perform transition */ |
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PSC->MDCTL[module] = ((PSC->MDCTL[module]) & (0xFFFFFFE0)) | (state); |
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PSC->PTCMD |= (0x00000001 << domain); |
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/* Wait for transition to complete */ |
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while ((PSC->PTSTAT) & (0x00000001 << domain)) |
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; |
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/* Wait and verify the state */ |
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while (((PSC->MDSTAT[module]) & 0x1F) != state) |
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; |
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} |
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static void |
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i2c_init(void) |
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{ |
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int i; |
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// Perform a bus clear. That is the best we can do to |
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// unlock I2C devices that do not have reset signal |
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SYSTEM->PINMUX[1] &= ~PINMUX1_I2C; |
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gpio_direction_in(43); // SCL High |
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waitloop(450); |
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gpio_direction_in(44); // SDA High |
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waitloop(450); |
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gpio_direction_out(43, 0); // SCL Low |
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waitloop(450); |
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gpio_direction_out(44, 0); // SDA Low |
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waitloop(450); |
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for (i=0; i<9; i++) { |
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gpio_direction_in(43); // SCL High |
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waitloop(450); |
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gpio_direction_out(43, 0); // SCL Low |
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waitloop(450); |
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} |
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gpio_direction_in(43); // SCL High |
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waitloop(450); |
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gpio_direction_in(44); // SDA High |
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SYSTEM->PINMUX[1] |= PINMUX1_I2C; |
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} |
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static void |
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ivt_init(void) |
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{ |
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volatile uint32_t *ivect; |
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extern uint32_t __IVT; |
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if (bootmode == NON_SECURE_NOR) { |
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ivect = &(__IVT); |
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*ivect++ = 0xEAFFFFFE; /* Reset @ 0x00*/ |
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} else |
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ivect = &(__IVT) + 4; |
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*ivect++ = 0xEAFFFFFE; /* Undefined Address @ 0x04 */ |
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*ivect++ = 0xEAFFFFFE; /* Software Interrupt @0x08 */ |
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*ivect++ = 0xEAFFFFFE; /* Pre-Fetch Abort @ 0x0C */ |
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*ivect++ = 0xEAFFFFFE; /* Data Abort @ 0x10 */ |
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*ivect++ = 0xEAFFFFFE; /* Reserved @ 0x14 */ |
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*ivect++ = 0xEAFFFFFE; /* IRQ @ 0x18 */ |
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*ivect = 0xEAFFFFFE; /* FIQ @ 0x1C */ |
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} |
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void |
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timer0_start(uint32_t period) |
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{ |
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TIMER0->TGCR = 0x00000000; /* Reset timer */ |
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TIMER0->TCR = 0x00000000; /* Disable timer */ |
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TIMER0->PRD12 = period; |
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AINTC->IRQ1 |= 0x00000001; /* Clear interrupt */ |
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TIMER0->TIM12 = 0x00000000; /* Reset timer count to zero */ |
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TIMER0->TCR = 0x00000040; /* Setup for one-shot mode */ |
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TIMER0->TGCR = 0x00000005; /* Start TIMER12 in 32-bits mode. */ |
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} |
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uint32_t |
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timer0_status(void) |
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{ |
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return AINTC->IRQ1 & 0x1; |
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} |
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static int |
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uart0_init(void) |
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{ |
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UART0->PWREMU_MGNT = 0; /* Reset UART TX & RX components */ |
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waitloop(100); |
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|
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/* Set DLAB bit - allows setting of clock divisors */ |
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UART0->LCR |= 0x80; |
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/* |
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* Compute divisor value. Normally, we should simply return: |
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* SYSTEM_CLK_HZ / (16 * baudrate) |
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* but we need to round that value by adding 0.5. |
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* Rounding is especially important at high baud rates. |
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*/ |
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UART0->DLL = (SYSTEM_CLK_HZ + (UART_BAUDRATE * (UART_BCLK_RATIO / 2))) / |
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(UART_BCLK_RATIO * UART_BAUDRATE); |
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UART0->DLH = 0x00; |
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UART0->FCR = 0x0007; /* Clear UART TX & RX FIFOs */ |
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UART0->MCR = 0x0000; /* RTS & CTS disabled, |
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* Loopback mode disabled, |
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* Autoflow disabled |
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*/ |
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UART0->LCR = 0x0003; /* Clear DLAB bit |
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* 8-bit words, |
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* 1 STOP bit generated, |
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* No Parity, No Stick paritiy, |
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* No Break control |
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*/ |
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/* Enable receiver, transmitter, set to run. */ |
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UART0->PWREMU_MGNT |= 0x6001; |
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return E_PASS; |
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} |
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static int |
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pll_init(volatile struct pll_regs_t *pll, int pll_mult, int plldiv_ratio[5]) |
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{ |
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int k; |
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volatile uint32_t *plldiv_reg[5]; |
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int pll_is_powered_up = |
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(pll->PLLCTL & DEVICE_PLLCTL_PLLPWRDN_MASK) >> 1; |
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plldiv_reg[0] = &pll->PLLDIV1; |
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plldiv_reg[1] = &pll->PLLDIV2; |
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plldiv_reg[2] = &pll->PLLDIV3; |
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plldiv_reg[3] = &pll->PLLDIV4; |
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plldiv_reg[4] = &pll->PLLDIV5; |
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|
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/* Set PLL clock input to internal osc. */ |
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pll->PLLCTL &= ~(DEVICE_PLLCTL_CLKMODE_MASK); |
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|
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/* Set PLL to bypass, then wait for PLL to stabilize */ |
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pll->PLLCTL &= ~(DEVICE_PLLCTL_PLLENSRC_MASK | |
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DEVICE_PLLCTL_PLLEN_MASK); |
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waitloop(150); |
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/* Reset PLL: Warning, bit state is inverted for DM644x vs DM35x. */ |
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#if defined(DM644x) |
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pll->PLLCTL &= ~DEVICE_PLLCTL_PLLRST_MASK; |
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#elif defined(DM35x) |
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pll->PLLCTL |= DEVICE_PLLCTL_PLLRST_MASK; |
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#endif |
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if (pll_is_powered_up) { |
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/* Disable PLL */ |
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pll->PLLCTL |= DEVICE_PLLCTL_PLLDIS_MASK; |
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|
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/* Powerup PLL */ |
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pll->PLLCTL &= ~(DEVICE_PLLCTL_PLLPWRDN_MASK); |
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} |
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/* Enable PLL */ |
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pll->PLLCTL &= ~(DEVICE_PLLCTL_PLLDIS_MASK); |
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/* Wait for PLL to stabilize */ |
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waitloop(150); |
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/* Load PLL multiplier. */ |
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pll->PLLM = (pll_mult - 1) & 0xff; |
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|
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/* Set and enable dividers as needed. */ |
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for (k = 0; k < 5; k++) { |
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if (plldiv_ratio[k] > 0) |
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*(plldiv_reg[k]) |= DEVICE_PLLDIV_EN_MASK | |
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(plldiv_ratio[k] - 1); |
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} |
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#if defined(DM35x) |
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/* Set the processor AIM wait state and PLL1 post-divider to to 1 */ |
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SYSTEM->MISC &= ~(DEVICE_MISC_PLL1POSTDIV_MASK | |
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DEVICE_MISC_AIMWAITST_MASK); |
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#endif |
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|
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/* Initiate a new divider transition. */ |
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pll->PLLCMD |= DEVICE_PLLCMD_GOSET_MASK; |
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|
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/* Wait for completion of phase alignment. */ |
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while ((pll->PLLSTAT & DEVICE_PLLSTAT_GOSTAT_MASK)) |
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; |
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|
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/* Wait for PLL to reset ( ~5 usec ) */ |
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waitloop(5000); |
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|
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/* Release PLL from reset */ |
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|
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/* Reset PLL: Warning, bit state is inverted for DM644x vs DM35x. */ |
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#if defined(DM644x) |
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pll->PLLCTL |= DEVICE_PLLCTL_PLLRST_MASK; |
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#elif defined(DM35x) |
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pll->PLLCTL &= ~DEVICE_PLLCTL_PLLRST_MASK; |
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#endif |
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|
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/* Wait for PLL to re-lock: |
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* DM644z: 2000P |
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* DM35x: 8000P |
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*/ |
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waitloop(8000); |
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|
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/* Switch out of BYPASS mode */ |
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pll->PLLCTL |= DEVICE_PLLCTL_PLLEN_MASK; |
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|
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return E_PASS; |
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} |
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static int |
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pll1_init(int cfg) |
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{ |
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int plldiv_ratio[5]; |
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|
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#if defined(DM644x) |
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plldiv_ratio[0] = 1; /* PLLDIV1 fixed */ |
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plldiv_ratio[1] = 2; /* PLLDIV2 fixed */ |
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plldiv_ratio[2] = 3; /* PLLDIV3 fixed */ |
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plldiv_ratio[3] = -1; /* PLLDIV4 not used */ |
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plldiv_ratio[4] = 6; /* PLLDIV5 fixed */ |
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#elif defined(DM35x) |
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plldiv_ratio[0] = 2; /* PLLDIV1 fixed */ |
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plldiv_ratio[1] = 4; /* PLLDIV2 fixed */ |
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|
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/* Calculate PLL divider ratio for divider 3 (feeds VPBE) */ |
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plldiv_ratio[2] = 0; |
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while ((plldiv_ratio[2] * VPBE_CLK_HZ) < |
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(SYSTEM_CLK_HZ * (pll1_settings[cfg].mult >> 3))) |
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plldiv_ratio[2]++; |
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|
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/* Check to make sure we can supply accurate VPBE clock */ |
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if ((plldiv_ratio[2] * VPBE_CLK_HZ) != |
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(SYSTEM_CLK_HZ * (pll1_settings[cfg].mult >> 3))) |
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return E_FAIL; |
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|
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/* See the device datasheet for more info (must be 2 or 4) */ |
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plldiv_ratio[3] = 4; |
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plldiv_ratio[4] = -1; /* PLLDIV5 not used */ |
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#endif |
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|
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return pll_init(PLL1, pll1_settings[cfg].mult, plldiv_ratio); |
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} |
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|
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static int |
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pll2_init(int cfg) |
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{ |
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int plldiv_ratio[5]; |
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plldiv_ratio[0] = PLL2_Div1; |
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plldiv_ratio[1] = PLL2_Div2; |
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plldiv_ratio[2] = -1; /* PLLDIV3 not used */ |
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plldiv_ratio[3] = -1; /* PLLDIV4 not used */ |
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plldiv_ratio[4] = -1; /* PLLDIV5 not used */ |
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|
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return pll_init(PLL2, pll2_settings[cfg].mult, plldiv_ratio); |
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} |
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|
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static void |
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ddr_timing_setup(int cfg) |
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{ |
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/* The configuration of DDRPHYCR is not dependent on the DDR2 device |
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* specification but rather on the board layout. |
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* Setup the read latency and clear DLLPWRDN */ |
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DDR->DDRPHYCR = DDRPHYCR_DEFAULT | |
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(ddr_timing_infos[cfg].READ_Latency & DDRPHYCR_READLAT_MASK); |
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|
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/* |
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* Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR) |
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* as suggested in TMS320DM6446 errata 2.1.2: |
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* |
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* On DM6446 Silicon Revision 2.1 and earlier, under certain conditions |
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* low priority modules can occupy the bus and prevent high priority |
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* modules like the VPSS from getting the required DDR2 throughput. |
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*/ |
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DDR->PBBPR = DDR_PBBPR_PR_OLD_COUNT; |
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|
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/* TIMUNLOCK (unlocked), CAS Latency, number of banks and page size */ |
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DDR->SDBCR = SDBCR_TIMUNLOCK | ddr_timing_infos[cfg].SDBCR; |
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|
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/* Program timing registers */ |
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DDR->SDTIMR = ddr_timing_infos[cfg].SDTIMR; |
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DDR->SDTIMR2 = ddr_timing_infos[cfg].SDTIMR2; |
|
|
|
/* Clear the TIMUNLOCK bit (locked) */ |
|
DDR->SDBCR &= ~SDBCR_TIMUNLOCK; |
|
|
|
/* Set the refresh rate */ |
|
DDR->SDRCR = ddr_timing_infos[cfg].SDRCR; |
|
} |
|
|
|
static void |
|
ddr_reset(void) |
|
{ |
|
/* Perform a soft reset to the DDR2 memory controller: |
|
* Put in SYNCRESET and enable it again. */ |
|
lpsc_tansition(LPSC_DDR2, PD0, PSC_SYNCRESET); |
|
lpsc_tansition(LPSC_DDR2, PD0, PSC_ENABLE); |
|
} |
|
|
|
static int |
|
ddr_init(int cfg) |
|
{ |
|
volatile uint32_t *ddr_start = &__DDR_START; |
|
/* For reading/writing dummy value in order to apply timing settings */ |
|
volatile uint32_t ddr_dummy_read; |
|
|
|
/* Enable DDR2 module. */ |
|
lpsc_tansition(LPSC_DDR2, PD0, PSC_ENABLE); |
|
|
|
#if defined(DM35x) |
|
ddr_vtp_calibration(); |
|
ddr_reset(); |
|
#endif |
|
|
|
ddr_timing_setup(cfg); |
|
|
|
/* Dummy read to apply timing settings */ |
|
ddr_dummy_read = ddr_start[0]; |
|
|
|
#if defined(DM644x) |
|
ddr_reset(); |
|
ddr_vtp_calibration(); |
|
#endif |
|
|
|
/* Verify correct initialization. */ |
|
ddr_start[0] = DDR_TEST_PATTERN; |
|
if (ddr_start[0] != DDR_TEST_PATTERN) { |
|
log_fail("DDR init failed"); |
|
return E_FAIL; |
|
} |
|
|
|
return E_PASS; |
|
} |
|
|
|
static void |
|
psc_init(void) |
|
{ |
|
uint32_t i; |
|
|
|
#if defined(DM35x) |
|
/* Do always on power domain transitions */ |
|
while ((PSC->PTSTAT) & 0x00000001); |
|
#elif defined(DM644x) |
|
/* |
|
* Workaround for TMS320DM6446 errata 1.3.22 |
|
* (Revision(s) Affected: 1.3 and earlier): |
|
* PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset. |
|
* Clear the reserved location at address 0x01C41A20 |
|
*/ |
|
PSC_PTSTAT_WORKAROUND_REG = 0; |
|
|
|
/* Put the C64x+ Core into reset (if it's on) */ |
|
PSC->MDCTL[LPSC_DSP] &= (~0x00000100); |
|
PSC->PTCMD |= 0x00000002; |
|
while ((PSC->PTSTAT) & (0x00000002)); |
|
while ((PSC->MDSTAT[LPSC_DSP]) & (0x00000100)); |
|
#endif |
|
|
|
/* Enable selected modules */ |
|
for (i = 0; i < lpsc_en_list_len; i++) { |
|
int8_t k = lpsc_en_list[i]; |
|
|
|
PSC->MDCTL[k] = (PSC->MDCTL[k] & 0xFFFFFFE0) | PSC_ENABLE; |
|
} |
|
|
|
/* Set EMURSTIE on selected modules */ |
|
for (i = 0; i < lpsc_emurstie_list_len; i++) { |
|
int8_t k = lpsc_emurstie_list[i]; |
|
|
|
PSC->MDCTL[k] |= EMURSTIE_MASK; |
|
} |
|
|
|
/* Do Always-On Power Domain Transitions */ |
|
PSC->PTCMD |= 0x00000001; |
|
while ((PSC->PTSTAT) & 0x00000001); |
|
|
|
#if defined(DM644x) |
|
/* DO DSP Power Domain Transitions */ |
|
PSC->PTCMD |= 0x00000002; |
|
while ((PSC->PTSTAT) & (0x00000002)); |
|
#endif |
|
|
|
/* Clear EMURSTIE on selected modules */ |
|
for (i = 0; i < lpsc_emurstie_list_len; i++) { |
|
int8_t k = lpsc_emurstie_list[i]; |
|
|
|
PSC->MDCTL[k] &= (~EMURSTIE_MASK); |
|
} |
|
} |
|
|
|
int |
|
davinci_platform_init(char *version, int *nwp_nand) |
|
{ |
|
int pllCfg; |
|
int ddrCfg; |
|
int status = E_PASS; |
|
unsigned *gpio01 = (unsigned *)(DAVINCI_GPIO_BASE + 0x20); |
|
|
|
*nwp_nand = 0; |
|
|
|
psc_init(); |
|
|
|
/* Disable ARM interrupts */ |
|
AINTC->INTCTL = 0x0; |
|
AINTC->EABASE = 0x0; |
|
AINTC->EINT0 = 0x0; |
|
AINTC->EINT1 = 0x0; |
|
|
|
AINTC->FIQ0 = 0xFFFFFFFF; |
|
AINTC->FIQ1 = 0xFFFFFFFF; |
|
AINTC->IRQ0 = 0xFFFFFFFF; |
|
AINTC->IRQ1 = 0xFFFFFFFF; |
|
|
|
#ifdef PINMUX0_DEFAULT |
|
pinmuxControl(0, 0xFFFFFFFF, PINMUX0_DEFAULT); |
|
#endif |
|
#ifdef PINMUX1_DEFAULT |
|
pinmuxControl(1, 0xFFFFFFFF, PINMUX1_DEFAULT); |
|
#endif |
|
/* The folowing are only available on DM35x */ |
|
#ifdef PINMUX2_DEFAULT |
|
pinmuxControl(2, 0xFFFFFFFF, PINMUX2_DEFAULT); |
|
#endif |
|
#ifdef PINMUX3_DEFAULT |
|
pinmuxControl(3, 0xFFFFFFFF, PINMUX3_DEFAULT); |
|
#endif |
|
#ifdef PINMUX4_DEFAULT |
|
pinmuxControl(4, 0xFFFFFFFF, PINMUX4_DEFAULT); |
|
#endif |
|
|
|
/* Init board configuration */ |
|
#if defined(board_sysmobts_v2) |
|
char boardVer; |
|
char boardCfg; |
|
boardCfg = (*gpio01 >> 10) & 0x001F; |
|
boardVer = (*gpio01 >> 15) & 0x0007; |
|
if (boardVer >= 5) |
|
{ |
|
uart_send_str_lf("Board needs GPIO for nWP"); |
|
*nwp_nand = 1; |
|
} |
|
|
|
if ( boardVer > 1 ) |
|
{ |
|
/* Davinci @ 405/810 MHz */ |
|
pllCfg = PLL_DAVINCI_810_CFG; |
|
|
|
/* Micron MT47H64M16HR-3IT @ 189 MHz */ |
|
ddrCfg = DDR_MT47H64M16HR_3IT_189MHz_CFG; |
|
|
|
uart_send_str_lf("CPU: Davinci @ 405/810 MHz"); |
|
uart_send_str_lf("DDR: Micron MT47H64M16HR-3IT @ 189 MHz"); |
|
} else if ( (boardVer == 1) && ((boardCfg == 0x02) || (boardCfg == 0x04) || (boardCfg == 0x05)) ) |
|
{ |
|
/* Davinci @ 405/810 MHz */ |
|
pllCfg = PLL_DAVINCI_810_CFG; |
|
|
|
/* Micron MT47H64M16HR-3IT @ 189 MHz */ |
|
ddrCfg = DDR_MT47H64M16HR_3IT_189MHz_CFG; |
|
|
|
uart_send_str_lf("CPU: Davinci @ 405/810 MHz"); |
|
uart_send_str_lf("DDR: Micron MT47H64M16HR-3IT @ 189 MHz"); |
|
} |
|
else if ( (boardVer == 0) && (boardCfg != 0x00) ) |
|
{ |
|
DDR_SIZE = (256 << 20); |
|
|
|
/* Davinci @ 297/594 MHz */ |
|
pllCfg = PLL_DAVINCI_594_CFG; |
|
|
|
/* Micron MT47H32M16BN-3 @ 162 MHz */ |
|
ddrCfg = DDR_MT47H64M16HR_3IT_162MHz_CFG; |
|
|
|
uart_send_str_lf("CPU: Davinci @ 297/594 MHz"); |
|
uart_send_str_lf("DDR: Micron MT47H32M16BN-3 @ 162 MHz"); |
|
} |
|
else |
|
#endif |
|
{ |
|
#if defined(board_sysmobts_v2) |
|
DDR_SIZE = (256 << 20); |
|
#else |
|
DDR_SIZE = (128 << 20); |
|
#endif |
|
|
|
/* Davinci @ 297/594 MHz */ |
|
pllCfg = PLL_DAVINCI_594_CFG; |
|
|
|
/* Micron MT47H32M16BN-3 @ 162 MHz */ |
|
ddrCfg = DDR_MT47H32M16BN_3_162MHz_CFG; |
|
|
|
uart_send_str_lf("CPU: Davinci @ 297/594 MHz"); |
|
uart_send_str_lf("DDR: Micron MT47H32M16BN-3 @ 162 MHz"); |
|
} |
|
|
|
if (status == E_PASS) |
|
status |= pll1_init(pllCfg); |
|
|
|
if (status == E_PASS) |
|
status |= uart0_init(); |
|
|
|
uart_send_lf(); |
|
log_info(version); |
|
|
|
#if defined(board_sysmobts_v2) |
|
char str[4]; |
|
uart_send_str("Board revision: "); |
|
str[0] = 'A' + boardVer; |
|
str[1] = '.'; |
|
str[2] = '0' + boardCfg; |
|
str[3] = '\0'; |
|
uart_send_str_lf(str); |
|
#endif |
|
|
|
if (status == E_PASS) |
|
status |= pll2_init(pllCfg); |
|
|
|
if (status == E_PASS) |
|
status |= ddr_init(ddrCfg); |
|
|
|
#ifdef STATUS_LED |
|
gpio_direction_out(STATUS_LED, 1); |
|
#endif /* STATUS_LED */ |
|
|
|
#ifdef board_minidas |
|
gpio_direction_out(FAN, 0); |
|
gpio_direction_out(BUZZER, 0); |
|
|
|
/* Put all peripherals in RESET state */ |
|
gpio_direction_out(DSP1_PWR_ENA, 0); |
|
gpio_direction_out(DSP2_PWR_ENA, 0); |
|
gpio_direction_out(WIFI_RESETn, 0); |
|
gpio_direction_out(GPS_RESETn, 0); |
|
gpio_direction_out(CAN_RESETn, 0); |
|
gpio_direction_out(ATA_RESETn, 0); |
|
gpio_direction_out(CAMERA_RESETn, 0); |
|
|
|
/* Enable power for hard disk */ |
|
gpio_direction_out(HDD_ENA, 1); |
|
#endif |
|
|
|
/* Init/Reset I2C */ |
|
#ifdef PINMUX1_DEFAULT |
|
if ((PINMUX1_DEFAULT) & PINMUX1_I2C) |
|
i2c_init(); |
|
#endif |
|
|
|
/* IRQ Vector Table Setup */ |
|
ivt_init(); |
|
|
|
return status; |
|
}
|
|
|