122 lines
3.0 KiB
C
122 lines
3.0 KiB
C
/*
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* dm35x.c - DM35x specific platform initialization
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*
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* Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com>
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*
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* Based on TI DaVinci Flash and Boot Utilities, original copyright follows:
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* Copyright 2008 Texas Instruments, Inc. <www.ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include "davinci.h"
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#include "util.h"
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#define DEVICE_VTPIOCR_PWRDN_MASK (0x00000040)
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#define DEVICE_VTPIOCR_LOCK_MASK (0x00000080)
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#define DEVICE_VTPIOCR_PWRSAVE_MASK (0x00000100)
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#define DEVICE_VTPIOCR_CLR_MASK (0x00002000)
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#define DEVICE_VTPIOCR_VTPIOREADY_MASK (0x00004000)
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#define DEVICE_VTPIOCR_READY_MASK (0x00008000)
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/* List of modules to enable in the PSC */
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const int8_t lpsc_en_list[] = {
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LPSC_VPSS_MAST,
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LPSC_VPSS_SLV,
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LPSC_EDMACC,
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LPSC_EDMATC0,
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LPSC_EDMATC1,
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LPSC_TIMER3,
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LPSC_SPI1,
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LPSC_MMC_SD1,
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LPSC_ASP1,
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LPSC_USB,
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LPSC_PWM3,
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LPSC_SPI2,
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LPSC_RTO,
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LPSC_DDR2,
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LPSC_AEMIF,
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LPSC_MMC_SD0,
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LPSC_MEMSTK,
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LPSC_ASP0,
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LPSC_I2C,
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LPSC_UART0,
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LPSC_UART1,
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LPSC_UART2,
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LPSC_SPIO,
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LPSC_PWM0,
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LPSC_PWM1,
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LPSC_PWM2,
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LPSC_GPIO,
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LPSC_TIMER0,
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LPSC_TIMER1,
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LPSC_TIMER2,
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LPSC_SYSMOD,
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LPSC_ARM,
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LPSC_VPSS_DAC,
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};
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const size_t lpsc_en_list_len = sizeof(lpsc_en_list) /
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sizeof(lpsc_en_list[0]);
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/* List of modules for which to control EMURSTIE */
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const int8_t lpsc_emurstie_list[] = {
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LPSC_VPSS_MAST,
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LPSC_VPSS_SLV,
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LPSC_TIMER3,
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LPSC_SPI1,
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LPSC_USB,
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LPSC_PWM3,
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LPSC_DDR2,
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LPSC_AEMIF,
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LPSC_MMC_SD0,
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LPSC_ASP0,
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LPSC_GPIO,
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LPSC_VPSS_DAC,
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};
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const size_t lpsc_emurstie_list_len = sizeof(lpsc_emurstie_list) /
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sizeof(lpsc_emurstie_list[0]);
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/* DDR2 VTP Calibration */
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void
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ddr_vtp_calibration(void)
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{
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/* DO VTP calibration:
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* Clear CLR & PWRDN & LOCK bits */
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SYSTEM->VTPIOCR &= ~(DEVICE_VTPIOCR_PWRDN_MASK |
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DEVICE_VTPIOCR_LOCK_MASK |
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DEVICE_VTPIOCR_CLR_MASK);
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/* Un-clear VTP */
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SYSTEM->VTPIOCR |= DEVICE_VTPIOCR_CLR_MASK;
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/* Wait for ready */
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while (!(SYSTEM->VTPIOCR & DEVICE_VTPIOCR_READY_MASK));
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/* Set bit VTP_IO_READY */
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SYSTEM->VTPIOCR |= DEVICE_VTPIOCR_VTPIOREADY_MASK;
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/* Enable power save mode and lock impedance */
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SYSTEM->VTPIOCR |= (DEVICE_VTPIOCR_PWRSAVE_MASK |
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DEVICE_VTPIOCR_LOCK_MASK);
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/* Powerdown VTP as it is locked */
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SYSTEM->VTPIOCR |= DEVICE_VTPIOCR_PWRDN_MASK;
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/* Wait for calibration to complete */
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waitloop(150);
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}
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