Multiple peripherals in SPEAr share common hardware interrupt lines. This patch adds support for a shared irq layer, which registers hardware irqs by itself and exposes virtual irq numbers to peripherals. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>master
viresh kumar
13 years ago
committed by
Russell King
parent
ff37f6e591
commit
4c18e77f71
@ -0,0 +1,73 @@ |
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/*
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* arch/arm/plat-spear/include/plat/shirq.h |
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* |
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* SPEAr platform shared irq layer header file |
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* |
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* Copyright (C) 2009 ST Microelectronics |
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* Viresh Kumar<viresh.kumar@st.com> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#ifndef __PLAT_SHIRQ_H |
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#define __PLAT_SHIRQ_H |
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#include <linux/irq.h> |
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#include <linux/types.h> |
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/*
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* struct shirq_dev_config: shared irq device configuration |
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* |
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* virq: virtual irq number of device |
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* enb_mask: enable mask of device |
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* status_mask: status mask of device |
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* clear_mask: clear mask of device |
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*/ |
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struct shirq_dev_config { |
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u32 virq; |
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u32 enb_mask; |
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u32 status_mask; |
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u32 clear_mask; |
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}; |
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/*
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* struct shirq_regs: shared irq register configuration |
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* |
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* base: base address of shared irq register |
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* enb_reg: enable register offset |
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* reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt |
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* status_reg: status register offset |
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* status_reg_mask: status register valid mask |
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* clear_reg: clear register offset |
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* reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt |
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*/ |
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struct shirq_regs { |
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void __iomem *base; |
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u32 enb_reg; |
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u32 reset_to_enb; |
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u32 status_reg; |
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u32 status_reg_mask; |
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u32 clear_reg; |
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u32 reset_to_clear; |
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}; |
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/*
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* struct spear_shirq: shared irq structure |
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* |
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* irq: hardware irq number |
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* dev_config: array of device config structures which are using "irq" line |
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* dev_count: size of dev_config array |
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* regs: register configuration for shared irq block |
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*/ |
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struct spear_shirq { |
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u32 irq; |
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struct shirq_dev_config *dev_config; |
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u32 dev_count; |
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struct shirq_regs regs; |
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}; |
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int spear_shirq_register(struct spear_shirq *shirq); |
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#endif /* __PLAT_SHIRQ_H */ |
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@ -0,0 +1,118 @@ |
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/*
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* arch/arm/plat-spear/shirq.c |
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* |
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* SPEAr platform shared irq layer source file |
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* |
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* Copyright (C) 2009 ST Microelectronics |
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* Viresh Kumar<viresh.kumar@st.com> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/spinlock.h> |
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#include <plat/shirq.h> |
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struct spear_shirq *shirq; |
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static DEFINE_SPINLOCK(lock); |
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static void shirq_irq_mask(unsigned irq) |
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{ |
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struct spear_shirq *shirq = get_irq_chip_data(irq); |
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u32 val, id = irq - shirq->dev_config[0].virq; |
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unsigned long flags; |
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if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1) |
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return; |
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spin_lock_irqsave(&lock, flags); |
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val = readl(shirq->regs.base + shirq->regs.enb_reg); |
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if (shirq->regs.reset_to_enb) |
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val |= shirq->dev_config[id].enb_mask; |
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else |
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val &= ~(shirq->dev_config[id].enb_mask); |
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writel(val, shirq->regs.base + shirq->regs.enb_reg); |
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spin_unlock_irqrestore(&lock, flags); |
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} |
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static void shirq_irq_unmask(unsigned irq) |
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{ |
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struct spear_shirq *shirq = get_irq_chip_data(irq); |
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u32 val, id = irq - shirq->dev_config[0].virq; |
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unsigned long flags; |
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if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1) |
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return; |
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spin_lock_irqsave(&lock, flags); |
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val = readl(shirq->regs.base + shirq->regs.enb_reg); |
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if (shirq->regs.reset_to_enb) |
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val &= ~(shirq->dev_config[id].enb_mask); |
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else |
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val |= shirq->dev_config[id].enb_mask; |
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writel(val, shirq->regs.base + shirq->regs.enb_reg); |
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spin_unlock_irqrestore(&lock, flags); |
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} |
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static struct irq_chip shirq_chip = { |
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.name = "spear_shirq", |
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.ack = shirq_irq_mask, |
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.mask = shirq_irq_mask, |
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.unmask = shirq_irq_unmask, |
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}; |
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static void shirq_handler(unsigned irq, struct irq_desc *desc) |
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{ |
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u32 i, val, mask; |
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struct spear_shirq *shirq = get_irq_data(irq); |
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desc->chip->ack(irq); |
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while ((val = readl(shirq->regs.base + shirq->regs.status_reg) & |
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shirq->regs.status_reg_mask)) { |
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for (i = 0; (i < shirq->dev_count) && val; i++) { |
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if (!(shirq->dev_config[i].status_mask & val)) |
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continue; |
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generic_handle_irq(shirq->dev_config[i].virq); |
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/* clear interrupt */ |
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val &= ~shirq->dev_config[i].status_mask; |
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if ((shirq->regs.clear_reg == -1) || |
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shirq->dev_config[i].clear_mask == -1) |
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continue; |
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mask = readl(shirq->regs.base + shirq->regs.clear_reg); |
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if (shirq->regs.reset_to_clear) |
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mask &= ~shirq->dev_config[i].clear_mask; |
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else |
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mask |= shirq->dev_config[i].clear_mask; |
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writel(mask, shirq->regs.base + shirq->regs.clear_reg); |
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} |
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} |
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desc->chip->unmask(irq); |
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} |
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int spear_shirq_register(struct spear_shirq *shirq) |
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{ |
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int i; |
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if (!shirq || !shirq->dev_config || !shirq->regs.base) |
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return -EFAULT; |
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if (!shirq->dev_count) |
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return -EINVAL; |
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set_irq_chained_handler(shirq->irq, shirq_handler); |
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for (i = 0; i < shirq->dev_count; i++) { |
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set_irq_chip(shirq->dev_config[i].virq, &shirq_chip); |
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set_irq_handler(shirq->dev_config[i].virq, handle_simple_irq); |
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set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID); |
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set_irq_chip_data(shirq->dev_config[i].virq, shirq); |
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} |
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set_irq_data(shirq->irq, shirq); |
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return 0; |
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} |
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