@ -161,120 +161,6 @@
@@ -161,120 +161,6 @@
# define EDC_MODE_LIMITING 0x0044
# define EDC_MODE_PASSIVE_DAC 0x0055
/* BRB default for class 0 E2 */
# define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170
# define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250
# define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10
# define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50
/* BRB thresholds for E2*/
# define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
# define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
# define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
# define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
# define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
# define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
# define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
# define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
/* BRB default for class 0 E3A0 */
# define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290
# define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410
# define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10
# define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50
/* BRB thresholds for E3A0 */
# define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
# define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
# define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
# define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
# define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
# define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
# define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
# define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
/* BRB default for E3B0 */
# define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330
# define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490
# define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15
# define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55
/* BRB thresholds for E3B0 2 port mode*/
# define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
# define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
# define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
# define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
# define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
# define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
# define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
# define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
/* only for E3B0*/
# define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
# define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
/* Lossy +Lossless GUARANTIED == GUART */
# define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
/* Lossless +Lossless*/
# define PFC_E3B0_2P_PAUSE_LB_GUART 236
/* Lossy +Lossy*/
# define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
/* Lossy +Lossless*/
# define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
/* Lossless +Lossless*/
# define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
/* Lossy +Lossy*/
# define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
# define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
# define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
# define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
/* BRB thresholds for E3B0 4 port mode */
# define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
# define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
# define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
# define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
# define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
# define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
# define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
# define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
/* only for E3B0*/
# define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
# define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
# define PFC_E3B0_4P_LB_GUART 120
# define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
# define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
# define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
# define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
/* Pause defines*/
# define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330
# define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490
# define DEFAULT_E3B0_LB_GUART 40
# define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40
# define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0
# define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40
# define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0
/* ETS defines*/
# define DCBX_INVALID_COS (0xFF)
@ -2144,391 +2030,6 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
@@ -2144,391 +2030,6 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
REG_WR_DMAE ( bp , bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL , wb_data , 2 ) ;
}
/* PFC BRB internal port configuration params */
struct bnx2x_pfc_brb_threshold_val {
u32 pause_xoff ;
u32 pause_xon ;
u32 full_xoff ;
u32 full_xon ;
} ;
struct bnx2x_pfc_brb_e3b0_val {
u32 per_class_guaranty_mode ;
u32 lb_guarantied_hyst ;
u32 full_lb_xoff_th ;
u32 full_lb_xon_threshold ;
u32 lb_guarantied ;
u32 mac_0_class_t_guarantied ;
u32 mac_0_class_t_guarantied_hyst ;
u32 mac_1_class_t_guarantied ;
u32 mac_1_class_t_guarantied_hyst ;
} ;
struct bnx2x_pfc_brb_th_val {
struct bnx2x_pfc_brb_threshold_val pauseable_th ;
struct bnx2x_pfc_brb_threshold_val non_pauseable_th ;
struct bnx2x_pfc_brb_threshold_val default_class0 ;
struct bnx2x_pfc_brb_threshold_val default_class1 ;
} ;
static int bnx2x_pfc_brb_get_config_params (
struct link_params * params ,
struct bnx2x_pfc_brb_th_val * config_val )
{
struct bnx2x * bp = params - > bp ;
DP ( NETIF_MSG_LINK , " Setting PFC BRB configuration \n " ) ;
config_val - > default_class1 . pause_xoff = 0 ;
config_val - > default_class1 . pause_xon = 0 ;
config_val - > default_class1 . full_xoff = 0 ;
config_val - > default_class1 . full_xon = 0 ;
if ( CHIP_IS_E2 ( bp ) ) {
/* Class0 defaults */
config_val - > default_class0 . pause_xoff =
DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR ;
config_val - > default_class0 . pause_xon =
DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR ;
config_val - > default_class0 . full_xoff =
DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR ;
config_val - > default_class0 . full_xon =
DEFAULT0_E2_BRB_MAC_FULL_XON_THR ;
/* Pause able*/
config_val - > pauseable_th . pause_xoff =
PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE ;
config_val - > pauseable_th . pause_xon =
PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE ;
config_val - > pauseable_th . full_xoff =
PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE ;
config_val - > pauseable_th . full_xon =
PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE ;
/* Non pause able*/
config_val - > non_pauseable_th . pause_xoff =
PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE ;
config_val - > non_pauseable_th . pause_xon =
PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE ;
config_val - > non_pauseable_th . full_xoff =
PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE ;
config_val - > non_pauseable_th . full_xon =
PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE ;
} else if ( CHIP_IS_E3A0 ( bp ) ) {
/* Class0 defaults */
config_val - > default_class0 . pause_xoff =
DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR ;
config_val - > default_class0 . pause_xon =
DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR ;
config_val - > default_class0 . full_xoff =
DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR ;
config_val - > default_class0 . full_xon =
DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR ;
/* Pause able */
config_val - > pauseable_th . pause_xoff =
PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE ;
config_val - > pauseable_th . pause_xon =
PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE ;
config_val - > pauseable_th . full_xoff =
PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE ;
config_val - > pauseable_th . full_xon =
PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE ;
/* Non pause able*/
config_val - > non_pauseable_th . pause_xoff =
PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE ;
config_val - > non_pauseable_th . pause_xon =
PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE ;
config_val - > non_pauseable_th . full_xoff =
PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE ;
config_val - > non_pauseable_th . full_xon =
PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE ;
} else if ( CHIP_IS_E3B0 ( bp ) ) {
/* Class0 defaults */
config_val - > default_class0 . pause_xoff =
DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR ;
config_val - > default_class0 . pause_xon =
DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR ;
config_val - > default_class0 . full_xoff =
DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR ;
config_val - > default_class0 . full_xon =
DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR ;
if ( params - > phy [ INT_PHY ] . flags &
FLAGS_4_PORT_MODE ) {
config_val - > pauseable_th . pause_xoff =
PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE ;
config_val - > pauseable_th . pause_xon =
PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE ;
config_val - > pauseable_th . full_xoff =
PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE ;
config_val - > pauseable_th . full_xon =
PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE ;
/* Non pause able*/
config_val - > non_pauseable_th . pause_xoff =
PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE ;
config_val - > non_pauseable_th . pause_xon =
PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE ;
config_val - > non_pauseable_th . full_xoff =
PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE ;
config_val - > non_pauseable_th . full_xon =
PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE ;
} else {
config_val - > pauseable_th . pause_xoff =
PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE ;
config_val - > pauseable_th . pause_xon =
PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE ;
config_val - > pauseable_th . full_xoff =
PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE ;
config_val - > pauseable_th . full_xon =
PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE ;
/* Non pause able*/
config_val - > non_pauseable_th . pause_xoff =
PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE ;
config_val - > non_pauseable_th . pause_xon =
PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE ;
config_val - > non_pauseable_th . full_xoff =
PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE ;
config_val - > non_pauseable_th . full_xon =
PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE ;
}
} else
return - EINVAL ;
return 0 ;
}
static void bnx2x_pfc_brb_get_e3b0_config_params (
struct link_params * params ,
struct bnx2x_pfc_brb_e3b0_val
* e3b0_val ,
struct bnx2x_nig_brb_pfc_port_params * pfc_params ,
const u8 pfc_enabled )
{
if ( pfc_enabled & & pfc_params ) {
e3b0_val - > per_class_guaranty_mode = 1 ;
e3b0_val - > lb_guarantied_hyst = 80 ;
if ( params - > phy [ INT_PHY ] . flags &
FLAGS_4_PORT_MODE ) {
e3b0_val - > full_lb_xoff_th =
PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR ;
e3b0_val - > full_lb_xon_threshold =
PFC_E3B0_4P_BRB_FULL_LB_XON_THR ;
e3b0_val - > lb_guarantied =
PFC_E3B0_4P_LB_GUART ;
e3b0_val - > mac_0_class_t_guarantied =
PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART ;
e3b0_val - > mac_0_class_t_guarantied_hyst =
PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST ;
e3b0_val - > mac_1_class_t_guarantied =
PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART ;
e3b0_val - > mac_1_class_t_guarantied_hyst =
PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST ;
} else {
e3b0_val - > full_lb_xoff_th =
PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR ;
e3b0_val - > full_lb_xon_threshold =
PFC_E3B0_2P_BRB_FULL_LB_XON_THR ;
e3b0_val - > mac_0_class_t_guarantied_hyst =
PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST ;
e3b0_val - > mac_1_class_t_guarantied =
PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART ;
e3b0_val - > mac_1_class_t_guarantied_hyst =
PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST ;
if ( pfc_params - > cos0_pauseable ! =
pfc_params - > cos1_pauseable ) {
/* Nonpauseable= Lossy + pauseable = Lossless*/
e3b0_val - > lb_guarantied =
PFC_E3B0_2P_MIX_PAUSE_LB_GUART ;
e3b0_val - > mac_0_class_t_guarantied =
PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART ;
} else if ( pfc_params - > cos0_pauseable ) {
/* Lossless +Lossless*/
e3b0_val - > lb_guarantied =
PFC_E3B0_2P_PAUSE_LB_GUART ;
e3b0_val - > mac_0_class_t_guarantied =
PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART ;
} else {
/* Lossy +Lossy*/
e3b0_val - > lb_guarantied =
PFC_E3B0_2P_NON_PAUSE_LB_GUART ;
e3b0_val - > mac_0_class_t_guarantied =
PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART ;
}
}
} else {
e3b0_val - > per_class_guaranty_mode = 0 ;
e3b0_val - > lb_guarantied_hyst = 0 ;
e3b0_val - > full_lb_xoff_th =
DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR ;
e3b0_val - > full_lb_xon_threshold =
DEFAULT_E3B0_BRB_FULL_LB_XON_THR ;
e3b0_val - > lb_guarantied =
DEFAULT_E3B0_LB_GUART ;
e3b0_val - > mac_0_class_t_guarantied =
DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART ;
e3b0_val - > mac_0_class_t_guarantied_hyst =
DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST ;
e3b0_val - > mac_1_class_t_guarantied =
DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART ;
e3b0_val - > mac_1_class_t_guarantied_hyst =
DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST ;
}
}
static int bnx2x_update_pfc_brb ( struct link_params * params ,
struct link_vars * vars ,
struct bnx2x_nig_brb_pfc_port_params
* pfc_params )
{
struct bnx2x * bp = params - > bp ;
struct bnx2x_pfc_brb_th_val config_val = { { 0 } } ;
struct bnx2x_pfc_brb_threshold_val * reg_th_config =
& config_val . pauseable_th ;
struct bnx2x_pfc_brb_e3b0_val e3b0_val = { 0 } ;
const int set_pfc = params - > feature_config_flags &
FEATURE_CONFIG_PFC_ENABLED ;
const u8 pfc_enabled = ( set_pfc & & pfc_params ) ;
int bnx2x_status = 0 ;
u8 port = params - > port ;
/* default - pause configuration */
reg_th_config = & config_val . pauseable_th ;
bnx2x_status = bnx2x_pfc_brb_get_config_params ( params , & config_val ) ;
if ( bnx2x_status )
return bnx2x_status ;
if ( pfc_enabled ) {
/* First COS */
if ( pfc_params - > cos0_pauseable )
reg_th_config = & config_val . pauseable_th ;
else
reg_th_config = & config_val . non_pauseable_th ;
} else
reg_th_config = & config_val . default_class0 ;
/* The number of free blocks below which the pause signal to class 0
* of MAC # n is asserted . n = 0 , 1
*/
REG_WR ( bp , ( port ) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
reg_th_config - > pause_xoff ) ;
/* The number of free blocks above which the pause signal to class 0
* of MAC # n is de - asserted . n = 0 , 1
*/
REG_WR ( bp , ( port ) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config - > pause_xon ) ;
/* The number of free blocks below which the full signal to class 0
* of MAC # n is asserted . n = 0 , 1
*/
REG_WR ( bp , ( port ) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config - > full_xoff ) ;
/* The number of free blocks above which the full signal to class 0
* of MAC # n is de - asserted . n = 0 , 1
*/
REG_WR ( bp , ( port ) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config - > full_xon ) ;
if ( pfc_enabled ) {
/* Second COS */
if ( pfc_params - > cos1_pauseable )
reg_th_config = & config_val . pauseable_th ;
else
reg_th_config = & config_val . non_pauseable_th ;
} else
reg_th_config = & config_val . default_class1 ;
/* The number of free blocks below which the pause signal to
* class 1 of MAC # n is asserted . n = 0 , 1
*/
REG_WR ( bp , ( port ) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 ,
reg_th_config - > pause_xoff ) ;
/* The number of free blocks above which the pause signal to
* class 1 of MAC # n is de - asserted . n = 0 , 1
*/
REG_WR ( bp , ( port ) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
BRB1_REG_PAUSE_1_XON_THRESHOLD_0 ,
reg_th_config - > pause_xon ) ;
/* The number of free blocks below which the full signal to
* class 1 of MAC # n is asserted . n = 0 , 1
*/
REG_WR ( bp , ( port ) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
BRB1_REG_FULL_1_XOFF_THRESHOLD_0 ,
reg_th_config - > full_xoff ) ;
/* The number of free blocks above which the full signal to
* class 1 of MAC # n is de - asserted . n = 0 , 1
*/
REG_WR ( bp , ( port ) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
BRB1_REG_FULL_1_XON_THRESHOLD_0 ,
reg_th_config - > full_xon ) ;
if ( CHIP_IS_E3B0 ( bp ) ) {
bnx2x_pfc_brb_get_e3b0_config_params (
params ,
& e3b0_val ,
pfc_params ,
pfc_enabled ) ;
REG_WR ( bp , BRB1_REG_PER_CLASS_GUARANTY_MODE ,
e3b0_val . per_class_guaranty_mode ) ;
/* The hysteresis on the guarantied buffer space for the Lb
* port before signaling XON .
*/
REG_WR ( bp , BRB1_REG_LB_GUARANTIED_HYST ,
e3b0_val . lb_guarantied_hyst ) ;
/* The number of free blocks below which the full signal to the
* LB port is asserted .
*/
REG_WR ( bp , BRB1_REG_FULL_LB_XOFF_THRESHOLD ,
e3b0_val . full_lb_xoff_th ) ;
/* The number of free blocks above which the full signal to the
* LB port is de - asserted .
*/
REG_WR ( bp , BRB1_REG_FULL_LB_XON_THRESHOLD ,
e3b0_val . full_lb_xon_threshold ) ;
/* The number of blocks guarantied for the MAC #n port. n=0,1
*/
/* The number of blocks guarantied for the LB port. */
REG_WR ( bp , BRB1_REG_LB_GUARANTIED ,
e3b0_val . lb_guarantied ) ;
/* The number of blocks guarantied for the MAC #n port. */
REG_WR ( bp , BRB1_REG_MAC_GUARANTIED_0 ,
2 * e3b0_val . mac_0_class_t_guarantied ) ;
REG_WR ( bp , BRB1_REG_MAC_GUARANTIED_1 ,
2 * e3b0_val . mac_1_class_t_guarantied ) ;
/* The number of blocks guarantied for class #t in MAC0. t=0,1
*/
REG_WR ( bp , BRB1_REG_MAC_0_CLASS_0_GUARANTIED ,
e3b0_val . mac_0_class_t_guarantied ) ;
REG_WR ( bp , BRB1_REG_MAC_0_CLASS_1_GUARANTIED ,
e3b0_val . mac_0_class_t_guarantied ) ;
/* The hysteresis on the guarantied buffer space for class in
* MAC0 . t = 0 , 1
*/
REG_WR ( bp , BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST ,
e3b0_val . mac_0_class_t_guarantied_hyst ) ;
REG_WR ( bp , BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST ,
e3b0_val . mac_0_class_t_guarantied_hyst ) ;
/* The number of blocks guarantied for class #t in MAC1.t=0,1
*/
REG_WR ( bp , BRB1_REG_MAC_1_CLASS_0_GUARANTIED ,
e3b0_val . mac_1_class_t_guarantied ) ;
REG_WR ( bp , BRB1_REG_MAC_1_CLASS_1_GUARANTIED ,
e3b0_val . mac_1_class_t_guarantied ) ;
/* The hysteresis on the guarantied buffer space for class #t
* in MAC1 . t = 0 , 1
*/
REG_WR ( bp , BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST ,
e3b0_val . mac_1_class_t_guarantied_hyst ) ;
REG_WR ( bp , BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST ,
e3b0_val . mac_1_class_t_guarantied_hyst ) ;
}
return bnx2x_status ;
}
/******************************************************************************
* Description :
* This function is needed because NIG ARB_CREDIT_WEIGHT_X are
@ -2705,11 +2206,6 @@ int bnx2x_update_pfc(struct link_params *params,
@@ -2705,11 +2206,6 @@ int bnx2x_update_pfc(struct link_params *params,
/* Update NIG params */
bnx2x_update_pfc_nig ( params , vars , pfc_params ) ;
/* Update BRB params */
bnx2x_status = bnx2x_update_pfc_brb ( params , vars , pfc_params ) ;
if ( bnx2x_status )
return bnx2x_status ;
if ( ! vars - > link_up )
return bnx2x_status ;
Yuval Mintz
10 years ago
committed by