Refs #526. Upgraded GCC ARM demo programs to version 8-2018-q4 of GNU ARM Embedded.
git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@721 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
parent
555f7ce0cf
commit
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File diff suppressed because it is too large
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|
||||||
<name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cmFunc.h</name>
|
|
||||||
</file>
|
|
||||||
<file>
|
|
||||||
<name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cmInstr.h</name>
|
|
||||||
</file>
|
|
||||||
<file>
|
|
||||||
<name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cmSimd.h</name>
|
|
||||||
</file>
|
|
||||||
<file>
|
<file>
|
||||||
<name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32F4xx\Include\stm32f405xx.h</name>
|
<name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32F4xx\Include\stm32f405xx.h</name>
|
||||||
</file>
|
</file>
|
||||||
|
@ -2409,6 +2406,9 @@
|
||||||
<file>
|
<file>
|
||||||
<name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h</name>
|
<name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h</name>
|
||||||
</file>
|
</file>
|
||||||
|
<file>
|
||||||
|
<name>$PROJ_DIR$\..\lib\CMSIS\Include\tz_context.h</name>
|
||||||
|
</file>
|
||||||
</group>
|
</group>
|
||||||
<group>
|
<group>
|
||||||
<name>fatfs</name>
|
<name>fatfs</name>
|
||||||
|
@ -2457,6 +2457,12 @@
|
||||||
<file>
|
<file>
|
||||||
<name>$PROJ_DIR$\..\lib\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h</name>
|
<name>$PROJ_DIR$\..\lib\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h</name>
|
||||||
</file>
|
</file>
|
||||||
|
<file>
|
||||||
|
<name>$PROJ_DIR$\..\lib\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c</name>
|
||||||
|
</file>
|
||||||
|
<file>
|
||||||
|
<name>$PROJ_DIR$\..\lib\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h</name>
|
||||||
|
</file>
|
||||||
<file>
|
<file>
|
||||||
<name>$PROJ_DIR$\..\lib\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c</name>
|
<name>$PROJ_DIR$\..\lib\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c</name>
|
||||||
</file>
|
</file>
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -122,11 +122,11 @@
|
||||||
#endif /* USE_HAL_DRIVER */
|
#endif /* USE_HAL_DRIVER */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief CMSIS version number V2.6.2
|
* @brief CMSIS version number V2.6.3
|
||||||
*/
|
*/
|
||||||
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
|
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
|
||||||
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
|
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
|
||||||
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
|
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
|
||||||
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||||
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|
||||||
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
|
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
|
||||||
|
@ -211,10 +211,10 @@ typedef enum
|
||||||
} FunctionalState;
|
} FunctionalState;
|
||||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||||
|
|
||||||
typedef enum
|
typedef enum
|
||||||
{
|
{
|
||||||
ERROR = 0U,
|
SUCCESS = 0U,
|
||||||
SUCCESS = !ERROR
|
ERROR = !SUCCESS
|
||||||
} ErrorStatus;
|
} ErrorStatus;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -1,136 +0,0 @@
|
||||||
/* ----------------------------------------------------------------------
|
|
||||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* $Date: 19. October 2015
|
|
||||||
* $Revision: V.1.4.5 a
|
|
||||||
*
|
|
||||||
* Project: CMSIS DSP Library
|
|
||||||
* Title: arm_common_tables.h
|
|
||||||
*
|
|
||||||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
|
|
||||||
*
|
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
* - Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* - Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this
|
|
||||||
* software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
#ifndef _ARM_COMMON_TABLES_H
|
|
||||||
#define _ARM_COMMON_TABLES_H
|
|
||||||
|
|
||||||
#include "arm_math.h"
|
|
||||||
|
|
||||||
extern const uint16_t armBitRevTable[1024];
|
|
||||||
extern const q15_t armRecipTableQ15[64];
|
|
||||||
extern const q31_t armRecipTableQ31[64];
|
|
||||||
/* extern const q31_t realCoefAQ31[1024]; */
|
|
||||||
/* extern const q31_t realCoefBQ31[1024]; */
|
|
||||||
extern const float32_t twiddleCoef_16[32];
|
|
||||||
extern const float32_t twiddleCoef_32[64];
|
|
||||||
extern const float32_t twiddleCoef_64[128];
|
|
||||||
extern const float32_t twiddleCoef_128[256];
|
|
||||||
extern const float32_t twiddleCoef_256[512];
|
|
||||||
extern const float32_t twiddleCoef_512[1024];
|
|
||||||
extern const float32_t twiddleCoef_1024[2048];
|
|
||||||
extern const float32_t twiddleCoef_2048[4096];
|
|
||||||
extern const float32_t twiddleCoef_4096[8192];
|
|
||||||
#define twiddleCoef twiddleCoef_4096
|
|
||||||
extern const q31_t twiddleCoef_16_q31[24];
|
|
||||||
extern const q31_t twiddleCoef_32_q31[48];
|
|
||||||
extern const q31_t twiddleCoef_64_q31[96];
|
|
||||||
extern const q31_t twiddleCoef_128_q31[192];
|
|
||||||
extern const q31_t twiddleCoef_256_q31[384];
|
|
||||||
extern const q31_t twiddleCoef_512_q31[768];
|
|
||||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
|
||||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
|
||||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
|
||||||
extern const q15_t twiddleCoef_16_q15[24];
|
|
||||||
extern const q15_t twiddleCoef_32_q15[48];
|
|
||||||
extern const q15_t twiddleCoef_64_q15[96];
|
|
||||||
extern const q15_t twiddleCoef_128_q15[192];
|
|
||||||
extern const q15_t twiddleCoef_256_q15[384];
|
|
||||||
extern const q15_t twiddleCoef_512_q15[768];
|
|
||||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
|
||||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
|
||||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
|
||||||
extern const float32_t twiddleCoef_rfft_32[32];
|
|
||||||
extern const float32_t twiddleCoef_rfft_64[64];
|
|
||||||
extern const float32_t twiddleCoef_rfft_128[128];
|
|
||||||
extern const float32_t twiddleCoef_rfft_256[256];
|
|
||||||
extern const float32_t twiddleCoef_rfft_512[512];
|
|
||||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
|
||||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
|
||||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
|
||||||
|
|
||||||
|
|
||||||
/* floating-point bit reversal tables */
|
|
||||||
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
|
|
||||||
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
|
|
||||||
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
|
|
||||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
|
|
||||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
|
|
||||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
|
|
||||||
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
|
|
||||||
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
|
|
||||||
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
|
|
||||||
|
|
||||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
|
|
||||||
|
|
||||||
/* fixed-point bit reversal tables */
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
|
||||||
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
|
||||||
|
|
||||||
/* Tables for Fast Math Sine and Cosine */
|
|
||||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
|
||||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
|
||||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
|
||||||
|
|
||||||
#endif /* ARM_COMMON_TABLES_H */
|
|
|
@ -1,79 +0,0 @@
|
||||||
/* ----------------------------------------------------------------------
|
|
||||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* $Date: 19. March 2015
|
|
||||||
* $Revision: V.1.4.5
|
|
||||||
*
|
|
||||||
* Project: CMSIS DSP Library
|
|
||||||
* Title: arm_const_structs.h
|
|
||||||
*
|
|
||||||
* Description: This file has constant structs that are initialized for
|
|
||||||
* user convenience. For example, some can be given as
|
|
||||||
* arguments to the arm_cfft_f32() function.
|
|
||||||
*
|
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
* - Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* - Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this
|
|
||||||
* software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
#ifndef _ARM_CONST_STRUCTS_H
|
|
||||||
#define _ARM_CONST_STRUCTS_H
|
|
||||||
|
|
||||||
#include "arm_math.h"
|
|
||||||
#include "arm_common_tables.h"
|
|
||||||
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
|
||||||
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
|
||||||
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
|
||||||
|
|
||||||
#endif
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,43 +1,104 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file cmsis_armcc.h
|
* @file cmsis_armcc.h
|
||||||
* @brief CMSIS Cortex-M Core Function/Instruction Header File
|
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||||
* @version V4.30
|
* @version V5.0.4
|
||||||
* @date 20. October 2015
|
* @date 10. January 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#ifndef __CMSIS_ARMCC_H
|
#ifndef __CMSIS_ARMCC_H
|
||||||
#define __CMSIS_ARMCC_H
|
#define __CMSIS_ARMCC_H
|
||||||
|
|
||||||
|
|
||||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CMSIS compiler control architecture macros */
|
||||||
|
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||||
|
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||||
|
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||||
|
|
||||||
|
|
||||||
|
/* CMSIS compiler specific defines */
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE static __forceinline
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __declspec(noreturn)
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT __packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION __packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* ########################### Core Function Access ########################### */
|
/* ########################### Core Function Access ########################### */
|
||||||
|
@ -46,7 +107,19 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable IRQ Interrupts
|
||||||
|
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
/* intrinsic void __enable_irq(); */
|
/* intrinsic void __enable_irq(); */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable IRQ Interrupts
|
||||||
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
/* intrinsic void __disable_irq(); */
|
/* intrinsic void __disable_irq(); */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -181,7 +254,8 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable FIQ
|
\brief Enable FIQ
|
||||||
|
@ -256,14 +330,13 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
{
|
{
|
||||||
register uint32_t __regFaultMask __ASM("faultmask");
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
__regFaultMask = (faultMask & (uint32_t)1);
|
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get FPSCR
|
\brief Get FPSCR
|
||||||
\details Returns the current value of the Floating Point Status/Control register.
|
\details Returns the current value of the Floating Point Status/Control register.
|
||||||
|
@ -271,7 +344,8 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
{
|
{
|
||||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
register uint32_t __regfpscr __ASM("fpscr");
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
return(__regfpscr);
|
return(__regfpscr);
|
||||||
#else
|
#else
|
||||||
|
@ -287,15 +361,15 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
{
|
{
|
||||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
register uint32_t __regfpscr __ASM("fpscr");
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
__regfpscr = (fpscr);
|
__regfpscr = (fpscr);
|
||||||
|
#else
|
||||||
|
(void)fpscr;
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||||
|
|
||||||
|
@ -369,9 +443,10 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
__schedule_barrier();\
|
__schedule_barrier();\
|
||||||
} while (0U)
|
} while (0U)
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Reverse byte order (32 bit)
|
\brief Reverse byte order (32 bit)
|
||||||
\details Reverses the byte order in integer value.
|
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
|
@ -380,7 +455,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Reverse byte order (16 bit)
|
\brief Reverse byte order (16 bit)
|
||||||
\details Reverses the byte order in two unsigned short values.
|
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
|
@ -392,14 +467,15 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Reverse byte order in signed short value
|
\brief Reverse byte order (16 bit)
|
||||||
\details Reverses the byte order in a signed short value with sign extension to integer.
|
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
#ifndef __NO_EMBEDDED_ASM
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||||
{
|
{
|
||||||
revsh r0, r0
|
revsh r0, r0
|
||||||
bx lr
|
bx lr
|
||||||
|
@ -410,8 +486,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
||||||
/**
|
/**
|
||||||
\brief Rotate Right in unsigned value (32 bit)
|
\brief Rotate Right in unsigned value (32 bit)
|
||||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||||
\param [in] value Value to rotate
|
\param [in] op1 Value to rotate
|
||||||
\param [in] value Number of Bits to rotate
|
\param [in] op2 Number of Bits to rotate
|
||||||
\return Rotated value
|
\return Rotated value
|
||||||
*/
|
*/
|
||||||
#define __ROR __ror
|
#define __ROR __ror
|
||||||
|
@ -433,23 +509,24 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
#define __RBIT __rbit
|
#define __RBIT __rbit
|
||||||
#else
|
#else
|
||||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
|
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||||
|
|
||||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||||
for (value >>= 1U; value; value >>= 1U)
|
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||||
{
|
{
|
||||||
result <<= 1U;
|
result <<= 1U;
|
||||||
result |= value & 1U;
|
result |= value & 1U;
|
||||||
s--;
|
s--;
|
||||||
}
|
}
|
||||||
result <<= s; /* shift when v's highest bits are zero */
|
result <<= s; /* shift when v's highest bits are zero */
|
||||||
return(result);
|
return result;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -463,7 +540,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
#define __CLZ __clz
|
#define __CLZ __clz
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief LDR Exclusive (8 bit)
|
\brief LDR Exclusive (8 bit)
|
||||||
|
@ -645,7 +723,60 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
|
||||||
*/
|
*/
|
||||||
#define __STRT(value, ptr) __strt(value, ptr)
|
#define __STRT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Signed Saturate
|
||||||
|
\details Saturates a signed value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if ((sat >= 1U) && (sat <= 32U))
|
||||||
|
{
|
||||||
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||||
|
const int32_t min = -1 - max ;
|
||||||
|
if (val > max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < min)
|
||||||
|
{
|
||||||
|
return min;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Unsigned Saturate
|
||||||
|
\details Saturates an unsigned value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if (sat <= 31U)
|
||||||
|
{
|
||||||
|
const uint32_t max = ((1U << sat) - 1U);
|
||||||
|
if (val > (int32_t)max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < 0)
|
||||||
|
{
|
||||||
|
return 0U;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (uint32_t)val;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||||
|
|
||||||
|
@ -656,7 +787,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
|
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
#define __SADD8 __sadd8
|
#define __SADD8 __sadd8
|
||||||
#define __QADD8 __qadd8
|
#define __QADD8 __qadd8
|
||||||
|
@ -727,7 +858,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
|
||||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x04) */
|
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||||
|
|
||||||
|
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,266 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_compiler.h
|
||||||
|
* @brief CMSIS compiler generic header file
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CMSIS_COMPILER_H
|
||||||
|
#define __CMSIS_COMPILER_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 4/5
|
||||||
|
*/
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#include "cmsis_armcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 6 (armclang)
|
||||||
|
*/
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#include "cmsis_armclang.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GNU Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#include "cmsis_gcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* IAR Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#include <cmsis_iccarm.h>
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TI Arm Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TASKING Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __packed__ T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __align(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* COSMIC Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#include <cmsis_csm.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM _asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
// NO RETURN is automatically detected hence no warning here
|
||||||
|
#define __NO_RETURN
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||||
|
#define __USED
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __weak
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED @packed
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT @packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION @packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
@packed struct T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||||
|
#define __ALIGNED(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error Unknown compiler.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CMSIS_COMPILER_H */
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,935 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_iccarm.h
|
||||||
|
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||||
|
* @version V5.0.7
|
||||||
|
* @date 19. June 2018
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
//
|
||||||
|
// Copyright (c) 2017-2018 IAR Systems
|
||||||
|
//
|
||||||
|
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||||
|
// you may not use this file except in compliance with the License.
|
||||||
|
// You may obtain a copy of the License at
|
||||||
|
// http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
//
|
||||||
|
// Unless required by applicable law or agreed to in writing, software
|
||||||
|
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
// See the License for the specific language governing permissions and
|
||||||
|
// limitations under the License.
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __CMSIS_ICCARM_H__
|
||||||
|
#define __CMSIS_ICCARM_H__
|
||||||
|
|
||||||
|
#ifndef __ICCARM__
|
||||||
|
#error This file should only be compiled by ICCARM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#pragma system_include
|
||||||
|
|
||||||
|
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||||
|
|
||||||
|
#if (__VER__ >= 8000000)
|
||||||
|
#define __ICCARM_V8 1
|
||||||
|
#else
|
||||||
|
#define __ICCARM_V8 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#elif (__VER__ >= 7080000)
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#else
|
||||||
|
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||||
|
#define __ALIGNED(x)
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||||
|
*/
|
||||||
|
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||||
|
/* Macros already defined */
|
||||||
|
#else
|
||||||
|
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#elif defined(__ARM8M_BASELINE__)
|
||||||
|
#define __ARM_ARCH_8M_BASE__ 1
|
||||||
|
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||||
|
#if __ARM_ARCH == 6
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#elif __ARM_ARCH == 7
|
||||||
|
#if __ARM_FEATURE_DSP
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#else
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#endif
|
||||||
|
#endif /* __ARM_ARCH */
|
||||||
|
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Alternativ core deduction for older ICCARM's */
|
||||||
|
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||||
|
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||||
|
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||||
|
#define __ARM_ARCH_8M_BASE__ 1
|
||||||
|
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#else
|
||||||
|
#error "Unknown target."
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||||
|
#define __IAR_M0_FAMILY 1
|
||||||
|
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||||
|
#define __IAR_M0_FAMILY 1
|
||||||
|
#else
|
||||||
|
#define __IAR_M0_FAMILY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __NO_RETURN __attribute__((__noreturn__))
|
||||||
|
#else
|
||||||
|
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED __packed
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED_STRUCT __packed struct
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED_UNION __packed union
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __FORCEINLINE
|
||||||
|
#define __FORCEINLINE _Pragma("inline=forced")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||||
|
{
|
||||||
|
return *(__packed uint16_t*)(ptr);
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||||
|
{
|
||||||
|
*(__packed uint16_t*)(ptr) = val;;
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||||
|
{
|
||||||
|
return *(__packed uint32_t*)(ptr);
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||||
|
{
|
||||||
|
*(__packed uint32_t*)(ptr) = val;;
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__packed struct __iar_u32 { uint32_t v; };
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __USED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#else
|
||||||
|
#define __USED _Pragma("__root")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __WEAK
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#else
|
||||||
|
#define __WEAK _Pragma("__weak")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||||
|
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||||
|
|
||||||
|
#if defined(__CLZ)
|
||||||
|
#undef __CLZ
|
||||||
|
#endif
|
||||||
|
#if defined(__REVSH)
|
||||||
|
#undef __REVSH
|
||||||
|
#endif
|
||||||
|
#if defined(__RBIT)
|
||||||
|
#undef __RBIT
|
||||||
|
#endif
|
||||||
|
#if defined(__SSAT)
|
||||||
|
#undef __SSAT
|
||||||
|
#endif
|
||||||
|
#if defined(__USAT)
|
||||||
|
#undef __USAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "iccarm_builtin.h"
|
||||||
|
|
||||||
|
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||||
|
#define __disable_irq __iar_builtin_disable_interrupt
|
||||||
|
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||||
|
#define __enable_irq __iar_builtin_enable_interrupt
|
||||||
|
#define __arm_rsr __iar_builtin_rsr
|
||||||
|
#define __arm_wsr __iar_builtin_wsr
|
||||||
|
|
||||||
|
|
||||||
|
#define __get_APSR() (__arm_rsr("APSR"))
|
||||||
|
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||||
|
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||||
|
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||||
|
|
||||||
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
|
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||||
|
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||||
|
#else
|
||||||
|
#define __get_FPSCR() ( 0 )
|
||||||
|
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||||
|
#define __get_MSP() (__arm_rsr("MSP"))
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
#define __get_MSPLIM() (0U)
|
||||||
|
#else
|
||||||
|
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||||
|
#endif
|
||||||
|
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||||
|
#define __get_PSP() (__arm_rsr("PSP"))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __get_PSPLIM() (0U)
|
||||||
|
#else
|
||||||
|
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||||
|
|
||||||
|
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||||
|
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||||
|
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||||
|
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||||
|
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||||
|
#endif
|
||||||
|
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||||
|
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||||
|
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||||
|
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||||
|
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||||
|
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||||
|
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||||
|
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||||
|
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||||
|
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||||
|
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||||
|
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __TZ_get_PSPLIM_NS() (0U)
|
||||||
|
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||||
|
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||||
|
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||||
|
|
||||||
|
#define __NOP __iar_builtin_no_operation
|
||||||
|
|
||||||
|
#define __CLZ __iar_builtin_CLZ
|
||||||
|
#define __CLREX __iar_builtin_CLREX
|
||||||
|
|
||||||
|
#define __DMB __iar_builtin_DMB
|
||||||
|
#define __DSB __iar_builtin_DSB
|
||||||
|
#define __ISB __iar_builtin_ISB
|
||||||
|
|
||||||
|
#define __LDREXB __iar_builtin_LDREXB
|
||||||
|
#define __LDREXH __iar_builtin_LDREXH
|
||||||
|
#define __LDREXW __iar_builtin_LDREX
|
||||||
|
|
||||||
|
#define __RBIT __iar_builtin_RBIT
|
||||||
|
#define __REV __iar_builtin_REV
|
||||||
|
#define __REV16 __iar_builtin_REV16
|
||||||
|
|
||||||
|
__IAR_FT int16_t __REVSH(int16_t val)
|
||||||
|
{
|
||||||
|
return (int16_t) __iar_builtin_REVSH(val);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define __ROR __iar_builtin_ROR
|
||||||
|
#define __RRX __iar_builtin_RRX
|
||||||
|
|
||||||
|
#define __SEV __iar_builtin_SEV
|
||||||
|
|
||||||
|
#if !__IAR_M0_FAMILY
|
||||||
|
#define __SSAT __iar_builtin_SSAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __STREXB __iar_builtin_STREXB
|
||||||
|
#define __STREXH __iar_builtin_STREXH
|
||||||
|
#define __STREXW __iar_builtin_STREX
|
||||||
|
|
||||||
|
#if !__IAR_M0_FAMILY
|
||||||
|
#define __USAT __iar_builtin_USAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __WFE __iar_builtin_WFE
|
||||||
|
#define __WFI __iar_builtin_WFI
|
||||||
|
|
||||||
|
#if __ARM_MEDIA__
|
||||||
|
#define __SADD8 __iar_builtin_SADD8
|
||||||
|
#define __QADD8 __iar_builtin_QADD8
|
||||||
|
#define __SHADD8 __iar_builtin_SHADD8
|
||||||
|
#define __UADD8 __iar_builtin_UADD8
|
||||||
|
#define __UQADD8 __iar_builtin_UQADD8
|
||||||
|
#define __UHADD8 __iar_builtin_UHADD8
|
||||||
|
#define __SSUB8 __iar_builtin_SSUB8
|
||||||
|
#define __QSUB8 __iar_builtin_QSUB8
|
||||||
|
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||||
|
#define __USUB8 __iar_builtin_USUB8
|
||||||
|
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||||
|
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||||
|
#define __SADD16 __iar_builtin_SADD16
|
||||||
|
#define __QADD16 __iar_builtin_QADD16
|
||||||
|
#define __SHADD16 __iar_builtin_SHADD16
|
||||||
|
#define __UADD16 __iar_builtin_UADD16
|
||||||
|
#define __UQADD16 __iar_builtin_UQADD16
|
||||||
|
#define __UHADD16 __iar_builtin_UHADD16
|
||||||
|
#define __SSUB16 __iar_builtin_SSUB16
|
||||||
|
#define __QSUB16 __iar_builtin_QSUB16
|
||||||
|
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||||
|
#define __USUB16 __iar_builtin_USUB16
|
||||||
|
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||||
|
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||||
|
#define __SASX __iar_builtin_SASX
|
||||||
|
#define __QASX __iar_builtin_QASX
|
||||||
|
#define __SHASX __iar_builtin_SHASX
|
||||||
|
#define __UASX __iar_builtin_UASX
|
||||||
|
#define __UQASX __iar_builtin_UQASX
|
||||||
|
#define __UHASX __iar_builtin_UHASX
|
||||||
|
#define __SSAX __iar_builtin_SSAX
|
||||||
|
#define __QSAX __iar_builtin_QSAX
|
||||||
|
#define __SHSAX __iar_builtin_SHSAX
|
||||||
|
#define __USAX __iar_builtin_USAX
|
||||||
|
#define __UQSAX __iar_builtin_UQSAX
|
||||||
|
#define __UHSAX __iar_builtin_UHSAX
|
||||||
|
#define __USAD8 __iar_builtin_USAD8
|
||||||
|
#define __USADA8 __iar_builtin_USADA8
|
||||||
|
#define __SSAT16 __iar_builtin_SSAT16
|
||||||
|
#define __USAT16 __iar_builtin_USAT16
|
||||||
|
#define __UXTB16 __iar_builtin_UXTB16
|
||||||
|
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||||
|
#define __SXTB16 __iar_builtin_SXTB16
|
||||||
|
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||||
|
#define __SMUAD __iar_builtin_SMUAD
|
||||||
|
#define __SMUADX __iar_builtin_SMUADX
|
||||||
|
#define __SMMLA __iar_builtin_SMMLA
|
||||||
|
#define __SMLAD __iar_builtin_SMLAD
|
||||||
|
#define __SMLADX __iar_builtin_SMLADX
|
||||||
|
#define __SMLALD __iar_builtin_SMLALD
|
||||||
|
#define __SMLALDX __iar_builtin_SMLALDX
|
||||||
|
#define __SMUSD __iar_builtin_SMUSD
|
||||||
|
#define __SMUSDX __iar_builtin_SMUSDX
|
||||||
|
#define __SMLSD __iar_builtin_SMLSD
|
||||||
|
#define __SMLSDX __iar_builtin_SMLSDX
|
||||||
|
#define __SMLSLD __iar_builtin_SMLSLD
|
||||||
|
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||||
|
#define __SEL __iar_builtin_SEL
|
||||||
|
#define __QADD __iar_builtin_QADD
|
||||||
|
#define __QSUB __iar_builtin_QSUB
|
||||||
|
#define __PKHBT __iar_builtin_PKHBT
|
||||||
|
#define __PKHTB __iar_builtin_PKHTB
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||||
|
#define __CLZ __cmsis_iar_clz_not_active
|
||||||
|
#define __SSAT __cmsis_iar_ssat_not_active
|
||||||
|
#define __USAT __cmsis_iar_usat_not_active
|
||||||
|
#define __RBIT __cmsis_iar_rbit_not_active
|
||||||
|
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||||
|
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||||
|
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __INTRINSICS_INCLUDED
|
||||||
|
#error intrinsics.h is already included previously!
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <intrinsics.h>
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||||
|
#undef __CLZ
|
||||||
|
#undef __SSAT
|
||||||
|
#undef __USAT
|
||||||
|
#undef __RBIT
|
||||||
|
#undef __get_APSR
|
||||||
|
|
||||||
|
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||||
|
{
|
||||||
|
if (data == 0U) { return 32U; }
|
||||||
|
|
||||||
|
uint32_t count = 0U;
|
||||||
|
uint32_t mask = 0x80000000U;
|
||||||
|
|
||||||
|
while ((data & mask) == 0U)
|
||||||
|
{
|
||||||
|
count += 1U;
|
||||||
|
mask = mask >> 1U;
|
||||||
|
}
|
||||||
|
return count;
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||||
|
{
|
||||||
|
uint8_t sc = 31U;
|
||||||
|
uint32_t r = v;
|
||||||
|
for (v >>= 1U; v; v >>= 1U)
|
||||||
|
{
|
||||||
|
r <<= 1U;
|
||||||
|
r |= v & 1U;
|
||||||
|
sc--;
|
||||||
|
}
|
||||||
|
return (r << sc);
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm("MRS %0,APSR" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||||
|
#undef __get_FPSCR
|
||||||
|
#undef __set_FPSCR
|
||||||
|
#define __get_FPSCR() (0)
|
||||||
|
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#pragma diag_suppress=Pe940
|
||||||
|
#pragma diag_suppress=Pe177
|
||||||
|
|
||||||
|
#define __enable_irq __enable_interrupt
|
||||||
|
#define __disable_irq __disable_interrupt
|
||||||
|
#define __NOP __no_operation
|
||||||
|
|
||||||
|
#define __get_xPSR __get_PSR
|
||||||
|
|
||||||
|
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||||
|
{
|
||||||
|
return __LDREX((unsigned long *)ptr);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||||
|
{
|
||||||
|
return __STREX(value, (unsigned long *)ptr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#define __enable_fault_irq __enable_fiq
|
||||||
|
#define __disable_fault_irq __disable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||||
|
}
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||||
|
|
||||||
|
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||||
|
|
||||||
|
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if ((sat >= 1U) && (sat <= 32U))
|
||||||
|
{
|
||||||
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||||
|
const int32_t min = -1 - max ;
|
||||||
|
if (val > max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < min)
|
||||||
|
{
|
||||||
|
return min;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if (sat <= 31U)
|
||||||
|
{
|
||||||
|
const uint32_t max = ((1U << sat) - 1U);
|
||||||
|
if (val > (int32_t)max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < 0)
|
||||||
|
{
|
||||||
|
return 0U;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (uint32_t)val;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||||
|
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||||
|
|
||||||
|
#undef __IAR_FT
|
||||||
|
#undef __IAR_M0_FAMILY
|
||||||
|
#undef __ICCARM_V8
|
||||||
|
|
||||||
|
#pragma diag_default=Pe940
|
||||||
|
#pragma diag_default=Pe177
|
||||||
|
|
||||||
|
#endif /* __CMSIS_ICCARM_H__ */
|
|
@ -0,0 +1,39 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_version.h
|
||||||
|
* @brief CMSIS Core(M) Version definitions
|
||||||
|
* @version V5.0.2
|
||||||
|
* @date 19. April 2017
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CMSIS_VERSION_H
|
||||||
|
#define __CMSIS_VERSION_H
|
||||||
|
|
||||||
|
/* CMSIS Version definitions */
|
||||||
|
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||||
|
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||||
|
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||||
|
#endif
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -1,40 +1,30 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_cm0.h
|
* @file core_cm0.h
|
||||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||||
* @version V4.30
|
* @version V5.0.5
|
||||||
* @date 20. October 2015
|
* @date 28. May 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -70,53 +60,15 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
/* CMSIS CM0 definitions */
|
/* CMSIS CM0 definitions */
|
||||||
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
|
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#define __packed
|
|
||||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error Unknown compiler
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** __FPU_USED indicates whether an FPU is used or not.
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
This core does not support an FPU at all
|
This core does not support an FPU at all
|
||||||
|
@ -128,7 +80,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
#if defined __ARM_PCS_VFP
|
#if defined __ARM_PCS_VFP
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -143,7 +95,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
#elif defined ( __TI_ARM__ )
|
||||||
#if defined __TI_VFP_SUPPORT__
|
#if defined __TI_VFP_SUPPORT__
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -160,8 +112,8 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
#include "core_cmFunc.h" /* Core Function Access */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -555,18 +507,18 @@ typedef struct
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a bit field value for use in a register bit range.
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of the bit field.
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted value.
|
\return Masked and shifted value.
|
||||||
*/
|
*/
|
||||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a register value to extract a bit filed value.
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of register.
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted bit field value.
|
\return Masked and shifted bit field value.
|
||||||
*/
|
*/
|
||||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
/*@} end of group CMSIS_core_bitfield */
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
@ -578,7 +530,7 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Memory mapping of Cortex-M0 Hardware */
|
/* Memory mapping of Core Hardware */
|
||||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
@ -614,87 +566,177 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
/* The following MACROS handle generation of the register offset and byte masks */
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||||
|
|
||||||
|
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||||
|
#define __NVIC_GetPriorityGrouping() (0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable External Interrupt
|
\brief Enable Interrupt
|
||||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Disable External Interrupt
|
\brief Get Interrupt Enable status
|
||||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Pending Interrupt
|
\brief Get Pending Interrupt
|
||||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not pending.
|
\return 0 Interrupt status is not pending.
|
||||||
\return 1 Interrupt status is pending.
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Pending Interrupt
|
\brief Set Pending Interrupt
|
||||||
\details Sets the pending bit of an external interrupt.
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Clear Pending Interrupt
|
\brief Clear Pending Interrupt
|
||||||
\details Clears the pending bit of an external interrupt.
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Interrupt Priority
|
\brief Set Interrupt Priority
|
||||||
\details Sets the priority of an interrupt.
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
\note The priority cannot be set for every core interrupt.
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\param [in] priority Priority to set.
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
{
|
{
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -702,24 +744,108 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Interrupt Priority
|
\brief Get Interrupt Priority
|
||||||
\details Reads the priority of an interrupt.
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
or negative to specify an internal (core) interrupt.
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\return Interrupt Priority.
|
\return Interrupt Priority.
|
||||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
|
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
|
||||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Encode Priority
|
||||||
|
\details Encodes the priority for an interrupt with the given priority group,
|
||||||
|
preemptive priority value, and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [in] SubPriority Subpriority value (starting from 0).
|
||||||
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
return (
|
||||||
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||||
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Decode Priority
|
||||||
|
\details Decodes an interrupt priority value with a given priority group to
|
||||||
|
preemptive priority value and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||||
|
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||||
|
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
Address 0 must be mapped to SRAM.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -727,7 +853,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
\brief System Reset
|
\brief System Reset
|
||||||
\details Initiates a system reset request to reset the MCU.
|
\details Initiates a system reset request to reset the MCU.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
{
|
{
|
||||||
__DSB(); /* Ensure all outstanding memory accesses included
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
buffered write are completed before reset */
|
buffered write are completed before reset */
|
||||||
|
@ -744,6 +870,31 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
/*@} end of CMSIS_Core_NVICFunctions */
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ################################## SysTick function ############################################ */
|
/* ################################## SysTick function ############################################ */
|
||||||
/**
|
/**
|
||||||
|
@ -753,7 +904,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__Vendor_SysTickConfig == 0U)
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Tick Configuration
|
\brief System Tick Configuration
|
||||||
|
|
|
@ -1,40 +1,30 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_cm0plus.h
|
* @file core_cm0plus.h
|
||||||
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
|
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
|
||||||
* @version V4.30
|
* @version V5.0.6
|
||||||
* @date 20. October 2015
|
* @date 28. May 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -70,53 +60,15 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
/* CMSIS CM0+ definitions */
|
/* CMSIS CM0+ definitions */
|
||||||
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
|
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
|
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#define __packed
|
|
||||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error Unknown compiler
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** __FPU_USED indicates whether an FPU is used or not.
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
This core does not support an FPU at all
|
This core does not support an FPU at all
|
||||||
|
@ -128,7 +80,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
#if defined __ARM_PCS_VFP
|
#if defined __ARM_PCS_VFP
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -143,7 +95,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
#elif defined ( __TI_ARM__ )
|
||||||
#if defined __TI_VFP_SUPPORT__
|
#if defined __TI_VFP_SUPPORT__
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -160,8 +112,8 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
#include "core_cmFunc.h" /* Core Function Access */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -404,7 +356,7 @@ typedef struct
|
||||||
{
|
{
|
||||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||||
#if (__VTOR_PRESENT == 1U)
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||||||
#else
|
#else
|
||||||
uint32_t RESERVED0;
|
uint32_t RESERVED0;
|
||||||
|
@ -461,7 +413,7 @@ typedef struct
|
||||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
#if (__VTOR_PRESENT == 1U)
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||||
/* SCB Interrupt Control State Register Definitions */
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
|
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
|
||||||
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||||
|
@ -558,7 +510,7 @@ typedef struct
|
||||||
|
|
||||||
/*@} end of group CMSIS_SysTick */
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
/**
|
/**
|
||||||
\ingroup CMSIS_core_register
|
\ingroup CMSIS_core_register
|
||||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||||
|
@ -578,6 +530,8 @@ typedef struct
|
||||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||||
} MPU_Type;
|
} MPU_Type;
|
||||||
|
|
||||||
|
#define MPU_TYPE_RALIASES 1U
|
||||||
|
|
||||||
/* MPU Type Register Definitions */
|
/* MPU Type Register Definitions */
|
||||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||||
|
@ -667,18 +621,18 @@ typedef struct
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a bit field value for use in a register bit range.
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of the bit field.
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted value.
|
\return Masked and shifted value.
|
||||||
*/
|
*/
|
||||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a register value to extract a bit filed value.
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of register.
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted bit field value.
|
\return Masked and shifted bit field value.
|
||||||
*/
|
*/
|
||||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
/*@} end of group CMSIS_core_bitfield */
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
@ -690,7 +644,7 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Memory mapping of Cortex-M0+ Hardware */
|
/* Memory mapping of Core Hardware */
|
||||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
@ -700,7 +654,7 @@ typedef struct
|
||||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||||
#endif
|
#endif
|
||||||
|
@ -730,87 +684,177 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
/* The following MACROS handle generation of the register offset and byte masks */
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||||
|
|
||||||
|
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||||
|
#define __NVIC_GetPriorityGrouping() (0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable External Interrupt
|
\brief Enable Interrupt
|
||||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Disable External Interrupt
|
\brief Get Interrupt Enable status
|
||||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Pending Interrupt
|
\brief Get Pending Interrupt
|
||||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not pending.
|
\return 0 Interrupt status is not pending.
|
||||||
\return 1 Interrupt status is pending.
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Pending Interrupt
|
\brief Set Pending Interrupt
|
||||||
\details Sets the pending bit of an external interrupt.
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Clear Pending Interrupt
|
\brief Clear Pending Interrupt
|
||||||
\details Clears the pending bit of an external interrupt.
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Interrupt Priority
|
\brief Set Interrupt Priority
|
||||||
\details Sets the priority of an interrupt.
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
\note The priority cannot be set for every core interrupt.
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\param [in] priority Priority to set.
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
{
|
{
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -818,24 +862,117 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Interrupt Priority
|
\brief Get Interrupt Priority
|
||||||
\details Reads the priority of an interrupt.
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
or negative to specify an internal (core) interrupt.
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\return Interrupt Priority.
|
\return Interrupt Priority.
|
||||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
|
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
|
||||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Encode Priority
|
||||||
|
\details Encodes the priority for an interrupt with the given priority group,
|
||||||
|
preemptive priority value, and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [in] SubPriority Subpriority value (starting from 0).
|
||||||
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
return (
|
||||||
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||||
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Decode Priority
|
||||||
|
\details Decodes an interrupt priority value with a given priority group to
|
||||||
|
preemptive priority value and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||||
|
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||||
|
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
VTOR must been relocated to SRAM before.
|
||||||
|
If VTOR is not present address 0 must be mapped to SRAM.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
#else
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
#endif
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
#else
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
#endif
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -843,7 +980,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
\brief System Reset
|
\brief System Reset
|
||||||
\details Initiates a system reset request to reset the MCU.
|
\details Initiates a system reset request to reset the MCU.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
{
|
{
|
||||||
__DSB(); /* Ensure all outstanding memory accesses included
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
buffered write are completed before reset */
|
buffered write are completed before reset */
|
||||||
|
@ -859,6 +996,38 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_NVICFunctions */
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
/* ########################## MPU functions #################################### */
|
||||||
|
|
||||||
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
|
|
||||||
|
#include "mpu_armv7.h"
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ################################## SysTick function ############################################ */
|
/* ################################## SysTick function ############################################ */
|
||||||
|
@ -869,7 +1038,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__Vendor_SysTickConfig == 0U)
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Tick Configuration
|
\brief System Tick Configuration
|
||||||
|
|
|
@ -0,0 +1,976 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cm1.h
|
||||||
|
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||||
|
* @version V1.0.0
|
||||||
|
* @date 23. July 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CORE_CM1_H_GENERIC
|
||||||
|
#define __CORE_CM1_H_GENERIC
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||||
|
CMSIS violates the following MISRA-C:2004 rules:
|
||||||
|
|
||||||
|
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||||
|
Function definitions in header files are used to allow 'inlining'.
|
||||||
|
|
||||||
|
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||||
|
Unions are used for effective representation of core registers.
|
||||||
|
|
||||||
|
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||||
|
Function-like macros are used to allow more efficient code.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* CMSIS definitions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\ingroup Cortex_M1
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
|
/* CMSIS CM1 definitions */
|
||||||
|
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
|
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
|
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
|
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
|
This core does not support an FPU at all
|
||||||
|
*/
|
||||||
|
#define __FPU_USED 0U
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#if defined __TARGET_FPU_VFP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#if defined __ARM_PCS_VFP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#if defined __ARMVFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#if defined __TI_VFP_SUPPORT__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#if defined __FPU_VFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#if ( __CSMC__ & 0x400U)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM1_H_GENERIC */
|
||||||
|
|
||||||
|
#ifndef __CMSIS_GENERIC
|
||||||
|
|
||||||
|
#ifndef __CORE_CM1_H_DEPENDANT
|
||||||
|
#define __CORE_CM1_H_DEPENDANT
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* check device defines and use defaults */
|
||||||
|
#if defined __CHECK_DEVICE_DEFINES
|
||||||
|
#ifndef __CM1_REV
|
||||||
|
#define __CM1_REV 0x0100U
|
||||||
|
#warning "__CM1_REV not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NVIC_PRIO_BITS
|
||||||
|
#define __NVIC_PRIO_BITS 2U
|
||||||
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __Vendor_SysTickConfig
|
||||||
|
#define __Vendor_SysTickConfig 0U
|
||||||
|
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* IO definitions (access restrictions to peripheral registers) */
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||||
|
|
||||||
|
<strong>IO Type Qualifiers</strong> are used
|
||||||
|
\li to specify the access to peripheral variables.
|
||||||
|
\li for automatic generation of peripheral register debug information.
|
||||||
|
*/
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define __I volatile /*!< Defines 'read only' permissions */
|
||||||
|
#else
|
||||||
|
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||||
|
#endif
|
||||||
|
#define __O volatile /*!< Defines 'write only' permissions */
|
||||||
|
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||||
|
|
||||||
|
/* following defines should be used for structure members */
|
||||||
|
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||||
|
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||||
|
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||||
|
|
||||||
|
/*@} end of group Cortex_M1 */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Register Abstraction
|
||||||
|
Core Register contain:
|
||||||
|
- Core Register
|
||||||
|
- Core NVIC Register
|
||||||
|
- Core SCB Register
|
||||||
|
- Core SysTick Register
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||||
|
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CORE Status and Control Registers
|
||||||
|
\brief Core Register type definitions.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Application Program Status Register (APSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} APSR_Type;
|
||||||
|
|
||||||
|
/* APSR Register Definitions */
|
||||||
|
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||||
|
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||||
|
|
||||||
|
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||||
|
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||||
|
|
||||||
|
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||||
|
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||||
|
|
||||||
|
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||||
|
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} IPSR_Type;
|
||||||
|
|
||||||
|
/* IPSR Register Definitions */
|
||||||
|
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||||
|
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||||
|
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} xPSR_Type;
|
||||||
|
|
||||||
|
/* xPSR Register Definitions */
|
||||||
|
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||||
|
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||||
|
|
||||||
|
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||||
|
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||||
|
|
||||||
|
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||||
|
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||||
|
|
||||||
|
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||||
|
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||||
|
|
||||||
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
|
||||||
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Control Registers (CONTROL).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||||
|
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||||
|
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} CONTROL_Type;
|
||||||
|
|
||||||
|
/* CONTROL Register Definitions */
|
||||||
|
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||||
|
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_CORE */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||||
|
\brief Type definitions for the NVIC Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||||
|
uint32_t RESERVED0[31U];
|
||||||
|
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||||
|
uint32_t RSERVED1[31U];
|
||||||
|
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||||
|
uint32_t RESERVED2[31U];
|
||||||
|
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||||
|
uint32_t RESERVED3[31U];
|
||||||
|
uint32_t RESERVED4[64U];
|
||||||
|
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||||
|
} NVIC_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_NVIC */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||||
|
\brief Type definitions for the System Control Block Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Control Block (SCB).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||||
|
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||||
|
uint32_t RESERVED0;
|
||||||
|
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||||
|
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||||
|
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||||
|
uint32_t RESERVED1;
|
||||||
|
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||||
|
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||||
|
} SCB_Type;
|
||||||
|
|
||||||
|
/* SCB CPUID Register Definitions */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||||
|
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||||
|
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||||
|
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||||
|
|
||||||
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||||
|
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||||
|
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||||
|
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||||
|
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB System Control Register Definitions */
|
||||||
|
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||||
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||||
|
|
||||||
|
/* SCB Configuration Control Register Definitions */
|
||||||
|
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||||
|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||||
|
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||||
|
|
||||||
|
/* SCB System Handler Control and State Register Definitions */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCB */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||||
|
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t RESERVED0[2U];
|
||||||
|
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||||
|
} SCnSCB_Type;
|
||||||
|
|
||||||
|
/* Auxiliary Control Register Definitions */
|
||||||
|
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
|
||||||
|
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
|
||||||
|
|
||||||
|
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
|
||||||
|
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCnotSCB */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||||
|
\brief Type definitions for the System Timer Registers.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Timer (SysTick).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||||
|
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||||
|
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||||
|
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||||
|
} SysTick_Type;
|
||||||
|
|
||||||
|
/* SysTick Control / Status Register Definitions */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||||
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||||
|
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||||
|
|
||||||
|
/* SysTick Reload Register Definitions */
|
||||||
|
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||||
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||||
|
|
||||||
|
/* SysTick Current Register Definitions */
|
||||||
|
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||||
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||||
|
|
||||||
|
/* SysTick Calibration Register Definitions */
|
||||||
|
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||||
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||||
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||||
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||||
|
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||||
|
Therefore they are not covered by the Cortex-M1 header file.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*@} end of group CMSIS_CoreDebug */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||||
|
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted value.
|
||||||
|
*/
|
||||||
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted bit field value.
|
||||||
|
*/
|
||||||
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_base Core Definitions
|
||||||
|
\brief Definitions for base addresses, unions, and structures.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Memory mapping of Core Hardware */
|
||||||
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||||
|
|
||||||
|
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||||
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||||
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
|
|
||||||
|
/*@} */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Hardware Abstraction Layer
|
||||||
|
Core Function Interface contains:
|
||||||
|
- Core NVIC Functions
|
||||||
|
- Core SysTick Functions
|
||||||
|
- Core Register Access Functions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## NVIC functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||||
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||||
|
|
||||||
|
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||||
|
#define __NVIC_GetPriorityGrouping() (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable Interrupt
|
||||||
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Enable status
|
||||||
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Pending Interrupt
|
||||||
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt status is not pending.
|
||||||
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Pending Interrupt
|
||||||
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Clear Pending Interrupt
|
||||||
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Priority
|
||||||
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Priority
|
||||||
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Interrupt Priority.
|
||||||
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Encode Priority
|
||||||
|
\details Encodes the priority for an interrupt with the given priority group,
|
||||||
|
preemptive priority value, and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [in] SubPriority Subpriority value (starting from 0).
|
||||||
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
return (
|
||||||
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||||
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Decode Priority
|
||||||
|
\details Decodes an interrupt priority value with a given priority group to
|
||||||
|
preemptive priority value and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||||
|
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||||
|
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
Address 0 must be mapped to SRAM.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Reset
|
||||||
|
\details Initiates a system reset request to reset the MCU.
|
||||||
|
*/
|
||||||
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
|
buffered write are completed before reset */
|
||||||
|
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||||
|
__DSB(); /* Ensure completion of memory access */
|
||||||
|
|
||||||
|
for(;;) /* wait until reset */
|
||||||
|
{
|
||||||
|
__NOP();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ################################## SysTick function ############################################ */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||||
|
\brief Functions that configure the System.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Tick Configuration
|
||||||
|
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||||
|
Counter is in free running mode to generate periodic interrupts.
|
||||||
|
\param [in] ticks Number of ticks between two interrupts.
|
||||||
|
\return 0 Function succeeded.
|
||||||
|
\return 1 Function failed.
|
||||||
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||||
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||||
|
must contain a vendor-specific implementation of this function.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
|
{
|
||||||
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||||
|
{
|
||||||
|
return (1UL); /* Reload value impossible */
|
||||||
|
}
|
||||||
|
|
||||||
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||||
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||||
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||||
|
SysTick_CTRL_TICKINT_Msk |
|
||||||
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||||
|
return (0UL); /* Function successful */
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM1_H_DEPENDANT */
|
||||||
|
|
||||||
|
#endif /* __CMSIS_GENERIC */
|
File diff suppressed because it is too large
Load Diff
|
@ -1,40 +1,30 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_cm3.h
|
* @file core_cm3.h
|
||||||
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
|
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
|
||||||
* @version V4.30
|
* @version V5.0.8
|
||||||
* @date 20. October 2015
|
* @date 04. June 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -70,53 +60,15 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
/* CMSIS CM3 definitions */
|
/* CMSIS CM3 definitions */
|
||||||
#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
|
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
__CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
__CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
#define __CORTEX_M (0x03U) /*!< Cortex-M Core */
|
#define __CORTEX_M (3U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#define __packed
|
|
||||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error Unknown compiler
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** __FPU_USED indicates whether an FPU is used or not.
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
This core does not support an FPU at all
|
This core does not support an FPU at all
|
||||||
|
@ -128,7 +80,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
#if defined __ARM_PCS_VFP
|
#if defined __ARM_PCS_VFP
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -143,7 +95,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
#elif defined ( __TI_ARM__ )
|
||||||
#if defined __TI_VFP_SUPPORT__
|
#if defined __TI_VFP_SUPPORT__
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -160,8 +112,8 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
#include "core_cmFunc.h" /* Core Function Access */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -191,7 +143,7 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef __NVIC_PRIO_BITS
|
#ifndef __NVIC_PRIO_BITS
|
||||||
#define __NVIC_PRIO_BITS 4U
|
#define __NVIC_PRIO_BITS 3U
|
||||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -308,9 +260,11 @@ typedef union
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
|
||||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
|
||||||
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
|
uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit */
|
||||||
|
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
|
||||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
@ -336,12 +290,15 @@ typedef union
|
||||||
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
|
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
|
||||||
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
|
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
|
||||||
|
|
||||||
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
|
#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
|
||||||
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
|
#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
|
||||||
|
|
||||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
|
||||||
|
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
|
||||||
|
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
|
||||||
|
|
||||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
@ -487,7 +444,7 @@ typedef struct
|
||||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
/* SCB Vector Table Offset Register Definitions */
|
/* SCB Vector Table Offset Register Definitions */
|
||||||
#if (__CM3_REV < 0x0201U) /* core r2p1 */
|
#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
|
||||||
#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
|
#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
|
||||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||||
|
|
||||||
|
@ -602,6 +559,60 @@ typedef struct
|
||||||
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
||||||
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
||||||
|
|
||||||
|
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
|
||||||
|
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
|
||||||
|
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
|
||||||
|
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
|
||||||
|
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
|
||||||
|
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
|
||||||
|
|
||||||
|
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
|
||||||
|
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
|
||||||
|
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
|
||||||
|
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
|
||||||
|
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
|
||||||
|
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
|
||||||
|
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
|
||||||
|
|
||||||
|
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
|
||||||
|
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
|
||||||
|
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
|
||||||
|
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
|
||||||
|
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
|
||||||
|
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
|
||||||
|
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
|
||||||
|
|
||||||
/* SCB Hard Fault Status Register Definitions */
|
/* SCB Hard Fault Status Register Definitions */
|
||||||
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
|
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
|
||||||
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
||||||
|
@ -645,7 +656,7 @@ typedef struct
|
||||||
{
|
{
|
||||||
uint32_t RESERVED0[1U];
|
uint32_t RESERVED0[1U];
|
||||||
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
|
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
|
||||||
#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
|
#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
|
||||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||||
#else
|
#else
|
||||||
uint32_t RESERVED1[1U];
|
uint32_t RESERVED1[1U];
|
||||||
|
@ -770,7 +781,7 @@ typedef struct
|
||||||
|
|
||||||
/* ITM Trace Privilege Register Definitions */
|
/* ITM Trace Privilege Register Definitions */
|
||||||
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
|
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
|
||||||
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
|
#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
|
||||||
|
|
||||||
/* ITM Trace Control Register Definitions */
|
/* ITM Trace Control Register Definitions */
|
||||||
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
|
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
|
||||||
|
@ -984,7 +995,7 @@ typedef struct
|
||||||
*/
|
*/
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
||||||
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
||||||
uint32_t RESERVED0[2U];
|
uint32_t RESERVED0[2U];
|
||||||
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
||||||
|
@ -995,7 +1006,7 @@ typedef struct
|
||||||
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
||||||
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
||||||
uint32_t RESERVED3[759U];
|
uint32_t RESERVED3[759U];
|
||||||
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
|
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
|
||||||
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
||||||
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
||||||
uint32_t RESERVED4[1U];
|
uint32_t RESERVED4[1U];
|
||||||
|
@ -1065,8 +1076,11 @@ typedef struct
|
||||||
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
||||||
|
|
||||||
/* TPI ITATBCTR2 Register Definitions */
|
/* TPI ITATBCTR2 Register Definitions */
|
||||||
#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
|
#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
|
||||||
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
|
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
|
||||||
|
|
||||||
|
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
|
||||||
|
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
|
||||||
|
|
||||||
/* TPI Integration ITM Data Register Definitions (FIFO1) */
|
/* TPI Integration ITM Data Register Definitions (FIFO1) */
|
||||||
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
|
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
|
||||||
|
@ -1091,12 +1105,15 @@ typedef struct
|
||||||
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
||||||
|
|
||||||
/* TPI ITATBCTR0 Register Definitions */
|
/* TPI ITATBCTR0 Register Definitions */
|
||||||
#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
|
#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
|
||||||
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
|
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
|
||||||
|
|
||||||
|
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
|
||||||
|
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
|
||||||
|
|
||||||
/* TPI Integration Mode Control Register Definitions */
|
/* TPI Integration Mode Control Register Definitions */
|
||||||
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
|
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
|
||||||
#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
||||||
|
|
||||||
/* TPI DEVID Register Definitions */
|
/* TPI DEVID Register Definitions */
|
||||||
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
|
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
|
||||||
|
@ -1118,16 +1135,16 @@ typedef struct
|
||||||
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
||||||
|
|
||||||
/* TPI DEVTYPE Register Definitions */
|
/* TPI DEVTYPE Register Definitions */
|
||||||
#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
|
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
|
||||||
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
|
||||||
|
|
||||||
#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
|
|
||||||
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
||||||
|
|
||||||
|
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
|
||||||
|
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
||||||
|
|
||||||
/*@}*/ /* end of group CMSIS_TPI */
|
/*@}*/ /* end of group CMSIS_TPI */
|
||||||
|
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
/**
|
/**
|
||||||
\ingroup CMSIS_core_register
|
\ingroup CMSIS_core_register
|
||||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||||
|
@ -1153,6 +1170,8 @@ typedef struct
|
||||||
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
|
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
|
||||||
} MPU_Type;
|
} MPU_Type;
|
||||||
|
|
||||||
|
#define MPU_TYPE_RALIASES 4U
|
||||||
|
|
||||||
/* MPU Type Register Definitions */
|
/* MPU Type Register Definitions */
|
||||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||||
|
@ -1337,18 +1356,18 @@ typedef struct
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a bit field value for use in a register bit range.
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of the bit field.
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted value.
|
\return Masked and shifted value.
|
||||||
*/
|
*/
|
||||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a register value to extract a bit filed value.
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of register.
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted bit field value.
|
\return Masked and shifted bit field value.
|
||||||
*/
|
*/
|
||||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
/*@} end of group CMSIS_core_bitfield */
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
@ -1360,7 +1379,7 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Memory mapping of Cortex-M3 Hardware */
|
/* Memory mapping of Core Hardware */
|
||||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
||||||
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
||||||
|
@ -1379,7 +1398,7 @@ typedef struct
|
||||||
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
||||||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||||
#endif
|
#endif
|
||||||
|
@ -1410,6 +1429,45 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
#define NVIC_GetActive __NVIC_GetActive
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Priority Grouping
|
\brief Set Priority Grouping
|
||||||
\details Sets the priority grouping field using the required unlock sequence.
|
\details Sets the priority grouping field using the required unlock sequence.
|
||||||
|
@ -1419,7 +1477,7 @@ typedef struct
|
||||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
\param [in] PriorityGroup Priority grouping field.
|
\param [in] PriorityGroup Priority grouping field.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
{
|
{
|
||||||
uint32_t reg_value;
|
uint32_t reg_value;
|
||||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
@ -1428,7 +1486,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
||||||
reg_value = (reg_value |
|
reg_value = (reg_value |
|
||||||
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
||||||
SCB->AIRCR = reg_value;
|
SCB->AIRCR = reg_value;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1438,121 +1496,178 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
||||||
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
||||||
{
|
{
|
||||||
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable External Interrupt
|
\brief Enable Interrupt
|
||||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Disable External Interrupt
|
\brief Get Interrupt Enable status
|
||||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Pending Interrupt
|
\brief Get Pending Interrupt
|
||||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not pending.
|
\return 0 Interrupt status is not pending.
|
||||||
\return 1 Interrupt status is pending.
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Pending Interrupt
|
\brief Set Pending Interrupt
|
||||||
\details Sets the pending bit of an external interrupt.
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Clear Pending Interrupt
|
\brief Clear Pending Interrupt
|
||||||
\details Clears the pending bit of an external interrupt.
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Active Interrupt
|
\brief Get Active Interrupt
|
||||||
\details Reads the active register in NVIC and returns the active bit.
|
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not active.
|
\return 0 Interrupt status is not active.
|
||||||
\return 1 Interrupt status is active.
|
\return 1 Interrupt status is active.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Interrupt Priority
|
\brief Set Interrupt Priority
|
||||||
\details Sets the priority of an interrupt.
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
\note The priority cannot be set for every core interrupt.
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\param [in] priority Priority to set.
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
{
|
{
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Interrupt Priority
|
\brief Get Interrupt Priority
|
||||||
\details Reads the priority of an interrupt.
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
or negative to specify an internal (core) interrupt.
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\return Interrupt Priority.
|
\return Interrupt Priority.
|
||||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
|
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1609,11 +1724,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
VTOR must been relocated to SRAM before.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Reset
|
\brief System Reset
|
||||||
\details Initiates a system reset request to reset the MCU.
|
\details Initiates a system reset request to reset the MCU.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
{
|
{
|
||||||
__DSB(); /* Ensure all outstanding memory accesses included
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
buffered write are completed before reset */
|
buffered write are completed before reset */
|
||||||
|
@ -1630,6 +1776,38 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_NVICFunctions */
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
/* ########################## MPU functions #################################### */
|
||||||
|
|
||||||
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
|
|
||||||
|
#include "mpu_armv7.h"
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ################################## SysTick function ############################################ */
|
/* ################################## SysTick function ############################################ */
|
||||||
|
@ -1640,7 +1818,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__Vendor_SysTickConfig == 0U)
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Tick Configuration
|
\brief System Tick Configuration
|
||||||
|
@ -1683,8 +1861,8 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
||||||
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,40 +1,30 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_cm4.h
|
* @file core_cm4.h
|
||||||
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
|
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
|
||||||
* @version V4.30
|
* @version V5.0.8
|
||||||
* @date 20. October 2015
|
* @date 04. June 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -70,60 +60,22 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* CMSIS CM4 definitions */
|
#include "cmsis_version.h"
|
||||||
#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
|
||||||
#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
/* CMSIS CM4 definitions */
|
||||||
|
#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
|
#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
|
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
__CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
__CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
#define __CORTEX_M (0x04U) /*!< Cortex-M Core */
|
#define __CORTEX_M (4U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#define __packed
|
|
||||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error Unknown compiler
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** __FPU_USED indicates whether an FPU is used or not.
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
|
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
|
||||||
*/
|
*/
|
||||||
#if defined ( __CC_ARM )
|
#if defined ( __CC_ARM )
|
||||||
#if defined __TARGET_FPU_VFP
|
#if defined __TARGET_FPU_VFP
|
||||||
#if (__FPU_PRESENT == 1U)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -133,9 +85,9 @@
|
||||||
#define __FPU_USED 0U
|
#define __FPU_USED 0U
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
#if defined __ARM_PCS_VFP
|
#if defined __ARM_PCS_VFP
|
||||||
#if (__FPU_PRESENT == 1)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -147,7 +99,7 @@
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
#elif defined ( __GNUC__ )
|
||||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||||
#if (__FPU_PRESENT == 1U)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -159,7 +111,7 @@
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
#elif defined ( __ICCARM__ )
|
||||||
#if defined __ARMVFP__
|
#if defined __ARMVFP__
|
||||||
#if (__FPU_PRESENT == 1U)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -169,9 +121,9 @@
|
||||||
#define __FPU_USED 0U
|
#define __FPU_USED 0U
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
#elif defined ( __TI_ARM__ )
|
||||||
#if defined __TI_VFP_SUPPORT__
|
#if defined __TI_VFP_SUPPORT__
|
||||||
#if (__FPU_PRESENT == 1U)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -183,7 +135,7 @@
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
#elif defined ( __TASKING__ )
|
||||||
#if defined __FPU_VFP__
|
#if defined __FPU_VFP__
|
||||||
#if (__FPU_PRESENT == 1U)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -195,7 +147,7 @@
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
#elif defined ( __CSMC__ )
|
||||||
#if ( __CSMC__ & 0x400U)
|
#if ( __CSMC__ & 0x400U)
|
||||||
#if (__FPU_PRESENT == 1U)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -207,9 +159,8 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
#include "core_cmFunc.h" /* Core Function Access */
|
|
||||||
#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -244,7 +195,7 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef __NVIC_PRIO_BITS
|
#ifndef __NVIC_PRIO_BITS
|
||||||
#define __NVIC_PRIO_BITS 4U
|
#define __NVIC_PRIO_BITS 3U
|
||||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -367,11 +318,12 @@ typedef union
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
|
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
|
||||||
|
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
|
||||||
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||||
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
|
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
|
||||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
uint32_t T:1; /*!< bit: 24 Thumb bit */
|
||||||
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
|
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
|
||||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
@ -397,8 +349,8 @@ typedef union
|
||||||
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
|
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
|
||||||
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
|
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
|
||||||
|
|
||||||
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
|
#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
|
||||||
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
|
#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
|
||||||
|
|
||||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
@ -406,6 +358,9 @@ typedef union
|
||||||
#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
|
#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
|
||||||
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
|
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
|
||||||
|
|
||||||
|
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
|
||||||
|
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
|
||||||
|
|
||||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
@ -662,6 +617,66 @@ typedef struct
|
||||||
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
||||||
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
||||||
|
|
||||||
|
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
|
||||||
|
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
|
||||||
|
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
|
||||||
|
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
|
||||||
|
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
|
||||||
|
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
|
||||||
|
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
|
||||||
|
|
||||||
|
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
|
||||||
|
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
|
||||||
|
#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
|
||||||
|
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
|
||||||
|
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
|
||||||
|
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
|
||||||
|
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
|
||||||
|
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
|
||||||
|
|
||||||
|
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
|
||||||
|
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
|
||||||
|
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
|
||||||
|
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
|
||||||
|
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
|
||||||
|
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
|
||||||
|
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
|
||||||
|
|
||||||
/* SCB Hard Fault Status Register Definitions */
|
/* SCB Hard Fault Status Register Definitions */
|
||||||
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
|
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
|
||||||
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
||||||
|
@ -831,7 +846,7 @@ typedef struct
|
||||||
|
|
||||||
/* ITM Trace Privilege Register Definitions */
|
/* ITM Trace Privilege Register Definitions */
|
||||||
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
|
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
|
||||||
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
|
#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
|
||||||
|
|
||||||
/* ITM Trace Control Register Definitions */
|
/* ITM Trace Control Register Definitions */
|
||||||
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
|
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
|
||||||
|
@ -1045,7 +1060,7 @@ typedef struct
|
||||||
*/
|
*/
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
||||||
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
||||||
uint32_t RESERVED0[2U];
|
uint32_t RESERVED0[2U];
|
||||||
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
||||||
|
@ -1056,7 +1071,7 @@ typedef struct
|
||||||
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
||||||
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
||||||
uint32_t RESERVED3[759U];
|
uint32_t RESERVED3[759U];
|
||||||
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
|
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
|
||||||
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
||||||
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
||||||
uint32_t RESERVED4[1U];
|
uint32_t RESERVED4[1U];
|
||||||
|
@ -1126,8 +1141,11 @@ typedef struct
|
||||||
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
||||||
|
|
||||||
/* TPI ITATBCTR2 Register Definitions */
|
/* TPI ITATBCTR2 Register Definitions */
|
||||||
#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
|
#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
|
||||||
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
|
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
|
||||||
|
|
||||||
|
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
|
||||||
|
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
|
||||||
|
|
||||||
/* TPI Integration ITM Data Register Definitions (FIFO1) */
|
/* TPI Integration ITM Data Register Definitions (FIFO1) */
|
||||||
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
|
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
|
||||||
|
@ -1152,12 +1170,15 @@ typedef struct
|
||||||
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
||||||
|
|
||||||
/* TPI ITATBCTR0 Register Definitions */
|
/* TPI ITATBCTR0 Register Definitions */
|
||||||
#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
|
#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
|
||||||
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
|
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
|
||||||
|
|
||||||
|
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
|
||||||
|
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
|
||||||
|
|
||||||
/* TPI Integration Mode Control Register Definitions */
|
/* TPI Integration Mode Control Register Definitions */
|
||||||
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
|
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
|
||||||
#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
||||||
|
|
||||||
/* TPI DEVID Register Definitions */
|
/* TPI DEVID Register Definitions */
|
||||||
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
|
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
|
||||||
|
@ -1179,16 +1200,16 @@ typedef struct
|
||||||
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
||||||
|
|
||||||
/* TPI DEVTYPE Register Definitions */
|
/* TPI DEVTYPE Register Definitions */
|
||||||
#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
|
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
|
||||||
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
|
||||||
|
|
||||||
#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
|
|
||||||
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
||||||
|
|
||||||
|
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
|
||||||
|
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
||||||
|
|
||||||
/*@}*/ /* end of group CMSIS_TPI */
|
/*@}*/ /* end of group CMSIS_TPI */
|
||||||
|
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
/**
|
/**
|
||||||
\ingroup CMSIS_core_register
|
\ingroup CMSIS_core_register
|
||||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||||
|
@ -1214,6 +1235,8 @@ typedef struct
|
||||||
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
|
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
|
||||||
} MPU_Type;
|
} MPU_Type;
|
||||||
|
|
||||||
|
#define MPU_TYPE_RALIASES 4U
|
||||||
|
|
||||||
/* MPU Type Register Definitions */
|
/* MPU Type Register Definitions */
|
||||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||||
|
@ -1280,10 +1303,9 @@ typedef struct
|
||||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
||||||
|
|
||||||
/*@} end of group CMSIS_MPU */
|
/*@} end of group CMSIS_MPU */
|
||||||
#endif
|
#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
|
||||||
|
|
||||||
|
|
||||||
#if (__FPU_PRESENT == 1U)
|
|
||||||
/**
|
/**
|
||||||
\ingroup CMSIS_core_register
|
\ingroup CMSIS_core_register
|
||||||
\defgroup CMSIS_FPU Floating Point Unit (FPU)
|
\defgroup CMSIS_FPU Floating Point Unit (FPU)
|
||||||
|
@ -1388,7 +1410,6 @@ typedef struct
|
||||||
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
|
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
|
||||||
|
|
||||||
/*@} end of group CMSIS_FPU */
|
/*@} end of group CMSIS_FPU */
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1506,18 +1527,18 @@ typedef struct
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a bit field value for use in a register bit range.
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of the bit field.
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted value.
|
\return Masked and shifted value.
|
||||||
*/
|
*/
|
||||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a register value to extract a bit filed value.
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of register.
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted bit field value.
|
\return Masked and shifted bit field value.
|
||||||
*/
|
*/
|
||||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
/*@} end of group CMSIS_core_bitfield */
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
@ -1529,7 +1550,7 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Memory mapping of Cortex-M4 Hardware */
|
/* Memory mapping of Core Hardware */
|
||||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
||||||
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
||||||
|
@ -1548,15 +1569,13 @@ typedef struct
|
||||||
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
||||||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if (__FPU_PRESENT == 1U)
|
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
|
||||||
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
|
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
|
||||||
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*@} */
|
/*@} */
|
||||||
|
|
||||||
|
@ -1584,6 +1603,48 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
#define NVIC_GetActive __NVIC_GetActive
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
|
||||||
|
#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
|
||||||
|
#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Priority Grouping
|
\brief Set Priority Grouping
|
||||||
\details Sets the priority grouping field using the required unlock sequence.
|
\details Sets the priority grouping field using the required unlock sequence.
|
||||||
|
@ -1593,7 +1654,7 @@ typedef struct
|
||||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
\param [in] PriorityGroup Priority grouping field.
|
\param [in] PriorityGroup Priority grouping field.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
{
|
{
|
||||||
uint32_t reg_value;
|
uint32_t reg_value;
|
||||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
@ -1602,7 +1663,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
||||||
reg_value = (reg_value |
|
reg_value = (reg_value |
|
||||||
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
||||||
SCB->AIRCR = reg_value;
|
SCB->AIRCR = reg_value;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1612,121 +1673,178 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
||||||
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
||||||
{
|
{
|
||||||
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable External Interrupt
|
\brief Enable Interrupt
|
||||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Disable External Interrupt
|
\brief Get Interrupt Enable status
|
||||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Pending Interrupt
|
\brief Get Pending Interrupt
|
||||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not pending.
|
\return 0 Interrupt status is not pending.
|
||||||
\return 1 Interrupt status is pending.
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Pending Interrupt
|
\brief Set Pending Interrupt
|
||||||
\details Sets the pending bit of an external interrupt.
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Clear Pending Interrupt
|
\brief Clear Pending Interrupt
|
||||||
\details Clears the pending bit of an external interrupt.
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Active Interrupt
|
\brief Get Active Interrupt
|
||||||
\details Reads the active register in NVIC and returns the active bit.
|
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not active.
|
\return 0 Interrupt status is not active.
|
||||||
\return 1 Interrupt status is active.
|
\return 1 Interrupt status is active.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Interrupt Priority
|
\brief Set Interrupt Priority
|
||||||
\details Sets the priority of an interrupt.
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
\note The priority cannot be set for every core interrupt.
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\param [in] priority Priority to set.
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
{
|
{
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Interrupt Priority
|
\brief Get Interrupt Priority
|
||||||
\details Reads the priority of an interrupt.
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
or negative to specify an internal (core) interrupt.
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\return Interrupt Priority.
|
\return Interrupt Priority.
|
||||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
|
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1783,11 +1901,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
VTOR must been relocated to SRAM before.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Reset
|
\brief System Reset
|
||||||
\details Initiates a system reset request to reset the MCU.
|
\details Initiates a system reset request to reset the MCU.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
{
|
{
|
||||||
__DSB(); /* Ensure all outstanding memory accesses included
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
buffered write are completed before reset */
|
buffered write are completed before reset */
|
||||||
|
@ -1804,6 +1953,49 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_NVICFunctions */
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
/* ########################## MPU functions #################################### */
|
||||||
|
|
||||||
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
|
|
||||||
|
#include "mpu_armv7.h"
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
uint32_t mvfr0;
|
||||||
|
|
||||||
|
mvfr0 = FPU->MVFR0;
|
||||||
|
if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
|
||||||
|
{
|
||||||
|
return 1U; /* Single precision FPU */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ################################## SysTick function ############################################ */
|
/* ################################## SysTick function ############################################ */
|
||||||
|
@ -1814,7 +2006,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__Vendor_SysTickConfig == 0U)
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Tick Configuration
|
\brief System Tick Configuration
|
||||||
|
@ -1857,8 +2049,8 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
||||||
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,87 +0,0 @@
|
||||||
/**************************************************************************//**
|
|
||||||
* @file core_cmFunc.h
|
|
||||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
|
||||||
* @version V4.30
|
|
||||||
* @date 20. October 2015
|
|
||||||
******************************************************************************/
|
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
|
||||||
|
|
||||||
All rights reserved.
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
- Redistributions of source code must retain the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer.
|
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
|
||||||
to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
*
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#pragma clang system_header /* treat file as system include file */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef __CORE_CMFUNC_H
|
|
||||||
#define __CORE_CMFUNC_H
|
|
||||||
|
|
||||||
|
|
||||||
/* ########################### Core Function Access ########################### */
|
|
||||||
/** \ingroup CMSIS_Core_FunctionInterface
|
|
||||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
|
||||||
@{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*------------------ RealView Compiler -----------------*/
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#include "cmsis_armcc.h"
|
|
||||||
|
|
||||||
/*------------------ ARM Compiler V6 -------------------*/
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#include "cmsis_armcc_V6.h"
|
|
||||||
|
|
||||||
/*------------------ GNU Compiler ----------------------*/
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#include "cmsis_gcc.h"
|
|
||||||
|
|
||||||
/*------------------ ICC Compiler ----------------------*/
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#include <cmsis_iar.h>
|
|
||||||
|
|
||||||
/*------------------ TI CCS Compiler -------------------*/
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#include <cmsis_ccs.h>
|
|
||||||
|
|
||||||
/*------------------ TASKING Compiler ------------------*/
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
/*
|
|
||||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
|
||||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
|
||||||
* Including the CMSIS ones.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*------------------ COSMIC Compiler -------------------*/
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#include <cmsis_csm.h>
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
|
||||||
|
|
||||||
#endif /* __CORE_CMFUNC_H */
|
|
|
@ -1,87 +0,0 @@
|
||||||
/**************************************************************************//**
|
|
||||||
* @file core_cmInstr.h
|
|
||||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
|
||||||
* @version V4.30
|
|
||||||
* @date 20. October 2015
|
|
||||||
******************************************************************************/
|
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
|
||||||
|
|
||||||
All rights reserved.
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
- Redistributions of source code must retain the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer.
|
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
|
||||||
to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
*
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#pragma clang system_header /* treat file as system include file */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef __CORE_CMINSTR_H
|
|
||||||
#define __CORE_CMINSTR_H
|
|
||||||
|
|
||||||
|
|
||||||
/* ########################## Core Instruction Access ######################### */
|
|
||||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
|
||||||
Access to dedicated instructions
|
|
||||||
@{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*------------------ RealView Compiler -----------------*/
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#include "cmsis_armcc.h"
|
|
||||||
|
|
||||||
/*------------------ ARM Compiler V6 -------------------*/
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#include "cmsis_armcc_V6.h"
|
|
||||||
|
|
||||||
/*------------------ GNU Compiler ----------------------*/
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#include "cmsis_gcc.h"
|
|
||||||
|
|
||||||
/*------------------ ICC Compiler ----------------------*/
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#include <cmsis_iar.h>
|
|
||||||
|
|
||||||
/*------------------ TI CCS Compiler -------------------*/
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#include <cmsis_ccs.h>
|
|
||||||
|
|
||||||
/*------------------ TASKING Compiler ------------------*/
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
/*
|
|
||||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
|
||||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
|
||||||
* Including the CMSIS ones.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*------------------ COSMIC Compiler -------------------*/
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#include <cmsis_csm.h>
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
|
||||||
|
|
||||||
#endif /* __CORE_CMINSTR_H */
|
|
|
@ -1,96 +0,0 @@
|
||||||
/**************************************************************************//**
|
|
||||||
* @file core_cmSimd.h
|
|
||||||
* @brief CMSIS Cortex-M SIMD Header File
|
|
||||||
* @version V4.30
|
|
||||||
* @date 20. October 2015
|
|
||||||
******************************************************************************/
|
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
|
||||||
|
|
||||||
All rights reserved.
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
- Redistributions of source code must retain the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer.
|
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
|
||||||
to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
*
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#pragma clang system_header /* treat file as system include file */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef __CORE_CMSIMD_H
|
|
||||||
#define __CORE_CMSIMD_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/* ################### Compiler specific Intrinsics ########################### */
|
|
||||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
|
||||||
Access to dedicated SIMD instructions
|
|
||||||
@{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*------------------ RealView Compiler -----------------*/
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#include "cmsis_armcc.h"
|
|
||||||
|
|
||||||
/*------------------ ARM Compiler V6 -------------------*/
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#include "cmsis_armcc_V6.h"
|
|
||||||
|
|
||||||
/*------------------ GNU Compiler ----------------------*/
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#include "cmsis_gcc.h"
|
|
||||||
|
|
||||||
/*------------------ ICC Compiler ----------------------*/
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#include <cmsis_iar.h>
|
|
||||||
|
|
||||||
/*------------------ TI CCS Compiler -------------------*/
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#include <cmsis_ccs.h>
|
|
||||||
|
|
||||||
/*------------------ TASKING Compiler ------------------*/
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
/*
|
|
||||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
|
||||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
|
||||||
* Including the CMSIS ones.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*------------------ COSMIC Compiler -------------------*/
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#include <cmsis_csm.h>
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __CORE_CMSIMD_H */
|
|
|
@ -1,40 +1,30 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_sc000.h
|
* @file core_sc000.h
|
||||||
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
|
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
|
||||||
* @version V4.30
|
* @version V5.0.5
|
||||||
* @date 20. October 2015
|
* @date 28. May 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -70,53 +60,15 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
/* CMSIS SC000 definitions */
|
/* CMSIS SC000 definitions */
|
||||||
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
|
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
__SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
#define __CORTEX_SC (000U) /*!< Cortex secure core */
|
#define __CORTEX_SC (000U) /*!< Cortex secure core */
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#define __packed
|
|
||||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error Unknown compiler
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** __FPU_USED indicates whether an FPU is used or not.
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
This core does not support an FPU at all
|
This core does not support an FPU at all
|
||||||
|
@ -128,7 +80,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
#if defined __ARM_PCS_VFP
|
#if defined __ARM_PCS_VFP
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -143,7 +95,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
#elif defined ( __TI_ARM__ )
|
||||||
#if defined __TI_VFP_SUPPORT__
|
#if defined __TI_VFP_SUPPORT__
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -160,8 +112,8 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
#include "core_cmFunc.h" /* Core Function Access */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -569,7 +521,7 @@ typedef struct
|
||||||
|
|
||||||
/*@} end of group CMSIS_SysTick */
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
/**
|
/**
|
||||||
\ingroup CMSIS_core_register
|
\ingroup CMSIS_core_register
|
||||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||||
|
@ -678,18 +630,18 @@ typedef struct
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a bit field value for use in a register bit range.
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of the bit field.
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted value.
|
\return Masked and shifted value.
|
||||||
*/
|
*/
|
||||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a register value to extract a bit filed value.
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of register.
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted bit field value.
|
\return Masked and shifted bit field value.
|
||||||
*/
|
*/
|
||||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
/*@} end of group CMSIS_core_bitfield */
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
@ -701,7 +653,7 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Memory mapping of SC000 Hardware */
|
/* Memory mapping of Core Hardware */
|
||||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
@ -712,7 +664,7 @@ typedef struct
|
||||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||||
#endif
|
#endif
|
||||||
|
@ -742,7 +694,46 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
|
||||||
|
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
/* The following MACROS handle generation of the register offset and byte masks */
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
|
@ -750,79 +741,128 @@ typedef struct
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable External Interrupt
|
\brief Enable Interrupt
|
||||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Disable External Interrupt
|
\brief Get Interrupt Enable status
|
||||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Pending Interrupt
|
\brief Get Pending Interrupt
|
||||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not pending.
|
\return 0 Interrupt status is not pending.
|
||||||
\return 1 Interrupt status is pending.
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Pending Interrupt
|
\brief Set Pending Interrupt
|
||||||
\details Sets the pending bit of an external interrupt.
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Clear Pending Interrupt
|
\brief Clear Pending Interrupt
|
||||||
\details Clears the pending bit of an external interrupt.
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Interrupt Priority
|
\brief Set Interrupt Priority
|
||||||
\details Sets the priority of an interrupt.
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
\note The priority cannot be set for every core interrupt.
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\param [in] priority Priority to set.
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
{
|
{
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -830,24 +870,55 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Interrupt Priority
|
\brief Get Interrupt Priority
|
||||||
\details Reads the priority of an interrupt.
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
or negative to specify an internal (core) interrupt.
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\return Interrupt Priority.
|
\return Interrupt Priority.
|
||||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
|
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
|
||||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
VTOR must been relocated to SRAM before.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -855,7 +926,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
\brief System Reset
|
\brief System Reset
|
||||||
\details Initiates a system reset request to reset the MCU.
|
\details Initiates a system reset request to reset the MCU.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
{
|
{
|
||||||
__DSB(); /* Ensure all outstanding memory accesses included
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
buffered write are completed before reset */
|
buffered write are completed before reset */
|
||||||
|
@ -872,6 +943,31 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
/*@} end of CMSIS_Core_NVICFunctions */
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ################################## SysTick function ############################################ */
|
/* ################################## SysTick function ############################################ */
|
||||||
/**
|
/**
|
||||||
|
@ -881,7 +977,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__Vendor_SysTickConfig == 0U)
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Tick Configuration
|
\brief System Tick Configuration
|
||||||
|
|
|
@ -1,40 +1,30 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_sc300.h
|
* @file core_sc300.h
|
||||||
* @brief CMSIS SC300 Core Peripheral Access Layer Header File
|
* @brief CMSIS SC300 Core Peripheral Access Layer Header File
|
||||||
* @version V4.30
|
* @version V5.0.6
|
||||||
* @date 20. October 2015
|
* @date 04. June 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -70,53 +60,15 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
/* CMSIS SC300 definitions */
|
/* CMSIS SC300 definitions */
|
||||||
#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
|
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
__SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
__SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
#define __CORTEX_SC (300U) /*!< Cortex secure core */
|
#define __CORTEX_SC (300U) /*!< Cortex secure core */
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#define __packed
|
|
||||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error Unknown compiler
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** __FPU_USED indicates whether an FPU is used or not.
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
This core does not support an FPU at all
|
This core does not support an FPU at all
|
||||||
|
@ -128,7 +80,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
#if defined __ARM_PCS_VFP
|
#if defined __ARM_PCS_VFP
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -143,7 +95,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
#elif defined ( __TI_ARM__ )
|
||||||
#if defined __TI_VFP_SUPPORT__
|
#if defined __TI_VFP_SUPPORT__
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -160,8 +112,8 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
#include "core_cmFunc.h" /* Core Function Access */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -191,7 +143,7 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef __NVIC_PRIO_BITS
|
#ifndef __NVIC_PRIO_BITS
|
||||||
#define __NVIC_PRIO_BITS 4U
|
#define __NVIC_PRIO_BITS 3U
|
||||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -308,9 +260,11 @@ typedef union
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
|
||||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
|
||||||
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
|
uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit */
|
||||||
|
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
|
||||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
@ -336,12 +290,15 @@ typedef union
|
||||||
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
|
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
|
||||||
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
|
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
|
||||||
|
|
||||||
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
|
#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
|
||||||
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
|
#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
|
||||||
|
|
||||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
|
||||||
|
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
|
||||||
|
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
|
||||||
|
|
||||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
@ -599,6 +556,60 @@ typedef struct
|
||||||
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
||||||
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
||||||
|
|
||||||
|
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
|
||||||
|
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
|
||||||
|
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
|
||||||
|
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
|
||||||
|
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
|
||||||
|
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
|
||||||
|
|
||||||
|
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
|
||||||
|
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
|
||||||
|
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
|
||||||
|
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
|
||||||
|
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
|
||||||
|
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
|
||||||
|
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
|
||||||
|
|
||||||
|
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
|
||||||
|
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
|
||||||
|
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
|
||||||
|
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
|
||||||
|
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
|
||||||
|
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
|
||||||
|
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
|
||||||
|
|
||||||
/* SCB Hard Fault Status Register Definitions */
|
/* SCB Hard Fault Status Register Definitions */
|
||||||
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
|
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
|
||||||
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
||||||
|
@ -966,7 +977,7 @@ typedef struct
|
||||||
*/
|
*/
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
||||||
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
||||||
uint32_t RESERVED0[2U];
|
uint32_t RESERVED0[2U];
|
||||||
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
||||||
|
@ -977,7 +988,7 @@ typedef struct
|
||||||
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
||||||
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
||||||
uint32_t RESERVED3[759U];
|
uint32_t RESERVED3[759U];
|
||||||
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
|
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
|
||||||
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
||||||
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
||||||
uint32_t RESERVED4[1U];
|
uint32_t RESERVED4[1U];
|
||||||
|
@ -1047,8 +1058,11 @@ typedef struct
|
||||||
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
||||||
|
|
||||||
/* TPI ITATBCTR2 Register Definitions */
|
/* TPI ITATBCTR2 Register Definitions */
|
||||||
#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
|
#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
|
||||||
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
|
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
|
||||||
|
|
||||||
|
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
|
||||||
|
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
|
||||||
|
|
||||||
/* TPI Integration ITM Data Register Definitions (FIFO1) */
|
/* TPI Integration ITM Data Register Definitions (FIFO1) */
|
||||||
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
|
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
|
||||||
|
@ -1073,12 +1087,15 @@ typedef struct
|
||||||
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
||||||
|
|
||||||
/* TPI ITATBCTR0 Register Definitions */
|
/* TPI ITATBCTR0 Register Definitions */
|
||||||
#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
|
#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
|
||||||
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
|
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
|
||||||
|
|
||||||
|
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
|
||||||
|
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
|
||||||
|
|
||||||
/* TPI Integration Mode Control Register Definitions */
|
/* TPI Integration Mode Control Register Definitions */
|
||||||
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
|
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
|
||||||
#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
||||||
|
|
||||||
/* TPI DEVID Register Definitions */
|
/* TPI DEVID Register Definitions */
|
||||||
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
|
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
|
||||||
|
@ -1100,16 +1117,16 @@ typedef struct
|
||||||
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
||||||
|
|
||||||
/* TPI DEVTYPE Register Definitions */
|
/* TPI DEVTYPE Register Definitions */
|
||||||
#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
|
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
|
||||||
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
|
||||||
|
|
||||||
#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
|
|
||||||
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
||||||
|
|
||||||
|
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
|
||||||
|
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
||||||
|
|
||||||
/*@}*/ /* end of group CMSIS_TPI */
|
/*@}*/ /* end of group CMSIS_TPI */
|
||||||
|
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
/**
|
/**
|
||||||
\ingroup CMSIS_core_register
|
\ingroup CMSIS_core_register
|
||||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||||
|
@ -1319,18 +1336,18 @@ typedef struct
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a bit field value for use in a register bit range.
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of the bit field.
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted value.
|
\return Masked and shifted value.
|
||||||
*/
|
*/
|
||||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a register value to extract a bit filed value.
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of register.
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted bit field value.
|
\return Masked and shifted bit field value.
|
||||||
*/
|
*/
|
||||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
/*@} end of group CMSIS_core_bitfield */
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
@ -1342,7 +1359,7 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Memory mapping of Cortex-M3 Hardware */
|
/* Memory mapping of Core Hardware */
|
||||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
||||||
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
||||||
|
@ -1361,7 +1378,7 @@ typedef struct
|
||||||
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
||||||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||||
#endif
|
#endif
|
||||||
|
@ -1392,6 +1409,46 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
#define NVIC_GetActive __NVIC_GetActive
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Priority Grouping
|
\brief Set Priority Grouping
|
||||||
\details Sets the priority grouping field using the required unlock sequence.
|
\details Sets the priority grouping field using the required unlock sequence.
|
||||||
|
@ -1401,7 +1458,7 @@ typedef struct
|
||||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
\param [in] PriorityGroup Priority grouping field.
|
\param [in] PriorityGroup Priority grouping field.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
{
|
{
|
||||||
uint32_t reg_value;
|
uint32_t reg_value;
|
||||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
@ -1420,121 +1477,178 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
||||||
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
||||||
{
|
{
|
||||||
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable External Interrupt
|
\brief Enable Interrupt
|
||||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Disable External Interrupt
|
\brief Get Interrupt Enable status
|
||||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Pending Interrupt
|
\brief Get Pending Interrupt
|
||||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not pending.
|
\return 0 Interrupt status is not pending.
|
||||||
\return 1 Interrupt status is pending.
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Pending Interrupt
|
\brief Set Pending Interrupt
|
||||||
\details Sets the pending bit of an external interrupt.
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Clear Pending Interrupt
|
\brief Clear Pending Interrupt
|
||||||
\details Clears the pending bit of an external interrupt.
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Active Interrupt
|
\brief Get Active Interrupt
|
||||||
\details Reads the active register in NVIC and returns the active bit.
|
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not active.
|
\return 0 Interrupt status is not active.
|
||||||
\return 1 Interrupt status is active.
|
\return 1 Interrupt status is active.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Interrupt Priority
|
\brief Set Interrupt Priority
|
||||||
\details Sets the priority of an interrupt.
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
\note The priority cannot be set for every core interrupt.
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\param [in] priority Priority to set.
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
{
|
{
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Interrupt Priority
|
\brief Get Interrupt Priority
|
||||||
\details Reads the priority of an interrupt.
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
or negative to specify an internal (core) interrupt.
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\return Interrupt Priority.
|
\return Interrupt Priority.
|
||||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
|
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1591,11 +1705,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
VTOR must been relocated to SRAM before.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Reset
|
\brief System Reset
|
||||||
\details Initiates a system reset request to reset the MCU.
|
\details Initiates a system reset request to reset the MCU.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
{
|
{
|
||||||
__DSB(); /* Ensure all outstanding memory accesses included
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
buffered write are completed before reset */
|
buffered write are completed before reset */
|
||||||
|
@ -1613,6 +1758,31 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
/*@} end of CMSIS_Core_NVICFunctions */
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ################################## SysTick function ############################################ */
|
/* ################################## SysTick function ############################################ */
|
||||||
/**
|
/**
|
||||||
|
@ -1622,7 +1792,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__Vendor_SysTickConfig == 0U)
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Tick Configuration
|
\brief System Tick Configuration
|
||||||
|
@ -1665,8 +1835,8 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
||||||
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -0,0 +1,270 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file mpu_armv7.h
|
||||||
|
* @brief CMSIS MPU API for Armv7-M MPU
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_MPU_ARMV7_H
|
||||||
|
#define ARM_MPU_ARMV7_H
|
||||||
|
|
||||||
|
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||||
|
|
||||||
|
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||||
|
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||||
|
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||||
|
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||||
|
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||||
|
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||||
|
|
||||||
|
/** MPU Region Base Address Register Value
|
||||||
|
*
|
||||||
|
* \param Region The region to be configured, number 0 to 15.
|
||||||
|
* \param BaseAddress The base address for the region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||||
|
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||||
|
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||||
|
(MPU_RBAR_VALID_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attributes
|
||||||
|
*
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||||
|
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||||
|
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||||
|
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||||
|
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||||
|
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||||
|
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||||
|
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||||
|
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for strongly ordered memory.
|
||||||
|
* - TEX: 000b
|
||||||
|
* - Shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Non-bufferable
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for device memory.
|
||||||
|
* - TEX: 000b (if non-shareable) or 010b (if shareable)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||||
|
*
|
||||||
|
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for normal memory.
|
||||||
|
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||||
|
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||||
|
*
|
||||||
|
* \param OuterCp Configures the outer cache policy.
|
||||||
|
* \param InnerCp Configures the inner cache policy.
|
||||||
|
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute non-cacheable policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for a single MPU Region
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||||
|
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||||
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
|
/** Enable the MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RASR = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure an MPU region.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rsar Value for RSAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure the given MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rsar Value for RSAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||||
|
* \param dst Destination data is copied to.
|
||||||
|
* \param src Source data is copied from.
|
||||||
|
* \param len Amount of data words to be copied.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
for (i = 0U; i < len; ++i)
|
||||||
|
{
|
||||||
|
dst[i] = src[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
|
while (cnt > MPU_TYPE_RALIASES) {
|
||||||
|
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||||
|
table += MPU_TYPE_RALIASES;
|
||||||
|
cnt -= MPU_TYPE_RALIASES;
|
||||||
|
}
|
||||||
|
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,333 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file mpu_armv8.h
|
||||||
|
* @brief CMSIS MPU API for Armv8-M MPU
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_MPU_ARMV8_H
|
||||||
|
#define ARM_MPU_ARMV8_H
|
||||||
|
|
||||||
|
/** \brief Attribute for device memory (outer only) */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||||
|
|
||||||
|
/** \brief Attribute for non-cacheable, normal memory */
|
||||||
|
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||||
|
|
||||||
|
/** \brief Attribute for normal memory (outer and inner)
|
||||||
|
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||||
|
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||||
|
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||||
|
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||||
|
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||||
|
|
||||||
|
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||||
|
|
||||||
|
/** \brief Memory Attribute
|
||||||
|
* \param O Outer memory attributes
|
||||||
|
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||||
|
|
||||||
|
/** \brief Normal memory non-shareable */
|
||||||
|
#define ARM_MPU_SH_NON (0U)
|
||||||
|
|
||||||
|
/** \brief Normal memory outer shareable */
|
||||||
|
#define ARM_MPU_SH_OUTER (2U)
|
||||||
|
|
||||||
|
/** \brief Normal memory inner shareable */
|
||||||
|
#define ARM_MPU_SH_INNER (3U)
|
||||||
|
|
||||||
|
/** \brief Memory access permissions
|
||||||
|
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||||
|
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||||
|
|
||||||
|
/** \brief Region Base Address Register value
|
||||||
|
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||||
|
* \param SH Defines the Shareability domain for this memory region.
|
||||||
|
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||||
|
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||||
|
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||||
|
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||||
|
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||||
|
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||||
|
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||||
|
|
||||||
|
/** \brief Region Limit Address Register value
|
||||||
|
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||||
|
* \param IDX The attribute index to be associated with this memory region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||||
|
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||||
|
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||||
|
(MPU_RLAR_EN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for a single MPU Region
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||||
|
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||||
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
|
/** Enable the MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Enable the Non-secure MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the Non-secure MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Set the memory attribute encoding to the given MPU.
|
||||||
|
* \param mpu Pointer to the MPU to be configured.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
const uint8_t reg = idx / 4U;
|
||||||
|
const uint32_t pos = ((idx % 4U) * 8U);
|
||||||
|
const uint32_t mask = 0xFFU << pos;
|
||||||
|
|
||||||
|
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||||
|
return; // invalid index
|
||||||
|
}
|
||||||
|
|
||||||
|
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Set the memory attribute encoding.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region of the given MPU.
|
||||||
|
* \param mpu Pointer to MPU to be used.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||||
|
{
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
mpu->RLAR = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
|
{
|
||||||
|
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Clear and disable the given Non-secure MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||||
|
{
|
||||||
|
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Configure the given MPU region of the given MPU.
|
||||||
|
* \param mpu Pointer to MPU to be used.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
mpu->RBAR = rbar;
|
||||||
|
mpu->RLAR = rlar;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure the given MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Configure the given Non-secure MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||||
|
* \param dst Destination data is copied to.
|
||||||
|
* \param src Source data is copied from.
|
||||||
|
* \param len Amount of data words to be copied.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
for (i = 0U; i < len; ++i)
|
||||||
|
{
|
||||||
|
dst[i] = src[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table to the given MPU.
|
||||||
|
* \param mpu Pointer to the MPU registers to be used.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
|
if (cnt == 1U) {
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||||
|
} else {
|
||||||
|
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||||
|
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||||
|
|
||||||
|
mpu->RNR = rnrBase;
|
||||||
|
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||||
|
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||||
|
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||||
|
table += c;
|
||||||
|
cnt -= c;
|
||||||
|
rnrOffset = 0U;
|
||||||
|
rnrBase += MPU_TYPE_RALIASES;
|
||||||
|
mpu->RNR = rnrBase;
|
||||||
|
}
|
||||||
|
|
||||||
|
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
|
@ -0,0 +1,70 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file tz_context.h
|
||||||
|
* @brief Context Management for Armv8-M TrustZone
|
||||||
|
* @version V1.0.1
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef TZ_CONTEXT_H
|
||||||
|
#define TZ_CONTEXT_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#ifndef TZ_MODULEID_T
|
||||||
|
#define TZ_MODULEID_T
|
||||||
|
/// \details Data type that identifies secure software modules called by a process.
|
||||||
|
typedef uint32_t TZ_ModuleId_t;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||||
|
typedef uint32_t TZ_MemoryId_t;
|
||||||
|
|
||||||
|
/// Initialize secure context memory system
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_InitContextSystem_S (void);
|
||||||
|
|
||||||
|
/// Allocate context memory for calling secure software modules in TrustZone
|
||||||
|
/// \param[in] module identifies software modules called from non-secure mode
|
||||||
|
/// \return value != 0 id TrustZone memory slot identifier
|
||||||
|
/// \return value 0 no memory available or internal error
|
||||||
|
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||||
|
|
||||||
|
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
/// Load secure context (called on RTOS thread context switch)
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
/// Store secure context (called on RTOS thread context switch)
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
#endif // TZ_CONTEXT_H
|
|
@ -7,36 +7,20 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32_HAL_LEGACY
|
#ifndef STM32_HAL_LEGACY
|
||||||
#define __STM32_HAL_LEGACY
|
#define STM32_HAL_LEGACY
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
|
@ -110,6 +94,10 @@
|
||||||
#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
|
#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
|
||||||
#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
|
#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
|
||||||
#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
|
#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
|
||||||
|
#endif /* STM32H7 */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -274,7 +262,100 @@
|
||||||
#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
|
#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
|
||||||
#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
|
#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
|
||||||
|
|
||||||
|
#if defined(STM32L4)
|
||||||
|
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
|
||||||
|
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
||||||
|
|
||||||
|
#endif /* STM32L4 */
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
|
||||||
|
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
|
||||||
|
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
|
||||||
|
|
||||||
|
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
|
||||||
|
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
|
||||||
|
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
|
||||||
|
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
|
||||||
|
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
||||||
|
|
||||||
|
#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
|
||||||
|
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
|
||||||
|
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
|
||||||
|
|
||||||
|
#endif /* STM32H7 */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
@ -355,6 +436,38 @@
|
||||||
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
|
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
|
||||||
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
|
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
|
||||||
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
|
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
|
||||||
|
#if defined(STM32G0)
|
||||||
|
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
|
||||||
|
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
|
||||||
|
#else
|
||||||
|
#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
|
||||||
|
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
|
||||||
|
#endif
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
|
||||||
|
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
|
||||||
|
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
|
||||||
|
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
|
||||||
|
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
|
||||||
|
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
|
||||||
|
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
|
||||||
|
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
|
||||||
|
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
|
||||||
|
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
|
||||||
|
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
|
||||||
|
#endif /* STM32H7 */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
@ -381,12 +494,12 @@
|
||||||
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
|
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
|
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
|
||||||
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
|
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
|
||||||
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
|
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
|
||||||
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
|
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
|
||||||
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
|
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
|
||||||
#else
|
#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
|
||||||
#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
|
#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
|
||||||
#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
|
#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
|
||||||
#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
|
#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
|
||||||
|
@ -427,16 +540,25 @@
|
||||||
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
|
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
|
||||||
|
#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
|
||||||
|
#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
|
||||||
|
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
|
||||||
|
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
|
||||||
|
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
|
||||||
|
#endif
|
||||||
|
|
||||||
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
|
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
|
||||||
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
|
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
|
||||||
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
|
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
|
||||||
|
|
||||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4)
|
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)
|
||||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
||||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
||||||
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
|
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
|
||||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
|
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
|
||||||
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */
|
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/
|
||||||
|
|
||||||
#if defined(STM32L1)
|
#if defined(STM32L1)
|
||||||
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
|
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
|
||||||
|
@ -456,78 +578,6 @@
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(STM32H7)
|
|
||||||
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
|
|
||||||
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
|
|
||||||
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
|
|
||||||
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
|
|
||||||
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
|
|
||||||
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
|
|
||||||
|
|
||||||
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
|
|
||||||
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
|
|
||||||
|
|
||||||
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
|
|
||||||
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
|
|
||||||
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
|
|
||||||
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
|
|
||||||
|
|
||||||
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
|
|
||||||
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
|
|
||||||
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
|
||||||
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* STM32H7 */
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
|
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
@ -696,6 +746,16 @@
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
|
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define I2S_IT_TXE I2S_IT_TXP
|
||||||
|
#define I2S_IT_RXNE I2S_IT_RXP
|
||||||
|
|
||||||
|
#define I2S_FLAG_TXE I2S_FLAG_TXP
|
||||||
|
#define I2S_FLAG_RXNE I2S_FLAG_RXP
|
||||||
|
#define I2S_FLAG_FRE I2S_FLAG_TIFRE
|
||||||
|
#endif
|
||||||
|
|
||||||
#if defined(STM32F7)
|
#if defined(STM32F7)
|
||||||
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
|
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
|
||||||
#endif
|
#endif
|
||||||
|
@ -820,6 +880,21 @@
|
||||||
#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
|
#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
|
||||||
#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
|
#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
|
||||||
|
#define SPI_FLAG_TXE SPI_FLAG_TXP
|
||||||
|
#define SPI_FLAG_RXNE SPI_FLAG_RXP
|
||||||
|
|
||||||
|
#define SPI_IT_TXE SPI_IT_TXP
|
||||||
|
#define SPI_IT_RXNE SPI_IT_RXP
|
||||||
|
|
||||||
|
#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
|
||||||
|
#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
|
||||||
|
#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
|
||||||
|
#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
|
||||||
|
|
||||||
|
#endif /* STM32H7 */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -887,6 +962,15 @@
|
||||||
#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
|
#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
|
||||||
#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
|
#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
|
||||||
|
|
||||||
|
#if defined(STM32L0)
|
||||||
|
#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
|
||||||
|
#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32F3)
|
||||||
|
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
|
||||||
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -1047,8 +1131,9 @@
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
|
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
|
||||||
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
|| defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
|
||||||
|
|| defined(STM32H7)
|
||||||
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
|
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
@ -1072,7 +1157,7 @@
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
#endif /* STM32L4 || STM32F7*/
|
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
|
||||||
|
|
||||||
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
|
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
|
||||||
* @{
|
* @{
|
||||||
|
@ -1164,6 +1249,28 @@
|
||||||
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
|
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
|
||||||
|
|
||||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||||
|
|
||||||
|
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7)
|
||||||
|
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
|
||||||
|
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
|
||||||
|
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
|
||||||
|
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
|
||||||
|
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
|
||||||
|
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
|
||||||
|
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
|
||||||
|
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
|
||||||
|
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 */
|
||||||
|
|
||||||
|
#if defined(STM32F4)
|
||||||
|
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
|
||||||
|
#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
|
||||||
|
#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
|
||||||
|
#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
|
||||||
|
#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
|
||||||
|
#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
|
||||||
|
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
|
||||||
|
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
|
||||||
|
#endif /* STM32F4 */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -1243,6 +1350,14 @@
|
||||||
#define HAL_TIM_DMAError TIM_DMAError
|
#define HAL_TIM_DMAError TIM_DMAError
|
||||||
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
|
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
|
||||||
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
|
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
|
||||||
|
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0)
|
||||||
|
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
|
||||||
|
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
|
||||||
|
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
|
||||||
|
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
|
||||||
|
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
|
||||||
|
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
|
||||||
|
#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -1456,10 +1571,17 @@
|
||||||
#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
|
#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
|
||||||
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
|
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
|
||||||
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
|
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
|
||||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
|
#if defined(STM32H7)
|
||||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
|
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
|
||||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
|
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
|
||||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
|
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
|
||||||
|
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
|
||||||
|
#else
|
||||||
|
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
|
||||||
|
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
|
||||||
|
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
|
||||||
|
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
|
||||||
|
#endif /* STM32H7 */
|
||||||
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
|
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
|
||||||
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
|
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
|
||||||
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
|
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
|
||||||
|
@ -1725,6 +1847,10 @@
|
||||||
#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
|
#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
|
||||||
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
|
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
|
||||||
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -2932,7 +3058,7 @@
|
||||||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#if defined (STM32G0)
|
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
|
||||||
#else
|
#else
|
||||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||||
#endif
|
#endif
|
||||||
|
@ -3064,6 +3190,7 @@
|
||||||
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
|
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
|
||||||
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
|
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
|
||||||
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
|
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
|
||||||
|
#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
|
||||||
#endif
|
#endif
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
@ -3291,6 +3418,21 @@
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (STM32H7) || defined (STM32F3)
|
||||||
|
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
|
||||||
|
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
|
||||||
|
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
|
||||||
|
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
|
||||||
|
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
|
||||||
|
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
|
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
@ -3303,7 +3445,7 @@
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* ___STM32_HAL_LEGACY */
|
#endif /* STM32_HAL_LEGACY */
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
|
|
|
@ -7,29 +7,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -253,7 +237,9 @@ void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||||
void HAL_EnableCompensationCell(void);
|
void HAL_EnableCompensationCell(void);
|
||||||
void HAL_DisableCompensationCell(void);
|
void HAL_DisableCompensationCell(void);
|
||||||
void HAL_GetUID(uint32_t *UID);
|
uint32_t HAL_GetUIDw0(void);
|
||||||
|
uint32_t HAL_GetUIDw1(void);
|
||||||
|
uint32_t HAL_GetUIDw2(void);
|
||||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
|
||||||
defined(STM32F469xx) || defined(STM32F479xx)
|
defined(STM32F469xx) || defined(STM32F479xx)
|
||||||
void HAL_EnableMemorySwappingBank(void);
|
void HAL_EnableMemorySwappingBank(void);
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -151,7 +135,7 @@ typedef struct
|
||||||
This parameter can be a value of @ref CAN_filter_scale */
|
This parameter can be a value of @ref CAN_filter_scale */
|
||||||
|
|
||||||
uint32_t FilterActivation; /*!< Enable or disable the filter.
|
uint32_t FilterActivation; /*!< Enable or disable the filter.
|
||||||
This parameter can be set to ENABLE or DISABLE. */
|
This parameter can be a value of @ref CAN_filter_activation */
|
||||||
|
|
||||||
uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
|
uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
|
||||||
For single CAN instances, this parameter is meaningless.
|
For single CAN instances, this parameter is meaningless.
|
||||||
|
@ -233,8 +217,58 @@ typedef struct __CAN_HandleTypeDef
|
||||||
__IO uint32_t ErrorCode; /*!< CAN Error code.
|
__IO uint32_t ErrorCode; /*!< CAN Error code.
|
||||||
This parameter can be a value of @ref CAN_Error_Code */
|
This parameter can be a value of @ref CAN_Error_Code */
|
||||||
|
|
||||||
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||||
|
void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */
|
||||||
|
void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */
|
||||||
|
void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */
|
||||||
|
void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */
|
||||||
|
void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */
|
||||||
|
void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */
|
||||||
|
void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */
|
||||||
|
void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */
|
||||||
|
void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */
|
||||||
|
void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */
|
||||||
|
void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */
|
||||||
|
void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */
|
||||||
|
void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */
|
||||||
|
|
||||||
|
void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */
|
||||||
|
void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */
|
||||||
|
|
||||||
|
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
|
||||||
} CAN_HandleTypeDef;
|
} CAN_HandleTypeDef;
|
||||||
|
|
||||||
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||||
|
/**
|
||||||
|
* @brief HAL CAN common Callback ID enumeration definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */
|
||||||
|
HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */
|
||||||
|
HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */
|
||||||
|
HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */
|
||||||
|
HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */
|
||||||
|
HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */
|
||||||
|
HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */
|
||||||
|
HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */
|
||||||
|
HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
|
||||||
|
HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
|
||||||
|
HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
|
||||||
|
HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */
|
||||||
|
HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
|
||||||
|
|
||||||
|
HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
|
||||||
|
HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */
|
||||||
|
|
||||||
|
} HAL_CAN_CallbackIDTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL CAN Callback pointer definition
|
||||||
|
*/
|
||||||
|
typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */
|
||||||
|
|
||||||
|
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -272,6 +306,11 @@ typedef struct __CAN_HandleTypeDef
|
||||||
#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
|
#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
|
||||||
#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
|
#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
|
||||||
|
|
||||||
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||||
|
#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */
|
||||||
|
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||||
|
#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -364,6 +403,15 @@ typedef struct __CAN_HandleTypeDef
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_filter_activation CAN Filter Activation
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */
|
||||||
|
#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
|
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
@ -496,7 +544,15 @@ typedef struct __CAN_HandleTypeDef
|
||||||
* @param __HANDLE__ CAN handle.
|
* @param __HANDLE__ CAN handle.
|
||||||
* @retval None
|
* @retval None
|
||||||
*/
|
*/
|
||||||
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||||
|
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||||
|
(__HANDLE__)->State = HAL_CAN_STATE_RESET; \
|
||||||
|
(__HANDLE__)->MspInitCallback = NULL; \
|
||||||
|
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||||
|
} while(0)
|
||||||
|
#else
|
||||||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
|
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
|
||||||
|
#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Enable the specified CAN interrupts.
|
* @brief Enable the specified CAN interrupts.
|
||||||
|
@ -587,6 +643,12 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
|
||||||
void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
|
void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
|
||||||
void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
|
void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
|
||||||
|
|
||||||
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||||
|
/* Callbacks Register/UnRegister functions ***********************************/
|
||||||
|
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
|
||||||
|
HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
|
||||||
|
|
||||||
|
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -738,6 +800,8 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
|
||||||
((MODE) == CAN_FILTERMODE_IDLIST))
|
((MODE) == CAN_FILTERMODE_IDLIST))
|
||||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
|
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
|
||||||
((SCALE) == CAN_FILTERSCALE_32BIT))
|
((SCALE) == CAN_FILTERSCALE_32BIT))
|
||||||
|
#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
|
||||||
|
((ACTIVATION) == CAN_FILTER_ENABLE))
|
||||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
|
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
|
||||||
((FIFO) == CAN_FILTER_FIFO1))
|
((FIFO) == CAN_FILTER_FIFO1))
|
||||||
#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
|
#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -7,29 +7,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -45,7 +29,7 @@
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f4xx.h"
|
#include "stm32f4xx.h"
|
||||||
#include "Legacy/stm32_hal_legacy.h"
|
#include "Legacy/stm32_hal_legacy.h"
|
||||||
#include <stdio.h>
|
#include <stddef.h>
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
@ -75,8 +59,8 @@ typedef enum
|
||||||
|
|
||||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||||
|
|
||||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
|
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
||||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
|
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||||
|
|
||||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||||
do{ \
|
do{ \
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -0,0 +1,264 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f4xx_hal_exti.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief Header file of EXTI HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef STM32f4xx_HAL_EXTI_H
|
||||||
|
#define STM32f4xx_HAL_EXTI_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f4xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI EXTI
|
||||||
|
* @brief EXTI HAL module driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_EXTI_COMMON_CB_ID = 0x00U,
|
||||||
|
HAL_EXTI_RISING_CB_ID = 0x01U,
|
||||||
|
HAL_EXTI_FALLING_CB_ID = 0x02U,
|
||||||
|
} EXTI_CallbackIDTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Handle structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Line; /*!< Exti line number */
|
||||||
|
void (* RisingCallback)(void); /*!< Exti rising callback */
|
||||||
|
void (* FallingCallback)(void); /*!< Exti falling callback */
|
||||||
|
} EXTI_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Configuration structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||||
|
can be a value of @ref EXTI_Line */
|
||||||
|
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||||
|
This parameter can be a combination of @ref EXTI_Mode */
|
||||||
|
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||||
|
can be a value of @ref EXTI_Trigger */
|
||||||
|
} EXTI_ConfigTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Line EXTI Line
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define EXTI_LINE_0 EXTI_IMR_IM0 /*!< External interrupt line 0 */
|
||||||
|
#define EXTI_LINE_1 EXTI_IMR_IM1 /*!< External interrupt line 1 */
|
||||||
|
#define EXTI_LINE_2 EXTI_IMR_IM2 /*!< External interrupt line 2 */
|
||||||
|
#define EXTI_LINE_3 EXTI_IMR_IM3 /*!< External interrupt line 3 */
|
||||||
|
#define EXTI_LINE_4 EXTI_IMR_IM4 /*!< External interrupt line 4 */
|
||||||
|
#define EXTI_LINE_5 EXTI_IMR_IM5 /*!< External interrupt line 5 */
|
||||||
|
#define EXTI_LINE_6 EXTI_IMR_IM6 /*!< External interrupt line 6 */
|
||||||
|
#define EXTI_LINE_7 EXTI_IMR_IM7 /*!< External interrupt line 7 */
|
||||||
|
#define EXTI_LINE_8 EXTI_IMR_IM8 /*!< External interrupt line 8 */
|
||||||
|
#define EXTI_LINE_9 EXTI_IMR_IM9 /*!< External interrupt line 9 */
|
||||||
|
#define EXTI_LINE_10 EXTI_IMR_IM10 /*!< External interrupt line 10 */
|
||||||
|
#define EXTI_LINE_11 EXTI_IMR_IM11 /*!< External interrupt line 11 */
|
||||||
|
#define EXTI_LINE_12 EXTI_IMR_IM12 /*!< External interrupt line 12 */
|
||||||
|
#define EXTI_LINE_13 EXTI_IMR_IM13 /*!< External interrupt line 13 */
|
||||||
|
#define EXTI_LINE_14 EXTI_IMR_IM14 /*!< External interrupt line 14 */
|
||||||
|
#define EXTI_LINE_15 EXTI_IMR_IM15 /*!< External interrupt line 15 */
|
||||||
|
#define EXTI_LINE_16 EXTI_IMR_IM16 /*!< External interrupt line 16 Connected to the PVD Output */
|
||||||
|
#define EXTI_LINE_17 EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||||
|
#define EXTI_LINE_18 EXTI_IMR_IM18 /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
|
||||||
|
#define EXTI_LINE_19 EXTI_IMR_IM19 /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||||
|
#define EXTI_LINE_20 EXTI_IMR_IM20 /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
|
||||||
|
#define EXTI_LINE_21 EXTI_IMR_IM21 /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
|
||||||
|
#define EXTI_LINE_22 EXTI_IMR_IM22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Mode EXTI Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define EXTI_MODE_INTERRUPT 0x00000000U
|
||||||
|
#define EXTI_MODE_EVENT 0x00000004U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define EXTI_TRIGGER_RISING 0x00000008U
|
||||||
|
#define EXTI_TRIGGER_FALLING 0x0000000CU
|
||||||
|
#define EXTI_TRIGGER_RISING_FALLING 0x00000010U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief EXTI Mask for interrupt & event mode
|
||||||
|
*/
|
||||||
|
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Mask for trigger possibilities
|
||||||
|
*/
|
||||||
|
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING | EXTI_TRIGGER_RISING_FALLING)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Line number
|
||||||
|
*/
|
||||||
|
#define EXTI_LINE_NB 23UL
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_EXTI_LINE(__LINE__) (((__LINE__) == EXTI_LINE_0) || \
|
||||||
|
((__LINE__) == EXTI_LINE_1) || \
|
||||||
|
((__LINE__) == EXTI_LINE_2) || \
|
||||||
|
((__LINE__) == EXTI_LINE_3) || \
|
||||||
|
((__LINE__) == EXTI_LINE_4) || \
|
||||||
|
((__LINE__) == EXTI_LINE_5) || \
|
||||||
|
((__LINE__) == EXTI_LINE_6) || \
|
||||||
|
((__LINE__) == EXTI_LINE_7) || \
|
||||||
|
((__LINE__) == EXTI_LINE_8) || \
|
||||||
|
((__LINE__) == EXTI_LINE_9) || \
|
||||||
|
((__LINE__) == EXTI_LINE_10) || \
|
||||||
|
((__LINE__) == EXTI_LINE_11) || \
|
||||||
|
((__LINE__) == EXTI_LINE_12) || \
|
||||||
|
((__LINE__) == EXTI_LINE_13) || \
|
||||||
|
((__LINE__) == EXTI_LINE_14) || \
|
||||||
|
((__LINE__) == EXTI_LINE_15) || \
|
||||||
|
((__LINE__) == EXTI_LINE_16) || \
|
||||||
|
((__LINE__) == EXTI_LINE_17) || \
|
||||||
|
((__LINE__) == EXTI_LINE_18) || \
|
||||||
|
((__LINE__) == EXTI_LINE_19) || \
|
||||||
|
((__LINE__) == EXTI_LINE_20) || \
|
||||||
|
((__LINE__) == EXTI_LINE_21) || \
|
||||||
|
((__LINE__) == EXTI_LINE_22))
|
||||||
|
|
||||||
|
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))
|
||||||
|
|
||||||
|
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
|
||||||
|
|
||||||
|
#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \
|
||||||
|
((__LINE__) == EXTI_TRIGGER_RISING) || \
|
||||||
|
((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
|
||||||
|
|
||||||
|
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||||
|
* @brief EXTI Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||||
|
* @brief Configuration functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Configuration functions ****************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||||
|
* @brief IO operation functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* IO operation functions *****************************************************/
|
||||||
|
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
|
||||||
|
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||||
|
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||||
|
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* STM32f4xx_HAL_EXTI_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -542,8 +526,9 @@
|
||||||
*/
|
*/
|
||||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||||
|
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
|
||||||
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
|
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
|
||||||
#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
|
#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief AF 6 selection
|
* @brief AF 6 selection
|
||||||
|
@ -566,7 +551,6 @@
|
||||||
/**
|
/**
|
||||||
* @brief AF 9 selection
|
* @brief AF 9 selection
|
||||||
*/
|
*/
|
||||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
|
|
||||||
#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */
|
#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */
|
||||||
#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */
|
#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */
|
||||||
|
|
||||||
|
@ -1319,7 +1303,7 @@
|
||||||
((__GPIOx__) == (GPIOE))? 4U : 7U)
|
((__GPIOx__) == (GPIOE))? 4U : 7U)
|
||||||
#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
|
#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
|
||||||
|
|
||||||
#if defined(STM32F446xx) || defined(STM32F412Zx) ||defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
|
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
|
||||||
((__GPIOx__) == (GPIOB))? 1U :\
|
((__GPIOx__) == (GPIOB))? 1U :\
|
||||||
((__GPIOx__) == (GPIOC))? 2U :\
|
((__GPIOx__) == (GPIOC))? 2U :\
|
||||||
|
@ -1327,7 +1311,25 @@
|
||||||
((__GPIOx__) == (GPIOE))? 4U :\
|
((__GPIOx__) == (GPIOE))? 4U :\
|
||||||
((__GPIOx__) == (GPIOF))? 5U :\
|
((__GPIOx__) == (GPIOF))? 5U :\
|
||||||
((__GPIOx__) == (GPIOG))? 6U : 7U)
|
((__GPIOx__) == (GPIOG))? 6U : 7U)
|
||||||
#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
|
#endif /* STM32F446xx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
|
#if defined(STM32F412Vx)
|
||||||
|
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
|
||||||
|
((__GPIOx__) == (GPIOB))? 1U :\
|
||||||
|
((__GPIOx__) == (GPIOC))? 2U :\
|
||||||
|
((__GPIOx__) == (GPIOD))? 3U :\
|
||||||
|
((__GPIOx__) == (GPIOE))? 4U : 7U)
|
||||||
|
#endif /* STM32F412Vx */
|
||||||
|
#if defined(STM32F412Rx)
|
||||||
|
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
|
||||||
|
((__GPIOx__) == (GPIOB))? 1U :\
|
||||||
|
((__GPIOx__) == (GPIOC))? 2U :\
|
||||||
|
((__GPIOx__) == (GPIOD))? 3U : 7U)
|
||||||
|
#endif /* STM32F412Rx */
|
||||||
|
#if defined(STM32F412Cx)
|
||||||
|
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
|
||||||
|
((__GPIOx__) == (GPIOB))? 1U :\
|
||||||
|
((__GPIOx__) == (GPIOC))? 2U : 7U)
|
||||||
|
#endif /* STM32F412Cx */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
@ -1441,7 +1443,7 @@
|
||||||
|
|
||||||
/*---------------------------------------- STM32F401xx------------------------*/
|
/*---------------------------------------- STM32F401xx------------------------*/
|
||||||
#if defined(STM32F401xC) || defined(STM32F401xE)
|
#if defined(STM32F401xC) || defined(STM32F401xE)
|
||||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
|
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF12_SDIO) || \
|
||||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
|
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
|
||||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||||
((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
|
((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
|
||||||
|
@ -1453,7 +1455,7 @@
|
||||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||||
((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \
|
((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \
|
||||||
((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \
|
((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \
|
||||||
((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT))
|
((AF) == GPIO_AF15_EVENTOUT))
|
||||||
|
|
||||||
#endif /* STM32F401xC || STM32F401xE */
|
#endif /* STM32F401xC || STM32F401xE */
|
||||||
/*----------------------------------------------------------------------------*/
|
/*----------------------------------------------------------------------------*/
|
||||||
|
|
|
@ -6,118 +6,142 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F4xx_HAL_PCD_H
|
#ifndef STM32F4xx_HAL_PCD_H
|
||||||
#define __STM32F4xx_HAL_PCD_H
|
#define STM32F4xx_HAL_PCD_H
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
|
|
||||||
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
|
|
||||||
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
|
|
||||||
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
|
|
||||||
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f4xx_ll_usb.h"
|
#include "stm32f4xx_ll_usb.h"
|
||||||
|
|
||||||
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
|
|
||||||
/** @addtogroup STM32F4xx_HAL_Driver
|
/** @addtogroup STM32F4xx_HAL_Driver
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup PCD
|
/** @addtogroup PCD
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
/* Exported types ------------------------------------------------------------*/
|
||||||
/** @defgroup PCD_Exported_Types PCD Exported Types
|
/** @defgroup PCD_Exported_Types PCD Exported Types
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief PCD State structure definition
|
* @brief PCD State structure definition
|
||||||
*/
|
*/
|
||||||
typedef enum
|
typedef enum
|
||||||
{
|
{
|
||||||
HAL_PCD_STATE_RESET = 0x00U,
|
HAL_PCD_STATE_RESET = 0x00,
|
||||||
HAL_PCD_STATE_READY = 0x01U,
|
HAL_PCD_STATE_READY = 0x01,
|
||||||
HAL_PCD_STATE_ERROR = 0x02U,
|
HAL_PCD_STATE_ERROR = 0x02,
|
||||||
HAL_PCD_STATE_BUSY = 0x03U,
|
HAL_PCD_STATE_BUSY = 0x03,
|
||||||
HAL_PCD_STATE_TIMEOUT = 0x04U
|
HAL_PCD_STATE_TIMEOUT = 0x04
|
||||||
} PCD_StateTypeDef;
|
} PCD_StateTypeDef;
|
||||||
|
|
||||||
#ifdef USB_OTG_GLPMCFG_LPMEN
|
|
||||||
/* Device LPM suspend state */
|
/* Device LPM suspend state */
|
||||||
typedef enum
|
typedef enum
|
||||||
{
|
{
|
||||||
LPM_L0 = 0x00U, /* on */
|
LPM_L0 = 0x00, /* on */
|
||||||
LPM_L1 = 0x01U, /* LPM L1 sleep */
|
LPM_L1 = 0x01, /* LPM L1 sleep */
|
||||||
LPM_L2 = 0x02U, /* suspend */
|
LPM_L2 = 0x02, /* suspend */
|
||||||
LPM_L3 = 0x03U /* off */
|
LPM_L3 = 0x03, /* off */
|
||||||
}PCD_LPM_StateTypeDef;
|
} PCD_LPM_StateTypeDef;
|
||||||
#endif /* USB_OTG_GLPMCFG_LPMEN */
|
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
PCD_LPM_L0_ACTIVE = 0x00, /* on */
|
||||||
|
PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
|
||||||
|
} PCD_LPM_MsgTypeDef;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
PCD_BCD_ERROR = 0xFF,
|
||||||
|
PCD_BCD_CONTACT_DETECTION = 0xFE,
|
||||||
|
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
|
||||||
|
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
|
||||||
|
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
|
||||||
|
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
|
||||||
|
|
||||||
|
} PCD_BCD_MsgTypeDef;
|
||||||
|
|
||||||
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
|
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
|
||||||
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
|
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
|
||||||
typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
|
typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
|
||||||
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief PCD Handle Structure definition
|
* @brief PCD Handle Structure definition
|
||||||
*/
|
*/
|
||||||
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||||
|
typedef struct __PCD_HandleTypeDef
|
||||||
|
#else
|
||||||
typedef struct
|
typedef struct
|
||||||
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||||
{
|
{
|
||||||
PCD_TypeDef *Instance; /*!< Register base address */
|
PCD_TypeDef *Instance; /*!< Register base address */
|
||||||
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
||||||
PCD_EPTypeDef IN_ep[16U]; /*!< IN endpoint parameters */
|
__IO uint8_t USB_Address; /*!< USB Address */
|
||||||
PCD_EPTypeDef OUT_ep[16U]; /*!< OUT endpoint parameters */
|
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
|
||||||
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
|
||||||
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
||||||
uint32_t Setup[12U]; /*!< Setup packet buffer */
|
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
||||||
#ifdef USB_OTG_GLPMCFG_LPMEN
|
__IO uint32_t ErrorCode; /*!< PCD Error code */
|
||||||
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
|
uint32_t Setup[12]; /*!< Setup packet buffer */
|
||||||
|
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
|
||||||
uint32_t BESL;
|
uint32_t BESL;
|
||||||
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
|
|
||||||
This parameter can be set to ENABLE or DISABLE */
|
|
||||||
#endif /* USB_OTG_GLPMCFG_LPMEN */
|
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
|
||||||
#ifdef USB_OTG_GCCFG_BCDEN
|
This parameter can be set to ENABLE or DISABLE */
|
||||||
uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
|
|
||||||
This parameter can be set to ENABLE or DISABLE */
|
uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
|
||||||
#endif /* USB_OTG_GCCFG_BCDEN */
|
This parameter can be set to ENABLE or DISABLE */
|
||||||
void *pData; /*!< Pointer to upper stack Handler */
|
void *pData; /*!< Pointer to upper stack Handler */
|
||||||
|
|
||||||
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||||
|
void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
|
||||||
|
void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
|
||||||
|
void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
|
||||||
|
void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
|
||||||
|
void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
|
||||||
|
void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
|
||||||
|
void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
|
||||||
|
|
||||||
|
void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
|
||||||
|
void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
|
||||||
|
void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
|
||||||
|
void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
|
||||||
|
void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */
|
||||||
|
void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
|
||||||
|
|
||||||
|
void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
|
||||||
|
void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
|
||||||
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||||
} PCD_HandleTypeDef;
|
} PCD_HandleTypeDef;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Include PCD HAL Extension module */
|
/* Include PCD HAL Extended module */
|
||||||
#include "stm32f4xx_hal_pcd_ex.h"
|
#include "stm32f4xx_hal_pcd_ex.h"
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
@ -128,31 +152,31 @@ typedef struct
|
||||||
/** @defgroup PCD_Speed PCD Speed
|
/** @defgroup PCD_Speed PCD Speed
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define PCD_SPEED_HIGH 0U
|
#define PCD_SPEED_HIGH USBD_HS_SPEED
|
||||||
#define PCD_SPEED_HIGH_IN_FULL 1U
|
#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED
|
||||||
#define PCD_SPEED_FULL 2U
|
#define PCD_SPEED_FULL USBD_FS_SPEED
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup PCD_PHY_Module PCD PHY Module
|
/** @defgroup PCD_PHY_Module PCD PHY Module
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define PCD_PHY_ULPI 1U
|
#define PCD_PHY_ULPI 1U
|
||||||
#define PCD_PHY_EMBEDDED 2U
|
#define PCD_PHY_EMBEDDED 2U
|
||||||
|
#define PCD_PHY_UTMI 3U
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
|
/** @defgroup PCD_Error_Code_definition PCD Error Code definition
|
||||||
|
* @brief PCD Error Code definition
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#ifndef USBD_HS_TRDT_VALUE
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||||
#define USBD_HS_TRDT_VALUE 9U
|
#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
|
||||||
#endif /* USBD_HS_TRDT_VALUE */
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||||
#ifndef USBD_FS_TRDT_VALUE
|
|
||||||
#define USBD_FS_TRDT_VALUE 5U
|
|
||||||
#endif /* USBD_FS_TRDT_VALUE */
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -166,75 +190,48 @@ typedef struct
|
||||||
* @brief macros to handle interrupts and specific clock configurations
|
* @brief macros to handle interrupts and specific clock configurations
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||||
|
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||||
|
|
||||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
|
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
|
||||||
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||||
|
|
||||||
|
|
||||||
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
|
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
|
||||||
~(USB_OTG_PCGCCTL_STOPCLK)
|
~(USB_OTG_PCGCCTL_STOPCLK)
|
||||||
|
|
||||||
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
|
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
|
||||||
|
|
||||||
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10U)
|
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
|
||||||
|
|
||||||
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
|
|
||||||
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
|
|
||||||
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
|
|
||||||
|
|
||||||
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
|
|
||||||
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
|
|
||||||
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
|
|
||||||
|
|
||||||
#define USB_OTG_HS_WAKEUP_EXTI_LINE 0x00100000U /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
|
|
||||||
#define USB_OTG_FS_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
|
|
||||||
|
|
||||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
|
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||||
|
|
||||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
|
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
|
||||||
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
|
do { \
|
||||||
}while(0U)
|
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
|
||||||
|
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
|
||||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
|
} while(0U)
|
||||||
EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
|
|
||||||
}while(0U)
|
|
||||||
|
|
||||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
|
|
||||||
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
|
|
||||||
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
|
|
||||||
EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
|
|
||||||
}while(0U)
|
|
||||||
|
|
||||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
|
|
||||||
|
|
||||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
|
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
|
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
|
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
|
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||||
|
|
||||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
|
||||||
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
|
do { \
|
||||||
}while(0U)
|
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
|
||||||
|
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
|
||||||
|
} while(0U)
|
||||||
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
|
|
||||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
|
||||||
EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
|
||||||
}while(0U)
|
|
||||||
|
|
||||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
|
||||||
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
|
||||||
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
|
|
||||||
EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
|
|
||||||
}while(0U)
|
|
||||||
|
|
||||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
/* Exported functions --------------------------------------------------------*/
|
||||||
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
|
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
|
||||||
|
@ -249,6 +246,68 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
|
||||||
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
|
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
|
||||||
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
|
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
|
||||||
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
|
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
|
||||||
|
|
||||||
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||||
|
/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
|
||||||
|
* @brief HAL USB OTG PCD Callback ID enumeration definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
|
||||||
|
HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
|
||||||
|
HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
|
||||||
|
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
|
||||||
|
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
|
||||||
|
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
|
||||||
|
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
|
||||||
|
|
||||||
|
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
|
||||||
|
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
|
||||||
|
|
||||||
|
} HAL_PCD_CallbackIDTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
|
||||||
|
* @brief HAL USB OTG PCD Callback pointer definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
|
||||||
|
typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
|
||||||
|
typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
|
||||||
|
typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
|
||||||
|
typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
|
||||||
|
typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
|
||||||
|
typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -258,22 +317,22 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
|
||||||
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
|
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/* Non-Blocking mode: Interrupt */
|
|
||||||
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
||||||
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
||||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||||
|
|
||||||
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
|
||||||
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
|
||||||
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
|
||||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||||
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
|
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
|
||||||
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
|
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
|
||||||
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
|
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
|
||||||
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
|
||||||
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
|
||||||
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
|
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
|
||||||
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
|
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
|
||||||
|
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||||
|
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||||
|
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||||
|
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -289,7 +348,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
|
||||||
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||||
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||||
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||||
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||||
|
@ -306,12 +365,66 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup PCD_Private_Constants PCD Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
|
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
|
||||||
|
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
|
||||||
|
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
|
||||||
|
|
||||||
|
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
|
||||||
|
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
|
||||||
|
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
|
||||||
|
|
||||||
|
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
|
||||||
|
#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */
|
||||||
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
|
#ifndef USB_OTG_DOEPINT_OTEPSPR
|
||||||
|
#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef USB_OTG_DOEPMSK_OTEPSPRM
|
||||||
|
#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef USB_OTG_DOEPINT_NAK
|
||||||
|
#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef USB_OTG_DOEPMSK_NAKM
|
||||||
|
#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef USB_OTG_DOEPINT_STPKTRX
|
||||||
|
#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef USB_OTG_DOEPMSK_NYETM
|
||||||
|
#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
|
||||||
|
#endif
|
||||||
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
/* Private macros ------------------------------------------------------------*/
|
||||||
/** @defgroup PCD_Private_Macros PCD Private Macros
|
/** @defgroup PCD_Private_Macros PCD Private Macros
|
||||||
* @{
|
* @{
|
||||||
|
@ -319,23 +432,21 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
|
|
||||||
STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#endif /* STM32F4xx_HAL_PCD_H */
|
||||||
#endif /* __STM32F4xx_HAL_PCD_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
@ -2,52 +2,33 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file stm32f4xx_hal_pcd_ex.h
|
* @file stm32f4xx_hal_pcd_ex.h
|
||||||
* @author MCD Application Team
|
* @author MCD Application Team
|
||||||
* @brief Header file of PCD HAL module.
|
* @brief Header file of PCD HAL Extension module.
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F4xx_HAL_PCD_EX_H
|
#ifndef STM32F4xx_HAL_PCD_EX_H
|
||||||
#define __STM32F4xx_HAL_PCD_EX_H
|
#define STM32F4xx_HAL_PCD_EX_H
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
|
|
||||||
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
|
|
||||||
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
|
|
||||||
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
|
|
||||||
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f4xx_hal_def.h"
|
#include "stm32f4xx_hal_def.h"
|
||||||
|
|
||||||
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
/** @addtogroup STM32F4xx_HAL_Driver
|
/** @addtogroup STM32F4xx_HAL_Driver
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
@ -56,76 +37,55 @@
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/* Exported types ------------------------------------------------------------*/
|
/* Exported types ------------------------------------------------------------*/
|
||||||
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
|
|
||||||
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
PCD_LPM_L0_ACTIVE = 0x00U, /* on */
|
|
||||||
PCD_LPM_L1_ACTIVE = 0x01U /* LPM L1 sleep */
|
|
||||||
}PCD_LPM_MsgTypeDef;
|
|
||||||
#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx*/
|
|
||||||
|
|
||||||
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
PCD_BCD_ERROR = 0xFFU,
|
|
||||||
PCD_BCD_CONTACT_DETECTION = 0xFEU,
|
|
||||||
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFDU,
|
|
||||||
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFCU,
|
|
||||||
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFBU,
|
|
||||||
PCD_BCD_DISCOVERY_COMPLETED = 0x00U
|
|
||||||
}PCD_BCD_MsgTypeDef;
|
|
||||||
#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
/* Exported constants --------------------------------------------------------*/
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
/* Exported macros -----------------------------------------------------------*/
|
||||||
/* Exported functions --------------------------------------------------------*/
|
/* Exported functions --------------------------------------------------------*/
|
||||||
/** @addtogroup PCDEx_Exported_Functions PCD Extended Exported Functions
|
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
|
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
|
||||||
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
|
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
|
||||||
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
|
||||||
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
|
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
|
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||||
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
|
||||||
#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
|
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
|
||||||
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
|
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
|
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||||
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
|
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
|
||||||
|
#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
|
||||||
|
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
|
||||||
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
|
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
|
||||||
void HAL_PCDEx_ADP_Sensing_Start(PCD_HandleTypeDef *hpcd);
|
|
||||||
void HAL_PCDEx_ADP_Sensing_Callback(PCD_HandleTypeDef *hpcd);
|
|
||||||
#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
|
|
||||||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
|
/**
|
||||||
STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
#endif /* __STM32F4xx_HAL_PCD_EX_H */
|
#endif /* STM32F4xx_HAL_PCD_EX_H */
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -225,11 +209,6 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
|
||||||
uint32_t HAL_PWREx_GetVoltageRange(void);
|
uint32_t HAL_PWREx_GetVoltageRange(void);
|
||||||
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
|
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
|
||||||
|
|
||||||
#if defined(STM32F469xx) || defined(STM32F479xx)
|
|
||||||
void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void);
|
|
||||||
void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void);
|
|
||||||
#endif /* STM32F469xx || STM32F479xx */
|
|
||||||
|
|
||||||
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
|
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
|
||||||
defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
|
defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
|
||||||
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
|
@ -298,11 +277,6 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
|
||||||
#define BRE_BIT_NUMBER PWR_CSR_BRE_Pos
|
#define BRE_BIT_NUMBER PWR_CSR_BRE_Pos
|
||||||
#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
|
#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
|
||||||
|
|
||||||
#if defined(STM32F469xx) || defined(STM32F479xx)
|
|
||||||
/* Alias word address of WUPP bit */
|
|
||||||
#define WUPP_BIT_NUMBER PWR_CSR_WUPP_Pos
|
|
||||||
#define CSR_WUPP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (WUPP_BIT_NUMBER * 4U))
|
|
||||||
#endif /* STM32F469xx || STM32F479xx */
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -4730,6 +4714,7 @@ typedef struct
|
||||||
* using it.
|
* using it.
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
|
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
|
||||||
__IO uint32_t tmpreg = 0x00U; \
|
__IO uint32_t tmpreg = 0x00U; \
|
||||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
|
||||||
|
@ -4737,6 +4722,8 @@ typedef struct
|
||||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
|
||||||
UNUSED(tmpreg); \
|
UNUSED(tmpreg); \
|
||||||
} while(0U)
|
} while(0U)
|
||||||
|
#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
|
#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
|
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
|
||||||
__IO uint32_t tmpreg = 0x00U; \
|
__IO uint32_t tmpreg = 0x00U; \
|
||||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
|
||||||
|
@ -4744,6 +4731,8 @@ typedef struct
|
||||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
|
||||||
UNUSED(tmpreg); \
|
UNUSED(tmpreg); \
|
||||||
} while(0U)
|
} while(0U)
|
||||||
|
#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
|
#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
|
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
|
||||||
__IO uint32_t tmpreg = 0x00U; \
|
__IO uint32_t tmpreg = 0x00U; \
|
||||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
|
||||||
|
@ -4758,6 +4747,7 @@ typedef struct
|
||||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
|
||||||
UNUSED(tmpreg); \
|
UNUSED(tmpreg); \
|
||||||
} while(0U)
|
} while(0U)
|
||||||
|
#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
|
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
|
||||||
__IO uint32_t tmpreg = 0x00U; \
|
__IO uint32_t tmpreg = 0x00U; \
|
||||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
|
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
|
||||||
|
@ -4765,11 +4755,16 @@ typedef struct
|
||||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
|
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
|
||||||
UNUSED(tmpreg); \
|
UNUSED(tmpreg); \
|
||||||
} while(0U)
|
} while(0U)
|
||||||
|
#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
|
#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
|
||||||
|
#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
|
#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
|
#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
|
||||||
|
#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
|
#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
|
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
|
||||||
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
|
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
|
||||||
|
#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
|
#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
@ -4782,16 +4777,28 @@ typedef struct
|
||||||
* using it.
|
* using it.
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
|
#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
|
||||||
|
#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
|
#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
|
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
|
||||||
|
#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
|
#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
|
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
|
||||||
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
|
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
|
||||||
|
#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
|
#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
|
||||||
|
|
||||||
|
#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
|
#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
|
||||||
|
#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
|
#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
|
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
|
||||||
|
#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
|
#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
|
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
|
||||||
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
|
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
|
||||||
|
#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
|
#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
@ -5346,16 +5353,28 @@ typedef struct
|
||||||
* @brief Force or release AHB1 peripheral reset.
|
* @brief Force or release AHB1 peripheral reset.
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
|
#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
|
||||||
|
#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
|
#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
|
#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
|
||||||
|
#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
|
#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
|
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
|
||||||
#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
|
#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
|
||||||
|
#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
|
#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
|
||||||
|
|
||||||
|
#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
|
#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
|
||||||
|
#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
|
#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
|
#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
|
||||||
|
#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
|
#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
|
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
|
||||||
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
|
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
|
||||||
|
#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
|
||||||
#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
|
#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -2,43 +2,27 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file stm32f4xx_hal_tim_ex.h
|
* @file stm32f4xx_hal_tim_ex.h
|
||||||
* @author MCD Application Team
|
* @author MCD Application Team
|
||||||
* @brief Header file of TIM HAL Extension module.
|
* @brief Header file of TIM HAL Extended module.
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F4xx_HAL_TIM_EX_H
|
#ifndef STM32F4xx_HAL_TIM_EX_H
|
||||||
#define __STM32F4xx_HAL_TIM_EX_H
|
#define STM32F4xx_HAL_TIM_EX_H
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
@ -50,22 +34,21 @@
|
||||||
|
|
||||||
/** @addtogroup TIMEx
|
/** @addtogroup TIMEx
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
/* Exported types ------------------------------------------------------------*/
|
||||||
/** @defgroup TIMEx_Exported_Types TIM Exported Types
|
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief TIM Hall sensor Configuration Structure definition
|
* @brief TIM Hall sensor Configuration Structure definition
|
||||||
*/
|
*/
|
||||||
|
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
|
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
|
||||||
|
|
||||||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
||||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||||
|
@ -73,296 +56,296 @@ typedef struct
|
||||||
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
||||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||||
|
|
||||||
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||||
This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
|
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||||
} TIM_HallSensor_InitTypeDef;
|
} TIM_HallSensor_InitTypeDef;
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief TIM Master configuration Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct {
|
|
||||||
uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection.
|
|
||||||
This parameter can be a value of @ref TIM_Master_Mode_Selection */
|
|
||||||
|
|
||||||
uint32_t MasterSlaveMode; /*!< Master/slave mode selection.
|
|
||||||
This parameter can be a value of @ref TIM_Master_Slave_Mode */
|
|
||||||
}TIM_MasterConfigTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief TIM Break and Dead time configuration Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t OffStateRunMode; /*!< TIM off state in run mode.
|
|
||||||
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
|
|
||||||
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
|
|
||||||
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
|
|
||||||
uint32_t LockLevel; /*!< TIM Lock level.
|
|
||||||
This parameter can be a value of @ref TIM_Lock_level */
|
|
||||||
uint32_t DeadTime; /*!< TIM dead Time.
|
|
||||||
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
|
||||||
uint32_t BreakState; /*!< TIM Break State.
|
|
||||||
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
|
|
||||||
uint32_t BreakPolarity; /*!< TIM Break input polarity.
|
|
||||||
This parameter can be a value of @ref TIM_Break_Polarity */
|
|
||||||
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
|
|
||||||
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
|
||||||
}TIM_BreakDeadTimeConfigTypeDef;
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
/* End of exported types -----------------------------------------------------*/
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
/* Exported constants --------------------------------------------------------*/
|
||||||
/** @defgroup TIMEx_Exported_Constants TIM Exported Constants
|
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup TIMEx_Remap TIM Remap
|
/** @defgroup TIMEx_Remap TIM Extended Remapping
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define TIM_TIM2_TIM8_TRGO 0x00000000U
|
#if defined (TIM2)
|
||||||
#define TIM_TIM2_ETH_PTP 0x00000400U
|
#if defined(TIM8)
|
||||||
#define TIM_TIM2_USBFS_SOF 0x00000800U
|
#define TIM_TIM2_TIM8_TRGO 0x00000000U /*!< TIM2 ITR1 is connected to TIM8 TRGO */
|
||||||
#define TIM_TIM2_USBHS_SOF 0x00000C00U
|
#else
|
||||||
#define TIM_TIM5_GPIO 0x00000000U
|
#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */
|
||||||
#define TIM_TIM5_LSI 0x00000040U
|
#endif /* TIM8 */
|
||||||
#define TIM_TIM5_LSE 0x00000080U
|
#define TIM_TIM2_USBFS_SOF TIM_OR_ITR1_RMP_1 /*!< TIM2 ITR1 is connected to OTG FS SOF */
|
||||||
#define TIM_TIM5_RTC 0x000000C0U
|
#define TIM_TIM2_USBHS_SOF (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0) /*!< TIM2 ITR1 is connected to OTG HS SOF */
|
||||||
#define TIM_TIM11_GPIO 0x00000000U
|
#endif /* TIM2 */
|
||||||
#define TIM_TIM11_HSE 0x00000002U
|
|
||||||
|
|
||||||
#if defined(STM32F413xx) || defined(STM32F423xx)
|
#define TIM_TIM5_GPIO 0x00000000U /*!< TIM5 TI4 is connected to GPIO */
|
||||||
#define TIM_TIM9_TIM3_TRGO 0x10000000U
|
#define TIM_TIM5_LSI TIM_OR_TI4_RMP_0 /*!< TIM5 TI4 is connected to LSI */
|
||||||
#define TIM_TIM9_LPTIM 0x10000010U
|
#define TIM_TIM5_LSE TIM_OR_TI4_RMP_1 /*!< TIM5 TI4 is connected to LSE */
|
||||||
#define TIM_TIM5_TIM3_TRGO 0x10000000U
|
#define TIM_TIM5_RTC (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0) /*!< TIM5 TI4 is connected to the RTC wakeup interrupt */
|
||||||
#define TIM_TIM5_LPTIM 0x10000008U
|
|
||||||
#define TIM_TIM1_TIM3_TRGO 0x10000000U
|
|
||||||
#define TIM_TIM1_LPTIM 0x10000004U
|
|
||||||
#endif /* STM32F413xx | STM32F423xx */
|
|
||||||
|
|
||||||
#if defined (STM32F446xx)
|
#define TIM_TIM11_GPIO 0x00000000U /*!< TIM11 TI1 is connected to GPIO */
|
||||||
#define TIM_TIM11_SPDIFRX 0x00000001U
|
#define TIM_TIM11_HSE TIM_OR_TI1_RMP_1 /*!< TIM11 TI1 is connected to HSE_RTC clock */
|
||||||
#endif /* STM32F446xx */
|
#if defined(SPDIFRX)
|
||||||
|
#define TIM_TIM11_SPDIFRX TIM_OR_TI1_RMP_0 /*!< TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC */
|
||||||
|
#endif /* SPDIFRX*/
|
||||||
|
|
||||||
|
#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP)
|
||||||
|
#define LPTIM_REMAP_MASK 0x10000000U
|
||||||
|
|
||||||
|
#define TIM_TIM9_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM9 ITR1 is connected to TIM3 TRGO */
|
||||||
|
#define TIM_TIM9_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP) /*!< TIM9 ITR1 is connected to LPTIM1 output */
|
||||||
|
|
||||||
|
#define TIM_TIM5_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM5 ITR1 is connected to TIM3 TRGO */
|
||||||
|
#define TIM_TIM5_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP) /*!< TIM5 ITR1 is connected to LPTIM1 output */
|
||||||
|
|
||||||
|
#define TIM_TIM1_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM1 ITR2 is connected to TIM3 TRGO */
|
||||||
|
#define TIM_TIM1_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP) /*!< TIM1 ITR2 is connected to LPTIM1 output */
|
||||||
|
#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
|
|
||||||
/** @defgroup TIMEx_SystemBreakInput TIM System Break Input
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define TIM_SYSTEMBREAKINPUT_HARDFAULT 0x00000001U /* Core Lockup lock output(Hardfault) is connected to Break Input of TIM1 and TIM8 */
|
|
||||||
#define TIM_SYSTEMBREAKINPUT_PVD 0x00000004U /* PVD Interrupt is connected to Break Input of TIM1 and TIM8 */
|
|
||||||
#define TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD 0x00000005U /* Core Lockup lock output(Hardfault) and PVD Interrupt are connected to Break Input of TIM1 and TIM8 */
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
|
/* End of exported constants -------------------------------------------------*/
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* End of exported macro -----------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined(SPDIFRX)
|
||||||
|
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
|
||||||
|
((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
|
||||||
|
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_LSI) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_LSE) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_RTC))) || \
|
||||||
|
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM11_SPDIFRX) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM11_HSE))))
|
||||||
|
#elif defined(TIM2)
|
||||||
|
#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP)
|
||||||
|
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
|
||||||
|
((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
|
||||||
|
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_LSI) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_LSE) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_RTC))) || \
|
||||||
|
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM11_HSE))) || \
|
||||||
|
(((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM1_LPTIM))) || \
|
||||||
|
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_LPTIM))) || \
|
||||||
|
(((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM9_LPTIM))))
|
||||||
|
#elif defined(TIM8)
|
||||||
|
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
|
||||||
|
((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
|
||||||
|
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_LSI) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_LSE) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_RTC))) || \
|
||||||
|
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM11_HSE))))
|
||||||
|
#else
|
||||||
|
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
|
||||||
|
((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
|
||||||
|
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_LSI) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_LSE) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_RTC))) || \
|
||||||
|
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM11_HSE))))
|
||||||
|
#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */
|
||||||
|
#else
|
||||||
|
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
|
||||||
|
((((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_LSI) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_LSE) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_RTC))) || \
|
||||||
|
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM11_HSE))))
|
||||||
|
#endif /* SPDIFRX */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* End of private macro ------------------------------------------------------*/
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
/* Exported functions --------------------------------------------------------*/
|
||||||
/** @addtogroup TIMEx_Exported_Functions
|
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group1
|
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
|
||||||
* @{
|
* @brief Timer Hall Sensor functions
|
||||||
*/
|
* @{
|
||||||
|
*/
|
||||||
/* Timer Hall Sensor functions **********************************************/
|
/* Timer Hall Sensor functions **********************************************/
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
|
||||||
|
|
||||||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
|
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
|
||||||
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
|
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
|
||||||
|
|
||||||
/* Blocking mode: Polling */
|
/* Blocking mode: Polling */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
|
||||||
/* Non-Blocking mode: Interrupt */
|
/* Non-Blocking mode: Interrupt */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
|
||||||
/* Non-Blocking mode: DMA */
|
/* Non-Blocking mode: DMA */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group2
|
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
|
||||||
* @{
|
* @brief Timer Complementary Output Compare functions
|
||||||
*/
|
* @{
|
||||||
|
*/
|
||||||
/* Timer Complementary Output Compare functions *****************************/
|
/* Timer Complementary Output Compare functions *****************************/
|
||||||
/* Blocking mode: Polling */
|
/* Blocking mode: Polling */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
|
|
||||||
/* Non-Blocking mode: Interrupt */
|
/* Non-Blocking mode: Interrupt */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
|
|
||||||
/* Non-Blocking mode: DMA */
|
/* Non-Blocking mode: DMA */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group3
|
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
|
||||||
* @{
|
* @brief Timer Complementary PWM functions
|
||||||
*/
|
* @{
|
||||||
|
*/
|
||||||
/* Timer Complementary PWM functions ****************************************/
|
/* Timer Complementary PWM functions ****************************************/
|
||||||
/* Blocking mode: Polling */
|
/* Blocking mode: Polling */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
|
|
||||||
/* Non-Blocking mode: Interrupt */
|
/* Non-Blocking mode: Interrupt */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
/* Non-Blocking mode: DMA */
|
/* Non-Blocking mode: DMA */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group4
|
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
|
||||||
* @{
|
* @brief Timer Complementary One Pulse functions
|
||||||
*/
|
* @{
|
||||||
|
*/
|
||||||
/* Timer Complementary One Pulse functions **********************************/
|
/* Timer Complementary One Pulse functions **********************************/
|
||||||
/* Blocking mode: Polling */
|
/* Blocking mode: Polling */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||||
|
|
||||||
/* Non-Blocking mode: Interrupt */
|
/* Non-Blocking mode: Interrupt */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group5
|
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
||||||
* @{
|
* @brief Peripheral Control functions
|
||||||
*/
|
* @{
|
||||||
/* Extension Control functions ************************************************/
|
*/
|
||||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
/* Extended Control functions ************************************************/
|
||||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
|
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
|
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
||||||
|
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group6
|
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
|
||||||
|
* @brief Extended Callbacks functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/* Extension Callback *********************************************************/
|
/* Extended Callback **********************************************************/
|
||||||
void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
|
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
|
||||||
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
|
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
|
||||||
|
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
|
||||||
|
* @brief Extended Peripheral State functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Extended Peripheral State functions ***************************************/
|
||||||
|
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* End of exported functions -------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Private functions----------------------------------------------------------*/
|
||||||
|
/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
|
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
|
||||||
|
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
/* End of private functions --------------------------------------------------*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group7
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Extension Peripheral State functions **************************************/
|
|
||||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private types -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup TIMEx_Private_Macros TIM Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#if defined (STM32F446xx)
|
|
||||||
#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_GPIO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_LSI)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_LSE)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_RTC)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM11_GPIO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM11_SPDIFRX)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM11_HSE))
|
|
||||||
#elif defined(STM32F413xx) || defined(STM32F423xx)
|
|
||||||
#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_GPIO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_LSI)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_LSE)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_RTC)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM11_GPIO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM11_HSE)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM9_TIM3_TRGO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM9_LPTIM)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_TIM3_TRGO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_LPTIM)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM1_TIM3_TRGO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM1_LPTIM))
|
|
||||||
#else
|
|
||||||
#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_GPIO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_LSI)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_LSE)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_RTC)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM11_GPIO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM11_HSE))
|
|
||||||
#endif /* STM32F446xx */
|
|
||||||
|
|
||||||
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
|
|
||||||
#define IS_TIM_SYSTEMBREAKINPUT(BREAKINPUT) (((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT)||\
|
|
||||||
((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_PVD)||\
|
|
||||||
((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD))
|
|
||||||
|
|
||||||
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
|
|
||||||
|
|
||||||
#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
/** @defgroup TIMEx_Private_Functions TIM Private Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* __STM32F4xx_HAL_TIM_EX_H */
|
|
||||||
|
#endif /* STM32F4xx_HAL_TIM_EX_H */
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
@ -23,29 +23,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -22,29 +22,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -5354,7 +5338,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
|
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
|
||||||
{
|
{
|
||||||
register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
|
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
|
||||||
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
|
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
|
||||||
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
|
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
|
||||||
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
|
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
|
||||||
|
@ -5474,7 +5458,7 @@ __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PL
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
|
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
|
||||||
{
|
{
|
||||||
register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
|
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
|
||||||
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
|
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
|
||||||
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
|
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
|
||||||
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
|
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
|
||||||
|
@ -5678,7 +5662,7 @@ __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
|
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
|
||||||
{
|
{
|
||||||
register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
|
register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
|
||||||
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
|
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
|
||||||
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
|
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
|
||||||
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
|
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
|
||||||
|
|
|
@ -6,36 +6,20 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F4xx_LL_SPI_H
|
#ifndef STM32F4xx_LL_SPI_H
|
||||||
#define __STM32F4xx_LL_SPI_H
|
#define STM32F4xx_LL_SPI_H
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
|
@ -162,7 +146,7 @@ typedef struct
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
|
#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
|
||||||
#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
|
#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -252,8 +236,8 @@ typedef struct
|
||||||
/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
|
/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
|
#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
|
||||||
#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
|
#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -336,7 +320,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
|
return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -628,7 +612,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
|
return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -747,7 +731,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
|
return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -758,7 +742,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
|
return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -769,7 +753,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
|
return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -780,7 +764,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
|
return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -791,7 +775,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
|
return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -809,7 +793,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
|
return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -820,7 +804,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
|
return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -844,11 +828,10 @@ __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
|
__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
__IO uint32_t tmpreg;
|
__IO uint32_t tmpreg_sr;
|
||||||
tmpreg = SPIx->SR;
|
tmpreg_sr = SPIx->SR;
|
||||||
(void) tmpreg;
|
(void) tmpreg_sr;
|
||||||
tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
|
CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
|
||||||
(void) tmpreg;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -966,7 +949,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -977,7 +960,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -988,7 +971,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1029,7 +1012,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1062,7 +1045,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1115,7 +1098,12 @@ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
|
__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
|
||||||
{
|
{
|
||||||
SPIx->DR = TxData;
|
#if defined (__GNUC__)
|
||||||
|
__IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
|
||||||
|
*spidr = TxData;
|
||||||
|
#else
|
||||||
|
*((__IO uint8_t *)&SPIx->DR) = TxData;
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1127,7 +1115,12 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
|
__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
|
||||||
{
|
{
|
||||||
|
#if defined (__GNUC__)
|
||||||
|
__IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
|
||||||
|
*spidr = TxData;
|
||||||
|
#else
|
||||||
SPIx->DR = TxData;
|
SPIx->DR = TxData;
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1313,16 +1306,16 @@ typedef struct
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
|
#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
|
#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
|
#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
|
#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
|
#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
|
#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
|
#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
|
#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
|
#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
|
#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -1407,7 +1400,7 @@ __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
|
return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1616,7 +1609,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
|
return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(SPI_I2SCFGR_ASTRTEN)
|
#if defined(SPI_I2SCFGR_ASTRTEN)
|
||||||
|
@ -1650,7 +1643,7 @@ __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
|
return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
#endif /* SPI_I2SCFGR_ASTRTEN */
|
#endif /* SPI_I2SCFGR_ASTRTEN */
|
||||||
|
|
||||||
|
@ -1714,7 +1707,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
|
return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1739,7 +1732,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
|
return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2031,6 +2024,6 @@ ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* __STM32F4xx_LL_SPI_H */
|
#endif /* STM32F4xx_LL_SPI_H */
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
@ -18,29 +18,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -215,7 +199,7 @@ typedef struct
|
||||||
|
|
||||||
/** @defgroup USART_LL_EC_PARITY Parity Control
|
/** @defgroup USART_LL_EC_PARITY Parity Control
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
|
#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
|
||||||
#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
|
#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
|
||||||
#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
|
#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
|
||||||
|
@ -1883,7 +1867,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
|
||||||
* @brief Clear Parity Error Flag
|
* @brief Clear Parity Error Flag
|
||||||
* @note Clearing this flag is done by a read access to the USARTx_SR
|
* @note Clearing this flag is done by a read access to the USARTx_SR
|
||||||
* register followed by a read access to the USARTx_DR register.
|
* register followed by a read access to the USARTx_DR register.
|
||||||
* @note Please also consider that when clearing this flag, other flags as
|
* @note Please also consider that when clearing this flag, other flags as
|
||||||
* NE, FE, ORE, IDLE would also be cleared.
|
* NE, FE, ORE, IDLE would also be cleared.
|
||||||
* @rmtoll SR PE LL_USART_ClearFlag_PE
|
* @rmtoll SR PE LL_USART_ClearFlag_PE
|
||||||
* @param USARTx USART Instance
|
* @param USARTx USART Instance
|
||||||
|
@ -1902,7 +1886,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
|
||||||
* @brief Clear Framing Error Flag
|
* @brief Clear Framing Error Flag
|
||||||
* @note Clearing this flag is done by a read access to the USARTx_SR
|
* @note Clearing this flag is done by a read access to the USARTx_SR
|
||||||
* register followed by a read access to the USARTx_DR register.
|
* register followed by a read access to the USARTx_DR register.
|
||||||
* @note Please also consider that when clearing this flag, other flags as
|
* @note Please also consider that when clearing this flag, other flags as
|
||||||
* PE, NE, ORE, IDLE would also be cleared.
|
* PE, NE, ORE, IDLE would also be cleared.
|
||||||
* @rmtoll SR FE LL_USART_ClearFlag_FE
|
* @rmtoll SR FE LL_USART_ClearFlag_FE
|
||||||
* @param USARTx USART Instance
|
* @param USARTx USART Instance
|
||||||
|
@ -1921,7 +1905,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
|
||||||
* @brief Clear Noise detected Flag
|
* @brief Clear Noise detected Flag
|
||||||
* @note Clearing this flag is done by a read access to the USARTx_SR
|
* @note Clearing this flag is done by a read access to the USARTx_SR
|
||||||
* register followed by a read access to the USARTx_DR register.
|
* register followed by a read access to the USARTx_DR register.
|
||||||
* @note Please also consider that when clearing this flag, other flags as
|
* @note Please also consider that when clearing this flag, other flags as
|
||||||
* PE, FE, ORE, IDLE would also be cleared.
|
* PE, FE, ORE, IDLE would also be cleared.
|
||||||
* @rmtoll SR NF LL_USART_ClearFlag_NE
|
* @rmtoll SR NF LL_USART_ClearFlag_NE
|
||||||
* @param USARTx USART Instance
|
* @param USARTx USART Instance
|
||||||
|
@ -1940,7 +1924,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
|
||||||
* @brief Clear OverRun Error Flag
|
* @brief Clear OverRun Error Flag
|
||||||
* @note Clearing this flag is done by a read access to the USARTx_SR
|
* @note Clearing this flag is done by a read access to the USARTx_SR
|
||||||
* register followed by a read access to the USARTx_DR register.
|
* register followed by a read access to the USARTx_DR register.
|
||||||
* @note Please also consider that when clearing this flag, other flags as
|
* @note Please also consider that when clearing this flag, other flags as
|
||||||
* PE, NE, FE, IDLE would also be cleared.
|
* PE, NE, FE, IDLE would also be cleared.
|
||||||
* @rmtoll SR ORE LL_USART_ClearFlag_ORE
|
* @rmtoll SR ORE LL_USART_ClearFlag_ORE
|
||||||
* @param USARTx USART Instance
|
* @param USARTx USART Instance
|
||||||
|
@ -1959,7 +1943,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
|
||||||
* @brief Clear IDLE line detected Flag
|
* @brief Clear IDLE line detected Flag
|
||||||
* @note Clearing this flag is done by a read access to the USARTx_SR
|
* @note Clearing this flag is done by a read access to the USARTx_SR
|
||||||
* register followed by a read access to the USARTx_DR register.
|
* register followed by a read access to the USARTx_DR register.
|
||||||
* @note Please also consider that when clearing this flag, other flags as
|
* @note Please also consider that when clearing this flag, other flags as
|
||||||
* PE, NE, FE, ORE would also be cleared.
|
* PE, NE, FE, ORE would also be cleared.
|
||||||
* @rmtoll SR IDLE LL_USART_ClearFlag_IDLE
|
* @rmtoll SR IDLE LL_USART_ClearFlag_IDLE
|
||||||
* @param USARTx USART Instance
|
* @param USARTx USART Instance
|
||||||
|
@ -1982,7 +1966,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
|
__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
|
||||||
{
|
{
|
||||||
WRITE_REG(USARTx->SR , ~(USART_SR_TC));
|
WRITE_REG(USARTx->SR, ~(USART_SR_TC));
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1993,7 +1977,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
|
__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
|
||||||
{
|
{
|
||||||
WRITE_REG(USARTx->SR , ~(USART_SR_RXNE));
|
WRITE_REG(USARTx->SR, ~(USART_SR_RXNE));
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2006,7 +1990,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
|
__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
|
||||||
{
|
{
|
||||||
WRITE_REG(USARTx->SR , ~(USART_SR_LBD));
|
WRITE_REG(USARTx->SR, ~(USART_SR_LBD));
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2019,7 +2003,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
|
__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
|
||||||
{
|
{
|
||||||
WRITE_REG(USARTx->SR , ~(USART_SR_CTS));
|
WRITE_REG(USARTx->SR, ~(USART_SR_CTS));
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2398,7 +2382,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
|
||||||
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
|
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
|
||||||
{
|
{
|
||||||
/* return address of DR register */
|
/* return address of DR register */
|
||||||
return ((uint32_t) &(USARTx->DR));
|
return ((uint32_t) & (USARTx->DR));
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -2,244 +2,228 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file stm32f4xx_ll_usb.h
|
* @file stm32f4xx_ll_usb.h
|
||||||
* @author MCD Application Team
|
* @author MCD Application Team
|
||||||
* @brief Header file of USB Core HAL module.
|
* @brief Header file of USB Low Layer HAL module.
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F4xx_LL_USB_H
|
#ifndef STM32F4xx_LL_USB_H
|
||||||
#define __STM32F4xx_LL_USB_H
|
#define STM32F4xx_LL_USB_H
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
|
|
||||||
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
|
|
||||||
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
|
|
||||||
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
|
|
||||||
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f4xx_hal_def.h"
|
#include "stm32f4xx_hal_def.h"
|
||||||
|
|
||||||
/** @addtogroup STM32F4xx_HAL
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
|
/** @addtogroup STM32F4xx_HAL_Driver
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup USB_Core
|
/** @addtogroup USB_LL
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief USB Mode definition
|
* @brief USB Mode definition
|
||||||
*/
|
*/
|
||||||
typedef enum
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
|
|
||||||
|
typedef enum
|
||||||
{
|
{
|
||||||
USB_OTG_DEVICE_MODE = 0U,
|
USB_DEVICE_MODE = 0,
|
||||||
USB_OTG_HOST_MODE = 1U,
|
USB_HOST_MODE = 1,
|
||||||
USB_OTG_DRD_MODE = 2U
|
USB_DRD_MODE = 2
|
||||||
|
} USB_OTG_ModeTypeDef;
|
||||||
}USB_OTG_ModeTypeDef;
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief URB States definition
|
* @brief URB States definition
|
||||||
*/
|
*/
|
||||||
typedef enum {
|
typedef enum
|
||||||
URB_IDLE = 0U,
|
{
|
||||||
|
URB_IDLE = 0,
|
||||||
URB_DONE,
|
URB_DONE,
|
||||||
URB_NOTREADY,
|
URB_NOTREADY,
|
||||||
URB_NYET,
|
URB_NYET,
|
||||||
URB_ERROR,
|
URB_ERROR,
|
||||||
URB_STALL
|
URB_STALL
|
||||||
|
} USB_OTG_URBStateTypeDef;
|
||||||
}USB_OTG_URBStateTypeDef;
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Host channel States definition
|
* @brief Host channel States definition
|
||||||
*/
|
*/
|
||||||
typedef enum {
|
typedef enum
|
||||||
HC_IDLE = 0U,
|
{
|
||||||
|
HC_IDLE = 0,
|
||||||
HC_XFRC,
|
HC_XFRC,
|
||||||
HC_HALTED,
|
HC_HALTED,
|
||||||
HC_NAK,
|
HC_NAK,
|
||||||
HC_NYET,
|
HC_NYET,
|
||||||
HC_STALL,
|
HC_STALL,
|
||||||
HC_XACTERR,
|
HC_XACTERR,
|
||||||
HC_BBLERR,
|
HC_BBLERR,
|
||||||
HC_DATATGLERR
|
HC_DATATGLERR
|
||||||
|
} USB_OTG_HCStateTypeDef;
|
||||||
}USB_OTG_HCStateTypeDef;
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief PCD Initialization Structure definition
|
* @brief USB OTG Initialization Structure definition
|
||||||
*/
|
*/
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
uint32_t dev_endpoints; /*!< Device Endpoints number.
|
uint32_t dev_endpoints; /*!< Device Endpoints number.
|
||||||
This parameter depends on the used USB core.
|
This parameter depends on the used USB core.
|
||||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
uint32_t Host_channels; /*!< Host Channels number.
|
uint32_t Host_channels; /*!< Host Channels number.
|
||||||
This parameter Depends on the used USB core.
|
This parameter Depends on the used USB core.
|
||||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
uint32_t speed; /*!< USB Core speed.
|
uint32_t speed; /*!< USB Core speed.
|
||||||
This parameter can be any value of @ref USB_Core_Speed_ */
|
This parameter can be any value of @ref USB_Core_Speed_ */
|
||||||
|
|
||||||
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */
|
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
|
||||||
|
|
||||||
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
|
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
|
||||||
This parameter can be any value of @ref USB_EP0_MPS_ */
|
|
||||||
|
|
||||||
uint32_t phy_itface; /*!< Select the used PHY interface.
|
uint32_t phy_itface; /*!< Select the used PHY interface.
|
||||||
This parameter can be any value of @ref USB_Core_PHY_ */
|
This parameter can be any value of @ref USB_Core_PHY_ */
|
||||||
|
|
||||||
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
|
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
|
||||||
|
|
||||||
uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
|
uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
|
||||||
|
|
||||||
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
|
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
|
||||||
|
|
||||||
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
|
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
|
||||||
|
|
||||||
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
|
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
|
||||||
|
|
||||||
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
|
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
|
||||||
|
|
||||||
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
|
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
|
||||||
|
} USB_OTG_CfgTypeDef;
|
||||||
|
|
||||||
}USB_OTG_CfgTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief OTG End Point Initialization Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
uint8_t num; /*!< Endpoint number
|
uint8_t num; /*!< Endpoint number
|
||||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
uint8_t is_in; /*!< Endpoint direction
|
uint8_t is_in; /*!< Endpoint direction
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
uint8_t is_stall; /*!< Endpoint stall condition
|
uint8_t is_stall; /*!< Endpoint stall condition
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
uint8_t type; /*!< Endpoint type
|
uint8_t type; /*!< Endpoint type
|
||||||
This parameter can be any value of @ref USB_EP_Type_ */
|
This parameter can be any value of @ref USB_EP_Type_ */
|
||||||
|
|
||||||
uint8_t data_pid_start; /*!< Initial data PID
|
uint8_t data_pid_start; /*!< Initial data PID
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
uint8_t even_odd_frame; /*!< IFrame parity
|
uint8_t even_odd_frame; /*!< IFrame parity
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
uint16_t tx_fifo_num; /*!< Transmission FIFO number
|
uint16_t tx_fifo_num; /*!< Transmission FIFO number
|
||||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
uint32_t maxpacket; /*!< Endpoint Max packet size
|
uint32_t maxpacket; /*!< Endpoint Max packet size
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
||||||
|
|
||||||
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
|
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
|
||||||
|
|
||||||
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
|
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
|
||||||
|
|
||||||
uint32_t xfer_len; /*!< Current transfer length */
|
uint32_t xfer_len; /*!< Current transfer length */
|
||||||
|
|
||||||
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
|
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
|
||||||
|
} USB_OTG_EPTypeDef;
|
||||||
|
|
||||||
}USB_OTG_EPTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief OTG HC Initialization Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
uint8_t dev_addr ; /*!< USB device address.
|
uint8_t dev_addr ; /*!< USB device address.
|
||||||
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
|
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
|
||||||
|
|
||||||
uint8_t ch_num; /*!< Host channel number.
|
uint8_t ch_num; /*!< Host channel number.
|
||||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
uint8_t ep_num; /*!< Endpoint number.
|
uint8_t ep_num; /*!< Endpoint number.
|
||||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
uint8_t ep_is_in; /*!< Endpoint direction
|
uint8_t ep_is_in; /*!< Endpoint direction
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
uint8_t speed; /*!< USB Host speed.
|
uint8_t speed; /*!< USB Host speed.
|
||||||
This parameter can be any value of @ref USB_Core_Speed_ */
|
This parameter can be any value of @ref USB_Core_Speed_ */
|
||||||
|
|
||||||
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
|
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
|
||||||
|
|
||||||
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
|
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
|
||||||
|
|
||||||
uint8_t ep_type; /*!< Endpoint Type.
|
uint8_t ep_type; /*!< Endpoint Type.
|
||||||
This parameter can be any value of @ref USB_EP_Type_ */
|
This parameter can be any value of @ref USB_EP_Type_ */
|
||||||
|
|
||||||
uint16_t max_packet; /*!< Endpoint Max packet size.
|
uint16_t max_packet; /*!< Endpoint Max packet size.
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
||||||
|
|
||||||
uint8_t data_pid; /*!< Initial data PID.
|
uint8_t data_pid; /*!< Initial data PID.
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
|
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
|
||||||
|
|
||||||
uint32_t xfer_len; /*!< Current transfer length. */
|
uint32_t xfer_len; /*!< Current transfer length. */
|
||||||
|
|
||||||
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
|
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
|
||||||
|
|
||||||
uint8_t toggle_in; /*!< IN transfer current toggle flag.
|
uint8_t toggle_in; /*!< IN transfer current toggle flag.
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
uint8_t toggle_out; /*!< OUT transfer current toggle flag
|
uint8_t toggle_out; /*!< OUT transfer current toggle flag
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
|
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
|
||||||
|
|
||||||
uint32_t ErrCnt; /*!< Host channel error count.*/
|
uint32_t ErrCnt; /*!< Host channel error count.*/
|
||||||
|
|
||||||
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
|
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
|
||||||
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
|
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
|
||||||
|
|
||||||
|
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
|
||||||
|
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
|
||||||
|
} USB_OTG_HCTypeDef;
|
||||||
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
|
|
||||||
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
|
|
||||||
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
|
|
||||||
|
|
||||||
}USB_OTG_HCTypeDef;
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
|
||||||
/** @defgroup PCD_Exported_Constants PCD Exported Constants
|
/** @defgroup PCD_Exported_Constants PCD Exported Constants
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
|
/** @defgroup USB_OTG_CORE VERSION ID
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USB_OTG_CORE_ID_300A 0x4F54300AU
|
||||||
|
#define USB_OTG_CORE_ID_310A 0x4F54310AU
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
/** @defgroup USB_Core_Mode_ USB Core Mode
|
/** @defgroup USB_Core_Mode_ USB Core Mode
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
@ -250,50 +234,75 @@ typedef struct
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup USB_Core_Speed_ USB Core Speed
|
/** @defgroup USB_LL Device Speed
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
#define USBD_HS_SPEED 0U
|
||||||
|
#define USBD_HSINFS_SPEED 1U
|
||||||
|
#define USBH_HS_SPEED 0U
|
||||||
|
#define USBD_FS_SPEED 2U
|
||||||
|
#define USBH_FS_SPEED 1U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
#define USB_OTG_SPEED_HIGH 0U
|
#define USB_OTG_SPEED_HIGH 0U
|
||||||
#define USB_OTG_SPEED_HIGH_IN_FULL 1U
|
#define USB_OTG_SPEED_HIGH_IN_FULL 1U
|
||||||
#define USB_OTG_SPEED_LOW 2U
|
|
||||||
#define USB_OTG_SPEED_FULL 3U
|
#define USB_OTG_SPEED_FULL 3U
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup USB_Core_PHY_ USB Core PHY
|
/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define USB_OTG_ULPI_PHY 1U
|
#define USB_OTG_ULPI_PHY 1U
|
||||||
#define USB_OTG_EMBEDDED_PHY 2U
|
#define USB_OTG_EMBEDDED_PHY 2U
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup USB_Core_MPS_ USB Core MPS
|
/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define USB_OTG_HS_MAX_PACKET_SIZE 512U
|
#ifndef USBD_HS_TRDT_VALUE
|
||||||
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
|
#define USBD_HS_TRDT_VALUE 9U
|
||||||
#define USB_OTG_MAX_EP0_SIZE 64U
|
#endif /* USBD_HS_TRDT_VALUE */
|
||||||
|
#ifndef USBD_FS_TRDT_VALUE
|
||||||
|
#define USBD_FS_TRDT_VALUE 5U
|
||||||
|
#define USBD_DEFAULT_TRDT_VALUE 9U
|
||||||
|
#endif /* USBD_HS_TRDT_VALUE */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency
|
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1U)
|
#define USB_OTG_HS_MAX_PACKET_SIZE 512U
|
||||||
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1U)
|
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
|
||||||
#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1U)
|
#define USB_OTG_MAX_EP0_SIZE 64U
|
||||||
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1U)
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval
|
/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
|
||||||
|
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
|
||||||
|
#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1)
|
||||||
|
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
#define DCFG_FRAME_INTERVAL_80 0U
|
#define DCFG_FRAME_INTERVAL_80 0U
|
||||||
#define DCFG_FRAME_INTERVAL_85 1U
|
#define DCFG_FRAME_INTERVAL_85 1U
|
||||||
#define DCFG_FRAME_INTERVAL_90 2U
|
#define DCFG_FRAME_INTERVAL_90 2U
|
||||||
|
@ -302,7 +311,7 @@ typedef struct
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup USB_EP0_MPS_ USB EP0 MPS
|
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define DEP0CTL_MPS_64 0U
|
#define DEP0CTL_MPS_64 0U
|
||||||
|
@ -313,7 +322,7 @@ typedef struct
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup USB_EP_Speed_ USB EP Speed
|
/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define EP_SPEED_LOW 0U
|
#define EP_SPEED_LOW 0U
|
||||||
|
@ -323,7 +332,7 @@ typedef struct
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup USB_EP_Type_ USB EP Type
|
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define EP_TYPE_CTRL 0U
|
#define EP_TYPE_CTRL 0U
|
||||||
|
@ -335,7 +344,7 @@ typedef struct
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup USB_STS_Defines_ USB STS Defines
|
/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define STS_GOUT_NAK 1U
|
#define STS_GOUT_NAK 1U
|
||||||
|
@ -347,31 +356,31 @@ typedef struct
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines
|
/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define HCFG_30_60_MHZ 0U
|
#define HCFG_30_60_MHZ 0U
|
||||||
#define HCFG_48_MHZ 1U
|
#define HCFG_48_MHZ 1U
|
||||||
#define HCFG_6_MHZ 2U
|
#define HCFG_6_MHZ 2U
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines
|
/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define HPRT0_PRTSPD_HIGH_SPEED 0U
|
#define HPRT0_PRTSPD_HIGH_SPEED 0U
|
||||||
#define HPRT0_PRTSPD_FULL_SPEED 1U
|
#define HPRT0_PRTSPD_FULL_SPEED 1U
|
||||||
#define HPRT0_PRTSPD_LOW_SPEED 2U
|
#define HPRT0_PRTSPD_LOW_SPEED 2U
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define HCCHAR_CTRL 0U
|
#define HCCHAR_CTRL 0U
|
||||||
#define HCCHAR_ISOC 1U
|
#define HCCHAR_ISOC 1U
|
||||||
#define HCCHAR_BULK 2U
|
#define HCCHAR_BULK 2U
|
||||||
#define HCCHAR_INTR 3U
|
#define HCCHAR_INTR 3U
|
||||||
|
|
||||||
#define HC_PID_DATA0 0U
|
#define HC_PID_DATA0 0U
|
||||||
#define HC_PID_DATA2 1U
|
#define HC_PID_DATA2 1U
|
||||||
#define HC_PID_DATA1 2U
|
#define HC_PID_DATA1 2U
|
||||||
|
@ -381,95 +390,122 @@ typedef struct
|
||||||
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
|
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
|
||||||
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
|
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
|
||||||
#define GRXSTS_PKTSTS_CH_HALTED 7U
|
#define GRXSTS_PKTSTS_CH_HALTED 7U
|
||||||
|
|
||||||
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
|
|
||||||
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
|
|
||||||
|
|
||||||
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE))
|
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
|
||||||
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
|
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
|
||||||
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
|
|
||||||
#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
|
|
||||||
|
|
||||||
#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
|
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
|
||||||
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
|
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
|
||||||
|
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
|
||||||
|
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
|
||||||
|
|
||||||
|
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
|
||||||
|
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
|
||||||
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
|
|
||||||
|
#define EP_ADDR_MSK 0xFU
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
|
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
|
||||||
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
|
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
|
||||||
|
|
||||||
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
|
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
|
||||||
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
|
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
|
||||||
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
/* Exported functions --------------------------------------------------------*/
|
||||||
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
|
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
|
||||||
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
|
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||||
|
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||||
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||||
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||||
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
|
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
|
||||||
HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
|
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
|
||||||
HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
|
HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
|
||||||
HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
|
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
|
||||||
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||||
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||||
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||||
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||||
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
|
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
|
||||||
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
|
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
|
||||||
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
|
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
|
||||||
void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
|
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||||
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
|
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||||
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
|
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||||
HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
|
HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
|
||||||
HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
|
HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
|
||||||
HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
|
HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
|
||||||
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
|
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
|
||||||
HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
|
HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
|
||||||
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
|
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
|
||||||
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
|
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
|
||||||
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
|
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
|
||||||
uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
|
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
|
||||||
uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
|
uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||||
uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
|
uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
|
||||||
uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
|
uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||||
uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
|
uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
|
||||||
void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
|
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
|
||||||
|
|
||||||
HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||||
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
|
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
|
||||||
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
|
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
|
||||||
HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
|
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
|
||||||
uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
|
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
|
||||||
uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
|
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
|
||||||
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
|
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
|
||||||
uint8_t ch_num,
|
uint8_t ch_num,
|
||||||
uint8_t epnum,
|
uint8_t epnum,
|
||||||
uint8_t dev_address,
|
uint8_t dev_address,
|
||||||
uint8_t speed,
|
uint8_t speed,
|
||||||
uint8_t ep_type,
|
uint8_t ep_type,
|
||||||
uint16_t mps);
|
uint16_t mps);
|
||||||
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
|
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
|
||||||
uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
|
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||||
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
|
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
|
||||||
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
|
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
|
||||||
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
|
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
|
||||||
/**
|
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
|
||||||
* @}
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
|
|
||||||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
|
/**
|
||||||
STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
#endif /* __STM32F4xx_LL_USB_H */
|
#endif /* STM32F4xx_LL_USB_H */
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
@ -18,29 +18,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -237,7 +221,7 @@ __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
||||||
{
|
{
|
||||||
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
|
return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -255,7 +239,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_GetPackageType(void)
|
__STATIC_INLINE uint32_t LL_GetPackageType(void)
|
||||||
{
|
{
|
||||||
return (uint8_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
|
return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -269,7 +253,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void)
|
||||||
/**
|
/**
|
||||||
* @brief This function configures the Cortex-M SysTick source of the time base.
|
* @brief This function configures the Cortex-M SysTick source of the time base.
|
||||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||||
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||||
* @param Ticks Number of ticks
|
* @param Ticks Number of ticks
|
||||||
* @retval None
|
* @retval None
|
||||||
|
|
|
@ -21,29 +21,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -66,11 +50,11 @@
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/**
|
/**
|
||||||
* @brief STM32F4xx HAL Driver version number V1.7.4
|
* @brief STM32F4xx HAL Driver version number V1.7.6
|
||||||
*/
|
*/
|
||||||
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||||
#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
|
#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
|
||||||
#define __STM32F4xx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
|
#define __STM32F4xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */
|
||||||
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||||
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|
||||||
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
|
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
|
||||||
|
@ -542,15 +526,30 @@ void HAL_DisableCompensationCell(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Return the unique device identifier (UID based on 96 bits)
|
* @brief Returns first word of the unique device identifier (UID based on 96 bits)
|
||||||
* @param UID pointer to 3 words array.
|
|
||||||
* @retval Device identifier
|
* @retval Device identifier
|
||||||
*/
|
*/
|
||||||
void HAL_GetUID(uint32_t *UID)
|
uint32_t HAL_GetUIDw0(void)
|
||||||
{
|
{
|
||||||
UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
|
return (READ_REG(*((uint32_t *)UID_BASE)));
|
||||||
UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
|
}
|
||||||
UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
|
|
||||||
|
/**
|
||||||
|
* @brief Returns second word of the unique device identifier (UID based on 96 bits)
|
||||||
|
* @retval Device identifier
|
||||||
|
*/
|
||||||
|
uint32_t HAL_GetUIDw1(void)
|
||||||
|
{
|
||||||
|
return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns third word of the unique device identifier (UID based on 96 bits)
|
||||||
|
* @retval Device identifier
|
||||||
|
*/
|
||||||
|
uint32_t HAL_GetUIDw2(void)
|
||||||
|
{
|
||||||
|
return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -68,29 +68,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -83,29 +83,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -367,13 +351,21 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||||
/* Get DMA steam Base Address */
|
/* Get DMA steam Base Address */
|
||||||
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
|
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
|
||||||
|
|
||||||
|
/* Clean all callbacks */
|
||||||
|
hdma->XferCpltCallback = NULL;
|
||||||
|
hdma->XferHalfCpltCallback = NULL;
|
||||||
|
hdma->XferM1CpltCallback = NULL;
|
||||||
|
hdma->XferM1HalfCpltCallback = NULL;
|
||||||
|
hdma->XferErrorCallback = NULL;
|
||||||
|
hdma->XferAbortCallback = NULL;
|
||||||
|
|
||||||
/* Clear all interrupt flags at correct offset within the register */
|
/* Clear all interrupt flags at correct offset within the register */
|
||||||
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
||||||
|
|
||||||
/* Initialize the error code */
|
/* Reset the error code */
|
||||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||||
|
|
||||||
/* Initialize the DMA state */
|
/* Reset the DMA state */
|
||||||
hdma->State = HAL_DMA_STATE_RESET;
|
hdma->State = HAL_DMA_STATE_RESET;
|
||||||
|
|
||||||
/* Release Lock */
|
/* Release Lock */
|
||||||
|
|
|
@ -25,29 +25,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -0,0 +1,440 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f4xx_hal_exti.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief EXTI HAL module driver.
|
||||||
|
* This file provides firmware functions to manage the following
|
||||||
|
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
|
||||||
|
* + Initialization and de-initialization functions
|
||||||
|
* + IO operation functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### EXTI Peripheral features #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
(+) Each Exti line can be configured within this driver.
|
||||||
|
|
||||||
|
(+) Exti line can be configured in 3 different modes
|
||||||
|
(++) Interrupt
|
||||||
|
(++) Event
|
||||||
|
(++) Both of them
|
||||||
|
|
||||||
|
(+) Configurable Exti lines can be configured with 3 different triggers
|
||||||
|
(++) Rising
|
||||||
|
(++) Falling
|
||||||
|
(++) Both of them
|
||||||
|
|
||||||
|
(+) When set in interrupt mode, configurable Exti lines have two different
|
||||||
|
interrupts pending registers which allow to distinguish which transition
|
||||||
|
occurs:
|
||||||
|
(++) Rising edge pending interrupt
|
||||||
|
(++) Falling
|
||||||
|
|
||||||
|
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
|
||||||
|
be selected through multiplexer.
|
||||||
|
|
||||||
|
##### How to use this driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
|
||||||
|
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
|
||||||
|
(++) Choose the interrupt line number by setting "Line" member from
|
||||||
|
EXTI_ConfigTypeDef structure.
|
||||||
|
(++) Configure the interrupt and/or event mode using "Mode" member from
|
||||||
|
EXTI_ConfigTypeDef structure.
|
||||||
|
(++) For configurable lines, configure rising and/or falling trigger
|
||||||
|
"Trigger" member from EXTI_ConfigTypeDef structure.
|
||||||
|
|
||||||
|
(#) Get current Exti configuration of a dedicated line using
|
||||||
|
HAL_EXTI_GetConfigLine().
|
||||||
|
(++) Provide exiting handle as parameter.
|
||||||
|
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
|
||||||
|
|
||||||
|
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
|
||||||
|
(++) Provide exiting handle as parameter.
|
||||||
|
|
||||||
|
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
|
||||||
|
(++) Provide exiting handle as first parameter.
|
||||||
|
(++) Provide which callback will be registered using one value from
|
||||||
|
EXTI_CallbackIDTypeDef.
|
||||||
|
(++) Provide callback function pointer.
|
||||||
|
|
||||||
|
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
|
||||||
|
|
||||||
|
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
|
||||||
|
|
||||||
|
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f4xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EXTI
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** MISRA C:2012 deviation rule has been granted for following rule:
|
||||||
|
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
|
||||||
|
* of bounds [0,3] in following API :
|
||||||
|
* HAL_EXTI_SetConfigLine
|
||||||
|
* HAL_EXTI_GetConfigLine
|
||||||
|
* HAL_EXTI_ClearConfigLine
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private defines -----------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup EXTI_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EXTI_Exported_Functions_Group1
|
||||||
|
* @brief Configuration functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### Configuration functions #####
|
||||||
|
===============================================================================
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set configuration of a dedicated Exti line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @param pExtiConfig Pointer on EXTI configuration to be set.
|
||||||
|
* @retval HAL Status.
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||||
|
{
|
||||||
|
uint32_t regval;
|
||||||
|
|
||||||
|
/* Check null pointer */
|
||||||
|
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check parameters */
|
||||||
|
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
|
||||||
|
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
|
||||||
|
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
|
||||||
|
|
||||||
|
/* Assign line number to handle */
|
||||||
|
hexti->Line = pExtiConfig->Line;
|
||||||
|
|
||||||
|
/* Clear EXTI line configuration */
|
||||||
|
EXTI->IMR &= ~pExtiConfig->Line;
|
||||||
|
EXTI->EMR &= ~pExtiConfig->Line;
|
||||||
|
|
||||||
|
/* Select the Mode for the selected external interrupts */
|
||||||
|
regval = (uint32_t)EXTI_BASE;
|
||||||
|
regval += pExtiConfig->Mode;
|
||||||
|
*(__IO uint32_t *) regval |= pExtiConfig->Line;
|
||||||
|
|
||||||
|
/* Clear Rising Falling edge configuration */
|
||||||
|
EXTI->RTSR &= ~pExtiConfig->Line;
|
||||||
|
EXTI->FTSR &= ~pExtiConfig->Line;
|
||||||
|
|
||||||
|
/* Select the trigger for the selected external interrupts */
|
||||||
|
if (pExtiConfig->Trigger == EXTI_TRIGGER_RISING_FALLING)
|
||||||
|
{
|
||||||
|
/* Rising Falling edge */
|
||||||
|
EXTI->RTSR |= pExtiConfig->Line;
|
||||||
|
EXTI->FTSR |= pExtiConfig->Line;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
regval = (uint32_t)EXTI_BASE;
|
||||||
|
regval += pExtiConfig->Trigger;
|
||||||
|
*(__IO uint32_t *) regval |= pExtiConfig->Line;
|
||||||
|
}
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get configuration of a dedicated Exti line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @param pExtiConfig Pointer on structure to store Exti configuration.
|
||||||
|
* @retval HAL Status.
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||||
|
{
|
||||||
|
/* Check null pointer */
|
||||||
|
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameter */
|
||||||
|
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||||
|
|
||||||
|
/* Store handle line number to configuration structure */
|
||||||
|
pExtiConfig->Line = hexti->Line;
|
||||||
|
|
||||||
|
/* Get EXTI mode to configiguration structure */
|
||||||
|
if ((EXTI->IMR & hexti->Line) == hexti->Line)
|
||||||
|
{
|
||||||
|
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
|
||||||
|
}
|
||||||
|
else if ((EXTI->EMR & hexti->Line) == hexti->Line)
|
||||||
|
{
|
||||||
|
pExtiConfig->Mode = EXTI_MODE_EVENT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* No MODE selected */
|
||||||
|
pExtiConfig->Mode = 0x0Bu;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get EXTI Trigger to configiguration structure */
|
||||||
|
if ((EXTI->RTSR & hexti->Line) == hexti->Line)
|
||||||
|
{
|
||||||
|
if ((EXTI->FTSR & hexti->Line) == hexti->Line)
|
||||||
|
{
|
||||||
|
pExtiConfig->Trigger = EXTI_TRIGGER_RISING_FALLING;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if ((EXTI->FTSR & hexti->Line) == hexti->Line)
|
||||||
|
{
|
||||||
|
pExtiConfig->Trigger = EXTI_TRIGGER_FALLING;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* No Trigger selected */
|
||||||
|
pExtiConfig->Trigger = 0x00u;
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear whole configuration of a dedicated Exti line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @retval HAL Status.
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
|
||||||
|
{
|
||||||
|
/* Check null pointer */
|
||||||
|
if (hexti == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameter */
|
||||||
|
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||||
|
|
||||||
|
/* 1] Clear interrupt mode */
|
||||||
|
EXTI->IMR = (EXTI->IMR & ~hexti->Line);
|
||||||
|
|
||||||
|
/* 2] Clear event mode */
|
||||||
|
EXTI->EMR = (EXTI->EMR & ~hexti->Line);
|
||||||
|
|
||||||
|
/* 3] Clear triggers */
|
||||||
|
EXTI->RTSR = (EXTI->RTSR & ~hexti->Line);
|
||||||
|
EXTI->FTSR = (EXTI->FTSR & ~hexti->Line);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Register callback for a dedicated Exti line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @param CallbackID User callback identifier.
|
||||||
|
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
|
||||||
|
* @param pPendingCbfn function pointer to be stored as callback.
|
||||||
|
* @retval HAL Status.
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
|
||||||
|
{
|
||||||
|
HAL_StatusTypeDef status = HAL_OK;
|
||||||
|
|
||||||
|
switch (CallbackID)
|
||||||
|
{
|
||||||
|
case HAL_EXTI_COMMON_CB_ID:
|
||||||
|
hexti->RisingCallback = pPendingCbfn;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
status = HAL_ERROR;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Store line number as handle private field.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @param ExtiLine Exti line number.
|
||||||
|
* This parameter can be from 0 to @ref EXTI_LINE_NB.
|
||||||
|
* @retval HAL Status.
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_EXTI_LINE(ExtiLine));
|
||||||
|
|
||||||
|
/* Check null pointer */
|
||||||
|
if (hexti == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Store line number as handle private field */
|
||||||
|
hexti->Line = ExtiLine;
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EXTI_Exported_Functions_Group2
|
||||||
|
* @brief EXTI IO functions.
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### IO operation functions #####
|
||||||
|
===============================================================================
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Handle EXTI interrupt request.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @retval none.
|
||||||
|
*/
|
||||||
|
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
|
||||||
|
{
|
||||||
|
if (EXTI->PR != 0x00u)
|
||||||
|
{
|
||||||
|
/* Clear pending bit */
|
||||||
|
EXTI->PR = hexti->Line;
|
||||||
|
|
||||||
|
/* Call callback */
|
||||||
|
if (hexti->RisingCallback != NULL)
|
||||||
|
{
|
||||||
|
hexti->RisingCallback();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get interrupt pending bit of a dedicated line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @param Edge Specify which pending edge as to be checked.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||||
|
* This parameter is kept for compatibility with other series.
|
||||||
|
* @retval 1 if interrupt is pending else 0.
|
||||||
|
*/
|
||||||
|
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||||
|
{
|
||||||
|
__IO uint32_t *regaddr;
|
||||||
|
uint32_t regval;
|
||||||
|
|
||||||
|
/* Check parameters */
|
||||||
|
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||||
|
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||||
|
|
||||||
|
/* Get pending bit */
|
||||||
|
regaddr = &EXTI->PR;
|
||||||
|
|
||||||
|
/* return 1 if bit is set else 0 */
|
||||||
|
regval = ((*regaddr & hexti->Line) >> POSITION_VAL(hexti->Line));
|
||||||
|
|
||||||
|
return regval;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear interrupt pending bit of a dedicated line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @param Edge Specify which pending edge as to be clear.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||||
|
* This parameter is kept for compatibility with other series.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||||
|
{
|
||||||
|
/* Check parameters */
|
||||||
|
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||||
|
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||||
|
|
||||||
|
EXTI->PR = hexti->Line;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Generate a software interrupt for a dedicated line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
|
||||||
|
{
|
||||||
|
/* Check parameters */
|
||||||
|
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||||
|
|
||||||
|
EXTI->SWIER = hexti->Line;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -63,29 +63,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -49,29 +49,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -1294,13 +1278,13 @@ static uint8_t FLASH_OB_GetRDP(void)
|
||||||
{
|
{
|
||||||
readstatus = OB_RDP_LEVEL_2;
|
readstatus = OB_RDP_LEVEL_2;
|
||||||
}
|
}
|
||||||
else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1))
|
else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0))
|
||||||
{
|
{
|
||||||
readstatus = OB_RDP_LEVEL_1;
|
readstatus = OB_RDP_LEVEL_0;
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
readstatus = OB_RDP_LEVEL_0;
|
readstatus = OB_RDP_LEVEL_1;
|
||||||
}
|
}
|
||||||
|
|
||||||
return readstatus;
|
return readstatus;
|
||||||
|
|
|
@ -34,29 +34,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -93,29 +93,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -329,22 +313,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||||
|
|
||||||
if(iocurrent == ioposition)
|
if(iocurrent == ioposition)
|
||||||
{
|
{
|
||||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
|
||||||
/* Configure IO Direction in Input Floating Mode */
|
|
||||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
|
|
||||||
|
|
||||||
/* Configure the default Alternate Function in current IO */
|
|
||||||
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
|
|
||||||
|
|
||||||
/* Configure the default value for IO Speed */
|
|
||||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
|
|
||||||
|
|
||||||
/* Configure the default value IO Output Type */
|
|
||||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
||||||
|
|
||||||
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
|
||||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
|
||||||
|
|
||||||
/*------------------------- EXTI Mode Configuration --------------------*/
|
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||||
tmp = SYSCFG->EXTICR[position >> 2U];
|
tmp = SYSCFG->EXTICR[position >> 2U];
|
||||||
tmp &= (0x0FU << (4U * (position & 0x03U)));
|
tmp &= (0x0FU << (4U * (position & 0x03U)));
|
||||||
|
@ -362,6 +330,22 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||||
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
||||||
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||||
|
/* Configure IO Direction in Input Floating Mode */
|
||||||
|
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
|
||||||
|
|
||||||
|
/* Configure the default Alternate Function in current IO */
|
||||||
|
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
|
||||||
|
|
||||||
|
/* Configure the default value for IO Speed */
|
||||||
|
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
|
||||||
|
|
||||||
|
/* Configure the default value IO Output Type */
|
||||||
|
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||||
|
|
||||||
|
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
||||||
|
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -453,7 +437,14 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||||
/* Check the parameters */
|
/* Check the parameters */
|
||||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||||
|
|
||||||
GPIOx->ODR ^= GPIO_Pin;
|
if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
|
||||||
|
{
|
||||||
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
GPIOx->BSRR = GPIO_Pin;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -2,40 +2,24 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file stm32f4xx_hal_pcd_ex.c
|
* @file stm32f4xx_hal_pcd_ex.c
|
||||||
* @author MCD Application Team
|
* @author MCD Application Team
|
||||||
* @brief PCD HAL module driver.
|
* @brief PCD Extended HAL module driver.
|
||||||
* This file provides firmware functions to manage the following
|
* This file provides firmware functions to manage the following
|
||||||
* functionalities of the USB Peripheral Controller:
|
* functionalities of the USB Peripheral Controller:
|
||||||
* + Extended features functions
|
* + Extended features functions
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f4xx_hal.h"
|
#include "stm32f4xx_hal.h"
|
||||||
|
@ -48,12 +32,10 @@
|
||||||
* @brief PCD Extended HAL module driver
|
* @brief PCD Extended HAL module driver
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifdef HAL_PCD_MODULE_ENABLED
|
#ifdef HAL_PCD_MODULE_ENABLED
|
||||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
|
|
||||||
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
|
|
||||||
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
|
|
||||||
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
|
||||||
/* Private types -------------------------------------------------------------*/
|
/* Private types -------------------------------------------------------------*/
|
||||||
/* Private variables ---------------------------------------------------------*/
|
/* Private variables ---------------------------------------------------------*/
|
||||||
/* Private constants ---------------------------------------------------------*/
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
@ -61,24 +43,24 @@
|
||||||
/* Private functions ---------------------------------------------------------*/
|
/* Private functions ---------------------------------------------------------*/
|
||||||
/* Exported functions --------------------------------------------------------*/
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
/** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions
|
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||||
* @brief PCDEx control functions
|
* @brief PCDEx control functions
|
||||||
*
|
*
|
||||||
@verbatim
|
@verbatim
|
||||||
===============================================================================
|
===============================================================================
|
||||||
##### Extended features functions #####
|
##### Extended features functions #####
|
||||||
===============================================================================
|
===============================================================================
|
||||||
[..] This section provides functions allowing to:
|
[..] This section provides functions allowing to:
|
||||||
(+) Update FIFO configuration
|
(+) Update FIFO configuration
|
||||||
|
|
||||||
@endverbatim
|
@endverbatim
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||||
/**
|
/**
|
||||||
* @brief Set Tx FIFO
|
* @brief Set Tx FIFO
|
||||||
* @param hpcd PCD handle
|
* @param hpcd PCD handle
|
||||||
|
@ -88,37 +70,37 @@
|
||||||
*/
|
*/
|
||||||
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
|
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
|
||||||
{
|
{
|
||||||
uint8_t i = 0;
|
uint8_t i;
|
||||||
uint32_t Tx_Offset = 0U;
|
uint32_t Tx_Offset;
|
||||||
|
|
||||||
/* TXn min size = 16 words. (n : Transmit FIFO index)
|
/* TXn min size = 16 words. (n : Transmit FIFO index)
|
||||||
When a TxFIFO is not used, the Configuration should be as follows:
|
When a TxFIFO is not used, the Configuration should be as follows:
|
||||||
case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
|
case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
|
||||||
--> Txm can use the space allocated for Txn.
|
--> Txm can use the space allocated for Txn.
|
||||||
case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
|
case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
|
||||||
--> Txn should be configured with the minimum space of 16 words
|
--> Txn should be configured with the minimum space of 16 words
|
||||||
The FIFO is used optimally when used TxFIFOs are allocated in the top
|
The FIFO is used optimally when used TxFIFOs are allocated in the top
|
||||||
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
|
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
|
||||||
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
|
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
|
||||||
|
|
||||||
Tx_Offset = hpcd->Instance->GRXFSIZ;
|
Tx_Offset = hpcd->Instance->GRXFSIZ;
|
||||||
|
|
||||||
if(fifo == 0)
|
if (fifo == 0U)
|
||||||
{
|
{
|
||||||
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
|
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U;
|
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
|
||||||
for (i = 0; i < (fifo - 1); i++)
|
for (i = 0U; i < (fifo - 1U); i++)
|
||||||
{
|
{
|
||||||
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16U);
|
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Multiply Tx_Size by 2 to get higher performance */
|
/* Multiply Tx_Size by 2 to get higher performance */
|
||||||
hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
|
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
|
||||||
}
|
}
|
||||||
|
|
||||||
return HAL_OK;
|
return HAL_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -131,27 +113,25 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
|
||||||
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
|
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
|
||||||
{
|
{
|
||||||
hpcd->Instance->GRXFSIZ = size;
|
hpcd->Instance->GRXFSIZ = size;
|
||||||
|
|
||||||
return HAL_OK;
|
return HAL_OK;
|
||||||
}
|
}
|
||||||
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
|
|
||||||
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
|
||||||
/**
|
/**
|
||||||
* @brief Activate LPM feature
|
* @brief Activate LPM feature.
|
||||||
* @param hpcd PCD handle
|
* @param hpcd PCD handle
|
||||||
* @retval HAL status
|
* @retval HAL status
|
||||||
*/
|
*/
|
||||||
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
||||||
{
|
{
|
||||||
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
||||||
|
|
||||||
hpcd->lpm_active = ENABLE;
|
hpcd->lpm_active = 1U;
|
||||||
hpcd->LPM_State = LPM_L0;
|
hpcd->LPM_State = LPM_L0;
|
||||||
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
|
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
|
||||||
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
|
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
|
||||||
|
|
||||||
return HAL_OK;
|
return HAL_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -161,14 +141,157 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
||||||
*/
|
*/
|
||||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
|
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
|
||||||
{
|
{
|
||||||
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
||||||
|
|
||||||
hpcd->lpm_active = DISABLE;
|
hpcd->lpm_active = 0U;
|
||||||
USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
|
USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
|
||||||
USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
|
USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
|
||||||
|
|
||||||
return HAL_OK;
|
return HAL_OK;
|
||||||
}
|
}
|
||||||
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
|
||||||
|
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
|
/**
|
||||||
|
* @brief Handle BatteryCharging Process.
|
||||||
|
* @param hpcd PCD handle
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
|
||||||
|
{
|
||||||
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
||||||
|
uint32_t tickstart = HAL_GetTick();
|
||||||
|
|
||||||
|
/* Enable DCD : Data Contact Detect */
|
||||||
|
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
|
||||||
|
|
||||||
|
/* Wait Detect flag or a timeout is happen*/
|
||||||
|
while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
|
||||||
|
{
|
||||||
|
/* Check for the Timeout */
|
||||||
|
if ((HAL_GetTick() - tickstart) > 1000U)
|
||||||
|
{
|
||||||
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||||
|
hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
|
||||||
|
#else
|
||||||
|
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
|
||||||
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Right response got */
|
||||||
|
HAL_Delay(200U);
|
||||||
|
|
||||||
|
/* Check Detect flag*/
|
||||||
|
if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
|
||||||
|
{
|
||||||
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||||
|
hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
|
||||||
|
#else
|
||||||
|
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
|
||||||
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*Primary detection: checks if connected to Standard Downstream Port
|
||||||
|
(without charging capability) */
|
||||||
|
USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
|
||||||
|
HAL_Delay(50U);
|
||||||
|
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
|
||||||
|
HAL_Delay(50U);
|
||||||
|
|
||||||
|
if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
|
||||||
|
{
|
||||||
|
/* Case of Standard Downstream Port */
|
||||||
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||||
|
hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
|
||||||
|
#else
|
||||||
|
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
|
||||||
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* start secondary detection to check connection to Charging Downstream
|
||||||
|
Port or Dedicated Charging Port */
|
||||||
|
USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
|
||||||
|
HAL_Delay(50U);
|
||||||
|
USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
|
||||||
|
HAL_Delay(50U);
|
||||||
|
|
||||||
|
if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
|
||||||
|
{
|
||||||
|
/* case Dedicated Charging Port */
|
||||||
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||||
|
hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
|
||||||
|
#else
|
||||||
|
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
|
||||||
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* case Charging Downstream Port */
|
||||||
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||||
|
hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
|
||||||
|
#else
|
||||||
|
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
|
||||||
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Battery Charging capability discovery finished */
|
||||||
|
(void)HAL_PCDEx_DeActivateBCD(hpcd);
|
||||||
|
|
||||||
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||||
|
hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
|
||||||
|
#else
|
||||||
|
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
|
||||||
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Activate BatteryCharging feature.
|
||||||
|
* @param hpcd PCD handle
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
|
||||||
|
{
|
||||||
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
||||||
|
|
||||||
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
|
||||||
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
|
||||||
|
|
||||||
|
/* Power Down USB tranceiver */
|
||||||
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
||||||
|
|
||||||
|
/* Enable Battery charging */
|
||||||
|
USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;
|
||||||
|
|
||||||
|
hpcd->battery_charging_active = 1U;
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deactivate BatteryCharging feature.
|
||||||
|
* @param hpcd PCD handle
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
|
||||||
|
{
|
||||||
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
||||||
|
|
||||||
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
|
||||||
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
|
||||||
|
|
||||||
|
/* Disable Battery charging */
|
||||||
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
|
||||||
|
|
||||||
|
hpcd->battery_charging_active = 0U;
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
|
||||||
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Send LPM message to user layer callback.
|
* @brief Send LPM message to user layer callback.
|
||||||
|
@ -181,111 +304,14 @@ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef m
|
||||||
/* Prevent unused argument(s) compilation warning */
|
/* Prevent unused argument(s) compilation warning */
|
||||||
UNUSED(hpcd);
|
UNUSED(hpcd);
|
||||||
UNUSED(msg);
|
UNUSED(msg);
|
||||||
}
|
|
||||||
#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
|
|
||||||
|
|
||||||
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
|
/* NOTE : This function should not be modified, when the callback is needed,
|
||||||
/**
|
the HAL_PCDEx_LPM_Callback could be implemented in the user file
|
||||||
* @brief HAL_PCDEx_BCD_VBUSDetect : handle BatteryCharging Process
|
*/
|
||||||
* @param hpcd PCD handle
|
|
||||||
* @retval HAL status
|
|
||||||
*/
|
|
||||||
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
|
|
||||||
{
|
|
||||||
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
||||||
uint32_t tickstart = HAL_GetTick();
|
|
||||||
|
|
||||||
/* Start BCD When device is connected */
|
|
||||||
if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS)
|
|
||||||
{
|
|
||||||
/* Enable DCD : Data Contact Detect */
|
|
||||||
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
|
|
||||||
|
|
||||||
/* Wait Detect flag or a timeout is happen*/
|
|
||||||
while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
|
|
||||||
{
|
|
||||||
/* Check for the Timeout */
|
|
||||||
if((HAL_GetTick() - tickstart ) > 1000U)
|
|
||||||
{
|
|
||||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Right response got */
|
|
||||||
HAL_Delay(100U);
|
|
||||||
|
|
||||||
/* Check Detect flag*/
|
|
||||||
if (USBx->GCCFG & USB_OTG_GCCFG_DCDET)
|
|
||||||
{
|
|
||||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*Primary detection: checks if connected to Standard Downstream Port
|
|
||||||
(without charging capability) */
|
|
||||||
USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN;
|
|
||||||
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
|
|
||||||
HAL_Delay(100U);
|
|
||||||
|
|
||||||
if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET))
|
|
||||||
{
|
|
||||||
/* Case of Standard Downstream Port */
|
|
||||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* start secondary detection to check connection to Charging Downstream
|
|
||||||
Port or Dedicated Charging Port */
|
|
||||||
USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN;
|
|
||||||
USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
|
|
||||||
HAL_Delay(100U);
|
|
||||||
|
|
||||||
if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET)
|
|
||||||
{
|
|
||||||
/* case Dedicated Charging Port */
|
|
||||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* case Charging Downstream Port */
|
|
||||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* Battery Charging capability discovery finished */
|
|
||||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief HAL_PCDEx_ActivateBCD : active BatteryCharging feature
|
* @brief Send BatteryCharging message to user layer callback.
|
||||||
* @param hpcd PCD handle
|
|
||||||
* @retval HAL status
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
|
|
||||||
{
|
|
||||||
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
||||||
|
|
||||||
hpcd->battery_charging_active = ENABLE;
|
|
||||||
USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN);
|
|
||||||
|
|
||||||
return HAL_OK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL_PCDEx_DeActivateBCD : de-active BatteryCharging feature
|
|
||||||
* @param hpcd PCD handle
|
|
||||||
* @retval HAL status
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
|
|
||||||
{
|
|
||||||
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
||||||
hpcd->battery_charging_active = DISABLE;
|
|
||||||
USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
|
|
||||||
return HAL_OK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL_PCDEx_BatteryCharging_Callback : Send BatteryCharging message to user layer
|
|
||||||
* @param hpcd PCD handle
|
* @param hpcd PCD handle
|
||||||
* @param msg LPM message
|
* @param msg LPM message
|
||||||
* @retval HAL status
|
* @retval HAL status
|
||||||
|
@ -295,10 +321,12 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m
|
||||||
/* Prevent unused argument(s) compilation warning */
|
/* Prevent unused argument(s) compilation warning */
|
||||||
UNUSED(hpcd);
|
UNUSED(hpcd);
|
||||||
UNUSED(msg);
|
UNUSED(msg);
|
||||||
|
|
||||||
|
/* NOTE : This function should not be modified, when the callback is needed,
|
||||||
|
the HAL_PCDEx_BCD_Callback could be implemented in the user file
|
||||||
|
*/
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -306,11 +334,9 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
|
|
||||||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
|
|
||||||
STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
|
|
||||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -11,29 +11,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -10,29 +10,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -365,26 +349,6 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
||||||
}
|
}
|
||||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
||||||
|
|
||||||
#if defined(STM32F469xx) || defined(STM32F479xx)
|
|
||||||
/**
|
|
||||||
* @brief Enables Wakeup Pin Detection on high level (rising edge).
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void)
|
|
||||||
{
|
|
||||||
*(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables Wakeup Pin Detection on low level (falling edge).
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void)
|
|
||||||
{
|
|
||||||
*(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE;
|
|
||||||
}
|
|
||||||
#endif /* STM32F469xx || STM32F479xx */
|
|
||||||
|
|
||||||
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
|
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
|
||||||
defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
|
defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
|
||||||
defined(STM32F413xx) || defined(STM32F423xx)
|
defined(STM32F413xx) || defined(STM32F423xx)
|
||||||
|
|
|
@ -54,29 +54,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -10,29 +10,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -222,7 +206,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
|
||||||
/**
|
/**
|
||||||
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
|
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
|
||||||
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
|
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
|
||||||
* SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
* SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
||||||
* @param SPIx SPI Instance
|
* @param SPIx SPI Instance
|
||||||
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
|
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
|
||||||
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
|
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
|
||||||
|
@ -406,7 +390,7 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
|
||||||
/**
|
/**
|
||||||
* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
|
* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
|
||||||
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
|
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
|
||||||
* SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
* SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
||||||
* @param SPIx SPI Instance
|
* @param SPIx SPI Instance
|
||||||
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
|
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
|
||||||
* @retval An ErrorStatus enumeration value:
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
@ -415,9 +399,9 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
|
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
|
||||||
{
|
{
|
||||||
uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
|
uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
|
||||||
uint32_t tmp = 0U;
|
uint32_t tmp;
|
||||||
uint32_t sourceclock = 0U;
|
uint32_t sourceclock;
|
||||||
ErrorStatus status = ERROR;
|
ErrorStatus status = ERROR;
|
||||||
|
|
||||||
/* Check the I2S parameters */
|
/* Check the I2S parameters */
|
||||||
|
@ -475,25 +459,25 @@ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
|
||||||
if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
|
if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
|
||||||
{
|
{
|
||||||
/* MCLK output is enabled */
|
/* MCLK output is enabled */
|
||||||
tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
|
tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
/* MCLK output is disabled */
|
/* MCLK output is disabled */
|
||||||
tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
|
tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Remove the floating point */
|
/* Remove the floating point */
|
||||||
tmp = tmp / 10U;
|
tmp = tmp / 10U;
|
||||||
|
|
||||||
/* Check the parity of the divider */
|
/* Check the parity of the divider */
|
||||||
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
|
i2sodd = (tmp & (uint16_t)0x0001U);
|
||||||
|
|
||||||
/* Compute the i2sdiv prescaler */
|
/* Compute the i2sdiv prescaler */
|
||||||
i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
|
i2sdiv = ((tmp - i2sodd) / 2U);
|
||||||
|
|
||||||
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
|
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
|
||||||
i2sodd = (uint16_t)(i2sodd << 8U);
|
i2sodd = (i2sodd << 8U);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Test if the divider is 1 or 0 or greater than 0xFF */
|
/* Test if the divider is 1 or 0 or greater than 0xFF */
|
||||||
|
@ -568,7 +552,7 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_
|
||||||
*/
|
*/
|
||||||
ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
|
ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
|
||||||
{
|
{
|
||||||
uint16_t mode = 0U;
|
uint32_t mode = 0U;
|
||||||
ErrorStatus status = ERROR;
|
ErrorStatus status = ERROR;
|
||||||
|
|
||||||
/* Check the I2S parameters */
|
/* Check the I2S parameters */
|
||||||
|
|
|
@ -6,32 +6,17 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(USE_FULL_LL_DRIVER)
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
@ -402,8 +387,8 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
|
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
|
||||||
* @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
|
* @param USART_InitStruct Pointer to a @ref LL_USART_InitTypeDef structure
|
||||||
* whose fields will be set to default values.
|
* whose fields will be set to default values.
|
||||||
* @retval None
|
* @retval None
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
@ -425,7 +410,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
|
||||||
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
|
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
|
||||||
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
||||||
* @param USARTx USART Instance
|
* @param USARTx USART Instance
|
||||||
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
|
* @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
|
||||||
* that contains the Clock configuration information for the specified USART peripheral.
|
* that contains the Clock configuration information for the specified USART peripheral.
|
||||||
* @retval An ErrorStatus enumeration value:
|
* @retval An ErrorStatus enumeration value:
|
||||||
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
|
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
|
||||||
|
@ -486,8 +471,8 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
|
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
|
||||||
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
|
* @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
|
||||||
* whose fields will be set to default values.
|
* whose fields will be set to default values.
|
||||||
* @retval None
|
* @retval None
|
||||||
*/
|
*/
|
||||||
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
|
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -152,7 +152,6 @@ void send_initial_clock_train(void)
|
||||||
/*-----------------------------------------------------------------------*/
|
/*-----------------------------------------------------------------------*/
|
||||||
/* When the target system does not support socket power control, there */
|
/* When the target system does not support socket power control, there */
|
||||||
/* is nothing to do in these functions. */
|
/* is nothing to do in these functions. */
|
||||||
|
|
||||||
static
|
static
|
||||||
void power_on (void)
|
void power_on (void)
|
||||||
{
|
{
|
||||||
|
|
|
@ -92,6 +92,7 @@
|
||||||
/* #define HAL_LPTIM_MODULE_ENABLED */
|
/* #define HAL_LPTIM_MODULE_ENABLED */
|
||||||
/* #define HAL_EXTI_MODULE_ENABLED */
|
/* #define HAL_EXTI_MODULE_ENABLED */
|
||||||
#define HAL_GPIO_MODULE_ENABLED
|
#define HAL_GPIO_MODULE_ENABLED
|
||||||
|
#define HAL_EXTI_MODULE_ENABLED
|
||||||
#define HAL_DMA_MODULE_ENABLED
|
#define HAL_DMA_MODULE_ENABLED
|
||||||
#define HAL_RCC_MODULE_ENABLED
|
#define HAL_RCC_MODULE_ENABLED
|
||||||
#define HAL_FLASH_MODULE_ENABLED
|
#define HAL_FLASH_MODULE_ENABLED
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -122,11 +122,11 @@
|
||||||
#endif /* USE_HAL_DRIVER */
|
#endif /* USE_HAL_DRIVER */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief CMSIS version number V2.6.2
|
* @brief CMSIS version number V2.6.3
|
||||||
*/
|
*/
|
||||||
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
|
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
|
||||||
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
|
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
|
||||||
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
|
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
|
||||||
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||||
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|
||||||
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
|
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
|
||||||
|
@ -211,10 +211,10 @@ typedef enum
|
||||||
} FunctionalState;
|
} FunctionalState;
|
||||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||||
|
|
||||||
typedef enum
|
typedef enum
|
||||||
{
|
{
|
||||||
ERROR = 0U,
|
SUCCESS = 0U,
|
||||||
SUCCESS = !ERROR
|
ERROR = !SUCCESS
|
||||||
} ErrorStatus;
|
} ErrorStatus;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -1,136 +0,0 @@
|
||||||
/* ----------------------------------------------------------------------
|
|
||||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* $Date: 19. October 2015
|
|
||||||
* $Revision: V.1.4.5 a
|
|
||||||
*
|
|
||||||
* Project: CMSIS DSP Library
|
|
||||||
* Title: arm_common_tables.h
|
|
||||||
*
|
|
||||||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
|
|
||||||
*
|
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
* - Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* - Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this
|
|
||||||
* software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
#ifndef _ARM_COMMON_TABLES_H
|
|
||||||
#define _ARM_COMMON_TABLES_H
|
|
||||||
|
|
||||||
#include "arm_math.h"
|
|
||||||
|
|
||||||
extern const uint16_t armBitRevTable[1024];
|
|
||||||
extern const q15_t armRecipTableQ15[64];
|
|
||||||
extern const q31_t armRecipTableQ31[64];
|
|
||||||
/* extern const q31_t realCoefAQ31[1024]; */
|
|
||||||
/* extern const q31_t realCoefBQ31[1024]; */
|
|
||||||
extern const float32_t twiddleCoef_16[32];
|
|
||||||
extern const float32_t twiddleCoef_32[64];
|
|
||||||
extern const float32_t twiddleCoef_64[128];
|
|
||||||
extern const float32_t twiddleCoef_128[256];
|
|
||||||
extern const float32_t twiddleCoef_256[512];
|
|
||||||
extern const float32_t twiddleCoef_512[1024];
|
|
||||||
extern const float32_t twiddleCoef_1024[2048];
|
|
||||||
extern const float32_t twiddleCoef_2048[4096];
|
|
||||||
extern const float32_t twiddleCoef_4096[8192];
|
|
||||||
#define twiddleCoef twiddleCoef_4096
|
|
||||||
extern const q31_t twiddleCoef_16_q31[24];
|
|
||||||
extern const q31_t twiddleCoef_32_q31[48];
|
|
||||||
extern const q31_t twiddleCoef_64_q31[96];
|
|
||||||
extern const q31_t twiddleCoef_128_q31[192];
|
|
||||||
extern const q31_t twiddleCoef_256_q31[384];
|
|
||||||
extern const q31_t twiddleCoef_512_q31[768];
|
|
||||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
|
||||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
|
||||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
|
||||||
extern const q15_t twiddleCoef_16_q15[24];
|
|
||||||
extern const q15_t twiddleCoef_32_q15[48];
|
|
||||||
extern const q15_t twiddleCoef_64_q15[96];
|
|
||||||
extern const q15_t twiddleCoef_128_q15[192];
|
|
||||||
extern const q15_t twiddleCoef_256_q15[384];
|
|
||||||
extern const q15_t twiddleCoef_512_q15[768];
|
|
||||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
|
||||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
|
||||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
|
||||||
extern const float32_t twiddleCoef_rfft_32[32];
|
|
||||||
extern const float32_t twiddleCoef_rfft_64[64];
|
|
||||||
extern const float32_t twiddleCoef_rfft_128[128];
|
|
||||||
extern const float32_t twiddleCoef_rfft_256[256];
|
|
||||||
extern const float32_t twiddleCoef_rfft_512[512];
|
|
||||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
|
||||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
|
||||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
|
||||||
|
|
||||||
|
|
||||||
/* floating-point bit reversal tables */
|
|
||||||
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
|
|
||||||
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
|
|
||||||
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
|
|
||||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
|
|
||||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
|
|
||||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
|
|
||||||
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
|
|
||||||
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
|
|
||||||
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
|
|
||||||
|
|
||||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
|
|
||||||
|
|
||||||
/* fixed-point bit reversal tables */
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
|
||||||
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
|
||||||
|
|
||||||
/* Tables for Fast Math Sine and Cosine */
|
|
||||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
|
||||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
|
||||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
|
||||||
|
|
||||||
#endif /* ARM_COMMON_TABLES_H */
|
|
|
@ -1,79 +0,0 @@
|
||||||
/* ----------------------------------------------------------------------
|
|
||||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* $Date: 19. March 2015
|
|
||||||
* $Revision: V.1.4.5
|
|
||||||
*
|
|
||||||
* Project: CMSIS DSP Library
|
|
||||||
* Title: arm_const_structs.h
|
|
||||||
*
|
|
||||||
* Description: This file has constant structs that are initialized for
|
|
||||||
* user convenience. For example, some can be given as
|
|
||||||
* arguments to the arm_cfft_f32() function.
|
|
||||||
*
|
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
* - Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* - Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this
|
|
||||||
* software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
#ifndef _ARM_CONST_STRUCTS_H
|
|
||||||
#define _ARM_CONST_STRUCTS_H
|
|
||||||
|
|
||||||
#include "arm_math.h"
|
|
||||||
#include "arm_common_tables.h"
|
|
||||||
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
|
||||||
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
|
||||||
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
|
||||||
|
|
||||||
#endif
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,43 +1,104 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file cmsis_armcc.h
|
* @file cmsis_armcc.h
|
||||||
* @brief CMSIS Cortex-M Core Function/Instruction Header File
|
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||||
* @version V4.30
|
* @version V5.0.4
|
||||||
* @date 20. October 2015
|
* @date 10. January 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#ifndef __CMSIS_ARMCC_H
|
#ifndef __CMSIS_ARMCC_H
|
||||||
#define __CMSIS_ARMCC_H
|
#define __CMSIS_ARMCC_H
|
||||||
|
|
||||||
|
|
||||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CMSIS compiler control architecture macros */
|
||||||
|
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||||
|
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||||
|
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||||
|
|
||||||
|
|
||||||
|
/* CMSIS compiler specific defines */
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE static __forceinline
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __declspec(noreturn)
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT __packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION __packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* ########################### Core Function Access ########################### */
|
/* ########################### Core Function Access ########################### */
|
||||||
|
@ -46,7 +107,19 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable IRQ Interrupts
|
||||||
|
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
/* intrinsic void __enable_irq(); */
|
/* intrinsic void __enable_irq(); */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable IRQ Interrupts
|
||||||
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
/* intrinsic void __disable_irq(); */
|
/* intrinsic void __disable_irq(); */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -181,7 +254,8 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable FIQ
|
\brief Enable FIQ
|
||||||
|
@ -256,14 +330,13 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
{
|
{
|
||||||
register uint32_t __regFaultMask __ASM("faultmask");
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
__regFaultMask = (faultMask & (uint32_t)1);
|
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get FPSCR
|
\brief Get FPSCR
|
||||||
\details Returns the current value of the Floating Point Status/Control register.
|
\details Returns the current value of the Floating Point Status/Control register.
|
||||||
|
@ -271,7 +344,8 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
{
|
{
|
||||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
register uint32_t __regfpscr __ASM("fpscr");
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
return(__regfpscr);
|
return(__regfpscr);
|
||||||
#else
|
#else
|
||||||
|
@ -287,15 +361,15 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
{
|
{
|
||||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
register uint32_t __regfpscr __ASM("fpscr");
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
__regfpscr = (fpscr);
|
__regfpscr = (fpscr);
|
||||||
|
#else
|
||||||
|
(void)fpscr;
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||||
|
|
||||||
|
@ -369,9 +443,10 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
__schedule_barrier();\
|
__schedule_barrier();\
|
||||||
} while (0U)
|
} while (0U)
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Reverse byte order (32 bit)
|
\brief Reverse byte order (32 bit)
|
||||||
\details Reverses the byte order in integer value.
|
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
|
@ -380,7 +455,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Reverse byte order (16 bit)
|
\brief Reverse byte order (16 bit)
|
||||||
\details Reverses the byte order in two unsigned short values.
|
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
|
@ -392,14 +467,15 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Reverse byte order in signed short value
|
\brief Reverse byte order (16 bit)
|
||||||
\details Reverses the byte order in a signed short value with sign extension to integer.
|
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
#ifndef __NO_EMBEDDED_ASM
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||||
{
|
{
|
||||||
revsh r0, r0
|
revsh r0, r0
|
||||||
bx lr
|
bx lr
|
||||||
|
@ -410,8 +486,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
||||||
/**
|
/**
|
||||||
\brief Rotate Right in unsigned value (32 bit)
|
\brief Rotate Right in unsigned value (32 bit)
|
||||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||||
\param [in] value Value to rotate
|
\param [in] op1 Value to rotate
|
||||||
\param [in] value Number of Bits to rotate
|
\param [in] op2 Number of Bits to rotate
|
||||||
\return Rotated value
|
\return Rotated value
|
||||||
*/
|
*/
|
||||||
#define __ROR __ror
|
#define __ROR __ror
|
||||||
|
@ -433,23 +509,24 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
#define __RBIT __rbit
|
#define __RBIT __rbit
|
||||||
#else
|
#else
|
||||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
|
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||||
|
|
||||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||||
for (value >>= 1U; value; value >>= 1U)
|
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||||
{
|
{
|
||||||
result <<= 1U;
|
result <<= 1U;
|
||||||
result |= value & 1U;
|
result |= value & 1U;
|
||||||
s--;
|
s--;
|
||||||
}
|
}
|
||||||
result <<= s; /* shift when v's highest bits are zero */
|
result <<= s; /* shift when v's highest bits are zero */
|
||||||
return(result);
|
return result;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -463,7 +540,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
#define __CLZ __clz
|
#define __CLZ __clz
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief LDR Exclusive (8 bit)
|
\brief LDR Exclusive (8 bit)
|
||||||
|
@ -645,7 +723,60 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
|
||||||
*/
|
*/
|
||||||
#define __STRT(value, ptr) __strt(value, ptr)
|
#define __STRT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Signed Saturate
|
||||||
|
\details Saturates a signed value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if ((sat >= 1U) && (sat <= 32U))
|
||||||
|
{
|
||||||
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||||
|
const int32_t min = -1 - max ;
|
||||||
|
if (val > max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < min)
|
||||||
|
{
|
||||||
|
return min;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Unsigned Saturate
|
||||||
|
\details Saturates an unsigned value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if (sat <= 31U)
|
||||||
|
{
|
||||||
|
const uint32_t max = ((1U << sat) - 1U);
|
||||||
|
if (val > (int32_t)max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < 0)
|
||||||
|
{
|
||||||
|
return 0U;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (uint32_t)val;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||||
|
|
||||||
|
@ -656,7 +787,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
|
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
#define __SADD8 __sadd8
|
#define __SADD8 __sadd8
|
||||||
#define __QADD8 __qadd8
|
#define __QADD8 __qadd8
|
||||||
|
@ -727,7 +858,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
|
||||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x04) */
|
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||||
|
|
||||||
|
|
||||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue