diff --git a/Target/Source/ARMCM3_STM32F1/can.c b/Target/Source/ARMCM3_STM32F1/can.c
index 0122dcc5..4509a89f 100644
--- a/Target/Source/ARMCM3_STM32F1/can.c
+++ b/Target/Source/ARMCM3_STM32F1/can.c
@@ -123,6 +123,14 @@ typedef struct
 #define CAN_BIT_TXRQ     ((blt_int32u)0x00000001)
 /** \brief Release FIFO 0 mailbox bit. */
 #define CAN_BIT_RFOM0    ((blt_int32u)0x00000020)
+/** \brief Standard 11-bit identifier bit mask. */
+#define CAN_BIT_STDID_MASK (0x7FFu << CAN_BIT_STDID_POS)
+/** \brief Standard 11-bit identifier bits position. */
+#define CAN_BIT_STDID_POS  (21u)
+/** \brief Extended 29-bit identifier bit mask. */
+#define CAN_BIT_EXTID_MASK (0x1FFFFFFFu << CAN_BIT_EXTID_POS)
+/** \brief Extended 29-bit identifier bits position. */
+#define CAN_BIT_EXTID_POS  (3u)
 
 
 /****************************************************************************************
@@ -229,6 +237,8 @@ void CanInit(void)
   blt_int8u  tseg1, tseg2;
   blt_bool   result;
   blt_int32u timeout;
+  blt_int32u rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
+  blt_int32u rxFilterId, rxFilterMask;
 
   /* the current implementation supports CAN1. throw an assertion error in case a
    * different CAN channel is configured.
@@ -290,15 +300,34 @@ void CanInit(void)
       break;
     }
   }
+
+  /* determine the reception filter mask and id values such that it only leaves one
+   * CAN identifier through (BOOT_COM_CAN_RX_MSG_ID).
+   */
+  if ((rxMsgId & 0x80000000) == 0)
+  {
+    rxFilterId = rxMsgId << CAN_BIT_STDID_POS;
+    rxFilterMask = (CAN_BIT_STDID_MASK) | CAN_BIT_IDE;
+  }
+  else
+  {
+    /* negate the ID-type bit */
+    rxMsgId &= ~0x80000000;
+    rxFilterId = (rxMsgId << CAN_BIT_EXTID_POS) | CAN_BIT_IDE;
+    rxFilterMask = (CAN_BIT_EXTID_MASK) | CAN_BIT_IDE;
+  }
+
   /* enter initialisation mode for the acceptance filter */
   CANx->FMR |= CAN_BIT_FINIT;
   /* deactivate filter 0 */
   CANx->FA1R &= ~CAN_BIT_FILTER0;
   /* 32-bit scale for the filter */
   CANx->FS1R |= CAN_BIT_FILTER0;
-  /* open up the acceptance filter to receive all messages */
-  CANx->sFilterRegister[0].FR1 = 0;
-  CANx->sFilterRegister[0].FR2 = 0;
+  /* Configure identifier mask mode for the filter */
+  CANx->FM1R &= ~CAN_BIT_FILTER0;
+  /* configure the acceptance filter to receive just one message */
+  CANx->sFilterRegister[0].FR1 = rxFilterId;
+  CANx->sFilterRegister[0].FR2 = rxFilterMask;
   /* select id/mask mode for the filter */
   CANx->FM1R &= ~CAN_BIT_FILTER0;
   /* FIFO 0 assignation for the filter */
diff --git a/Target/Source/ARMCM4_STM32F4/can.c b/Target/Source/ARMCM4_STM32F4/can.c
index 207bb846..f183597e 100644
--- a/Target/Source/ARMCM4_STM32F4/can.c
+++ b/Target/Source/ARMCM4_STM32F4/can.c
@@ -125,6 +125,18 @@ typedef struct
 #define CAN_BIT_TXRQ     ((blt_int32u)0x00000001)
 /** \brief Release FIFO 0 mailbox bit. */
 #define CAN_BIT_RFOM0    ((blt_int32u)0x00000020)
+/** \brief CAN2 start bank bit mask. */
+#define CAN_BIT_CAN2SB_MASK (0x3Fu << CAN_BIT_CAN2SB_POS)
+/** \brief CAN2 start bank position. */
+#define CAN_BIT_CAN2SB_POS  (8u)
+/** \brief Standard 11-bit identifier bit mask. */
+#define CAN_BIT_STDID_MASK (0x7FFu << CAN_BIT_STDID_POS)
+/** \brief Standard 11-bit identifier bits position. */
+#define CAN_BIT_STDID_POS  (21u)
+/** \brief Extended 29-bit identifier bit mask. */
+#define CAN_BIT_EXTID_MASK (0x1FFFFFFFu << CAN_BIT_EXTID_POS)
+/** \brief Extended 29-bit identifier bits position. */
+#define CAN_BIT_EXTID_POS  (3u)
 
 
 /****************************************************************************************
@@ -238,6 +250,8 @@ void CanInit(void)
   blt_int8u  tseg1, tseg2;
   blt_bool   result;
   blt_int32u timeout;
+  blt_int32u rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
+  blt_int32u rxFilterId, rxFilterMask;
 
   /* the current implementation supports CAN1 and 2. throw an assertion error in case a
    * different CAN channel is configured.
@@ -301,24 +315,46 @@ void CanInit(void)
     }
   }
 
-#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)
+  /* determine the reception filter mask and id values such that it only leaves one
+   * CAN identifier through (BOOT_COM_CAN_RX_MSG_ID).
+   */
+  if ((rxMsgId & 0x80000000) == 0)
+  {
+    rxFilterId = rxMsgId << CAN_BIT_STDID_POS;
+    rxFilterMask = (CAN_BIT_STDID_MASK) | CAN_BIT_IDE;
+  }
+  else
+  {
+    /* negate the ID-type bit */
+    rxMsgId &= ~0x80000000;
+    rxFilterId = (rxMsgId << CAN_BIT_EXTID_POS) | CAN_BIT_IDE;
+    rxFilterMask = (CAN_BIT_EXTID_MASK) | CAN_BIT_IDE;
+  }
+
   /* enter initialisation mode for the acceptance filter */
   CAN1->FMR |= CAN_BIT_FINIT;
+  /* set that CAN2 start bank to 14. This means that filters 0..13 are available
+   * for CAN1 and 14..27 for CAN2. it is also the default value after reset. first
+   * reset the active configuration.
+   */
+  CAN1->FMR &= ~CAN_BIT_CAN2SB_MASK;
+  CAN1->FMR |=  ((blt_int32u)(14 << CAN_BIT_CAN2SB_POS));
+#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)
   /* deactivate filter 0 */
   CAN1->FA1R &= ~CAN_BIT_FILTER0;
   /* 32-bit scale for the filter */
   CAN1->FS1R |= CAN_BIT_FILTER0;
-  /* open up the acceptance filter to receive all messages */
-  CAN1->sFilterRegister[0].FR1 = 0;
-  CAN1->sFilterRegister[0].FR2 = 0;
+  /* Configure identifier mask mode for the filter */
+  CAN1->FM1R &= ~CAN_BIT_FILTER0;
+  /* configure the acceptance filter to receive just one message */
+  CAN1->sFilterRegister[0].FR1 = rxFilterId;
+  CAN1->sFilterRegister[0].FR2 = rxFilterMask;
   /* select id/mask mode for the filter */
   CAN1->FM1R &= ~CAN_BIT_FILTER0;
   /* FIFO 0 assignation for the filter */
   CAN1->FFA1R &= ~CAN_BIT_FILTER0;
   /* filter activation */
   CAN1->FA1R |= CAN_BIT_FILTER0;
-  /* leave initialisation mode for the acceptance filter */
-  CAN1->FMR &= ~CAN_BIT_FINIT;
 #else
   /* enter initialisation mode for the acceptance filter */
   CAN1->FMR |= CAN_BIT_FINIT;
@@ -326,18 +362,20 @@ void CanInit(void)
   CAN1->FA1R &= ~CAN_BIT_FILTER14;
   /* 32-bit scale for the filter */
   CAN1->FS1R |= CAN_BIT_FILTER14;
-  /* open up the acceptance filter to receive all messages */
-  CAN1->sFilterRegister[14].FR1 = 0;
-  CAN1->sFilterRegister[14].FR2 = 0;
+  /* Configure identifier mask mode for the filter */
+  CAN1->FM1R &= ~CAN_BIT_FILTER14;
+  /* configure the acceptance filter to receive just one message */
+  CAN1->sFilterRegister[14].FR1 = rxFilterId;
+  CAN1->sFilterRegister[14].FR2 = rxFilterMask;
   /* select id/mask mode for the filter */
   CAN1->FM1R &= ~CAN_BIT_FILTER14;
   /* FIFO 0 assignation for the filter */
   CAN1->FFA1R &= ~CAN_BIT_FILTER14;
   /* filter activation */
   CAN1->FA1R |= CAN_BIT_FILTER14;
+#endif
   /* leave initialisation mode for the acceptance filter */
   CAN1->FMR &= ~CAN_BIT_FINIT;
-#endif
 } /*** end of CanInit ***/