diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openblt_olimex_lpc_l2294_20mhz.elf b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openblt_olimex_lpc_l2294_20mhz.elf
deleted file mode 100644
index 4552863e..00000000
Binary files a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openblt_olimex_lpc_l2294_20mhz.elf and /dev/null differ
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openblt_olimex_lpc_l2294_20mhz.map b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openblt_olimex_lpc_l2294_20mhz.map
deleted file mode 100644
index ed303e53..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openblt_olimex_lpc_l2294_20mhz.map
+++ /dev/null
@@ -1,887 +0,0 @@
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-.text 0x00000240 0x19f0
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- .text.UartInit
- 0x00000d74 0x40 ARM Flash Debug/../../obj/uart.o
- 0x00000d74 UartInit
- .text.UartTransmitPacket
- 0x00000db4 0x84 ARM Flash Debug/../../obj/uart.o
- 0x00000db4 UartTransmitPacket
- .text.UartReceivePacket
- 0x00000e38 0x108 ARM Flash Debug/../../obj/uart.o
- 0x00000e38 UartReceivePacket
- .text.AssertFailure
- 0x00000f40 0xc ARM Flash Debug/../../obj/assert.o
- 0x00000f40 AssertFailure
- .text.BackDoorCheck
- 0x00000f4c 0x54 ARM Flash Debug/../../obj/backdoor.o
- 0x00000f4c BackDoorCheck
- .text.BackDoorInit
- 0x00000fa0 0x30 ARM Flash Debug/../../obj/backdoor.o
- 0x00000fa0 BackDoorInit
- .text.BootInit
- 0x00000fd0 0x24 ARM Flash Debug/../../obj/boot.o
- 0x00000fd0 BootInit
- .text.BootTask
- 0x00000ff4 0x1c ARM Flash Debug/../../obj/boot.o
- 0x00000ff4 BootTask
- .text.ComInit 0x00001010 0x30 ARM Flash Debug/../../obj/com.o
- 0x00001010 ComInit
- .text.ComTask 0x00001040 0x5c ARM Flash Debug/../../obj/com.o
- 0x00001040 ComTask
- .text.ComFree 0x0000109c 0x4 ARM Flash Debug/../../obj/com.o
- 0x0000109c ComFree
- .text.ComTransmitPacket
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- 0x000010a0 ComTransmitPacket
- .text.ComGetActiveInterfaceMaxRxLen
- 0x000010ec 0x38 ARM Flash Debug/../../obj/com.o
- 0x000010ec ComGetActiveInterfaceMaxRxLen
- .text.ComGetActiveInterfaceMaxTxLen
- 0x00001124 0x38 ARM Flash Debug/../../obj/com.o
- 0x00001124 ComGetActiveInterfaceMaxTxLen
- .text.ComIsConnected
- 0x0000115c 0x10 ARM Flash Debug/../../obj/com.o
- 0x0000115c ComIsConnected
- .text.CopInit 0x0000116c 0x4 ARM Flash Debug/../../obj/cop.o
- 0x0000116c CopInit
- .text.CopService
- 0x00001170 0x4 ARM Flash Debug/../../obj/cop.o
- 0x00001170 CopService
- .text.XcpProtectResources
- 0x00001174 0x14 ARM Flash Debug/../../obj/xcp.o
- .text.XcpSetCtoError
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- .text.XcpInit 0x000011a8 0x28 ARM Flash Debug/../../obj/xcp.o
- 0x000011a8 XcpInit
- .text.XcpIsConnected
- 0x000011d0 0x18 ARM Flash Debug/../../obj/xcp.o
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- 0x00001740 __int32_div
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- 0x00001a40 __aeabi_uidiv
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- 0x00001bb0 __modsi3
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- 0x00001bd0 __aeabi_idivmod
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-
-.vfp11_veneer 0x00000000 0x0
- .vfp11_veneer 0x00000000 0x0 linker stubs
-
-.v4_bx 0x00000000 0x0
- .v4_bx 0x00000000 0x0 linker stubs
- 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .text is too large to fit in FLASH memory segment)
- 0x00001c30 __dtors_load_start__ = ALIGN (__text_end__, 0x4)
-
-.dtors 0x00001c30 0x0
- 0x00001c30 __dtors_start__ = .
- *(SORT(.dtors.*))
- *(.dtors)
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- 0x00001c30 __dtors_load_end__ = __dtors_end__
- 0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .dtors is too large to fit in FLASH memory segment)
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-
-.ctors 0x00001c30 0x0
- 0x00001c30 __ctors_start__ = .
- *(SORT(.ctors.*))
- *(.ctors)
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- 0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .ctors is too large to fit in FLASH memory segment)
- 0x00001c30 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
-
-.rodata 0x00001c30 0x250
- 0x00001c30 __rodata_start__ = .
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- 0x00001c30 0xc0 ARM Flash Debug/../../obj/flash.o
- .rodata.str1.4
- 0x00001cf0 0x7d ARM Flash Debug/../../obj/can.o
- 0x80 (size before relaxing)
- *fill* 0x00001d6d 0x3 00
- .rodata.canTiming
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- .rodata.str1.4
- 0x00001db8 0x80 ARM Flash Debug/../../obj/uart.o
- .rodata.xcpStationId
- 0x00001e38 0x8 ARM Flash Debug/../../obj/xcp.o
- .rodata.libc.__aeabi_uidiv
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- 0x00001e80 __rodata_load_end__ = __rodata_end__
- 0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .rodata is too large to fit in FLASH memory segment)
- 0x00001e80 __data_load_start__ = ALIGN (__rodata_end__, 0x4)
-
-.data 0x4000023c 0x4 load address 0x00001e80
- 0x4000023c __data_start__ = .
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- .data.comActiveInterface
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- 0x00000001 . = ASSERT ((((__data_load_start__ + SIZEOF (.data)) >= __FLASH_segment_start__) && ((__data_load_start__ + SIZEOF (.data)) <= (__FLASH_segment_start__ + 0x40000))), error: .data is too large to fit in FLASH memory segment)
-
-.data_run 0x4000023c 0x4 load address 0x00001e80
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- 0x00000001 . = ASSERT (((__data_run_end__ >= __SRAM_segment_start__) && (__data_run_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .data_run is too large to fit in SRAM memory segment)
- 0x40000240 __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
-
-.bss 0x40000240 0x4f4
- 0x40000240 __bss_start__ = .
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- .bss.blockInfo
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- .bss.xcpCtoRxLength.897
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- *fill* 0x40000651 0x3 00
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- .bss.xcpCtoRxInProgress.898
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- .bss.backdoorOpen
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- *fill* 0x400006a1 0x3 00
- .bss.backdoorOpenTime
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- .bss.xcpCtoReqPacket.891
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- *(COMMON)
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- 0x40000734 __bss_load_end__ = __bss_end__
- 0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .bss is too large to fit in SRAM memory segment)
- 0x40000734 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
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-.non_init 0x40000734 0x0
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- 0x40000734 __non_init_load_end__ = __non_init_end__
- 0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .non_init is too large to fit in SRAM memory segment)
- 0x40000734 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
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-.heap 0x40000734 0x400
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- *(.heap .heap.*)
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- *fill* 0x40000734 0x400 00
- 0x40000b34 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
- 0x40000b34 __heap_load_end__ = __heap_end__
- 0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .heap is too large to fit in SRAM memory segment)
- 0x40000b34 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
-
-.stack 0x40000b34 0x400
- 0x40000b34 __stack_start__ = .
- *(.stack .stack.*)
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- *fill* 0x40000b34 0x400 00
- 0x40000f34 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
- 0x40000f34 __stack_load_end__ = __stack_end__
- 0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack is too large to fit in SRAM memory segment)
- 0x40000f34 __stack_irq_load_start__ = ALIGN (__stack_end__, 0x4)
-
-.stack_irq 0x40000f34 0x100
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- *fill* 0x40000f34 0x100 00
- 0x40001034 __stack_irq_end__ = (__stack_irq_start__ + SIZEOF (.stack_irq))
- 0x40001034 __stack_irq_load_end__ = __stack_irq_end__
- 0x00000001 . = ASSERT (((__stack_irq_end__ >= __SRAM_segment_start__) && (__stack_irq_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_irq is too large to fit in SRAM memory segment)
- 0x40001034 __stack_fiq_load_start__ = ALIGN (__stack_irq_end__, 0x4)
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-.stack_fiq 0x40001034 0x100
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- 0x00000001 . = ASSERT (((__stack_fiq_end__ >= __SRAM_segment_start__) && (__stack_fiq_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_fiq is too large to fit in SRAM memory segment)
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-.stack_svc 0x40001134 0x0
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- 0x00000001 . = ASSERT (((__stack_svc_end__ >= __SRAM_segment_start__) && (__stack_svc_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_svc is too large to fit in SRAM memory segment)
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-.stack_abt 0x40001134 0x0
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- 0x00000001 . = ASSERT (((__stack_abt_end__ >= __SRAM_segment_start__) && (__stack_abt_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_abt is too large to fit in SRAM memory segment)
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-.stack_und 0x40001134 0x0
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- 0x00000001 . = ASSERT (((__stack_und_end__ >= __SRAM_segment_start__) && (__stack_und_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_und is too large to fit in SRAM memory segment)
- 0x00001e84 __fast_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
-
-.fast 0x40001134 0x0 load address 0x00001e84
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- 0x00000001 . = ASSERT ((((__fast_load_start__ + SIZEOF (.fast)) >= __FLASH_segment_start__) && ((__fast_load_start__ + SIZEOF (.fast)) <= (__FLASH_segment_start__ + 0x40000))), error: .fast is too large to fit in FLASH memory segment)
-
-.fast_run 0x40001134 0x0
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- 0x40001134 __SRAM_segment_used_end__ = (ALIGN (__stack_und_end__, 0x4) + SIZEOF (.fast_run))
- 0x00000001 . = ASSERT (((__fast_run_end__ >= __SRAM_segment_start__) && (__fast_run_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .fast_run is too large to fit in SRAM memory segment)
-START GROUP
-LOAD ARM Flash Debug/../../obj/hooks.o
-LOAD ARM Flash Debug/../../obj/main.o
-LOAD ARM Flash Debug/../../obj/extflash.o
-LOAD ARM Flash Debug/../../obj/cstart.o
-LOAD ARM Flash Debug/../../obj/flash.o
-LOAD ARM Flash Debug/../../obj/cpu_comp.o
-LOAD ARM Flash Debug/../../obj/can.o
-LOAD ARM Flash Debug/../../obj/cpu.o
-LOAD ARM Flash Debug/../../obj/nvm.o
-LOAD ARM Flash Debug/../../obj/timer.o
-LOAD ARM Flash Debug/../../obj/uart.o
-LOAD ARM Flash Debug/../../obj/assert.o
-LOAD ARM Flash Debug/../../obj/backdoor.o
-LOAD ARM Flash Debug/../../obj/boot.o
-LOAD ARM Flash Debug/../../obj/com.o
-LOAD ARM Flash Debug/../../obj/cop.o
-LOAD ARM Flash Debug/../../obj/xcp.o
-LOAD C:/Users/voorburg/AppData/Local/Rowley Associates Limited/CrossWorks for ARM/packages/lib/liblpc2000_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libarm_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcpp_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_targetio_impl_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v4t_a_le.a
-END GROUP
-OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/../bin/openblt_olimex_lpc_l2294_20mhz.elf elf32-littlearm)
-
-.debug_info 0x00000000 0x1b23
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- .debug_info 0x000001ca 0x106 ARM Flash Debug/../../obj/cstart.o
- .debug_info 0x000002d0 0x54c ARM Flash Debug/../../obj/flash.o
- .debug_info 0x0000081c 0x105 ARM Flash Debug/../../obj/cpu_comp.o
- .debug_info 0x00000921 0x201 ARM Flash Debug/../../obj/can.o
- .debug_info 0x00000b22 0x14f ARM Flash Debug/../../obj/cpu.o
- .debug_info 0x00000c71 0x177 ARM Flash Debug/../../obj/nvm.o
- .debug_info 0x00000de8 0xf2 ARM Flash Debug/../../obj/timer.o
- .debug_info 0x00000eda 0x1e1 ARM Flash Debug/../../obj/uart.o
- .debug_info 0x000010bb 0xb2 ARM Flash Debug/../../obj/assert.o
- .debug_info 0x0000116d 0xc0 ARM Flash Debug/../../obj/backdoor.o
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-
-.debug_abbrev 0x00000000 0xc7a
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-
-.debug_line 0x00000000 0x1463
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- .debug_line 0x00000b39 0x163 ARM Flash Debug/../../obj/uart.o
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- .debug_line 0x00000dc5 0x147 ARM Flash Debug/../../obj/backdoor.o
- .debug_line 0x00000f0c 0xbc ARM Flash Debug/../../obj/boot.o
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-
-.debug_str 0x00000000 0xfc6
- .debug_str 0x00000000 0xe8 ARM Flash Debug/../../obj/hooks.o
- 0x106 (size before relaxing)
- .debug_str 0x000000e8 0x9e ARM Flash Debug/../../obj/main.o
- 0x147 (size before relaxing)
- .debug_str 0x00000186 0x65 ARM Flash Debug/../../obj/extflash.o
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- .debug_str 0x000001eb 0x258 ARM Flash Debug/../../obj/flash.o
- 0x320 (size before relaxing)
- .debug_str 0x00000443 0xcb ARM Flash Debug/../../obj/cpu_comp.o
- 0x17a (size before relaxing)
- .debug_str 0x0000050e 0x117 ARM Flash Debug/../../obj/can.o
- 0x1e5 (size before relaxing)
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diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openblt_olimex_lpc_l2294_20mhz.srec b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openblt_olimex_lpc_l2294_20mhz.srec
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diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/blt_conf.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/blt_conf.h
deleted file mode 100644
index e0b9634b..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/blt_conf.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\blt_conf.h
-* \brief Bootloader configuration header file.
-* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-#ifndef BLT_CONF_H
-#define BLT_CONF_H
-
-/****************************************************************************************
-* C P U D R I V E R C O N F I G U R A T I O N
-****************************************************************************************/
-/* To properly initialize the baudrate clocks of the communication interface, typically
- * the speed of the crystal oscillator and/or the speed at which the system runs is
- * needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
- * BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
- * not dependent on the targets architecture, the byte ordering needs to be known.
- * Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
- * little endian mode.
- *
- * Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
- * called the moment the user program is about to be started. This could be used to
- * de-initialize application specific parts, for example to stop blinking an LED, etc.
- */
-/** \brief Frequency of the external crystal oscillator. */
-#define BOOT_CPU_XTAL_SPEED_KHZ (20000)
-/** \brief Desired system speed. */
-#define BOOT_CPU_SYSTEM_SPEED_KHZ (60000)
-/** \brief Motorola or Intel style byte ordering. */
-#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
-/** \brief Enable/disable hook function call right before user program start. */
-#define BOOT_CPU_USER_PROGRAM_START_HOOK (0)
-
-
-/****************************************************************************************
-* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
-****************************************************************************************/
-/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
- * configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
- * in bits/second. Two CAN messages are reserved for communication with the host. The
- * message identifier for sending data from the target to the host is configured with
- * BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
- * BOOT_COM_CAN_RXMSG_ID. The maximum amount of data bytes in a message for data
- * transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
- * BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
- * than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
- * CAN controller channel.
- *
- */
-/** \brief Enable/disable CAN transport layer. */
-#define BOOT_COM_CAN_ENABLE (1)
-/** \brief Configure the desired CAN baudrate. */
-#define BOOT_COM_CAN_BAUDRATE (500000)
-/** \brief Configure CAN message ID target->host. */
-#define BOOT_COM_CAN_TX_MSG_ID (0x7E1)
-/** \brief Configure number of bytes in the target->host CAN message. */
-#define BOOT_COM_CAN_TX_MAX_DATA (8)
-/** \brief Configure CAN message ID host->target. */
-#define BOOT_COM_CAN_RX_MSG_ID (0x667)
-/** \brief Configure number of bytes in the host->target CAN message. */
-#define BOOT_COM_CAN_RX_MAX_DATA (8)
-/** \brief Select the desired CAN peripheral as a zero based index. */
-#define BOOT_COM_CAN_CHANNEL_INDEX (0)
-
-/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
- * configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
- * in bits/second. The maximum amount of data bytes in a message for data transmission
- * and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,
- * respectively. It is common for a microcontroller to have more than 1 UART interface
- * on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.
- *
- */
-/** \brief Enable/disable UART transport layer. */
-#define BOOT_COM_UART_ENABLE (1)
-/** \brief Configure the desired communication speed. */
-#define BOOT_COM_UART_BAUDRATE (57600)
-/** \brief Configure number of bytes in the target->host data packet. */
-#define BOOT_COM_UART_TX_MAX_DATA (64)
-/** \brief Configure number of bytes in the host->target data packet. */
-#define BOOT_COM_UART_RX_MAX_DATA (64)
-/** \brief Select the desired UART peripheral as a zero based index. */
-#define BOOT_COM_UART_CHANNEL_INDEX (0)
-
-
-/****************************************************************************************
-* B A C K D O O R E N T R Y C O N F I G U R A T I O N
-****************************************************************************************/
-/* It is possible to implement an application specific method to force the bootloader to
- * stay active after a reset. Such a backdoor entry into the bootloader is desired in
- * situations where the user program does not run properly and therefore cannot
- * reactivate the bootloader. By enabling these hook functions, the application can
- * implement the backdoor, which overrides the default backdoor entry that is programmed
- * into the bootloader. When desired for security purposes, these hook functions can
- * also be implemented in a way that disables the backdoor entry altogether.
- */
-/** \brief Enable/disable the backdoor override hook functions. */
-#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
-
-
-/****************************************************************************************
-* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
-****************************************************************************************/
-/* The NVM driver typically supports erase and program operations of the internal memory
- * present on the microcontroller. Through these hook functions the NVM driver can be
- * extended to support additional memory types such as external flash memory and serial
- * eeproms. The size of the internal memory in kilobytes is specified with configurable
- * BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
- * be overridden with a application specific method by enabling configuration switch
- * BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
- */
-/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
-#define BOOT_NVM_HOOKS_ENABLE (0)
-/** \brief Configure the size of the default memory device (typically flash EEPROM). */
-#define BOOT_NVM_SIZE_KB (256)
-/** \brief Enable/disable hooks functions to override the user program checksum handling. */
-#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0)
-
-
-/****************************************************************************************
-* W A T C H D O G D R I V E R C O N F I G U R A T I O N
-****************************************************************************************/
-/* The COP driver cannot be configured internally in the bootloader, because its use
- * and configuration is application specific. The bootloader does need to service the
- * watchdog in case it is used. When the application requires the use of a watchdog,
- * set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
- * hook functions.
- */
-/** \brief Enable/disable the hook functions for controlling the watchdog. */
-#define BOOT_COP_HOOKS_ENABLE (0)
-
-
-/****************************************************************************************
-* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N
-****************************************************************************************/
-/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
- * rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
- * operations can be performed, access to this resource need to be unlocked.
- * In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
- * implements the unlocking algorithm. The demo programs are configured for the (simple)
- * algorithm in "FeaserKey.dll". The source code for this DLL is available so it can be
- * customized to your needs.
- * During the unlock sequence, Microboot requests a seed from the bootloader, which is in
- * the format of a byte array. Using this seed the unlock algorithm in the DLL computes
- * a key, which is also a byte array, and sends this back to the bootloader. The
- * bootloader then verifies this key to determine if programming and erase operations are
- * permitted.
- * After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
- * are called by the bootloader to obtain the seed and to verify the key, respectively.
- */
-#define BOOT_XCP_SEED_KEY_ENABLE (0)
-
-
-#endif /* BLT_CONF_H */
-/*********************************** end of blt_conf.h *********************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/boot.dox b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/boot.dox
deleted file mode 100644
index a7843c0c..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/boot.dox
+++ /dev/null
@@ -1,7 +0,0 @@
-/**
-\defgroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks Bootloader
-\brief Bootloader.
-\ingroup ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-*/
-
-
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/extflash.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/extflash.c
deleted file mode 100644
index ad52d59e..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/extflash.c
+++ /dev/null
@@ -1,653 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\extflash.c
-* \brief Bootloader external flash driver source file.
-* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "boot.h" /* bootloader generic header */
-
-
-#if (BOOT_NVM_HOOKS_ENABLE > 0)
-/****************************************************************************************
-* Macro definitions
-****************************************************************************************/
-/** \brief Value for an invalid flash sector. */
-#define FLASH_INVALID_SECTOR (0xff)
-/** \brief Value for an invalid flash address. */
-#define FLASH_INVALID_ADDRESS (0xffffffff)
-/** \brief Standard size of a flash block for writing. */
-#define FLASH_WRITE_BLOCK_SIZE (512)
-/** \brief Total numbers of sectors in array flashLayout[]. */
-#define FLASH_TOTAL_SECTORS (sizeof(flashLayout)/sizeof(flashLayout[0]))
-/** \brief C3 Intel flash read array command. */
-#define FLASH_CMD_READ_ARRAY_MODE (0xFF)
-/** \brief C3 Intel flash read id command. */
-#define FLASH_CMD_READ_ID_MODE (0x90)
-/** \brief C3 Intel flash erase command. */
-#define FLASH_CMD_ERASE_MODE (0x20)
-/** \brief C3 Intel flash read status command. */
-#define FLASH_CMD_READ_STATUS_MODE (0x70)
-/** \brief C3 Intel flash change lock command. */
-#define FLASH_CMD_CHANGE_LOCK_MODE (0x60)
-/** \brief C3 Intel flash unlock sector command. */
-#define FLASH_CMD_UNLOCK_SECTOR (0xD0)
-/** \brief C3 Intel flash lock sector command. */
-#define FLASH_CMD_LOCK_SECTOR (0x01)
-/** \brief C3 Intel flash program command. */
-#define FLASH_CMD_PROGRAM_MODE (0x40)
-/** \brief C3 Intel flash erase confirm command. */
-#define FLASH_CMD_ERASE_CONFIRM (0xD0)
-/** \brief C3 Intel flash clear status command. */
-#define FLASH_CMD_CLEAR_STATUS (0x50)
-/** \brief C3 Intel flash lock bit. */
-#define FLASH_LOCK_BIT (0x01)
-/** \brief C3 Intel flash status ready bit. */
-#define FLASH_STATUS_READY_BIT (0x80)
-/** \brief C3 Intel flash locked error code. */
-#define FLASH_ERR_LOCKED (0x02)
-/** \brief C3 Intel flash Vpp range error code. */
-#define FLASH_ERR_VPP_RANGE (0x08)
-/** \brief C3 Intel flash program error code. */
-#define FLASH_ERR_PROGRAM (0x10)
-/** \brief C3 Intel flash command sequence error code. */
-#define FLASH_ERR_CMD_SEQ (0x10)
-/** \brief C3 Intel flash erase error code. */
-#define FLASH_ERR_ERASE (0x20)
-/** \brief Flash erase timeout value. */
-#define FLASH_ERASE_TIMEOUT ((blt_int32u)5000000)
-/** \brief Flash program timeout value. */
-#define FLASH_PROGRAM_TIMEOUT ((blt_int32u)1000000)
-/** \brief Supported Intel C3 flash manufacturer ID. */
-#define FLASH_DEV_MAN_ID ((blt_int16u)0x0089)
-/** \brief Supported Intel C3 flash device ID. */
-#define FLASH_DEV_ID ((blt_int16u)0x88c3)
-/** \brief Offset for reading manufacturer ID. */
-#define FLASH_DEVINFO_MAN_ID ((blt_int16u)0x0000)
-/** \brief Offset for reading device ID. */
-#define FLASH_DEVINFO_DEV_ID ((blt_int16u)0x0001)
-/** \brief Offset for reading lock status. */
-#define FLASH_DEVINFO_LOCK_STATUS ((blt_int16u)0x0002)
-/** \brief Runtime efficient macro for obtaining the manufacturer ID. */
-#define ExtFlashGetManID() (ExtFlashGetDeviceInfo(flashLayout[0].sector_start, \
- FLASH_DEVINFO_MAN_ID))
-/** \brief Runtime efficient macro for obtaining the device ID. */
-#define ExtFlashGetDevID() (ExtFlashGetDeviceInfo(flashLayout[0].sector_start, \
- FLASH_DEVINFO_DEV_ID))
-/** \brief Runtime efficient macro for obtaining the lock status. */
-#define ExtFlashGetLockStatus(base) (ExtFlashGetDeviceInfo(base, \
- FLASH_DEVINFO_LOCK_STATUS))
-
-
-/****************************************************************************************
-* Type definitions
-****************************************************************************************/
-/** \brief Flash sector descriptor type. */
-typedef struct
-{
- blt_addr sector_start; /**< sector start address */
- blt_int32u sector_size; /**< sector size in bytes */
- blt_int8u sector_num; /**< sector number */
-} tFlashSector;
-
-/** \brief Structure type for grouping flash block information.
- * \details Programming is done per block of max FLASH_WRITE_BLOCK_SIZE. for this a
- * flash block manager is implemented in this driver. this flash block manager
- * depends on this flash block info structure. It holds the base address of
- * the flash block and the data that should be programmed into the flash
- * block.
- */
-typedef struct
-{
- blt_addr base_addr; /**< Base address for the flash operation.*/
- blt_int8u data[FLASH_WRITE_BLOCK_SIZE]; /**< Data array. */
-} tFlashBlockInfo;
-
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-static blt_bool ExtFlashInitBlock(tFlashBlockInfo *block, blt_addr address);
-static tFlashBlockInfo *ExtFlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr);
-static blt_bool ExtFlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
- blt_int8u *data, blt_int32u len);
-static blt_bool ExtFlashWriteBlock(tFlashBlockInfo *block);
-static blt_bool ExtFlashEraseSector(blt_addr sector_base);
-static blt_int16u ExtFlashGetDeviceInfo(blt_addr block_base, blt_int16u info);
-static void ExtFlashLockSector(blt_addr sector_base);
-static void ExtFlashUnlockSector(blt_addr sector_base);
-static blt_int8u ExtFlashGetSector(blt_addr address);
-
-
-/****************************************************************************************
-* Local constant declarations
-****************************************************************************************/
-/** \brief Array wit the layout of the flash memory.
- * \details The current layout supports the 2MB external C3 Intel flash:
- * - manufacturer id = 0x0089
- * - device id = 0x88c3 (16 Mbit bottom boot device)
- * Note that what Intel calls a block in the user manual, is called a sector in this
- * driver.
- */
-static const tFlashSector flashLayout[] =
-{
- { 0x80000000, 0x02000, 0}, /* flash sector 0 - 8 kbyte */
- { 0x80002000, 0x02000, 1}, /* flash sector 1 - 8 kbyte */
- { 0x80004000, 0x02000, 2}, /* flash sector 2 - 8 kbyte */
- { 0x80006000, 0x02000, 3}, /* flash sector 3 - 8 kbyte */
- { 0x80008000, 0x02000, 4}, /* flash sector 4 - 8 kbyte */
- { 0x8000A000, 0x02000, 5}, /* flash sector 5 - 8 kbyte */
- { 0x8000C000, 0x02000, 6}, /* flash sector 6 - 8 kbyte */
- { 0x8000E000, 0x02000, 7}, /* flash sector 7 - 8 kbyte */
- { 0x80010000, 0x10000, 8}, /* flash sector 8 - 64 kbyte */
- { 0x80020000, 0x10000, 9}, /* flash sector 9 - 64 kbyte */
- { 0x80030000, 0x10000, 10}, /* flash sector 10 - 64 kbyte */
- { 0x80040000, 0x10000, 11}, /* flash sector 11 - 64 kbyte */
- { 0x80050000, 0x10000, 12}, /* flash sector 12 - 64 kbyte */
- { 0x80060000, 0x10000, 13}, /* flash sector 13 - 64 kbyte */
- { 0x80070000, 0x10000, 14}, /* flash sector 14 - 64 kbyte */
- { 0x80080000, 0x10000, 15}, /* flash sector 15 - 64 kbyte */
- { 0x80090000, 0x10000, 16}, /* flash sector 16 - 64 kbyte */
- { 0x800A0000, 0x10000, 17}, /* flash sector 17 - 64 kbyte */
- { 0x800B0000, 0x10000, 18}, /* flash sector 18 - 64 kbyte */
- { 0x800C0000, 0x10000, 19}, /* flash sector 19 - 64 kbyte */
- { 0x800D0000, 0x10000, 20}, /* flash sector 20 - 64 kbyte */
- { 0x800E0000, 0x10000, 21}, /* flash sector 21 - 64 kbyte */
- { 0x800F0000, 0x10000, 22}, /* flash sector 22 - 64 kbyte */
- { 0x80100000, 0x10000, 23}, /* flash sector 23 - 64 kbyte */
- { 0x80110000, 0x10000, 24}, /* flash sector 24 - 64 kbyte */
- { 0x80120000, 0x10000, 25}, /* flash sector 25 - 64 kbyte */
- { 0x80130000, 0x10000, 26}, /* flash sector 26 - 64 kbyte */
- { 0x80140000, 0x10000, 27}, /* flash sector 27 - 64 kbyte */
- { 0x80150000, 0x10000, 28}, /* flash sector 28 - 64 kbyte */
- { 0x80160000, 0x10000, 29}, /* flash sector 29 - 64 kbyte */
- { 0x80170000, 0x10000, 30}, /* flash sector 30 - 64 kbyte */
- { 0x80180000, 0x10000, 31}, /* flash sector 31 - 64 kbyte */
- { 0x80190000, 0x10000, 32}, /* flash sector 32 - 64 kbyte */
- { 0x801A0000, 0x10000, 33}, /* flash sector 33 - 64 kbyte */
- { 0x801B0000, 0x10000, 34}, /* flash sector 34 - 64 kbyte */
- { 0x801C0000, 0x10000, 35}, /* flash sector 35 - 64 kbyte */
- { 0x801D0000, 0x10000, 36}, /* flash sector 36 - 64 kbyte */
- { 0x801E0000, 0x10000, 37}, /* flash sector 37 - 64 kbyte */
- { 0x801F0000, 0x10000, 38} /* flash sector 38 - 64 kbyte */
-};
-
-
-/****************************************************************************************
-* Local data declarations
-****************************************************************************************/
-/** \brief Local variable with information about the flash block that is currently
- * being operated on.
- * \details The smallest amount of flash that can be programmed is
- * FLASH_WRITE_BLOCK_SIZE. A flash block manager is implemented in this driver
- * and stores info in this variable. Whenever new data should be flashed, it
- * is first added to a RAM buffer, which is part of this variable. Whenever
- * the RAM buffer, which has the size of a flash block, is full or data needs
- * to be written to a different block, the contents of the RAM buffer are
- * programmed to flash. The flash block manager requires some software
- * overhead, yet results is faster flash programming because data is first
- * harvested, ideally until there is enough to program an entire flash block,
- * before the flash device is actually operated on.
- */
-static tFlashBlockInfo blockInfo;
-
-
-/************************************************************************************//**
-** \brief Initializes the flash driver.
-** \return none.
-**
-****************************************************************************************/
-void ExtFlashInit(void)
-{
- /* init the flash block info struct by setting the address to an invalid address */
- blockInfo.base_addr = FLASH_INVALID_ADDRESS;
- /* check the flash device identification */
- if ((ExtFlashGetManID() != FLASH_DEV_MAN_ID) || (ExtFlashGetDevID() != FLASH_DEV_ID))
- {
- ASSERT_RT(BLT_FALSE);
- }
-} /*** end of ExtFlashInit ***/
-
-
-/************************************************************************************//**
-** \brief Writes the data to flash.
-** \param addr Start address.
-** \param len Length in bytes.
-** \param data Pointer to the data buffer.
-** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
-** not within the supported memory range, or BLT_NVM_ERROR is the write
-** operation failed.
-**
-****************************************************************************************/
-blt_int8u ExtFlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
-{
- /* make sure the addresses are within the flash device */
- if ( (ExtFlashGetSector(addr) == FLASH_INVALID_SECTOR) || \
- (ExtFlashGetSector(addr+len-1) == FLASH_INVALID_SECTOR) )
- {
- return BLT_NVM_NOT_IN_RANGE;
- }
-
- /* let the block manager handle it */
- if (ExtFlashAddToBlock(&blockInfo, addr, data, len) == BLT_FALSE)
- {
- return BLT_NVM_ERROR;
- }
- return BLT_NVM_OKAY;
-} /*** end of FlashWrite ***/
-
-
-/************************************************************************************//**
-** \brief Erases the flash memory. Note that this function also checks that no
-** data is erased outside the flash memory region.
-** \param addr Start address.
-** \param len Length in bytes.
-** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
-** not within the supported memory range, or BLT_NVM_ERROR is the erase
-** operation failed.
-**
-****************************************************************************************/
-blt_int8u ExtFlashErase(blt_addr addr, blt_int32u len)
-{
- blt_int8u first_sector;
- blt_int8u last_sector;
- blt_int8u sectorIdx;
-
- /* obtain the first and last sector number */
- first_sector = ExtFlashGetSector(addr);
- last_sector = ExtFlashGetSector(addr+len-1);
- /* check them */
- if ( (first_sector == FLASH_INVALID_SECTOR) || (last_sector == FLASH_INVALID_SECTOR) )
- {
- return BLT_NVM_NOT_IN_RANGE;
- }
- /* erase the sectors one-by-one */
- for (sectorIdx = first_sector; sectorIdx <= last_sector; sectorIdx++)
- {
- /* keep the watchdog happy */
- CopService();
- /* erase the sector */
- if (ExtFlashEraseSector(flashLayout[sectorIdx].sector_start) == BLT_FALSE)
- {
- return BLT_NVM_ERROR;
- }
- }
- /* done so return the result of the operation */
- return BLT_NVM_OKAY;
-} /*** end of ExtFlashErase ***/
-
-
-/************************************************************************************//**
-** \brief Finalizes the flash driver operations.
-** \return BLT_TRUE is succesful, BLT_FALSE otherwise.
-**
-****************************************************************************************/
-blt_bool ExtFlashDone(void)
-{
- /* check if there is still data waiting to be programmed */
- if (blockInfo.base_addr != FLASH_INVALID_ADDRESS)
- {
- if (ExtFlashWriteBlock(&blockInfo) == BLT_FALSE)
- {
- return BLT_FALSE;
- }
- }
- /* still here so all is okay */
- return BLT_TRUE;
-} /*** end of ExtFlashDone ***/
-
-
-/************************************************************************************//**
-** \brief Copies data currently in flash to the block->data and sets the
-** base address.
-** \param block Pointer to flash block info structure to operate on.
-** \param address Base address of the block data.
-** \return BLT_TRUE is succesful, BLT_FALSE otherwise.
-**
-****************************************************************************************/
-static blt_bool ExtFlashInitBlock(tFlashBlockInfo *block, blt_addr address)
-{
- /* check address alignment */
- if ((address % FLASH_WRITE_BLOCK_SIZE) != 0)
- {
- return BLT_FALSE;
- }
- /* make sure that we are initializing a new block and not the same one */
- if (block->base_addr == address)
- {
- /* block already initialized, so nothing to do */
- return BLT_TRUE;
- }
- /* set the base address and copies the current data from flash */
- block->base_addr = address;
- CpuMemCopy((blt_addr)block->data, address, FLASH_WRITE_BLOCK_SIZE);
- return BLT_TRUE;
-} /*** end of ExtFlashInitBlock ***/
-
-
-/************************************************************************************//**
-** \brief Switches blocks by programming the current one and initializing the next.
-** \param block Pointer to flash block info structure to operate on.
-** \param base_addr Base address for the next block.
-** \return The pointer of the block info struct that is no being used, or a NULL
-** pointer in case of error.
-**
-****************************************************************************************/
-static tFlashBlockInfo *ExtFlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr)
-{
- /* need to switch to a new block, so program the current one and init the next */
- if (ExtFlashWriteBlock(block) == BLT_FALSE)
- {
- return BLT_NULL;
- }
- /* initialize the new block when necessary */
- if (ExtFlashInitBlock(block, base_addr) == BLT_FALSE)
- {
- return BLT_NULL;
- }
- /* still here to all is okay */
- return block;
-} /*** end of ExtFlashSwitchBlock ***/
-
-
-/************************************************************************************//**
-** \brief Programming is done per block. This function adds data to the block
-** that is currently collecting data to be written to flash. If the
-** address is outside of the current block, the current block is written
-** to flash an a new block is initialized.
-** \param block Pointer to flash block info structure to operate on.
-** \param address Flash destination address.
-** \param data Pointer to the byte array with data.
-** \param len Number of bytes to add to the block.
-** \return BLT_TRUE if successful, BLT_FALSE otherwise.
-**
-****************************************************************************************/
-static blt_bool ExtFlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
- blt_int8u *data, blt_int32u len)
-{
- blt_addr current_base_addr;
- blt_int8u *dst;
- blt_int8u *src;
-
- /* determine the current base address */
- current_base_addr = (address/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE;
-
- /* make sure the blockInfo is not uninitialized */
- if (block->base_addr == FLASH_INVALID_ADDRESS)
- {
- /* initialize the blockInfo struct for the current block */
- if (ExtFlashInitBlock(block, current_base_addr) == BLT_FALSE)
- {
- return BLT_FALSE;
- }
- }
- /* check if the new data fits in the current block */
- if (block->base_addr != current_base_addr)
- {
- /* need to switch to a new block, so program the current one and init the next */
- block = ExtFlashSwitchBlock(block, current_base_addr);
- if (block == BLT_NULL)
- {
- return BLT_FALSE;
- }
- }
- /* add the data to the current block, but check for block overflow */
- dst = &(block->data[address - block->base_addr]);
- src = data;
- do
- {
- /* keep the watchdog happy */
- CopService();
- /* buffer overflow? */
- if ((blt_addr)(dst-&(block->data[0])) >= FLASH_WRITE_BLOCK_SIZE)
- {
- /* need to switch to a new block, so program the current one and init the next */
- block = ExtFlashSwitchBlock(block, current_base_addr+FLASH_WRITE_BLOCK_SIZE);
- if (block == BLT_NULL)
- {
- return BLT_FALSE;
- }
- /* reset destination pointer */
- dst = &(block->data[0]);
- }
- /* write the data to the buffer */
- *dst = *src;
- /* update pointers */
- dst++;
- src++;
- /* decrement byte counter */
- len--;
- }
- while (len > 0);
- /* still here so all is good */
- return BLT_TRUE;
-} /*** end of ExtFlashAddToBlock ***/
-
-
-/************************************************************************************//**
-** \brief Programs FLASH_WRITE_BLOCK_SIZE bytes to flash from the block->data array.
-** \param block Pointer to flash block info structure to operate on.
-** \return BLT_TRUE if successful, BLT_FALSE otherwise.
-**
-****************************************************************************************/
-static blt_bool ExtFlashWriteBlock(tFlashBlockInfo *block)
-{
- volatile blt_int16u *pAddr;
- volatile blt_int16u *pData;
- blt_bool result = BLT_TRUE;
- volatile blt_int32u timeout = 0;
-
- /* unlock the sector */
- ExtFlashUnlockSector(block->base_addr);
- /* init pointer to valid address in the flash block */
- pAddr = (blt_int16u *)block->base_addr;
- /* init pointer to start of block data */
- pData = (blt_int16u *)block->data;
- /* program all block data 16-bits at a time */
- while ((blt_addr)pAddr < (block->base_addr+FLASH_WRITE_BLOCK_SIZE))
- {
- /* keep the watchdog happy */
- CopService();
- /* issue program setup command */
- *pAddr = FLASH_CMD_PROGRAM_MODE;
- /* write 16-bit data that is to be programmed to start programming operation */
- *pAddr = *pData;
- /* check status register for completion */
- *pAddr = FLASH_CMD_READ_STATUS_MODE;
- /* wait for completion or timeout */
- while( ((*pAddr & FLASH_STATUS_READY_BIT) == 0) && (timeout < FLASH_PROGRAM_TIMEOUT) )
- {
- timeout++;
- }
- /* check for possible errors */
- if ( (timeout >= FLASH_ERASE_TIMEOUT) || \
- ((*pAddr & (FLASH_ERR_LOCKED | FLASH_ERR_VPP_RANGE | FLASH_ERR_PROGRAM))!= 0) )
- {
- result = BLT_FALSE;
- }
- /* clear the status register */
- *pAddr = FLASH_CMD_CLEAR_STATUS;
- /* increment address and data pointers */
- pAddr++;
- pData++;
- }
- /* lock the sector. this also switches back to read array mode */
- ExtFlashLockSector(block->base_addr);
- /* inform the caller about the result */
- return result;
-} /*** end of ExtFlashWriteBlock ***/
-
-
-/************************************************************************************//**
-** \brief Erases the flash sector.
-** \param sector_base Base address of the sector to erase.
-** \return BLT_TRUE if successful, BLT_FALSE otherwise.
-**
-****************************************************************************************/
-static blt_bool ExtFlashEraseSector(blt_addr sector_base)
-{
- volatile blt_int16u *pAddr;
- blt_bool result = BLT_TRUE;
- volatile blt_int32u timeout = 0;
-
- /* unlock the sector */
- ExtFlashUnlockSector(sector_base);
- /* init pointer to valid address in the flash sector */
- pAddr = (blt_int16u *)sector_base;
- /* issue erase setup command */
- *pAddr = FLASH_CMD_ERASE_MODE;
- /* issue erase confirm command */
- *pAddr = FLASH_CMD_ERASE_CONFIRM;
- /* check status register for completion */
- *pAddr = FLASH_CMD_READ_STATUS_MODE;
- /* wait for completion or timeout */
- while( ((*pAddr & FLASH_STATUS_READY_BIT) == 0) && (timeout < FLASH_ERASE_TIMEOUT) )
- {
- timeout++;
- }
- /* check for possible errors */
- if ( (timeout >= FLASH_ERASE_TIMEOUT) || \
- ((*pAddr & (FLASH_ERR_LOCKED | FLASH_ERR_VPP_RANGE | FLASH_ERR_ERASE))!= 0) )
- {
- result = BLT_FALSE;
- }
- /* clear the status register */
- *pAddr = FLASH_CMD_CLEAR_STATUS;
- /* lock the sector. this also switches back to read array mode */
- ExtFlashLockSector(sector_base);
- /* inform the caller about the result */
- return result;
-} /*** end of ExtFlashEraseSector ***/
-
-
-/************************************************************************************//**
-** \brief Locks the flash sector.
-** \param sector_base Base address of the sector to lock.
-** \return none.
-**
-****************************************************************************************/
-static void ExtFlashLockSector(blt_addr sector_base)
-{
- volatile blt_int16u *pAddr;
-
- /* no need to lock a sector that is already locked */
- if ((ExtFlashGetLockStatus(sector_base) & FLASH_LOCK_BIT) != 0)
- {
- return;
- }
- /* init pointer to valid address in the flash sector */
- pAddr = (blt_int16u *)sector_base;
- /* switch to change lock mode */
- *pAddr = FLASH_CMD_CHANGE_LOCK_MODE;
- /* unlock the sector */
- *pAddr = FLASH_CMD_LOCK_SECTOR;
- /* check that the sector is now actually locked */
- ASSERT_RT((ExtFlashGetLockStatus(sector_base) & FLASH_LOCK_BIT) != 0);
-} /*** end of ExtFlashLockSector ***/
-
-
-/************************************************************************************//**
-** \brief Unlocks the flash sector.
-** \param sector_base Base address of the sector to unlock.
-** \return none.
-**
-****************************************************************************************/
-static void ExtFlashUnlockSector(blt_addr sector_base)
-{
- volatile blt_int16u *pAddr;
-
- /* no need to unlock a sector that is already unlocked */
- if ((ExtFlashGetLockStatus(sector_base) & FLASH_LOCK_BIT) == 0)
- {
- return;
- }
- /* init pointer to valid address in the flash sector */
- pAddr = (blt_int16u *)sector_base;
- /* switch to change lock mode */
- *pAddr = FLASH_CMD_CHANGE_LOCK_MODE;
- /* unlock the sector */
- *pAddr = FLASH_CMD_UNLOCK_SECTOR;
- /* check that the sector is now actually unlocked */
- ASSERT_RT((ExtFlashGetLockStatus(sector_base) & FLASH_LOCK_BIT) == 0);
-} /*** end of ExtFlashUnlockSector ***/
-
-
-/************************************************************************************//**
-** \brief Obtains device information from the flash device.
-** \param sector_base Base address of the sector to get the info from.
-** \param info Identifier to the type of info to obtain.
-** \return Device info.
-**
-****************************************************************************************/
-static blt_int16u ExtFlashGetDeviceInfo(blt_addr sector_base, blt_int16u info)
-{
- volatile blt_int16u *pAddr;
- blt_int16u readData;
-
- /* init pointer to any valid address in the flash device */
- pAddr = (blt_int16u *)sector_base + info;
- /* switch to read identifier mode */
- *pAddr = FLASH_CMD_READ_ID_MODE;
- /* read the info */
- readData = *pAddr;
- /* switch back to reading mode */
- *pAddr = FLASH_CMD_READ_ARRAY_MODE;
- /* return the result */
- return readData;
-} /*** end of ExtFlashGetDeviceInfo ***/
-
-
-/************************************************************************************//**
-** \brief Determines the flash sector the address is in.
-** \param address Address in the flash sector.
-** \return Flash sector number or FLASH_INVALID_SECTOR
-**
-****************************************************************************************/
-static blt_int8u ExtFlashGetSector(blt_addr address)
-{
- blt_int8u sectorIdx;
-
- /* search through the sectors to find the right one */
- for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++)
- {
- /* keep the watchdog happy */
- CopService();
- /* is the address in this sector? */
- if ( (address >= flashLayout[sectorIdx].sector_start) && \
- (address < (flashLayout[sectorIdx].sector_start + \
- flashLayout[sectorIdx].sector_size)) )
- {
- /* return the sector number */
- return flashLayout[sectorIdx].sector_num;
- }
- }
- /* still here so no valid sector found */
- return FLASH_INVALID_SECTOR;
-} /*** end of ExtFlashGetSector ***/
-#endif
-
-/*********************************** end of extflash.c *********************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/extflash.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/extflash.h
deleted file mode 100644
index f9bb9547..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/extflash.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\extflash.h
-* \brief Bootloader external flash driver header file.
-* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-#ifndef EXTFLASH_H
-#define EXTFLASH_H
-
-#if (BOOT_NVM_HOOKS_ENABLE > 0)
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-void ExtFlashInit(void);
-blt_int8u ExtFlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data);
-blt_int8u ExtFlashErase(blt_addr addr, blt_int32u len);
-blt_bool ExtFlashDone(void);
-#endif
-
-#endif /* EXTFLASH_H */
-/*********************************** end of extflash.h *********************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/hooks.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/hooks.c
deleted file mode 100644
index 0104cd90..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/hooks.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\hooks.c
-* \brief Bootloader callback source file.
-* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "boot.h" /* bootloader generic header */
-#include "lpc2294.h" /* CPU register definitions */
-
-
-/****************************************************************************************
-* B A C K D O O R E N T R Y H O O K F U N C T I O N S
-****************************************************************************************/
-
-#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
-/************************************************************************************//**
-** \brief Initializes the backdoor entry option.
-** \return none.
-**
-****************************************************************************************/
-void BackDoorInitHook(void)
-{
- /* configure the button connected to P0.16 as a digital input */
- IO0DIR &= ~(1<<16);
-} /*** end of BackDoorInitHook ***/
-
-
-/************************************************************************************//**
-** \brief Checks if a backdoor entry is requested.
-** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
-**
-****************************************************************************************/
-blt_bool BackDoorEntryHook(void)
-{
- /* button P0.16 has a pullup, so will read high by default. enter backdoor only when
- * this button is pressed. this is the case when it reads low */
- if ((IO0PIN & (1<<16)) == 0)
- {
- return BLT_TRUE;
- }
- return BLT_FALSE;
-} /*** end of BackDoorEntryHook ***/
-#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
-
-
-/****************************************************************************************
-* C P U D R I V E R H O O K F U N C T I O N S
-****************************************************************************************/
-
-#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
-/************************************************************************************//**
-** \brief Callback that gets called when the bootloader is about to exit and
-** hand over control to the user program. This is the last moment that
-** some final checking can be performed and if necessary prevent the
-** bootloader from activiting the user program.
-** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
-** keep the bootloader active.
-**
-****************************************************************************************/
-blt_bool CpuUserProgramStartHook(void)
-{
- /* okay to start the user program */
- return BLT_TRUE;
-} /*** end of CpuUserProgramStartHook ***/
-#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
-
-
-/****************************************************************************************
-* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
-****************************************************************************************/
-
-#if (BOOT_NVM_HOOKS_ENABLE > 0)
-#include "extflash.h"
-/************************************************************************************//**
-** \brief Callback that gets called at the start of the internal NVM driver
-** initialization routine.
-** \return none.
-**
-****************************************************************************************/
-void NvmInitHook(void)
-{
- /* init the external flash driver */
- ExtFlashInit();
-} /*** end of NvmInitHook ***/
-
-
-/************************************************************************************//**
-** \brief Callback that gets called at the start of a firmware update to reinitialize
-** the NVM driver.
-** \return none.
-**
-****************************************************************************************/
-void NvmReinitHook(void)
-{
-} /*** end of NvmReinitHook ***/
-
-
-/************************************************************************************//**
-** \brief Callback that gets called at the start of the NVM driver write
-** routine. It allows additional memory to be operated on. If the address
-** is not within the range of the additional memory, then
-** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
-** been written yet.
-** \param addr Start address.
-** \param len Length in bytes.
-** \param data Pointer to the data buffer.
-** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
-** not within the supported memory range, or BLT_NVM_ERROR is the write
-** operation failed.
-**
-****************************************************************************************/
-blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
-{
- /* attempt to write with the external flash driver */
- return ExtFlashWrite(addr, len, data);
-} /*** end of NvmWriteHook ***/
-
-
-/************************************************************************************//**
-** \brief Callback that gets called at the start of the NVM driver erase
-** routine. It allows additional memory to be operated on. If the address
-** is not within the range of the additional memory, then
-** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
-** hasn't been erased yet.
-** \param addr Start address.
-** \param len Length in bytes.
-** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
-** not within the supported memory range, or BLT_NVM_ERROR is the erase
-** operation failed.
-**
-****************************************************************************************/
-blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
-{
- /* attempt to erase with the external flash driver */
- return ExtFlashErase(addr, len);
-} /*** end of NvmEraseHook ***/
-
-
-/************************************************************************************//**
-** \brief Callback that gets called at the end of the NVM programming session.
-** \return BLT_TRUE is successful, BLT_FALSE otherwise.
-**
-****************************************************************************************/
-blt_bool NvmDoneHook(void)
-{
- /* finish up the operations of the external flash driver */
- return ExtFlashDone();
-} /*** end of NvmDoneHook ***/
-#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
-
-
-#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
-/************************************************************************************//**
-** \brief Verifies the checksum, which indicates that a valid user program is
-** present and can be started.
-** \return BLT_TRUE if successful, BLT_FALSE otherwise.
-**
-****************************************************************************************/
-blt_bool NvmVerifyChecksumHook(void)
-{
- return BLT_TRUE;
-} /*** end of NvmVerifyChecksum ***/
-
-
-/************************************************************************************//**
-** \brief Writes a checksum of the user program to non-volatile memory. This is
-** performed once the entire user program has been programmed. Through
-** the checksum, the bootloader can check if a valid user programming is
-** present and can be started.
-** \return BLT_TRUE if successful, BLT_FALSE otherwise.
-**
-****************************************************************************************/
-blt_bool NvmWriteChecksumHook(void)
-{
- return BLT_TRUE;
-}
-#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
-
-
-/****************************************************************************************
-* W A T C H D O G D R I V E R H O O K F U N C T I O N S
-****************************************************************************************/
-
-#if (BOOT_COP_HOOKS_ENABLE > 0)
-/************************************************************************************//**
-** \brief Callback that gets called at the end of the internal COP driver
-** initialization routine. It can be used to configure and enable the
-** watchdog.
-** \return none.
-**
-****************************************************************************************/
-void CopInitHook(void)
-{
-} /*** end of CopInitHook ***/
-
-
-/************************************************************************************//**
-** \brief Callback that gets called at the end of the internal COP driver
-** service routine. This gets called upon initialization and during
-** potential long lasting loops and routine. It can be used to service
-** the watchdog to prevent a watchdog reset.
-** \return none.
-**
-****************************************************************************************/
-void CopServiceHook(void)
-{
-} /*** end of CopServiceHook ***/
-#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
-
-
-/****************************************************************************************
-* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S
-****************************************************************************************/
-
-#if (BOOT_XCP_SEED_KEY_ENABLE > 0)
-/************************************************************************************//**
-** \brief Provides a seed to the XCP master that will be used for the key
-** generation when the master attempts to unlock the specified resource.
-** Called by the GET_SEED command.
-** \param resource Resource that the seed if requested for (XCP_RES_XXX).
-** \param seed Pointer to byte buffer wher the seed will be stored.
-** \return Length of the seed in bytes.
-**
-****************************************************************************************/
-blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)
-{
- /* request seed for unlocking ProGraMming resource */
- if ((resource & XCP_RES_PGM) != 0)
- {
- seed[0] = 0x55;
- }
-
- /* return seed length */
- return 1;
-} /*** end of XcpGetSeedHook ***/
-
-
-/************************************************************************************//**
-** \brief Called by the UNLOCK command and checks if the key to unlock the
-** specified resource was correct. If so, then the resource protection
-** will be removed.
-** \param resource resource to unlock (XCP_RES_XXX).
-** \param key pointer to the byte buffer holding the key.
-** \param len length of the key in bytes.
-** \return 1 if the key was correct, 0 otherwise.
-**
-****************************************************************************************/
-blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)
-{
- /* suppress compiler warning for unused parameter */
- len = len;
-
- /* the example key algorithm in "FeaserKey.dll" works as follows:
- * - PGM will be unlocked if key = seed - 1
- */
-
- /* check key for unlocking ProGraMming resource */
- if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))
- {
- /* correct key received for unlocking PGM resource */
- return 1;
- }
-
- /* still here so key incorrect */
- return 0;
-} /*** end of XcpVerifyKeyHook ***/
-#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */
-
-
-
-/*********************************** end of hooks.c ************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzp b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzp
deleted file mode 100644
index f520e7db..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzp
+++ /dev/null
@@ -1,67 +0,0 @@
-
-
-
-
-
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-
-
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-
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzs b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzs
deleted file mode 100644
index 8dad7215..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzs
+++ /dev/null
@@ -1,57 +0,0 @@
-
-
-
-
-
-
-
-
-
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diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/readme.txt b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/readme.txt
deleted file mode 100644
index a49767fb..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/readme.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Integrated Development Environment
-----------------------------------
-Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
-the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/
\ No newline at end of file
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/lpc2294.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/lpc2294.h
deleted file mode 100644
index 07664a2d..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/lpc2294.h
+++ /dev/null
@@ -1,404 +0,0 @@
-/****************************************************************************************
-| Description: NXP LPC2294 register definitions
-| File Name: lpc2294.h
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You have received a copy of the GNU General Public License along with OpenBLT. It
-| should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-|
-****************************************************************************************/
-#ifndef LPC2294_H
-#define LPC2294_H
-
-
-/****************************************************************************************
-* Macro definitions
-****************************************************************************************/
-/* EXTERNAL MEMORY CONTROLLER (EMC) */
-#define BCFG0 (*((volatile unsigned long *) 0xFFE00000)) /* lpc22xx only */
-#define BCFG1 (*((volatile unsigned long *) 0xFFE00004)) /* lpc22xx only */
-#define BCFG2 (*((volatile unsigned long *) 0xFFE00008)) /* lpc22xx only */
-#define BCFG3 (*((volatile unsigned long *) 0xFFE0000C)) /* lpc22xx only */
-
-/* External Interrupts */
-#define EXTINT (*((volatile unsigned char *) 0xE01FC140))
-#define EXTWAKE (*((volatile unsigned char *) 0xE01FC144))
-#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) /* no in lpc210x*/
-#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) /* no in lpc210x*/
-
-/* SMemory mapping control. */
-#define MEMMAP (*((volatile unsigned long *) 0xE01FC040))
-
-/* Phase Locked Loop (PLL) */
-#define PLLCON (*((volatile unsigned char *) 0xE01FC080))
-#define PLLCFG (*((volatile unsigned char *) 0xE01FC084))
-#define PLLSTAT (*((volatile unsigned short*) 0xE01FC088))
-#define PLLFEED (*((volatile unsigned char *) 0xE01FC08C))
-
-/* Power Control */
-#define PCON (*((volatile unsigned char *) 0xE01FC0C0))
-#define PCONP (*((volatile unsigned long *) 0xE01FC0C4))
-
-/* VPB Divider */
-#define VPBDIV (*((volatile unsigned char *) 0xE01FC100))
-
-/* Memory Accelerator Module (MAM) */
-#define MAMCR (*((volatile unsigned char *) 0xE01FC000))
-#define MAMTIM (*((volatile unsigned char *) 0xE01FC004))
-
-/* Vectored Interrupt Controller (VIC) */
-#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000))
-#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004))
-#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008))
-#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C))
-#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010))
-#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014))
-#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018))
-#define VICSoftIntClear (*((volatile unsigned long *) 0xFFFFF01C))
-#define VICProtection (*((volatile unsigned long *) 0xFFFFF020))
-#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030))
-#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034))
-#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100))
-#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104))
-#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108))
-#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C))
-#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110))
-#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114))
-#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118))
-#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C))
-#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120))
-#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124))
-#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128))
-#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C))
-#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130))
-#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134))
-#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138))
-#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C))
-#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200))
-#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204))
-#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208))
-#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C))
-#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210))
-#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214))
-#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218))
-#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C))
-#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220))
-#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224))
-#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228))
-#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C))
-#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230))
-#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234))
-#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238))
-#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C))
-
-/* Pin Connect Block */
-#define PINSEL0 (*((volatile unsigned long *) 0xE002C000))
-#define PINSEL1 (*((volatile unsigned long *) 0xE002C004))
-#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) /* no in lpc210x*/
-
-/* General Purpose Input/Output (GPIO) */
-#define IOPIN (*((volatile unsigned long *) 0xE0028000)) /* lpc210x only */
-#define IOSET (*((volatile unsigned long *) 0xE0028004)) /* lpc210x only */
-#define IODIR (*((volatile unsigned long *) 0xE0028008)) /* lpc210x only */
-#define IOCLR (*((volatile unsigned long *) 0xE002800C)) /* lpc210x only */
-
-#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) /* no in lpc210x*/
-#define IO0SET (*((volatile unsigned long *) 0xE0028004)) /* no in lpc210x*/
-#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) /* no in lpc210x*/
-#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) /* no in lpc210x*/
-
-#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) /* no in lpc210x*/
-#define IO1SET (*((volatile unsigned long *) 0xE0028014)) /* no in lpc210x*/
-#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) /* no in lpc210x*/
-#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) /* no in lpc210x*/
-
-#define IO2PIN (*((volatile unsigned long *) 0xE0028020)) /* lpc22xx only */
-#define IO2SET (*((volatile unsigned long *) 0xE0028024)) /* lpc22xx only */
-#define IO2DIR (*((volatile unsigned long *) 0xE0028028)) /* lpc22xx only */
-#define IO2CLR (*((volatile unsigned long *) 0xE002802C)) /* lpc22xx only */
-
-#define IO3PIN (*((volatile unsigned long *) 0xE0028030)) /* lpc22xx only */
-#define IO3SET (*((volatile unsigned long *) 0xE0028034)) /* lpc22xx only */
-#define IO3DIR (*((volatile unsigned long *) 0xE0028038)) /* lpc22xx only */
-#define IO3CLR (*((volatile unsigned long *) 0xE002803C)) /* lpc22xx only */
-
-/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
-#define U0RBR (*((volatile unsigned char *) 0xE000C000))
-#define U0THR (*((volatile unsigned char *) 0xE000C000))
-#define U0IER (*((volatile unsigned char *) 0xE000C004))
-#define U0IIR (*((volatile unsigned char *) 0xE000C008))
-#define U0FCR (*((volatile unsigned char *) 0xE000C008))
-#define U0LCR (*((volatile unsigned char *) 0xE000C00C))
-#define U0LSR (*((volatile unsigned char *) 0xE000C014))
-#define U0SCR (*((volatile unsigned char *) 0xE000C01C))
-#define U0DLL (*((volatile unsigned char *) 0xE000C000))
-#define U0DLM (*((volatile unsigned char *) 0xE000C004))
-
-/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
-#define U1RBR (*((volatile unsigned char *) 0xE0010000))
-#define U1THR (*((volatile unsigned char *) 0xE0010000))
-#define U1IER (*((volatile unsigned char *) 0xE0010004))
-#define U1IIR (*((volatile unsigned char *) 0xE0010008))
-#define U1FCR (*((volatile unsigned char *) 0xE0010008))
-#define U1LCR (*((volatile unsigned char *) 0xE001000C))
-#define U1MCR (*((volatile unsigned char *) 0xE0010010))
-#define U1LSR (*((volatile unsigned char *) 0xE0010014))
-#define U1MSR (*((volatile unsigned char *) 0xE0010018))
-#define U1SCR (*((volatile unsigned char *) 0xE001001C))
-#define U1DLL (*((volatile unsigned char *) 0xE0010000))
-#define U1DLM (*((volatile unsigned char *) 0xE0010004))
-
-/* I2C (8/16 bit data bus) */
-#define I2CONSET (*((volatile unsigned long *) 0xE001C000))
-#define I2STAT (*((volatile unsigned long *) 0xE001C004))
-#define I2DAT (*((volatile unsigned long *) 0xE001C008))
-#define I2ADR (*((volatile unsigned long *) 0xE001C00C))
-#define I2SCLH (*((volatile unsigned long *) 0xE001C010))
-#define I2SCLL (*((volatile unsigned long *) 0xE001C014))
-#define I2CONCLR (*((volatile unsigned long *) 0xE001C018))
-
-/* SPI (Serial Peripheral Interface) */
- /* only for lpc210x*/
-#define SPI_SPCR (*((volatile unsigned char *) 0xE0020000))
-#define SPI_SPSR (*((volatile unsigned char *) 0xE0020004))
-#define SPI_SPDR (*((volatile unsigned char *) 0xE0020008))
-#define SPI_SPCCR (*((volatile unsigned char *) 0xE002000C))
-#define SPI_SPINT (*((volatile unsigned char *) 0xE002001C))
-
-#define S0PCR (*((volatile unsigned char *) 0xE0020000)) /* no in lpc210x*/
-#define S0PSR (*((volatile unsigned char *) 0xE0020004)) /* no in lpc210x*/
-#define S0PDR (*((volatile unsigned char *) 0xE0020008)) /* no in lpc210x*/
-#define S0PCCR (*((volatile unsigned char *) 0xE002000C)) /* no in lpc210x*/
-#define S0PINT (*((volatile unsigned char *) 0xE002001C)) /* no in lpc210x*/
-
-#define S1PCR (*((volatile unsigned char *) 0xE0030000)) /* no in lpc210x*/
-#define S1PSR (*((volatile unsigned char *) 0xE0030004)) /* no in lpc210x*/
-#define S1PDR (*((volatile unsigned char *) 0xE0030008)) /* no in lpc210x*/
-#define S1PCCR (*((volatile unsigned char *) 0xE003000C)) /* no in lpc210x*/
-#define S1PINT (*((volatile unsigned char *) 0xE003001C)) /* no in lpc210x*/
-
-/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
-#define CAN1MOD (*((volatile unsigned long *) 0xE0044000)) /* All CAN Parts */
-#define CAN1CMR (*((volatile unsigned long *) 0xE0044004)) /* All CAN Parts */
-#define CAN1GSR (*((volatile unsigned long *) 0xE0044008)) /* All CAN Parts */
-#define CAN1ICR (*((volatile unsigned long *) 0xE004400C)) /* All CAN Parts */
-#define CAN1IER (*((volatile unsigned long *) 0xE0044010)) /* All CAN Parts */
-#define CAN1BTR (*((volatile unsigned long *) 0xE0044014)) /* All CAN Parts */
-#define CAN1EWL (*((volatile unsigned long *) 0xE0044018)) /* All CAN Parts */
-#define CAN1SR (*((volatile unsigned long *) 0xE004401C)) /* All CAN Parts */
-#define CAN1RFS (*((volatile unsigned long *) 0xE0044020)) /* All CAN Parts */
-#define CAN1RID (*((volatile unsigned long *) 0xE0044024)) /* All CAN Parts */
-#define CAN1RDA (*((volatile unsigned long *) 0xE0044028)) /* All CAN Parts */
-#define CAN1RDB (*((volatile unsigned long *) 0xE004402C)) /* All CAN Parts */
-#define CAN1TFI1 (*((volatile unsigned long *) 0xE0044030)) /* All CAN Parts */
-#define CAN1TID1 (*((volatile unsigned long *) 0xE0044034)) /* All CAN Parts */
-#define CAN1TDA1 (*((volatile unsigned long *) 0xE0044038)) /* All CAN Parts */
-#define CAN1TDB1 (*((volatile unsigned long *) 0xE004403C)) /* All CAN Parts */
-#define CAN1TFI2 (*((volatile unsigned long *) 0xE0044040)) /* All CAN Parts */
-#define CAN1TID2 (*((volatile unsigned long *) 0xE0044044)) /* All CAN Parts */
-#define CAN1TDA2 (*((volatile unsigned long *) 0xE0044048)) /* All CAN Parts */
-#define CAN1TDB2 (*((volatile unsigned long *) 0xE004404C)) /* All CAN Parts */
-#define CAN1TFI3 (*((volatile unsigned long *) 0xE0044050)) /* All CAN Parts */
-#define CAN1TID3 (*((volatile unsigned long *) 0xE0044054)) /* All CAN Parts */
-#define CAN1TDA3 (*((volatile unsigned long *) 0xE0044058)) /* All CAN Parts */
-#define CAN1TDB3 (*((volatile unsigned long *) 0xE004405C)) /* All CAN Parts */
-
-#define CAN2MOD (*((volatile unsigned long *) 0xE0048000)) /* All CAN Parts */
-#define CAN2CMR (*((volatile unsigned long *) 0xE0048004)) /* All CAN Parts */
-#define CAN2GSR (*((volatile unsigned long *) 0xE0048008)) /* All CAN Parts */
-#define CAN2ICR (*((volatile unsigned long *) 0xE004800C)) /* All CAN Parts */
-#define CAN2IER (*((volatile unsigned long *) 0xE0048010)) /* All CAN Parts */
-#define CAN2BTR (*((volatile unsigned long *) 0xE0048014)) /* All CAN Parts */
-#define CAN2EWL (*((volatile unsigned long *) 0xE0048018)) /* All CAN Parts */
-#define CAN2SR (*((volatile unsigned long *) 0xE004801C)) /* All CAN Parts */
-#define CAN2RFS (*((volatile unsigned long *) 0xE0048020)) /* All CAN Parts */
-#define CAN2RID (*((volatile unsigned long *) 0xE0048024)) /* All CAN Parts */
-#define CAN2RDA (*((volatile unsigned long *) 0xE0048028)) /* All CAN Parts */
-#define CAN2RDB (*((volatile unsigned long *) 0xE004802C)) /* All CAN Parts */
-#define CAN2TFI1 (*((volatile unsigned long *) 0xE0048030)) /* All CAN Parts */
-#define CAN2TID1 (*((volatile unsigned long *) 0xE0048034)) /* All CAN Parts */
-#define CAN2TDA1 (*((volatile unsigned long *) 0xE0048038)) /* All CAN Parts */
-#define CAN2TDB1 (*((volatile unsigned long *) 0xE004803C)) /* All CAN Parts */
-#define CAN2TFI2 (*((volatile unsigned long *) 0xE0048040)) /* All CAN Parts */
-#define CAN2TID2 (*((volatile unsigned long *) 0xE0048044)) /* All CAN Parts */
-#define CAN2TDA2 (*((volatile unsigned long *) 0xE0048048)) /* All CAN Parts */
-#define CAN2TDB2 (*((volatile unsigned long *) 0xE004804C)) /* All CAN Parts */
-#define CAN2TFI3 (*((volatile unsigned long *) 0xE0048050)) /* All CAN Parts */
-#define CAN2TID3 (*((volatile unsigned long *) 0xE0048054)) /* All CAN Parts */
-#define CAN2TDA3 (*((volatile unsigned long *) 0xE0048058)) /* All CAN Parts */
-#define CAN2TDB3 (*((volatile unsigned long *) 0xE004805C)) /* All CAN Parts */
-
-#define CAN3MOD (*((volatile unsigned long *) 0xE004C000)) /* lpc2194\lpc2294 only */
-#define CAN3CMR (*((volatile unsigned long *) 0xE004C004)) /* lpc2194\lpc2294 only */
-#define CAN3GSR (*((volatile unsigned long *) 0xE004C008)) /* lpc2194\lpc2294 only */
-#define CAN3ICR (*((volatile unsigned long *) 0xE004C00C)) /* lpc2194\lpc2294 only */
-#define CAN3IER (*((volatile unsigned long *) 0xE004C010)) /* lpc2194\lpc2294 only */
-#define CAN3BTR (*((volatile unsigned long *) 0xE004C014)) /* lpc2194\lpc2294 only */
-#define CAN3EWL (*((volatile unsigned long *) 0xE004C018)) /* lpc2194\lpc2294 only */
-#define CAN3SR (*((volatile unsigned long *) 0xE004C01C)) /* lpc2194\lpc2294 only */
-#define CAN3RFS (*((volatile unsigned long *) 0xE004C020)) /* lpc2194\lpc2294 only */
-#define CAN3RID (*((volatile unsigned long *) 0xE004C024)) /* lpc2194\lpc2294 only */
-#define CAN3RDA (*((volatile unsigned long *) 0xE004C028)) /* lpc2194\lpc2294 only */
-#define CAN3RDB (*((volatile unsigned long *) 0xE004C02C)) /* lpc2194\lpc2294 only */
-#define CAN3TFI1 (*((volatile unsigned long *) 0xE004C030)) /* lpc2194\lpc2294 only */
-#define CAN3TID1 (*((volatile unsigned long *) 0xE004C034)) /* lpc2194\lpc2294 only */
-#define CAN3TDA1 (*((volatile unsigned long *) 0xE004C038)) /* lpc2194\lpc2294 only */
-#define CAN3TDB1 (*((volatile unsigned long *) 0xE004C03C)) /* lpc2194\lpc2294 only */
-#define CAN3TFI2 (*((volatile unsigned long *) 0xE004C040)) /* lpc2194\lpc2294 only */
-#define CAN3TID2 (*((volatile unsigned long *) 0xE004C044)) /* lpc2194\lpc2294 only */
-#define CAN3TDA2 (*((volatile unsigned long *) 0xE004C048)) /* lpc2194\lpc2294 only */
-#define CAN3TDB2 (*((volatile unsigned long *) 0xE004C04C)) /* lpc2194\lpc2294 only */
-#define CAN3TFI3 (*((volatile unsigned long *) 0xE004C050)) /* lpc2194\lpc2294 only */
-#define CAN3TID3 (*((volatile unsigned long *) 0xE004C054)) /* lpc2194\lpc2294 only */
-#define CAN3TDA3 (*((volatile unsigned long *) 0xE004C058)) /* lpc2194\lpc2294 only */
-#define CAN3TDB3 (*((volatile unsigned long *) 0xE004C05C)) /* lpc2194\lpc2294 only */
-
-#define CAN4MOD (*((volatile unsigned long *) 0xE0050000)) /* lpc2194\lpc2294 only */
-#define CAN4CMR (*((volatile unsigned long *) 0xE0050004)) /* lpc2194\lpc2294 only */
-#define CAN4GSR (*((volatile unsigned long *) 0xE0050008)) /* lpc2194\lpc2294 only */
-#define CAN4ICR (*((volatile unsigned long *) 0xE005000C)) /* lpc2194\lpc2294 only */
-#define CAN4IER (*((volatile unsigned long *) 0xE0050010)) /* lpc2194\lpc2294 only */
-#define CAN4BTR (*((volatile unsigned long *) 0xE0050014)) /* lpc2194\lpc2294 only */
-#define CAN4EWL (*((volatile unsigned long *) 0xE0050018)) /* lpc2194\lpc2294 only */
-#define CAN4SR (*((volatile unsigned long *) 0xE005001C)) /* lpc2194\lpc2294 only */
-#define CAN4RFS (*((volatile unsigned long *) 0xE0050020)) /* lpc2194\lpc2294 only */
-#define CAN4RID (*((volatile unsigned long *) 0xE0050024)) /* lpc2194\lpc2294 only */
-#define CAN4RDA (*((volatile unsigned long *) 0xE0050028)) /* lpc2194\lpc2294 only */
-#define CAN4RDB (*((volatile unsigned long *) 0xE005002C)) /* lpc2194\lpc2294 only */
-#define CAN4TFI1 (*((volatile unsigned long *) 0xE0050030)) /* lpc2194\lpc2294 only */
-#define CAN4TID1 (*((volatile unsigned long *) 0xE0050034)) /* lpc2194\lpc2294 only */
-#define CAN4TDA1 (*((volatile unsigned long *) 0xE0050038)) /* lpc2194\lpc2294 only */
-#define CAN4TDB1 (*((volatile unsigned long *) 0xE005003C)) /* lpc2194\lpc2294 only */
-#define CAN4TFI2 (*((volatile unsigned long *) 0xE0050040)) /* lpc2194\lpc2294 only */
-#define CAN4TID2 (*((volatile unsigned long *) 0xE0050044)) /* lpc2194\lpc2294 only */
-#define CAN4TDA2 (*((volatile unsigned long *) 0xE0050048)) /* lpc2194\lpc2294 only */
-#define CAN4TDB2 (*((volatile unsigned long *) 0xE005004C)) /* lpc2194\lpc2294 only */
-#define CAN4TFI3 (*((volatile unsigned long *) 0xE0050050)) /* lpc2194\lpc2294 only */
-#define CAN4TID3 (*((volatile unsigned long *) 0xE0050054)) /* lpc2194\lpc2294 only */
-#define CAN4TDA3 (*((volatile unsigned long *) 0xE0050058)) /* lpc2194\lpc2294 only */
-#define CAN4TDB3 (*((volatile unsigned long *) 0xE005005C)) /* lpc2194\lpc2294 only */
-
-
-#define CANTxSR (*((volatile unsigned long *) 0xE0040000)) /* ALL CAN Parts */
-#define CANRxSR (*((volatile unsigned long *) 0xE0040004)) /* ALL CAN Parts */
-#define CANMSR (*((volatile unsigned long *) 0xE0040008)) /* ALL CAN Parts */
-
-#define CANAFMR (*((volatile unsigned char *) 0xE003C000)) /* ALL CAN Parts */
-#define CANSFF_sa (*((volatile unsigned short*) 0xE003C004)) /* ALL CAN Parts */
-#define CANSFF_GRP_sa (*((volatile unsigned short*) 0xE003C008)) /* ALL CAN Parts */
-#define CANEFF_sa (*((volatile unsigned short*) 0xE003C00C)) /* ALL CAN Parts */
-#define CANEFF_GRP_sa (*((volatile unsigned short*) 0xE003C010)) /* ALL CAN Parts */
-#define CANENDofTable (*((volatile unsigned short*) 0xE003C014)) /* ALL CAN Parts */
-#define CANLUTerrAd (*((volatile unsigned short*) 0xE003C018)) /* ALL CAN Parts */
-#define CANLUTerr (*((volatile unsigned char *) 0xE003C01C)) /* ALL CAN Parts */
-
-
-/* Timer 0 */
-#define T0IR (*((volatile unsigned long *) 0xE0004000))
-#define T0TCR (*((volatile unsigned long *) 0xE0004004))
-#define T0TC (*((volatile unsigned long *) 0xE0004008))
-#define T0PR (*((volatile unsigned long *) 0xE000400C))
-#define T0PC (*((volatile unsigned long *) 0xE0004010))
-#define T0MCR (*((volatile unsigned long *) 0xE0004014))
-#define T0MR0 (*((volatile unsigned long *) 0xE0004018))
-#define T0MR1 (*((volatile unsigned long *) 0xE000401C))
-#define T0MR2 (*((volatile unsigned long *) 0xE0004020))
-#define T0MR3 (*((volatile unsigned long *) 0xE0004024))
-#define T0CCR (*((volatile unsigned long *) 0xE0004028))
-#define T0CR0 (*((volatile unsigned long *) 0xE000402C))
-#define T0CR1 (*((volatile unsigned long *) 0xE0004030))
-#define T0CR2 (*((volatile unsigned long *) 0xE0004034))
-#define T0CR3 (*((volatile unsigned long *) 0xE0004038))
-#define T0EMR (*((volatile unsigned long *) 0xE000403C))
-
-/* Timer 1 */
-#define T1IR (*((volatile unsigned long *) 0xE0008000))
-#define T1TCR (*((volatile unsigned long *) 0xE0008004))
-#define T1TC (*((volatile unsigned long *) 0xE0008008))
-#define T1PR (*((volatile unsigned long *) 0xE000800C))
-#define T1PC (*((volatile unsigned long *) 0xE0008010))
-#define T1MCR (*((volatile unsigned long *) 0xE0008014))
-#define T1MR0 (*((volatile unsigned long *) 0xE0008018))
-#define T1MR1 (*((volatile unsigned long *) 0xE000801C))
-#define T1MR2 (*((volatile unsigned long *) 0xE0008020))
-#define T1MR3 (*((volatile unsigned long *) 0xE0008024))
-#define T1CCR (*((volatile unsigned long *) 0xE0008028))
-#define T1CR0 (*((volatile unsigned long *) 0xE000802C))
-#define T1CR1 (*((volatile unsigned long *) 0xE0008030))
-#define T1CR2 (*((volatile unsigned long *) 0xE0008034))
-#define T1CR3 (*((volatile unsigned long *) 0xE0008038))
-#define T1EMR (*((volatile unsigned long *) 0xE000803C))
-
-/* Pulse Width Modulator (PWM) */
-#define PWMIR (*((volatile unsigned long *) 0xE0014000))
-#define PWMTCR (*((volatile unsigned long *) 0xE0014004))
-#define PWMTC (*((volatile unsigned long *) 0xE0014008))
-#define PWMPR (*((volatile unsigned long *) 0xE001400C))
-#define PWMPC (*((volatile unsigned long *) 0xE0014010))
-#define PWMMCR (*((volatile unsigned long *) 0xE0014014))
-#define PWMMR0 (*((volatile unsigned long *) 0xE0014018))
-#define PWMMR1 (*((volatile unsigned long *) 0xE001401C))
-#define PWMMR2 (*((volatile unsigned long *) 0xE0014020))
-#define PWMMR3 (*((volatile unsigned long *) 0xE0014024))
-#define PWMMR4 (*((volatile unsigned long *) 0xE0014040))
-#define PWMMR5 (*((volatile unsigned long *) 0xE0014044))
-#define PWMMR6 (*((volatile unsigned long *) 0xE0014048))
-#define PWMPCR (*((volatile unsigned long *) 0xE001404C))
-#define PWMLER (*((volatile unsigned long *) 0xE0014050))
-
-/* A/D CONVERTER */
-#define ADCR (*((volatile unsigned long *) 0xE0034000)) /* no in lpc210x*/
-#define ADDR (*((volatile unsigned long *) 0xE0034004)) /* no in lpc210x*/
-
-/* Real Time Clock */
-#define ILR (*((volatile unsigned char *) 0xE0024000))
-#define CTC (*((volatile unsigned short*) 0xE0024004))
-#define CCR (*((volatile unsigned char *) 0xE0024008))
-#define CIIR (*((volatile unsigned char *) 0xE002400C))
-#define AMR (*((volatile unsigned char *) 0xE0024010))
-#define CTIME0 (*((volatile unsigned long *) 0xE0024014))
-#define CTIME1 (*((volatile unsigned long *) 0xE0024018))
-#define CTIME2 (*((volatile unsigned long *) 0xE002401C))
-#define SEC (*((volatile unsigned char *) 0xE0024020))
-#define MIN (*((volatile unsigned char *) 0xE0024024))
-#define HOUR (*((volatile unsigned char *) 0xE0024028))
-#define DOM (*((volatile unsigned char *) 0xE002402C))
-#define DOW (*((volatile unsigned char *) 0xE0024030))
-#define DOY (*((volatile unsigned short*) 0xE0024034))
-#define MONTH (*((volatile unsigned char *) 0xE0024038))
-#define YEAR (*((volatile unsigned short*) 0xE002403C))
-#define ALSEC (*((volatile unsigned char *) 0xE0024060))
-#define ALMIN (*((volatile unsigned char *) 0xE0024064))
-#define ALHOUR (*((volatile unsigned char *) 0xE0024068))
-#define ALDOM (*((volatile unsigned char *) 0xE002406C))
-#define ALDOW (*((volatile unsigned char *) 0xE0024070))
-#define ALDOY (*((volatile unsigned short*) 0xE0024074))
-#define ALMON (*((volatile unsigned char *) 0xE0024078))
-#define ALYEAR (*((volatile unsigned short*) 0xE002407C))
-#define PREINT (*((volatile unsigned short*) 0xE0024080))
-#define PREFRAC (*((volatile unsigned short*) 0xE0024084))
-
-/* Watchdog */
-#define WDMOD (*((volatile unsigned char *) 0xE0000000))
-#define WDTC (*((volatile unsigned long *) 0xE0000004))
-#define WDFEED (*((volatile unsigned char *) 0xE0000008))
-#define WDTV (*((volatile unsigned long *) 0xE000000C))
-
-#endif /* LPC2294_H */
-/*********************************** end of lpc2294.h **********************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/main.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/main.c
deleted file mode 100644
index 4f79f95b..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/main.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\main.c
-* \brief Bootloader application source file.
-* \ingroup Boot_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "boot.h" /* bootloader generic header */
-#include "lpc2294.h" /* CPU register definitions */
-
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-static void Init(void);
-
-
-/************************************************************************************//**
-** \brief This is the entry point for the bootloader application and is called
-** by the reset interrupt vector after the C-startup routines executed.
-** \return Program return code.
-**
-****************************************************************************************/
-int main(void)
-{
- /* initialize the microcontroller */
- Init();
- /* initialize the bootloader */
- BootInit();
- /* start the infinite program loop */
- while (1)
- {
- /* run the bootloader task */
- BootTask();
- }
-
- /* program should never get here */
- return 0;
-} /*** end of main ***/
-
-
-/************************************************************************************//**
-** \brief Initializes the microcontroller. The Fpll is set to 60MHz and Fvpb is
-** configured equal to Fpll. The GPIO pin of the status LED is configured
-** as digital output.
-** \return none.
-**
-****************************************************************************************/
-static void Init(void)
-{
- blt_int8u m_sel; /* pll multiplier register value */
- static blt_int8u pll_dividers[] = { 1, 2, 4, 8 }; /* possible pll dividers */
- blt_int8u p_sel_cnt; /* loop counter to find p_sel */
- blt_int32u f_cco; /* current controller oscillator */
-
- /* check that pll multiplier value will be in the range 1..32 */
- ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
- BOOT_CPU_XTAL_SPEED_KHZ >= 1);
-
- ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
- BOOT_CPU_XTAL_SPEED_KHZ <= 32);
-
- /* calculate MSEL: M = round(Fcclk / Fosc) */
- m_sel = (BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
- BOOT_CPU_XTAL_SPEED_KHZ;
- /* value for the PLLCFG register is -1 */
- m_sel--;
-
- /* find PSEL value so that Fcco(= Fcclk * 2 * P) is in the 156000..320000 kHz range. */
- for (p_sel_cnt=0; p_sel_cnt= 156000) && (f_cco <= 320000) )
- {
- /* found a valid pll divider value */
- break;
- }
- }
- /* check that a valid value was found */
- ASSERT_RT(p_sel_cnt < (sizeof(pll_dividers)/sizeof(pll_dividers[0])));
-
- /* set multiplier and divider values */
- PLLCFG = (p_sel_cnt << 5) | m_sel;
- PLLFEED = 0xAA;
- PLLFEED = 0x55;
- /* enable the PLL */
- PLLCON = 0x1;
- PLLFEED = 0xAA;
- PLLFEED = 0x55;
- /* wait for the PLL to lock to set frequency */
- while(!(PLLSTAT & 0x400)) { ; }
- /* connect the PLL as the clock source */
- PLLCON = 0x3;
- PLLFEED = 0xAA;
- PLLFEED = 0x55;
- /* enable MAM and set number of clocks used for Flash memory fetch. Recommended:
- * Fcclk >= 60 MHz: 4 clock cycles
- * Fcclk >= 40 MHz: 3 clock cycles
- * Fcclk >= 20 MHz: 2 clock cycles
- * Fcclk < 20 MHz: 1 clock cycle
- */
- MAMCR = 0x0;
-#if (BOOT_CPU_SYSTEM_SPEED_KHZ >= 60000)
- MAMTIM = 4;
-#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 40000)
- MAMTIM = 3;
-#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 20000)
- MAMTIM = 2;
-#else
- MAMTIM = 1;
-#endif
- MAMCR = 0x2;
- /* setting peripheral Clock (pclk) to System Clock (cclk) */
- VPBDIV = 0x1;
-#if (BOOT_NVM_HOOKS_ENABLE > 0)
- /* in this the external memory on the Olimex LPC-L2294 board is used so configure
- * the memory banks for the external flash EEPROM and RAM
- */
- /* external flash EEPROM:
- * IDCY=3 (idle timing)
- * WST1=4 (read timing)
- * RBLE=1
- * WST2=6 (write timing)
- * MW=1 (16-bit data bus)
- */
- BCFG0 = (0x3 << 0) | (0x4 << 5) | (0x1 << 10) | (0x6 << 11) | (0x1 << 28);
- /* external RAM:
- * IDCY=0 (idle timing)
- * WST1=0 (read timing)
- * RBLE=1
- * WST2=0 (write timing)
- * MW=2 (32-bit data bus)
- */
- BCFG1 = (0x0 << 0) | (0x0 << 5) | (0x1 << 10) | (0x0 << 11) | (0x2 << 28);
- /* configure use of data bus and strobe pins for the external memory */
- PINSEL2 = 0x0F000924;
-#endif
-#if (BOOT_COM_UART_ENABLE > 0)
- /* configure P0.0 for UART0 Tx and P0.1 for UART0 Rx functionality */
- PINSEL0 |= 0x05;
-#endif
-#if (BOOT_COM_CAN_ENABLE > 0)
- /* configure P0.25 for CAN1 Rx functionality */
- PINSEL1 |= 0x00040000L;
-#endif
-} /*** end of Init ***/
-
-
-/*********************************** end of main.c *************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.elf b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.elf
deleted file mode 100644
index fa2b5b52..00000000
Binary files a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.elf and /dev/null differ
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.map b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.map
deleted file mode 100644
index ce9478b9..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.map
+++ /dev/null
@@ -1,1487 +0,0 @@
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-Memory Configuration
-
-Name Origin Length Attributes
-UNPLACED_SECTIONS 0xffffffff 0x00000000 xw
-AHB_Peripherals 0xffe00000 0x00200000 xw
-VPB_Peripherals 0xe0000000 0x00200000 xw
-BANK3 0x83000000 0x01000000 xw
-BANK2 0x82000000 0x01000000 xw
-External_SRAM 0x81000000 0x00100000 xw
-External_FLASH 0x80000000 0x00200000 xr
-SRAM 0x40000200 0x00003ce0 xw
-FLASH 0x00002000 0x0003e000 xr
-*default* 0x00000000 0xffffffff
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-Linker script and memory map
-
- 0x0000459c __do_debug_operation = __do_debug_operation_dcc
- 0x00003350 __vfprintf = __vfprintf_int
- 0x00003e34 __vfscanf = __vfscanf_int
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- 0x00000000 __AHB_Peripherals_segment_end__ = 0x0
- 0xe0000000 __VPB_Peripherals_segment_start__ = 0xe0000000
- 0xe0200000 __VPB_Peripherals_segment_end__ = 0xe0200000
- 0x83000000 __BANK3_segment_start__ = 0x83000000
- 0x84000000 __BANK3_segment_end__ = 0x84000000
- 0x82000000 __BANK2_segment_start__ = 0x82000000
- 0x83000000 __BANK2_segment_end__ = 0x83000000
- 0x81000000 __External_SRAM_segment_start__ = 0x81000000
- 0x81100000 __External_SRAM_segment_end__ = 0x81100000
- 0x80000000 __External_FLASH_segment_start__ = 0x80000000
- 0x80200000 __External_FLASH_segment_end__ = 0x80200000
- 0x40002000 __SRAM_segment_start__ = 0x40002000
- 0x40003ee0 __SRAM_segment_end__ = 0x40003ee0
- 0x00002000 __FLASH_segment_start__ = 0x2000
- 0x00040000 __FLASH_segment_end__ = 0x40000
- 0x00000400 __STACKSIZE__ = 0x400
- 0x00000100 __STACKSIZE_IRQ__ = 0x100
- 0x00000100 __STACKSIZE_FIQ__ = 0x100
- 0x00000100 __STACKSIZE_SVC__ = 0x100
- 0x00000100 __STACKSIZE_ABT__ = 0x100
- 0x00000100 __STACKSIZE_UND__ = 0x100
- 0x00000400 __HEAPSIZE__ = 0x400
- 0x80000000 __text2_load_start__ = ALIGN (__External_FLASH_segment_start__, 0x4)
-
-.text2 0x80000000 0x0
- 0x80000000 __text2_start__ = .
- *(.text2 .text2.*)
- 0x80000000 __text2_end__ = (__text2_start__ + SIZEOF (.text2))
- 0x80000000 __text2_load_end__ = __text2_end__
- 0x00000001 . = ASSERT (((__text2_end__ >= __External_FLASH_segment_start__) && (__text2_end__ <= (__External_FLASH_segment_start__ + 0x400000))), error: .text2 is too large to fit in External_FLASH memory segment)
- 0x80000000 __rodata2_load_start__ = ALIGN (__text2_end__, 0x4)
-
-.rodata2 0x80000000 0x0
- 0x80000000 __rodata2_start__ = .
- *(.rodata2 .rodata2.*)
- 0x80000000 __rodata2_end__ = (__rodata2_start__ + SIZEOF (.rodata2))
- 0x80000000 __rodata2_load_end__ = __rodata2_end__
- 0x00000001 . = ASSERT (((__rodata2_end__ >= __External_FLASH_segment_start__) && (__rodata2_end__ <= (__External_FLASH_segment_start__ + 0x400000))), error: .rodata2 is too large to fit in External_FLASH memory segment)
- 0x80000000 __data2_load_start__ = ALIGN (__rodata2_end__, 0x4)
-
-.data2 0x81000000 0x0 load address 0x80000000
- 0x81000000 __data2_start__ = .
- *(.data2 .data2.*)
- 0x81000000 __data2_end__ = (__data2_start__ + SIZEOF (.data2))
- 0x80000000 __data2_load_end__ = (__data2_load_start__ + SIZEOF (.data2))
- 0x80000000 __External_FLASH_segment_used_end__ = (ALIGN (__rodata2_end__, 0x4) + SIZEOF (.data2))
- 0x00000001 . = ASSERT ((((__data2_load_start__ + SIZEOF (.data2)) >= __External_FLASH_segment_start__) && ((__data2_load_start__ + SIZEOF (.data2)) <= (__External_FLASH_segment_start__ + 0x400000))), error: .data2 is too large to fit in External_FLASH memory segment)
-
-.data2_run 0x81000000 0x0
- 0x81000000 __data2_run_start__ = .
- 0x81000000 . = MAX ((__data2_run_start__ + SIZEOF (.data2)), .)
- 0x81000000 __data2_run_end__ = (__data2_run_start__ + SIZEOF (.data2_run))
- 0x81000000 __data2_run_load_end__ = __data2_run_end__
- 0x00000001 . = ASSERT (((__data2_run_end__ >= __External_SRAM_segment_start__) && (__data2_run_end__ <= (__External_SRAM_segment_start__ + 0x100000))), error: .data2_run is too large to fit in External_SRAM memory segment)
- 0x81000000 __bss2_load_start__ = ALIGN (__data2_run_end__, 0x4)
-
-.bss2 0x81000000 0x0
- 0x81000000 __bss2_start__ = .
- *(.bss2 .bss2.*)
- 0x81000000 __bss2_end__ = (__bss2_start__ + SIZEOF (.bss2))
- 0x81000000 __bss2_load_end__ = __bss2_end__
- 0x81000000 __External_SRAM_segment_used_end__ = (ALIGN (__data2_run_end__, 0x4) + SIZEOF (.bss2))
- 0x00000001 . = ASSERT (((__bss2_end__ >= __External_SRAM_segment_start__) && (__bss2_end__ <= (__External_SRAM_segment_start__ + 0x100000))), error: .bss2 is too large to fit in External_SRAM memory segment)
- 0x40002000 __vectors_ram_load_start__ = __SRAM_segment_start__
-
-.vectors_ram 0x40002000 0x3c
- 0x40002000 __vectors_ram_start__ = .
- *(.vectors_ram .vectors_ram.*)
- 0x4000203c . = MAX ((__vectors_ram_start__ + 0x3c), .)
- *fill* 0x40002000 0x3c 00
- 0x4000203c __vectors_ram_end__ = (__vectors_ram_start__ + SIZEOF (.vectors_ram))
- 0x4000203c __vectors_ram_load_end__ = __vectors_ram_end__
- 0x00000001 . = ASSERT (((__vectors_ram_end__ >= __SRAM_segment_start__) && (__vectors_ram_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .vectors_ram is too large to fit in SRAM memory segment)
- 0x00002000 __vectors_load_start__ = __FLASH_segment_start__
-
-.vectors 0x00002000 0x38
- 0x00002000 __vectors_start__ = .
- *(.vectors .vectors.*)
- .vectors 0x00002000 0x38 ARM Flash Debug/../../obj/cstart.o
- 0x00002000 _vectors
- 0x00002038 __vectors_end__ = (__vectors_start__ + SIZEOF (.vectors))
- 0x00002038 __vectors_load_end__ = __vectors_end__
- 0x00000001 . = ASSERT (((__vectors_end__ >= __FLASH_segment_start__) && (__vectors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .vectors is too large to fit in FLASH memory segment)
- 0x00002038 __init_load_start__ = ALIGN (__vectors_end__, 0x4)
-
-.init 0x00002038 0x218
- 0x00002038 __init_start__ = .
- *(.init .init.*)
- *fill* 0x00002038 0x8 00
- .init 0x00002040 0x210 ARM Flash Debug/../../obj/cstart.o
- 0x00002040 undef_handler
- 0x00002044 swi_handler
- 0x00002048 pabort_handler
- 0x0000204c dabort_handler
- 0x00002050 fiq_handler
- 0x00002054 irq_handler
- 0x00002060 _start
- 0x00002060 __start
- 0x00002178 exit
- 0x00002250 __init_end__ = (__init_start__ + SIZEOF (.init))
- 0x00002250 __init_load_end__ = __init_end__
- 0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .init is too large to fit in FLASH memory segment)
- 0x00002250 __text_load_start__ = ALIGN (__init_end__, 0x4)
-
-.text 0x00002250 0x2608
- 0x00002250 __text_start__ = .
- *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table)
- .glue_7 0x00000000 0x0 linker stubs
- .glue_7t 0x00000000 0x0 linker stubs
- .text.BootComInit
- 0x00002250 0x34 ARM Flash Debug/../../obj/boot.o
- 0x00002250 BootComInit
- .text.BootComCheckActivationRequest
- 0x00002284 0x34 ARM Flash Debug/../../obj/boot.o
- 0x00002284 BootComCheckActivationRequest
- .text.BootActivate
- 0x000022b8 0x5c ARM Flash Debug/../../obj/boot.o
- 0x000022b8 BootActivate
- .text.BootComUartInit
- 0x00002314 0xb8 ARM Flash Debug/../../obj/boot.o
- .text.BootComUartCheckActivationRequest
- 0x000023cc 0x108 ARM Flash Debug/../../obj/boot.o
- .text.UartReceiveByte
- 0x000024d4 0x64 ARM Flash Debug/../../obj/boot.o
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-START GROUP
-LOAD ARM Flash Debug/../../obj/boot.o
-LOAD ARM Flash Debug/../../obj/cstart.o
-LOAD ARM Flash Debug/../../obj/irq.o
-LOAD ARM Flash Debug/../../obj/led.o
-LOAD ARM Flash Debug/../../obj/main.o
-LOAD ARM Flash Debug/../../obj/timer.o
-LOAD ARM Flash Debug/../../obj/vectors.o
-LOAD C:/Users/voorburg/AppData/Local/Rowley Associates Limited/CrossWorks for ARM/packages/lib/liblpc2000_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libarm_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcpp_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_targetio_impl_v4t_a_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v4t_a_le.a
-END GROUP
-OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/../bin/demoprog_olimex_lpc_l2294_20mhz.elf elf32-littlearm)
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diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.c
deleted file mode 100644
index 5a172b5a..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.c
+++ /dev/null
@@ -1,404 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\boot.c
-* \brief Demo program bootloader interface source file.
-* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-#if (BOOT_COM_UART_ENABLE > 0)
-static void BootComUartInit(void);
-static void BootComUartCheckActivationRequest(void);
-#endif
-#if (BOOT_COM_CAN_ENABLE > 0)
-static void BootComCanInit(void);
-static void BootComCanCheckActivationRequest(void);
-#endif
-
-/************************************************************************************//**
-** \brief Initializes the communication interface.
-** \return none.
-**
-****************************************************************************************/
-void BootComInit(void)
-{
-#if (BOOT_COM_UART_ENABLE > 0)
- BootComUartInit();
-#endif
-#if (BOOT_COM_CAN_ENABLE > 0)
- BootComCanInit();
-#endif
-} /*** end of BootComInit ***/
-
-
-/************************************************************************************//**
-** \brief Receives the CONNECT request from the host, which indicates that the
-** bootloader should be activated and, if so, activates it.
-** \return none.
-**
-****************************************************************************************/
-void BootComCheckActivationRequest(void)
-{
-#if (BOOT_COM_UART_ENABLE > 0)
- BootComUartCheckActivationRequest();
-#endif
-#if (BOOT_COM_CAN_ENABLE > 0)
- BootComCanCheckActivationRequest();
-#endif
-} /*** end of BootComCheckActivationRequest ***/
-
-
-/************************************************************************************//**
-** \brief Bootloader activation function. Performs a software reset by configuring
-** and triggering the watchdog.
-** \return none.
-**
-****************************************************************************************/
-void BootActivate(void)
-{
- #define WDEN_BIT (0x01) /* watchdog enable bit (set only) */
- #define WDRESET_BIT (0x02) /* watchdog reset enable bit */
-
- /* configure a short timeout. not really interesting as we won't be using it */
- WDTC = 1024;
- /* enable the watchdog and configure it such that a watchdog timeout causes a reset */
- WDMOD = WDEN_BIT | WDRESET_BIT;
- /* start the watchdog */
- WDFEED = 0xAA;
- WDFEED = 0x55;
- /* write invalid feed sequence to cause an instant reset */
- WDFEED = 0xAA;
- WDFEED = 0x00;
-} /*** end of BootActivate ***/
-
-
-#if (BOOT_COM_UART_ENABLE > 0)
-/****************************************************************************************
-* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E
-****************************************************************************************/
-
-/****************************************************************************************
-* Macro definitions
-****************************************************************************************/
-/** \brief Divisor latch access bit. */
-#define UART_DLAB (0x80)
-/** \brief 8 data and 1 stop bit, no parity. */
-#define UART_MODE_8N1 (0x03)
-/** \brief FIFO reset and RX FIFO 1 deep. */
-#define UART_FIFO_RX1 (0x07)
-/** \brief Receiver data ready. */
-#define UART_RDR (0x01)
-
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-static unsigned char UartReceiveByte(unsigned char *data);
-
-
-/************************************************************************************//**
-** \brief Initializes the UART communication interface.
-** \return none.
-**
-****************************************************************************************/
-static void BootComUartInit(void)
-{
- unsigned long baud_reg_value; /* baudrate register value */
-
- /* configure P0.0 for UART0 Tx and P0.1 for UART0 Rx functionality */
- PINSEL0 |= 0x05;
- /* disable UART related interrupt generation. this driver works in polling mode */
- U0IER = 0;
- /* clear interrupt id register */
- U0IIR = 0;
- /* clear line status register */
- U0LSR = 0;
- /* set divisor latch DLAB = 1 so buadrate can be configured */
- U0LCR = UART_DLAB;
- /* Baudrate calculation:
- * y = BOOT_CPU_SYSTEM_SPEED_KHZ * 1000 / 16 / BOOT_COM_UART_BAUDRATE and add
- * smartness to automatically round the value up/down using the following trick:
- * y = x/n can round with y = (x + (n + 1)/2 ) / n
- */
- baud_reg_value = (((BOOT_CPU_SYSTEM_SPEED_KHZ*1000/16)+ \
- ((BOOT_COM_UART_BAUDRATE+1)/2))/BOOT_COM_UART_BAUDRATE);
- /* write the calculated baudrate selector value to the registers */
- U0DLL = (unsigned char)baud_reg_value;
- U0DLM = (unsigned char)(baud_reg_value >> 8);
- /* configure 8 data bits, no parity and 1 stop bit and set DLAB = 0 */
- U0LCR = UART_MODE_8N1;
- /* enable and reset transmit and receive FIFO. necessary for UART operation */
- U0FCR = UART_FIFO_RX1;
-} /*** end of BootComUartInit ***/
-
-
-/************************************************************************************//**
-** \brief Receives the CONNECT request from the host, which indicates that the
-** bootloader should be activated and, if so, activates it.
-** \return none.
-**
-****************************************************************************************/
-static void BootComUartCheckActivationRequest(void)
-{
- static unsigned char xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1];
- static unsigned char xcpCtoRxLength;
- static unsigned char xcpCtoRxInProgress = 0;
-
- /* start of cto packet received? */
- if (xcpCtoRxInProgress == 0)
- {
- /* store the message length when received */
- if (UartReceiveByte(&xcpCtoReqPacket[0]) == 1)
- {
- /* indicate that a cto packet is being received */
- xcpCtoRxInProgress = 1;
-
- /* reset packet data count */
- xcpCtoRxLength = 0;
- }
- }
- else
- {
- /* store the next packet byte */
- if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
- {
- /* increment the packet data count */
- xcpCtoRxLength++;
-
- /* check to see if the entire packet was received */
- if (xcpCtoRxLength == xcpCtoReqPacket[0])
- {
- /* done with cto packet reception */
- xcpCtoRxInProgress = 0;
-
- /* check if this was an XCP CONNECT command */
- if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00))
- {
- /* connection request received so start the bootloader */
- BootActivate();
- }
- }
- }
- }
-} /*** end of BootComUartCheckActivationRequest ***/
-
-
-/************************************************************************************//**
-** \brief Receives a communication interface byte if one is present.
-** \param data Pointer to byte where the data is to be stored.
-** \return 1 if a byte was received, 0 otherwise.
-**
-****************************************************************************************/
-static unsigned char UartReceiveByte(unsigned char *data)
-{
- /* check if a new byte was received by means of the RDR-bit */
- if((U0LSR & UART_RDR) != 0)
- {
- /* store the received byte */
- data[0] = U0RBR;
- /* inform caller of the newly received byte */
- return 1;
- }
- /* inform caller that no new data was received */
- return 0;
-} /*** end of UartReceiveByte ***/
-#endif /* BOOT_COM_UART_ENABLE > 0 */
-
-
-#if (BOOT_COM_CAN_ENABLE > 0)
-/****************************************************************************************
-* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E
-****************************************************************************************/
-
-/****************************************************************************************
-* Macro definitions
-****************************************************************************************/
-/** \brief Transmit buffer 1 idle. */
-#define CAN_TBS1 (0x00000004)
-/** \brief Transmit buffer 1 complete. */
-#define CAN_TCS1 (0x00000008)
-/** \brief Receive buffer release. */
-#define CAN_RRB (0x04)
-/** \brief Receive buffer status. */
-#define CAN_RBS (0x01)
-/** \brief Transmission request. */
-#define CAN_TR (0x01)
-/** \brief Select tx buffer 1 for transmit. */
-#define CAN_STB1 (0x20)
-
-
-/****************************************************************************************
-* Type definitions
-****************************************************************************************/
-/** \brief Structure type for grouping CAN bus timing related information. */
-typedef struct t_can_bus_timing
-{
- unsigned char tseg1; /**< CAN time segment 1 */
- unsigned char tseg2; /**< CAN time segment 2 */
-} tCanBusTiming;
-
-
-/****************************************************************************************
-* Local constant declarations
-****************************************************************************************/
-/** \brief CAN bittiming table for dynamically calculating the bittiming settings.
- * \details According to the CAN protocol 1 bit-time can be made up of between 8..25
- * time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
- * always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) *
- * 100%. This array contains possible and valid time quanta configurations with
- * a sample point between 68..78%.
- */
-static const tCanBusTiming canTiming[] =
-{ /* TQ | TSEG1 | TSEG2 | SP */
- /* ------------------------- */
- { 5, 2 }, /* 8 | 5 | 2 | 75% */
- { 6, 2 }, /* 9 | 6 | 2 | 78% */
- { 6, 3 }, /* 10 | 6 | 3 | 70% */
- { 7, 3 }, /* 11 | 7 | 3 | 73% */
- { 8, 3 }, /* 12 | 8 | 3 | 75% */
- { 9, 3 }, /* 13 | 9 | 3 | 77% */
- { 9, 4 }, /* 14 | 9 | 4 | 71% */
- { 10, 4 }, /* 15 | 10 | 4 | 73% */
- { 11, 4 }, /* 16 | 11 | 4 | 75% */
- { 12, 4 }, /* 17 | 12 | 4 | 76% */
- { 12, 5 }, /* 18 | 12 | 5 | 72% */
- { 13, 5 }, /* 19 | 13 | 5 | 74% */
- { 14, 5 }, /* 20 | 14 | 5 | 75% */
- { 15, 5 }, /* 21 | 15 | 5 | 76% */
- { 15, 6 }, /* 22 | 15 | 6 | 73% */
- { 16, 6 }, /* 23 | 16 | 6 | 74% */
- { 16, 7 }, /* 24 | 16 | 7 | 71% */
- { 16, 8 } /* 25 | 16 | 8 | 68% */
-};
-
-
-/************************************************************************************//**
-** \brief Search algorithm to match the desired baudrate to a possible bus
-** timing configuration.
-** \param baud The desired baudrate in kbps. Valid values are 10..1000.
-** \param btr Pointer to where the value for register CANxBTR will be stored.
-** \return 1 if the CAN bustiming register values were found, 0 otherwise.
-**
-****************************************************************************************/
-static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned long *btr)
-{
- unsigned short prescaler;
- unsigned char cnt;
-
- /* loop through all possible time quanta configurations to find a match */
- for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
- {
- if ((BOOT_CPU_SYSTEM_SPEED_KHZ % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
- {
- /* compute the prescaler that goes with this TQ configuration */
- prescaler = BOOT_CPU_SYSTEM_SPEED_KHZ/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
-
- /* make sure the prescaler is valid */
- if ( (prescaler > 0) && (prescaler <= 1024) )
- {
- /* store the prescaler and bustiming register value */
- *btr = prescaler - 1;
- *btr |= ((canTiming[cnt].tseg2 - 1) << 20) | ((canTiming[cnt].tseg1 - 1) << 16);
- /* found a good bus timing configuration */
- return 1;
- }
- }
- }
- /* could not find a good bus timing configuration */
- return 0;
-} /*** end of CanGetSpeedConfig ***/
-
-
-/************************************************************************************//**
-** \brief Initializes the CAN communication interface.
-** \return none.
-**
-****************************************************************************************/
-static void BootComCanInit(void)
-{
- unsigned long btr_reg_value;
-
- /* configure acceptance filter for bypass mode so it receives all messages */
- CANAFMR = 0x00000002L;
- /* take CAN controller offline and go into reset mode */
- CAN1MOD = 1;
- /* disable all interrupts. driver only needs to work in polling mode */
- CAN1IER = 0;
- /* reset CAN controller status */
- CAN1GSR = 0;
- /* configure the bittiming */
- if (CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &btr_reg_value) == 1)
- {
- /* write the bittiming configuration to the register */
- CAN1BTR = btr_reg_value;
- }
- /* enter normal operating mode and synchronize to the CAN bus */
- CAN1MOD = 0;
-} /*** end of BootComCanInit ***/
-
-
-/************************************************************************************//**
-** \brief Receives the CONNECT request from the host, which indicates that the
-** bootloader should be activated and, if so, activates it.
-** \return none.
-**
-****************************************************************************************/
-static void BootComCanCheckActivationRequest(void)
-{
- unsigned char data[2];
-
- /* check if a new message was received */
- if ((CAN1SR & CAN_RBS) == 0)
- {
- return;
- }
- /* see if this is the message identifier that we are interested in */
- if (CAN1RID != BOOT_COM_CAN_RX_MSG_ID)
- {
- return;
- }
- /* store the message data */
- data[0] = (unsigned char)CAN1RDA;
- data[1] = (unsigned char)(CAN1RDA >> 8);
- /* release the receive buffer */
- CAN1CMR = CAN_RRB;
- /* check if this was an XCP CONNECT command */
- if ((data[0] == 0xff) && (data[1] == 0x00))
- {
- /* connection request received so start the bootloader */
- BootActivate();
- }
-} /*** end of BootComCanCheckActivationRequest ***/
-#endif /* BOOT_COM_CAN_ENABLE > 0 */
-
-
-/*********************************** end of boot.c *************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.h
deleted file mode 100644
index 450665f8..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\boot.h
-* \brief Demo program bootloader interface header file.
-* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-#ifndef BOOT_H
-#define BOOT_H
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-void BootComInit(void);
-void BootComCheckActivationRequest(void);
-void BootActivate(void);
-
-
-#endif /* BOOT_H */
-/*********************************** end of boot.h *************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/cstart.s b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/cstart.s
deleted file mode 100644
index 35f28e4b..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/cstart.s
+++ /dev/null
@@ -1,415 +0,0 @@
-/*****************************************************************************
- * Copyright (c) 2001, 2002 Rowley Associates Limited. *
- * *
- * This file may be distributed under the terms of the License Agreement *
- * provided with this software. *
- * *
- * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
- * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
- *****************************************************************************/
-
-/*****************************************************************************
- * Preprocessor Definitions
- * ------------------------
- * APP_ENTRY_POINT
- *
- * Defines the application entry point function, if undefined this setting
- * defaults to "main".
- *
- * INITIALIZE_STACKS
- *
- * If defined, the contents of the stacks will be initialized to a the
- * value 0xCC.
- *
- * INITIALIZE_SECONDARY_SECTIONS
- *
- * If defined, the .text2, .data2 and .bss2 sections will be initialized.
- *
- * SUPERVISOR_START
- *
- * If defined, the application will start up in supervisor mode. If
- * undefined the application will start up in system mode.
- *
- * FULL_LIBRARY
- *
- * If defined then
- * - argc, argv are setup by the debug_getargs.
- * - the exit symbol is defined and executes on return from main.
- * - the exit symbol calls destructors, atexit functions and then debug_exit.
- *
- * If not defined then
- * - argc and argv are zero.
- * - the exit symbol is defined, executes on return from main and loops
- *
- *****************************************************************************/
-
- .section .vectors, "ax"
- .code 32
- .align 0
- .global _vectors
- .global reset_handler
-
-/*****************************************************************************
- * Exception Vectors *
- *****************************************************************************/
-_vectors:
- ldr pc, [pc, #reset_handler_address - . - 8] /* reset */
- ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */
- ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */
- ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */
- ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */
- .word 0xB9205F88 /* boot loader checksum */
- ldr pc, [pc, #-0xFF0] /* irq handler */
- ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq handler */
-
-reset_handler_address:
- .word _start
-undef_handler_address:
- .word undef_handler
-swi_handler_address:
- .word swi_handler
-pabort_handler_address:
- .word pabort_handler
-dabort_handler_address:
- .word dabort_handler
-fiq_handler_address:
- .word fiq_handler
-
- .section .init, "ax"
- .code 32
- .align 0
-
-/******************************************************************************
- * *
- * Default exception handlers *
- * *
- ******************************************************************************/
-/******************************************************************************
- * *
- * Default exception handlers *
- * These are declared weak symbols so they can be redefined in user code. *
- * *
- ******************************************************************************/
-undef_handler:
- b undef_handler
-
-swi_handler:
- b swi_handler
-
-pabort_handler:
- b pabort_handler
-
-dabort_handler:
- b dabort_handler
-
-fiq_handler:
- b fiq_handler
-
-irq_handler:
- b irq_handler
-
- .weak undef_handler, swi_handler, pabort_handler, dabort_handler, fiq_handler, irq_handler
-
- .section .init, "ax"
- .code 32
- .align 4
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-
- .weak _start
- .global __start
- .global __gccmain
- .extern APP_ENTRY_POINT
- .global exit
-
-/*****************************************************************************
- * Function : _start *
- * Description : Main entry point and startup code for C system. *
- *****************************************************************************/
-_start:
-__start:
- mrs r0, cpsr
- bic r0, r0, #0x1F
-
- /* Setup stacks */
- orr r1, r0, #0x1B /* Undefined mode */
- msr cpsr_cxsf, r1
- ldr sp, =__stack_und_end__
-#ifdef __ARM_EABI__
- bic sp, sp, #0x7
-#endif
-
- orr r1, r0, #0x17 /* Abort mode */
- msr cpsr_cxsf, r1
- ldr sp, =__stack_abt_end__
-#ifdef __ARM_EABI__
- bic sp, sp, #0x7
-#endif
-
- orr r1, r0, #0x12 /* IRQ mode */
- msr cpsr_cxsf, r1
- ldr sp, =__stack_irq_end__
-#ifdef __ARM_EABI__
- bic sp, sp, #0x7
-#endif
-
- orr r1, r0, #0x11 /* FIQ mode */
- msr cpsr_cxsf, r1
- ldr sp, =__stack_fiq_end__
-#ifdef __ARM_EABI__
- bic sp, sp, #0x7
-#endif
-
- orr r1, r0, #0x13 /* Supervisor mode */
- msr cpsr_cxsf, r1
- ldr sp, =__stack_svc_end__
-#ifdef __ARM_EABI__
- bic sp, sp, #0x7
-#endif
-
-#ifdef SUPERVISOR_START
- /* Start application in supervisor mode */
- ldr r1, =__stack_end__ /* Setup user/system mode stack */
-#ifdef __ARM_EABI__
- bic r1, r1, #0x7
-#endif
- mov r2, sp
- stmfd r2!, {r1}
- ldmfd r2, {sp}^
-#else
- /* Start application in system mode */
- orr r1, r0, #0x1F /* System mode */
- msr cpsr_cxsf, r1
- ldr sp, =__stack_end__
-#ifdef __ARM_EABI__
- bic sp, sp, #0x7
-#endif
-#endif
-
-#ifdef INITIALIZE_STACKS
- mov r2, #0xCC
- ldr r0, =__stack_und_start__
- ldr r1, =__stack_und_end__
- bl memory_set
- ldr r0, =__stack_abt_start__
- ldr r1, =__stack_abt_end__
- bl memory_set
- ldr r0, =__stack_irq_start__
- ldr r1, =__stack_irq_end__
- bl memory_set
- ldr r0, =__stack_fiq_start__
- ldr r1, =__stack_fiq_end__
- bl memory_set
- ldr r0, =__stack_svc_start__
- ldr r1, =__stack_svc_end__
- bl memory_set
- ldr r0, =__stack_start__
- ldr r1, =__stack_end__
- bl memory_set
-#endif
-
- /* Copy initialised memory sections into RAM (if necessary). */
- ldr r0, =__data_load_start__
- ldr r1, =__data_start__
- ldr r2, =__data_end__
- bl memory_copy
- ldr r0, =__text_load_start__
- ldr r1, =__text_start__
- ldr r2, =__text_end__
- bl memory_copy
- ldr r0, =__fast_load_start__
- ldr r1, =__fast_start__
- ldr r2, =__fast_end__
- bl memory_copy
- ldr r0, =__ctors_load_start__
- ldr r1, =__ctors_start__
- ldr r2, =__ctors_end__
- bl memory_copy
- ldr r0, =__dtors_load_start__
- ldr r1, =__dtors_start__
- ldr r2, =__dtors_end__
- bl memory_copy
- ldr r0, =__rodata_load_start__
- ldr r1, =__rodata_start__
- ldr r2, =__rodata_end__
- bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
- ldr r0, =__data2_load_start__
- ldr r1, =__data2_start__
- ldr r2, =__data2_end__
- bl memory_copy
- ldr r0, =__text2_load_start__
- ldr r1, =__text2_start__
- ldr r2, =__text2_end__
- bl memory_copy
- ldr r0, =__rodata2_load_start__
- ldr r1, =__rodata2_start__
- ldr r2, =__rodata2_end__
- bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-
- /* Zero the bss. */
- ldr r0, =__bss_start__
- ldr r1, =__bss_end__
- mov r2, #0
- bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
- ldr r0, =__bss2_start__
- ldr r1, =__bss2_end__
- mov r2, #0
- bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-
- /* Initialise the heap */
- ldr r0, = __heap_start__
- ldr r1, = __heap_end__
- sub r1, r1, r0
- cmp r1, #8
- movge r2, #0
- strge r2, [r0], #+4
- strge r1, [r0]
-
- /* Call constructors */
- ldr r0, =__ctors_start__
- ldr r1, =__ctors_end__
-ctor_loop:
- cmp r0, r1
- beq ctor_end
- ldr r2, [r0], #+4
- stmfd sp!, {r0-r1}
- mov lr, pc
-#ifdef __ARM_ARCH_3__
- mov pc, r2
-#else
- bx r2
-#endif
- ldmfd sp!, {r0-r1}
- b ctor_loop
-ctor_end:
-
- .type start, function
-start:
- /* Jump to application entry point */
-#ifdef FULL_LIBRARY
- mov r0, #ARGSSPACE
- ldr r1, =args
- ldr r2, =debug_getargs
- mov lr, pc
-#ifdef __ARM_ARCH_3__
- mov pc, r2
-#else
- bx r2
-#endif
- ldr r1, =args
-#else
- mov r0, #0
- mov r1, #0
-#endif
- ldr r2, =APP_ENTRY_POINT
- mov lr, pc
-#ifdef __ARM_ARCH_3__
- mov pc, r2
-#else
- bx r2
-#endif
-
-exit:
-#ifdef FULL_LIBRARY
- mov r5, r0 // save the exit parameter/return result
-
- /* Call destructors */
- ldr r0, =__dtors_start__
- ldr r1, =__dtors_end__
-dtor_loop:
- cmp r0, r1
- beq dtor_end
- ldr r2, [r0], #+4
- stmfd sp!, {r0-r1}
- mov lr, pc
-#ifdef __ARM_ARCH_3__
- mov pc, r2
-#else
- bx r2
-#endif
- ldmfd sp!, {r0-r1}
- b dtor_loop
-dtor_end:
-
- /* Call atexit functions */
- ldr r2, =_execute_at_exit_fns
- mov lr, pc
-#ifdef __ARM_ARCH_3__
- mov pc, r2
-#else
- bx r2
-#endif
-
- /* Call debug_exit with return result/exit parameter */
- mov r0, r5
- ldr r2, =debug_exit
- mov lr, pc
-#ifdef __ARM_ARCH_3__
- mov pc, r2
-#else
- bx r2
-#endif
-
-#endif
-
- /* Returned from application entry point/debug_exit, loop forever. */
-exit_loop:
- b exit_loop
-
-memory_copy:
- cmp r0, r1
- moveq pc, lr
- subs r2, r2, r1
- moveq pc, lr
-
- /* if either pointer or length is not word aligned then byte copy */
- orr r3, r0, r1
- orr r3, r3, r2
- tst r3, #0x3
- bne 2f
- /* word copy */
-1:
- ldr r3, [r0], #+4
- str r3, [r1], #+4
- subs r2, r2, #4
- bne 1b
- mov pc, lr
- /* byte copy */
-2:
- ldrb r3, [r0], #+1
- strb r3, [r1], #+1
- subs r2, r2, #1
- bne 2b
- mov pc, lr
-
-memory_set:
- cmp r0, r1
- moveq pc, lr
- strb r2, [r0], #1
- b memory_set
-
-#ifdef FULL_LIBRARY
- .bss
-args:
- .space ARGSSPACE
-#endif
-
- /* Setup attibutes of stack and heap sections so they don't take up unnecessary room in the elf file */
- .section .stack, "wa", %nobits
- .section .stack_abt, "wa", %nobits
- .section .stack_irq, "wa", %nobits
- .section .stack_fiq, "wa", %nobits
- .section .stack_svc, "wa", %nobits
- .section .stack_und, "wa", %nobits
- .section .heap, "wa", %nobits
-
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/header.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/header.h
deleted file mode 100644
index 1584de97..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/header.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\header.h
-* \brief Generic header file.
-* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-#ifndef HEADER_H
-#define HEADER_H
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "../Boot/blt_conf.h" /* bootloader configuration */
-#include "lpc2294.h" /* CPU register definitions */
-#include "boot.h" /* bootloader interface driver */
-#include "irq.h" /* IRQ driver */
-#include "led.h" /* LED driver */
-#include "timer.h" /* Timer driver */
-
-
-#endif /* HEADER_H */
-/*********************************** end of header.h ***********************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/lpc2294_crossworks.hzp b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/lpc2294_crossworks.hzp
deleted file mode 100644
index 773e1a8a..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/lpc2294_crossworks.hzp
+++ /dev/null
@@ -1,40 +0,0 @@
-
-
-
-
-
-
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-
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-
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-
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-
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-
-
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/lpc2294_crossworks.hzs b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/lpc2294_crossworks.hzs
deleted file mode 100644
index b71bbe7b..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/lpc2294_crossworks.hzs
+++ /dev/null
@@ -1,60 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
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-
-
-
-
-
-
-
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-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/readme.txt b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/readme.txt
deleted file mode 100644
index a49767fb..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/readme.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Integrated Development Environment
-----------------------------------
-Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
-the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/
\ No newline at end of file
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/irq.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/irq.c
deleted file mode 100644
index e94ae90a..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/irq.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\irq.c
-* \brief IRQ driver source file.
-* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* Local data definitions
-****************************************************************************************/
-/** \brief Interrupt status before disabling. Used for global interrupt en/disable. */
-static unsigned long oldInterruptStatus;
-/** \brief Interrupt nesting counter. Used for global interrupt en/disable. */
-static unsigned char interruptNesting = 0;
-
-
-/************************************************************************************//**
-** \brief Obtains current value of CPSR CPU register. Derived from a sample by R O
-** Software that is Copyright 2004, R O SoftWare, and can be used for hobby
-** or commercial purposes.
-** \return CPSR value.
-**
-****************************************************************************************/
-static unsigned long IrqGetCPSR(void)
-{
- unsigned long retval;
- __asm__ volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ );
- return retval;
-} /*** end of IrqGetCPSR ***/
-
-
-/************************************************************************************//**
-** \brief Update value of CPSR CPU register. Derived from a sample by R O
-** Software that is Copyright 2004, R O SoftWare, and can be used for hobby
-** or commercial purposes.
-** \param val CPSR value.
-** \return none.
-**
-****************************************************************************************/
-static void IrqSetCPSR(unsigned long val)
-{
- __asm__ volatile (" msr cpsr, %0" : /* no outputs */ : "r" (val) );
-} /*** end of IrqSetCPSR ***/
-
-
-/************************************************************************************//**
-** \brief Enables the generation IRQ interrupts. Typically called once during
-** software startup after completion of the initialization.
-** \return none.
-**
-****************************************************************************************/
-void IrqInterruptEnable(void)
-{
- unsigned _cpsr;
-
- _cpsr = IrqGetCPSR();
- IrqSetCPSR(_cpsr & ~0x00000080);
-} /*** end of IrqInterruptEnable ***/
-
-
-/************************************************************************************//**
-** \brief Disables the generation IRQ interrupts and stores information on
-** whether or not the interrupts were already disabled before explicitly
-** disabling them with this function. Normally used as a pair together
-** with IrqInterruptRestore during a critical section.
-** \return none.
-**
-****************************************************************************************/
-void IrqInterruptDisable(void)
-{
- unsigned long _cpsr;
-
- if (interruptNesting == 0)
- {
- _cpsr = IrqGetCPSR();
- IrqSetCPSR(_cpsr | 0x00000080);
- oldInterruptStatus = _cpsr;
- }
- interruptNesting++;
-} /*** end of IrqInterruptDisable ***/
-
-
-/************************************************************************************//**
-** \brief Restore the generation IRQ interrupts to the setting it had prior to
-** calling IrqInterruptDisable. Normally used as a pair together with
-** IrqInterruptDisable during a critical section.
-** \return none.
-**
-****************************************************************************************/
-void IrqInterruptRestore(void)
-{
- unsigned _cpsr;
-
- interruptNesting--;
- if (interruptNesting == 0)
- {
- _cpsr = IrqGetCPSR();
- IrqSetCPSR((_cpsr & ~0x00000080) | (oldInterruptStatus & 0x00000080));
- }
-} /*** end of IrqInterruptRestore ***/
-
-
-/*********************************** end of irq.c **************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/irq.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/irq.h
deleted file mode 100644
index 86a0d69c..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/irq.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\irq.h
-* \brief IRQ driver header file.
-* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-#ifndef IRQ_H
-#define IRQ_H
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-void IrqInterruptEnable(void);
-void IrqInterruptDisable(void);
-void IrqInterruptRestore(void);
-
-
-#endif /* IRQ_H */
-/*********************************** end of irq.h **************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/led.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/led.c
deleted file mode 100644
index f02e3f77..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/led.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\led.c
-* \brief LED driver source file.
-* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* Macro definitions
-****************************************************************************************/
-/** \brief Toggle interval time in milliseconds. */
-#define LED_TOGGLE_MS (500)
-
-
-/************************************************************************************//**
-** \brief Initializes the LED.
-** \return none.
-**
-****************************************************************************************/
-void LedInit(void)
-{
- /* set io pins for led P1.23 */
- IO1DIR |= 0x00800000;
- /* turn the led off */
- IO1SET = 0x00800000;
-} /*** end of LedInit ***/
-
-
-/************************************************************************************//**
-** \brief Toggles the LED at a fixed time interval.
-** \return none.
-**
-****************************************************************************************/
-void LedToggle(void)
-{
- static unsigned char led_toggle_state = 0;
- static unsigned long timer_counter_last = 0;
- unsigned long timer_counter_now;
-
- /* check if toggle interval time passed */
- timer_counter_now = TimerGet();
- if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
- {
- /* not yet time to toggle */
- return;
- }
-
- /* determine toggle action */
- if (led_toggle_state == 0)
- {
- led_toggle_state = 1;
- /* turn the LED on */
- IO1CLR = 0x00800000;
- }
- else
- {
- led_toggle_state = 0;
- /* turn the LED off */
- IO1SET = 0x00800000;
- }
-
- /* store toggle time to determine next toggle interval */
- timer_counter_last = timer_counter_now;
-} /*** end of LedToggle ***/
-
-
-/*********************************** end of led.c **************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/led.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/led.h
deleted file mode 100644
index 70d183d1..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/led.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\led.h
-* \brief LED driver header file.
-* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-#ifndef LED_H
-#define LED_H
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-void LedInit(void);
-void LedToggle(void);
-
-
-#endif /* LED_H */
-/*********************************** end of led.h **************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/lpc2294.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/lpc2294.h
deleted file mode 100644
index 933080db..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/lpc2294.h
+++ /dev/null
@@ -1,404 +0,0 @@
-/****************************************************************************************
-| Description: NXP LPC2294 register definitions
-| File Name: lpc2294.h
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You have received a copy of the GNU General Public License along with OpenBLT. It
-| should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-|
-****************************************************************************************/
-#ifndef LPC2294_H
-#define LPC2294_H
-
-
-/****************************************************************************************
-* Macro definitions
-****************************************************************************************/
-/* EXTERNAL MEMORY CONTROLLER (EMC) */
-#define BCFG0 (*((volatile unsigned long *) 0xFFE00000)) /* lpc22xx only */
-#define BCFG1 (*((volatile unsigned long *) 0xFFE00004)) /* lpc22xx only */
-#define BCFG2 (*((volatile unsigned long *) 0xFFE00008)) /* lpc22xx only */
-#define BCFG3 (*((volatile unsigned long *) 0xFFE0000C)) /* lpc22xx only */
-
-/* External Interrupts */
-#define EXTINT (*((volatile unsigned char *) 0xE01FC140))
-#define EXTWAKE (*((volatile unsigned char *) 0xE01FC144))
-#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) /* no in lpc210x*/
-#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) /* no in lpc210x*/
-
-/* SMemory mapping control. */
-#define MEMMAP (*((volatile unsigned long *) 0xE01FC040))
-
-/* Phase Locked Loop (PLL) */
-#define PLLCON (*((volatile unsigned char *) 0xE01FC080))
-#define PLLCFG (*((volatile unsigned char *) 0xE01FC084))
-#define PLLSTAT (*((volatile unsigned short*) 0xE01FC088))
-#define PLLFEED (*((volatile unsigned char *) 0xE01FC08C))
-
-/* Power Control */
-#define PCON (*((volatile unsigned char *) 0xE01FC0C0))
-#define PCONP (*((volatile unsigned long *) 0xE01FC0C4))
-
-/* VPB Divider */
-#define VPBDIV (*((volatile unsigned char *) 0xE01FC100))
-
-/* Memory Accelerator Module (MAM) */
-#define MAMCR (*((volatile unsigned char *) 0xE01FC000))
-#define MAMTIM (*((volatile unsigned char *) 0xE01FC004))
-
-/* Vectored Interrupt Controller (VIC) */
-#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000))
-#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004))
-#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008))
-#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C))
-#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010))
-#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014))
-#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018))
-#define VICSoftIntClear (*((volatile unsigned long *) 0xFFFFF01C))
-#define VICProtection (*((volatile unsigned long *) 0xFFFFF020))
-#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030))
-#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034))
-#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100))
-#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104))
-#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108))
-#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C))
-#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110))
-#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114))
-#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118))
-#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C))
-#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120))
-#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124))
-#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128))
-#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C))
-#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130))
-#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134))
-#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138))
-#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C))
-#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200))
-#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204))
-#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208))
-#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C))
-#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210))
-#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214))
-#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218))
-#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C))
-#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220))
-#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224))
-#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228))
-#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C))
-#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230))
-#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234))
-#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238))
-#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C))
-
-/* Pin Connect Block */
-#define PINSEL0 (*((volatile unsigned long *) 0xE002C000))
-#define PINSEL1 (*((volatile unsigned long *) 0xE002C004))
-#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) /* no in lpc210x*/
-
-/* General Purpose Input/Output (GPIO) */
-#define IOPIN (*((volatile unsigned long *) 0xE0028000)) /* lpc210x only */
-#define IOSET (*((volatile unsigned long *) 0xE0028004)) /* lpc210x only */
-#define IODIR (*((volatile unsigned long *) 0xE0028008)) /* lpc210x only */
-#define IOCLR (*((volatile unsigned long *) 0xE002800C)) /* lpc210x only */
-
-#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) /* no in lpc210x*/
-#define IO0SET (*((volatile unsigned long *) 0xE0028004)) /* no in lpc210x*/
-#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) /* no in lpc210x*/
-#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) /* no in lpc210x*/
-
-#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) /* no in lpc210x*/
-#define IO1SET (*((volatile unsigned long *) 0xE0028014)) /* no in lpc210x*/
-#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) /* no in lpc210x*/
-#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) /* no in lpc210x*/
-
-#define IO2PIN (*((volatile unsigned long *) 0xE0028020)) /* lpc22xx only */
-#define IO2SET (*((volatile unsigned long *) 0xE0028024)) /* lpc22xx only */
-#define IO2DIR (*((volatile unsigned long *) 0xE0028028)) /* lpc22xx only */
-#define IO2CLR (*((volatile unsigned long *) 0xE002802C)) /* lpc22xx only */
-
-#define IO3PIN (*((volatile unsigned long *) 0xE0028030)) /* lpc22xx only */
-#define IO3SET (*((volatile unsigned long *) 0xE0028034)) /* lpc22xx only */
-#define IO3DIR (*((volatile unsigned long *) 0xE0028038)) /* lpc22xx only */
-#define IO3CLR (*((volatile unsigned long *) 0xE002803C)) /* lpc22xx only */
-
-/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
-#define U0RBR (*((volatile unsigned char *) 0xE000C000))
-#define U0THR (*((volatile unsigned char *) 0xE000C000))
-#define U0IER (*((volatile unsigned char *) 0xE000C004))
-#define U0IIR (*((volatile unsigned char *) 0xE000C008))
-#define U0FCR (*((volatile unsigned char *) 0xE000C008))
-#define U0LCR (*((volatile unsigned char *) 0xE000C00C))
-#define U0LSR (*((volatile unsigned char *) 0xE000C014))
-#define U0SCR (*((volatile unsigned char *) 0xE000C01C))
-#define U0DLL (*((volatile unsigned char *) 0xE000C000))
-#define U0DLM (*((volatile unsigned char *) 0xE000C004))
-
-/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
-#define U1RBR (*((volatile unsigned char *) 0xE0010000))
-#define U1THR (*((volatile unsigned char *) 0xE0010000))
-#define U1IER (*((volatile unsigned char *) 0xE0010004))
-#define U1IIR (*((volatile unsigned char *) 0xE0010008))
-#define U1FCR (*((volatile unsigned char *) 0xE0010008))
-#define U1LCR (*((volatile unsigned char *) 0xE001000C))
-#define U1MCR (*((volatile unsigned char *) 0xE0010010))
-#define U1LSR (*((volatile unsigned char *) 0xE0010014))
-#define U1MSR (*((volatile unsigned char *) 0xE0010018))
-#define U1SCR (*((volatile unsigned char *) 0xE001001C))
-#define U1DLL (*((volatile unsigned char *) 0xE0010000))
-#define U1DLM (*((volatile unsigned char *) 0xE0010004))
-
-/* I2C (8/16 bit data bus) */
-#define I2CONSET (*((volatile unsigned long *) 0xE001C000))
-#define I2STAT (*((volatile unsigned long *) 0xE001C004))
-#define I2DAT (*((volatile unsigned long *) 0xE001C008))
-#define I2ADR (*((volatile unsigned long *) 0xE001C00C))
-#define I2SCLH (*((volatile unsigned long *) 0xE001C010))
-#define I2SCLL (*((volatile unsigned long *) 0xE001C014))
-#define I2CONCLR (*((volatile unsigned long *) 0xE001C018))
-
-/* SPI (Serial Peripheral Interface) */
- /* only for lpc210x*/
-#define SPI_SPCR (*((volatile unsigned char *) 0xE0020000))
-#define SPI_SPSR (*((volatile unsigned char *) 0xE0020004))
-#define SPI_SPDR (*((volatile unsigned char *) 0xE0020008))
-#define SPI_SPCCR (*((volatile unsigned char *) 0xE002000C))
-#define SPI_SPINT (*((volatile unsigned char *) 0xE002001C))
-
-#define S0PCR (*((volatile unsigned char *) 0xE0020000)) /* no in lpc210x*/
-#define S0PSR (*((volatile unsigned char *) 0xE0020004)) /* no in lpc210x*/
-#define S0PDR (*((volatile unsigned char *) 0xE0020008)) /* no in lpc210x*/
-#define S0PCCR (*((volatile unsigned char *) 0xE002000C)) /* no in lpc210x*/
-#define S0PINT (*((volatile unsigned char *) 0xE002001C)) /* no in lpc210x*/
-
-#define S1PCR (*((volatile unsigned char *) 0xE0030000)) /* no in lpc210x*/
-#define S1PSR (*((volatile unsigned char *) 0xE0030004)) /* no in lpc210x*/
-#define S1PDR (*((volatile unsigned char *) 0xE0030008)) /* no in lpc210x*/
-#define S1PCCR (*((volatile unsigned char *) 0xE003000C)) /* no in lpc210x*/
-#define S1PINT (*((volatile unsigned char *) 0xE003001C)) /* no in lpc210x*/
-
-/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
-#define CAN1MOD (*((volatile unsigned long *) 0xE0044000)) /* All CAN Parts */
-#define CAN1CMR (*((volatile unsigned long *) 0xE0044004)) /* All CAN Parts */
-#define CAN1GSR (*((volatile unsigned long *) 0xE0044008)) /* All CAN Parts */
-#define CAN1ICR (*((volatile unsigned long *) 0xE004400C)) /* All CAN Parts */
-#define CAN1IER (*((volatile unsigned long *) 0xE0044010)) /* All CAN Parts */
-#define CAN1BTR (*((volatile unsigned long *) 0xE0044014)) /* All CAN Parts */
-#define CAN1EWL (*((volatile unsigned long *) 0xE0044018)) /* All CAN Parts */
-#define CAN1SR (*((volatile unsigned long *) 0xE004401C)) /* All CAN Parts */
-#define CAN1RFS (*((volatile unsigned long *) 0xE0044020)) /* All CAN Parts */
-#define CAN1RID (*((volatile unsigned long *) 0xE0044024)) /* All CAN Parts */
-#define CAN1RDA (*((volatile unsigned long *) 0xE0044028)) /* All CAN Parts */
-#define CAN1RDB (*((volatile unsigned long *) 0xE004402C)) /* All CAN Parts */
-#define CAN1TFI1 (*((volatile unsigned long *) 0xE0044030)) /* All CAN Parts */
-#define CAN1TID1 (*((volatile unsigned long *) 0xE0044034)) /* All CAN Parts */
-#define CAN1TDA1 (*((volatile unsigned long *) 0xE0044038)) /* All CAN Parts */
-#define CAN1TDB1 (*((volatile unsigned long *) 0xE004403C)) /* All CAN Parts */
-#define CAN1TFI2 (*((volatile unsigned long *) 0xE0044040)) /* All CAN Parts */
-#define CAN1TID2 (*((volatile unsigned long *) 0xE0044044)) /* All CAN Parts */
-#define CAN1TDA2 (*((volatile unsigned long *) 0xE0044048)) /* All CAN Parts */
-#define CAN1TDB2 (*((volatile unsigned long *) 0xE004404C)) /* All CAN Parts */
-#define CAN1TFI3 (*((volatile unsigned long *) 0xE0044050)) /* All CAN Parts */
-#define CAN1TID3 (*((volatile unsigned long *) 0xE0044054)) /* All CAN Parts */
-#define CAN1TDA3 (*((volatile unsigned long *) 0xE0044058)) /* All CAN Parts */
-#define CAN1TDB3 (*((volatile unsigned long *) 0xE004405C)) /* All CAN Parts */
-
-#define CAN2MOD (*((volatile unsigned long *) 0xE0048000)) /* All CAN Parts */
-#define CAN2CMR (*((volatile unsigned long *) 0xE0048004)) /* All CAN Parts */
-#define CAN2GSR (*((volatile unsigned long *) 0xE0048008)) /* All CAN Parts */
-#define CAN2ICR (*((volatile unsigned long *) 0xE004800C)) /* All CAN Parts */
-#define CAN2IER (*((volatile unsigned long *) 0xE0048010)) /* All CAN Parts */
-#define CAN2BTR (*((volatile unsigned long *) 0xE0048014)) /* All CAN Parts */
-#define CAN2EWL (*((volatile unsigned long *) 0xE0048018)) /* All CAN Parts */
-#define CAN2SR (*((volatile unsigned long *) 0xE004801C)) /* All CAN Parts */
-#define CAN2RFS (*((volatile unsigned long *) 0xE0048020)) /* All CAN Parts */
-#define CAN2RID (*((volatile unsigned long *) 0xE0048024)) /* All CAN Parts */
-#define CAN2RDA (*((volatile unsigned long *) 0xE0048028)) /* All CAN Parts */
-#define CAN2RDB (*((volatile unsigned long *) 0xE004802C)) /* All CAN Parts */
-#define CAN2TFI1 (*((volatile unsigned long *) 0xE0048030)) /* All CAN Parts */
-#define CAN2TID1 (*((volatile unsigned long *) 0xE0048034)) /* All CAN Parts */
-#define CAN2TDA1 (*((volatile unsigned long *) 0xE0048038)) /* All CAN Parts */
-#define CAN2TDB1 (*((volatile unsigned long *) 0xE004803C)) /* All CAN Parts */
-#define CAN2TFI2 (*((volatile unsigned long *) 0xE0048040)) /* All CAN Parts */
-#define CAN2TID2 (*((volatile unsigned long *) 0xE0048044)) /* All CAN Parts */
-#define CAN2TDA2 (*((volatile unsigned long *) 0xE0048048)) /* All CAN Parts */
-#define CAN2TDB2 (*((volatile unsigned long *) 0xE004804C)) /* All CAN Parts */
-#define CAN2TFI3 (*((volatile unsigned long *) 0xE0048050)) /* All CAN Parts */
-#define CAN2TID3 (*((volatile unsigned long *) 0xE0048054)) /* All CAN Parts */
-#define CAN2TDA3 (*((volatile unsigned long *) 0xE0048058)) /* All CAN Parts */
-#define CAN2TDB3 (*((volatile unsigned long *) 0xE004805C)) /* All CAN Parts */
-
-#define CAN3MOD (*((volatile unsigned long *) 0xE004C000)) /* lpc2194\lpc2294 only */
-#define CAN3CMR (*((volatile unsigned long *) 0xE004C004)) /* lpc2194\lpc2294 only */
-#define CAN3GSR (*((volatile unsigned long *) 0xE004C008)) /* lpc2194\lpc2294 only */
-#define CAN3ICR (*((volatile unsigned long *) 0xE004C00C)) /* lpc2194\lpc2294 only */
-#define CAN3IER (*((volatile unsigned long *) 0xE004C010)) /* lpc2194\lpc2294 only */
-#define CAN3BTR (*((volatile unsigned long *) 0xE004C014)) /* lpc2194\lpc2294 only */
-#define CAN3EWL (*((volatile unsigned long *) 0xE004C018)) /* lpc2194\lpc2294 only */
-#define CAN3SR (*((volatile unsigned long *) 0xE004C01C)) /* lpc2194\lpc2294 only */
-#define CAN3RFS (*((volatile unsigned long *) 0xE004C020)) /* lpc2194\lpc2294 only */
-#define CAN3RID (*((volatile unsigned long *) 0xE004C024)) /* lpc2194\lpc2294 only */
-#define CAN3RDA (*((volatile unsigned long *) 0xE004C028)) /* lpc2194\lpc2294 only */
-#define CAN3RDB (*((volatile unsigned long *) 0xE004C02C)) /* lpc2194\lpc2294 only */
-#define CAN3TFI1 (*((volatile unsigned long *) 0xE004C030)) /* lpc2194\lpc2294 only */
-#define CAN3TID1 (*((volatile unsigned long *) 0xE004C034)) /* lpc2194\lpc2294 only */
-#define CAN3TDA1 (*((volatile unsigned long *) 0xE004C038)) /* lpc2194\lpc2294 only */
-#define CAN3TDB1 (*((volatile unsigned long *) 0xE004C03C)) /* lpc2194\lpc2294 only */
-#define CAN3TFI2 (*((volatile unsigned long *) 0xE004C040)) /* lpc2194\lpc2294 only */
-#define CAN3TID2 (*((volatile unsigned long *) 0xE004C044)) /* lpc2194\lpc2294 only */
-#define CAN3TDA2 (*((volatile unsigned long *) 0xE004C048)) /* lpc2194\lpc2294 only */
-#define CAN3TDB2 (*((volatile unsigned long *) 0xE004C04C)) /* lpc2194\lpc2294 only */
-#define CAN3TFI3 (*((volatile unsigned long *) 0xE004C050)) /* lpc2194\lpc2294 only */
-#define CAN3TID3 (*((volatile unsigned long *) 0xE004C054)) /* lpc2194\lpc2294 only */
-#define CAN3TDA3 (*((volatile unsigned long *) 0xE004C058)) /* lpc2194\lpc2294 only */
-#define CAN3TDB3 (*((volatile unsigned long *) 0xE004C05C)) /* lpc2194\lpc2294 only */
-
-#define CAN4MOD (*((volatile unsigned long *) 0xE0050000)) /* lpc2194\lpc2294 only */
-#define CAN4CMR (*((volatile unsigned long *) 0xE0050004)) /* lpc2194\lpc2294 only */
-#define CAN4GSR (*((volatile unsigned long *) 0xE0050008)) /* lpc2194\lpc2294 only */
-#define CAN4ICR (*((volatile unsigned long *) 0xE005000C)) /* lpc2194\lpc2294 only */
-#define CAN4IER (*((volatile unsigned long *) 0xE0050010)) /* lpc2194\lpc2294 only */
-#define CAN4BTR (*((volatile unsigned long *) 0xE0050014)) /* lpc2194\lpc2294 only */
-#define CAN4EWL (*((volatile unsigned long *) 0xE0050018)) /* lpc2194\lpc2294 only */
-#define CAN4SR (*((volatile unsigned long *) 0xE005001C)) /* lpc2194\lpc2294 only */
-#define CAN4RFS (*((volatile unsigned long *) 0xE0050020)) /* lpc2194\lpc2294 only */
-#define CAN4RID (*((volatile unsigned long *) 0xE0050024)) /* lpc2194\lpc2294 only */
-#define CAN4RDA (*((volatile unsigned long *) 0xE0050028)) /* lpc2194\lpc2294 only */
-#define CAN4RDB (*((volatile unsigned long *) 0xE005002C)) /* lpc2194\lpc2294 only */
-#define CAN4TFI1 (*((volatile unsigned long *) 0xE0050030)) /* lpc2194\lpc2294 only */
-#define CAN4TID1 (*((volatile unsigned long *) 0xE0050034)) /* lpc2194\lpc2294 only */
-#define CAN4TDA1 (*((volatile unsigned long *) 0xE0050038)) /* lpc2194\lpc2294 only */
-#define CAN4TDB1 (*((volatile unsigned long *) 0xE005003C)) /* lpc2194\lpc2294 only */
-#define CAN4TFI2 (*((volatile unsigned long *) 0xE0050040)) /* lpc2194\lpc2294 only */
-#define CAN4TID2 (*((volatile unsigned long *) 0xE0050044)) /* lpc2194\lpc2294 only */
-#define CAN4TDA2 (*((volatile unsigned long *) 0xE0050048)) /* lpc2194\lpc2294 only */
-#define CAN4TDB2 (*((volatile unsigned long *) 0xE005004C)) /* lpc2194\lpc2294 only */
-#define CAN4TFI3 (*((volatile unsigned long *) 0xE0050050)) /* lpc2194\lpc2294 only */
-#define CAN4TID3 (*((volatile unsigned long *) 0xE0050054)) /* lpc2194\lpc2294 only */
-#define CAN4TDA3 (*((volatile unsigned long *) 0xE0050058)) /* lpc2194\lpc2294 only */
-#define CAN4TDB3 (*((volatile unsigned long *) 0xE005005C)) /* lpc2194\lpc2294 only */
-
-
-#define CANTxSR (*((volatile unsigned long *) 0xE0040000)) /* ALL CAN Parts */
-#define CANRxSR (*((volatile unsigned long *) 0xE0040004)) /* ALL CAN Parts */
-#define CANMSR (*((volatile unsigned long *) 0xE0040008)) /* ALL CAN Parts */
-
-#define CANAFMR (*((volatile unsigned char *) 0xE003C000)) /* ALL CAN Parts */
-#define CANSFF_sa (*((volatile unsigned short*) 0xE003C004)) /* ALL CAN Parts */
-#define CANSFF_GRP_sa (*((volatile unsigned short*) 0xE003C008)) /* ALL CAN Parts */
-#define CANEFF_sa (*((volatile unsigned short*) 0xE003C00C)) /* ALL CAN Parts */
-#define CANEFF_GRP_sa (*((volatile unsigned short*) 0xE003C010)) /* ALL CAN Parts */
-#define CANENDofTable (*((volatile unsigned short*) 0xE003C014)) /* ALL CAN Parts */
-#define CANLUTerrAd (*((volatile unsigned short*) 0xE003C018)) /* ALL CAN Parts */
-#define CANLUTerr (*((volatile unsigned char *) 0xE003C01C)) /* ALL CAN Parts */
-
-
-/* Timer 0 */
-#define T0IR (*((volatile unsigned long *) 0xE0004000))
-#define T0TCR (*((volatile unsigned long *) 0xE0004004))
-#define T0TC (*((volatile unsigned long *) 0xE0004008))
-#define T0PR (*((volatile unsigned long *) 0xE000400C))
-#define T0PC (*((volatile unsigned long *) 0xE0004010))
-#define T0MCR (*((volatile unsigned long *) 0xE0004014))
-#define T0MR0 (*((volatile unsigned long *) 0xE0004018))
-#define T0MR1 (*((volatile unsigned long *) 0xE000401C))
-#define T0MR2 (*((volatile unsigned long *) 0xE0004020))
-#define T0MR3 (*((volatile unsigned long *) 0xE0004024))
-#define T0CCR (*((volatile unsigned long *) 0xE0004028))
-#define T0CR0 (*((volatile unsigned long *) 0xE000402C))
-#define T0CR1 (*((volatile unsigned long *) 0xE0004030))
-#define T0CR2 (*((volatile unsigned long *) 0xE0004034))
-#define T0CR3 (*((volatile unsigned long *) 0xE0004038))
-#define T0EMR (*((volatile unsigned long *) 0xE000403C))
-
-/* Timer 1 */
-#define T1IR (*((volatile unsigned long *) 0xE0008000))
-#define T1TCR (*((volatile unsigned long *) 0xE0008004))
-#define T1TC (*((volatile unsigned long *) 0xE0008008))
-#define T1PR (*((volatile unsigned long *) 0xE000800C))
-#define T1PC (*((volatile unsigned long *) 0xE0008010))
-#define T1MCR (*((volatile unsigned long *) 0xE0008014))
-#define T1MR0 (*((volatile unsigned long *) 0xE0008018))
-#define T1MR1 (*((volatile unsigned long *) 0xE000801C))
-#define T1MR2 (*((volatile unsigned long *) 0xE0008020))
-#define T1MR3 (*((volatile unsigned long *) 0xE0008024))
-#define T1CCR (*((volatile unsigned long *) 0xE0008028))
-#define T1CR0 (*((volatile unsigned long *) 0xE000802C))
-#define T1CR1 (*((volatile unsigned long *) 0xE0008030))
-#define T1CR2 (*((volatile unsigned long *) 0xE0008034))
-#define T1CR3 (*((volatile unsigned long *) 0xE0008038))
-#define T1EMR (*((volatile unsigned long *) 0xE000803C))
-
-/* Pulse Width Modulator (PWM) */
-#define PWMIR (*((volatile unsigned long *) 0xE0014000))
-#define PWMTCR (*((volatile unsigned long *) 0xE0014004))
-#define PWMTC (*((volatile unsigned long *) 0xE0014008))
-#define PWMPR (*((volatile unsigned long *) 0xE001400C))
-#define PWMPC (*((volatile unsigned long *) 0xE0014010))
-#define PWMMCR (*((volatile unsigned long *) 0xE0014014))
-#define PWMMR0 (*((volatile unsigned long *) 0xE0014018))
-#define PWMMR1 (*((volatile unsigned long *) 0xE001401C))
-#define PWMMR2 (*((volatile unsigned long *) 0xE0014020))
-#define PWMMR3 (*((volatile unsigned long *) 0xE0014024))
-#define PWMMR4 (*((volatile unsigned long *) 0xE0014040))
-#define PWMMR5 (*((volatile unsigned long *) 0xE0014044))
-#define PWMMR6 (*((volatile unsigned long *) 0xE0014048))
-#define PWMPCR (*((volatile unsigned long *) 0xE001404C))
-#define PWMLER (*((volatile unsigned long *) 0xE0014050))
-
-/* A/D CONVERTER */
-#define ADCR (*((volatile unsigned long *) 0xE0034000)) /* no in lpc210x*/
-#define ADDR (*((volatile unsigned long *) 0xE0034004)) /* no in lpc210x*/
-
-/* Real Time Clock */
-#define ILR (*((volatile unsigned char *) 0xE0024000))
-#define CTC (*((volatile unsigned short*) 0xE0024004))
-#define CCR (*((volatile unsigned char *) 0xE0024008))
-#define CIIR (*((volatile unsigned char *) 0xE002400C))
-#define AMR (*((volatile unsigned char *) 0xE0024010))
-#define CTIME0 (*((volatile unsigned long *) 0xE0024014))
-#define CTIME1 (*((volatile unsigned long *) 0xE0024018))
-#define CTIME2 (*((volatile unsigned long *) 0xE002401C))
-#define SEC (*((volatile unsigned char *) 0xE0024020))
-#define MIN (*((volatile unsigned char *) 0xE0024024))
-#define HOUR (*((volatile unsigned char *) 0xE0024028))
-#define DOM (*((volatile unsigned char *) 0xE002402C))
-#define DOW (*((volatile unsigned char *) 0xE0024030))
-#define DOY (*((volatile unsigned short*) 0xE0024034))
-#define MONTH (*((volatile unsigned char *) 0xE0024038))
-#define YEAR (*((volatile unsigned short*) 0xE002403C))
-#define ALSEC (*((volatile unsigned char *) 0xE0024060))
-#define ALMIN (*((volatile unsigned char *) 0xE0024064))
-#define ALHOUR (*((volatile unsigned char *) 0xE0024068))
-#define ALDOM (*((volatile unsigned char *) 0xE002406C))
-#define ALDOW (*((volatile unsigned char *) 0xE0024070))
-#define ALDOY (*((volatile unsigned short*) 0xE0024074))
-#define ALMON (*((volatile unsigned char *) 0xE0024078))
-#define ALYEAR (*((volatile unsigned short*) 0xE002407C))
-#define PREINT (*((volatile unsigned short*) 0xE0024080))
-#define PREFRAC (*((volatile unsigned short*) 0xE0024084))
-
-/* Watchdog */
-#define WDMOD (*((volatile unsigned char *) 0xE0000000))
-#define WDTC (*((volatile unsigned long *) 0xE0000004))
-#define WDFEED (*((volatile unsigned char *) 0xE0000008))
-#define WDTV (*((volatile unsigned long *) 0xE000000C))
-
-#endif /* LPC2294_H */
-/*********************************** end of lpc2294.h **********************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/main.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/main.c
deleted file mode 100644
index aeceabc1..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/main.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\main.c
-* \brief Demo program application source file.
-* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-static void Init(void);
-
-
-/****************************************************************************************
-* Constant data declarations
-****************************************************************************************/
-#if (BOOT_NVM_HOOKS_ENABLE > 0)
-/** \brief Array with test data to program in the external flash.
- * \details ROM data allocated to the external flash on the Olimex LPC-L2294 board to
- * test the programming of data in external flash. To test programming with
- * the additional external flash driver, build the bootloader and this program
- * with configurable BOOT_NVM_HOOKS_ENABLE set to 1 in blt_conf.h
- */
-__attribute__((section (".rodata2"))) const unsigned long ExtFlashTestData[] =
-{
- 0x00000000, 0x11111111, 0x22222222, 0x33333333,
- 0x44444444, 0x55555555, 0x66666666, 0x77777777,
- 0x88888888, 0x99999999, 0xAAAAAAAA, 0xBBBBBBBB,
- 0xCCCCCCCC, 0xDDDDDDDD, 0xEEEEEEEE, 0xFFFFFFFF
-};
-#endif
-
-
-/************************************************************************************//**
-** \brief This is the entry point for the bootloader application and is called
-** by the reset interrupt vector after the C-startup routines executed.
-** \return Program return code.
-**
-****************************************************************************************/
-int main(void)
-{
- /* initialize the microcontroller */
- Init();
-
- /* initialize the bootloader interface */
- BootComInit();
-
- /* start the infinite program loop */
- while (1)
- {
- /* toggle LED with a fixed frequency */
- LedToggle();
-
- /* check for bootloader activation request */
- BootComCheckActivationRequest();
- }
-
- /* program should never get here */
- return 0;
-} /*** end of main ***/
-
-
-/************************************************************************************//**
-** \brief Initializes the microcontroller. The Fpll is set to 60MHz and Fvpb is
-** configured equal to Fpll. The GPIO pin of the status LED is configured
-** as digital output.
-** \return none.
-**
-****************************************************************************************/
-static void Init(void)
-{
- unsigned char m_sel; /* pll multiplier register value */
- unsigned char pll_dividers[] = { 1, 2, 4, 8 }; /* possible pll dividers */
- unsigned char p_sel_cnt; /* loop counter to find p_sel */
- unsigned long f_cco; /* current controller oscillator */
-
- /* calculate MSEL: M = round(Fcclk / Fosc) */
- m_sel = (BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
- BOOT_CPU_XTAL_SPEED_KHZ;
- /* value for the PLLCFG register is -1 */
- m_sel--;
-
- /* find PSEL value so that Fcco(= Fcclk * 2 * P) is in the 156000..320000 kHz range. */
- for (p_sel_cnt=0; p_sel_cnt= 156000) && (f_cco <= 320000) )
- {
- /* found a valid pll divider value */
- break;
- }
- }
-
- /* set multiplier and divider values */
- PLLCFG = (p_sel_cnt << 5) | m_sel;
- PLLFEED = 0xAA;
- PLLFEED = 0x55;
- /* enable the PLL */
- PLLCON = 0x1;
- PLLFEED = 0xAA;
- PLLFEED = 0x55;
- /* wait for the PLL to lock to set frequency */
- while(!(PLLSTAT & 0x400)) { ; }
- /* connect the PLL as the clock source */
- PLLCON = 0x3;
- PLLFEED = 0xAA;
- PLLFEED = 0x55;
- /* enable MAM and set number of clocks used for Flash memory fetch. Recommended:
- * Fcclk >= 60 MHz: 4 clock cycles
- * Fcclk >= 40 MHz: 3 clock cycles
- * Fcclk >= 20 MHz: 2 clock cycles
- * Fcclk < 20 MHz: 1 clock cycle
- */
- MAMCR = 0x0;
-#if (BOOT_CPU_SYSTEM_SPEED_KHZ >= 60000)
- MAMTIM = 4;
-#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 40000)
- MAMTIM = 3;
-#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 20000)
- MAMTIM = 2;
-#else
- MAMTIM = 1;
-#endif
- MAMCR = 0x2;
- /* setting peripheral Clock (pclk) to System Clock (cclk) */
- VPBDIV = 0x1;
- /* init the led driver */
- LedInit();
- /* init the timer driver */
- TimerInit();
- /* enable IRQ's */
- IrqInterruptEnable();
-} /*** end of Init ***/
-
-
-/*********************************** end of main.c *************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/memory.x b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/memory.x
deleted file mode 100644
index 70cbf672..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/memory.x
+++ /dev/null
@@ -1,356 +0,0 @@
-MEMORY
-{
- UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0
- AHB_Peripherals (wx) : ORIGIN = 0xffe00000, LENGTH = 0x00200000
- VPB_Peripherals (wx) : ORIGIN = 0xe0000000, LENGTH = 0x00200000
- BANK3 (wx) : ORIGIN = 0x83000000, LENGTH = 0x01000000
- BANK2 (wx) : ORIGIN = 0x82000000, LENGTH = 0x01000000
- External_SRAM (wx) : ORIGIN = 0x81000000, LENGTH = 0x00100000
- External_FLASH (rx) : ORIGIN = 0x80000000, LENGTH = 0x00200000
- SRAM (wx) : ORIGIN = 0x40000200, LENGTH = 0x00003CE0
- FLASH (rx) : ORIGIN = 0x00002000, LENGTH = 0x0003E000
-}
-
-
-SECTIONS
-{
- __AHB_Peripherals_segment_start__ = 0xffe00000;
- __AHB_Peripherals_segment_end__ = 0x00000000;
- __VPB_Peripherals_segment_start__ = 0xe0000000;
- __VPB_Peripherals_segment_end__ = 0xe0200000;
- __BANK3_segment_start__ = 0x83000000;
- __BANK3_segment_end__ = 0x84000000;
- __BANK2_segment_start__ = 0x82000000;
- __BANK2_segment_end__ = 0x83000000;
- __External_SRAM_segment_start__ = 0x81000000;
- __External_SRAM_segment_end__ = 0x81100000;
- __External_FLASH_segment_start__ = 0x80000000;
- __External_FLASH_segment_end__ = 0x80200000;
- __SRAM_segment_start__ = 0x40002000;
- __SRAM_segment_end__ = 0x40003EE0;
- __FLASH_segment_start__ = 0x00002000;
- __FLASH_segment_end__ = 0x00040000;
-
- __STACKSIZE__ = 1024;
- __STACKSIZE_IRQ__ = 256;
- __STACKSIZE_FIQ__ = 256;
- __STACKSIZE_SVC__ = 256;
- __STACKSIZE_ABT__ = 256;
- __STACKSIZE_UND__ = 256;
- __HEAPSIZE__ = 1024;
-
- __text2_load_start__ = ALIGN(__External_FLASH_segment_start__ , 4);
- .text2 ALIGN(__External_FLASH_segment_start__ , 4) : AT(ALIGN(__External_FLASH_segment_start__ , 4))
- {
- __text2_start__ = .;
- *(.text2 .text2.*)
- }
- __text2_end__ = __text2_start__ + SIZEOF(.text2);
-
- __text2_load_end__ = __text2_end__;
-
- . = ASSERT(__text2_end__ >= __External_FLASH_segment_start__ && __text2_end__ <= (__External_FLASH_segment_start__ + 0x00400000) , "error: .text2 is too large to fit in External_FLASH memory segment");
-
- __rodata2_load_start__ = ALIGN(__text2_end__ , 4);
- .rodata2 ALIGN(__text2_end__ , 4) : AT(ALIGN(__text2_end__ , 4))
- {
- __rodata2_start__ = .;
- *(.rodata2 .rodata2.*)
- }
- __rodata2_end__ = __rodata2_start__ + SIZEOF(.rodata2);
-
- __rodata2_load_end__ = __rodata2_end__;
-
- . = ASSERT(__rodata2_end__ >= __External_FLASH_segment_start__ && __rodata2_end__ <= (__External_FLASH_segment_start__ + 0x00400000) , "error: .rodata2 is too large to fit in External_FLASH memory segment");
-
- __data2_load_start__ = ALIGN(__rodata2_end__ , 4);
- .data2 ALIGN(__External_SRAM_segment_start__ , 4) : AT(ALIGN(__rodata2_end__ , 4))
- {
- __data2_start__ = .;
- *(.data2 .data2.*)
- }
- __data2_end__ = __data2_start__ + SIZEOF(.data2);
-
- __data2_load_end__ = __data2_load_start__ + SIZEOF(.data2);
-
- __External_FLASH_segment_used_end__ = ALIGN(__rodata2_end__ , 4) + SIZEOF(.data2);
-
- . = ASSERT((__data2_load_start__ + SIZEOF(.data2)) >= __External_FLASH_segment_start__ && (__data2_load_start__ + SIZEOF(.data2)) <= (__External_FLASH_segment_start__ + 0x00400000) , "error: .data2 is too large to fit in External_FLASH memory segment");
-
- .data2_run ALIGN(__External_SRAM_segment_start__ , 4) (NOLOAD) :
- {
- __data2_run_start__ = .;
- . = MAX(__data2_run_start__ + SIZEOF(.data2), .);
- }
- __data2_run_end__ = __data2_run_start__ + SIZEOF(.data2_run);
-
- __data2_run_load_end__ = __data2_run_end__;
-
- . = ASSERT(__data2_run_end__ >= __External_SRAM_segment_start__ && __data2_run_end__ <= (__External_SRAM_segment_start__ + 0x00100000) , "error: .data2_run is too large to fit in External_SRAM memory segment");
-
- __bss2_load_start__ = ALIGN(__data2_run_end__ , 4);
- .bss2 ALIGN(__data2_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data2_run_end__ , 4))
- {
- __bss2_start__ = .;
- *(.bss2 .bss2.*)
- }
- __bss2_end__ = __bss2_start__ + SIZEOF(.bss2);
-
- __bss2_load_end__ = __bss2_end__;
-
- __External_SRAM_segment_used_end__ = ALIGN(__data2_run_end__ , 4) + SIZEOF(.bss2);
-
- . = ASSERT(__bss2_end__ >= __External_SRAM_segment_start__ && __bss2_end__ <= (__External_SRAM_segment_start__ + 0x00100000) , "error: .bss2 is too large to fit in External_SRAM memory segment");
-
- __vectors_ram_load_start__ = __SRAM_segment_start__;
- .vectors_ram __SRAM_segment_start__ (NOLOAD) : AT(__SRAM_segment_start__)
- {
- __vectors_ram_start__ = .;
- *(.vectors_ram .vectors_ram.*)
- . = MAX(__vectors_ram_start__ + 0x0000003C , .);
- }
- __vectors_ram_end__ = __vectors_ram_start__ + SIZEOF(.vectors_ram);
-
- __vectors_ram_load_end__ = __vectors_ram_end__;
-
- . = ASSERT(__vectors_ram_end__ >= __SRAM_segment_start__ && __vectors_ram_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .vectors_ram is too large to fit in SRAM memory segment");
-
- __vectors_load_start__ = __FLASH_segment_start__;
- .vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__)
- {
- __vectors_start__ = .;
- *(.vectors .vectors.*)
- }
- __vectors_end__ = __vectors_start__ + SIZEOF(.vectors);
-
- __vectors_load_end__ = __vectors_end__;
-
- . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .vectors is too large to fit in FLASH memory segment");
-
- __init_load_start__ = ALIGN(__vectors_end__ , 4);
- .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4))
- {
- __init_start__ = .;
- *(.init .init.*)
- }
- __init_end__ = __init_start__ + SIZEOF(.init);
-
- __init_load_end__ = __init_end__;
-
- . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .init is too large to fit in FLASH memory segment");
-
- __text_load_start__ = ALIGN(__init_end__ , 4);
- .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4))
- {
- __text_start__ = .;
- *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table)
- }
- __text_end__ = __text_start__ + SIZEOF(.text);
-
- __text_load_end__ = __text_end__;
-
- . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .text is too large to fit in FLASH memory segment");
-
- __dtors_load_start__ = ALIGN(__text_end__ , 4);
- .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4))
- {
- __dtors_start__ = .;
- KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors))
- }
- __dtors_end__ = __dtors_start__ + SIZEOF(.dtors);
-
- __dtors_load_end__ = __dtors_end__;
-
- . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .dtors is too large to fit in FLASH memory segment");
-
- __ctors_load_start__ = ALIGN(__dtors_end__ , 4);
- .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
- {
- __ctors_start__ = .;
- KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors))
- }
- __ctors_end__ = __ctors_start__ + SIZEOF(.ctors);
-
- __ctors_load_end__ = __ctors_end__;
-
- . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .ctors is too large to fit in FLASH memory segment");
-
- __rodata_load_start__ = ALIGN(__ctors_end__ , 4);
- .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
- {
- __rodata_start__ = .;
- *(.rodata .rodata.* .gnu.linkonce.r.*)
- }
- __rodata_end__ = __rodata_start__ + SIZEOF(.rodata);
-
- __rodata_load_end__ = __rodata_end__;
-
- . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .rodata is too large to fit in FLASH memory segment");
-
- __data_load_start__ = ALIGN(__rodata_end__ , 4);
- .data ALIGN(__vectors_ram_end__ , 4) : AT(ALIGN(__rodata_end__ , 4))
- {
- __data_start__ = .;
- *(.data .data.* .gnu.linkonce.d.*)
- }
- __data_end__ = __data_start__ + SIZEOF(.data);
-
- __data_load_end__ = __data_load_start__ + SIZEOF(.data);
-
- . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .data is too large to fit in FLASH memory segment");
-
- .data_run ALIGN(__vectors_ram_end__ , 4) (NOLOAD) :
- {
- __data_run_start__ = .;
- . = MAX(__data_run_start__ + SIZEOF(.data), .);
- }
- __data_run_end__ = __data_run_start__ + SIZEOF(.data_run);
-
- __data_run_load_end__ = __data_run_end__;
-
- . = ASSERT(__data_run_end__ >= __SRAM_segment_start__ && __data_run_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .data_run is too large to fit in SRAM memory segment");
-
- __bss_load_start__ = ALIGN(__data_run_end__ , 4);
- .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
- {
- __bss_start__ = .;
- *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
- }
- __bss_end__ = __bss_start__ + SIZEOF(.bss);
-
- __bss_load_end__ = __bss_end__;
-
- . = ASSERT(__bss_end__ >= __SRAM_segment_start__ && __bss_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .bss is too large to fit in SRAM memory segment");
-
- __non_init_load_start__ = ALIGN(__bss_end__ , 4);
- .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
- {
- __non_init_start__ = .;
- *(.non_init .non_init.*)
- }
- __non_init_end__ = __non_init_start__ + SIZEOF(.non_init);
-
- __non_init_load_end__ = __non_init_end__;
-
- . = ASSERT(__non_init_end__ >= __SRAM_segment_start__ && __non_init_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .non_init is too large to fit in SRAM memory segment");
-
- __heap_load_start__ = ALIGN(__non_init_end__ , 4);
- .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
- {
- __heap_start__ = .;
- *(.heap .heap.*)
- . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4);
- }
- __heap_end__ = __heap_start__ + SIZEOF(.heap);
-
- __heap_load_end__ = __heap_end__;
-
- . = ASSERT(__heap_end__ >= __SRAM_segment_start__ && __heap_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .heap is too large to fit in SRAM memory segment");
-
- __stack_load_start__ = ALIGN(__heap_end__ , 4);
- .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4))
- {
- __stack_start__ = .;
- *(.stack .stack.*)
- . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4);
- }
- __stack_end__ = __stack_start__ + SIZEOF(.stack);
-
- __stack_load_end__ = __stack_end__;
-
- . = ASSERT(__stack_end__ >= __SRAM_segment_start__ && __stack_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack is too large to fit in SRAM memory segment");
-
- __stack_irq_load_start__ = ALIGN(__stack_end__ , 4);
- .stack_irq ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4))
- {
- __stack_irq_start__ = .;
- *(.stack_irq .stack_irq.*)
- . = ALIGN(MAX(__stack_irq_start__ + __STACKSIZE_IRQ__ , .), 4);
- }
- __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq);
-
- __stack_irq_load_end__ = __stack_irq_end__;
-
- . = ASSERT(__stack_irq_end__ >= __SRAM_segment_start__ && __stack_irq_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_irq is too large to fit in SRAM memory segment");
-
- __stack_fiq_load_start__ = ALIGN(__stack_irq_end__ , 4);
- .stack_fiq ALIGN(__stack_irq_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_irq_end__ , 4))
- {
- __stack_fiq_start__ = .;
- *(.stack_fiq .stack_fiq.*)
- . = ALIGN(MAX(__stack_fiq_start__ + __STACKSIZE_FIQ__ , .), 4);
- }
- __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq);
-
- __stack_fiq_load_end__ = __stack_fiq_end__;
-
- . = ASSERT(__stack_fiq_end__ >= __SRAM_segment_start__ && __stack_fiq_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_fiq is too large to fit in SRAM memory segment");
-
- __stack_svc_load_start__ = ALIGN(__stack_fiq_end__ , 4);
- .stack_svc ALIGN(__stack_fiq_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_fiq_end__ , 4))
- {
- __stack_svc_start__ = .;
- *(.stack_svc .stack_svc.*)
- . = ALIGN(MAX(__stack_svc_start__ + __STACKSIZE_SVC__ , .), 4);
- }
- __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc);
-
- __stack_svc_load_end__ = __stack_svc_end__;
-
- . = ASSERT(__stack_svc_end__ >= __SRAM_segment_start__ && __stack_svc_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_svc is too large to fit in SRAM memory segment");
-
- __stack_abt_load_start__ = ALIGN(__stack_svc_end__ , 4);
- .stack_abt ALIGN(__stack_svc_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_svc_end__ , 4))
- {
- __stack_abt_start__ = .;
- *(.stack_abt .stack_abt.*)
- . = ALIGN(MAX(__stack_abt_start__ + __STACKSIZE_ABT__ , .), 4);
- }
- __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt);
-
- __stack_abt_load_end__ = __stack_abt_end__;
-
- . = ASSERT(__stack_abt_end__ >= __SRAM_segment_start__ && __stack_abt_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_abt is too large to fit in SRAM memory segment");
-
- __stack_und_load_start__ = ALIGN(__stack_abt_end__ , 4);
- .stack_und ALIGN(__stack_abt_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_abt_end__ , 4))
- {
- __stack_und_start__ = .;
- *(.stack_und .stack_und.*)
- . = ALIGN(MAX(__stack_und_start__ + __STACKSIZE_UND__ , .), 4);
- }
- __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und);
-
- __stack_und_load_end__ = __stack_und_end__;
-
- . = ASSERT(__stack_und_end__ >= __SRAM_segment_start__ && __stack_und_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_und is too large to fit in SRAM memory segment");
-
- __fast_load_start__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4);
- .fast ALIGN(__stack_und_end__ , 4) : AT(ALIGN(__data_load_start__ + SIZEOF(.data) , 4))
- {
- __fast_start__ = .;
- *(.fast .fast.*)
- }
- __fast_end__ = __fast_start__ + SIZEOF(.fast);
-
- __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
-
- __FLASH_segment_used_end__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4) + SIZEOF(.fast);
-
- . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .fast is too large to fit in FLASH memory segment");
-
- .fast_run ALIGN(__stack_und_end__ , 4) (NOLOAD) :
- {
- __fast_run_start__ = .;
- . = MAX(__fast_run_start__ + SIZEOF(.fast), .);
- }
- __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run);
-
- __fast_run_load_end__ = __fast_run_end__;
-
- __SRAM_segment_used_end__ = ALIGN(__stack_und_end__ , 4) + SIZEOF(.fast_run);
-
- . = ASSERT(__fast_run_end__ >= __SRAM_segment_start__ && __fast_run_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .fast_run is too large to fit in SRAM memory segment");
-
-}
-
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/prog.dox b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/prog.dox
deleted file mode 100644
index 5da523f9..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/prog.dox
+++ /dev/null
@@ -1,7 +0,0 @@
-/**
-\defgroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks User Program
-\brief User Program.
-\ingroup ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-*/
-
-
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.c
deleted file mode 100644
index 7998238e..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\timer.c
-* \brief Timer driver source file.
-* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* Local data declarations
-****************************************************************************************/
-/** \brief Local variable for storing the number of milliseconds that have elapsed since
- * startup.
- */
-static unsigned long millisecond_counter;
-
-
-/****************************************************************************************
-* External functions
-****************************************************************************************/
-extern void TIMER0_ISR(void);
-
-
-/************************************************************************************//**
-** \brief Initializes the timer.
-** \return none.
-**
-****************************************************************************************/
-void TimerInit(void)
-{
- /* configure timer0 as 1 ms software output compare */
- T0MR0 = BOOT_CPU_SYSTEM_SPEED_KHZ-1;
- /* enable interrupt and automatic reset upon compare */
- T0MCR = 0x01 | 0x02;
- /* enable the output compare */
- T0TCR = 0x01;
- /* set the interrupt service routine for the output compare event */
- VICVectAddr0 = (unsigned long)TIMER0_ISR;
- /* connect vectored IRQ slot 0 to Timer0's channel 4 */
- VICVectCntl0 = 0x20 | 4;
- /* enable the timer0 interrupt */
- VICIntEnable = 0x10;
- /* reset the millisecond counter */
- TimerSet(0);
-} /*** end of TimerInit ***/
-
-
-/************************************************************************************//**
-** \brief Updates the millisecond timer. Should be called every millisecond by
-** the timer interrupt service routine.
-** \return none.
-**
-****************************************************************************************/
-void TimerUpdate(void)
-{
- /* increment the millisecond counter */
- millisecond_counter++;
-} /*** end of TimerUpdate ***/
-
-
-/************************************************************************************//**
-** \brief Sets the initial counter value of the millisecond timer.
-** \param timer_value initialize value of the millisecond timer.
-** \return none.
-**
-****************************************************************************************/
-void TimerSet(unsigned long timer_value)
-{
- /* set the millisecond counter */
- millisecond_counter = timer_value;
-} /*** end of TimerSet ***/
-
-
-/************************************************************************************//**
-** \brief Obtains the counter value of the millisecond timer.
-** \return Current value of the millisecond timer.
-**
-****************************************************************************************/
-unsigned long TimerGet(void)
-{
- /* read and return the millisecond counter value */
- return millisecond_counter;
-} /*** end of TimerGet ***/
-
-
-/*********************************** end of timer.c ************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.h
deleted file mode 100644
index 8e44a8b0..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\timer.h
-* \brief Timer driver header file.
-* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-#ifndef TIMER_H
-#define TIMER_H
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-void TimerInit(void);
-void TimerUpdate(void);
-void TimerSet(unsigned long timer_value);
-unsigned long TimerGet(void);
-
-
-#endif /* TIMER_H */
-/*********************************** end of timer.h ************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/vectors.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/vectors.c
deleted file mode 100644
index 7f4c245d..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/vectors.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\vectors.c
-* \brief Demo program interrupt vectors source file.
-* \ingroup Prog_ARM7_LPC2000_Olimex_LPC_L2294_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-void __attribute__ ((interrupt("IRQ"))) TIMER0_ISR(void);
-
-
-/************************************************************************************//**
-** \brief Timer0 exception routine.
-** \return none.
-**
-****************************************************************************************/
-void TIMER0_ISR(void)
-{
- /* clear the interrupt flag */
- T0IR = 0x01;
- /* acknowledge interrupt */
- VICVectAddr = 0;
- /* process time tick */
- TimerUpdate();
-} /*** end of TIMER0_ISR ***/
-
-
-/*********************************** end of vectors.c **********************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/demo.dox b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/demo.dox
deleted file mode 100644
index d89ec7df..00000000
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/demo.dox
+++ /dev/null
@@ -1,8 +0,0 @@
-/**
-\defgroup ARM7_LPC2000_Olimex_LPC_L2294_Crossworks Demo for Olimex LPC-L2294/Crossworks
-\brief Preconfigured programs for the Olimex LPC-L2294 and the Crossworks IDE.
-\details Refer to http://feaser.com/openblt/doku.php?id=manual:demos
- for detailed getting started instructions.
-*/
-
-
diff --git a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.elf b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.elf
index 124c44ec..db60538c 100644
Binary files a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.elf and b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.elf differ
diff --git a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.map b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.map
index 9d3a3a6d..687d78d7 100644
--- a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.map
+++ b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.map
@@ -17,14 +17,16 @@ Discarded input sections
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/cpu.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/cpu.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/cpu.o
- .text.CpuReset
- 0x00000000 0x10 THUMB Flash Debug/../../obj/cpu.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/flash.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/flash.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/flash.o
+ .text.FlashReinit
+ 0x00000000 0x18 THUMB Flash Debug/../../obj/flash.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/nvm.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/nvm.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/nvm.o
+ .text.NvmReinit
+ 0x00000000 0x8 THUMB Flash Debug/../../obj/nvm.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/timer.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/timer.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/timer.o
@@ -52,17 +54,30 @@ Discarded input sections
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/core_cm3.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/core_cm3.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_info 0x00000000 0x52 THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_abbrev 0x00000000 0x27 THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_pubnames
+ 0x00000000 0x12 THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_pubtypes
+ 0x00000000 0x9f THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_aranges
+ 0x00000000 0x18 THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_line 0x00000000 0x1d THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_str 0x00000000 0x217 THUMB Flash Debug/../../obj/core_cm3.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/core_cm3.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/core_cm3.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/system_efm32.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/system_efm32.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/system_efm32.o
.text.SystemHFXOClockGet
0x00000000 0xc THUMB Flash Debug/../../obj/system_efm32.o
.text.SystemHFXOClockSet
- 0x00000000 0x24 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x00000000 0x20 THUMB Flash Debug/../../obj/system_efm32.o
.text.SystemULFRCOClockGet
0x00000000 0x6 THUMB Flash Debug/../../obj/system_efm32.o
.text.SystemLFXOClockSet
- 0x00000000 0x24 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x00000000 0x20 THUMB Flash Debug/../../obj/system_efm32.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_acmp.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_acmp.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_acmp.o
@@ -77,58 +92,111 @@ Discarded input sections
.text.ACMP_Reset
0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_acmp.o
.text.ACMP_GPIOSetup
- 0x00000000 0x1c THUMB Flash Debug/../../obj/efm32_acmp.o
+ 0x00000000 0x1a THUMB Flash Debug/../../obj/efm32_acmp.o
.text.ACMP_ChannelSet
0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_acmp.o
.text.ACMP_Init
0x00000000 0x4a THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_frame 0x00000000 0xb4 THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_info 0x00000000 0x5b1 THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_abbrev 0x00000000 0x1ad THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_loc 0x00000000 0x21f THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_pubnames
+ 0x00000000 0xc0 THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_pubtypes
+ 0x00000000 0x18a THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_aranges
+ 0x00000000 0x58 THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_ranges 0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_line 0x00000000 0x35e THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_str 0x00000000 0x646 THUMB Flash Debug/../../obj/efm32_acmp.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_acmp.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_acmp.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_adc.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_adc.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_adc.o
.text.ADC_Init
0x00000000 0x32 THUMB Flash Debug/../../obj/efm32_adc.o
.text.ADC_InitScan
- 0x00000000 0xd8 THUMB Flash Debug/../../obj/efm32_adc.o
+ 0x00000000 0xe4 THUMB Flash Debug/../../obj/efm32_adc.o
.text.ADC_InitSingle
- 0x00000000 0xd4 THUMB Flash Debug/../../obj/efm32_adc.o
+ 0x00000000 0xe4 THUMB Flash Debug/../../obj/efm32_adc.o
.text.ADC_PrescaleCalc
0x00000000 0x40 THUMB Flash Debug/../../obj/efm32_adc.o
.text.ADC_Reset
0x00000000 0x44 THUMB Flash Debug/../../obj/efm32_adc.o
.text.ADC_TimebaseCalc
- 0x00000000 0x34 THUMB Flash Debug/../../obj/efm32_adc.o
+ 0x00000000 0x30 THUMB Flash Debug/../../obj/efm32_adc.o
+ .debug_frame 0x00000000 0xa8 THUMB Flash Debug/../../obj/efm32_adc.o
+ .debug_info 0x00000000 0xa27 THUMB Flash Debug/../../obj/efm32_adc.o
+ .debug_abbrev 0x00000000 0x219 THUMB Flash Debug/../../obj/efm32_adc.o
+ .debug_loc 0x00000000 0x27b THUMB Flash Debug/../../obj/efm32_adc.o
+ .debug_pubnames
+ 0x00000000 0x3b0 THUMB Flash Debug/../../obj/efm32_adc.o
+ .debug_pubtypes
+ 0x00000000 0x206 THUMB Flash Debug/../../obj/efm32_adc.o
+ .debug_aranges
+ 0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_adc.o
+ .debug_ranges 0x00000000 0x38 THUMB Flash Debug/../../obj/efm32_adc.o
+ .debug_line 0x00000000 0x38c THUMB Flash Debug/../../obj/efm32_adc.o
+ .debug_str 0x00000000 0xb39 THUMB Flash Debug/../../obj/efm32_adc.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_adc.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_adc.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_aes.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_aes.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_aes.o
.text.AES_CBC128
- 0x00000000 0x100 THUMB Flash Debug/../../obj/efm32_aes.o
+ 0x00000000 0xe8 THUMB Flash Debug/../../obj/efm32_aes.o
.text.AES_CBC256
- 0x00000000 0x130 THUMB Flash Debug/../../obj/efm32_aes.o
+ 0x00000000 0xf8 THUMB Flash Debug/../../obj/efm32_aes.o
.text.AES_CFB128
- 0x00000000 0x9c THUMB Flash Debug/../../obj/efm32_aes.o
+ 0x00000000 0x8c THUMB Flash Debug/../../obj/efm32_aes.o
.text.AES_CFB256
- 0x00000000 0xa8 THUMB Flash Debug/../../obj/efm32_aes.o
+ 0x00000000 0x90 THUMB Flash Debug/../../obj/efm32_aes.o
.text.AES_CTR128
- 0x00000000 0x7c THUMB Flash Debug/../../obj/efm32_aes.o
+ 0x00000000 0x80 THUMB Flash Debug/../../obj/efm32_aes.o
.text.AES_CTR256
- 0x00000000 0x78 THUMB Flash Debug/../../obj/efm32_aes.o
+ 0x00000000 0x80 THUMB Flash Debug/../../obj/efm32_aes.o
.text.AES_CTRUpdate32Bit
0x00000000 0xc THUMB Flash Debug/../../obj/efm32_aes.o
.text.AES_DecryptKey128
- 0x00000000 0x44 THUMB Flash Debug/../../obj/efm32_aes.o
+ 0x00000000 0x40 THUMB Flash Debug/../../obj/efm32_aes.o
.text.AES_DecryptKey256
- 0x00000000 0x44 THUMB Flash Debug/../../obj/efm32_aes.o
+ 0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_aes.o
.text.AES_ECB128
- 0x00000000 0x74 THUMB Flash Debug/../../obj/efm32_aes.o
+ 0x00000000 0x6c THUMB Flash Debug/../../obj/efm32_aes.o
.text.AES_ECB256
- 0x00000000 0x88 THUMB Flash Debug/../../obj/efm32_aes.o
+ 0x00000000 0x68 THUMB Flash Debug/../../obj/efm32_aes.o
.text.AES_OFB128
- 0x00000000 0x74 THUMB Flash Debug/../../obj/efm32_aes.o
+ 0x00000000 0x70 THUMB Flash Debug/../../obj/efm32_aes.o
.text.AES_OFB256
- 0x00000000 0x98 THUMB Flash Debug/../../obj/efm32_aes.o
+ 0x00000000 0x80 THUMB Flash Debug/../../obj/efm32_aes.o
+ .debug_frame 0x00000000 0x1fc THUMB Flash Debug/../../obj/efm32_aes.o
+ .debug_info 0x00000000 0x1461 THUMB Flash Debug/../../obj/efm32_aes.o
+ .debug_abbrev 0x00000000 0x26b THUMB Flash Debug/../../obj/efm32_aes.o
+ .debug_loc 0x00000000 0x170e THUMB Flash Debug/../../obj/efm32_aes.o
+ .debug_pubnames
+ 0x00000000 0x106 THUMB Flash Debug/../../obj/efm32_aes.o
+ .debug_pubtypes
+ 0x00000000 0x106 THUMB Flash Debug/../../obj/efm32_aes.o
+ .debug_aranges
+ 0x00000000 0x80 THUMB Flash Debug/../../obj/efm32_aes.o
+ .debug_ranges 0x00000000 0x70 THUMB Flash Debug/../../obj/efm32_aes.o
+ .debug_line 0x00000000 0xa83 THUMB Flash Debug/../../obj/efm32_aes.o
+ .debug_str 0x00000000 0x3ae THUMB Flash Debug/../../obj/efm32_aes.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_aes.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_aes.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_assert.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_assert.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_assert.o
+ .debug_line 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_assert.o
+ .debug_str 0x00000000 0x1a9 THUMB Flash Debug/../../obj/efm32_assert.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_assert.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_assert.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_cmu.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_cmu.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_cmu.o
@@ -141,7 +209,7 @@ Discarded input sections
.text.CMU_HFRCOBandGet
0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_cmu.o
.text.CMU_HFRCOBandSet
- 0x00000000 0x8c THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00000000 0x90 THUMB Flash Debug/../../obj/efm32_cmu.o
.text.CMU_HFRCOStartupDelayGet
0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_cmu.o
.text.CMU_HFRCOStartupDelaySet
@@ -157,69 +225,115 @@ Discarded input sections
.text.CMU_PCNTClockExternalGet
0x00000000 0x38 THUMB Flash Debug/../../obj/efm32_cmu.o
.text.CMU_PCNTClockExternalSet
- 0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00000000 0xc THUMB Flash Debug/../../obj/efm32_cmu.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_dac.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_dac.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_dac.o
.text.DAC_Enable
- 0x00000000 0x14 THUMB Flash Debug/../../obj/efm32_dac.o
+ 0x00000000 0x12 THUMB Flash Debug/../../obj/efm32_dac.o
.text.DAC_Init
- 0x00000000 0x7c THUMB Flash Debug/../../obj/efm32_dac.o
+ 0x00000000 0x74 THUMB Flash Debug/../../obj/efm32_dac.o
.text.DAC_InitChannel
0x00000000 0x28 THUMB Flash Debug/../../obj/efm32_dac.o
.text.DAC_PrescaleCalc
0x00000000 0x34 THUMB Flash Debug/../../obj/efm32_dac.o
.text.DAC_Reset
0x00000000 0x20 THUMB Flash Debug/../../obj/efm32_dac.o
+ .debug_frame 0x00000000 0x78 THUMB Flash Debug/../../obj/efm32_dac.o
+ .debug_info 0x00000000 0x7e2 THUMB Flash Debug/../../obj/efm32_dac.o
+ .debug_abbrev 0x00000000 0x228 THUMB Flash Debug/../../obj/efm32_dac.o
+ .debug_loc 0x00000000 0x21e THUMB Flash Debug/../../obj/efm32_dac.o
+ .debug_pubnames
+ 0x00000000 0x332 THUMB Flash Debug/../../obj/efm32_dac.o
+ .debug_pubtypes
+ 0x00000000 0x1a3 THUMB Flash Debug/../../obj/efm32_dac.o
+ .debug_aranges
+ 0x00000000 0x40 THUMB Flash Debug/../../obj/efm32_dac.o
+ .debug_ranges 0x00000000 0x30 THUMB Flash Debug/../../obj/efm32_dac.o
+ .debug_line 0x00000000 0x33f THUMB Flash Debug/../../obj/efm32_dac.o
+ .debug_str 0x00000000 0x7d0 THUMB Flash Debug/../../obj/efm32_dac.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_dac.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_dac.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_dbg.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_dbg.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_dbg.o
.text.DBG_SWOEnable
- 0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_dbg.o
+ 0x00000000 0x50 THUMB Flash Debug/../../obj/efm32_dbg.o
+ .debug_frame 0x00000000 0x44 THUMB Flash Debug/../../obj/efm32_dbg.o
+ .debug_info 0x00000000 0x40d THUMB Flash Debug/../../obj/efm32_dbg.o
+ .debug_abbrev 0x00000000 0x1d9 THUMB Flash Debug/../../obj/efm32_dbg.o
+ .debug_loc 0x00000000 0xad THUMB Flash Debug/../../obj/efm32_dbg.o
+ .debug_pubnames
+ 0x00000000 0x24b THUMB Flash Debug/../../obj/efm32_dbg.o
+ .debug_pubtypes
+ 0x00000000 0x109 THUMB Flash Debug/../../obj/efm32_dbg.o
+ .debug_aranges
+ 0x00000000 0x20 THUMB Flash Debug/../../obj/efm32_dbg.o
+ .debug_ranges 0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_dbg.o
+ .debug_line 0x00000000 0x2dd THUMB Flash Debug/../../obj/efm32_dbg.o
+ .debug_str 0x00000000 0x513 THUMB Flash Debug/../../obj/efm32_dbg.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_dbg.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_dbg.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_dma.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_dma.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_dma.o
.text.DMA_Prepare
- 0x00000000 0x90 THUMB Flash Debug/../../obj/efm32_dma.o
+ 0x00000000 0x8c THUMB Flash Debug/../../obj/efm32_dma.o
.text.DMA_IRQHandler
- 0x00000000 0x78 THUMB Flash Debug/../../obj/efm32_dma.o
+ 0x00000000 0x74 THUMB Flash Debug/../../obj/efm32_dma.o
.text.DMA_ActivateAuto
- 0x00000000 0x30 THUMB Flash Debug/../../obj/efm32_dma.o
+ 0x00000000 0x2c THUMB Flash Debug/../../obj/efm32_dma.o
.text.DMA_ActivateBasic
- 0x00000000 0x34 THUMB Flash Debug/../../obj/efm32_dma.o
+ 0x00000000 0x30 THUMB Flash Debug/../../obj/efm32_dma.o
.text.DMA_ActivatePingPong
0x00000000 0x4c THUMB Flash Debug/../../obj/efm32_dma.o
.text.DMA_ActivateScatterGather
- 0x00000000 0x80 THUMB Flash Debug/../../obj/efm32_dma.o
+ 0x00000000 0x84 THUMB Flash Debug/../../obj/efm32_dma.o
.text.DMA_CfgChannel
0x00000000 0x4c THUMB Flash Debug/../../obj/efm32_dma.o
.text.DMA_CfgDescr
- 0x00000000 0x3c THUMB Flash Debug/../../obj/efm32_dma.o
+ 0x00000000 0x38 THUMB Flash Debug/../../obj/efm32_dma.o
.text.DMA_CfgDescrScatterGather
- 0x00000000 0x5e THUMB Flash Debug/../../obj/efm32_dma.o
+ 0x00000000 0x72 THUMB Flash Debug/../../obj/efm32_dma.o
.text.DMA_ChannelEnabled
0x00000000 0x14 THUMB Flash Debug/../../obj/efm32_dma.o
.text.DMA_RefreshPingPong
- 0x00000000 0x74 THUMB Flash Debug/../../obj/efm32_dma.o
+ 0x00000000 0x78 THUMB Flash Debug/../../obj/efm32_dma.o
.text.DMA_Reset
0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_dma.o
.text.DMA_Init
0x00000000 0x4c THUMB Flash Debug/../../obj/efm32_dma.o
+ .debug_frame 0x00000000 0x1c8 THUMB Flash Debug/../../obj/efm32_dma.o
+ .debug_info 0x00000000 0x1144 THUMB Flash Debug/../../obj/efm32_dma.o
+ .debug_abbrev 0x00000000 0x390 THUMB Flash Debug/../../obj/efm32_dma.o
+ .debug_loc 0x00000000 0x8d6 THUMB Flash Debug/../../obj/efm32_dma.o
+ .debug_pubnames
+ 0x00000000 0x866 THUMB Flash Debug/../../obj/efm32_dma.o
+ .debug_pubtypes
+ 0x00000000 0x25c THUMB Flash Debug/../../obj/efm32_dma.o
+ .debug_aranges
+ 0x00000000 0x80 THUMB Flash Debug/../../obj/efm32_dma.o
+ .debug_ranges 0x00000000 0x70 THUMB Flash Debug/../../obj/efm32_dma.o
+ .debug_line 0x00000000 0x4e6 THUMB Flash Debug/../../obj/efm32_dma.o
+ .debug_str 0x00000000 0xca9 THUMB Flash Debug/../../obj/efm32_dma.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_dma.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_dma.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_ebi.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_ebi.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_ebi.o
- .text.BITBAND_Peripheral
- 0x00000000 0xe THUMB Flash Debug/../../obj/efm32_ebi.o
.text.EBI_Disable
0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_ebi.o
.text.EBI_BankEnable
- 0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_ebi.o
+ 0x00000000 0x34 THUMB Flash Debug/../../obj/efm32_ebi.o
.text.EBI_BankAddress
0x00000000 0x14 THUMB Flash Debug/../../obj/efm32_ebi.o
.text.EBI_ChipSelectEnable
- 0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_ebi.o
+ 0x00000000 0x34 THUMB Flash Debug/../../obj/efm32_ebi.o
.text.EBI_PolaritySet
- 0x00000000 0x44 THUMB Flash Debug/../../obj/efm32_ebi.o
+ 0x00000000 0x38 THUMB Flash Debug/../../obj/efm32_ebi.o
.text.EBI_ReadTimingSet
0x00000000 0x20 THUMB Flash Debug/../../obj/efm32_ebi.o
.text.EBI_WriteTimingSet
@@ -227,18 +341,34 @@ Discarded input sections
.text.EBI_AddressTimingSet
0x00000000 0x1c THUMB Flash Debug/../../obj/efm32_ebi.o
.text.EBI_Init
- 0x00000000 0xd4 THUMB Flash Debug/../../obj/efm32_ebi.o
- .rodata.CSWTCH.3
+ 0x00000000 0xc8 THUMB Flash Debug/../../obj/efm32_ebi.o
+ .rodata.CSWTCH.6
0x00000000 0x3c THUMB Flash Debug/../../obj/efm32_ebi.o
+ .debug_frame 0x00000000 0xc8 THUMB Flash Debug/../../obj/efm32_ebi.o
+ .debug_info 0x00000000 0xb03 THUMB Flash Debug/../../obj/efm32_ebi.o
+ .debug_abbrev 0x00000000 0x28a THUMB Flash Debug/../../obj/efm32_ebi.o
+ .debug_loc 0x00000000 0x660 THUMB Flash Debug/../../obj/efm32_ebi.o
+ .debug_pubnames
+ 0x00000000 0x162 THUMB Flash Debug/../../obj/efm32_ebi.o
+ .debug_pubtypes
+ 0x00000000 0x14d THUMB Flash Debug/../../obj/efm32_ebi.o
+ .debug_aranges
+ 0x00000000 0x60 THUMB Flash Debug/../../obj/efm32_ebi.o
+ .debug_ranges 0x00000000 0xb0 THUMB Flash Debug/../../obj/efm32_ebi.o
+ .debug_line 0x00000000 0x41d THUMB Flash Debug/../../obj/efm32_ebi.o
+ .debug_str 0x00000000 0x5b6 THUMB Flash Debug/../../obj/efm32_ebi.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_ebi.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_ebi.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_emu.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_emu.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_emu.o
.text.EMU_Restore
0x00000000 0x78 THUMB Flash Debug/../../obj/efm32_emu.o
.text.EMU_EnterEM2
- 0x00000000 0x44 THUMB Flash Debug/../../obj/efm32_emu.o
+ 0x00000000 0x3c THUMB Flash Debug/../../obj/efm32_emu.o
.text.EMU_EnterEM3
- 0x00000000 0x5c THUMB Flash Debug/../../obj/efm32_emu.o
+ 0x00000000 0x60 THUMB Flash Debug/../../obj/efm32_emu.o
.text.EMU_EnterEM4
0x00000000 0x24 THUMB Flash Debug/../../obj/efm32_emu.o
.text.EMU_MemPwrDown
@@ -249,13 +379,13 @@ Discarded input sections
.text.GPIO_DbgLocationSet
0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_gpio.o
.text.GPIO_IntConfig
- 0x00000000 0x88 THUMB Flash Debug/../../obj/efm32_gpio.o
+ 0x00000000 0x64 THUMB Flash Debug/../../obj/efm32_gpio.o
.text.GPIO_PinInGet
- 0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_gpio.o
+ 0x00000000 0x16 THUMB Flash Debug/../../obj/efm32_gpio.o
.text.GPIO_PinOutClear
0x00000000 0x16 THUMB Flash Debug/../../obj/efm32_gpio.o
.text.GPIO_PinOutGet
- 0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_gpio.o
+ 0x00000000 0x16 THUMB Flash Debug/../../obj/efm32_gpio.o
.text.GPIO_PinOutSet
0x00000000 0x16 THUMB Flash Debug/../../obj/efm32_gpio.o
.text.GPIO_PinOutToggle
@@ -269,7 +399,7 @@ Discarded input sections
.text.GPIO_PortOutSet
0x00000000 0x12 THUMB Flash Debug/../../obj/efm32_gpio.o
.text.GPIO_PortOutSetVal
- 0x00000000 0x1c THUMB Flash Debug/../../obj/efm32_gpio.o
+ 0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_gpio.o
.text.GPIO_PortOutToggle
0x00000000 0x12 THUMB Flash Debug/../../obj/efm32_gpio.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_i2c.o
@@ -280,29 +410,58 @@ Discarded input sections
.text.I2C_BusFreqSet
0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_i2c.o
.text.I2C_Enable
- 0x00000000 0xc THUMB Flash Debug/../../obj/efm32_i2c.o
+ 0x00000000 0xa THUMB Flash Debug/../../obj/efm32_i2c.o
.text.I2C_Init
0x00000000 0x34 THUMB Flash Debug/../../obj/efm32_i2c.o
.text.I2C_Reset
0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_i2c.o
.text.I2C_Transfer
- 0x00000000 0x290 THUMB Flash Debug/../../obj/efm32_i2c.o
+ 0x00000000 0x2c8 THUMB Flash Debug/../../obj/efm32_i2c.o
.text.I2C_TransferInit
- 0x00000000 0x78 THUMB Flash Debug/../../obj/efm32_i2c.o
+ 0x00000000 0x68 THUMB Flash Debug/../../obj/efm32_i2c.o
.rodata.i2cNSum
0x00000000 0x4 THUMB Flash Debug/../../obj/efm32_i2c.o
.bss.i2cTransfer
- 0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_i2c.o
+ 0x00000000 0xc THUMB Flash Debug/../../obj/efm32_i2c.o
+ .debug_frame 0x00000000 0xc4 THUMB Flash Debug/../../obj/efm32_i2c.o
+ .debug_info 0x00000000 0x8cc THUMB Flash Debug/../../obj/efm32_i2c.o
+ .debug_abbrev 0x00000000 0x2e2 THUMB Flash Debug/../../obj/efm32_i2c.o
+ .debug_loc 0x00000000 0x536 THUMB Flash Debug/../../obj/efm32_i2c.o
+ .debug_pubnames
+ 0x00000000 0x4d7 THUMB Flash Debug/../../obj/efm32_i2c.o
+ .debug_pubtypes
+ 0x00000000 0x198 THUMB Flash Debug/../../obj/efm32_i2c.o
+ .debug_aranges
+ 0x00000000 0x50 THUMB Flash Debug/../../obj/efm32_i2c.o
+ .debug_ranges 0x00000000 0x58 THUMB Flash Debug/../../obj/efm32_i2c.o
+ .debug_line 0x00000000 0x42e THUMB Flash Debug/../../obj/efm32_i2c.o
+ .debug_str 0x00000000 0x7a1 THUMB Flash Debug/../../obj/efm32_i2c.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_i2c.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_i2c.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_int.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_int.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_int.o
.bss.INT_LockCnt
0x00000000 0x4 THUMB Flash Debug/../../obj/efm32_int.o
+ .debug_info 0x00000000 0x91 THUMB Flash Debug/../../obj/efm32_int.o
+ .debug_abbrev 0x00000000 0x5d THUMB Flash Debug/../../obj/efm32_int.o
+ .debug_pubnames
+ 0x00000000 0x22 THUMB Flash Debug/../../obj/efm32_int.o
+ .debug_pubtypes
+ 0x00000000 0xc5 THUMB Flash Debug/../../obj/efm32_int.o
+ .debug_aranges
+ 0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_int.o
+ .debug_line 0x00000000 0x17a THUMB Flash Debug/../../obj/efm32_int.o
+ .debug_str 0x00000000 0x242 THUMB Flash Debug/../../obj/efm32_int.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_int.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_int.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_lcd.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_lcd.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_lcd.o
.text.LCD_Initialize
- 0x00000000 0x40 THUMB Flash Debug/../../obj/efm32_lcd.o
+ 0x00000000 0x3c THUMB Flash Debug/../../obj/efm32_lcd.o
.text.LCD_VLCDSelect
0x00000000 0x1c THUMB Flash Debug/../../obj/efm32_lcd.o
.text.LCD_UpdateCtrl
@@ -314,48 +473,95 @@ Discarded input sections
.text.LCD_SegmentRangeEnable
0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_lcd.o
.text.LCD_SegmentSet
- 0x00000000 0x60 THUMB Flash Debug/../../obj/efm32_lcd.o
+ 0x00000000 0x58 THUMB Flash Debug/../../obj/efm32_lcd.o
.text.LCD_SegmentSetLow
- 0x00000000 0x50 THUMB Flash Debug/../../obj/efm32_lcd.o
+ 0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_lcd.o
.text.LCD_SegmentSetHigh
- 0x00000000 0x50 THUMB Flash Debug/../../obj/efm32_lcd.o
+ 0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_lcd.o
.text.LCD_ContrastSet
0x00000000 0x14 THUMB Flash Debug/../../obj/efm32_lcd.o
.text.LCD_VBoostSet
0x00000000 0x14 THUMB Flash Debug/../../obj/efm32_lcd.o
+ .debug_frame 0x00000000 0xc0 THUMB Flash Debug/../../obj/efm32_lcd.o
+ .debug_info 0x00000000 0xa50 THUMB Flash Debug/../../obj/efm32_lcd.o
+ .debug_abbrev 0x00000000 0x27a THUMB Flash Debug/../../obj/efm32_lcd.o
+ .debug_loc 0x00000000 0x6ea THUMB Flash Debug/../../obj/efm32_lcd.o
+ .debug_pubnames
+ 0x00000000 0x170 THUMB Flash Debug/../../obj/efm32_lcd.o
+ .debug_pubtypes
+ 0x00000000 0x23d THUMB Flash Debug/../../obj/efm32_lcd.o
+ .debug_aranges
+ 0x00000000 0x70 THUMB Flash Debug/../../obj/efm32_lcd.o
+ .debug_ranges 0x00000000 0x78 THUMB Flash Debug/../../obj/efm32_lcd.o
+ .debug_line 0x00000000 0x3fd THUMB Flash Debug/../../obj/efm32_lcd.o
+ .debug_str 0x00000000 0x84f THUMB Flash Debug/../../obj/efm32_lcd.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_lcd.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_lcd.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_lesense.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_lesense.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_lesense.o
+ .debug_info 0x00000000 0x75 THUMB Flash Debug/../../obj/efm32_lesense.o
+ .debug_abbrev 0x00000000 0x4c THUMB Flash Debug/../../obj/efm32_lesense.o
+ .debug_pubnames
+ 0x00000000 0x12 THUMB Flash Debug/../../obj/efm32_lesense.o
+ .debug_pubtypes
+ 0x00000000 0xb8 THUMB Flash Debug/../../obj/efm32_lesense.o
+ .debug_aranges
+ 0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_lesense.o
+ .debug_line 0x00000000 0xfa THUMB Flash Debug/../../obj/efm32_lesense.o
+ .debug_str 0x00000000 0x231 THUMB Flash Debug/../../obj/efm32_lesense.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_lesense.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_lesense.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_letimer.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_letimer.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_letimer.o
.text.LETIMER_Sync
0x00000000 0xe THUMB Flash Debug/../../obj/efm32_letimer.o
.text.LETIMER_CompareGet
- 0x00000000 0x14 THUMB Flash Debug/../../obj/efm32_letimer.o
+ 0x00000000 0x12 THUMB Flash Debug/../../obj/efm32_letimer.o
.text.LETIMER_CompareSet
- 0x00000000 0x28 THUMB Flash Debug/../../obj/efm32_letimer.o
+ 0x00000000 0x24 THUMB Flash Debug/../../obj/efm32_letimer.o
.text.LETIMER_Enable
0x00000000 0x1c THUMB Flash Debug/../../obj/efm32_letimer.o
.text.LETIMER_FreezeEnable
- 0x00000000 0x14 THUMB Flash Debug/../../obj/efm32_letimer.o
+ 0x00000000 0x12 THUMB Flash Debug/../../obj/efm32_letimer.o
.text.LETIMER_Init
0x00000000 0x8c THUMB Flash Debug/../../obj/efm32_letimer.o
.text.LETIMER_RepeatGet
- 0x00000000 0x14 THUMB Flash Debug/../../obj/efm32_letimer.o
+ 0x00000000 0x12 THUMB Flash Debug/../../obj/efm32_letimer.o
.text.LETIMER_RepeatSet
- 0x00000000 0x28 THUMB Flash Debug/../../obj/efm32_letimer.o
+ 0x00000000 0x24 THUMB Flash Debug/../../obj/efm32_letimer.o
.text.LETIMER_Reset
- 0x00000000 0x2c THUMB Flash Debug/../../obj/efm32_letimer.o
+ 0x00000000 0x22 THUMB Flash Debug/../../obj/efm32_letimer.o
+ .debug_frame 0x00000000 0xd4 THUMB Flash Debug/../../obj/efm32_letimer.o
+ .debug_info 0x00000000 0x5ef THUMB Flash Debug/../../obj/efm32_letimer.o
+ .debug_abbrev 0x00000000 0x2a9 THUMB Flash Debug/../../obj/efm32_letimer.o
+ .debug_loc 0x00000000 0x3ca THUMB Flash Debug/../../obj/efm32_letimer.o
+ .debug_pubnames
+ 0x00000000 0xcc THUMB Flash Debug/../../obj/efm32_letimer.o
+ .debug_pubtypes
+ 0x00000000 0x140 THUMB Flash Debug/../../obj/efm32_letimer.o
+ .debug_aranges
+ 0x00000000 0x60 THUMB Flash Debug/../../obj/efm32_letimer.o
+ .debug_ranges 0x00000000 0x50 THUMB Flash Debug/../../obj/efm32_letimer.o
+ .debug_line 0x00000000 0x3a5 THUMB Flash Debug/../../obj/efm32_letimer.o
+ .debug_str 0x00000000 0x49f THUMB Flash Debug/../../obj/efm32_letimer.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_letimer.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_letimer.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_leuart.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_leuart.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_leuart.o
.text.LEUART_BaudrateCalc
- 0x00000000 0x1e THUMB Flash Debug/../../obj/efm32_leuart.o
+ 0x00000000 0x20 THUMB Flash Debug/../../obj/efm32_leuart.o
.text.LEUART_BaudrateGet
- 0x00000000 0x3c THUMB Flash Debug/../../obj/efm32_leuart.o
+ 0x00000000 0x40 THUMB Flash Debug/../../obj/efm32_leuart.o
+ .text.LEUART_FreezeEnable
+ 0x00000000 0x12 THUMB Flash Debug/../../obj/efm32_leuart.o
.text.LEUART_Reset
- 0x00000000 0x30 THUMB Flash Debug/../../obj/efm32_leuart.o
+ 0x00000000 0x26 THUMB Flash Debug/../../obj/efm32_leuart.o
.text.LEUART_RxExt
0x00000000 0xc THUMB Flash Debug/../../obj/efm32_leuart.o
.text.LEUART_TxExt
@@ -365,12 +571,40 @@ Discarded input sections
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_mpu.o
.text.MPU_ConfigureRegion
0x00000000 0x4c THUMB Flash Debug/../../obj/efm32_mpu.o
+ .debug_frame 0x00000000 0x20 THUMB Flash Debug/../../obj/efm32_mpu.o
+ .debug_info 0x00000000 0x30b THUMB Flash Debug/../../obj/efm32_mpu.o
+ .debug_abbrev 0x00000000 0x104 THUMB Flash Debug/../../obj/efm32_mpu.o
+ .debug_pubnames
+ 0x00000000 0x2a THUMB Flash Debug/../../obj/efm32_mpu.o
+ .debug_pubtypes
+ 0x00000000 0x137 THUMB Flash Debug/../../obj/efm32_mpu.o
+ .debug_aranges
+ 0x00000000 0x20 THUMB Flash Debug/../../obj/efm32_mpu.o
+ .debug_ranges 0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_mpu.o
+ .debug_line 0x00000000 0x20e THUMB Flash Debug/../../obj/efm32_mpu.o
+ .debug_str 0x00000000 0x5ac THUMB Flash Debug/../../obj/efm32_mpu.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_mpu.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_mpu.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_msc.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_msc.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_msc.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_opamp.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_opamp.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_opamp.o
+ .debug_info 0x00000000 0x75 THUMB Flash Debug/../../obj/efm32_opamp.o
+ .debug_abbrev 0x00000000 0x4c THUMB Flash Debug/../../obj/efm32_opamp.o
+ .debug_pubnames
+ 0x00000000 0x12 THUMB Flash Debug/../../obj/efm32_opamp.o
+ .debug_pubtypes
+ 0x00000000 0xb8 THUMB Flash Debug/../../obj/efm32_opamp.o
+ .debug_aranges
+ 0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_opamp.o
+ .debug_line 0x00000000 0xfa THUMB Flash Debug/../../obj/efm32_opamp.o
+ .debug_str 0x00000000 0x22f THUMB Flash Debug/../../obj/efm32_opamp.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_opamp.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_opamp.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_pcnt.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_pcnt.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_pcnt.o
@@ -379,33 +613,81 @@ Discarded input sections
.text.PCNT_CounterReset
0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_pcnt.o
.text.PCNT_CounterTopSet
- 0x00000000 0x70 THUMB Flash Debug/../../obj/efm32_pcnt.o
+ 0x00000000 0x68 THUMB Flash Debug/../../obj/efm32_pcnt.o
.text.PCNT_Enable
- 0x00000000 0x1c THUMB Flash Debug/../../obj/efm32_pcnt.o
+ 0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_pcnt.o
.text.PCNT_FreezeEnable
- 0x00000000 0x14 THUMB Flash Debug/../../obj/efm32_pcnt.o
+ 0x00000000 0x12 THUMB Flash Debug/../../obj/efm32_pcnt.o
.text.PCNT_Init
- 0x00000000 0xc0 THUMB Flash Debug/../../obj/efm32_pcnt.o
- .text.PCNT_Reset
- 0x00000000 0x54 THUMB Flash Debug/../../obj/efm32_pcnt.o
+ 0x00000000 0xb8 THUMB Flash Debug/../../obj/efm32_pcnt.o
.text.PCNT_TopBufferSet
0x00000000 0x14 THUMB Flash Debug/../../obj/efm32_pcnt.o
+ .text.PCNT_Reset
+ 0x00000000 0x4c THUMB Flash Debug/../../obj/efm32_pcnt.o
.text.PCNT_TopSet
- 0x00000000 0x20 THUMB Flash Debug/../../obj/efm32_pcnt.o
+ 0x00000000 0x1c THUMB Flash Debug/../../obj/efm32_pcnt.o
+ .debug_frame 0x00000000 0x10c THUMB Flash Debug/../../obj/efm32_pcnt.o
+ .debug_info 0x00000000 0x7ea THUMB Flash Debug/../../obj/efm32_pcnt.o
+ .debug_abbrev 0x00000000 0x2a4 THUMB Flash Debug/../../obj/efm32_pcnt.o
+ .debug_loc 0x00000000 0x4b4 THUMB Flash Debug/../../obj/efm32_pcnt.o
+ .debug_pubnames
+ 0x00000000 0x12e THUMB Flash Debug/../../obj/efm32_pcnt.o
+ .debug_pubtypes
+ 0x00000000 0x10c THUMB Flash Debug/../../obj/efm32_pcnt.o
+ .debug_aranges
+ 0x00000000 0x60 THUMB Flash Debug/../../obj/efm32_pcnt.o
+ .debug_ranges 0x00000000 0xa8 THUMB Flash Debug/../../obj/efm32_pcnt.o
+ .debug_line 0x00000000 0x409 THUMB Flash Debug/../../obj/efm32_pcnt.o
+ .debug_str 0x00000000 0x3c6 THUMB Flash Debug/../../obj/efm32_pcnt.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_pcnt.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_pcnt.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_prs.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_prs.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_prs.o
.text.PRS_SourceSignalSet
0x00000000 0x1c THUMB Flash Debug/../../obj/efm32_prs.o
+ .debug_frame 0x00000000 0x20 THUMB Flash Debug/../../obj/efm32_prs.o
+ .debug_info 0x00000000 0x1a3 THUMB Flash Debug/../../obj/efm32_prs.o
+ .debug_abbrev 0x00000000 0xf3 THUMB Flash Debug/../../obj/efm32_prs.o
+ .debug_loc 0x00000000 0x83 THUMB Flash Debug/../../obj/efm32_prs.o
+ .debug_pubnames
+ 0x00000000 0x2a THUMB Flash Debug/../../obj/efm32_prs.o
+ .debug_pubtypes
+ 0x00000000 0xfd THUMB Flash Debug/../../obj/efm32_prs.o
+ .debug_aranges
+ 0x00000000 0x20 THUMB Flash Debug/../../obj/efm32_prs.o
+ .debug_ranges 0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_prs.o
+ .debug_line 0x00000000 0x2a1 THUMB Flash Debug/../../obj/efm32_prs.o
+ .debug_str 0x00000000 0x2d5 THUMB Flash Debug/../../obj/efm32_prs.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_prs.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_prs.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_rmu.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_rmu.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_rmu.o
.text.RMU_LockupResetDisable
0x00000000 0xc THUMB Flash Debug/../../obj/efm32_rmu.o
.text.RMU_ResetCauseClear
- 0x00000000 0x34 THUMB Flash Debug/../../obj/efm32_rmu.o
+ 0x00000000 0x30 THUMB Flash Debug/../../obj/efm32_rmu.o
.text.RMU_ResetCauseGet
0x00000000 0x2c THUMB Flash Debug/../../obj/efm32_rmu.o
+ .debug_frame 0x00000000 0x40 THUMB Flash Debug/../../obj/efm32_rmu.o
+ .debug_info 0x00000000 0x2de THUMB Flash Debug/../../obj/efm32_rmu.o
+ .debug_abbrev 0x00000000 0x1ad THUMB Flash Debug/../../obj/efm32_rmu.o
+ .debug_loc 0x00000000 0x133 THUMB Flash Debug/../../obj/efm32_rmu.o
+ .debug_pubnames
+ 0x00000000 0x8e THUMB Flash Debug/../../obj/efm32_rmu.o
+ .debug_pubtypes
+ 0x00000000 0xef THUMB Flash Debug/../../obj/efm32_rmu.o
+ .debug_aranges
+ 0x00000000 0x30 THUMB Flash Debug/../../obj/efm32_rmu.o
+ .debug_ranges 0x00000000 0x20 THUMB Flash Debug/../../obj/efm32_rmu.o
+ .debug_line 0x00000000 0x2ff THUMB Flash Debug/../../obj/efm32_rmu.o
+ .debug_str 0x00000000 0x2f9 THUMB Flash Debug/../../obj/efm32_rmu.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_rmu.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_rmu.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_rtc.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_rtc.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_rtc.o
@@ -414,7 +696,7 @@ Discarded input sections
.text.RTC_CompareGet
0x00000000 0x1c THUMB Flash Debug/../../obj/efm32_rtc.o
.text.RTC_CompareSet
- 0x00000000 0x2c THUMB Flash Debug/../../obj/efm32_rtc.o
+ 0x00000000 0x28 THUMB Flash Debug/../../obj/efm32_rtc.o
.text.RTC_Enable
0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_rtc.o
.text.RTC_FreezeEnable
@@ -424,48 +706,80 @@ Discarded input sections
.text.RTC_Reset
0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_rtc.o
.text.RTC_CounterReset
- 0x00000000 0x14 THUMB Flash Debug/../../obj/efm32_rtc.o
+ 0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_rtc.o
+ .debug_frame 0x00000000 0xc8 THUMB Flash Debug/../../obj/efm32_rtc.o
+ .debug_info 0x00000000 0x3b8 THUMB Flash Debug/../../obj/efm32_rtc.o
+ .debug_abbrev 0x00000000 0x23d THUMB Flash Debug/../../obj/efm32_rtc.o
+ .debug_loc 0x00000000 0x1a8 THUMB Flash Debug/../../obj/efm32_rtc.o
+ .debug_pubnames
+ 0x00000000 0xb0 THUMB Flash Debug/../../obj/efm32_rtc.o
+ .debug_pubtypes
+ 0x00000000 0xf4 THUMB Flash Debug/../../obj/efm32_rtc.o
+ .debug_aranges
+ 0x00000000 0x58 THUMB Flash Debug/../../obj/efm32_rtc.o
+ .debug_ranges 0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_rtc.o
+ .debug_line 0x00000000 0x361 THUMB Flash Debug/../../obj/efm32_rtc.o
+ .debug_str 0x00000000 0x338 THUMB Flash Debug/../../obj/efm32_rtc.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_rtc.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_rtc.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_system.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_system.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_system.o
.text.SYSTEM_GetCalibrationValue
- 0x00000000 0x2c THUMB Flash Debug/../../obj/efm32_system.o
+ 0x00000000 0x28 THUMB Flash Debug/../../obj/efm32_system.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_timer.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_timer.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_timer.o
.text.TIMER_Enable
- 0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_timer.o
+ 0x00000000 0xc THUMB Flash Debug/../../obj/efm32_timer.o
.text.TIMER_Init
0x00000000 0x6e THUMB Flash Debug/../../obj/efm32_timer.o
.text.TIMER_InitCC
- 0x00000000 0x64 THUMB Flash Debug/../../obj/efm32_timer.o
+ 0x00000000 0x66 THUMB Flash Debug/../../obj/efm32_timer.o
.text.TIMER_Lock
0x00000000 0x8 THUMB Flash Debug/../../obj/efm32_timer.o
.text.TIMER_Reset
0x00000000 0x44 THUMB Flash Debug/../../obj/efm32_timer.o
.text.TIMER_Unlock
0x00000000 0xa THUMB Flash Debug/../../obj/efm32_timer.o
+ .debug_frame 0x00000000 0x88 THUMB Flash Debug/../../obj/efm32_timer.o
+ .debug_info 0x00000000 0x695 THUMB Flash Debug/../../obj/efm32_timer.o
+ .debug_abbrev 0x00000000 0x15d THUMB Flash Debug/../../obj/efm32_timer.o
+ .debug_loc 0x00000000 0x87 THUMB Flash Debug/../../obj/efm32_timer.o
+ .debug_pubnames
+ 0x00000000 0x73 THUMB Flash Debug/../../obj/efm32_timer.o
+ .debug_pubtypes
+ 0x00000000 0x20f THUMB Flash Debug/../../obj/efm32_timer.o
+ .debug_aranges
+ 0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_timer.o
+ .debug_ranges 0x00000000 0x38 THUMB Flash Debug/../../obj/efm32_timer.o
+ .debug_line 0x00000000 0x34a THUMB Flash Debug/../../obj/efm32_timer.o
+ .debug_str 0x00000000 0x7c5 THUMB Flash Debug/../../obj/efm32_timer.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_timer.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_timer.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_usart.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_usart.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_BaudrateAsyncSet
0x00000000 0x60 THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_BaudrateCalc
- 0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_usart.o
+ 0x00000000 0x44 THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_BaudrateGet
- 0x00000000 0x2c THUMB Flash Debug/../../obj/efm32_usart.o
+ 0x00000000 0x30 THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_BaudrateSyncSet
0x00000000 0x30 THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_Enable
0x00000000 0xe THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_Reset
0x00000000 0x2c THUMB Flash Debug/../../obj/efm32_usart.o
- .text.USART_InitSync
- 0x00000000 0x4c THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_InitAsync
0x00000000 0x30 THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_InitIrDA
0x00000000 0x50 THUMB Flash Debug/../../obj/efm32_usart.o
+ .text.USART_InitSync
+ 0x00000000 0x4c THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_Rx
0x00000000 0xc THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_RxDouble
@@ -475,36 +789,97 @@ Discarded input sections
.text.USART_RxExt
0x00000000 0xc THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_Tx
- 0x00000000 0xc THUMB Flash Debug/../../obj/efm32_usart.o
+ 0x00000000 0xa THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_TxDouble
- 0x00000000 0xc THUMB Flash Debug/../../obj/efm32_usart.o
+ 0x00000000 0xa THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_TxDoubleExt
0x00000000 0xa THUMB Flash Debug/../../obj/efm32_usart.o
.text.USART_TxExt
- 0x00000000 0xc THUMB Flash Debug/../../obj/efm32_usart.o
+ 0x00000000 0xa THUMB Flash Debug/../../obj/efm32_usart.o
+ .debug_frame 0x00000000 0x198 THUMB Flash Debug/../../obj/efm32_usart.o
+ .debug_info 0x00000000 0xb37 THUMB Flash Debug/../../obj/efm32_usart.o
+ .debug_abbrev 0x00000000 0x235 THUMB Flash Debug/../../obj/efm32_usart.o
+ .debug_loc 0x00000000 0x5b2 THUMB Flash Debug/../../obj/efm32_usart.o
+ .debug_pubnames
+ 0x00000000 0x3e6 THUMB Flash Debug/../../obj/efm32_usart.o
+ .debug_pubtypes
+ 0x00000000 0x21c THUMB Flash Debug/../../obj/efm32_usart.o
+ .debug_aranges
+ 0x00000000 0xa0 THUMB Flash Debug/../../obj/efm32_usart.o
+ .debug_ranges 0x00000000 0x90 THUMB Flash Debug/../../obj/efm32_usart.o
+ .debug_line 0x00000000 0x468 THUMB Flash Debug/../../obj/efm32_usart.o
+ .debug_str 0x00000000 0xa43 THUMB Flash Debug/../../obj/efm32_usart.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_usart.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_usart.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_vcmp.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_vcmp.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_vcmp.o
.text.VCMP_LowPowerRefSet
- 0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_vcmp.o
+ 0x00000000 0x16 THUMB Flash Debug/../../obj/efm32_vcmp.o
.text.VCMP_TriggerSet
0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_vcmp.o
.text.VCMP_Init
- 0x00000000 0xdc THUMB Flash Debug/../../obj/efm32_vcmp.o
+ 0x00000000 0xd8 THUMB Flash Debug/../../obj/efm32_vcmp.o
+ .debug_frame 0x00000000 0x4c THUMB Flash Debug/../../obj/efm32_vcmp.o
+ .debug_info 0x00000000 0x304 THUMB Flash Debug/../../obj/efm32_vcmp.o
+ .debug_abbrev 0x00000000 0x1a6 THUMB Flash Debug/../../obj/efm32_vcmp.o
+ .debug_loc 0x00000000 0x75 THUMB Flash Debug/../../obj/efm32_vcmp.o
+ .debug_pubnames
+ 0x00000000 0x8f THUMB Flash Debug/../../obj/efm32_vcmp.o
+ .debug_pubtypes
+ 0x00000000 0x12c THUMB Flash Debug/../../obj/efm32_vcmp.o
+ .debug_aranges
+ 0x00000000 0x30 THUMB Flash Debug/../../obj/efm32_vcmp.o
+ .debug_ranges 0x00000000 0x38 THUMB Flash Debug/../../obj/efm32_vcmp.o
+ .debug_line 0x00000000 0x305 THUMB Flash Debug/../../obj/efm32_vcmp.o
+ .debug_str 0x00000000 0x41a THUMB Flash Debug/../../obj/efm32_vcmp.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_vcmp.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_vcmp.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_wdog.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_wdog.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_wdog.o
.text.WDOG_Enable
- 0x00000000 0x1c THUMB Flash Debug/../../obj/efm32_wdog.o
+ 0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_wdog.o
.text.WDOG_Feed
0x00000000 0x14 THUMB Flash Debug/../../obj/efm32_wdog.o
.text.WDOG_Lock
0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_wdog.o
.text.WDOG_Init
0x00000000 0x68 THUMB Flash Debug/../../obj/efm32_wdog.o
+ .debug_frame 0x00000000 0x70 THUMB Flash Debug/../../obj/efm32_wdog.o
+ .debug_info 0x00000000 0x389 THUMB Flash Debug/../../obj/efm32_wdog.o
+ .debug_abbrev 0x00000000 0x1ad THUMB Flash Debug/../../obj/efm32_wdog.o
+ .debug_loc 0x00000000 0x175 THUMB Flash Debug/../../obj/efm32_wdog.o
+ .debug_pubnames
+ 0x00000000 0x63 THUMB Flash Debug/../../obj/efm32_wdog.o
+ .debug_pubtypes
+ 0x00000000 0x129 THUMB Flash Debug/../../obj/efm32_wdog.o
+ .debug_aranges
+ 0x00000000 0x38 THUMB Flash Debug/../../obj/efm32_wdog.o
+ .debug_ranges 0x00000000 0x28 THUMB Flash Debug/../../obj/efm32_wdog.o
+ .debug_line 0x00000000 0x32b THUMB Flash Debug/../../obj/efm32_wdog.o
+ .debug_str 0x00000000 0x442 THUMB Flash Debug/../../obj/efm32_wdog.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_wdog.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_wdog.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/hooks.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/hooks.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/hooks.o
+ .debug_info 0x00000000 0x52 THUMB Flash Debug/../../obj/hooks.o
+ .debug_abbrev 0x00000000 0x27 THUMB Flash Debug/../../obj/hooks.o
+ .debug_pubnames
+ 0x00000000 0x12 THUMB Flash Debug/../../obj/hooks.o
+ .debug_pubtypes
+ 0x00000000 0x91 THUMB Flash Debug/../../obj/hooks.o
+ .debug_aranges
+ 0x00000000 0x18 THUMB Flash Debug/../../obj/hooks.o
+ .debug_line 0x00000000 0x1d THUMB Flash Debug/../../obj/hooks.o
+ .debug_str 0x00000000 0x1ec THUMB Flash Debug/../../obj/hooks.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/hooks.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/hooks.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/main.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/main.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/main.o
@@ -551,443 +926,446 @@ Linker script and memory map
0x00000001 . = ASSERT (((__vectors_end__ >= __FLASH_segment_start__) && (__vectors_end__ <= __FLASH_segment_end__)), error: .vectors is too large to fit in FLASH memory segment)
0x000000b8 __init_load_start__ = ALIGN (__vectors_end__, 0x4)
-.init 0x000000b8 0x11c
+.init 0x000000b8 0x124
0x000000b8 __init_start__ = .
*(.init .init.*)
- .init 0x000000b8 0x11c THUMB Flash Debug/../../obj/cstart.o
+ .init 0x000000b8 0x124 THUMB Flash Debug/../../obj/cstart.o
0x000000b8 reset_handler
- 0x00000148 exit
- 0x000001d4 __init_end__ = (__init_start__ + SIZEOF (.init))
- 0x000001d4 __init_load_end__ = __init_end__
+ 0x00000150 exit
+ 0x000001dc __init_end__ = (__init_start__ + SIZEOF (.init))
+ 0x000001dc __init_load_end__ = __init_end__
0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= __FLASH_segment_end__)), error: .init is too large to fit in FLASH memory segment)
- 0x000001d4 __text_load_start__ = ALIGN (__init_end__, 0x4)
+ 0x000001dc __text_load_start__ = ALIGN (__init_end__, 0x4)
-.text 0x000001d4 0x1560
- 0x000001d4 __text_start__ = .
+.text 0x000001dc 0x1494
+ 0x000001dc __text_start__ = .
*(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table .ARM.extab* .gnu.linkonce.armextab.*)
- .glue_7 0x00000000 0x0 linker stubs
- .glue_7t 0x00000000 0x0 linker stubs
+ .glue_7 0x000001dc 0x0 linker stubs
+ .glue_7t 0x000001dc 0x0 linker stubs
.text.UnusedISR
- 0x000001d4 0x18 THUMB Flash Debug/../../obj/vectors.o
- 0x000001d4 UnusedISR
+ 0x000001dc 0x10 THUMB Flash Debug/../../obj/vectors.o
+ 0x000001dc UnusedISR
.text.CpuIrqDisable
0x000001ec 0x4 THUMB Flash Debug/../../obj/cpu_comp.o
0x000001ec CpuIrqDisable
.text.CpuIrqEnable
0x000001f0 0x4 THUMB Flash Debug/../../obj/cpu_comp.o
0x000001f0 CpuIrqEnable
- .text.CpuInit 0x000001f4 0x10 THUMB Flash Debug/../../obj/cpu.o
+ .text.CpuInit 0x000001f4 0x8 THUMB Flash Debug/../../obj/cpu.o
0x000001f4 CpuInit
.text.CpuStartUserProgram
- 0x00000204 0x44 THUMB Flash Debug/../../obj/cpu.o
- 0x00000204 CpuStartUserProgram
+ 0x000001fc 0x4c THUMB Flash Debug/../../obj/cpu.o
+ 0x000001fc CpuStartUserProgram
.text.CpuMemCopy
- 0x00000248 0x24 THUMB Flash Debug/../../obj/cpu.o
+ 0x00000248 0x20 THUMB Flash Debug/../../obj/cpu.o
0x00000248 CpuMemCopy
.text.FlashGetSector
- 0x0000026c 0x3c THUMB Flash Debug/../../obj/flash.o
+ 0x00000268 0x40 THUMB Flash Debug/../../obj/flash.o
.text.FlashWriteBlock
- 0x000002a8 0x58 THUMB Flash Debug/../../obj/flash.o
+ 0x000002a8 0x60 THUMB Flash Debug/../../obj/flash.o
.text.FlashSwitchBlock
- 0x00000300 0x58 THUMB Flash Debug/../../obj/flash.o
+ 0x00000308 0x58 THUMB Flash Debug/../../obj/flash.o
.text.FlashAddToBlock
- 0x00000358 0x94 THUMB Flash Debug/../../obj/flash.o
+ 0x00000360 0x94 THUMB Flash Debug/../../obj/flash.o
.text.FlashInit
- 0x000003ec 0x24 THUMB Flash Debug/../../obj/flash.o
- 0x000003ec FlashInit
+ 0x000003f4 0x20 THUMB Flash Debug/../../obj/flash.o
+ 0x000003f4 FlashInit
.text.FlashWrite
- 0x00000410 0x50 THUMB Flash Debug/../../obj/flash.o
- 0x00000410 FlashWrite
+ 0x00000414 0x54 THUMB Flash Debug/../../obj/flash.o
+ 0x00000414 FlashWrite
.text.FlashErase
- 0x00000460 0x124 THUMB Flash Debug/../../obj/flash.o
- 0x00000460 FlashErase
+ 0x00000468 0x100 THUMB Flash Debug/../../obj/flash.o
+ 0x00000468 FlashErase
.text.FlashWriteChecksum
- 0x00000584 0x48 THUMB Flash Debug/../../obj/flash.o
- 0x00000584 FlashWriteChecksum
+ 0x00000568 0x48 THUMB Flash Debug/../../obj/flash.o
+ 0x00000568 FlashWriteChecksum
.text.FlashVerifyChecksum
- 0x000005cc 0x48 THUMB Flash Debug/../../obj/flash.o
- 0x000005cc FlashVerifyChecksum
+ 0x000005b0 0x46 THUMB Flash Debug/../../obj/flash.o
+ 0x000005b0 FlashVerifyChecksum
+ *fill* 0x000005f6 0x2
.text.FlashDone
- 0x00000614 0x38 THUMB Flash Debug/../../obj/flash.o
- 0x00000614 FlashDone
+ 0x000005f8 0x40 THUMB Flash Debug/../../obj/flash.o
+ 0x000005f8 FlashDone
.text.FlashGetUserProgBaseAddress
- 0x0000064c 0x6 THUMB Flash Debug/../../obj/flash.o
- 0x0000064c FlashGetUserProgBaseAddress
- *fill* 0x00000652 0x2 00
- .text.NvmInit 0x00000654 0x10 THUMB Flash Debug/../../obj/nvm.o
- 0x00000654 NvmInit
+ 0x00000638 0x6 THUMB Flash Debug/../../obj/flash.o
+ 0x00000638 FlashGetUserProgBaseAddress
+ *fill* 0x0000063e 0x2
+ .text.NvmInit 0x00000640 0x8 THUMB Flash Debug/../../obj/nvm.o
+ 0x00000640 NvmInit
.text.NvmWrite
- 0x00000664 0x10 THUMB Flash Debug/../../obj/nvm.o
- 0x00000664 NvmWrite
+ 0x00000648 0x8 THUMB Flash Debug/../../obj/nvm.o
+ 0x00000648 NvmWrite
.text.NvmErase
- 0x00000674 0x10 THUMB Flash Debug/../../obj/nvm.o
- 0x00000674 NvmErase
+ 0x00000650 0x8 THUMB Flash Debug/../../obj/nvm.o
+ 0x00000650 NvmErase
.text.NvmVerifyChecksum
- 0x00000684 0x10 THUMB Flash Debug/../../obj/nvm.o
- 0x00000684 NvmVerifyChecksum
+ 0x00000658 0x8 THUMB Flash Debug/../../obj/nvm.o
+ 0x00000658 NvmVerifyChecksum
.text.NvmGetUserProgBaseAddress
- 0x00000694 0x10 THUMB Flash Debug/../../obj/nvm.o
- 0x00000694 NvmGetUserProgBaseAddress
- .text.NvmDone 0x000006a4 0x18 THUMB Flash Debug/../../obj/nvm.o
- 0x000006a4 NvmDone
+ 0x00000660 0x8 THUMB Flash Debug/../../obj/nvm.o
+ 0x00000660 NvmGetUserProgBaseAddress
+ .text.NvmDone 0x00000668 0x1c THUMB Flash Debug/../../obj/nvm.o
+ 0x00000668 NvmDone
.text.TimerInit
- 0x000006bc 0x20 THUMB Flash Debug/../../obj/timer.o
- 0x000006bc TimerInit
+ 0x00000684 0x20 THUMB Flash Debug/../../obj/timer.o
+ 0x00000684 TimerInit
.text.TimerReset
- 0x000006dc 0xc THUMB Flash Debug/../../obj/timer.o
- 0x000006dc TimerReset
+ 0x000006a4 0xc THUMB Flash Debug/../../obj/timer.o
+ 0x000006a4 TimerReset
.text.TimerUpdate
- 0x000006e8 0x1c THUMB Flash Debug/../../obj/timer.o
- 0x000006e8 TimerUpdate
+ 0x000006b0 0x1c THUMB Flash Debug/../../obj/timer.o
+ 0x000006b0 TimerUpdate
.text.TimerGet
- 0x00000704 0x18 THUMB Flash Debug/../../obj/timer.o
- 0x00000704 TimerGet
+ 0x000006cc 0x14 THUMB Flash Debug/../../obj/timer.o
+ 0x000006cc TimerGet
.text.UartInit
- 0x0000071c 0xb8 THUMB Flash Debug/../../obj/uart.o
- 0x0000071c UartInit
+ 0x000006e0 0xac THUMB Flash Debug/../../obj/uart.o
+ 0x000006e0 UartInit
.text.UartTransmitPacket
- 0x000007d4 0x8c THUMB Flash Debug/../../obj/uart.o
- 0x000007d4 UartTransmitPacket
+ 0x0000078c 0x88 THUMB Flash Debug/../../obj/uart.o
+ 0x0000078c UartTransmitPacket
.text.UartReceivePacket
- 0x00000860 0xb0 THUMB Flash Debug/../../obj/uart.o
- 0x00000860 UartReceivePacket
+ 0x00000814 0x9c THUMB Flash Debug/../../obj/uart.o
+ 0x00000814 UartReceivePacket
.text.AssertFailure
- 0x00000910 0x1c THUMB Flash Debug/../../obj/assert.o
- 0x00000910 AssertFailure
+ 0x000008b0 0xc THUMB Flash Debug/../../obj/assert.o
+ 0x000008b0 AssertFailure
.text.BackDoorCheck
- 0x0000092c 0x40 THUMB Flash Debug/../../obj/backdoor.o
- 0x0000092c BackDoorCheck
+ 0x000008bc 0x44 THUMB Flash Debug/../../obj/backdoor.o
+ 0x000008bc BackDoorCheck
.text.BackDoorInit
- 0x0000096c 0x28 THUMB Flash Debug/../../obj/backdoor.o
- 0x0000096c BackDoorInit
+ 0x00000900 0x28 THUMB Flash Debug/../../obj/backdoor.o
+ 0x00000900 BackDoorInit
.text.BootInit
- 0x00000994 0x38 THUMB Flash Debug/../../obj/boot.o
- 0x00000994 BootInit
+ 0x00000928 0x38 THUMB Flash Debug/../../obj/boot.o
+ 0x00000928 BootInit
.text.BootTask
- 0x000009cc 0x28 THUMB Flash Debug/../../obj/boot.o
- 0x000009cc BootTask
- .text.ComInit 0x000009f4 0x20 THUMB Flash Debug/../../obj/com.o
- 0x000009f4 ComInit
- .text.ComTask 0x00000a14 0x2c THUMB Flash Debug/../../obj/com.o
- 0x00000a14 ComTask
- .text.ComFree 0x00000a40 0x2 THUMB Flash Debug/../../obj/com.o
- 0x00000a40 ComFree
- *fill* 0x00000a42 0x2 00
+ 0x00000960 0x28 THUMB Flash Debug/../../obj/boot.o
+ 0x00000960 BootTask
+ .text.ComInit 0x00000988 0x20 THUMB Flash Debug/../../obj/com.o
+ 0x00000988 ComInit
+ .text.ComTask 0x000009a8 0x30 THUMB Flash Debug/../../obj/com.o
+ 0x000009a8 ComTask
+ .text.ComFree 0x000009d8 0x2 THUMB Flash Debug/../../obj/com.o
+ 0x000009d8 ComFree
+ *fill* 0x000009da 0x2
.text.ComTransmitPacket
- 0x00000a44 0x24 THUMB Flash Debug/../../obj/com.o
- 0x00000a44 ComTransmitPacket
- .text.ComGetActiveInterfaceMaxRxLen
- 0x00000a68 0x14 THUMB Flash Debug/../../obj/com.o
- 0x00000a68 ComGetActiveInterfaceMaxRxLen
+ 0x000009dc 0x24 THUMB Flash Debug/../../obj/com.o
+ 0x000009dc ComTransmitPacket
.text.ComGetActiveInterfaceMaxTxLen
- 0x00000a7c 0x14 THUMB Flash Debug/../../obj/com.o
- 0x00000a7c ComGetActiveInterfaceMaxTxLen
+ 0x00000a00 0x14 THUMB Flash Debug/../../obj/com.o
+ 0x00000a00 ComGetActiveInterfaceMaxTxLen
+ .text.ComGetActiveInterfaceMaxRxLen
+ 0x00000a14 0x8 THUMB Flash Debug/../../obj/com.o
+ 0x00000a14 ComGetActiveInterfaceMaxRxLen
.text.ComIsConnected
- 0x00000a90 0x10 THUMB Flash Debug/../../obj/com.o
- 0x00000a90 ComIsConnected
- .text.CopInit 0x00000aa0 0x2 THUMB Flash Debug/../../obj/cop.o
- 0x00000aa0 CopInit
+ 0x00000a1c 0x8 THUMB Flash Debug/../../obj/com.o
+ 0x00000a1c ComIsConnected
+ .text.CopInit 0x00000a24 0x2 THUMB Flash Debug/../../obj/cop.o
+ 0x00000a24 CopInit
.text.CopService
- 0x00000aa2 0x2 THUMB Flash Debug/../../obj/cop.o
- 0x00000aa2 CopService
+ 0x00000a26 0x2 THUMB Flash Debug/../../obj/cop.o
+ 0x00000a26 CopService
.text.XcpSetCtoError
- 0x00000aa4 0x14 THUMB Flash Debug/../../obj/xcp.o
- .text.XcpInit 0x00000ab8 0x1c THUMB Flash Debug/../../obj/xcp.o
- 0x00000ab8 XcpInit
+ 0x00000a28 0x14 THUMB Flash Debug/../../obj/xcp.o
+ .text.XcpInit 0x00000a3c 0x1c THUMB Flash Debug/../../obj/xcp.o
+ 0x00000a3c XcpInit
.text.XcpIsConnected
- 0x00000ad4 0x10 THUMB Flash Debug/../../obj/xcp.o
- 0x00000ad4 XcpIsConnected
+ 0x00000a58 0x10 THUMB Flash Debug/../../obj/xcp.o
+ 0x00000a58 XcpIsConnected
.text.XcpPacketTransmitted
- 0x00000ae4 0x10 THUMB Flash Debug/../../obj/xcp.o
- 0x00000ae4 XcpPacketTransmitted
+ 0x00000a68 0x10 THUMB Flash Debug/../../obj/xcp.o
+ 0x00000a68 XcpPacketTransmitted
.text.XcpPacketReceived
- 0x00000af4 0x240 THUMB Flash Debug/../../obj/xcp.o
- 0x00000af4 XcpPacketReceived
+ 0x00000a78 0x240 THUMB Flash Debug/../../obj/xcp.o
+ 0x00000a78 XcpPacketReceived
.text.SystemHFClockGet
- 0x00000d34 0x98 THUMB Flash Debug/../../obj/system_efm32.o
- 0x00000d34 SystemHFClockGet
+ 0x00000cb8 0x94 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x00000cb8 SystemHFClockGet
.text.SystemCoreClockGet
- 0x00000dcc 0x28 THUMB Flash Debug/../../obj/system_efm32.o
- 0x00000dcc SystemCoreClockGet
+ 0x00000d4c 0x24 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x00000d4c SystemCoreClockGet
.text.SystemInit
- 0x00000df4 0x2 THUMB Flash Debug/../../obj/system_efm32.o
- 0x00000df4 SystemInit
+ 0x00000d70 0x2 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x00000d70 SystemInit
.text.SystemLFRCOClockGet
- 0x00000df6 0x6 THUMB Flash Debug/../../obj/system_efm32.o
- 0x00000df6 SystemLFRCOClockGet
+ 0x00000d72 0x6 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x00000d72 SystemLFRCOClockGet
.text.SystemLFXOClockGet
- 0x00000dfc 0xc THUMB Flash Debug/../../obj/system_efm32.o
- 0x00000dfc SystemLFXOClockGet
+ 0x00000d78 0xc THUMB Flash Debug/../../obj/system_efm32.o
+ 0x00000d78 SystemLFXOClockGet
.text.CMU_FlashWaitStateMax
- 0x00000e08 0x30 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00000d84 0x30 THUMB Flash Debug/../../obj/efm32_cmu.o
.text.CMU_FlashWaitStateControl
- 0x00000e38 0x54 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00000db4 0x54 THUMB Flash Debug/../../obj/efm32_cmu.o
.text.CMU_Sync
- 0x00000e8c 0x14 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00000e08 0x14 THUMB Flash Debug/../../obj/efm32_cmu.o
.text.CMU_LFClkGet
- 0x00000ea0 0x48 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00000e1c 0x44 THUMB Flash Debug/../../obj/efm32_cmu.o
.text.CMU_ClockDivSet
- 0x00000ee8 0x12c THUMB Flash Debug/../../obj/efm32_cmu.o
- 0x00000ee8 CMU_ClockDivSet
+ 0x00000e60 0x12c THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00000e60 CMU_ClockDivSet
.text.CMU_ClockEnable
- 0x00001014 0x70 THUMB Flash Debug/../../obj/efm32_cmu.o
- 0x00001014 CMU_ClockEnable
+ 0x00000f8c 0x70 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00000f8c CMU_ClockEnable
.text.CMU_ClockSelectGet
- 0x00001084 0x6c THUMB Flash Debug/../../obj/efm32_cmu.o
- 0x00001084 CMU_ClockSelectGet
+ 0x00000ffc 0x68 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00000ffc CMU_ClockSelectGet
.text.CMU_ClockFreqGet
- 0x000010f0 0x13c THUMB Flash Debug/../../obj/efm32_cmu.o
- 0x000010f0 CMU_ClockFreqGet
+ 0x00001064 0x124 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00001064 CMU_ClockFreqGet
.text.CMU_OscillatorEnable
- 0x0000122c 0x54 THUMB Flash Debug/../../obj/efm32_cmu.o
- 0x0000122c CMU_OscillatorEnable
+ 0x00001188 0x54 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00001188 CMU_OscillatorEnable
.text.CMU_ClockSelectSet
- 0x00001280 0xc8 THUMB Flash Debug/../../obj/efm32_cmu.o
- 0x00001280 CMU_ClockSelectSet
+ 0x000011dc 0xc8 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x000011dc CMU_ClockSelectSet
.text.EMU_UpdateOscConfig
- 0x00001348 0x14 THUMB Flash Debug/../../obj/efm32_emu.o
- 0x00001348 EMU_UpdateOscConfig
+ 0x000012a4 0x14 THUMB Flash Debug/../../obj/efm32_emu.o
+ 0x000012a4 EMU_UpdateOscConfig
.text.GPIO_DriveModeSet
- 0x0000135c 0x18 THUMB Flash Debug/../../obj/efm32_gpio.o
- 0x0000135c GPIO_DriveModeSet
+ 0x000012b8 0x18 THUMB Flash Debug/../../obj/efm32_gpio.o
+ 0x000012b8 GPIO_DriveModeSet
.text.GPIO_PinModeSet
- 0x00001374 0x80 THUMB Flash Debug/../../obj/efm32_gpio.o
- 0x00001374 GPIO_PinModeSet
+ 0x000012d0 0x7a THUMB Flash Debug/../../obj/efm32_gpio.o
+ 0x000012d0 GPIO_PinModeSet
.text.LEUART_Sync
- 0x000013f4 0xe THUMB Flash Debug/../../obj/efm32_leuart.o
- *fill* 0x00001402 0x2 00
+ 0x0000134a 0xe THUMB Flash Debug/../../obj/efm32_leuart.o
.text.LEUART_BaudrateSet
- 0x00001404 0x4c THUMB Flash Debug/../../obj/efm32_leuart.o
- 0x00001404 LEUART_BaudrateSet
+ 0x00001358 0x4c THUMB Flash Debug/../../obj/efm32_leuart.o
+ 0x00001358 LEUART_BaudrateSet
.text.LEUART_Enable
- 0x00001450 0x1c THUMB Flash Debug/../../obj/efm32_leuart.o
- 0x00001450 LEUART_Enable
- .text.LEUART_FreezeEnable
- 0x0000146c 0x14 THUMB Flash Debug/../../obj/efm32_leuart.o
- 0x0000146c LEUART_FreezeEnable
+ 0x000013a4 0x1c THUMB Flash Debug/../../obj/efm32_leuart.o
+ 0x000013a4 LEUART_Enable
.text.LEUART_Init
- 0x00001480 0x50 THUMB Flash Debug/../../obj/efm32_leuart.o
- 0x00001480 LEUART_Init
+ 0x000013c0 0x48 THUMB Flash Debug/../../obj/efm32_leuart.o
+ 0x000013c0 LEUART_Init
.text.LEUART_Rx
- 0x000014d0 0xc THUMB Flash Debug/../../obj/efm32_leuart.o
- 0x000014d0 LEUART_Rx
+ 0x00001408 0xc THUMB Flash Debug/../../obj/efm32_leuart.o
+ 0x00001408 LEUART_Rx
.text.LEUART_Tx
- 0x000014dc 0x1c THUMB Flash Debug/../../obj/efm32_leuart.o
- 0x000014dc LEUART_Tx
+ 0x00001414 0x1c THUMB Flash Debug/../../obj/efm32_leuart.o
+ 0x00001414 LEUART_Tx
.text.MSC_Init
- 0x000014f8 0x20 THUMB Flash Debug/../../obj/efm32_msc.o
- 0x000014f8 MSC_Init
+ 0x00001430 0x20 THUMB Flash Debug/../../obj/efm32_msc.o
+ 0x00001430 MSC_Init
.text.MSC_Deinit
- 0x00001518 0x1c THUMB Flash Debug/../../obj/efm32_msc.o
- 0x00001518 MSC_Deinit
+ 0x00001450 0x1c THUMB Flash Debug/../../obj/efm32_msc.o
+ 0x00001450 MSC_Deinit
.text.SYSTEM_ChipRevisionGet
- 0x00001534 0x20 THUMB Flash Debug/../../obj/efm32_system.o
- 0x00001534 SYSTEM_ChipRevisionGet
+ 0x0000146c 0x20 THUMB Flash Debug/../../obj/efm32_system.o
+ 0x0000146c SYSTEM_ChipRevisionGet
.text.startup.main
- 0x00001554 0x1e0 THUMB Flash Debug/../../obj/main.o
- 0x00001554 main
- 0x00001734 __text_end__ = (__text_start__ + SIZEOF (.text))
- 0x00001734 __text_load_end__ = __text_end__
+ 0x0000148c 0x1e4 THUMB Flash Debug/../../obj/main.o
+ 0x0000148c main
+ 0x00001670 __text_end__ = (__text_start__ + SIZEOF (.text))
+ 0x00001670 __text_load_end__ = __text_end__
.vfp11_veneer 0x00000000 0x0
.vfp11_veneer 0x00000000 0x0 linker stubs
.v4_bx 0x00000000 0x0
.v4_bx 0x00000000 0x0 linker stubs
- 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= __FLASH_segment_end__)), error: .text is too large to fit in FLASH memory segment)
- 0x00001734 __dtors_load_start__ = ALIGN (__text_end__, 0x4)
-.dtors 0x00001734 0x0
- 0x00001734 __dtors_start__ = .
+.iplt 0x00000000 0x0
+ .iplt 0x00000000 0x0 THUMB Flash Debug/../../obj/cstart.o
+ 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= __FLASH_segment_end__)), error: .text is too large to fit in FLASH memory segment)
+ 0x00001670 __dtors_load_start__ = ALIGN (__text_end__, 0x4)
+
+.dtors 0x00001670 0x0
+ 0x00001670 __dtors_start__ = .
*(SORT(.dtors.*))
*(.dtors)
*(.fini_array .fini_array.*)
- 0x00001734 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
- 0x00001734 __dtors_load_end__ = __dtors_end__
+ 0x00001670 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
+ 0x00001670 __dtors_load_end__ = __dtors_end__
0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= __FLASH_segment_end__)), error: .dtors is too large to fit in FLASH memory segment)
- 0x00001734 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
+ 0x00001670 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
-.ctors 0x00001734 0x0
- 0x00001734 __ctors_start__ = .
+.ctors 0x00001670 0x0
+ 0x00001670 __ctors_start__ = .
*(SORT(.ctors.*))
*(.ctors)
*(.init_array .init_array.*)
- 0x00001734 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
- 0x00001734 __ctors_load_end__ = __ctors_end__
+ 0x00001670 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
+ 0x00001670 __ctors_load_end__ = __ctors_end__
0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= __FLASH_segment_end__)), error: .ctors is too large to fit in FLASH memory segment)
- 0x00001734 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
+ 0x00001670 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
-.rodata 0x00001734 0x1ef
- 0x00001734 __rodata_start__ = .
+.rodata 0x00001670 0x1e7
+ 0x00001670 __rodata_start__ = .
*(.rodata .rodata.* .gnu.linkonce.r.*)
.rodata.str1.1
- 0x00001734 0x92 THUMB Flash Debug/../../obj/vectors.o
- *fill* 0x000017c6 0x2 00
+ 0x00001670 0x92 THUMB Flash Debug/../../obj/vectors.o
+ *fill* 0x00001702 0x2
.rodata.flashLayout
- 0x000017c8 0xb4 THUMB Flash Debug/../../obj/flash.o
- .rodata 0x0000187c 0x18 THUMB Flash Debug/../../obj/uart.o
+ 0x00001704 0xb4 THUMB Flash Debug/../../obj/flash.o
+ .rodata 0x000017b8 0x10 THUMB Flash Debug/../../obj/uart.o
.rodata.str1.1
- 0x00001894 0x84 THUMB Flash Debug/../../obj/uart.o
+ 0x000017c8 0x84 THUMB Flash Debug/../../obj/uart.o
.rodata.xcpStationId
- 0x00001918 0x8 THUMB Flash Debug/../../obj/xcp.o
- .rodata.CSWTCH.5
- 0x00001920 0x3 THUMB Flash Debug/../../obj/efm32_cmu.o
- 0x00001923 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
- 0x00001923 __rodata_load_end__ = __rodata_end__
+ 0x0000184c 0x8 THUMB Flash Debug/../../obj/xcp.o
+ .rodata.CSWTCH.17
+ 0x00001854 0x3 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00001857 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
+ 0x00001857 __rodata_load_end__ = __rodata_end__
0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= __FLASH_segment_end__)), error: .rodata is too large to fit in FLASH memory segment)
- 0x00001924 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4)
+ 0x00001858 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4)
-.ARM.exidx 0x00001924 0x0
- 0x00001924 __ARM.exidx_start__ = .
- 0x00001924 __exidx_start = __ARM.exidx_start__
+.ARM.exidx 0x00001858 0x0
+ 0x00001858 __ARM.exidx_start__ = .
+ 0x00001858 __exidx_start = __ARM.exidx_start__
*(.ARM.exidx .ARM.exidx.*)
- 0x00001924 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx))
- 0x00001924 __exidx_end = __ARM.exidx_end__
- 0x00001924 __ARM.exidx_load_end__ = __ARM.exidx_end__
+ 0x00001858 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx))
+ 0x00001858 __exidx_end = __ARM.exidx_end__
+ 0x00001858 __ARM.exidx_load_end__ = __ARM.exidx_end__
0x00000001 . = ASSERT (((__ARM.exidx_end__ >= __FLASH_segment_start__) && (__ARM.exidx_end__ <= __FLASH_segment_end__)), error: .ARM.exidx is too large to fit in FLASH memory segment)
- 0x00001924 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4)
+ 0x00001858 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4)
-.fast 0x20000000 0x138 load address 0x00001924
+.fast 0x20000000 0x120 load address 0x00001858
0x20000000 __fast_start__ = .
*(.fast .fast.*)
- .fast 0x20000000 0x138 THUMB Flash Debug/../../obj/efm32_msc.o
- 0x20000000 MSC_ErasePage
- 0x20000078 MSC_WriteWord
- 0x20000138 __fast_end__ = (__fast_start__ + SIZEOF (.fast))
- 0x00001a5c __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
+ .fast 0x20000000 0x120 THUMB Flash Debug/../../obj/efm32_msc.o
+ 0x20000000 MSC_WriteWord
+ 0x200000ac MSC_ErasePage
+ 0x20000120 __fast_end__ = (__fast_start__ + SIZEOF (.fast))
+ 0x00001978 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
+
+.rel.dyn 0x00000000 0x0
+ .rel.iplt 0x00000000 0x0 THUMB Flash Debug/../../obj/cstart.o
0x00000001 . = ASSERT (((__fast_load_end__ >= __FLASH_segment_start__) && (__fast_load_end__ <= __FLASH_segment_end__)), error: .fast is too large to fit in FLASH memory segment)
-.fast_run 0x20000000 0x138 load address 0x00001924
+.fast_run 0x20000000 0x120 load address 0x00001858
0x20000000 __fast_run_start__ = .
- 0x20000138 . = MAX ((__fast_run_start__ + SIZEOF (.fast)), .)
- *fill* 0x20000000 0x138 00
- 0x20000138 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run))
- 0x20000138 __fast_run_load_end__ = __fast_run_end__
+ 0x20000120 . = MAX ((__fast_run_start__ + SIZEOF (.fast)), .)
+ *fill* 0x20000000 0x120
+ 0x20000120 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run))
+ 0x20000120 __fast_run_load_end__ = __fast_run_end__
0x00000001 . = ASSERT (((__fast_run_end__ >= __SRAM_segment_start__) && (__fast_run_end__ <= __SRAM_segment_end__)), error: .fast_run is too large to fit in SRAM memory segment)
- 0x00001a5c __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4)
+ 0x00001978 __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4)
-.data 0x20000138 0xc load address 0x00001a5c
- 0x20000138 __data_start__ = .
+.data 0x20000120 0xc load address 0x00001978
+ 0x20000120 __data_start__ = .
*(.data .data.* .gnu.linkonce.d.*)
.data.comActiveInterface
- 0x20000138 0x4 THUMB Flash Debug/../../obj/com.o
+ 0x20000120 0x1 THUMB Flash Debug/../../obj/com.o
+ *fill* 0x20000121 0x3
.data.SystemLFXOClock
- 0x2000013c 0x4 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x20000124 0x4 THUMB Flash Debug/../../obj/system_efm32.o
.data.SystemHFXOClock
- 0x20000140 0x4 THUMB Flash Debug/../../obj/system_efm32.o
- 0x20000144 __data_end__ = (__data_start__ + SIZEOF (.data))
- 0x00001a68 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+ 0x20000128 0x4 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x2000012c __data_end__ = (__data_start__ + SIZEOF (.data))
+ 0x00001984 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+
+.igot.plt 0x00000000 0x0
+ .igot.plt 0x00000000 0x0 THUMB Flash Debug/../../obj/cstart.o
0x00000001 . = ASSERT (((__data_load_end__ >= __FLASH_segment_start__) && (__data_load_end__ <= __FLASH_segment_end__)), error: .data is too large to fit in FLASH memory segment)
-.data_run 0x20000138 0xc load address 0x00001a5c
- 0x20000138 __data_run_start__ = .
- 0x20000144 . = MAX ((__data_run_start__ + SIZEOF (.data)), .)
- *fill* 0x20000138 0xc 00
- 0x20000144 __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run))
- 0x20000144 __data_run_load_end__ = __data_run_end__
+.data_run 0x20000120 0xc load address 0x00001978
+ 0x20000120 __data_run_start__ = .
+ 0x2000012c . = MAX ((__data_run_start__ + SIZEOF (.data)), .)
+ *fill* 0x20000120 0xc
+ 0x2000012c __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run))
+ 0x2000012c __data_run_load_end__ = __data_run_end__
0x00000001 . = ASSERT (((__data_run_end__ >= __SRAM_segment_start__) && (__data_run_end__ <= __SRAM_segment_end__)), error: .data_run is too large to fit in SRAM memory segment)
- 0x20000144 __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
+ 0x2000012c __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
-.bss 0x20000144 0x4f6
- 0x20000144 __bss_start__ = .
+.bss 0x2000012c 0x4ee
+ 0x2000012c __bss_start__ = .
*(.bss .bss.* .gnu.linkonce.b.*)
.bss.bootBlockInfo
- 0x20000144 0x204 THUMB Flash Debug/../../obj/flash.o
+ 0x2000012c 0x204 THUMB Flash Debug/../../obj/flash.o
.bss.blockInfo
- 0x20000348 0x204 THUMB Flash Debug/../../obj/flash.o
+ 0x20000330 0x204 THUMB Flash Debug/../../obj/flash.o
.bss.millisecond_counter
- 0x2000054c 0x4 THUMB Flash Debug/../../obj/timer.o
- .bss.xcpCtoRxStartTime.2187
- 0x20000550 0x4 THUMB Flash Debug/../../obj/uart.o
- .bss.xcpCtoRxLength.2185
- 0x20000554 0x1 THUMB Flash Debug/../../obj/uart.o
- .bss.xcpCtoRxInProgress.2186
- 0x20000555 0x1 THUMB Flash Debug/../../obj/uart.o
- .bss.xcpCtoReqPacket.2184
- 0x20000556 0x41 THUMB Flash Debug/../../obj/uart.o
- *fill* 0x20000597 0x1 00
- .bss.assert_failure_file
- 0x20000598 0x4 THUMB Flash Debug/../../obj/assert.o
- .bss.assert_failure_line
- 0x2000059c 0x4 THUMB Flash Debug/../../obj/assert.o
+ 0x20000534 0x4 THUMB Flash Debug/../../obj/timer.o
+ .bss.xcpCtoRxInProgress.5094
+ 0x20000538 0x1 THUMB Flash Debug/../../obj/uart.o
+ *fill* 0x20000539 0x3
+ .bss.xcpCtoRxStartTime.5095
+ 0x2000053c 0x4 THUMB Flash Debug/../../obj/uart.o
+ .bss.xcpCtoReqPacket.5092
+ 0x20000540 0x41 THUMB Flash Debug/../../obj/uart.o
+ .bss.xcpCtoRxLength.5093
+ 0x20000581 0x1 THUMB Flash Debug/../../obj/uart.o
.bss.backdoorOpen
- 0x200005a0 0x1 THUMB Flash Debug/../../obj/backdoor.o
- *fill* 0x200005a1 0x3 00
+ 0x20000582 0x1 THUMB Flash Debug/../../obj/backdoor.o
+ *fill* 0x20000583 0x1
.bss.backdoorOpenTime
- 0x200005a4 0x4 THUMB Flash Debug/../../obj/backdoor.o
- .bss.xcpCtoReqPacket.884
- 0x200005a8 0x40 THUMB Flash Debug/../../obj/com.o
- .bss.xcpInfo 0x200005e8 0x4c THUMB Flash Debug/../../obj/xcp.o
+ 0x20000584 0x4 THUMB Flash Debug/../../obj/backdoor.o
+ .bss.xcpCtoReqPacket.3788
+ 0x20000588 0x40 THUMB Flash Debug/../../obj/com.o
+ .bss.xcpInfo 0x200005c8 0x4c THUMB Flash Debug/../../obj/xcp.o
.bss.SystemCoreClock
- 0x20000634 0x4 THUMB Flash Debug/../../obj/system_efm32.o
- 0x20000634 SystemCoreClock
+ 0x20000614 0x4 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x20000614 SystemCoreClock
.bss.cmuStatus
- 0x20000638 0x2 THUMB Flash Debug/../../obj/efm32_emu.o
+ 0x20000618 0x2 THUMB Flash Debug/../../obj/efm32_emu.o
*(COMMON)
- 0x2000063a __bss_end__ = (__bss_start__ + SIZEOF (.bss))
- 0x2000063a __bss_load_end__ = __bss_end__
+ 0x2000061a __bss_end__ = (__bss_start__ + SIZEOF (.bss))
+ 0x2000061a __bss_load_end__ = __bss_end__
0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= __SRAM_segment_end__)), error: .bss is too large to fit in SRAM memory segment)
- 0x2000063c __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
+ 0x2000061c __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
-.non_init 0x2000063c 0x0
- 0x2000063c __non_init_start__ = .
+.non_init 0x2000061c 0x0
+ 0x2000061c __non_init_start__ = .
*(.non_init .non_init.*)
- 0x2000063c __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
- 0x2000063c __non_init_load_end__ = __non_init_end__
+ 0x2000061c __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
+ 0x2000061c __non_init_load_end__ = __non_init_end__
0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= __SRAM_segment_end__)), error: .non_init is too large to fit in SRAM memory segment)
- 0x2000063c __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
+ 0x2000061c __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
-.heap 0x2000063c 0x80
- 0x2000063c __heap_start__ = .
+.heap 0x2000061c 0x80
+ 0x2000061c __heap_start__ = .
*(.heap .heap.*)
- 0x200006bc . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
- *fill* 0x2000063c 0x80 00
- 0x200006bc __heap_end__ = (__heap_start__ + SIZEOF (.heap))
- 0x200006bc __heap_load_end__ = __heap_end__
+ 0x2000069c . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
+ *fill* 0x2000061c 0x80
+ 0x2000069c __heap_end__ = (__heap_start__ + SIZEOF (.heap))
+ 0x2000069c __heap_load_end__ = __heap_end__
0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= __SRAM_segment_end__)), error: .heap is too large to fit in SRAM memory segment)
- 0x200006bc __stack_load_start__ = ALIGN (__heap_end__, 0x4)
+ 0x2000069c __stack_load_start__ = ALIGN (__heap_end__, 0x4)
-.stack 0x200006bc 0x100
- 0x200006bc __stack_start__ = .
+.stack 0x2000069c 0x100
+ 0x2000069c __stack_start__ = .
*(.stack .stack.*)
- 0x200007bc . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
- *fill* 0x200006bc 0x100 00
- 0x200007bc __stack_end__ = (__stack_start__ + SIZEOF (.stack))
- 0x200007bc __stack_load_end__ = __stack_end__
+ 0x2000079c . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
+ *fill* 0x2000069c 0x100
+ 0x2000079c __stack_end__ = (__stack_start__ + SIZEOF (.stack))
+ 0x2000079c __stack_load_end__ = __stack_end__
0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= __SRAM_segment_end__)), error: .stack is too large to fit in SRAM memory segment)
- 0x200007bc __stack_process_load_start__ = ALIGN (__stack_end__, 0x4)
+ 0x2000079c __stack_process_load_start__ = ALIGN (__stack_end__, 0x4)
-.stack_process 0x200007bc 0x0
- 0x200007bc __stack_process_start__ = .
+.stack_process 0x2000079c 0x0
+ 0x2000079c __stack_process_start__ = .
*(.stack_process .stack_process.*)
- 0x200007bc . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4)
- 0x200007bc __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process))
- 0x200007bc __stack_process_load_end__ = __stack_process_end__
+ 0x2000079c . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4)
+ 0x2000079c __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process))
+ 0x2000079c __stack_process_load_end__ = __stack_process_end__
0x00000001 . = ASSERT (((__stack_process_end__ >= __SRAM_segment_start__) && (__stack_process_end__ <= __SRAM_segment_end__)), error: .stack_process is too large to fit in SRAM memory segment)
- 0x200007bc __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4)
+ 0x2000079c __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4)
-.tbss 0x200007bc 0x0
- 0x200007bc __tbss_start__ = .
+.tbss 0x2000079c 0x0
+ 0x2000079c __tbss_start__ = .
*(.tbss .tbss.*)
- 0x200007bc __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss))
- 0x200007bc __tbss_load_end__ = __tbss_end__
+ 0x2000079c __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss))
+ 0x2000079c __tbss_load_end__ = __tbss_end__
0x00000001 . = ASSERT (((__tbss_end__ >= __SRAM_segment_start__) && (__tbss_end__ <= __SRAM_segment_end__)), error: .tbss is too large to fit in SRAM memory segment)
- 0x00001a68 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
+ 0x00001984 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
-.tdata 0x200007bc 0x0 load address 0x00001a68
- 0x200007bc __tdata_start__ = .
+.tdata 0x2000079c 0x0 load address 0x00001984
+ 0x2000079c __tdata_start__ = .
*(.tdata .tdata.*)
- 0x200007bc __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata))
- 0x00001a68 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata))
- 0x00001a68 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata))
+ 0x2000079c __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata))
+ 0x00001984 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata))
+ 0x00001984 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata))
0x00000001 . = ASSERT (((__tdata_load_end__ >= __FLASH_segment_start__) && (__tdata_load_end__ <= __FLASH_segment_end__)), error: .tdata is too large to fit in FLASH memory segment)
-.tdata_run 0x200007bc 0x0
- 0x200007bc __tdata_run_start__ = .
- 0x200007bc . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .)
- 0x200007bc __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run))
- 0x200007bc __tdata_run_load_end__ = __tdata_run_end__
- 0x200007bc __SRAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run))
+.tdata_run 0x2000079c 0x0
+ 0x2000079c __tdata_run_start__ = .
+ 0x2000079c . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .)
+ 0x2000079c __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run))
+ 0x2000079c __tdata_run_load_end__ = __tdata_run_end__
+ 0x2000079c __SRAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run))
0x00000001 . = ASSERT (((__tdata_run_end__ >= __SRAM_segment_start__) && (__tdata_run_end__ <= __SRAM_segment_end__)), error: .tdata_run is too large to fit in SRAM memory segment)
START GROUP
LOAD THUMB Flash Debug/../../obj/cstart.o
@@ -1041,298 +1419,149 @@ END GROUP
OUTPUT(THUMB Flash Debug/../../bin/openbtl_olimex_efm32g880.elf elf32-littlearm)
.ARM.attributes
- 0x00000000 0x10
+ 0x00000000 0x2f
.ARM.attributes
- 0x00000000 0x10 THUMB Flash Debug/../../obj/cstart.o
+ 0x00000000 0x21 THUMB Flash Debug/../../obj/cstart.o
.ARM.attributes
- 0x00000010 0x10 THUMB Flash Debug/../../obj/vectors.o
+ 0x00000021 0x33 THUMB Flash Debug/../../obj/vectors.o
.ARM.attributes
- 0x00000020 0x10 THUMB Flash Debug/../../obj/cpu_comp.o
+ 0x00000054 0x33 THUMB Flash Debug/../../obj/cpu_comp.o
.ARM.attributes
- 0x00000030 0x10 THUMB Flash Debug/../../obj/cpu.o
+ 0x00000087 0x33 THUMB Flash Debug/../../obj/cpu.o
.ARM.attributes
- 0x00000040 0x10 THUMB Flash Debug/../../obj/flash.o
+ 0x000000ba 0x33 THUMB Flash Debug/../../obj/flash.o
.ARM.attributes
- 0x00000050 0x10 THUMB Flash Debug/../../obj/nvm.o
+ 0x000000ed 0x33 THUMB Flash Debug/../../obj/nvm.o
.ARM.attributes
- 0x00000060 0x10 THUMB Flash Debug/../../obj/timer.o
+ 0x00000120 0x33 THUMB Flash Debug/../../obj/timer.o
.ARM.attributes
- 0x00000070 0x10 THUMB Flash Debug/../../obj/uart.o
+ 0x00000153 0x33 THUMB Flash Debug/../../obj/uart.o
.ARM.attributes
- 0x00000080 0x10 THUMB Flash Debug/../../obj/assert.o
+ 0x00000186 0x33 THUMB Flash Debug/../../obj/assert.o
.ARM.attributes
- 0x00000090 0x10 THUMB Flash Debug/../../obj/backdoor.o
+ 0x000001b9 0x33 THUMB Flash Debug/../../obj/backdoor.o
.ARM.attributes
- 0x000000a0 0x10 THUMB Flash Debug/../../obj/boot.o
+ 0x000001ec 0x33 THUMB Flash Debug/../../obj/boot.o
.ARM.attributes
- 0x000000b0 0x10 THUMB Flash Debug/../../obj/com.o
+ 0x0000021f 0x33 THUMB Flash Debug/../../obj/com.o
.ARM.attributes
- 0x000000c0 0x10 THUMB Flash Debug/../../obj/cop.o
+ 0x00000252 0x33 THUMB Flash Debug/../../obj/cop.o
.ARM.attributes
- 0x000000d0 0x10 THUMB Flash Debug/../../obj/xcp.o
+ 0x00000285 0x33 THUMB Flash Debug/../../obj/xcp.o
.ARM.attributes
- 0x000000e0 0x10 THUMB Flash Debug/../../obj/core_cm3.o
+ 0x000002b8 0x33 THUMB Flash Debug/../../obj/system_efm32.o
.ARM.attributes
- 0x000000f0 0x10 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x000002eb 0x33 THUMB Flash Debug/../../obj/efm32_cmu.o
.ARM.attributes
- 0x00000100 0x10 THUMB Flash Debug/../../obj/efm32_acmp.o
+ 0x0000031e 0x33 THUMB Flash Debug/../../obj/efm32_emu.o
.ARM.attributes
- 0x00000110 0x10 THUMB Flash Debug/../../obj/efm32_adc.o
+ 0x00000351 0x33 THUMB Flash Debug/../../obj/efm32_gpio.o
.ARM.attributes
- 0x00000120 0x10 THUMB Flash Debug/../../obj/efm32_aes.o
+ 0x00000384 0x33 THUMB Flash Debug/../../obj/efm32_leuart.o
.ARM.attributes
- 0x00000130 0x10 THUMB Flash Debug/../../obj/efm32_assert.o
+ 0x000003b7 0x33 THUMB Flash Debug/../../obj/efm32_msc.o
.ARM.attributes
- 0x00000140 0x10 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x000003ea 0x33 THUMB Flash Debug/../../obj/efm32_system.o
.ARM.attributes
- 0x00000150 0x10 THUMB Flash Debug/../../obj/efm32_dac.o
- .ARM.attributes
- 0x00000160 0x10 THUMB Flash Debug/../../obj/efm32_dbg.o
- .ARM.attributes
- 0x00000170 0x10 THUMB Flash Debug/../../obj/efm32_dma.o
- .ARM.attributes
- 0x00000180 0x10 THUMB Flash Debug/../../obj/efm32_ebi.o
- .ARM.attributes
- 0x00000190 0x10 THUMB Flash Debug/../../obj/efm32_emu.o
- .ARM.attributes
- 0x000001a0 0x10 THUMB Flash Debug/../../obj/efm32_gpio.o
- .ARM.attributes
- 0x000001b0 0x10 THUMB Flash Debug/../../obj/efm32_i2c.o
- .ARM.attributes
- 0x000001c0 0x10 THUMB Flash Debug/../../obj/efm32_int.o
- .ARM.attributes
- 0x000001d0 0x10 THUMB Flash Debug/../../obj/efm32_lcd.o
- .ARM.attributes
- 0x000001e0 0x10 THUMB Flash Debug/../../obj/efm32_lesense.o
- .ARM.attributes
- 0x000001f0 0x10 THUMB Flash Debug/../../obj/efm32_letimer.o
- .ARM.attributes
- 0x00000200 0x10 THUMB Flash Debug/../../obj/efm32_leuart.o
- .ARM.attributes
- 0x00000210 0x10 THUMB Flash Debug/../../obj/efm32_mpu.o
- .ARM.attributes
- 0x00000220 0x10 THUMB Flash Debug/../../obj/efm32_msc.o
- .ARM.attributes
- 0x00000230 0x10 THUMB Flash Debug/../../obj/efm32_opamp.o
- .ARM.attributes
- 0x00000240 0x10 THUMB Flash Debug/../../obj/efm32_pcnt.o
- .ARM.attributes
- 0x00000250 0x10 THUMB Flash Debug/../../obj/efm32_prs.o
- .ARM.attributes
- 0x00000260 0x10 THUMB Flash Debug/../../obj/efm32_rmu.o
- .ARM.attributes
- 0x00000270 0x10 THUMB Flash Debug/../../obj/efm32_rtc.o
- .ARM.attributes
- 0x00000280 0x10 THUMB Flash Debug/../../obj/efm32_system.o
- .ARM.attributes
- 0x00000290 0x10 THUMB Flash Debug/../../obj/efm32_timer.o
- .ARM.attributes
- 0x000002a0 0x10 THUMB Flash Debug/../../obj/efm32_usart.o
- .ARM.attributes
- 0x000002b0 0x10 THUMB Flash Debug/../../obj/efm32_vcmp.o
- .ARM.attributes
- 0x000002c0 0x10 THUMB Flash Debug/../../obj/efm32_wdog.o
- .ARM.attributes
- 0x000002d0 0x10 THUMB Flash Debug/../../obj/hooks.o
- .ARM.attributes
- 0x000002e0 0x10 THUMB Flash Debug/../../obj/main.o
+ 0x0000041d 0x33 THUMB Flash Debug/../../obj/main.o
-.comment 0x00000000 0x4e
- .comment 0x00000000 0x4e THUMB Flash Debug/../../obj/vectors.o
- 0x4f (size before relaxing)
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/cpu_comp.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/cpu.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/flash.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/nvm.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/timer.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/uart.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/assert.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/backdoor.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/boot.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/com.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/cop.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/xcp.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/core_cm3.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/system_efm32.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_acmp.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_adc.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_aes.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_assert.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_cmu.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_dac.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_dbg.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_dma.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_ebi.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_emu.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_gpio.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_i2c.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_int.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_lcd.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_lesense.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_letimer.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_leuart.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_mpu.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_msc.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_opamp.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_pcnt.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_prs.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_rmu.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_rtc.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_system.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_timer.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_usart.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_vcmp.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/efm32_wdog.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/hooks.o
- .comment 0x00000000 0x4f THUMB Flash Debug/../../obj/main.o
+.comment 0x00000000 0x4c
+ .comment 0x00000000 0x4c THUMB Flash Debug/../../obj/vectors.o
+ 0x4d (size before relaxing)
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/cpu_comp.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/cpu.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/flash.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/nvm.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/timer.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/uart.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/assert.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/backdoor.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/boot.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/com.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/cop.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/xcp.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/system_efm32.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/efm32_cmu.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/efm32_emu.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/efm32_gpio.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/efm32_leuart.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/efm32_msc.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/efm32_system.o
+ .comment 0x0000004c 0x4d THUMB Flash Debug/../../obj/main.o
-.debug_line 0x00000000 0x876f
- .debug_line 0x00000000 0x11b THUMB Flash Debug/../../obj/cstart.o
- .debug_line 0x0000011b 0x14b THUMB Flash Debug/../../obj/vectors.o
- .debug_line 0x00000266 0xd5 THUMB Flash Debug/../../obj/cpu_comp.o
- .debug_line 0x0000033b 0x10c THUMB Flash Debug/../../obj/cpu.o
- .debug_line 0x00000447 0x412 THUMB Flash Debug/../../obj/flash.o
- .debug_line 0x00000859 0x122 THUMB Flash Debug/../../obj/nvm.o
- .debug_line 0x0000097b 0x108 THUMB Flash Debug/../../obj/timer.o
- .debug_line 0x00000a83 0x3b1 THUMB Flash Debug/../../obj/uart.o
- .debug_line 0x00000e34 0x13b THUMB Flash Debug/../../obj/assert.o
- .debug_line 0x00000f6f 0x158 THUMB Flash Debug/../../obj/backdoor.o
- .debug_line 0x000010c7 0xc2 THUMB Flash Debug/../../obj/boot.o
- .debug_line 0x00001189 0x1c2 THUMB Flash Debug/../../obj/com.o
- .debug_line 0x0000134b 0xb6 THUMB Flash Debug/../../obj/cop.o
- .debug_line 0x00001401 0x232 THUMB Flash Debug/../../obj/xcp.o
- .debug_line 0x00001633 0x1d THUMB Flash Debug/../../obj/core_cm3.o
- .debug_line 0x00001650 0x287 THUMB Flash Debug/../../obj/system_efm32.o
- .debug_line 0x000018d7 0x3a7 THUMB Flash Debug/../../obj/efm32_acmp.o
- .debug_line 0x00001c7e 0x3ce THUMB Flash Debug/../../obj/efm32_adc.o
- .debug_line 0x0000204c 0xd02 THUMB Flash Debug/../../obj/efm32_aes.o
- .debug_line 0x00002d4e 0x0 THUMB Flash Debug/../../obj/efm32_assert.o
- .debug_line 0x00002d4e 0x6e9 THUMB Flash Debug/../../obj/efm32_cmu.o
- .debug_line 0x00003437 0x372 THUMB Flash Debug/../../obj/efm32_dac.o
- .debug_line 0x000037a9 0x2f0 THUMB Flash Debug/../../obj/efm32_dbg.o
- .debug_line 0x00003a99 0x50c THUMB Flash Debug/../../obj/efm32_dma.o
- .debug_line 0x00003fa5 0x3e2 THUMB Flash Debug/../../obj/efm32_ebi.o
- .debug_line 0x00004387 0x3c5 THUMB Flash Debug/../../obj/efm32_emu.o
- .debug_line 0x0000474c 0x3ff THUMB Flash Debug/../../obj/efm32_gpio.o
- .debug_line 0x00004b4b 0x485 THUMB Flash Debug/../../obj/efm32_i2c.o
- .debug_line 0x00004fd0 0x201 THUMB Flash Debug/../../obj/efm32_int.o
- .debug_line 0x000051d1 0x440 THUMB Flash Debug/../../obj/efm32_lcd.o
- .debug_line 0x00005611 0x101 THUMB Flash Debug/../../obj/efm32_lesense.o
- .debug_line 0x00005712 0x3c5 THUMB Flash Debug/../../obj/efm32_letimer.o
- .debug_line 0x00005ad7 0x3ff THUMB Flash Debug/../../obj/efm32_leuart.o
- .debug_line 0x00005ed6 0x223 THUMB Flash Debug/../../obj/efm32_mpu.o
- .debug_line 0x000060f9 0x364 THUMB Flash Debug/../../obj/efm32_msc.o
- .debug_line 0x0000645d 0x101 THUMB Flash Debug/../../obj/efm32_opamp.o
- .debug_line 0x0000655e 0x424 THUMB Flash Debug/../../obj/efm32_pcnt.o
- .debug_line 0x00006982 0x2b8 THUMB Flash Debug/../../obj/efm32_prs.o
- .debug_line 0x00006c3a 0x321 THUMB Flash Debug/../../obj/efm32_rmu.o
- .debug_line 0x00006f5b 0x37e THUMB Flash Debug/../../obj/efm32_rtc.o
- .debug_line 0x000072d9 0x2e4 THUMB Flash Debug/../../obj/efm32_system.o
- .debug_line 0x000075bd 0x36d THUMB Flash Debug/../../obj/efm32_timer.o
- .debug_line 0x0000792a 0x49d THUMB Flash Debug/../../obj/efm32_usart.o
- .debug_line 0x00007dc7 0x31f THUMB Flash Debug/../../obj/efm32_vcmp.o
- .debug_line 0x000080e6 0x340 THUMB Flash Debug/../../obj/efm32_wdog.o
- .debug_line 0x00008426 0x1d THUMB Flash Debug/../../obj/hooks.o
- .debug_line 0x00008443 0x32c THUMB Flash Debug/../../obj/main.o
+.debug_line 0x00000000 0x33e9
+ .debug_line 0x00000000 0x146 THUMB Flash Debug/../../obj/cstart.o
+ .debug_line 0x00000146 0x101 THUMB Flash Debug/../../obj/vectors.o
+ .debug_line 0x00000247 0xd3 THUMB Flash Debug/../../obj/cpu_comp.o
+ .debug_line 0x0000031a 0x127 THUMB Flash Debug/../../obj/cpu.o
+ .debug_line 0x00000441 0x425 THUMB Flash Debug/../../obj/flash.o
+ .debug_line 0x00000866 0x165 THUMB Flash Debug/../../obj/nvm.o
+ .debug_line 0x000009cb 0x134 THUMB Flash Debug/../../obj/timer.o
+ .debug_line 0x00000aff 0x3b2 THUMB Flash Debug/../../obj/uart.o
+ .debug_line 0x00000eb1 0xee THUMB Flash Debug/../../obj/assert.o
+ .debug_line 0x00000f9f 0x111 THUMB Flash Debug/../../obj/backdoor.o
+ .debug_line 0x000010b0 0xc2 THUMB Flash Debug/../../obj/boot.o
+ .debug_line 0x00001172 0x186 THUMB Flash Debug/../../obj/com.o
+ .debug_line 0x000012f8 0xa5 THUMB Flash Debug/../../obj/cop.o
+ .debug_line 0x0000139d 0x20c THUMB Flash Debug/../../obj/xcp.o
+ .debug_line 0x000015a9 0x2f4 THUMB Flash Debug/../../obj/system_efm32.o
+ .debug_line 0x0000189d 0x6b6 THUMB Flash Debug/../../obj/efm32_cmu.o
+ .debug_line 0x00001f53 0x3d1 THUMB Flash Debug/../../obj/efm32_emu.o
+ .debug_line 0x00002324 0x3cc THUMB Flash Debug/../../obj/efm32_gpio.o
+ .debug_line 0x000026f0 0x3e8 THUMB Flash Debug/../../obj/efm32_leuart.o
+ .debug_line 0x00002ad8 0x337 THUMB Flash Debug/../../obj/efm32_msc.o
+ .debug_line 0x00002e0f 0x2cc THUMB Flash Debug/../../obj/efm32_system.o
+ .debug_line 0x000030db 0x30e THUMB Flash Debug/../../obj/main.o
-.debug_info 0x00000000 0xe3c9
+.debug_info 0x00000000 0x5d08
.debug_info 0x00000000 0x116 THUMB Flash Debug/../../obj/cstart.o
- .debug_info 0x00000116 0xf1 THUMB Flash Debug/../../obj/vectors.o
- .debug_info 0x00000207 0x86 THUMB Flash Debug/../../obj/cpu_comp.o
- .debug_info 0x0000028d 0x14f THUMB Flash Debug/../../obj/cpu.o
- .debug_info 0x000003dc 0x744 THUMB Flash Debug/../../obj/flash.o
- .debug_info 0x00000b20 0x177 THUMB Flash Debug/../../obj/nvm.o
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- .debug_info 0x00000dc3 0x7c2 THUMB Flash Debug/../../obj/uart.o
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diff --git a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.srec b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.srec
index 59faa1c7..3685518e 100644
--- a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.srec
+++ b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/bin/openbtl_olimex_efm32g880.srec
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diff --git a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/ide/EFM32G880_crossworks.hzs b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/ide/EFM32G880_crossworks.hzs
index 4ca95bf9..e70a572d 100644
--- a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/ide/EFM32G880_crossworks.hzs
+++ b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/ide/EFM32G880_crossworks.hzs
@@ -1,19 +1,22 @@
-
+
+
+
+
-
+
-
+
-
+
-
+
@@ -21,20 +24,18 @@
-
-
-
+
-
+
-
+
-
+
@@ -53,8 +54,7 @@
-
-
+
-
+
diff --git a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/ide/readme.txt b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/ide/readme.txt
index a49767fb..a10a52ca 100644
--- a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/ide/readme.txt
+++ b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Boot/ide/readme.txt
@@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
-Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
+Rowleys CrossWorks (version 3.7.6) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.elf b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.elf
index 0bc3a753..48add7eb 100644
Binary files a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.elf and b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.elf differ
diff --git a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.map b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.map
index 7326831a..86ac99e2 100644
--- a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.map
+++ b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.map
@@ -1,21 +1,17 @@
-Archive member included because of file (symbol)
+Archive member included to satisfy reference by file (symbol)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
THUMB Flash Debug/../../obj/lcdcontroller.o (abs)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2_asm.o)
- C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o) (memcpy)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(__vfprintf_int.o)
- (__vfprintf_int)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(__vfscanf_int.o)
- (__vfscanf_int)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc_asm.o)
- C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o) (__umoddi3)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- (__do_debug_operation_mempoll)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o) (__errno)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v7m_t_le.a(libm_asm.o)
- C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o) (__floatsisf)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o) (memcpy)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o) (__aeabi_uldivmod)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o) (__aeabi_i2f)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfprintf_v7m_t_le_eabi.o (frexp)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o) (fabs)
Discarded input sections
@@ -39,29 +35,44 @@ Discarded input sections
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/timer.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/timer.o
.text.TimerDeinit
- 0x00000000 0x10 THUMB Flash Debug/../../obj/timer.o
+ 0x00000000 0xc THUMB Flash Debug/../../obj/timer.o
+ .text.TimerSet
+ 0x00000000 0xc THUMB Flash Debug/../../obj/timer.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/vectors.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/vectors.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/vectors.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/core_cm3.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/core_cm3.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_info 0x00000000 0x52 THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_abbrev 0x00000000 0x27 THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_pubnames
+ 0x00000000 0x12 THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_pubtypes
+ 0x00000000 0x9f THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_aranges
+ 0x00000000 0x18 THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_line 0x00000000 0x1d THUMB Flash Debug/../../obj/core_cm3.o
+ .debug_str 0x00000000 0x217 THUMB Flash Debug/../../obj/core_cm3.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/core_cm3.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/core_cm3.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/system_efm32.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/system_efm32.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/system_efm32.o
.text.SystemHFXOClockGet
0x00000000 0xc THUMB Flash Debug/../../obj/system_efm32.o
.text.SystemHFXOClockSet
- 0x00000000 0x2c THUMB Flash Debug/../../obj/system_efm32.o
+ 0x00000000 0x24 THUMB Flash Debug/../../obj/system_efm32.o
.text.SystemULFRCOClockGet
0x00000000 0x8 THUMB Flash Debug/../../obj/system_efm32.o
.text.SystemLFXOClockSet
- 0x00000000 0x2c THUMB Flash Debug/../../obj/system_efm32.o
+ 0x00000000 0x24 THUMB Flash Debug/../../obj/system_efm32.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_acmp.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_acmp.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_acmp.o
.text.ACMP_CapsenseInit
- 0x00000000 0x50 THUMB Flash Debug/../../obj/efm32_acmp.o
+ 0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_acmp.o
.text.ACMP_CapsenseChannelSet
0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_acmp.o
.text.ACMP_Disable
@@ -69,396 +80,711 @@ Discarded input sections
.text.ACMP_Enable
0x00000000 0xc THUMB Flash Debug/../../obj/efm32_acmp.o
.text.ACMP_Reset
- 0x00000000 0x20 THUMB Flash Debug/../../obj/efm32_acmp.o
+ 0x00000000 0x18 THUMB Flash Debug/../../obj/efm32_acmp.o
.text.ACMP_GPIOSetup
- 0x00000000 0x20 THUMB Flash Debug/../../obj/efm32_acmp.o
+ 0x00000000 0x1c THUMB Flash Debug/../../obj/efm32_acmp.o
.text.ACMP_ChannelSet
0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_acmp.o
.text.ACMP_Init
- 0x00000000 0x54 THUMB Flash Debug/../../obj/efm32_acmp.o
+ 0x00000000 0x4c THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_frame 0x00000000 0xcc THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_info 0x00000000 0x5b1 THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_abbrev 0x00000000 0x1ad THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_loc 0x00000000 0x21f THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_pubnames
+ 0x00000000 0xc0 THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_pubtypes
+ 0x00000000 0x18a THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_aranges
+ 0x00000000 0x58 THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_ranges 0x00000000 0x48 THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_line 0x00000000 0x35d THUMB Flash Debug/../../obj/efm32_acmp.o
+ .debug_str 0x00000000 0x646 THUMB Flash Debug/../../obj/efm32_acmp.o
+ .comment 0x00000000 0x4d THUMB Flash Debug/../../obj/efm32_acmp.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Flash Debug/../../obj/efm32_acmp.o
.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_adc.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_adc.o
.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_adc.o
.text.ADC_Init
- 0x00000000 0x3c THUMB Flash Debug/../../obj/efm32_adc.o
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- .text.ADC_Reset
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- .text.ADC_TimebaseCalc
0x00000000 0x40 THUMB Flash Debug/../../obj/efm32_adc.o
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.text.AES_CBC128
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.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_cmu.o
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.text.CMU_Calibrate
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.text.CMU_ClockDivGet
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.text.CMU_FreezeEnable
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.text.CMU_HFRCOBandGet
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.text.CMU_HFRCOStartupDelayGet
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.text.CMU_HFRCOStartupDelaySet
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.text.CMU_LCDClkFDIVGet
0x00000000 0x10 THUMB Flash Debug/../../obj/efm32_cmu.o
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.text.CMU_OscillatorTuningGet
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.text.CMU_PCNTClockExternalGet
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.text.DAC_Init
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.text.DAC_PrescaleCalc
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.text.DAC_Reset
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.bss 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_dbg.o
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.text.DMA_ChannelEnabled
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.text.DMA_Init
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- .text.EBI_BankAddress
0x00000000 0x3c THUMB Flash Debug/../../obj/efm32_ebi.o
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.text.EBI_ChipSelectEnable
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.text.EBI_PolaritySet
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.text.EBI_ReadTimingSet
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.text.EBI_WriteTimingSet
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.text.EBI_AddressTimingSet
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.text.EBI_Init
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.text.EMU_Restore
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.text.EMU_EnterEM2
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.text.EMU_EnterEM3
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.text.EMU_EnterEM4
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.text.EMU_MemPwrDown
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.text.GPIO_DbgLocationSet
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.text.GPIO_IntConfig
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.text.GPIO_PinInGet
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.text.GPIO_PinOutClear
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.text.GPIO_PinOutGet
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.text.GPIO_PinOutSet
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.text.GPIO_PinOutToggle
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.text.GPIO_PortInGet
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.text.GPIO_PortOutClear
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.text.GPIO_PortOutGet
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.text.GPIO_PortOutSet
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.text.GPIO_PortOutSetVal
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.text.GPIO_PortOutToggle
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.text.I2C_BusFreqGet
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.text.I2C_BusFreqSet
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.text.I2C_Enable
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.text.I2C_Init
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.text.I2C_Reset
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.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_system.o
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.text.SYSTEM_GetCalibrationValue
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.text 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_timer.o
.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_timer.o
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.text.TIMER_Enable
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.text.TIMER_Init
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.text.TIMER_InitCC
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.text.TIMER_Reset
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.text.TIMER_Unlock
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.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_usart.o
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.text.USART_BaudrateAsyncSet
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.text.USART_BaudrateCalc
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.text.USART_BaudrateSyncSet
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.text.USART_Enable
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.text.USART_Reset
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- .text.USART_InitSync
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.text.USART_InitAsync
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.text.USART_InitIrDA
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.text.USART_Rx
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.text.USART_Tx
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.text.USART_TxExt
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.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_vcmp.o
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.data 0x00000000 0x0 THUMB Flash Debug/../../obj/efm32_wdog.o
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+ .text.libc.frexpf
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Memory Configuration
@@ -1248,9 +2739,8 @@ FLASH 0x00002000 0x0001e000 xr
Linker script and memory map
- 0x000041e0 __do_debug_operation = __do_debug_operation_mempoll
- 0x000036c4 __vfprintf = __vfprintf_int
- 0x00003e18 __vfscanf = __vfscanf_int
+ 0x00000000 __vfprintf = __vfprintf_float_long_long
+ 0x00000000 __vfscanf = __vfscanf_float_long_long_cc
0x20000000 __SRAM_segment_start__ = 0x20000000
0x20004000 __SRAM_segment_end__ = 0x20004000
0x00002000 __FLASH_segment_start__ = 0x2000
@@ -1283,254 +2773,191 @@ Linker script and memory map
0x00000001 . = ASSERT (((__vectors_end__ >= __FLASH_segment_start__) && (__vectors_end__ <= __FLASH_segment_end__)), error: .vectors is too large to fit in FLASH memory segment)
0x000020bc __init_load_start__ = ALIGN (__vectors_end__, 0x4)
-.init 0x000020bc 0x12c
+.init 0x000020bc 0x134
0x000020bc __init_start__ = .
*(.init .init.*)
- .init 0x000020bc 0x12c THUMB Flash Debug/../../obj/cstart.o
+ .init 0x000020bc 0x134 THUMB Flash Debug/../../obj/cstart.o
0x000020bc _start
- 0x0000214c exit
- 0x00002170 reset_handler
- 0x000021e8 __init_end__ = (__init_start__ + SIZEOF (.init))
- 0x000021e8 __init_load_end__ = __init_end__
+ 0x00002154 exit
+ 0x00002178 reset_handler
+ 0x000021f0 __init_end__ = (__init_start__ + SIZEOF (.init))
+ 0x000021f0 __init_load_end__ = __init_end__
0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= __FLASH_segment_end__)), error: .init is too large to fit in FLASH memory segment)
- 0x000021e8 __text_load_start__ = ALIGN (__init_end__, 0x4)
+ 0x000021f0 __text_load_start__ = ALIGN (__init_end__, 0x4)
-.text 0x000021e8 0x2038
- 0x000021e8 __text_start__ = .
+.text 0x000021f0 0xe9c
+ 0x000021f0 __text_start__ = .
*(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table .ARM.extab* .gnu.linkonce.armextab.*)
- .glue_7 0x00000000 0x0 linker stubs
- .glue_7t 0x00000000 0x0 linker stubs
- .text.UartReceiveByte
- 0x000021e8 0x34 THUMB Flash Debug/../../obj/boot.o
+ .glue_7 0x000021f0 0x0 linker stubs
+ .glue_7t 0x000021f0 0x0 linker stubs
.text.BootComInit
- 0x0000221c 0xf4 THUMB Flash Debug/../../obj/boot.o
- 0x0000221c BootComInit
+ 0x000021f0 0xac THUMB Flash Debug/../../obj/boot.o
+ 0x000021f0 BootComInit
.text.BootActivate
- 0x00002310 0x24 THUMB Flash Debug/../../obj/boot.o
- 0x00002310 BootActivate
+ 0x0000229c 0x20 THUMB Flash Debug/../../obj/boot.o
+ 0x0000229c BootActivate
.text.BootComCheckActivationRequest
- 0x00002334 0xc0 THUMB Flash Debug/../../obj/boot.o
- 0x00002334 BootComCheckActivationRequest
- .text.LedInit 0x000023f4 0x18 THUMB Flash Debug/../../obj/led.o
- 0x000023f4 LedInit
+ 0x000022bc 0x84 THUMB Flash Debug/../../obj/boot.o
+ 0x000022bc BootComCheckActivationRequest
+ .text.LedInit 0x00002340 0x14 THUMB Flash Debug/../../obj/led.o
+ 0x00002340 LedInit
.text.LedToggle
- 0x0000240c 0x80 THUMB Flash Debug/../../obj/led.o
- 0x0000240c LedToggle
- .text.main 0x0000248c 0x2a4 THUMB Flash Debug/../../obj/main.o
- 0x0000248c main
- .text.TimerSet
- 0x00002730 0xc THUMB Flash Debug/../../obj/timer.o
- 0x00002730 TimerSet
+ 0x00002354 0x54 THUMB Flash Debug/../../obj/led.o
+ 0x00002354 LedToggle
+ .text.main 0x000023a8 0x208 THUMB Flash Debug/../../obj/main.o
+ 0x000023a8 main
.text.TimerInit
- 0x0000273c 0x5c THUMB Flash Debug/../../obj/timer.o
- 0x0000273c TimerInit
+ 0x000025b0 0x44 THUMB Flash Debug/../../obj/timer.o
+ 0x000025b0 TimerInit
.text.TimerGet
- 0x00002798 0xc THUMB Flash Debug/../../obj/timer.o
- 0x00002798 TimerGet
+ 0x000025f4 0xc THUMB Flash Debug/../../obj/timer.o
+ 0x000025f4 TimerGet
.text.TimerISRHandler
- 0x000027a4 0x14 THUMB Flash Debug/../../obj/timer.o
- 0x000027a4 TimerISRHandler
+ 0x00002600 0x10 THUMB Flash Debug/../../obj/timer.o
+ 0x00002600 TimerISRHandler
.text.UnusedISR
- 0x000027b8 0x4 THUMB Flash Debug/../../obj/vectors.o
- 0x000027b8 UnusedISR
+ 0x00002610 0x4 THUMB Flash Debug/../../obj/vectors.o
+ 0x00002610 UnusedISR
.text.SystemHFClockGet
- 0x000027bc 0xb8 THUMB Flash Debug/../../obj/system_efm32.o
- 0x000027bc SystemHFClockGet
+ 0x00002614 0x9c THUMB Flash Debug/../../obj/system_efm32.o
+ 0x00002614 SystemHFClockGet
.text.SystemCoreClockGet
- 0x00002874 0x2c THUMB Flash Debug/../../obj/system_efm32.o
- 0x00002874 SystemCoreClockGet
+ 0x000026b0 0x24 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x000026b0 SystemCoreClockGet
.text.SystemInit
- 0x000028a0 0x4 THUMB Flash Debug/../../obj/system_efm32.o
- 0x000028a0 SystemInit
+ 0x000026d4 0x4 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x000026d4 SystemInit
.text.SystemLFRCOClockGet
- 0x000028a4 0x8 THUMB Flash Debug/../../obj/system_efm32.o
- 0x000028a4 SystemLFRCOClockGet
+ 0x000026d8 0x8 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x000026d8 SystemLFRCOClockGet
.text.SystemLFXOClockGet
- 0x000028ac 0xc THUMB Flash Debug/../../obj/system_efm32.o
- 0x000028ac SystemLFXOClockGet
+ 0x000026e0 0xc THUMB Flash Debug/../../obj/system_efm32.o
+ 0x000026e0 SystemLFXOClockGet
.text.CMU_FlashWaitStateMax
- 0x000028b8 0x38 THUMB Flash Debug/../../obj/efm32_cmu.o
- .text.CMU_DivToLog2
- 0x000028f0 0xc THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x000026ec 0x30 THUMB Flash Debug/../../obj/efm32_cmu.o
.text.CMU_FlashWaitStateControl
- 0x000028fc 0x64 THUMB Flash Debug/../../obj/efm32_cmu.o
- .text.CMU_AUXClkGet
- 0x00002960 0xc THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x0000271c 0x54 THUMB Flash Debug/../../obj/efm32_cmu.o
.text.CMU_LFClkGet
- 0x0000296c 0x5c THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00002770 0x44 THUMB Flash Debug/../../obj/efm32_cmu.o
.text.CMU_ClockDivSet
- 0x000029c8 0x204 THUMB Flash Debug/../../obj/efm32_cmu.o
- 0x000029c8 CMU_ClockDivSet
+ 0x000027b4 0x178 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x000027b4 CMU_ClockDivSet
.text.CMU_ClockEnable
- 0x00002bcc 0x9c THUMB Flash Debug/../../obj/efm32_cmu.o
- 0x00002bcc CMU_ClockEnable
+ 0x0000292c 0x80 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x0000292c CMU_ClockEnable
.text.CMU_ClockSelectGet
- 0x00002c68 0xac THUMB Flash Debug/../../obj/efm32_cmu.o
- 0x00002c68 CMU_ClockSelectGet
+ 0x000029ac 0x8c THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x000029ac CMU_ClockSelectGet
.text.CMU_ClockFreqGet
- 0x00002d14 0x208 THUMB Flash Debug/../../obj/efm32_cmu.o
- 0x00002d14 CMU_ClockFreqGet
+ 0x00002a38 0x144 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00002a38 CMU_ClockFreqGet
.text.CMU_OscillatorEnable
- 0x00002f1c 0x78 THUMB Flash Debug/../../obj/efm32_cmu.o
- 0x00002f1c CMU_OscillatorEnable
+ 0x00002b7c 0x54 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00002b7c CMU_OscillatorEnable
.text.CMU_ClockSelectSet
- 0x00002f94 0x110 THUMB Flash Debug/../../obj/efm32_cmu.o
- 0x00002f94 CMU_ClockSelectSet
+ 0x00002bd0 0xc8 THUMB Flash Debug/../../obj/efm32_cmu.o
+ 0x00002bd0 CMU_ClockSelectSet
.text.EMU_UpdateOscConfig
- 0x000030a4 0x18 THUMB Flash Debug/../../obj/efm32_emu.o
- 0x000030a4 EMU_UpdateOscConfig
+ 0x00002c98 0x14 THUMB Flash Debug/../../obj/efm32_emu.o
+ 0x00002c98 EMU_UpdateOscConfig
.text.GPIO_DriveModeSet
- 0x000030bc 0x1c THUMB Flash Debug/../../obj/efm32_gpio.o
- 0x000030bc GPIO_DriveModeSet
+ 0x00002cac 0x1c THUMB Flash Debug/../../obj/efm32_gpio.o
+ 0x00002cac GPIO_DriveModeSet
.text.GPIO_PinModeSet
- 0x000030d8 0xd8 THUMB Flash Debug/../../obj/efm32_gpio.o
- 0x000030d8 GPIO_PinModeSet
+ 0x00002cc8 0xc0 THUMB Flash Debug/../../obj/efm32_gpio.o
+ 0x00002cc8 GPIO_PinModeSet
.text.LEUART_BaudrateSet
- 0x000031b0 0x64 THUMB Flash Debug/../../obj/efm32_leuart.o
- 0x000031b0 LEUART_BaudrateSet
+ 0x00002d88 0x50 THUMB Flash Debug/../../obj/efm32_leuart.o
+ 0x00002d88 LEUART_BaudrateSet
.text.LEUART_Enable
- 0x00003214 0x20 THUMB Flash Debug/../../obj/efm32_leuart.o
- 0x00003214 LEUART_Enable
- .text.LEUART_FreezeEnable
- 0x00003234 0x1c THUMB Flash Debug/../../obj/efm32_leuart.o
- 0x00003234 LEUART_FreezeEnable
+ 0x00002dd8 0x20 THUMB Flash Debug/../../obj/efm32_leuart.o
+ 0x00002dd8 LEUART_Enable
.text.LEUART_Init
- 0x00003250 0x60 THUMB Flash Debug/../../obj/efm32_leuart.o
- 0x00003250 LEUART_Init
+ 0x00002df8 0x50 THUMB Flash Debug/../../obj/efm32_leuart.o
+ 0x00002df8 LEUART_Init
.text.LEUART_Rx
- 0x000032b0 0x10 THUMB Flash Debug/../../obj/efm32_leuart.o
- 0x000032b0 LEUART_Rx
+ 0x00002e48 0x10 THUMB Flash Debug/../../obj/efm32_leuart.o
+ 0x00002e48 LEUART_Rx
.text.SYSTEM_ChipRevisionGet
- 0x000032c0 0x24 THUMB Flash Debug/../../obj/efm32_system.o
- 0x000032c0 SYSTEM_ChipRevisionGet
+ 0x00002e58 0x20 THUMB Flash Debug/../../obj/efm32_system.o
+ 0x00002e58 SYSTEM_ChipRevisionGet
.text.LCD_enableSegment
- 0x000032e4 0x60 THUMB Flash Debug/../../obj/lcdcontroller.o
+ 0x00002e78 0x60 THUMB Flash Debug/../../obj/lcdcontroller.o
.text.LCD_disableSegment
- 0x00003344 0x70 THUMB Flash Debug/../../obj/lcdcontroller.o
+ 0x00002ed8 0x70 THUMB Flash Debug/../../obj/lcdcontroller.o
.text.LCD_IRQHandler
- 0x000033b4 0x20 THUMB Flash Debug/../../obj/lcdcontroller.o
- 0x000033b4 LCD_IRQHandler
+ 0x00002f48 0x1c THUMB Flash Debug/../../obj/lcdcontroller.o
+ 0x00002f48 LCD_IRQHandler
.text.LCD_AllOff
- 0x000033d4 0x1c THUMB Flash Debug/../../obj/lcdcontroller.o
- 0x000033d4 LCD_AllOff
+ 0x00002f64 0x1c THUMB Flash Debug/../../obj/lcdcontroller.o
+ 0x00002f64 LCD_AllOff
.text.LCD_Symbol
- 0x000033f0 0xa8 THUMB Flash Debug/../../obj/lcdcontroller.o
- 0x000033f0 LCD_Symbol
+ 0x00002f80 0x7c THUMB Flash Debug/../../obj/lcdcontroller.o
+ 0x00002f80 LCD_Symbol
.text.LCD_Init
- 0x00003498 0xa8 THUMB Flash Debug/../../obj/lcdcontroller.o
- 0x00003498 LCD_Init
- .text.libc.__getc
- 0x00003540 0x28 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- 0x00003540 __getc
- .text.libc.__putc
- 0x00003568 0x38 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- 0x00003568 __putc
- .text.libc.__print_padding
- 0x000035a0 0x24 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- 0x000035a0 __print_padding
- .text.libc.__pre_padding
- 0x000035c4 0x1c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- 0x000035c4 __pre_padding
- .text.libc.isupper
- 0x000035e0 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- 0x000035e0 isupper
- .text.libc.islower
- 0x000035f0 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- 0x000035f0 islower
- .text.libc.isdigit
- 0x00003600 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- 0x00003600 isdigit
- .text.libc.__digit
- 0x00003610 0x3c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- 0x00003610 __digit
- .text.libc.isspace
- 0x0000364c 0x18 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- 0x0000364c isspace
- .text.libc.strlen
- 0x00003664 0x60 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2_asm.o)
- 0x00003664 strlen
- .text.libc.__vfprintf_int
- 0x000036c4 0x5e4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(__vfprintf_int.o)
- 0x000036c4 __vfprintf_int
- .text.libc.__ungetc
- 0x00003ca8 0x20 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(__vfscanf_int.o)
- .text.libc.rd_int
- 0x00003cc8 0x150 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(__vfscanf_int.o)
- .text.libc.__vfscanf_int
- 0x00003e18 0x3c8 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(__vfscanf_int.o)
- 0x00003e18 __vfscanf_int
- .text.libdebugio.__do_debug_operation_mempoll
- 0x000041e0 0x38 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x000041e0 __do_debug_operation_mempoll
- .text.libc.__debug_io_lock
- 0x00004218 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- 0x00004218 __debug_io_lock
- .text.libc.__debug_io_unlock
- 0x0000421c 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- 0x0000421c __debug_io_unlock
- 0x00004220 __text_end__ = (__text_start__ + SIZEOF (.text))
- 0x00004220 __text_load_end__ = __text_end__
+ 0x00002ffc 0x90 THUMB Flash Debug/../../obj/lcdcontroller.o
+ 0x00002ffc LCD_Init
+ 0x0000308c __text_end__ = (__text_start__ + SIZEOF (.text))
+ 0x0000308c __text_load_end__ = __text_end__
.vfp11_veneer 0x00000000 0x0
.vfp11_veneer 0x00000000 0x0 linker stubs
.v4_bx 0x00000000 0x0
.v4_bx 0x00000000 0x0 linker stubs
- 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= __FLASH_segment_end__)), error: .text is too large to fit in FLASH memory segment)
- 0x00004220 __dtors_load_start__ = ALIGN (__text_end__, 0x4)
-.dtors 0x00004220 0x0
- 0x00004220 __dtors_start__ = .
+.iplt 0x00000000 0x0
+ .iplt 0x00000000 0x0 THUMB Flash Debug/../../obj/boot.o
+ 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= __FLASH_segment_end__)), error: .text is too large to fit in FLASH memory segment)
+ 0x0000308c __dtors_load_start__ = ALIGN (__text_end__, 0x4)
+
+.dtors 0x0000308c 0x0
+ 0x0000308c __dtors_start__ = .
*(SORT(.dtors.*))
*(.dtors)
*(.fini_array .fini_array.*)
- 0x00004220 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
- 0x00004220 __dtors_load_end__ = __dtors_end__
+ 0x0000308c __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
+ 0x0000308c __dtors_load_end__ = __dtors_end__
0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= __FLASH_segment_end__)), error: .dtors is too large to fit in FLASH memory segment)
- 0x00004220 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
+ 0x0000308c __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
-.ctors 0x00004220 0x0
- 0x00004220 __ctors_start__ = .
+.ctors 0x0000308c 0x0
+ 0x0000308c __ctors_start__ = .
*(SORT(.ctors.*))
*(.ctors)
*(.init_array .init_array.*)
- 0x00004220 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
- 0x00004220 __ctors_load_end__ = __ctors_end__
+ 0x0000308c __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
+ 0x0000308c __ctors_load_end__ = __ctors_end__
0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= __FLASH_segment_end__)), error: .ctors is too large to fit in FLASH memory segment)
- 0x00004220 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
+ 0x0000308c __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
-.rodata 0x00004220 0x40
- 0x00004220 __rodata_start__ = .
+.rodata 0x0000308c 0x10
+ 0x0000308c __rodata_start__ = .
*(.rodata .rodata.* .gnu.linkonce.r.*)
- .rodata 0x00004220 0x18 THUMB Flash Debug/../../obj/boot.o
- .rodata.libc.__hex_lc
- 0x00004238 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- 0x00004238 __hex_lc
- .rodata.libc.__hex_uc
- 0x00004248 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- 0x00004248 __hex_uc
- .rodata.libc.str1.4
- 0x00004258 0x8 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(__vfprintf_int.o)
- 0x00004260 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
- 0x00004260 __rodata_load_end__ = __rodata_end__
+ .rodata 0x0000308c 0x10 THUMB Flash Debug/../../obj/boot.o
+ 0x0000309c __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
+ 0x0000309c __rodata_load_end__ = __rodata_end__
+
+.rel.dyn 0x00002000 0x0
+ .rel.iplt 0x00002000 0x0 THUMB Flash Debug/../../obj/boot.o
0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= __FLASH_segment_end__)), error: .rodata is too large to fit in FLASH memory segment)
- 0x00004260 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4)
+ 0x0000309c __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4)
-.ARM.exidx 0x00004260 0x0
- 0x00004260 __ARM.exidx_start__ = .
- 0x00004260 __exidx_start = __ARM.exidx_start__
+.ARM.exidx 0x0000309c 0x0
+ 0x0000309c __ARM.exidx_start__ = .
+ 0x0000309c __exidx_start = __ARM.exidx_start__
*(.ARM.exidx .ARM.exidx.*)
- 0x00004260 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx))
- 0x00004260 __exidx_end = __ARM.exidx_end__
- 0x00004260 __ARM.exidx_load_end__ = __ARM.exidx_end__
+ 0x0000309c __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx))
+ 0x0000309c __exidx_end = __ARM.exidx_end__
+ 0x0000309c __ARM.exidx_load_end__ = __ARM.exidx_end__
0x00000001 . = ASSERT (((__ARM.exidx_end__ >= __FLASH_segment_start__) && (__ARM.exidx_end__ <= __FLASH_segment_end__)), error: .ARM.exidx is too large to fit in FLASH memory segment)
- 0x00004260 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4)
+ 0x0000309c __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4)
-.fast 0x20000000 0x0 load address 0x00004260
+.fast 0x20000000 0x0 load address 0x0000309c
0x20000000 __fast_start__ = .
*(.fast .fast.*)
0x20000000 __fast_end__ = (__fast_start__ + SIZEOF (.fast))
- 0x00004260 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
+ 0x0000309c __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
0x00000001 . = ASSERT (((__fast_load_end__ >= __FLASH_segment_start__) && (__fast_load_end__ <= __FLASH_segment_end__)), error: .fast is too large to fit in FLASH memory segment)
.fast_run 0x20000000 0x0
@@ -1539,9 +2966,9 @@ Linker script and memory map
0x20000000 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run))
0x20000000 __fast_run_load_end__ = __fast_run_end__
0x00000001 . = ASSERT (((__fast_run_end__ >= __SRAM_segment_start__) && (__fast_run_end__ <= __SRAM_segment_end__)), error: .fast_run is too large to fit in SRAM memory segment)
- 0x00004260 __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4)
+ 0x0000309c __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4)
-.data 0x20000000 0x8 load address 0x00004260
+.data 0x20000000 0x8 load address 0x0000309c
0x20000000 __data_start__ = .
*(.data .data.* .gnu.linkonce.d.*)
.data.SystemLFXOClock
@@ -1549,118 +2976,112 @@ Linker script and memory map
.data.SystemHFXOClock
0x20000004 0x4 THUMB Flash Debug/../../obj/system_efm32.o
0x20000008 __data_end__ = (__data_start__ + SIZEOF (.data))
- 0x00004268 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+ 0x000030a4 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+
+.igot.plt 0x00000000 0x0
+ .igot.plt 0x00000000 0x0 THUMB Flash Debug/../../obj/boot.o
0x00000001 . = ASSERT (((__data_load_end__ >= __FLASH_segment_start__) && (__data_load_end__ <= __FLASH_segment_end__)), error: .data is too large to fit in FLASH memory segment)
-.data_run 0x20000000 0x8 load address 0x00004260
+.data_run 0x20000000 0x8 load address 0x0000309c
0x20000000 __data_run_start__ = .
0x20000008 . = MAX ((__data_run_start__ + SIZEOF (.data)), .)
- *fill* 0x20000000 0x8 00
+ *fill* 0x20000000 0x8
0x20000008 __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run))
0x20000008 __data_run_load_end__ = __data_run_end__
0x00000001 . = ASSERT (((__data_run_end__ >= __SRAM_segment_start__) && (__data_run_end__ <= __SRAM_segment_end__)), error: .data_run is too large to fit in SRAM memory segment)
0x20000008 __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
-.bss 0x20000008 0x6c
+.bss 0x20000008 0x5c
0x20000008 __bss_start__ = .
*(.bss .bss.* .gnu.linkonce.b.*)
- .bss.xcpCtoReqPacket.2173
- 0x20000008 0x44 THUMB Flash Debug/../../obj/boot.o
- .bss.xcpCtoRxLength.2174
- 0x2000004c 0x1 THUMB Flash Debug/../../obj/boot.o
- .bss.xcpCtoRxInProgress.2175
- 0x2000004d 0x1 THUMB Flash Debug/../../obj/boot.o
- *fill* 0x2000004e 0x2 00
- .bss.timer_counter_last.2158
- 0x20000050 0x4 THUMB Flash Debug/../../obj/led.o
- .bss.led_toggle_state.2157
- 0x20000054 0x1 THUMB Flash Debug/../../obj/led.o
- *fill* 0x20000055 0x3 00
+ .bss.xcpCtoReqPacket.5081
+ 0x20000008 0x41 THUMB Flash Debug/../../obj/boot.o
+ .bss.xcpCtoRxLength.5082
+ 0x20000049 0x1 THUMB Flash Debug/../../obj/boot.o
+ .bss.xcpCtoRxInProgress.5083
+ 0x2000004a 0x1 THUMB Flash Debug/../../obj/boot.o
+ *fill* 0x2000004b 0x1
+ .bss.timer_counter_last.5066
+ 0x2000004c 0x4 THUMB Flash Debug/../../obj/led.o
+ .bss.led_toggle_state.5065
+ 0x20000050 0x1 THUMB Flash Debug/../../obj/led.o
+ *fill* 0x20000051 0x3
.bss.millisecond_counter
- 0x20000058 0x4 THUMB Flash Debug/../../obj/timer.o
+ 0x20000054 0x4 THUMB Flash Debug/../../obj/timer.o
.bss.SystemCoreClock
- 0x2000005c 0x4 THUMB Flash Debug/../../obj/system_efm32.o
- 0x2000005c SystemCoreClock
+ 0x20000058 0x4 THUMB Flash Debug/../../obj/system_efm32.o
+ 0x20000058 SystemCoreClock
.bss.cmuStatus
- 0x20000060 0x2 THUMB Flash Debug/../../obj/efm32_emu.o
- *fill* 0x20000062 0x2 00
+ 0x2000005c 0x2 THUMB Flash Debug/../../obj/efm32_emu.o
+ *fill* 0x2000005e 0x2
.bss.frameCounter
- 0x20000064 0x4 THUMB Flash Debug/../../obj/lcdcontroller.o
- 0x20000064 frameCounter
- .bss.libc.__format_extender
- 0x20000068 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- 0x20000068 __format_extender
- .bss.libdebugio.dbgCommWord
- 0x2000006c 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x2000006c dbgCommWord
- .bss.libdebugio.dbgCntrlWord_mempoll
- 0x20000070 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x20000070 dbgCntrlWord_mempoll
+ 0x20000060 0x4 THUMB Flash Debug/../../obj/lcdcontroller.o
+ 0x20000060 frameCounter
*(COMMON)
- 0x20000074 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
- 0x20000074 __bss_load_end__ = __bss_end__
+ 0x20000064 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
+ 0x20000064 __bss_load_end__ = __bss_end__
0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= __SRAM_segment_end__)), error: .bss is too large to fit in SRAM memory segment)
- 0x20000074 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
+ 0x20000064 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
-.non_init 0x20000074 0x0
- 0x20000074 __non_init_start__ = .
+.non_init 0x20000064 0x0
+ 0x20000064 __non_init_start__ = .
*(.non_init .non_init.*)
- 0x20000074 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
- 0x20000074 __non_init_load_end__ = __non_init_end__
+ 0x20000064 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
+ 0x20000064 __non_init_load_end__ = __non_init_end__
0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= __SRAM_segment_end__)), error: .non_init is too large to fit in SRAM memory segment)
- 0x20000074 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
+ 0x20000064 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
-.heap 0x20000074 0x80
- 0x20000074 __heap_start__ = .
+.heap 0x20000064 0x80
+ 0x20000064 __heap_start__ = .
*(.heap .heap.*)
- 0x200000f4 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
- *fill* 0x20000074 0x80 00
- 0x200000f4 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
- 0x200000f4 __heap_load_end__ = __heap_end__
+ 0x200000e4 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
+ *fill* 0x20000064 0x80
+ 0x200000e4 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
+ 0x200000e4 __heap_load_end__ = __heap_end__
0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= __SRAM_segment_end__)), error: .heap is too large to fit in SRAM memory segment)
- 0x200000f4 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
+ 0x200000e4 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
-.stack 0x200000f4 0x100
- 0x200000f4 __stack_start__ = .
+.stack 0x200000e4 0x100
+ 0x200000e4 __stack_start__ = .
*(.stack .stack.*)
- 0x200001f4 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
- *fill* 0x200000f4 0x100 00
- 0x200001f4 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
- 0x200001f4 __stack_load_end__ = __stack_end__
+ 0x200001e4 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
+ *fill* 0x200000e4 0x100
+ 0x200001e4 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
+ 0x200001e4 __stack_load_end__ = __stack_end__
0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= __SRAM_segment_end__)), error: .stack is too large to fit in SRAM memory segment)
- 0x200001f4 __stack_process_load_start__ = ALIGN (__stack_end__, 0x4)
+ 0x200001e4 __stack_process_load_start__ = ALIGN (__stack_end__, 0x4)
-.stack_process 0x200001f4 0x0
- 0x200001f4 __stack_process_start__ = .
+.stack_process 0x200001e4 0x0
+ 0x200001e4 __stack_process_start__ = .
*(.stack_process .stack_process.*)
- 0x200001f4 . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4)
- 0x200001f4 __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process))
- 0x200001f4 __stack_process_load_end__ = __stack_process_end__
+ 0x200001e4 . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4)
+ 0x200001e4 __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process))
+ 0x200001e4 __stack_process_load_end__ = __stack_process_end__
0x00000001 . = ASSERT (((__stack_process_end__ >= __SRAM_segment_start__) && (__stack_process_end__ <= __SRAM_segment_end__)), error: .stack_process is too large to fit in SRAM memory segment)
- 0x200001f4 __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4)
+ 0x200001e4 __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4)
-.tbss 0x200001f4 0x0
- 0x200001f4 __tbss_start__ = .
+.tbss 0x200001e4 0x0
+ 0x200001e4 __tbss_start__ = .
*(.tbss .tbss.*)
- 0x200001f4 __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss))
- 0x200001f4 __tbss_load_end__ = __tbss_end__
+ 0x200001e4 __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss))
+ 0x200001e4 __tbss_load_end__ = __tbss_end__
0x00000001 . = ASSERT (((__tbss_end__ >= __SRAM_segment_start__) && (__tbss_end__ <= __SRAM_segment_end__)), error: .tbss is too large to fit in SRAM memory segment)
- 0x00004268 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
+ 0x000030a4 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
-.tdata 0x200001f4 0x0 load address 0x00004268
- 0x200001f4 __tdata_start__ = .
+.tdata 0x200001e4 0x0 load address 0x000030a4
+ 0x200001e4 __tdata_start__ = .
*(.tdata .tdata.*)
- 0x200001f4 __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata))
- 0x00004268 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata))
- 0x00004268 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata))
+ 0x200001e4 __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata))
+ 0x000030a4 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata))
+ 0x000030a4 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata))
0x00000001 . = ASSERT (((__tdata_load_end__ >= __FLASH_segment_start__) && (__tdata_load_end__ <= __FLASH_segment_end__)), error: .tdata is too large to fit in FLASH memory segment)
-.tdata_run 0x200001f4 0x0
- 0x200001f4 __tdata_run_start__ = .
- 0x200001f4 . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .)
- 0x200001f4 __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run))
- 0x200001f4 __tdata_run_load_end__ = __tdata_run_end__
- 0x200001f4 __SRAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run))
+.tdata_run 0x200001e4 0x0
+ 0x200001e4 __tdata_run_start__ = .
+ 0x200001e4 . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .)
+ 0x200001e4 __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run))
+ 0x200001e4 __tdata_run_load_end__ = __tdata_run_end__
+ 0x200001e4 __SRAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run))
0x00000001 . = ASSERT (((__tdata_run_end__ >= __SRAM_segment_start__) && (__tdata_run_end__ <= __SRAM_segment_end__)), error: .tdata_run is too large to fit in SRAM memory segment)
START GROUP
LOAD THUMB Flash Debug/../../obj/boot.o
@@ -1701,565 +3122,251 @@ LOAD THUMB Flash Debug/../../obj/efm32_usart.o
LOAD THUMB Flash Debug/../../obj/efm32_vcmp.o
LOAD THUMB Flash Debug/../../obj/efm32_wdog.o
LOAD THUMB Flash Debug/../../obj/lcdcontroller.o
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcm_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcpp_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_targetio_impl_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libcm_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libdebugio_mempoll_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libcpp_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libdebugio_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfprintf_v7m_t_le_eabi.o
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfscanf_v7m_t_le_eabi.o
END GROUP
OUTPUT(THUMB Flash Debug/../../bin/demoprog_olimex_efm32g880.elf elf32-littlearm)
-.debug_frame 0x00000000 0x3b30
- .debug_frame 0x00000000 0x7c THUMB Flash Debug/../../obj/boot.o
- .debug_frame 0x0000007c 0x48 THUMB Flash Debug/../../obj/led.o
- .debug_frame 0x000000c4 0x30 THUMB Flash Debug/../../obj/main.o
- .debug_frame 0x000000f4 0x6c THUMB Flash Debug/../../obj/timer.o
- .debug_frame 0x00000160 0x20 THUMB Flash Debug/../../obj/vectors.o
- .debug_frame 0x00000180 0xc4 THUMB Flash Debug/../../obj/system_efm32.o
- .debug_frame 0x00000244 0xb4 THUMB Flash Debug/../../obj/efm32_acmp.o
- .debug_frame 0x000002f8 0xa0 THUMB Flash Debug/../../obj/efm32_adc.o
- .debug_frame 0x00000398 0x1ec THUMB Flash Debug/../../obj/efm32_aes.o
- .debug_frame 0x00000584 0x204 THUMB Flash Debug/../../obj/efm32_cmu.o
- .debug_frame 0x00000788 0x78 THUMB Flash Debug/../../obj/efm32_dac.o
- .debug_frame 0x00000800 0x30 THUMB Flash Debug/../../obj/efm32_dbg.o
- .debug_frame 0x00000830 0x1a4 THUMB Flash Debug/../../obj/efm32_dma.o
- .debug_frame 0x000009d4 0xc8 THUMB Flash Debug/../../obj/efm32_ebi.o
- .debug_frame 0x00000a9c 0x88 THUMB Flash Debug/../../obj/efm32_emu.o
- .debug_frame 0x00000b24 0x120 THUMB Flash Debug/../../obj/efm32_gpio.o
- .debug_frame 0x00000c44 0xd0 THUMB Flash Debug/../../obj/efm32_i2c.o
- .debug_frame 0x00000d14 0xcc THUMB Flash Debug/../../obj/efm32_lcd.o
- .debug_frame 0x00000de0 0xc4 THUMB Flash Debug/../../obj/efm32_letimer.o
- .debug_frame 0x00000ea4 0xfc THUMB Flash Debug/../../obj/efm32_leuart.o
- .debug_frame 0x00000fa0 0x20 THUMB Flash Debug/../../obj/efm32_mpu.o
- .debug_frame 0x00000fc0 0x68 THUMB Flash Debug/../../obj/efm32_msc.o
- .debug_frame 0x00001028 0xbc THUMB Flash Debug/../../obj/efm32_pcnt.o
- .debug_frame 0x000010e4 0x2c THUMB Flash Debug/../../obj/efm32_prs.o
- .debug_frame 0x00001110 0x40 THUMB Flash Debug/../../obj/efm32_rmu.o
- .debug_frame 0x00001150 0x98 THUMB Flash Debug/../../obj/efm32_rtc.o
- .debug_frame 0x000011e8 0x3c THUMB Flash Debug/../../obj/efm32_system.o
- .debug_frame 0x00001224 0x7c THUMB Flash Debug/../../obj/efm32_timer.o
- .debug_frame 0x000012a0 0x18c THUMB Flash Debug/../../obj/efm32_usart.o
- .debug_frame 0x0000142c 0x4c THUMB Flash Debug/../../obj/efm32_vcmp.o
- .debug_frame 0x00001478 0x5c THUMB Flash Debug/../../obj/efm32_wdog.o
- .debug_frame 0x000014d4 0x15c THUMB Flash Debug/../../obj/lcdcontroller.o
- .debug_frame 0x00001630 0x128c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- .debug_frame 0x000028bc 0x120 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2_asm.o)
- .debug_frame 0x000029dc 0x40 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(__vfprintf_int.o)
- .debug_frame 0x00002a1c 0x88 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(__vfscanf_int.o)
- .debug_frame 0x00002aa4 0x260 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc_asm.o)
- .debug_frame 0x00002d04 0x78c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .debug_frame 0x00003490 0xa0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- .debug_frame 0x00003530 0x600 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v7m_t_le.a(libm_asm.o)
+.debug_frame 0x00000000 0x860
+ .debug_frame 0x00000000 0x70 THUMB Flash Debug/../../obj/boot.o
+ .debug_frame 0x00000070 0x48 THUMB Flash Debug/../../obj/led.o
+ .debug_frame 0x000000b8 0x30 THUMB Flash Debug/../../obj/main.o
+ .debug_frame 0x000000e8 0x6c THUMB Flash Debug/../../obj/timer.o
+ .debug_frame 0x00000154 0x20 THUMB Flash Debug/../../obj/vectors.o
+ .debug_frame 0x00000174 0xc4 THUMB Flash Debug/../../obj/system_efm32.o
+ .debug_frame 0x00000238 0x1d8 THUMB Flash Debug/../../obj/efm32_cmu.o
+ .debug_frame 0x00000410 0x88 THUMB Flash Debug/../../obj/efm32_emu.o
+ .debug_frame 0x00000498 0x144 THUMB Flash Debug/../../obj/efm32_gpio.o
+ .debug_frame 0x000005dc 0xec THUMB Flash Debug/../../obj/efm32_leuart.o
+ .debug_frame 0x000006c8 0x30 THUMB Flash Debug/../../obj/efm32_system.o
+ .debug_frame 0x000006f8 0x168 THUMB Flash Debug/../../obj/lcdcontroller.o
-.debug_info 0x00000000 0xfd30
- .debug_info 0x00000000 0x844 THUMB Flash Debug/../../obj/boot.o
- .debug_info 0x00000844 0xee THUMB Flash Debug/../../obj/cstart.o
- .debug_info 0x00000932 0x2bf THUMB Flash Debug/../../obj/led.o
- .debug_info 0x00000bf1 0x5ca THUMB Flash Debug/../../obj/main.o
- .debug_info 0x000011bb 0x703 THUMB Flash Debug/../../obj/timer.o
- .debug_info 0x000018be 0x111 THUMB Flash Debug/../../obj/vectors.o
- .debug_info 0x000019cf 0x5a THUMB Flash Debug/../../obj/core_cm3.o
- .debug_info 0x00001a29 0x429 THUMB Flash Debug/../../obj/system_efm32.o
- .debug_info 0x00001e52 0x5f6 THUMB Flash Debug/../../obj/efm32_acmp.o
- .debug_info 0x00002448 0xa5b THUMB Flash Debug/../../obj/efm32_adc.o
- .debug_info 0x00002ea3 0x156e THUMB Flash Debug/../../obj/efm32_aes.o
- .debug_info 0x00004411 0xf7b THUMB Flash Debug/../../obj/efm32_cmu.o
- .debug_info 0x0000538c 0x809 THUMB Flash Debug/../../obj/efm32_dac.o
- .debug_info 0x00005b95 0x410 THUMB Flash Debug/../../obj/efm32_dbg.o
- .debug_info 0x00005fa5 0x10f7 THUMB Flash Debug/../../obj/efm32_dma.o
- .debug_info 0x0000709c 0x942 THUMB Flash Debug/../../obj/efm32_ebi.o
- .debug_info 0x000079de 0x680 THUMB Flash Debug/../../obj/efm32_emu.o
- .debug_info 0x0000805e 0x7cc THUMB Flash Debug/../../obj/efm32_gpio.o
- .debug_info 0x0000882a 0x84a THUMB Flash Debug/../../obj/efm32_i2c.o
- .debug_info 0x00009074 0xb0 THUMB Flash Debug/../../obj/efm32_int.o
- .debug_info 0x00009124 0xad2 THUMB Flash Debug/../../obj/efm32_lcd.o
- .debug_info 0x00009bf6 0x86 THUMB Flash Debug/../../obj/efm32_lesense.o
- .debug_info 0x00009c7c 0x613 THUMB Flash Debug/../../obj/efm32_letimer.o
- .debug_info 0x0000a28f 0x7d4 THUMB Flash Debug/../../obj/efm32_leuart.o
- .debug_info 0x0000aa63 0x33f THUMB Flash Debug/../../obj/efm32_mpu.o
- .debug_info 0x0000ada2 0x2b3 THUMB Flash Debug/../../obj/efm32_msc.o
- .debug_info 0x0000b055 0x86 THUMB Flash Debug/../../obj/efm32_opamp.o
- .debug_info 0x0000b0db 0x86a THUMB Flash Debug/../../obj/efm32_pcnt.o
- .debug_info 0x0000b945 0x1bf THUMB Flash Debug/../../obj/efm32_prs.o
- .debug_info 0x0000bb04 0x2f4 THUMB Flash Debug/../../obj/efm32_rmu.o
- .debug_info 0x0000bdf8 0x3b9 THUMB Flash Debug/../../obj/efm32_rtc.o
- .debug_info 0x0000c1b1 0x242 THUMB Flash Debug/../../obj/efm32_system.o
- .debug_info 0x0000c3f3 0x700 THUMB Flash Debug/../../obj/efm32_timer.o
- .debug_info 0x0000caf3 0xafd THUMB Flash Debug/../../obj/efm32_usart.o
- .debug_info 0x0000d5f0 0x2fc THUMB Flash Debug/../../obj/efm32_vcmp.o
- .debug_info 0x0000d8ec 0x39a THUMB Flash Debug/../../obj/efm32_wdog.o
- .debug_info 0x0000dc86 0xdc0 THUMB Flash Debug/../../obj/lcdcontroller.o
- .debug_info 0x0000ea46 0xc63 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- .debug_info 0x0000f6a9 0x36 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(__vfprintf_int.o)
- .debug_info 0x0000f6df 0x65 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(__vfscanf_int.o)
- .debug_info 0x0000f744 0x51f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .debug_info 0x0000fc63 0xcd C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
+.debug_info 0x00000000 0x5929
+ .debug_info 0x00000000 0x96a THUMB Flash Debug/../../obj/boot.o
+ .debug_info 0x0000096a 0xee THUMB Flash Debug/../../obj/cstart.o
+ .debug_info 0x00000a58 0x2d8 THUMB Flash Debug/../../obj/led.o
+ .debug_info 0x00000d30 0x78d THUMB Flash Debug/../../obj/main.o
+ .debug_info 0x000014bd 0x715 THUMB Flash Debug/../../obj/timer.o
+ .debug_info 0x00001bd2 0xfc THUMB Flash Debug/../../obj/vectors.o
+ .debug_info 0x00001cce 0x3cd THUMB Flash Debug/../../obj/system_efm32.o
+ .debug_info 0x0000209b 0x12ef THUMB Flash Debug/../../obj/efm32_cmu.o
+ .debug_info 0x0000338a 0x622 THUMB Flash Debug/../../obj/efm32_emu.o
+ .debug_info 0x000039ac 0x760 THUMB Flash Debug/../../obj/efm32_gpio.o
+ .debug_info 0x0000410c 0x882 THUMB Flash Debug/../../obj/efm32_leuart.o
+ .debug_info 0x0000498e 0x20d THUMB Flash Debug/../../obj/efm32_system.o
+ .debug_info 0x00004b9b 0xd8e THUMB Flash Debug/../../obj/lcdcontroller.o
-.debug_abbrev 0x00000000 0x3e79
- .debug_abbrev 0x00000000 0x1ad THUMB Flash Debug/../../obj/boot.o
- .debug_abbrev 0x000001ad 0x14 THUMB Flash Debug/../../obj/cstart.o
- .debug_abbrev 0x000001c1 0xf5 THUMB Flash Debug/../../obj/led.o
- .debug_abbrev 0x000002b6 0x16a THUMB Flash Debug/../../obj/main.o
- .debug_abbrev 0x00000420 0x1db THUMB Flash Debug/../../obj/timer.o
- .debug_abbrev 0x000005fb 0xcb THUMB Flash Debug/../../obj/vectors.o
- .debug_abbrev 0x000006c6 0x1d THUMB Flash Debug/../../obj/core_cm3.o
- .debug_abbrev 0x000006e3 0x1a5 THUMB Flash Debug/../../obj/system_efm32.o
- .debug_abbrev 0x00000888 0x1c2 THUMB Flash Debug/../../obj/efm32_acmp.o
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diff --git a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.srec b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.srec
index 52dd50d0..a0a65894 100644
--- a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/bin/demoprog_olimex_efm32g880.srec
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diff --git a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/ide/EFM32G880_crossworks.hzs b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/ide/EFM32G880_crossworks.hzs
index 71a455d0..29a2fa97 100644
--- a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/ide/EFM32G880_crossworks.hzs
+++ b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/ide/EFM32G880_crossworks.hzs
@@ -1,19 +1,22 @@
-
+
+
+
+
-
+
-
+
-
+
-
+
@@ -24,16 +27,16 @@
-
+
-
+
-
+
-
+
@@ -52,7 +55,7 @@
-
+
-
+
diff --git a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/ide/readme.txt b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/ide/readme.txt
index a49767fb..a10a52ca 100644
--- a/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/ide/readme.txt
+++ b/Target/Demo/ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks/Prog/ide/readme.txt
@@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
-Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
+Rowleys CrossWorks (version 3.7.6) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.elf b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.elf
index f462d12b..d485c698 100644
Binary files a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.elf and b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.elf differ
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.map b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.map
index d40ca116..4dd4ef3b 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.map
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.map
@@ -1,9 +1,17 @@
-Archive member included because of file (symbol)
+Archive member included to satisfy reference by file (symbol)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- (__do_debug_operation_mempoll)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o) (__debug_io_lock)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfscanf_v7m_t_le_eabi.o (__aeabi_i2d)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfprintf_v7m_t_le_eabi.o (frexp)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o) (fabs)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfprintf_v7m_t_le_eabi.o (__aeabi_uldivmod)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfscanf_v7m_t_le_eabi.o (__getc)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o) (memcpy)
Discarded input sections
@@ -17,60 +25,33 @@ Discarded input sections
.text 0x00000000 0x0 THUMB Debug/../../obj/main.o
.data 0x00000000 0x0 THUMB Debug/../../obj/main.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/main.o
- .text 0x00000000 0x0 THUMB Debug/../../obj/core_cm3.o
- .data 0x00000000 0x0 THUMB Debug/../../obj/core_cm3.o
- .bss 0x00000000 0x0 THUMB Debug/../../obj/core_cm3.o
- .text.__get_PSP
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__set_PSP
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__get_MSP
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__set_MSP
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__get_BASEPRI
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__set_BASEPRI
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__get_PRIMASK
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__set_PRIMASK
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__get_FAULTMASK
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__set_FAULTMASK
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__get_CONTROL
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__set_CONTROL
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__REV 0x00000000 0x4 THUMB Debug/../../obj/core_cm3.o
- .text.__REV16 0x00000000 0x4 THUMB Debug/../../obj/core_cm3.o
- .text.__REVSH 0x00000000 0x4 THUMB Debug/../../obj/core_cm3.o
- .text.__RBIT 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__LDREXB
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__LDREXH
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__LDREXW
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__STREXB
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__STREXH
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__STREXW
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
.text 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f10x.o
.data 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f10x.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f10x.o
.text.SystemInit
- 0x00000000 0x130 THUMB Debug/../../obj/system_stm32f10x.o
+ 0x00000000 0x100 THUMB Debug/../../obj/system_stm32f10x.o
.text.SystemCoreClockUpdate
- 0x00000000 0xe0 THUMB Debug/../../obj/system_stm32f10x.o
+ 0x00000000 0x8c THUMB Debug/../../obj/system_stm32f10x.o
.data.AHBPrescTable
0x00000000 0x10 THUMB Debug/../../obj/system_stm32f10x.o
.data.SystemCoreClock
0x00000000 0x4 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_frame 0x00000000 0x40 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_info 0x00000000 0x492 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_abbrev 0x00000000 0x175 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_loc 0x00000000 0xe8 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_pubnames
+ 0x00000000 0x97 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_pubtypes
+ 0x00000000 0x10d THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_aranges
+ 0x00000000 0x28 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_ranges 0x00000000 0x18 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_line 0x00000000 0x22d THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_str 0x00000000 0x400 THUMB Debug/../../obj/system_stm32f10x.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/system_stm32f10x.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/system_stm32f10x.o
.text 0x00000000 0x0 THUMB Debug/../../obj/usb_core.o
.data 0x00000000 0x0 THUMB Debug/../../obj/usb_core.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/usb_core.o
@@ -82,96 +63,96 @@ Discarded input sections
.text 0x00000000 0x0 THUMB Debug/../../obj/usb_int.o
.data 0x00000000 0x0 THUMB Debug/../../obj/usb_int.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/usb_int.o
- .text.CTR_HP 0x00000000 0x9c THUMB Debug/../../obj/usb_int.o
+ .text.CTR_HP 0x00000000 0x88 THUMB Debug/../../obj/usb_int.o
.text 0x00000000 0x0 THUMB Debug/../../obj/usb_mem.o
.data 0x00000000 0x0 THUMB Debug/../../obj/usb_mem.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/usb_mem.o
.text 0x00000000 0x0 THUMB Debug/../../obj/usb_regs.o
.data 0x00000000 0x0 THUMB Debug/../../obj/usb_regs.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/usb_regs.o
- .text.SetCNTR 0x00000000 0x10 THUMB Debug/../../obj/usb_regs.o
- .text.GetCNTR 0x00000000 0x10 THUMB Debug/../../obj/usb_regs.o
- .text.SetISTR 0x00000000 0x10 THUMB Debug/../../obj/usb_regs.o
- .text.GetISTR 0x00000000 0x10 THUMB Debug/../../obj/usb_regs.o
- .text.GetFNR 0x00000000 0x10 THUMB Debug/../../obj/usb_regs.o
+ .text.SetCNTR 0x00000000 0xc THUMB Debug/../../obj/usb_regs.o
+ .text.GetCNTR 0x00000000 0xc THUMB Debug/../../obj/usb_regs.o
+ .text.SetISTR 0x00000000 0xc THUMB Debug/../../obj/usb_regs.o
+ .text.GetISTR 0x00000000 0xc THUMB Debug/../../obj/usb_regs.o
+ .text.GetFNR 0x00000000 0xc THUMB Debug/../../obj/usb_regs.o
.text.SetDADDR
- 0x00000000 0x10 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0xc THUMB Debug/../../obj/usb_regs.o
.text.GetDADDR
- 0x00000000 0x10 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0xc THUMB Debug/../../obj/usb_regs.o
.text.GetBTABLE
- 0x00000000 0x10 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0xc THUMB Debug/../../obj/usb_regs.o
.text.SetENDPOINT
- 0x00000000 0x14 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x10 THUMB Debug/../../obj/usb_regs.o
.text.GetENDPOINT
- 0x00000000 0x14 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x10 THUMB Debug/../../obj/usb_regs.o
.text.GetEPType
- 0x00000000 0x18 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x14 THUMB Debug/../../obj/usb_regs.o
.text.SetDouBleBuffEPStall
- 0x00000000 0x3c THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x2c THUMB Debug/../../obj/usb_regs.o
.text.GetEPTxStatus
- 0x00000000 0x18 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x14 THUMB Debug/../../obj/usb_regs.o
.text.GetEPRxStatus
- 0x00000000 0x18 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x14 THUMB Debug/../../obj/usb_regs.o
.text.SetEP_KIND
- 0x00000000 0x24 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
.text.ClearEP_KIND
- 0x00000000 0x24 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
.text.Set_Status_Out
- 0x00000000 0x24 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
.text.SetEPDoubleBuff
- 0x00000000 0x24 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
.text.ClearEPDoubleBuff
- 0x00000000 0x24 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
.text.GetTxStallStatus
- 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
- .text.GetRxStallStatus
- 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
- .text.ClearEP_CTR_RX
0x00000000 0x1c THUMB Debug/../../obj/usb_regs.o
+ .text.GetRxStallStatus
+ 0x00000000 0x1c THUMB Debug/../../obj/usb_regs.o
+ .text.ClearEP_CTR_RX
+ 0x00000000 0x18 THUMB Debug/../../obj/usb_regs.o
.text.ClearEP_CTR_TX
0x00000000 0x1c THUMB Debug/../../obj/usb_regs.o
.text.ToggleDTOG_RX
- 0x00000000 0x24 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
.text.ToggleDTOG_TX
- 0x00000000 0x24 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
.text.SetEPAddress
- 0x00000000 0x2c THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x24 THUMB Debug/../../obj/usb_regs.o
.text.GetEPAddress
- 0x00000000 0x18 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x14 THUMB Debug/../../obj/usb_regs.o
.text.SetEPCountRxReg
- 0x00000000 0x38 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x2c THUMB Debug/../../obj/usb_regs.o
.text.GetEPTxCount
- 0x00000000 0x2c THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
.text.SetEPDblBuffAddr
- 0x00000000 0x4c THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x3c THUMB Debug/../../obj/usb_regs.o
.text.SetEPDblBuf0Addr
- 0x00000000 0x28 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
.text.SetEPDblBuf1Addr
- 0x00000000 0x2c THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
.text.GetEPDblBuf0Addr
- 0x00000000 0x24 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x1c THUMB Debug/../../obj/usb_regs.o
.text.GetEPDblBuf1Addr
- 0x00000000 0x24 THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x1c THUMB Debug/../../obj/usb_regs.o
.text.SetEPDblBuffCount
- 0x00000000 0x10c THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0xbc THUMB Debug/../../obj/usb_regs.o
.text.SetEPDblBuf0Count
- 0x00000000 0x84 THUMB Debug/../../obj/usb_regs.o
- .text.SetEPDblBuf1Count
- 0x00000000 0x84 THUMB Debug/../../obj/usb_regs.o
- .text.GetEPDblBuf0Count
- 0x00000000 0x2c THUMB Debug/../../obj/usb_regs.o
- .text.GetEPDblBuf1Count
- 0x00000000 0x2c THUMB Debug/../../obj/usb_regs.o
- .text.GetEPDblBufDir
0x00000000 0x60 THUMB Debug/../../obj/usb_regs.o
+ .text.SetEPDblBuf1Count
+ 0x00000000 0x60 THUMB Debug/../../obj/usb_regs.o
+ .text.GetEPDblBuf0Count
+ 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
+ .text.GetEPDblBuf1Count
+ 0x00000000 0x20 THUMB Debug/../../obj/usb_regs.o
+ .text.GetEPDblBufDir
+ 0x00000000 0x48 THUMB Debug/../../obj/usb_regs.o
.text.FreeUserBuffer
- 0x00000000 0x4c THUMB Debug/../../obj/usb_regs.o
- .text.ToWord 0x00000000 0xc THUMB Debug/../../obj/usb_regs.o
+ 0x00000000 0x48 THUMB Debug/../../obj/usb_regs.o
+ .text.ToWord 0x00000000 0x8 THUMB Debug/../../obj/usb_regs.o
.text 0x00000000 0x0 THUMB Debug/../../obj/usb_sil.o
.data 0x00000000 0x0 THUMB Debug/../../obj/usb_sil.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/usb_sil.o
.text.USB_SIL_Write
- 0x00000000 0x2c THUMB Debug/../../obj/usb_sil.o
+ 0x00000000 0x28 THUMB Debug/../../obj/usb_sil.o
.text 0x00000000 0x0 THUMB Debug/../../obj/usb_desc.o
.data 0x00000000 0x0 THUMB Debug/../../obj/usb_desc.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/usb_desc.o
@@ -188,14 +169,14 @@ Discarded input sections
.data 0x00000000 0x0 THUMB Debug/../../obj/usb_pwr.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/usb_pwr.o
.text.PowerOff
- 0x00000000 0x30 THUMB Debug/../../obj/usb_pwr.o
- .text.Suspend 0x00000000 0x28 THUMB Debug/../../obj/usb_pwr.o
+ 0x00000000 0x24 THUMB Debug/../../obj/usb_pwr.o
+ .text.Suspend 0x00000000 0x24 THUMB Debug/../../obj/usb_pwr.o
.text.Resume_Init
0x00000000 0x20 THUMB Debug/../../obj/usb_pwr.o
- .text.Resume 0x00000000 0x10c THUMB Debug/../../obj/usb_pwr.o
- .bss.ResumeS 0x00000000 0x8 THUMB Debug/../../obj/usb_pwr.o
+ .text.Resume 0x00000000 0xac THUMB Debug/../../obj/usb_pwr.o
+ .bss.ResumeS 0x00000000 0x2 THUMB Debug/../../obj/usb_pwr.o
.data.fSuspendEnabled
- 0x00000000 0x4 THUMB Debug/../../obj/usb_pwr.o
+ 0x00000000 0x1 THUMB Debug/../../obj/usb_pwr.o
.text 0x00000000 0x0 THUMB Debug/../../obj/cpu_comp.o
.data 0x00000000 0x0 THUMB Debug/../../obj/cpu_comp.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/cpu_comp.o
@@ -212,34 +193,58 @@ Discarded input sections
.text 0x00000000 0x0 THUMB Debug/../../obj/can.o
.data 0x00000000 0x0 THUMB Debug/../../obj/can.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/can.o
+ .debug_info 0x00000000 0x56 THUMB Debug/../../obj/can.o
+ .debug_abbrev 0x00000000 0x29 THUMB Debug/../../obj/can.o
+ .debug_pubnames
+ 0x00000000 0x12 THUMB Debug/../../obj/can.o
+ .debug_pubtypes
+ 0x00000000 0x91 THUMB Debug/../../obj/can.o
+ .debug_aranges
+ 0x00000000 0x18 THUMB Debug/../../obj/can.o
+ .debug_line 0x00000000 0x1d THUMB Debug/../../obj/can.o
+ .debug_str 0x00000000 0x251 THUMB Debug/../../obj/can.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/can.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/can.o
.text 0x00000000 0x0 THUMB Debug/../../obj/cpu.o
.data 0x00000000 0x0 THUMB Debug/../../obj/cpu.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/cpu.o
- .text.CpuReset
- 0x00000000 0xc THUMB Debug/../../obj/cpu.o
.text 0x00000000 0x0 THUMB Debug/../../obj/flash.o
.data 0x00000000 0x0 THUMB Debug/../../obj/flash.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/flash.o
.text.FlashReinit
- 0x00000000 0x1c THUMB Debug/../../obj/flash.o
+ 0x00000000 0x18 THUMB Debug/../../obj/flash.o
.text 0x00000000 0x0 THUMB Debug/../../obj/nvm.o
.data 0x00000000 0x0 THUMB Debug/../../obj/nvm.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/nvm.o
.text.NvmReinit
- 0x00000000 0xc THUMB Debug/../../obj/nvm.o
+ 0x00000000 0x8 THUMB Debug/../../obj/nvm.o
.text 0x00000000 0x0 THUMB Debug/../../obj/timer.o
.data 0x00000000 0x0 THUMB Debug/../../obj/timer.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/timer.o
.text 0x00000000 0x0 THUMB Debug/../../obj/uart.o
.data 0x00000000 0x0 THUMB Debug/../../obj/uart.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/uart.o
+ .debug_info 0x00000000 0x56 THUMB Debug/../../obj/uart.o
+ .debug_abbrev 0x00000000 0x29 THUMB Debug/../../obj/uart.o
+ .debug_pubnames
+ 0x00000000 0x12 THUMB Debug/../../obj/uart.o
+ .debug_pubtypes
+ 0x00000000 0x91 THUMB Debug/../../obj/uart.o
+ .debug_aranges
+ 0x00000000 0x18 THUMB Debug/../../obj/uart.o
+ .debug_line 0x00000000 0x1d THUMB Debug/../../obj/uart.o
+ .debug_str 0x00000000 0x252 THUMB Debug/../../obj/uart.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/uart.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/uart.o
.text 0x00000000 0x0 THUMB Debug/../../obj/usb.o
.data 0x00000000 0x0 THUMB Debug/../../obj/usb.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/usb.o
.text.UsbEnterLowPowerMode
- 0x00000000 0x18 THUMB Debug/../../obj/usb.o
+ 0x00000000 0x14 THUMB Debug/../../obj/usb.o
.text.UsbLeaveLowPowerMode
- 0x00000000 0x38 THUMB Debug/../../obj/usb.o
+ 0x00000000 0x24 THUMB Debug/../../obj/usb.o
.text 0x00000000 0x0 THUMB Debug/../../obj/assert.o
.data 0x00000000 0x0 THUMB Debug/../../obj/assert.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/assert.o
@@ -258,163 +263,1844 @@ Discarded input sections
.text 0x00000000 0x0 THUMB Debug/../../obj/xcp.o
.data 0x00000000 0x0 THUMB Debug/../../obj/xcp.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/xcp.o
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- .data 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .bss 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .text.libdebugio
- 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .text.libdebugio.__do_nvdebug_operation
- 0x00000000 0x18 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .text.libdebugio.debug_abort
- 0x00000000 0x14 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .text.libdebugio.debug_fopen
- 0x00000000 0x1c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .text.libdebugio.debug_fgets
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- .text.libdebugio.debug_fputc
- 0x00000000 0x14 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .text.libdebugio.debug_fputs
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- .text.libdebugio.debug_fread
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- 0x00000000 0x20 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .text.libdebugio.debug_fseek
- 0x00000000 0x18 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
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- 0x00000000 0x20 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
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- .text.libdebugio.debug_fflush
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- .text.libdebugio.debug_getchar
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- .text.libdebugio.debug_putchar
- 0x00000000 0x1c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .text.libdebugio.debug_puts
- 0x00000000 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .text.libdebugio.debug_rewind
- 0x00000000 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .text.libdebugio.debug_clearerr
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- .text.libdebugio.debug_feof
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- .text.libdebugio.debug_vfprintf
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Memory Configuration
@@ -426,7 +2112,8 @@ FLASH 0x08000000 0x00006000 xr
Linker script and memory map
- 0x08002b3c __do_debug_operation = __do_debug_operation_mempoll
+ 0x00000000 __vfprintf = __vfprintf_float_long_long
+ 0x00000000 __vfscanf = __vfscanf_float_long_long_cc
0x20000000 __SRAM_segment_start__ = 0x20000000
0x20002000 __SRAM_segment_end__ = 0x20002000
0x08000000 __FLASH_segment_start__ = 0x8000000
@@ -459,457 +2146,443 @@ Linker script and memory map
0x00000001 . = ASSERT (((__vectors_end__ >= __FLASH_segment_start__) && (__vectors_end__ <= __FLASH_segment_end__)), error: .vectors is too large to fit in FLASH memory segment)
0x08000150 __init_load_start__ = ALIGN (__vectors_end__, 0x4)
-.init 0x08000150 0x104
+.init 0x08000150 0x108
0x08000150 __init_start__ = .
*(.init .init.*)
- .init 0x08000150 0x104 THUMB Debug/../../obj/cstart.o
+ .init 0x08000150 0x108 THUMB Debug/../../obj/cstart.o
0x08000150 reset_handler
- 0x080001ce exit
- 0x08000254 __init_end__ = (__init_start__ + SIZEOF (.init))
- 0x08000254 __init_load_end__ = __init_end__
+ 0x080001d2 exit
+ 0x08000258 __init_end__ = (__init_start__ + SIZEOF (.init))
+ 0x08000258 __init_load_end__ = __init_end__
0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= __FLASH_segment_end__)), error: .init is too large to fit in FLASH memory segment)
- 0x08000254 __text_load_start__ = ALIGN (__init_end__, 0x4)
+ 0x08000258 __text_load_start__ = ALIGN (__init_end__, 0x4)
-.text 0x08000254 0x2928
- 0x08000254 __text_start__ = .
+.text 0x08000258 0x20c4
+ 0x08000258 __text_start__ = .
*(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table .ARM.extab* .gnu.linkonce.armextab.*)
- .glue_7 0x00000000 0x0 linker stubs
- .glue_7t 0x00000000 0x0 linker stubs
+ .glue_7 0x08000258 0x0 linker stubs
+ .glue_7t 0x08000258 0x0 linker stubs
.text.UsbConnectHook
- 0x08000254 0x5c THUMB Debug/../../obj/hooks.o
- 0x08000254 UsbConnectHook
+ 0x08000258 0x44 THUMB Debug/../../obj/hooks.o
+ 0x08000258 UsbConnectHook
.text.CpuUserProgramStartHook
- 0x080002b0 0x10 THUMB Debug/../../obj/hooks.o
- 0x080002b0 CpuUserProgramStartHook
- .text.main 0x080002c0 0x168 THUMB Debug/../../obj/main.o
- 0x080002c0 main
+ 0x0800029c 0x10 THUMB Debug/../../obj/hooks.o
+ 0x0800029c CpuUserProgramStartHook
+ .text.main 0x080002ac 0x138 THUMB Debug/../../obj/main.o
+ 0x080002ac main
.text.Standard_GetConfiguration
- 0x08000428 0x3c THUMB Debug/../../obj/usb_core.o
- 0x08000428 Standard_GetConfiguration
+ 0x080003e4 0x28 THUMB Debug/../../obj/usb_core.o
+ 0x080003e4 Standard_GetConfiguration
.text.Standard_GetInterface
- 0x08000464 0x3c THUMB Debug/../../obj/usb_core.o
- 0x08000464 Standard_GetInterface
+ 0x0800040c 0x28 THUMB Debug/../../obj/usb_core.o
+ 0x0800040c Standard_GetInterface
.text.Standard_GetStatus
- 0x080004a0 0x104 THUMB Debug/../../obj/usb_core.o
- 0x080004a0 Standard_GetStatus
+ 0x08000434 0xb0 THUMB Debug/../../obj/usb_core.o
+ 0x08000434 Standard_GetStatus
.text.DataStageIn
- 0x080005a4 0xe8 THUMB Debug/../../obj/usb_core.o
+ 0x080004e4 0xb0 THUMB Debug/../../obj/usb_core.o
.text.Standard_SetConfiguration
- 0x0800068c 0x54 THUMB Debug/../../obj/usb_core.o
- 0x0800068c Standard_SetConfiguration
+ 0x08000594 0x40 THUMB Debug/../../obj/usb_core.o
+ 0x08000594 Standard_SetConfiguration
.text.Standard_SetInterface
- 0x080006e0 0x64 THUMB Debug/../../obj/usb_core.o
- 0x080006e0 Standard_SetInterface
+ 0x080005d4 0x54 THUMB Debug/../../obj/usb_core.o
+ 0x080005d4 Standard_SetInterface
.text.Standard_ClearFeature
- 0x08000744 0x134 THUMB Debug/../../obj/usb_core.o
- 0x08000744 Standard_ClearFeature
+ 0x08000628 0x11c THUMB Debug/../../obj/usb_core.o
+ 0x08000628 Standard_ClearFeature
.text.Standard_SetEndPointFeature
- 0x08000878 0xc8 THUMB Debug/../../obj/usb_core.o
- 0x08000878 Standard_SetEndPointFeature
+ 0x08000744 0xb8 THUMB Debug/../../obj/usb_core.o
+ 0x08000744 Standard_SetEndPointFeature
.text.Standard_SetDeviceFeature
- 0x08000940 0x2c THUMB Debug/../../obj/usb_core.o
- 0x08000940 Standard_SetDeviceFeature
+ 0x080007fc 0x24 THUMB Debug/../../obj/usb_core.o
+ 0x080007fc Standard_SetDeviceFeature
.text.Standard_GetDescriptorData
- 0x0800096c 0x24 THUMB Debug/../../obj/usb_core.o
- 0x0800096c Standard_GetDescriptorData
+ 0x08000820 0x1c THUMB Debug/../../obj/usb_core.o
+ 0x08000820 Standard_GetDescriptorData
.text.Post0_Process
- 0x08000990 0x50 THUMB Debug/../../obj/usb_core.o
- 0x08000990 Post0_Process
- .text.Out0_Process
- 0x080009e0 0x130 THUMB Debug/../../obj/usb_core.o
- 0x080009e0 Out0_Process
+ 0x0800083c 0x40 THUMB Debug/../../obj/usb_core.o
+ 0x0800083c Post0_Process
.text.Setup0_Process
- 0x08000b10 0x3dc THUMB Debug/../../obj/usb_core.o
- 0x08000b10 Setup0_Process
+ 0x0800087c 0x338 THUMB Debug/../../obj/usb_core.o
+ 0x0800087c Setup0_Process
+ .text.Out0_Process
+ 0x08000bb4 0xf4 THUMB Debug/../../obj/usb_core.o
+ 0x08000bb4 Out0_Process
.text.SetDeviceAddress
- 0x08000eec 0x50 THUMB Debug/../../obj/usb_core.o
- 0x08000eec SetDeviceAddress
+ 0x08000ca8 0x44 THUMB Debug/../../obj/usb_core.o
+ 0x08000ca8 SetDeviceAddress
.text.In0_Process
- 0x08000f3c 0x7c THUMB Debug/../../obj/usb_core.o
- 0x08000f3c In0_Process
+ 0x08000cec 0x64 THUMB Debug/../../obj/usb_core.o
+ 0x08000cec In0_Process
.text.NOP_Process
- 0x08000fb8 0x4 THUMB Debug/../../obj/usb_core.o
- 0x08000fb8 NOP_Process
+ 0x08000d50 0x4 THUMB Debug/../../obj/usb_core.o
+ 0x08000d50 NOP_Process
.text.USB_Init
- 0x08000fbc 0x48 THUMB Debug/../../obj/usb_init.o
- 0x08000fbc USB_Init
- .text.CTR_LP 0x08001004 0x2d8 THUMB Debug/../../obj/usb_int.o
- 0x08001004 CTR_LP
+ 0x08000d54 0x38 THUMB Debug/../../obj/usb_init.o
+ 0x08000d54 USB_Init
+ .text.CTR_LP 0x08000d8c 0x278 THUMB Debug/../../obj/usb_int.o
+ 0x08000d8c CTR_LP
.text.UserToPMABufferCopy
- 0x080012dc 0x38 THUMB Debug/../../obj/usb_mem.o
- 0x080012dc UserToPMABufferCopy
+ 0x08001004 0x34 THUMB Debug/../../obj/usb_mem.o
+ 0x08001004 UserToPMABufferCopy
.text.PMAToUserBufferCopy
- 0x08001314 0x30 THUMB Debug/../../obj/usb_mem.o
- 0x08001314 PMAToUserBufferCopy
+ 0x08001038 0x20 THUMB Debug/../../obj/usb_mem.o
+ 0x08001038 PMAToUserBufferCopy
.text.SetBTABLE
- 0x08001344 0x14 THUMB Debug/../../obj/usb_regs.o
- 0x08001344 SetBTABLE
+ 0x08001058 0x10 THUMB Debug/../../obj/usb_regs.o
+ 0x08001058 SetBTABLE
.text.SetEPType
- 0x08001358 0x20 THUMB Debug/../../obj/usb_regs.o
- 0x08001358 SetEPType
+ 0x08001068 0x1c THUMB Debug/../../obj/usb_regs.o
+ 0x08001068 SetEPType
.text.SetEPTxStatus
- 0x08001378 0x3c THUMB Debug/../../obj/usb_regs.o
- 0x08001378 SetEPTxStatus
+ 0x08001084 0x3c THUMB Debug/../../obj/usb_regs.o
+ 0x08001084 SetEPTxStatus
.text.SetEPRxStatus
- 0x080013b4 0x3c THUMB Debug/../../obj/usb_regs.o
- 0x080013b4 SetEPRxStatus
+ 0x080010c0 0x3c THUMB Debug/../../obj/usb_regs.o
+ 0x080010c0 SetEPRxStatus
.text.SetEPTxValid
- 0x080013f0 0x28 THUMB Debug/../../obj/usb_regs.o
- 0x080013f0 SetEPTxValid
+ 0x080010fc 0x28 THUMB Debug/../../obj/usb_regs.o
+ 0x080010fc SetEPTxValid
.text.SetEPRxValid
- 0x08001418 0x28 THUMB Debug/../../obj/usb_regs.o
- 0x08001418 SetEPRxValid
+ 0x08001124 0x28 THUMB Debug/../../obj/usb_regs.o
+ 0x08001124 SetEPRxValid
.text.Clear_Status_Out
- 0x08001440 0x24 THUMB Debug/../../obj/usb_regs.o
- 0x08001440 Clear_Status_Out
+ 0x0800114c 0x20 THUMB Debug/../../obj/usb_regs.o
+ 0x0800114c Clear_Status_Out
.text.ClearDTOG_RX
- 0x08001464 0x2c THUMB Debug/../../obj/usb_regs.o
- 0x08001464 ClearDTOG_RX
+ 0x0800116c 0x28 THUMB Debug/../../obj/usb_regs.o
+ 0x0800116c ClearDTOG_RX
.text.ClearDTOG_TX
- 0x08001490 0x2c THUMB Debug/../../obj/usb_regs.o
- 0x08001490 ClearDTOG_TX
+ 0x08001194 0x28 THUMB Debug/../../obj/usb_regs.o
+ 0x08001194 ClearDTOG_TX
.text.SetEPTxAddr
- 0x080014bc 0x28 THUMB Debug/../../obj/usb_regs.o
- 0x080014bc SetEPTxAddr
+ 0x080011bc 0x20 THUMB Debug/../../obj/usb_regs.o
+ 0x080011bc SetEPTxAddr
.text.SetEPRxAddr
- 0x080014e4 0x2c THUMB Debug/../../obj/usb_regs.o
- 0x080014e4 SetEPRxAddr
+ 0x080011dc 0x20 THUMB Debug/../../obj/usb_regs.o
+ 0x080011dc SetEPRxAddr
.text.GetEPTxAddr
- 0x08001510 0x24 THUMB Debug/../../obj/usb_regs.o
- 0x08001510 GetEPTxAddr
+ 0x080011fc 0x1c THUMB Debug/../../obj/usb_regs.o
+ 0x080011fc GetEPTxAddr
.text.GetEPRxAddr
- 0x08001534 0x24 THUMB Debug/../../obj/usb_regs.o
- 0x08001534 GetEPRxAddr
+ 0x08001218 0x1c THUMB Debug/../../obj/usb_regs.o
+ 0x08001218 GetEPRxAddr
.text.SetEPTxCount
- 0x08001558 0x28 THUMB Debug/../../obj/usb_regs.o
- 0x08001558 SetEPTxCount
+ 0x08001234 0x1c THUMB Debug/../../obj/usb_regs.o
+ 0x08001234 SetEPTxCount
.text.SetEPRxCount
- 0x08001580 0x58 THUMB Debug/../../obj/usb_regs.o
- 0x08001580 SetEPRxCount
+ 0x08001250 0x44 THUMB Debug/../../obj/usb_regs.o
+ 0x08001250 SetEPRxCount
.text.GetEPRxCount
- 0x080015d8 0x2c THUMB Debug/../../obj/usb_regs.o
- 0x080015d8 GetEPRxCount
+ 0x08001294 0x20 THUMB Debug/../../obj/usb_regs.o
+ 0x08001294 GetEPRxCount
.text.ByteSwap
- 0x08001604 0x10 THUMB Debug/../../obj/usb_regs.o
- 0x08001604 ByteSwap
+ 0x080012b4 0xc THUMB Debug/../../obj/usb_regs.o
+ 0x080012b4 ByteSwap
.text.USB_SIL_Init
- 0x08001614 0x28 THUMB Debug/../../obj/usb_sil.o
- 0x08001614 USB_SIL_Init
+ 0x080012c0 0x20 THUMB Debug/../../obj/usb_sil.o
+ 0x080012c0 USB_SIL_Init
.text.USB_SIL_Read
- 0x0800163c 0x24 THUMB Debug/../../obj/usb_sil.o
- 0x0800163c USB_SIL_Read
+ 0x080012e0 0x24 THUMB Debug/../../obj/usb_sil.o
+ 0x080012e0 USB_SIL_Read
.text.EP1_IN_Callback
- 0x08001660 0xc THUMB Debug/../../obj/usb_endp.o
- 0x08001660 EP1_IN_Callback
+ 0x08001304 0x8 THUMB Debug/../../obj/usb_endp.o
+ 0x08001304 EP1_IN_Callback
.text.EP1_OUT_Callback
- 0x0800166c 0xc THUMB Debug/../../obj/usb_endp.o
- 0x0800166c EP1_OUT_Callback
+ 0x0800130c 0x8 THUMB Debug/../../obj/usb_endp.o
+ 0x0800130c EP1_OUT_Callback
.text.SOF_Callback
- 0x08001678 0x18 THUMB Debug/../../obj/usb_endp.o
- 0x08001678 SOF_Callback
+ 0x08001314 0x14 THUMB Debug/../../obj/usb_endp.o
+ 0x08001314 SOF_Callback
.text.USB_Istr
- 0x08001690 0xac THUMB Debug/../../obj/usb_istr.o
- 0x08001690 USB_Istr
+ 0x08001328 0x80 THUMB Debug/../../obj/usb_istr.o
+ 0x08001328 USB_Istr
.text.Bulk_SetConfiguration
- 0x0800173c 0x1c THUMB Debug/../../obj/usb_prop.o
- 0x0800173c Bulk_SetConfiguration
+ 0x080013a8 0x18 THUMB Debug/../../obj/usb_prop.o
+ 0x080013a8 Bulk_SetConfiguration
.text.Bulk_SetDeviceAddress
- 0x08001758 0x10 THUMB Debug/../../obj/usb_prop.o
- 0x08001758 Bulk_SetDeviceAddress
+ 0x080013c0 0xc THUMB Debug/../../obj/usb_prop.o
+ 0x080013c0 Bulk_SetDeviceAddress
.text.Bulk_Status_In
- 0x08001768 0x4 THUMB Debug/../../obj/usb_prop.o
- 0x08001768 Bulk_Status_In
+ 0x080013cc 0x4 THUMB Debug/../../obj/usb_prop.o
+ 0x080013cc Bulk_Status_In
.text.Bulk_Status_Out
- 0x0800176c 0x4 THUMB Debug/../../obj/usb_prop.o
- 0x0800176c Bulk_Status_Out
+ 0x080013d0 0x4 THUMB Debug/../../obj/usb_prop.o
+ 0x080013d0 Bulk_Status_Out
.text.Bulk_Data_Setup
- 0x08001770 0x58 THUMB Debug/../../obj/usb_prop.o
- 0x08001770 Bulk_Data_Setup
+ 0x080013d4 0x48 THUMB Debug/../../obj/usb_prop.o
+ 0x080013d4 Bulk_Data_Setup
.text.Bulk_NoData_Setup
- 0x080017c8 0x8 THUMB Debug/../../obj/usb_prop.o
- 0x080017c8 Bulk_NoData_Setup
+ 0x0800141c 0x4 THUMB Debug/../../obj/usb_prop.o
+ 0x0800141c Bulk_NoData_Setup
.text.Bulk_Get_Interface_Setting
- 0x080017d0 0x18 THUMB Debug/../../obj/usb_prop.o
- 0x080017d0 Bulk_Get_Interface_Setting
- .text.Bulk_GetBulkDescriptor
- 0x080017e8 0x14 THUMB Debug/../../obj/usb_prop.o
- 0x080017e8 Bulk_GetBulkDescriptor
- .text.Bulk_GetStringDescriptor
- 0x080017fc 0x30 THUMB Debug/../../obj/usb_prop.o
- 0x080017fc Bulk_GetStringDescriptor
- .text.Bulk_GetConfigDescriptor
- 0x0800182c 0x14 THUMB Debug/../../obj/usb_prop.o
- 0x0800182c Bulk_GetConfigDescriptor
- .text.Bulk_GetDeviceDescriptor
- 0x08001840 0x14 THUMB Debug/../../obj/usb_prop.o
- 0x08001840 Bulk_GetDeviceDescriptor
- .text.Bulk_Reset
- 0x08001854 0xd4 THUMB Debug/../../obj/usb_prop.o
- 0x08001854 Bulk_Reset
+ 0x08001420 0x10 THUMB Debug/../../obj/usb_prop.o
+ 0x08001420 Bulk_Get_Interface_Setting
.text.Bulk_Init
- 0x08001928 0x2c THUMB Debug/../../obj/usb_prop.o
- 0x08001928 Bulk_Init
- .text.PowerOn 0x08001954 0x3c THUMB Debug/../../obj/usb_pwr.o
- 0x08001954 PowerOn
+ 0x08001430 0x24 THUMB Debug/../../obj/usb_prop.o
+ 0x08001430 Bulk_Init
+ .text.Bulk_Reset
+ 0x08001454 0xac THUMB Debug/../../obj/usb_prop.o
+ 0x08001454 Bulk_Reset
+ .text.Bulk_GetDeviceDescriptor
+ 0x08001500 0x10 THUMB Debug/../../obj/usb_prop.o
+ 0x08001500 Bulk_GetDeviceDescriptor
+ .text.Bulk_GetConfigDescriptor
+ 0x08001510 0x10 THUMB Debug/../../obj/usb_prop.o
+ 0x08001510 Bulk_GetConfigDescriptor
+ .text.Bulk_GetStringDescriptor
+ 0x08001520 0x24 THUMB Debug/../../obj/usb_prop.o
+ 0x08001520 Bulk_GetStringDescriptor
+ .text.Bulk_GetBulkDescriptor
+ 0x08001544 0x10 THUMB Debug/../../obj/usb_prop.o
+ 0x08001544 Bulk_GetBulkDescriptor
+ .text.PowerOn 0x08001554 0x30 THUMB Debug/../../obj/usb_pwr.o
+ 0x08001554 PowerOn
.text.CpuIrqDisable
- 0x08001990 0x4 THUMB Debug/../../obj/cpu_comp.o
- 0x08001990 CpuIrqDisable
+ 0x08001584 0x4 THUMB Debug/../../obj/cpu_comp.o
+ 0x08001584 CpuIrqDisable
.text.CpuIrqEnable
- 0x08001994 0x4 THUMB Debug/../../obj/cpu_comp.o
- 0x08001994 CpuIrqEnable
+ 0x08001588 0x4 THUMB Debug/../../obj/cpu_comp.o
+ 0x08001588 CpuIrqEnable
.text.UnusedISR
- 0x08001998 0x18 THUMB Debug/../../obj/vectors.o
- 0x08001998 UnusedISR
- .text.CpuInit 0x080019b0 0xc THUMB Debug/../../obj/cpu.o
- 0x080019b0 CpuInit
+ 0x0800158c 0x10 THUMB Debug/../../obj/vectors.o
+ 0x0800158c UnusedISR
+ .text.CpuInit 0x0800159c 0x8 THUMB Debug/../../obj/cpu.o
+ 0x0800159c CpuInit
.text.CpuStartUserProgram
- 0x080019bc 0x3c THUMB Debug/../../obj/cpu.o
- 0x080019bc CpuStartUserProgram
+ 0x080015a4 0x38 THUMB Debug/../../obj/cpu.o
+ 0x080015a4 CpuStartUserProgram
.text.CpuMemCopy
- 0x080019f8 0x28 THUMB Debug/../../obj/cpu.o
- 0x080019f8 CpuMemCopy
- .text.FlashUnlock
- 0x08001a20 0x24 THUMB Debug/../../obj/flash.o
+ 0x080015dc 0x24 THUMB Debug/../../obj/cpu.o
+ 0x080015dc CpuMemCopy
.text.FlashLock
- 0x08001a44 0x14 THUMB Debug/../../obj/flash.o
+ 0x08001600 0x10 THUMB Debug/../../obj/flash.o
.text.FlashGetSector
- 0x08001a58 0x48 THUMB Debug/../../obj/flash.o
+ 0x08001610 0x38 THUMB Debug/../../obj/flash.o
.text.FlashWriteBlock
- 0x08001aa0 0xc8 THUMB Debug/../../obj/flash.o
- .text.FlashGetSectorBaseAddr
- 0x08001b68 0x40 THUMB Debug/../../obj/flash.o
- .text.FlashInitBlock
- 0x08001ba8 0x38 THUMB Debug/../../obj/flash.o
+ 0x08001648 0xb4 THUMB Debug/../../obj/flash.o
.text.FlashSwitchBlock
- 0x08001be0 0x50 THUMB Debug/../../obj/flash.o
+ 0x080016fc 0x58 THUMB Debug/../../obj/flash.o
.text.FlashAddToBlock
- 0x08001c30 0x94 THUMB Debug/../../obj/flash.o
+ 0x08001754 0x84 THUMB Debug/../../obj/flash.o
.text.FlashInit
- 0x08001cc4 0x1c THUMB Debug/../../obj/flash.o
- 0x08001cc4 FlashInit
+ 0x080017d8 0x18 THUMB Debug/../../obj/flash.o
+ 0x080017d8 FlashInit
.text.FlashWrite
- 0x08001ce0 0x58 THUMB Debug/../../obj/flash.o
- 0x08001ce0 FlashWrite
+ 0x080017f0 0x50 THUMB Debug/../../obj/flash.o
+ 0x080017f0 FlashWrite
.text.FlashErase
- 0x08001d38 0x140 THUMB Debug/../../obj/flash.o
- 0x08001d38 FlashErase
+ 0x08001840 0x148 THUMB Debug/../../obj/flash.o
+ 0x08001840 FlashErase
.text.FlashWriteChecksum
- 0x08001e78 0x5c THUMB Debug/../../obj/flash.o
- 0x08001e78 FlashWriteChecksum
+ 0x08001988 0x50 THUMB Debug/../../obj/flash.o
+ 0x08001988 FlashWriteChecksum
.text.FlashVerifyChecksum
- 0x08001ed4 0x68 THUMB Debug/../../obj/flash.o
- 0x08001ed4 FlashVerifyChecksum
+ 0x080019d8 0x50 THUMB Debug/../../obj/flash.o
+ 0x080019d8 FlashVerifyChecksum
.text.FlashDone
- 0x08001f3c 0x58 THUMB Debug/../../obj/flash.o
- 0x08001f3c FlashDone
+ 0x08001a28 0x3c THUMB Debug/../../obj/flash.o
+ 0x08001a28 FlashDone
.text.FlashGetUserProgBaseAddress
- 0x08001f94 0xc THUMB Debug/../../obj/flash.o
- 0x08001f94 FlashGetUserProgBaseAddress
- .text.NvmInit 0x08001fa0 0xc THUMB Debug/../../obj/nvm.o
- 0x08001fa0 NvmInit
+ 0x08001a64 0x8 THUMB Debug/../../obj/flash.o
+ 0x08001a64 FlashGetUserProgBaseAddress
+ .text.NvmInit 0x08001a6c 0x8 THUMB Debug/../../obj/nvm.o
+ 0x08001a6c NvmInit
.text.NvmWrite
- 0x08001fac 0xc THUMB Debug/../../obj/nvm.o
- 0x08001fac NvmWrite
+ 0x08001a74 0x8 THUMB Debug/../../obj/nvm.o
+ 0x08001a74 NvmWrite
.text.NvmErase
- 0x08001fb8 0xc THUMB Debug/../../obj/nvm.o
- 0x08001fb8 NvmErase
+ 0x08001a7c 0x8 THUMB Debug/../../obj/nvm.o
+ 0x08001a7c NvmErase
.text.NvmVerifyChecksum
- 0x08001fc4 0xc THUMB Debug/../../obj/nvm.o
- 0x08001fc4 NvmVerifyChecksum
+ 0x08001a84 0x8 THUMB Debug/../../obj/nvm.o
+ 0x08001a84 NvmVerifyChecksum
.text.NvmGetUserProgBaseAddress
- 0x08001fd0 0xc THUMB Debug/../../obj/nvm.o
- 0x08001fd0 NvmGetUserProgBaseAddress
- .text.NvmDone 0x08001fdc 0x18 THUMB Debug/../../obj/nvm.o
- 0x08001fdc NvmDone
- .text.TimerReset
- 0x08001ff4 0x10 THUMB Debug/../../obj/timer.o
- 0x08001ff4 TimerReset
+ 0x08001a8c 0x8 THUMB Debug/../../obj/nvm.o
+ 0x08001a8c NvmGetUserProgBaseAddress
+ .text.NvmDone 0x08001a94 0x14 THUMB Debug/../../obj/nvm.o
+ 0x08001a94 NvmDone
.text.TimerInit
- 0x08002004 0x34 THUMB Debug/../../obj/timer.o
- 0x08002004 TimerInit
+ 0x08001aa8 0x24 THUMB Debug/../../obj/timer.o
+ 0x08001aa8 TimerInit
+ .text.TimerReset
+ 0x08001acc 0xc THUMB Debug/../../obj/timer.o
+ 0x08001acc TimerReset
.text.TimerUpdate
- 0x08002038 0x24 THUMB Debug/../../obj/timer.o
- 0x08002038 TimerUpdate
+ 0x08001ad8 0x1c THUMB Debug/../../obj/timer.o
+ 0x08001ad8 TimerUpdate
.text.TimerGet
- 0x0800205c 0x14 THUMB Debug/../../obj/timer.o
- 0x0800205c TimerGet
+ 0x08001af4 0x10 THUMB Debug/../../obj/timer.o
+ 0x08001af4 TimerGet
.text.IntToUnicode
- 0x08002070 0x3c THUMB Debug/../../obj/usb.o
- .text.UsbFifoMgrCreate
- 0x080020ac 0x40 THUMB Debug/../../obj/usb.o
+ 0x08001b04 0x30 THUMB Debug/../../obj/usb.o
.text.UsbFifoMgrWrite
- 0x080020ec 0x84 THUMB Debug/../../obj/usb.o
- .text.UsbTransmitByte
- 0x08002170 0x18 THUMB Debug/../../obj/usb.o
+ 0x08001b34 0x6c THUMB Debug/../../obj/usb.o
.text.UsbFifoMgrRead
- 0x08002188 0x80 THUMB Debug/../../obj/usb.o
- .text.UsbReceiveByte
- 0x08002208 0x18 THUMB Debug/../../obj/usb.o
- .text.UsbInit 0x08002220 0x74 THUMB Debug/../../obj/usb.o
- 0x08002220 UsbInit
- .text.UsbFree 0x08002294 0x10 THUMB Debug/../../obj/usb.o
- 0x08002294 UsbFree
+ 0x08001ba0 0x64 THUMB Debug/../../obj/usb.o
+ .text.UsbInit 0x08001c04 0x60 THUMB Debug/../../obj/usb.o
+ 0x08001c04 UsbInit
+ .text.UsbFree 0x08001c64 0xc THUMB Debug/../../obj/usb.o
+ 0x08001c64 UsbFree
.text.UsbTransmitPacket
- 0x080022a4 0x70 THUMB Debug/../../obj/usb.o
- 0x080022a4 UsbTransmitPacket
+ 0x08001c70 0x68 THUMB Debug/../../obj/usb.o
+ 0x08001c70 UsbTransmitPacket
.text.UsbReceivePacket
- 0x08002314 0xc8 THUMB Debug/../../obj/usb.o
- 0x08002314 UsbReceivePacket
+ 0x08001cd8 0x8c THUMB Debug/../../obj/usb.o
+ 0x08001cd8 UsbReceivePacket
.text.UsbTransmitPipeBulkIN
- 0x080023dc 0xbc THUMB Debug/../../obj/usb.o
- 0x080023dc UsbTransmitPipeBulkIN
+ 0x08001d64 0x98 THUMB Debug/../../obj/usb.o
+ 0x08001d64 UsbTransmitPipeBulkIN
.text.UsbReceivePipeBulkOUT
- 0x08002498 0x60 THUMB Debug/../../obj/usb.o
- 0x08002498 UsbReceivePipeBulkOUT
+ 0x08001dfc 0x54 THUMB Debug/../../obj/usb.o
+ 0x08001dfc UsbReceivePipeBulkOUT
.text.UsbGetSerialNum
- 0x080024f8 0x44 THUMB Debug/../../obj/usb.o
- 0x080024f8 UsbGetSerialNum
+ 0x08001e50 0x38 THUMB Debug/../../obj/usb.o
+ 0x08001e50 UsbGetSerialNum
.text.AssertFailure
- 0x0800253c 0x8 THUMB Debug/../../obj/assert.o
- 0x0800253c AssertFailure
+ 0x08001e88 0x8 THUMB Debug/../../obj/assert.o
+ 0x08001e88 AssertFailure
.text.BackDoorCheck
- 0x08002544 0x44 THUMB Debug/../../obj/backdoor.o
- 0x08002544 BackDoorCheck
+ 0x08001e90 0x38 THUMB Debug/../../obj/backdoor.o
+ 0x08001e90 BackDoorCheck
.text.BackDoorInit
- 0x08002588 0x28 THUMB Debug/../../obj/backdoor.o
- 0x08002588 BackDoorInit
+ 0x08001ec8 0x20 THUMB Debug/../../obj/backdoor.o
+ 0x08001ec8 BackDoorInit
.text.BootInit
- 0x080025b0 0x20 THUMB Debug/../../obj/boot.o
- 0x080025b0 BootInit
+ 0x08001ee8 0x1c THUMB Debug/../../obj/boot.o
+ 0x08001ee8 BootInit
.text.BootTask
- 0x080025d0 0x18 THUMB Debug/../../obj/boot.o
- 0x080025d0 BootTask
- .text.ComInit 0x080025e8 0x1c THUMB Debug/../../obj/com.o
- 0x080025e8 ComInit
- .text.ComTask 0x08002604 0x30 THUMB Debug/../../obj/com.o
- 0x08002604 ComTask
- .text.ComFree 0x08002634 0xc THUMB Debug/../../obj/com.o
- 0x08002634 ComFree
+ 0x08001f04 0x14 THUMB Debug/../../obj/boot.o
+ 0x08001f04 BootTask
+ .text.ComInit 0x08001f18 0x18 THUMB Debug/../../obj/com.o
+ 0x08001f18 ComInit
+ .text.ComTask 0x08001f30 0x24 THUMB Debug/../../obj/com.o
+ 0x08001f30 ComTask
+ .text.ComFree 0x08001f54 0x8 THUMB Debug/../../obj/com.o
+ 0x08001f54 ComFree
.text.ComTransmitPacket
- 0x08002640 0x20 THUMB Debug/../../obj/com.o
- 0x08002640 ComTransmitPacket
+ 0x08001f5c 0x1c THUMB Debug/../../obj/com.o
+ 0x08001f5c ComTransmitPacket
.text.ComGetActiveInterfaceMaxRxLen
- 0x08002660 0x2c THUMB Debug/../../obj/com.o
- 0x08002660 ComGetActiveInterfaceMaxRxLen
+ 0x08001f78 0x18 THUMB Debug/../../obj/com.o
+ 0x08001f78 ComGetActiveInterfaceMaxRxLen
.text.ComGetActiveInterfaceMaxTxLen
- 0x0800268c 0x2c THUMB Debug/../../obj/com.o
- 0x0800268c ComGetActiveInterfaceMaxTxLen
+ 0x08001f90 0x18 THUMB Debug/../../obj/com.o
+ 0x08001f90 ComGetActiveInterfaceMaxTxLen
.text.ComIsConnected
- 0x080026b8 0xc THUMB Debug/../../obj/com.o
- 0x080026b8 ComIsConnected
- .text.CopInit 0x080026c4 0x4 THUMB Debug/../../obj/cop.o
- 0x080026c4 CopInit
+ 0x08001fa8 0x8 THUMB Debug/../../obj/com.o
+ 0x08001fa8 ComIsConnected
+ .text.CopInit 0x08001fb0 0x4 THUMB Debug/../../obj/cop.o
+ 0x08001fb0 CopInit
.text.CopService
- 0x080026c8 0x4 THUMB Debug/../../obj/cop.o
- 0x080026c8 CopService
- .text.XcpProtectResources
- 0x080026cc 0x10 THUMB Debug/../../obj/xcp.o
+ 0x08001fb4 0x4 THUMB Debug/../../obj/cop.o
+ 0x08001fb4 CopService
.text.XcpSetCtoError
- 0x080026dc 0x1c THUMB Debug/../../obj/xcp.o
- .text.XcpInit 0x080026f8 0x20 THUMB Debug/../../obj/xcp.o
- 0x080026f8 XcpInit
+ 0x08001fb8 0x14 THUMB Debug/../../obj/xcp.o
+ .text.XcpInit 0x08001fcc 0x1c THUMB Debug/../../obj/xcp.o
+ 0x08001fcc XcpInit
.text.XcpIsConnected
- 0x08002718 0x14 THUMB Debug/../../obj/xcp.o
- 0x08002718 XcpIsConnected
+ 0x08001fe8 0x10 THUMB Debug/../../obj/xcp.o
+ 0x08001fe8 XcpIsConnected
.text.XcpPacketTransmitted
- 0x0800272c 0x14 THUMB Debug/../../obj/xcp.o
- 0x0800272c XcpPacketTransmitted
+ 0x08001ff8 0x10 THUMB Debug/../../obj/xcp.o
+ 0x08001ff8 XcpPacketTransmitted
.text.XcpPacketReceived
- 0x08002740 0x3fc THUMB Debug/../../obj/xcp.o
- 0x08002740 XcpPacketReceived
- .text.libdebugio.__do_debug_operation_mempoll
- 0x08002b3c 0x38 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x08002b3c __do_debug_operation_mempoll
- .text.libc.__debug_io_lock
- 0x08002b74 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- 0x08002b74 __debug_io_lock
- .text.libc.__debug_io_unlock
- 0x08002b78 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- 0x08002b78 __debug_io_unlock
- 0x08002b7c __text_end__ = (__text_start__ + SIZEOF (.text))
- 0x08002b7c __text_load_end__ = __text_end__
+ 0x08002008 0x314 THUMB Debug/../../obj/xcp.o
+ 0x08002008 XcpPacketReceived
+ 0x0800231c __text_end__ = (__text_start__ + SIZEOF (.text))
+ 0x0800231c __text_load_end__ = __text_end__
.vfp11_veneer 0x00000000 0x0
.vfp11_veneer 0x00000000 0x0 linker stubs
.v4_bx 0x00000000 0x0
.v4_bx 0x00000000 0x0 linker stubs
- 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= __FLASH_segment_end__)), error: .text is too large to fit in FLASH memory segment)
- 0x08002b7c __dtors_load_start__ = ALIGN (__text_end__, 0x4)
-.dtors 0x08002b7c 0x0
- 0x08002b7c __dtors_start__ = .
+.iplt 0x00000000 0x0
+ .iplt 0x00000000 0x0 THUMB Debug/../../obj/hooks.o
+ 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= __FLASH_segment_end__)), error: .text is too large to fit in FLASH memory segment)
+ 0x0800231c __dtors_load_start__ = ALIGN (__text_end__, 0x4)
+
+.dtors 0x0800231c 0x0
+ 0x0800231c __dtors_start__ = .
*(SORT(.dtors.*))
*(.dtors)
*(.fini_array .fini_array.*)
- 0x08002b7c __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
- 0x08002b7c __dtors_load_end__ = __dtors_end__
+ 0x0800231c __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
+ 0x0800231c __dtors_load_end__ = __dtors_end__
0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= __FLASH_segment_end__)), error: .dtors is too large to fit in FLASH memory segment)
- 0x08002b7c __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
+ 0x0800231c __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
-.ctors 0x08002b7c 0x0
- 0x08002b7c __ctors_start__ = .
+.ctors 0x0800231c 0x0
+ 0x0800231c __ctors_start__ = .
*(SORT(.ctors.*))
*(.ctors)
*(.init_array .init_array.*)
- 0x08002b7c __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
- 0x08002b7c __ctors_load_end__ = __ctors_end__
+ 0x0800231c __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
+ 0x0800231c __ctors_load_end__ = __ctors_end__
0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= __FLASH_segment_end__)), error: .ctors is too large to fit in FLASH memory segment)
- 0x08002b7c __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
+ 0x0800231c __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
-.rodata 0x08002b7c 0x2c4
- 0x08002b7c __rodata_start__ = .
+.rodata 0x0800231c 0x2c4
+ 0x0800231c __rodata_start__ = .
*(.rodata .rodata.* .gnu.linkonce.r.*)
.rodata.str1.4
- 0x08002b7c 0x63 THUMB Debug/../../obj/main.o
- 0x64 (size before relaxing)
- *fill* 0x08002bdf 0x1 00
+ 0x0800231c 0x63 THUMB Debug/../../obj/main.o
+ *fill* 0x0800237f 0x1
.rodata.Bulk_DeviceDescriptor
- 0x08002be0 0x14 THUMB Debug/../../obj/usb_desc.o
- 0x08002be0 Bulk_DeviceDescriptor
+ 0x08002380 0x12 THUMB Debug/../../obj/usb_desc.o
+ 0x08002380 Bulk_DeviceDescriptor
+ *fill* 0x08002392 0x2
.rodata.Bulk_StringLangID
- 0x08002bf4 0x4 THUMB Debug/../../obj/usb_desc.o
- 0x08002bf4 Bulk_StringLangID
+ 0x08002394 0x4 THUMB Debug/../../obj/usb_desc.o
+ 0x08002394 Bulk_StringLangID
.rodata.Bulk_StringProduct
- 0x08002bf8 0x28 THUMB Debug/../../obj/usb_desc.o
- 0x08002bf8 Bulk_StringProduct
+ 0x08002398 0x26 THUMB Debug/../../obj/usb_desc.o
+ 0x08002398 Bulk_StringProduct
+ *fill* 0x080023be 0x2
.rodata.Bulk_ConfigDescriptor
- 0x08002c20 0x20 THUMB Debug/../../obj/usb_desc.o
- 0x08002c20 Bulk_ConfigDescriptor
+ 0x080023c0 0x20 THUMB Debug/../../obj/usb_desc.o
+ 0x080023c0 Bulk_ConfigDescriptor
.rodata.Bulk_StringVendor
- 0x08002c40 0x1c THUMB Debug/../../obj/usb_desc.o
- 0x08002c40 Bulk_StringVendor
+ 0x080023e0 0x1a THUMB Debug/../../obj/usb_desc.o
+ 0x080023e0 Bulk_StringVendor
+ *fill* 0x080023fa 0x2
.rodata.Bulk_StringInterface
- 0x08002c5c 0x2c THUMB Debug/../../obj/usb_desc.o
- 0x08002c5c Bulk_StringInterface
+ 0x080023fc 0x2c THUMB Debug/../../obj/usb_desc.o
+ 0x080023fc Bulk_StringInterface
.rodata.str1.4
- 0x08002c88 0x90 THUMB Debug/../../obj/vectors.o
+ 0x08002428 0x90 THUMB Debug/../../obj/vectors.o
.rodata.flashLayout
- 0x08002d18 0x9c THUMB Debug/../../obj/flash.o
+ 0x080024b8 0x9c THUMB Debug/../../obj/flash.o
.rodata.str1.4
- 0x08002db4 0x84 THUMB Debug/../../obj/usb.o
+ 0x08002554 0x84 THUMB Debug/../../obj/usb.o
+ 0x81 (size before relaxing)
.rodata.xcpStationId
- 0x08002e38 0x8 THUMB Debug/../../obj/xcp.o
- 0x08002e40 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
- 0x08002e40 __rodata_load_end__ = __rodata_end__
+ 0x080025d8 0x8 THUMB Debug/../../obj/xcp.o
+ 0x080025e0 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
+ 0x080025e0 __rodata_load_end__ = __rodata_end__
+
+.rel.dyn 0x08000000 0x0
+ .rel.iplt 0x08000000 0x0 THUMB Debug/../../obj/hooks.o
0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= __FLASH_segment_end__)), error: .rodata is too large to fit in FLASH memory segment)
- 0x08002e40 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4)
+ 0x080025e0 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4)
-.ARM.exidx 0x08002e40 0x0
- 0x08002e40 __ARM.exidx_start__ = .
- 0x08002e40 __exidx_start = __ARM.exidx_start__
+.ARM.exidx 0x080025e0 0x0
+ 0x080025e0 __ARM.exidx_start__ = .
+ 0x080025e0 __exidx_start = __ARM.exidx_start__
*(.ARM.exidx .ARM.exidx.*)
- 0x08002e40 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx))
- 0x08002e40 __exidx_end = __ARM.exidx_end__
- 0x08002e40 __ARM.exidx_load_end__ = __ARM.exidx_end__
+ 0x080025e0 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx))
+ 0x080025e0 __exidx_end = __ARM.exidx_end__
+ 0x080025e0 __ARM.exidx_load_end__ = __ARM.exidx_end__
0x00000001 . = ASSERT (((__ARM.exidx_end__ >= __FLASH_segment_start__) && (__ARM.exidx_end__ <= __FLASH_segment_end__)), error: .ARM.exidx is too large to fit in FLASH memory segment)
- 0x08002e40 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4)
+ 0x080025e0 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4)
-.fast 0x20000000 0x0 load address 0x08002e40
+.fast 0x20000000 0x0 load address 0x080025e0
0x20000000 __fast_start__ = .
*(.fast .fast.*)
0x20000000 __fast_end__ = (__fast_start__ + SIZEOF (.fast))
- 0x08002e40 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
+ 0x080025e0 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
0x00000001 . = ASSERT (((__fast_load_end__ >= __FLASH_segment_start__) && (__fast_load_end__ <= __FLASH_segment_end__)), error: .fast is too large to fit in FLASH memory segment)
.fast_run 0x20000000 0x0
@@ -918,9 +2591,9 @@ Linker script and memory map
0x20000000 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run))
0x20000000 __fast_run_load_end__ = __fast_run_end__
0x00000001 . = ASSERT (((__fast_run_end__ >= __SRAM_segment_start__) && (__fast_run_end__ <= __SRAM_segment_end__)), error: .fast_run is too large to fit in SRAM memory segment)
- 0x08002e40 __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4)
+ 0x080025e0 __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4)
-.data 0x20000000 0xf0 load address 0x08002e40
+.data 0x20000000 0xeb load address 0x080025e0
0x20000000 __data_start__ = .
*(.data .data.* .gnu.linkonce.d.*)
.data.Bulk_StringSerial
@@ -951,178 +2624,176 @@ Linker script and memory map
0x200000c0 0x28 THUMB Debug/../../obj/usb_prop.o
0x200000c0 String_Descriptor
.data.Device_Table
- 0x200000e8 0x4 THUMB Debug/../../obj/usb_prop.o
+ 0x200000e8 0x2 THUMB Debug/../../obj/usb_prop.o
0x200000e8 Device_Table
.data.comActiveInterface
- 0x200000ec 0x4 THUMB Debug/../../obj/com.o
- 0x200000f0 __data_end__ = (__data_start__ + SIZEOF (.data))
- 0x08002f30 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+ 0x200000ea 0x1 THUMB Debug/../../obj/com.o
+ 0x200000eb __data_end__ = (__data_start__ + SIZEOF (.data))
+ 0x080026cb __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+
+.igot.plt 0x00000000 0x0
+ .igot.plt 0x00000000 0x0 THUMB Debug/../../obj/hooks.o
0x00000001 . = ASSERT (((__data_load_end__ >= __FLASH_segment_start__) && (__data_load_end__ <= __FLASH_segment_end__)), error: .data is too large to fit in FLASH memory segment)
-.data_run 0x20000000 0xf0 load address 0x08002e40
+.data_run 0x20000000 0xeb load address 0x080025e0
0x20000000 __data_run_start__ = .
- 0x200000f0 . = MAX ((__data_run_start__ + SIZEOF (.data)), .)
- *fill* 0x20000000 0xf0 00
- 0x200000f0 __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run))
- 0x200000f0 __data_run_load_end__ = __data_run_end__
+ 0x200000eb . = MAX ((__data_run_start__ + SIZEOF (.data)), .)
+ *fill* 0x20000000 0xeb
+ 0x200000eb __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run))
+ 0x200000eb __data_run_load_end__ = __data_run_end__
0x00000001 . = ASSERT (((__data_run_end__ >= __SRAM_segment_start__) && (__data_run_end__ <= __SRAM_segment_end__)), error: .data_run is too large to fit in SRAM memory segment)
- 0x200000f0 __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
+ 0x200000ec __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
-.bss 0x200000f0 0x67c
- 0x200000f0 __bss_start__ = .
+.bss 0x200000ec 0x660
+ 0x200000ec __bss_start__ = .
*(.bss .bss.* .gnu.linkonce.b.*)
- .bss.initialized.1734
- 0x200000f0 0x1 THUMB Debug/../../obj/hooks.o
- *fill* 0x200000f1 0x3 00
+ .bss.initialized.4784
+ 0x200000ec 0x1 THUMB Debug/../../obj/hooks.o
.bss.Data_Mul_MaxPacketSize
- 0x200000f4 0x4 THUMB Debug/../../obj/usb_core.o
- 0x200000f4 Data_Mul_MaxPacketSize
+ 0x200000ed 0x1 THUMB Debug/../../obj/usb_core.o
+ 0x200000ed Data_Mul_MaxPacketSize
+ *fill* 0x200000ee 0x2
.bss.StatusInfo
- 0x200000f8 0x4 THUMB Debug/../../obj/usb_core.o
- 0x200000f8 StatusInfo
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+ 0x200000f0 StatusInfo
+ *fill* 0x200000f2 0x2
.bss.Device_Info
- 0x200000fc 0x24 THUMB Debug/../../obj/usb_init.o
- 0x200000fc Device_Info
- .bss.EPindex 0x20000120 0x1 THUMB Debug/../../obj/usb_init.o
- 0x20000120 EPindex
- *fill* 0x20000121 0x3 00
+ 0x200000f4 0x1c THUMB Debug/../../obj/usb_init.o
+ 0x200000f4 Device_Info
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+ 0x20000110 EPindex
+ *fill* 0x20000111 0x3
.bss.pInformation
- 0x20000124 0x4 THUMB Debug/../../obj/usb_init.o
- 0x20000124 pInformation
+ 0x20000114 0x4 THUMB Debug/../../obj/usb_init.o
+ 0x20000114 pInformation
.bss.pUser_Standard_Requests
- 0x20000128 0x4 THUMB Debug/../../obj/usb_init.o
- 0x20000128 pUser_Standard_Requests
+ 0x20000118 0x4 THUMB Debug/../../obj/usb_init.o
+ 0x20000118 pUser_Standard_Requests
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- 0x2000012c 0x2 THUMB Debug/../../obj/usb_init.o
- 0x2000012c wInterrupt_Mask
- *fill* 0x2000012e 0x2 00
+ 0x2000011c 0x2 THUMB Debug/../../obj/usb_init.o
+ 0x2000011c wInterrupt_Mask
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.bss.pProperty
- 0x20000130 0x4 THUMB Debug/../../obj/usb_init.o
- 0x20000130 pProperty
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+ 0x20000120 pProperty
.bss.SaveRState
- 0x20000134 0x2 THUMB Debug/../../obj/usb_int.o
- 0x20000134 SaveRState
+ 0x20000124 0x2 THUMB Debug/../../obj/usb_int.o
+ 0x20000124 SaveRState
.bss.SaveTState
- 0x20000136 0x2 THUMB Debug/../../obj/usb_int.o
- 0x20000136 SaveTState
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+ 0x20000126 SaveTState
.bss.bIntPackSOF
- 0x20000138 0x1 THUMB Debug/../../obj/usb_istr.o
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- *fill* 0x20000139 0x1 00
- .bss.wIstr 0x2000013a 0x2 THUMB Debug/../../obj/usb_istr.o
- 0x2000013a wIstr
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+ 0x20000128 bIntPackSOF
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+ 0x2000012a wIstr
.bss.bDeviceState
- 0x2000013c 0x4 THUMB Debug/../../obj/usb_pwr.o
- 0x2000013c bDeviceState
+ 0x2000012c 0x4 THUMB Debug/../../obj/usb_pwr.o
+ 0x2000012c bDeviceState
.bss.bootBlockInfo
- 0x20000140 0x204 THUMB Debug/../../obj/flash.o
+ 0x20000130 0x204 THUMB Debug/../../obj/flash.o
.bss.blockInfo
- 0x20000344 0x204 THUMB Debug/../../obj/flash.o
+ 0x20000334 0x204 THUMB Debug/../../obj/flash.o
.bss.millisecond_counter
- 0x20000548 0x4 THUMB Debug/../../obj/timer.o
- .bss.USB_Rx_Buffer.2246
- 0x2000054c 0x40 THUMB Debug/../../obj/usb.o
- .bss.xcpCtoRxInProgress.2216
- 0x2000058c 0x1 THUMB Debug/../../obj/usb.o
- *fill* 0x2000058d 0x3 00
- .bss.USB_Tx_Buffer.2235
- 0x20000590 0x40 THUMB Debug/../../obj/usb.o
- .bss.xcpCtoRxLength.2215
- 0x200005d0 0x1 THUMB Debug/../../obj/usb.o
- *fill* 0x200005d1 0x3 00
+ 0x20000538 0x4 THUMB Debug/../../obj/timer.o
+ .bss.xcpCtoReqPacket.5264
+ 0x2000053c 0x40 THUMB Debug/../../obj/usb.o
+ .bss.USB_Tx_Buffer.5285
+ 0x2000057c 0x40 THUMB Debug/../../obj/usb.o
+ .bss.xcpCtoRxLength.5265
+ 0x200005bc 0x1 THUMB Debug/../../obj/usb.o
+ .bss.xcpCtoRxInProgress.5266
+ 0x200005bd 0x1 THUMB Debug/../../obj/usb.o
+ *fill* 0x200005be 0x2
.bss.fifoCtrlFree
- 0x200005d4 0x4 THUMB Debug/../../obj/usb.o
- .bss.fifoCtrl 0x200005d8 0x30 THUMB Debug/../../obj/usb.o
+ 0x200005c0 0x4 THUMB Debug/../../obj/usb.o
+ .bss.fifoCtrl 0x200005c4 0x30 THUMB Debug/../../obj/usb.o
.bss.fifoPipeBulkOUT
- 0x20000608 0x44 THUMB Debug/../../obj/usb.o
- .bss.xcpCtoReqPacket.2214
- 0x2000064c 0x40 THUMB Debug/../../obj/usb.o
+ 0x200005f4 0x41 THUMB Debug/../../obj/usb.o
+ *fill* 0x20000635 0x3
+ .bss.USB_Rx_Buffer.5296
+ 0x20000638 0x40 THUMB Debug/../../obj/usb.o
.bss.fifoPipeBulkIN
- 0x2000068c 0x44 THUMB Debug/../../obj/usb.o
+ 0x20000678 0x41 THUMB Debug/../../obj/usb.o
.bss.backdoorOpen
- 0x200006d0 0x1 THUMB Debug/../../obj/backdoor.o
- *fill* 0x200006d1 0x3 00
+ 0x200006b9 0x1 THUMB Debug/../../obj/backdoor.o
+ *fill* 0x200006ba 0x2
.bss.backdoorOpenTime
- 0x200006d4 0x4 THUMB Debug/../../obj/backdoor.o
- .bss.xcpCtoReqPacket.894
- 0x200006d8 0x40 THUMB Debug/../../obj/com.o
- .bss.xcpInfo 0x20000718 0x4c THUMB Debug/../../obj/xcp.o
- .bss.libdebugio.dbgCommWord
- 0x20000764 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x20000764 dbgCommWord
- .bss.libdebugio.dbgCntrlWord_mempoll
- 0x20000768 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x20000768 dbgCntrlWord_mempoll
+ 0x200006bc 0x4 THUMB Debug/../../obj/backdoor.o
+ .bss.xcpCtoReqPacket.3796
+ 0x200006c0 0x3f THUMB Debug/../../obj/com.o
+ *fill* 0x200006ff 0x1
+ .bss.xcpInfo 0x20000700 0x4c THUMB Debug/../../obj/xcp.o
*(COMMON)
- 0x2000076c __bss_end__ = (__bss_start__ + SIZEOF (.bss))
- 0x2000076c __bss_load_end__ = __bss_end__
+ 0x2000074c __bss_end__ = (__bss_start__ + SIZEOF (.bss))
+ 0x2000074c __bss_load_end__ = __bss_end__
0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= __SRAM_segment_end__)), error: .bss is too large to fit in SRAM memory segment)
- 0x2000076c __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
+ 0x2000074c __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
-.non_init 0x2000076c 0x0
- 0x2000076c __non_init_start__ = .
+.non_init 0x2000074c 0x0
+ 0x2000074c __non_init_start__ = .
*(.non_init .non_init.*)
- 0x2000076c __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
- 0x2000076c __non_init_load_end__ = __non_init_end__
+ 0x2000074c __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
+ 0x2000074c __non_init_load_end__ = __non_init_end__
0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= __SRAM_segment_end__)), error: .non_init is too large to fit in SRAM memory segment)
- 0x2000076c __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
+ 0x2000074c __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
-.heap 0x2000076c 0x80
- 0x2000076c __heap_start__ = .
+.heap 0x2000074c 0x80
+ 0x2000074c __heap_start__ = .
*(.heap .heap.*)
- 0x200007ec . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
- *fill* 0x2000076c 0x80 00
- 0x200007ec __heap_end__ = (__heap_start__ + SIZEOF (.heap))
- 0x200007ec __heap_load_end__ = __heap_end__
+ 0x200007cc . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
+ *fill* 0x2000074c 0x80
+ 0x200007cc __heap_end__ = (__heap_start__ + SIZEOF (.heap))
+ 0x200007cc __heap_load_end__ = __heap_end__
0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= __SRAM_segment_end__)), error: .heap is too large to fit in SRAM memory segment)
- 0x200007ec __stack_load_start__ = ALIGN (__heap_end__, 0x4)
+ 0x200007cc __stack_load_start__ = ALIGN (__heap_end__, 0x4)
-.stack 0x200007ec 0x200
- 0x200007ec __stack_start__ = .
+.stack 0x200007cc 0x200
+ 0x200007cc __stack_start__ = .
*(.stack .stack.*)
- 0x200009ec . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
- *fill* 0x200007ec 0x200 00
- 0x200009ec __stack_end__ = (__stack_start__ + SIZEOF (.stack))
- 0x200009ec __stack_load_end__ = __stack_end__
+ 0x200009cc . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
+ *fill* 0x200007cc 0x200
+ 0x200009cc __stack_end__ = (__stack_start__ + SIZEOF (.stack))
+ 0x200009cc __stack_load_end__ = __stack_end__
0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= __SRAM_segment_end__)), error: .stack is too large to fit in SRAM memory segment)
- 0x200009ec __stack_process_load_start__ = ALIGN (__stack_end__, 0x4)
+ 0x200009cc __stack_process_load_start__ = ALIGN (__stack_end__, 0x4)
-.stack_process 0x200009ec 0x0
- 0x200009ec __stack_process_start__ = .
+.stack_process 0x200009cc 0x0
+ 0x200009cc __stack_process_start__ = .
*(.stack_process .stack_process.*)
- 0x200009ec . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4)
- 0x200009ec __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process))
- 0x200009ec __stack_process_load_end__ = __stack_process_end__
+ 0x200009cc . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4)
+ 0x200009cc __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process))
+ 0x200009cc __stack_process_load_end__ = __stack_process_end__
0x00000001 . = ASSERT (((__stack_process_end__ >= __SRAM_segment_start__) && (__stack_process_end__ <= __SRAM_segment_end__)), error: .stack_process is too large to fit in SRAM memory segment)
- 0x200009ec __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4)
+ 0x200009cc __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4)
-.tbss 0x200009ec 0x0
- 0x200009ec __tbss_start__ = .
+.tbss 0x200009cc 0x0
+ 0x200009cc __tbss_start__ = .
*(.tbss .tbss.*)
- 0x200009ec __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss))
- 0x200009ec __tbss_load_end__ = __tbss_end__
+ 0x200009cc __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss))
+ 0x200009cc __tbss_load_end__ = __tbss_end__
0x00000001 . = ASSERT (((__tbss_end__ >= __SRAM_segment_start__) && (__tbss_end__ <= __SRAM_segment_end__)), error: .tbss is too large to fit in SRAM memory segment)
- 0x08002f30 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
+ 0x080026cc __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
-.tdata 0x200009ec 0x0 load address 0x08002f30
- 0x200009ec __tdata_start__ = .
+.tdata 0x200009cc 0x0 load address 0x080026cc
+ 0x200009cc __tdata_start__ = .
*(.tdata .tdata.*)
- 0x200009ec __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata))
- 0x08002f30 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata))
- 0x08002f30 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata))
+ 0x200009cc __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata))
+ 0x080026cc __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata))
+ 0x080026cc __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata))
0x00000001 . = ASSERT (((__tdata_load_end__ >= __FLASH_segment_start__) && (__tdata_load_end__ <= __FLASH_segment_end__)), error: .tdata is too large to fit in FLASH memory segment)
-.tdata_run 0x200009ec 0x0
- 0x200009ec __tdata_run_start__ = .
- 0x200009ec . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .)
- 0x200009ec __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run))
- 0x200009ec __tdata_run_load_end__ = __tdata_run_end__
- 0x200009ec __SRAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run))
+.tdata_run 0x200009cc 0x0
+ 0x200009cc __tdata_run_start__ = .
+ 0x200009cc . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .)
+ 0x200009cc __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run))
+ 0x200009cc __tdata_run_load_end__ = __tdata_run_end__
+ 0x200009cc __SRAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run))
0x00000001 . = ASSERT (((__tdata_run_end__ >= __SRAM_segment_start__) && (__tdata_run_end__ <= __SRAM_segment_end__)), error: .tdata_run is too large to fit in SRAM memory segment)
START GROUP
LOAD THUMB Debug/../../obj/hooks.o
LOAD THUMB Debug/../../obj/main.o
-LOAD THUMB Debug/../../obj/core_cm3.o
LOAD THUMB Debug/../../obj/system_stm32f10x.o
LOAD THUMB Debug/../../obj/usb_core.o
LOAD THUMB Debug/../../obj/usb_init.o
@@ -1151,438 +2822,476 @@ LOAD THUMB Debug/../../obj/boot.o
LOAD THUMB Debug/../../obj/com.o
LOAD THUMB Debug/../../obj/cop.o
LOAD THUMB Debug/../../obj/xcp.o
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcm_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcpp_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_targetio_impl_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libcm_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libdebugio_mempoll_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libcpp_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libdebugio_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfprintf_v7m_t_le_eabi.o
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfscanf_v7m_t_le_eabi.o
END GROUP
OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/../bin/openblt_olimex_stm32h103.elf elf32-littlearm)
-.debug_frame 0x00000000 0x1b88
+.debug_frame 0x00000000 0x1144
.debug_frame 0x00000000 0x50 THUMB Debug/../../obj/hooks.o
.debug_frame 0x00000050 0x30 THUMB Debug/../../obj/main.o
- .debug_frame 0x00000080 0x170 THUMB Debug/../../obj/core_cm3.o
- .debug_frame 0x000001f0 0x38 THUMB Debug/../../obj/system_stm32f10x.o
- .debug_frame 0x00000228 0x1d4 THUMB Debug/../../obj/usb_core.o
- .debug_frame 0x000003fc 0x2c THUMB Debug/../../obj/usb_init.o
- .debug_frame 0x00000428 0x54 THUMB Debug/../../obj/usb_int.o
- .debug_frame 0x0000047c 0x48 THUMB Debug/../../obj/usb_mem.o
- .debug_frame 0x000004c4 0x3f4 THUMB Debug/../../obj/usb_regs.o
- .debug_frame 0x000008b8 0x60 THUMB Debug/../../obj/usb_sil.o
- .debug_frame 0x00000918 0x64 THUMB Debug/../../obj/usb_endp.o
- .debug_frame 0x0000097c 0x2c THUMB Debug/../../obj/usb_istr.o
- .debug_frame 0x000009a8 0x134 THUMB Debug/../../obj/usb_prop.o
- .debug_frame 0x00000adc 0xa0 THUMB Debug/../../obj/usb_pwr.o
- .debug_frame 0x00000b7c 0x30 THUMB Debug/../../obj/cpu_comp.o
- .debug_frame 0x00000bac 0x2c THUMB Debug/../../obj/vectors.o
- .debug_frame 0x00000bd8 0x84 THUMB Debug/../../obj/cpu.o
- .debug_frame 0x00000c5c 0x1b8 THUMB Debug/../../obj/flash.o
- .debug_frame 0x00000e14 0xd4 THUMB Debug/../../obj/nvm.o
- .debug_frame 0x00000ee8 0x68 THUMB Debug/../../obj/timer.o
- .debug_frame 0x00000f50 0x1e4 THUMB Debug/../../obj/usb.o
- .debug_frame 0x00001134 0x2c THUMB Debug/../../obj/assert.o
- .debug_frame 0x00001160 0x48 THUMB Debug/../../obj/backdoor.o
- .debug_frame 0x000011a8 0x48 THUMB Debug/../../obj/boot.o
- .debug_frame 0x000011f0 0xbc THUMB Debug/../../obj/com.o
- .debug_frame 0x000012ac 0x30 THUMB Debug/../../obj/cop.o
- .debug_frame 0x000012dc 0x80 THUMB Debug/../../obj/xcp.o
- .debug_frame 0x0000135c 0x78c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .debug_frame 0x00001ae8 0xa0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
+ .debug_frame 0x00000080 0x1fc THUMB Debug/../../obj/usb_core.o
+ .debug_frame 0x0000027c 0x2c THUMB Debug/../../obj/usb_init.o
+ .debug_frame 0x000002a8 0x60 THUMB Debug/../../obj/usb_int.o
+ .debug_frame 0x00000308 0x44 THUMB Debug/../../obj/usb_mem.o
+ .debug_frame 0x0000034c 0x3f8 THUMB Debug/../../obj/usb_regs.o
+ .debug_frame 0x00000744 0x60 THUMB Debug/../../obj/usb_sil.o
+ .debug_frame 0x000007a4 0x64 THUMB Debug/../../obj/usb_endp.o
+ .debug_frame 0x00000808 0x2c THUMB Debug/../../obj/usb_istr.o
+ .debug_frame 0x00000834 0x134 THUMB Debug/../../obj/usb_prop.o
+ .debug_frame 0x00000968 0xa0 THUMB Debug/../../obj/usb_pwr.o
+ .debug_frame 0x00000a08 0x30 THUMB Debug/../../obj/cpu_comp.o
+ .debug_frame 0x00000a38 0x2c THUMB Debug/../../obj/vectors.o
+ .debug_frame 0x00000a64 0x74 THUMB Debug/../../obj/cpu.o
+ .debug_frame 0x00000ad8 0x180 THUMB Debug/../../obj/flash.o
+ .debug_frame 0x00000c58 0xd4 THUMB Debug/../../obj/nvm.o
+ .debug_frame 0x00000d2c 0x5c THUMB Debug/../../obj/timer.o
+ .debug_frame 0x00000d88 0x1a4 THUMB Debug/../../obj/usb.o
+ .debug_frame 0x00000f2c 0x2c THUMB Debug/../../obj/assert.o
+ .debug_frame 0x00000f58 0x48 THUMB Debug/../../obj/backdoor.o
+ .debug_frame 0x00000fa0 0x48 THUMB Debug/../../obj/boot.o
+ .debug_frame 0x00000fe8 0xbc THUMB Debug/../../obj/com.o
+ .debug_frame 0x000010a4 0x30 THUMB Debug/../../obj/cop.o
+ .debug_frame 0x000010d4 0x70 THUMB Debug/../../obj/xcp.o
-.debug_info 0x00000000 0x6cb6
- .debug_info 0x00000000 0x25f THUMB Debug/../../obj/hooks.o
- .debug_info 0x0000025f 0x31f THUMB Debug/../../obj/main.o
- .debug_info 0x0000057e 0x53d THUMB Debug/../../obj/core_cm3.o
- .debug_info 0x00000abb 0x4c6 THUMB Debug/../../obj/system_stm32f10x.o
- .debug_info 0x00000f81 0xd09 THUMB Debug/../../obj/usb_core.o
- .debug_info 0x00001c8a 0x4db THUMB Debug/../../obj/usb_init.o
- .debug_info 0x00002165 0x232 THUMB Debug/../../obj/usb_int.o
- .debug_info 0x00002397 0x1bb THUMB Debug/../../obj/usb_mem.o
- .debug_info 0x00002552 0xd35 THUMB Debug/../../obj/usb_regs.o
- .debug_info 0x00003287 0x179 THUMB Debug/../../obj/usb_sil.o
- .debug_info 0x00003400 0x19d THUMB Debug/../../obj/usb_desc.o
- .debug_info 0x0000359d 0x124 THUMB Debug/../../obj/usb_endp.o
- .debug_info 0x000036c1 0x2ad THUMB Debug/../../obj/usb_istr.o
- .debug_info 0x0000396e 0x97e THUMB Debug/../../obj/usb_prop.o
- .debug_info 0x000042ec 0x2e5 THUMB Debug/../../obj/usb_pwr.o
- .debug_info 0x000045d1 0x8a THUMB Debug/../../obj/cpu_comp.o
- .debug_info 0x0000465b 0x110 THUMB Debug/../../obj/cstart.o
- .debug_info 0x0000476b 0xf5 THUMB Debug/../../obj/vectors.o
- .debug_info 0x00004860 0x5e THUMB Debug/../../obj/can.o
- .debug_info 0x000048be 0x153 THUMB Debug/../../obj/cpu.o
- .debug_info 0x00004a11 0x6a5 THUMB Debug/../../obj/flash.o
- .debug_info 0x000050b6 0x190 THUMB Debug/../../obj/nvm.o
- .debug_info 0x00005246 0x117 THUMB Debug/../../obj/timer.o
- .debug_info 0x0000535d 0x5e THUMB Debug/../../obj/uart.o
- .debug_info 0x000053bb 0x892 THUMB Debug/../../obj/usb.o
- .debug_info 0x00005c4d 0xb6 THUMB Debug/../../obj/assert.o
- .debug_info 0x00005d03 0xc4 THUMB Debug/../../obj/backdoor.o
- .debug_info 0x00005dc7 0x8c THUMB Debug/../../obj/boot.o
- .debug_info 0x00005e53 0x1d7 THUMB Debug/../../obj/com.o
- .debug_info 0x0000602a 0x8a THUMB Debug/../../obj/cop.o
- .debug_info 0x000060b4 0x616 THUMB Debug/../../obj/xcp.o
- .debug_info 0x000066ca 0x51f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .debug_info 0x00006be9 0xcd C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
+.debug_info 0x00000000 0x6839
+ .debug_info 0x00000000 0x228 THUMB Debug/../../obj/hooks.o
+ .debug_info 0x00000228 0x32f THUMB Debug/../../obj/main.o
+ .debug_info 0x00000557 0xe36 THUMB Debug/../../obj/usb_core.o
+ .debug_info 0x0000138d 0x429 THUMB Debug/../../obj/usb_init.o
+ .debug_info 0x000017b6 0x206 THUMB Debug/../../obj/usb_int.o
+ .debug_info 0x000019bc 0x1aa THUMB Debug/../../obj/usb_mem.o
+ .debug_info 0x00001b66 0xccc THUMB Debug/../../obj/usb_regs.o
+ .debug_info 0x00002832 0x21e THUMB Debug/../../obj/usb_sil.o
+ .debug_info 0x00002a50 0x18e THUMB Debug/../../obj/usb_desc.o
+ .debug_info 0x00002bde 0x144 THUMB Debug/../../obj/usb_endp.o
+ .debug_info 0x00002d22 0x278 THUMB Debug/../../obj/usb_istr.o
+ .debug_info 0x00002f9a 0xaa7 THUMB Debug/../../obj/usb_prop.o
+ .debug_info 0x00003a41 0x31e THUMB Debug/../../obj/usb_pwr.o
+ .debug_info 0x00003d5f 0x80 THUMB Debug/../../obj/cpu_comp.o
+ .debug_info 0x00003ddf 0x110 THUMB Debug/../../obj/cstart.o
+ .debug_info 0x00003eef 0x111 THUMB Debug/../../obj/vectors.o
+ .debug_info 0x00004000 0x1e3 THUMB Debug/../../obj/cpu.o
+ .debug_info 0x000041e3 0x8cd THUMB Debug/../../obj/flash.o
+ .debug_info 0x00004ab0 0x24e THUMB Debug/../../obj/nvm.o
+ .debug_info 0x00004cfe 0x127 THUMB Debug/../../obj/timer.o
+ .debug_info 0x00004e25 0xbaa THUMB Debug/../../obj/usb.o
+ .debug_info 0x000059cf 0xc2 THUMB Debug/../../obj/assert.o
+ .debug_info 0x00005a91 0x110 THUMB Debug/../../obj/backdoor.o
+ .debug_info 0x00005ba1 0x152 THUMB Debug/../../obj/boot.o
+ .debug_info 0x00005cf3 0x29e THUMB Debug/../../obj/com.o
+ .debug_info 0x00005f91 0x80 THUMB Debug/../../obj/cop.o
+ .debug_info 0x00006011 0x828 THUMB Debug/../../obj/xcp.o
-.debug_abbrev 0x00000000 0x1e4e
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diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.srec b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.srec
index c496e3c8..2c29c843 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/bin/openblt_olimex_stm32h103.srec
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diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/readme.txt b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/readme.txt
index a49767fb..a10a52ca 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/readme.txt
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/readme.txt
@@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
-Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
+Rowleys CrossWorks (version 3.7.6) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/stm32f103_crossworks.hzp b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/stm32f103_crossworks.hzp
index aeae92b4..fac4815b 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/stm32f103_crossworks.hzp
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/stm32f103_crossworks.hzp
@@ -1,106 +1,172 @@
-
-
+
+
-
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-
-
-
+
+
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-
-
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-
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-
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-
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-
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+
+
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+
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-
-
-
-
-
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-
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-
-
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+
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-
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-
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diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/stm32f103_crossworks.hzs b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/stm32f103_crossworks.hzs
index 7d9ff9a7..6a04c123 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/stm32f103_crossworks.hzs
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/ide/stm32f103_crossworks.hzs
@@ -1,23 +1,28 @@
-
+
-
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-
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@@ -25,22 +30,28 @@
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@@ -48,8 +59,8 @@
-
-
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@@ -62,7 +73,9 @@
-
+
+
+
-
+
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.c b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.c
deleted file mode 100644
index 56fddc52..00000000
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.c
+++ /dev/null
@@ -1,784 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.c
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
- mrs r0, psp
- bx lr
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
- msr psp, r0
- bx lr
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
- mrs r0, msp
- bx lr
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
- msr msp, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
- clrex
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t __get_BASEPRI(void)
-{
- mrs r0, basepri
- bx lr
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
- msr basepri, r0
- bx lr
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
- mrs r0, primask
- bx lr
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
- msr primask, r0
- bx lr
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t __get_FAULTMASK(void)
-{
- mrs r0, faultmask
- bx lr
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
- msr faultmask, r0
- bx lr
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
- mrs r0, control
- bx lr
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
- msr control, r0
- bx lr
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- __ASM("mrs r0, psp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM("msr psp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- __ASM("mrs r0, msp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM("msr msp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- __ASM("rev16 r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- __ASM("rbit r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- __ASM("ldrexb r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- __ASM("ldrexh r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- __ASM("ldrex r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- __ASM("strexb r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- __ASM("strexh r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- __ASM("strex r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, psp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, msp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- uint8_t result=0;
-
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- uint16_t result=0;
-
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.h b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.h
index 2b6b51a7..efac390f 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.h
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.h
@@ -1,16 +1,16 @@
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V1.30
- * @date 30. October 2009
+ * @version V3.00
+ * @date 03. February 2012
*
* @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -20,1618 +20,1354 @@
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
-
-#ifndef __CM3_CORE_H__
-#define __CM3_CORE_H__
-
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
- *
- * List of Lint messages which will be suppressed and not shown:
- * - Error 10: \n
- * register uint32_t __regBasePri __asm("basepri"); \n
- * Error 10: Expecting ';'
- * .
- * - Error 530: \n
- * return(__regBasePri); \n
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized
- * .
- * - Error 550: \n
- * __regBasePri = (basePri & 0x1ff); \n
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed
- * .
- * - Error 754: \n
- * uint32_t RESERVED0[24]; \n
- * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced
- * .
- * - Error 750: \n
- * #define __CM3_CORE_H__ \n
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
- * .
- * - Error 528: \n
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
- * .
- * - Error 751: \n
- * } InterruptType_Type; \n
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
- * .
- * Note: To re-enable a Message, insert a space before 'lint' *
- *
- */
-
-/*lint -save */
-/*lint -e10 */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core registers and bitfields
- - Cortex-M core peripheral base address
- @{
- */
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
#ifdef __cplusplus
extern "C" {
-#endif
-
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex core */
-
-#include /* Include standard types */
-
-#if defined (__ICCARM__)
- #include /* IAR Intrinsics */
#endif
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
-#ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
-#endif
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
*/
-#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
-#else
- #define __I volatile const /*!< defines 'read only' permissions */
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ /* add preprocessor checks */
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
/*******************************************************************************
* Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
******************************************************************************/
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
- @{
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
*/
-
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
@{
*/
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
typedef struct
{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
-} NVIC_Type;
-/*@}*/ /* end of group CMSIS_CM3_NVIC */
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
- memory mapped structure for System Control Block (SCB)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
@{
*/
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
typedef struct
{
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
-} SCB_Type;
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-/* SCB Interrupt Control State Register Definitions */
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Registers Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Registers Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-/*@}*/ /* end of group CMSIS_CM3_SCB */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
- memory mapped structure for SysTick
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
typedef struct
{
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
- memory mapped structure for Instrumentation Trace Macrocell (ITM)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
typedef struct
{
- __O union
+ __O union
{
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
-} ITM_Type;
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+} ITM_Type;
/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-/*@}*/ /* end of group CMSIS_CM3_ITM */
+/*@}*/ /* end of group CMSIS_ITM */
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
- memory mapped structure for Interrupt Type
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
typedef struct
{
- uint32_t RESERVED0;
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
-#else
- uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
-/* Interrupt Controller Type Register Definitions */
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-/* Auxiliary Control Register Definitions */
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
- memory mapped structure for Memory Protection Unit (MPU)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
@{
*/
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
typedef struct
{
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-/*@}*/ /* end of group CMSIS_CM3_MPU */
+/*@} end of group CMSIS_MPU */
#endif
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
- memory mapped structure for Core Debug Register
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
@{
*/
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
typedef struct
{
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register */
#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
-/*@}*/ /* end of group CMSIS_CM3_core_register */
+/*@} */
+
/*******************************************************************************
* Hardware Abstraction Layer
- ******************************************************************************/
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq __enable_fiq
-#define __disable_fault_irq __disable_fiq
-
-#define __NOP __nop
-#define __WFI __wfi
-#define __WFE __wfe
-#define __SEV __sev
-#define __ISB() __isb(0)
-#define __DSB() __dsb(0)
-#define __DMB() __dmb(0)
-#define __REV __rev
-#define __RBIT __rbit
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
-#define __STREXB(value, ptr) __strex(value, ptr)
-#define __STREXH(value, ptr) __strex(value, ptr)
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-extern void __CLREX(void);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else /* (__ARMCC_VERSION >= 400000) */
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#define __CLREX __clrex
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-static __INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & 1);
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
-
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
-static __INLINE void __WFI() { __ASM ("wfi"); }
-static __INLINE void __WFE() { __ASM ("wfe"); }
-static __INLINE void __SEV() { __ASM ("sev"); }
-static __INLINE void __CLREX() { __ASM ("clrex"); }
-
-/* intrinsic void __ISB(void) */
-/* intrinsic void __DSB(void) */
-/* intrinsic void __DMB(void) */
-/* intrinsic void __set_PRIMASK(); */
-/* intrinsic void __get_PRIMASK(); */
-/* intrinsic void __set_FAULTMASK(); */
-/* intrinsic void __get_FAULTMASK(); */
-/* intrinsic uint32_t __REV(uint32_t value); */
-/* intrinsic uint32_t __REVSH(uint32_t value); */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
-/* intrinsic unsigned long __LDREX(unsigned long *); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __NOP() { __ASM volatile ("nop"); }
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }
-static __INLINE void __SEV() { __ASM volatile ("sev"); }
-static __INLINE void __ISB() { __ASM volatile ("isb"); }
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
- Core Function Interface containing:
+ Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- - Core Reset Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
-/*@{*/
+
+
/* ########################## NVIC functions #################################### */
-
-/**
- * @brief Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param PriorityGroup is priority grouping field
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
*/
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
-
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
-/**
- * @brief Get the Priority Grouping from NVIC Interrupt Controller
- *
- * @return priority grouping field
- *
- * Get the priority grouping from NVIC Interrupt Controller.
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
}
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- *
- * @param IRQn The positive number of the external interrupt to enable
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
}
-/**
- * @brief Disable the interrupt line for external interrupt specified
- *
- * @param IRQn The positive number of the external interrupt to disable
- *
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
}
-/**
- * @brief Read the interrupt pending bit for a device specific interrupt source
- *
- * @param IRQn The number of the device specifc interrupt
- * @return 1 = interrupt pending, 0 = interrupt not pending
- *
- * Read the pending register in NVIC and return 1 if its status is pending,
- * otherwise it returns 0
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
*/
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
}
-/**
- * @brief Set the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for set pending
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
}
-/**
- * @brief Clear the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for clear pending
- *
- * Clear the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
-/**
- * @brief Read the active bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for read active bit
- * @return 1 = interrupt active, 0 = interrupt not active
- *
- * Read the active register in NVIC and returns 1 if its status is active,
- * otherwise it returns 0.
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
*/
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
}
-/**
- * @brief Set the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for set priority
- * @param priority The priority to set
- *
- * Set the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * Note: The priority cannot be set for every core interrupt.
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
*/
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
else {
NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
}
-/**
- * @brief Read the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for get priority
- * @return The priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
*/
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
else {
return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
-/**
- * @brief Encode the priority for an interrupt
- *
- * @param PriorityGroup The used priority group
- * @param PreemptPriority The preemptive priority value (starting from 0)
- * @param SubPriority The sub priority value (starting from 0)
- * @return The encoded priority for the interrupt
- *
- * Encode the priority for an interrupt with the given priority group,
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The returned priority value can be used for NVIC_SetPriority(...) function
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
@@ -1639,7 +1375,7 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
+
return (
((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
((SubPriority & ((1 << (SubPriorityBits )) - 1)))
@@ -1647,22 +1383,19 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
}
-/**
- * @brief Decode the priority of an interrupt
- *
- * @param Priority The priority for the interrupt
- * @param PriorityGroup The used priority group
- * @param pPreemptPriority The preemptive priority value (starting from 0)
- * @param pSubPriority The sub priority value (starting from 0)
- *
- * Decode an interrupt priority value with the given priority group to
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The priority value can be retrieved with NVIC_GetPriority(...) function
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
*/
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
@@ -1670,132 +1403,134 @@ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
+
*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
}
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
/* ################################## SysTick function ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/**
- * @brief Initialize and start the SysTick counter and its interrupt.
- *
- * @param ticks number of ticks between two interrupts
- * @return 1 = failed, 0 = successful
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate
- * periodical interrupts.
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
*/
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
+
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
-
-
-
-/* ################################## Reset function ############################################ */
-
-/**
- * @brief Initiate a system reset request.
- *
- * Initiate a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
+/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
-
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
- Core Debug Interface containing:
- - Core Debug Receive / Transmit Functions
- - Core Debug Defines
- - Core Debug Variables
-*/
-/*@{*/
-
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/**
- * @brief Outputs a character via the ITM channel 0
- *
- * @param ch character to output
- * @return character to output
- *
- * The function outputs a character via the ITM channel 0.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
*/
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0].u32 == 0);
ITM->PORT[0].u8 = (uint8_t) ch;
- }
+ }
return (ch);
}
-/**
- * @brief Inputs a character via variable ITM_RxBuffer
- *
- * @return received character, -1 = no character received
- *
- * The function inputs a character via variable ITM_RxBuffer.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
*/
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
-
- return (ch);
+
+ return (ch);
}
-/**
- * @brief Check if a character via variable ITM_RxBuffer is available
- *
- * @return 1 = character available, 0 = no character available
- *
- * The function checks variable ITM_RxBuffer whether a character is available or not.
- * The function returns '1' if a character is available and '0' if no character is available.
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
*/
-static __INLINE int ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
@@ -1804,15 +1539,12 @@ static __INLINE int ITM_CheckChar (void) {
}
}
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
+/*@} end of CMSIS_core_DebugFunctions */
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */
-
-#endif /* __CM3_CORE_H__ */
-
-/*lint -restore */
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/CMSIS/Include/core_cmFunc.h b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cmFunc.h
similarity index 100%
rename from Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/CMSIS/Include/core_cmFunc.h
rename to Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cmFunc.h
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/CMSIS/Include/core_cmInstr.h b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cmInstr.h
similarity index 100%
rename from Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/CMSIS/Include/core_cmInstr.h
rename to Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cmInstr.h
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CMSIS debug support.htm b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CMSIS debug support.htm
deleted file mode 100644
index efda685b..00000000
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CMSIS debug support.htm
+++ /dev/null
@@ -1,243 +0,0 @@
-
-
-
-CMSIS Debug Support
-
-
-
-
-
-
-
-
-
CMSIS Debug Support
-
-
-
-
Cortex-M3 ITM Debug Access
-
- The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
- the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
- 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
- communication channels are used by CMSIS to output the following information:
-
-
-
ITM Channel 0: used for printf-style output via the debug interface.
-
ITM Channel 31: is reserved for RTOS kernel awareness debugging.
-
-
-
Debug IN / OUT functions
-
CMSIS provides following debug functions:
-
-
ITM_SendChar (uses ITM channel 0)
-
ITM_ReceiveChar (uses global variable)
-
ITM_CheckChar (uses global variable)
-
-
-
ITM_SendChar
-
- ITM_SendChar is used to transmit a character over ITM channel 0 from
- the microcontroller system to the debug system.
- Only a 8 bit value is transmitted.
-
- ITM communication channel is only capable for OUT direction. For IN direction
- a globel variable is used. A simple mechansim detects if a character is received.
- The project to test need to be build with debug information.
-
-
-
- The globale variable ITM_RxBuffer is used to transmit a 8 bit value from debug system
- to microcontroller system. ITM_RxBuffer is 32 bit wide to enshure a proper handshake.
-
-
-extern volatile int ITM_RxBuffer; /* variable to receive characters */
-
-
- A dedicated bit pattern is used to determin if ITM_RxBuffer is empty
- or contains a valid value.
-
-
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
-
-
- ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking.
- It returns the received character or '-1' if no character was available.
-
-
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-
ITM_CheckChar
-
- ITM_CheckChar is used to check if a character is received.
-
-
-static __INLINE int ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-
-
ITM Debug Support in uVision
-
- uVision uses in a debug session the Debug (printf) Viewer window to
- display the debug data.
-
-
Direction microcontroller system -> uVision:
-
-
- Characters received via ITM communication channel 0 are written in a printf style
- to Debug (printf) Viewer window.
-
-
-
-
Direction uVision -> microcontroller system:
-
-
Check if ITM_RxBuffer variable is available (only performed once).
-
Read character from Debug (printf) Viewer window.
-
If ITM_RxBuffer empty write character to ITM_RxBuffer.
-
-
-
Note
-
-
Current solution does not use a buffer machanism for trasmitting the characters.
-
-
-
-
RTX Kernel awareness in uVision
-
- uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
- No format overhead is necessary.
- uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
- to ITM communication channel 31.
-
-
-
Following RTX events are traced:
-
-
Task Create / Delete event
-
-
32 bit access. Task start address is transmitted
-
16 bit access. Task ID and Create/Delete flag are transmitted
- High byte holds Create/Delete flag, Low byte holds TASK ID.
-
-
-
-
Task switch event
-
-
8 bit access. Task ID of current task is transmitted
-
-
-
-
-
Note
-
-
Other RTOS information could be retrieved via memory read access in a polling mode manner.
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CMSIS_changes.htm b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CMSIS_changes.htm
deleted file mode 100644
index 162ffcc9..00000000
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/CMSIS_changes.htm
+++ /dev/null
@@ -1,320 +0,0 @@
-
-
-
-CMSIS Changes
-
-
-
-
-
-
-
-
-
Changes to CMSIS version V1.20
-
-
-
-
1. Removed CMSIS Middelware packages
-
- CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
-
-
-
2. SystemFrequency renamed to SystemCoreClock
-
- The variable name SystemCoreClock is more precise than SystemFrequency
- because the variable holds the clock value at which the core is running.
-
-
-
3. Changed startup concept
-
- The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
- from main) has the weakness that it does not work for controllers which need a already
- configuerd clock system to configure the external memory controller.
-
-
-
Changed startup concept
-
-
- SystemInit() is called from startup file before premain.
-
-
- SystemInit() configures the clock system and also configures
- an existing external memory controller.
-
-
- SystemInit() must not use global variables.
-
-
- SystemCoreClock is initialized with a correct predefined value.
-
-
- Additional function void SystemCoreClockUpdate (void) is provided.
- SystemCoreClockUpdate() updates the variable SystemCoreClock
- and must be called whenever the core clock is changed.
- SystemCoreClockUpdate() evaluates the clock register settings and calculates
- the current core clock.
-
-
-
-
-
4. Advanced Debug Functions
-
- ITM communication channel is only capable for OUT direction. To allow also communication for
- IN direction a simple concept is provided.
-
-
-
- Global variable volatile int ITM_RxBuffer used for IN data.
-
-
- Function int ITM_CheckChar (void) checks if a new character is available.
-
-
- Function int ITM_ReceiveChar (void) retrieves the new character.
-
-
-
-
- For detailed explanation see file CMSIS debug support.htm.
-
-
-
-
5. Core Register Bit Definitions
-
- Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
- defines correspond with the Cortex-M Technical Reference Manual.
-
- DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
- using DoxyGen.
-
-
-
8. Folder Structure
-
- The folder structure is changed to differentiate the single support packages.
-
-
-
-
CM0
-
CM3
-
-
CoreSupport
-
DeviceSupport
-
-
Vendor
-
-
Device
-
-
Startup
-
-
Toolchain
-
Toolchain
-
...
-
-
-
-
-
Device
-
...
-
-
-
Vendor
-
...
-
-
-
Example
-
-
Toolchain
-
-
Device
-
Device
-
...
-
-
-
Toolchain
-
...
-
-
-
-
-
-
Documentation
-
-
-
9. Open Points
-
- Following points need to be clarified and solved:
-
-
-
-
- Equivalent C and Assembler startup files.
-
-
- Is there a need for having C startup files although assembler startup files are
- very efficient and do not need to be changed?
-
-
-
-
- Placing of HEAP in external RAM.
-
-
- It must be possible to place HEAP in external RAM if the device supports an
- external memory controller.
-
-
-
-
- Placing of STACK /HEAP.
-
-
- STACK should always be placed at the end of internal RAM.
-
-
- If HEAP is placed in internal RAM than it should be placed after RW ZI section.
-
-
-
-
- Removing core_cm3.c and core_cm0.c.
-
-
- On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
- appropriate compiler intrinsics.
-
-
-
-
-
-
10. Limitations
-
- The following limitations are not covered with the current CMSIS version:
-
-
-
- No C startup files for ARM toolchain are provided.
-
-
- No C startup files for GNU toolchain are provided.
-
-
- No C startup files for IAR toolchain are provided.
-
-
- No Tasking projects are provided yet.
-
-
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/License.doc b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/License.doc
deleted file mode 100644
index b6b8acec..00000000
Binary files a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Boot/lib/CMSIS/License.doc and /dev/null differ
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/bin/demoprog_olimex_stm32h103.elf b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/bin/demoprog_olimex_stm32h103.elf
index 149581e3..f14091a2 100644
Binary files a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/bin/demoprog_olimex_stm32h103.elf and b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/bin/demoprog_olimex_stm32h103.elf differ
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/bin/demoprog_olimex_stm32h103.map b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/bin/demoprog_olimex_stm32h103.map
index 143cff35..b8023814 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/bin/demoprog_olimex_stm32h103.map
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/bin/demoprog_olimex_stm32h103.map
@@ -1,9 +1,17 @@
-Archive member included because of file (symbol)
+Archive member included to satisfy reference by file (symbol)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- (__do_debug_operation_mempoll)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o) (__debug_io_lock)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfscanf_v7m_t_le_eabi.o (__aeabi_i2d)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfprintf_v7m_t_le_eabi.o (frexp)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o) (fabs)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfprintf_v7m_t_le_eabi.o (__aeabi_uldivmod)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfscanf_v7m_t_le_eabi.o (__getc)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o) (memcpy)
Discarded input sections
@@ -30,94 +38,124 @@ Discarded input sections
.data 0x00000000 0x0 THUMB Debug/../../obj/misc.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/misc.o
.text.NVIC_PriorityGroupConfig
- 0x00000000 0x28 THUMB Debug/../../obj/misc.o
+ 0x00000000 0x24 THUMB Debug/../../obj/misc.o
.text.NVIC_Init
- 0x00000000 0xe8 THUMB Debug/../../obj/misc.o
+ 0x00000000 0xc4 THUMB Debug/../../obj/misc.o
.text.NVIC_SetVectorTable
0x00000000 0x2c THUMB Debug/../../obj/misc.o
.text.NVIC_SystemLPConfig
- 0x00000000 0x54 THUMB Debug/../../obj/misc.o
+ 0x00000000 0x40 THUMB Debug/../../obj/misc.o
.text.SysTick_CLKSourceConfig
- 0x00000000 0x4c THUMB Debug/../../obj/misc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/misc.o
+ .debug_frame 0x00000000 0x150 THUMB Debug/../../obj/misc.o
+ .debug_info 0x00000000 0x527 THUMB Debug/../../obj/misc.o
+ .debug_abbrev 0x00000000 0x14a THUMB Debug/../../obj/misc.o
+ .debug_pubnames
+ 0x00000000 0xa0 THUMB Debug/../../obj/misc.o
+ .debug_pubtypes
+ 0x00000000 0x126 THUMB Debug/../../obj/misc.o
+ .debug_aranges
+ 0x00000000 0x40 THUMB Debug/../../obj/misc.o
+ .debug_ranges 0x00000000 0x30 THUMB Debug/../../obj/misc.o
+ .debug_line 0x00000000 0x333 THUMB Debug/../../obj/misc.o
+ .debug_str 0x00000000 0x483 THUMB Debug/../../obj/misc.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/misc.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/misc.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_adc.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_adc.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_DeInit
- 0x00000000 0x88 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x74 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_Init
- 0x00000000 0xb0 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0xa4 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_StructInit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_adc.o
- .text.ADC_Cmd 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
+ .text.ADC_Cmd 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_DMACmd
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
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.text.ADC_ITConfig
- 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_adc.o
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.text.ADC_ResetCalibration
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_GetResetCalibrationStatus
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_StartCalibration
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_GetCalibrationStatus
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_SoftwareStartConvCmd
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_GetSoftwareStartConvStatus
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_DiscModeChannelCountConfig
- 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_adc.o
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.text.ADC_DiscModeCmd
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
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.text.ADC_RegularChannelConfig
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.text.ADC_ExternalTrigConvCmd
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.text.ADC_GetConversionValue
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- .text.ADC_GetDualModeConversionValue
0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_adc.o
+ .text.ADC_GetDualModeConversionValue
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.text.ADC_AutoInjectedConvCmd
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.text.ADC_InjectedDiscModeCmd
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.text.ADC_ExternalTrigInjectedConvCmd
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- .text.ADC_GetSoftwareStartInjectedConvCmdStatus
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
+ .text.ADC_SoftwareStartInjectedConvCmd
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
+ .text.ADC_GetSoftwareStartInjectedConvCmdStatus
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.text.ADC_InjectedChannelConfig
- 0x00000000 0x144 THUMB Debug/../../obj/stm32f10x_adc.o
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.text.ADC_InjectedSequencerLengthConfig
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.text.ADC_SetInjectedOffset
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.text.ADC_GetInjectedConversionValue
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.text.ADC_AnalogWatchdogCmd
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.text.ADC_AnalogWatchdogThresholdsConfig
0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_AnalogWatchdogSingleChannelConfig
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.text.ADC_TempSensorVrefintCmd
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.text.ADC_GetFlagStatus
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.text.ADC_ClearFlag
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.text.ADC_GetITStatus
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.text.ADC_ClearITPendingBit
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+ .debug_str 0x00000000 0x7b5 THUMB Debug/../../obj/stm32f10x_adc.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_adc.o
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.text.BKP_DeInit
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.text.BKP_TamperPinLevelConfig
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.text.BKP_TamperPinCmd
@@ -125,82 +163,112 @@ Discarded input sections
.text.BKP_ITConfig
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_bkp.o
.text.BKP_RTCOutputConfig
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.text.BKP_SetRTCCalibrationValue
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.text.BKP_WriteBackupRegister
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.text.BKP_ReadBackupRegister
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_bkp.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_bkp.o
.text.BKP_GetFlagStatus
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.text.BKP_ClearFlag
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_bkp.o
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.text.BKP_GetITStatus
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.text.BKP_ClearITPendingBit
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_bkp.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_bkp.o
+ .debug_frame 0x00000000 0x2b4 THUMB Debug/../../obj/stm32f10x_bkp.o
+ .debug_info 0x00000000 0x76b THUMB Debug/../../obj/stm32f10x_bkp.o
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+ .debug_pubnames
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+ .debug_pubtypes
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+ .debug_aranges
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+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_bkp.o
+ .ARM.attributes
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.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_can.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_can.o
.text.CAN_DeInit
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_Init
- 0x00000000 0x1c0 THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_FilterInit
- 0x00000000 0x20c THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_StructInit
- 0x00000000 0x6c THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_SlaveStartBank
- 0x00000000 0x8c THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_DBGFreeze
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_TTComModeCmd
- 0x00000000 0x94 THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_Transmit
- 0x00000000 0x1dc THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_TransmitStatus
- 0x00000000 0x10c THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_CancelTransmit
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.text.CAN_Receive
- 0x00000000 0x1a8 THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_FIFORelease
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.text.CAN_MessagePending
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_OperatingModeRequest
- 0x00000000 0x114 THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_Sleep
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.text.CAN_WakeUp
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_GetLastErrorCode
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_GetReceiveErrorCounter
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_GetLSBTransmitErrorCounter
- 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_ITConfig
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.text.CAN_GetFlagStatus
- 0x00000000 0xf8 THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_ClearFlag
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.text.CAN_GetITStatus
- 0x00000000 0x1b8 THUMB Debug/../../obj/stm32f10x_can.o
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.text.CAN_ClearITPendingBit
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.text.CheckITStatus
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+ .debug_info 0x00000000 0xb6a THUMB Debug/../../obj/stm32f10x_can.o
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+ .debug_pubnames
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+ .debug_pubtypes
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+ .debug_str 0x00000000 0x7e8 THUMB Debug/../../obj/stm32f10x_can.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_can.o
+ .ARM.attributes
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.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_cec.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_cec.o
.text.CEC_DeInit
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_cec.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_cec.o
.text.CEC_Init
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- .text.CEC_Cmd 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_cec.o
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+ .text.CEC_Cmd 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_cec.o
.text.CEC_ITConfig
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.text.CEC_OwnAddressConfig
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.text.CEC_EndOfMessageCmd
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.text.CEC_GetFlagStatus
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.text.CEC_ClearFlag
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.text.CEC_GetITStatus
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.text.CEC_ClearITPendingBit
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+ .debug_pubtypes
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.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_crc.o
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.text.CRC_ResetDR
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.text.CRC_CalcCRC
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.text.CRC_CalcBlockCRC
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.text.CRC_GetCRC
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.text.CRC_SetIDRegister
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.text.CRC_GetIDRegister
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.text.DAC_DeInit
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- .text.DAC_SetDualChannelData
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+ .text.DAC_StructInit
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+ .text.DAC_DMACmd
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+ .text.DAC_SoftwareTriggerCmd
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+ .text.DAC_WaveGenerationCmd
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.text.GPIO_PinLockConfig
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.text.GPIO_EventOutputConfig
- 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_EventOutputCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_PinRemapConfig
- 0x00000000 0x11c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0xe0 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_EXTILineConfig
- 0x00000000 0xb0 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x84 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_ETH_MediaInterfaceConfig
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_i2c.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_i2c.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_DeInit
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_Init
- 0x00000000 0x1ac THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x184 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_StructInit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_i2c.o
- .text.I2C_Cmd 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ .text.I2C_Cmd 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_DMACmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_DMALastTransferCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_GenerateSTART
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_GenerateSTOP
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_AcknowledgeConfig
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_OwnAddress2Config
0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_DualAddressCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_GeneralCallCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_ITConfig
0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_SendData
@@ -484,7 +672,7 @@ Discarded input sections
.text.I2C_Send7bitAddress
0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_ReadRegister
- 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_SoftwareResetCmd
0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_NACKPositionConfig
@@ -492,31 +680,46 @@ Discarded input sections
.text.I2C_SMBusAlertConfig
0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_TransmitPEC
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_PECPositionConfig
0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_CalculatePEC
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_GetPEC
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_ARPCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_StretchClockCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_FastModeDutyCycleConfig
0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_CheckEvent
- 0x00000000 0x70 THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x60 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_GetLastEvent
- 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_GetFlagStatus
- 0x00000000 0x78 THUMB Debug/../../obj/stm32f10x_i2c.o
- .text.I2C_ClearFlag
- 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_i2c.o
- .text.I2C_GetITStatus
0x00000000 0x64 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .text.I2C_ClearFlag
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_i2c.o
+ .text.I2C_GetITStatus
+ 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_ClearITPendingBit
- 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_frame 0x00000000 0x840 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_info 0x00000000 0xad2 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_abbrev 0x00000000 0x169 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_pubnames
+ 0x00000000 0x30a THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_pubtypes
+ 0x00000000 0x158 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_aranges
+ 0x00000000 0x120 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_ranges 0x00000000 0x110 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_line 0x00000000 0x5d5 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_str 0x00000000 0x720 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_i2c.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/stm32f10x_i2c.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_iwdg.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_iwdg.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_iwdg.o
@@ -531,30 +734,58 @@ Discarded input sections
.text.IWDG_Enable
0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_iwdg.o
.text.IWDG_GetFlagStatus
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_frame 0x00000000 0x170 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_info 0x00000000 0x1d4 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_abbrev 0x00000000 0x106 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_pubnames
+ 0x00000000 0xa3 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_pubtypes
+ 0x00000000 0xfe THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_aranges
+ 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_ranges 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_line 0x00000000 0x2ad THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_str 0x00000000 0x316 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/stm32f10x_iwdg.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_pwr.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_pwr.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_pwr.o
- .text.__WFI 0x00000000 0xc THUMB Debug/../../obj/stm32f10x_pwr.o
- .text.__WFE 0x00000000 0xc THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_DeInit
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_pwr.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_BackupAccessCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_PVDCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_PVDLevelConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_pwr.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_WakeUpPinCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_EnterSTOPMode
- 0x00000000 0x84 THUMB Debug/../../obj/stm32f10x_pwr.o
+ 0x00000000 0x64 THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_EnterSTANDBYMode
- 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_pwr.o
- .text.PWR_GetFlagStatus
0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_pwr.o
+ .text.PWR_GetFlagStatus
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_ClearFlag
- 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_pwr.o
+ 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_pwr.o
+ .debug_frame 0x00000000 0x224 THUMB Debug/../../obj/stm32f10x_pwr.o
+ .debug_info 0x00000000 0x465 THUMB Debug/../../obj/stm32f10x_pwr.o
+ .debug_abbrev 0x00000000 0x184 THUMB Debug/../../obj/stm32f10x_pwr.o
+ .debug_pubnames
+ 0x00000000 0x108 THUMB Debug/../../obj/stm32f10x_pwr.o
+ .debug_pubtypes
+ 0x00000000 0x11e THUMB Debug/../../obj/stm32f10x_pwr.o
+ .debug_aranges
+ 0x00000000 0x60 THUMB Debug/../../obj/stm32f10x_pwr.o
+ .debug_ranges 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_pwr.o
+ .debug_line 0x00000000 0x319 THUMB Debug/../../obj/stm32f10x_pwr.o
+ .debug_str 0x00000000 0x3dc THUMB Debug/../../obj/stm32f10x_pwr.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_pwr.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/stm32f10x_pwr.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rcc.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rcc.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rcc.o
@@ -563,53 +794,53 @@ Discarded input sections
.data.ADCPrescTable
0x00000000 0x4 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_DeInit
- 0x00000000 0x9c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_HSEConfig
- 0x00000000 0x88 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_WaitForHSEStartUp
- 0x00000000 0x64 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_AdjustHSICalibrationValue
- 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_HSICmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_PLLConfig
- 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_PLLCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_SYSCLKConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_GetSYSCLKSource
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_HCLKConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_PCLK1Config
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_PCLK2Config
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ITConfig
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_USBCLKConfig
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ADCCLKConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_LSEConfig
- 0x00000000 0x60 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_LSICmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_RTCCLKConfig
- 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_RTCCLKCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_GetClocksFreq
- 0x00000000 0x1d4 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x160 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_AHBPeriphClockCmd
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_APB1PeriphClockCmd
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_APB2PeriphResetCmd
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_APB1PeriphResetCmd
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_BackupResetCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ClockSecuritySystemCmd
@@ -617,89 +848,104 @@ Discarded input sections
.text.RCC_MCOConfig
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_GetFlagStatus
- 0x00000000 0x90 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x70 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ClearFlag
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_GetITStatus
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ClearITPendingBit
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rtc.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rtc.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_ITConfig
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_EnterConfigMode
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_ExitConfigMode
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_GetCounter
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_SetCounter
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_SetPrescaler
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_SetAlarm
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_GetDivider
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_WaitForLastTask
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_WaitForSynchro
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_GetFlagStatus
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_ClearFlag
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_GetITStatus
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_ClearITPendingBit
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_frame 0x00000000 0x338 THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_info 0x00000000 0x402 THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_abbrev 0x00000000 0x192 THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_pubnames
+ 0x00000000 0x15f THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_pubtypes
+ 0x00000000 0x11e THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_aranges
+ 0x00000000 0x88 THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_ranges 0x00000000 0x78 THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_line 0x00000000 0x368 THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_str 0x00000000 0x45c THUMB Debug/../../obj/stm32f10x_rtc.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_rtc.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/stm32f10x_rtc.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_sdio.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_sdio.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_DeInit
- 0x00000000 0x8c THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_Init
- 0x00000000 0x68 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_StructInit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_ClockCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_SetPowerState
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetPowerState
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_ITConfig
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_DMACmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_SendCommand
- 0x00000000 0x68 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_CmdStructInit
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetCommandResponse
0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetResponse
- 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_DataConfig
- 0x00000000 0x70 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_DataStructInit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetDataCounter
- 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_ReadData
0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_WriteData
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetFIFOCount
- 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_StartSDIOReadWait
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_StopSDIOReadWait
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_SetSDIOReadWaitMode
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_SetSDIOOperation
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_SendSDIOSuspendCmd
@@ -711,90 +957,120 @@ Discarded input sections
.text.SDIO_SendCEATACmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetFlagStatus
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_ClearFlag
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetITStatus
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_ClearITPendingBit
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_frame 0x00000000 0x730 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_info 0x00000000 0x7c4 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_abbrev 0x00000000 0x1b4 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_pubnames
+ 0x00000000 0x2d5 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_pubtypes
+ 0x00000000 0x158 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_aranges
+ 0x00000000 0x108 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_ranges 0x00000000 0xf8 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_line 0x00000000 0x536 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_str 0x00000000 0x6f5 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_sdio.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/stm32f10x_sdio.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_spi.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_spi.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_DeInit
- 0x00000000 0x88 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x74 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_Init
0x00000000 0x88 THUMB Debug/../../obj/stm32f10x_spi.o
.text.I2S_Init
- 0x00000000 0x198 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x168 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_StructInit
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_spi.o
.text.I2S_StructInit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_spi.o
- .text.SPI_Cmd 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_spi.o
- .text.I2S_Cmd 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_spi.o
+ .text.SPI_Cmd 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_spi.o
+ .text.I2S_Cmd 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_ITConfig
- 0x00000000 0x68 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x60 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_DMACmd
0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_SendData
0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_ReceiveData
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_NSSInternalSoftwareConfig
0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_SSOutputCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_DataSizeConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_TransmitCRC
0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_CalculateCRC
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_GetCRC
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_GetCRCPolynomial
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_BiDirectionalLineConfig
0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_GetFlagStatus
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_spi.o
- .text.SPI_I2S_ClearFlag
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_spi.o
- .text.SPI_I2S_GetITStatus
- 0x00000000 0x88 THUMB Debug/../../obj/stm32f10x_spi.o
- .text.SPI_I2S_ClearITPendingBit
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_spi.o
+ .text.SPI_I2S_ClearFlag
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_spi.o
+ .text.SPI_I2S_GetITStatus
+ 0x00000000 0x74 THUMB Debug/../../obj/stm32f10x_spi.o
+ .text.SPI_I2S_ClearITPendingBit
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_frame 0x00000000 0x5c0 THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_info 0x00000000 0x8c1 THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_abbrev 0x00000000 0x183 THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_pubnames
+ 0x00000000 0x21f THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_pubtypes
+ 0x00000000 0x15c THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_aranges
+ 0x00000000 0xd0 THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_ranges 0x00000000 0xc0 THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_line 0x00000000 0x51d THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_str 0x00000000 0x6b7 THUMB Debug/../../obj/stm32f10x_spi.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_spi.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/stm32f10x_spi.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_tim.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_tim.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_DeInit
- 0x00000000 0x2b0 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x22c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_TimeBaseInit
- 0x00000000 0x11c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0xf8 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC1Init
- 0x00000000 0x128 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x118 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC2Init
- 0x00000000 0x128 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x110 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC3Init
- 0x00000000 0x120 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x10c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC4Init
- 0x00000000 0xe0 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0xd0 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ICInit
- 0x00000000 0xb8 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0xa8 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_PWMIConfig
- 0x00000000 0xcc THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0xb8 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_BDTRConfig
0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_TimeBaseStructInit
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OCStructInit
- 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ICStructInit
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_BDTRStructInit
- 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_Cmd 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_Cmd 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_CtrlPWMOutputs
0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ITConfig
@@ -810,13 +1086,13 @@ Discarded input sections
.text.TIM_ITRxExternalClockConfig
0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_TIxExternalClockConfig
- 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ETRClockMode1Config
- 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x60 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ETRClockMode2Config
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ETRConfig
- 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_PrescalerConfig
0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_CounterModeConfig
@@ -824,73 +1100,73 @@ Discarded input sections
.text.TIM_SelectInputTrigger
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_EncoderInterfaceConfig
- 0x00000000 0x94 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x98 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ForcedOC1Config
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ForcedOC2Config
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ForcedOC3Config
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ForcedOC4Config
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ARRPreloadConfig
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_SelectCOM
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_SelectCCDMA
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_CCPreloadControl
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC1PreloadConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC2PreloadConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC3PreloadConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC4PreloadConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC1FastConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC2FastConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC3FastConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC4FastConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ClearOC1Ref
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ClearOC2Ref
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ClearOC3Ref
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ClearOC4Ref
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC1PolarityConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC1NPolarityConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC2PolarityConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_OC2NPolarityConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_OC3PolarityConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_OC3NPolarityConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_OC4PolarityConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_CCxCmd
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_CCxNCmd
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_SelectOCxM
- 0x00000000 0xbc THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_UpdateDisableConfig
0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_OC2NPolarityConfig
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_OC3PolarityConfig
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_OC3NPolarityConfig
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_OC4PolarityConfig
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_CCxCmd
+ 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_CCxNCmd
+ 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_SelectOCxM
+ 0x00000000 0xac THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_UpdateDisableConfig
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_UpdateRequestConfig
0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_SelectHallSensor
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_SelectOnePulseMode
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_SelectOutputTrigger
@@ -922,50 +1198,65 @@ Discarded input sections
.text.TIM_SetClockDivision
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetCapture1
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetCapture2
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetCapture3
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetCapture4
0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetCounter
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetPrescaler
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetFlagStatus
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ClearFlag
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetITStatus
- 0x00000000 0x60 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ClearITPendingBit
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TI1_Config
- 0x00000000 0xe4 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0xe0 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TI2_Config
- 0x00000000 0x104 THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TI3_Config
0x00000000 0xf4 THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TI3_Config
+ 0x00000000 0xec THUMB Debug/../../obj/stm32f10x_tim.o
.text.TI4_Config
- 0x00000000 0x10c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0xf8 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_frame 0x00000000 0x1698 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_info 0x00000000 0x1c26 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_abbrev 0x00000000 0x1b5 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_pubnames
+ 0x00000000 0x815 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_pubtypes
+ 0x00000000 0x17e THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_aranges
+ 0x00000000 0x2f0 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_ranges 0x00000000 0x2e0 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_line 0x00000000 0xc40 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_str 0x00000000 0xe97 THUMB Debug/../../obj/stm32f10x_tim.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_tim.o
+ .ARM.attributes
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.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_usart.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_usart.o
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.text.USART_DeInit
- 0x00000000 0xd8 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0xb8 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_Init
- 0x00000000 0x1ac THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x174 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_StructInit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_ClockInit
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.text.USART_ClockStructInit
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_Cmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
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.text.USART_ITConfig
- 0x00000000 0xa0 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x90 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_DMACmd
0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_SetAddress
@@ -973,15 +1264,15 @@ Discarded input sections
.text.USART_WakeUpConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_ReceiverWakeUpCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_LINBreakDetectLengthConfig
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.text.USART_LINCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_SendData
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- .text.USART_ReceiveData
0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_usart.o
+ .text.USART_ReceiveData
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_SendBreak
0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_SetGuardTime
@@ -989,89 +1280,76 @@ Discarded input sections
.text.USART_SetPrescaler
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_SmartCardCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
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.text.USART_SmartCardNACKCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
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.text.USART_HalfDuplexCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
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.text.USART_OverSampling8Cmd
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.text.USART_OneBitMethodCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
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.text.USART_IrDACmd
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- .text.USART_GetFlagStatus
0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_usart.o
+ .text.USART_GetFlagStatus
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.text.USART_ClearFlag
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.text.USART_GetITStatus
- 0x00000000 0xc4 THUMB Debug/../../obj/stm32f10x_usart.o
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.text.USART_ClearITPendingBit
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- .text.__REV16 0x00000000 0x24 THUMB Debug/../../obj/core_cm3.o
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- .text.__RBIT 0x00000000 0x24 THUMB Debug/../../obj/core_cm3.o
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- .text.__STREXW
- 0x00000000 0x28 THUMB Debug/../../obj/core_cm3.o
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+ .debug_info 0x00000000 0x207 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_abbrev 0x00000000 0x11c THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_pubnames
+ 0x00000000 0xd9 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_pubtypes
+ 0x00000000 0xf1 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_aranges
+ 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_ranges 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_line 0x00000000 0x2d4 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_str 0x00000000 0x322 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .ARM.attributes
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.text 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f10x.o
.data 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f10x.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f10x.o
@@ -1080,170 +1358,1866 @@ Discarded input sections
.data.AHBPrescTable
0x00000000 0x10 THUMB Debug/../../obj/system_stm32f10x.o
.text.SystemInit
- 0x00000000 0xa8 THUMB Debug/../../obj/system_stm32f10x.o
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.text.SystemCoreClockUpdate
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.text.SetSysClock
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.text.SetSysClockTo72
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+ 0x00000000 0x60 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .debug_frame 0x00000000 0xb0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .ARM.attributes
+ 0x00000000 0x1b C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
Memory Configuration
@@ -1257,7 +3231,8 @@ CM3_System_Control_Space 0xe000e000 0x00001000 xw
Linker script and memory map
- 0x080068f8 __do_debug_operation = __do_debug_operation_mempoll
+ 0x00000000 __vfprintf = __vfprintf_float_long_long
+ 0x00000000 __vfscanf = __vfscanf_float_long_long_cc
0x08006000 __FLASH_segment_start__ = 0x8006000
0x08020000 __FLASH_segment_end__ = 0x8020000
0x20000000 __RAM_segment_start__ = 0x20000000
@@ -1294,125 +3269,122 @@ Linker script and memory map
0x00000001 . = ASSERT (((__vectors_end__ >= __FLASH_segment_start__) && (__vectors_end__ <= (__FLASH_segment_start__ + 0x20000))), error: .vectors is too large to fit in FLASH memory segment)
0x08006154 __init_load_start__ = ALIGN (__vectors_end__, 0x4)
-.init 0x08006154 0x114
+.init 0x08006154 0x118
0x08006154 __init_start__ = .
*(.init .init.*)
- .init 0x08006154 0x114 THUMB Debug/../../obj/cstart.o
+ .init 0x08006154 0x118 THUMB Debug/../../obj/cstart.o
0x08006154 _start
- 0x080061d2 exit
- 0x080061f6 reset_handler
- 0x08006268 __init_end__ = (__init_start__ + SIZEOF (.init))
- 0x08006268 __init_load_end__ = __init_end__
+ 0x080061d6 exit
+ 0x080061fa reset_handler
+ 0x0800626c __init_end__ = (__init_start__ + SIZEOF (.init))
+ 0x0800626c __init_load_end__ = __init_end__
0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= (__FLASH_segment_start__ + 0x20000))), error: .init is too large to fit in FLASH memory segment)
- 0x08006268 __text_load_start__ = ALIGN (__init_end__, 0x4)
+ 0x0800626c __text_load_start__ = ALIGN (__init_end__, 0x4)
-.text 0x08006268 0x6d0
- 0x08006268 __text_start__ = .
+.text 0x0800626c 0x4ec
+ 0x0800626c __text_start__ = .
*(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table .ARM.extab* .gnu.linkonce.armextab.*)
- .glue_7 0x00000000 0x0 linker stubs
- .glue_7t 0x00000000 0x0 linker stubs
- .text.LedInit 0x08006268 0x3c THUMB Debug/../../obj/led.o
- 0x08006268 LedInit
+ .glue_7 0x0800626c 0x0 linker stubs
+ .glue_7t 0x0800626c 0x0 linker stubs
+ .text.LedInit 0x0800626c 0x34 THUMB Debug/../../obj/led.o
+ 0x0800626c LedInit
.text.LedToggle
- 0x080062a4 0x88 THUMB Debug/../../obj/led.o
- 0x080062a4 LedToggle
- .text.main 0x0800632c 0x10 THUMB Debug/../../obj/main.o
- 0x0800632c main
- .text.Init 0x0800633c 0x248 THUMB Debug/../../obj/main.o
+ 0x080062a0 0x60 THUMB Debug/../../obj/led.o
+ 0x080062a0 LedToggle
+ .text.main 0x08006300 0x10 THUMB Debug/../../obj/main.o
+ 0x08006300 main
+ .text.Init 0x08006310 0x158 THUMB Debug/../../obj/main.o
.text.NVIC_SetPriority
- 0x08006584 0x58 THUMB Debug/../../obj/timer.o
+ 0x08006468 0x54 THUMB Debug/../../obj/timer.o
.text.SysTick_Config
- 0x080065dc 0x64 THUMB Debug/../../obj/timer.o
+ 0x080064bc 0x44 THUMB Debug/../../obj/timer.o
.text.TimerInit
- 0x08006640 0x1c THUMB Debug/../../obj/timer.o
- 0x08006640 TimerInit
+ 0x08006500 0x18 THUMB Debug/../../obj/timer.o
+ 0x08006500 TimerInit
.text.TimerSet
- 0x0800665c 0x20 THUMB Debug/../../obj/timer.o
- 0x0800665c TimerSet
+ 0x08006518 0x1c THUMB Debug/../../obj/timer.o
+ 0x08006518 TimerSet
.text.TimerGet
- 0x0800667c 0x18 THUMB Debug/../../obj/timer.o
- 0x0800667c TimerGet
+ 0x08006534 0x14 THUMB Debug/../../obj/timer.o
+ 0x08006534 TimerGet
.text.TimerISRHandler
- 0x08006694 0x24 THUMB Debug/../../obj/timer.o
- 0x08006694 TimerISRHandler
+ 0x08006548 0x1c THUMB Debug/../../obj/timer.o
+ 0x08006548 TimerISRHandler
.text.UnusedISR
- 0x080066b8 0x8 THUMB Debug/../../obj/vectors.o
- 0x080066b8 UnusedISR
+ 0x08006564 0x8 THUMB Debug/../../obj/vectors.o
+ 0x08006564 UnusedISR
.text.GPIO_Init
- 0x080066c0 0x1b0 THUMB Debug/../../obj/stm32f10x_gpio.o
- 0x080066c0 GPIO_Init
+ 0x0800656c 0x178 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x0800656c GPIO_Init
.text.GPIO_SetBits
- 0x08006870 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
- 0x08006870 GPIO_SetBits
+ 0x080066e4 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x080066e4 GPIO_SetBits
.text.GPIO_ResetBits
- 0x0800688c 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
- 0x0800688c GPIO_ResetBits
+ 0x08006700 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x08006700 GPIO_ResetBits
.text.RCC_APB2PeriphClockCmd
- 0x080068a8 0x50 THUMB Debug/../../obj/stm32f10x_rcc.o
- 0x080068a8 RCC_APB2PeriphClockCmd
- .text.libdebugio.__do_debug_operation_mempoll
- 0x080068f8 0x38 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x080068f8 __do_debug_operation_mempoll
- .text.libc.__debug_io_lock
- 0x08006930 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- 0x08006930 __debug_io_lock
- .text.libc.__debug_io_unlock
- 0x08006934 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- 0x08006934 __debug_io_unlock
- 0x08006938 __text_end__ = (__text_start__ + SIZEOF (.text))
- 0x08006938 __text_load_end__ = __text_end__
+ 0x0800671c 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x0800671c RCC_APB2PeriphClockCmd
+ 0x08006758 __text_end__ = (__text_start__ + SIZEOF (.text))
+ 0x08006758 __text_load_end__ = __text_end__
.vfp11_veneer 0x00000000 0x0
.vfp11_veneer 0x00000000 0x0 linker stubs
.v4_bx 0x00000000 0x0
.v4_bx 0x00000000 0x0 linker stubs
- 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= (__FLASH_segment_start__ + 0x20000))), error: .text is too large to fit in FLASH memory segment)
- 0x08006938 __dtors_load_start__ = ALIGN (__text_end__, 0x4)
-.dtors 0x08006938 0x0
- 0x08006938 __dtors_start__ = .
+.iplt 0x00000000 0x0
+ .iplt 0x00000000 0x0 THUMB Debug/../../obj/cstart.o
+
+.rel.dyn 0x08006000 0x0
+ .rel.iplt 0x08006000 0x0 THUMB Debug/../../obj/cstart.o
+ 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= (__FLASH_segment_start__ + 0x20000))), error: .text is too large to fit in FLASH memory segment)
+ 0x08006758 __dtors_load_start__ = ALIGN (__text_end__, 0x4)
+
+.dtors 0x08006758 0x0
+ 0x08006758 __dtors_start__ = .
*(SORT(.dtors.*))
*(.dtors)
*(.fini_array .fini_array.*)
- 0x08006938 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
- 0x08006938 __dtors_load_end__ = __dtors_end__
+ 0x08006758 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
+ 0x08006758 __dtors_load_end__ = __dtors_end__
0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= (__FLASH_segment_start__ + 0x20000))), error: .dtors is too large to fit in FLASH memory segment)
- 0x08006938 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
+ 0x08006758 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
-.ctors 0x08006938 0x0
- 0x08006938 __ctors_start__ = .
+.ctors 0x08006758 0x0
+ 0x08006758 __ctors_start__ = .
*(SORT(.ctors.*))
*(.ctors)
*(.init_array .init_array.*)
- 0x08006938 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
- 0x08006938 __ctors_load_end__ = __ctors_end__
+ 0x08006758 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
+ 0x08006758 __ctors_load_end__ = __ctors_end__
0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= (__FLASH_segment_start__ + 0x20000))), error: .ctors is too large to fit in FLASH memory segment)
- 0x08006938 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
+ 0x08006758 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
-.rodata 0x08006938 0x0
- 0x08006938 __rodata_start__ = .
+.rodata 0x08006758 0x0
+ 0x08006758 __rodata_start__ = .
*(.rodata .rodata.* .gnu.linkonce.r.*)
- 0x08006938 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
- 0x08006938 __rodata_load_end__ = __rodata_end__
+ 0x08006758 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
+ 0x08006758 __rodata_load_end__ = __rodata_end__
0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= (__FLASH_segment_start__ + 0x20000))), error: .rodata is too large to fit in FLASH memory segment)
- 0x08006938 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4)
+ 0x08006758 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4)
-.ARM.exidx 0x08006938 0x0
- 0x08006938 __ARM.exidx_start__ = .
- 0x08006938 __exidx_start = __ARM.exidx_start__
+.ARM.exidx 0x08006758 0x0
+ 0x08006758 __ARM.exidx_start__ = .
+ 0x08006758 __exidx_start = __ARM.exidx_start__
*(.ARM.exidx .ARM.exidx.*)
- 0x08006938 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx))
- 0x08006938 __exidx_end = __ARM.exidx_end__
- 0x08006938 __ARM.exidx_load_end__ = __ARM.exidx_end__
+ 0x08006758 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx))
+ 0x08006758 __exidx_end = __ARM.exidx_end__
+ 0x08006758 __ARM.exidx_load_end__ = __ARM.exidx_end__
0x00000001 . = ASSERT (((__ARM.exidx_end__ >= __FLASH_segment_start__) && (__ARM.exidx_end__ <= (__FLASH_segment_start__ + 0x20000))), error: .ARM.exidx is too large to fit in FLASH memory segment)
- 0x08006938 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4)
+ 0x08006758 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4)
-.fast 0x20000000 0x0 load address 0x08006938
+.fast 0x20000000 0x0 load address 0x08006758
0x20000000 __fast_start__ = .
*(.fast .fast.*)
0x20000000 __fast_end__ = (__fast_start__ + SIZEOF (.fast))
- 0x08006938 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
+ 0x08006758 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
0x00000001 . = ASSERT ((((__fast_load_start__ + SIZEOF (.fast)) >= __FLASH_segment_start__) && ((__fast_load_start__ + SIZEOF (.fast)) <= (__FLASH_segment_start__ + 0x20000))), error: .fast is too large to fit in FLASH memory segment)
.fast_run 0x20000000 0x0
@@ -1421,13 +3393,16 @@ Linker script and memory map
0x20000000 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run))
0x20000000 __fast_run_load_end__ = __fast_run_end__
0x00000001 . = ASSERT (((__fast_run_end__ >= __RAM_segment_start__) && (__fast_run_end__ <= (__RAM_segment_start__ + 0x5000))), error: .fast_run is too large to fit in RAM memory segment)
- 0x08006938 __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4)
+ 0x08006758 __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4)
-.data 0x20000000 0x0 load address 0x08006938
+.data 0x20000000 0x0 load address 0x08006758
0x20000000 __data_start__ = .
*(.data .data.* .gnu.linkonce.d.*)
0x20000000 __data_end__ = (__data_start__ + SIZEOF (.data))
- 0x08006938 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+ 0x08006758 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+
+.igot.plt 0x00000000 0x0
+ .igot.plt 0x00000000 0x0 THUMB Debug/../../obj/cstart.o
0x00000001 . = ASSERT ((((__data_load_start__ + SIZEOF (.data)) >= __FLASH_segment_start__) && ((__data_load_start__ + SIZEOF (.data)) <= (__FLASH_segment_start__ + 0x20000))), error: .data is too large to fit in FLASH memory segment)
.data_run 0x20000000 0x0
@@ -1438,87 +3413,81 @@ Linker script and memory map
0x00000001 . = ASSERT (((__data_run_end__ >= __RAM_segment_start__) && (__data_run_end__ <= (__RAM_segment_start__ + 0x5000))), error: .data_run is too large to fit in RAM memory segment)
0x20000000 __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
-.bss 0x20000000 0x14
+.bss 0x20000000 0xc
0x20000000 __bss_start__ = .
*(.bss .bss.* .gnu.linkonce.b.*)
- .bss.timer_counter_last.3144
+ .bss.timer_counter_last.6196
0x20000000 0x4 THUMB Debug/../../obj/led.o
- .bss.led_toggle_state.3143
+ .bss.led_toggle_state.6195
0x20000004 0x1 THUMB Debug/../../obj/led.o
- *fill* 0x20000005 0x3 00
+ *fill* 0x20000005 0x3
.bss.millisecond_counter
0x20000008 0x4 THUMB Debug/../../obj/timer.o
- .bss.libdebugio.dbgCommWord
- 0x2000000c 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x2000000c dbgCommWord
- .bss.libdebugio.dbgCntrlWord_mempoll
- 0x20000010 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x20000010 dbgCntrlWord_mempoll
*(COMMON)
- 0x20000014 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
- 0x20000014 __bss_load_end__ = __bss_end__
+ 0x2000000c __bss_end__ = (__bss_start__ + SIZEOF (.bss))
+ 0x2000000c __bss_load_end__ = __bss_end__
0x00000001 . = ASSERT (((__bss_end__ >= __RAM_segment_start__) && (__bss_end__ <= (__RAM_segment_start__ + 0x5000))), error: .bss is too large to fit in RAM memory segment)
- 0x20000014 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
+ 0x2000000c __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
-.non_init 0x20000014 0x0
- 0x20000014 __non_init_start__ = .
+.non_init 0x2000000c 0x0
+ 0x2000000c __non_init_start__ = .
*(.non_init .non_init.*)
- 0x20000014 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
- 0x20000014 __non_init_load_end__ = __non_init_end__
+ 0x2000000c __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
+ 0x2000000c __non_init_load_end__ = __non_init_end__
0x00000001 . = ASSERT (((__non_init_end__ >= __RAM_segment_start__) && (__non_init_end__ <= (__RAM_segment_start__ + 0x5000))), error: .non_init is too large to fit in RAM memory segment)
- 0x20000014 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
+ 0x2000000c __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
-.heap 0x20000014 0x80
- 0x20000014 __heap_start__ = .
+.heap 0x2000000c 0x80
+ 0x2000000c __heap_start__ = .
*(.heap .heap.*)
- 0x20000094 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
- *fill* 0x20000014 0x80 00
- 0x20000094 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
- 0x20000094 __heap_load_end__ = __heap_end__
+ 0x2000008c . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
+ *fill* 0x2000000c 0x80
+ 0x2000008c __heap_end__ = (__heap_start__ + SIZEOF (.heap))
+ 0x2000008c __heap_load_end__ = __heap_end__
0x00000001 . = ASSERT (((__heap_end__ >= __RAM_segment_start__) && (__heap_end__ <= (__RAM_segment_start__ + 0x5000))), error: .heap is too large to fit in RAM memory segment)
- 0x20000094 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
+ 0x2000008c __stack_load_start__ = ALIGN (__heap_end__, 0x4)
-.stack 0x20000094 0x100
- 0x20000094 __stack_start__ = .
+.stack 0x2000008c 0x100
+ 0x2000008c __stack_start__ = .
*(.stack .stack.*)
- 0x20000194 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
- *fill* 0x20000094 0x100 00
- 0x20000194 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
- 0x20000194 __stack_load_end__ = __stack_end__
+ 0x2000018c . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
+ *fill* 0x2000008c 0x100
+ 0x2000018c __stack_end__ = (__stack_start__ + SIZEOF (.stack))
+ 0x2000018c __stack_load_end__ = __stack_end__
0x00000001 . = ASSERT (((__stack_end__ >= __RAM_segment_start__) && (__stack_end__ <= (__RAM_segment_start__ + 0x5000))), error: .stack is too large to fit in RAM memory segment)
- 0x20000194 __stack_process_load_start__ = ALIGN (__stack_end__, 0x4)
+ 0x2000018c __stack_process_load_start__ = ALIGN (__stack_end__, 0x4)
-.stack_process 0x20000194 0x0
- 0x20000194 __stack_process_start__ = .
+.stack_process 0x2000018c 0x0
+ 0x2000018c __stack_process_start__ = .
*(.stack_process .stack_process.*)
- 0x20000194 . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4)
- 0x20000194 __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process))
- 0x20000194 __stack_process_load_end__ = __stack_process_end__
+ 0x2000018c . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4)
+ 0x2000018c __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process))
+ 0x2000018c __stack_process_load_end__ = __stack_process_end__
0x00000001 . = ASSERT (((__stack_process_end__ >= __RAM_segment_start__) && (__stack_process_end__ <= (__RAM_segment_start__ + 0x5000))), error: .stack_process is too large to fit in RAM memory segment)
- 0x20000194 __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4)
+ 0x2000018c __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4)
-.tbss 0x20000194 0x0
- 0x20000194 __tbss_start__ = .
+.tbss 0x2000018c 0x0
+ 0x2000018c __tbss_start__ = .
*(.tbss .tbss.*)
- 0x20000194 __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss))
- 0x20000194 __tbss_load_end__ = __tbss_end__
+ 0x2000018c __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss))
+ 0x2000018c __tbss_load_end__ = __tbss_end__
0x00000001 . = ASSERT (((__tbss_end__ >= __RAM_segment_start__) && (__tbss_end__ <= (__RAM_segment_start__ + 0x5000))), error: .tbss is too large to fit in RAM memory segment)
- 0x08006938 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
+ 0x08006758 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
-.tdata 0x20000194 0x0 load address 0x08006938
- 0x20000194 __tdata_start__ = .
+.tdata 0x2000018c 0x0 load address 0x08006758
+ 0x2000018c __tdata_start__ = .
*(.tdata .tdata.*)
- 0x20000194 __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata))
- 0x08006938 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata))
- 0x08006938 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata))
+ 0x2000018c __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata))
+ 0x08006758 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata))
+ 0x08006758 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata))
0x00000001 . = ASSERT ((((__tdata_load_start__ + SIZEOF (.tdata)) >= __FLASH_segment_start__) && ((__tdata_load_start__ + SIZEOF (.tdata)) <= (__FLASH_segment_start__ + 0x20000))), error: .tdata is too large to fit in FLASH memory segment)
-.tdata_run 0x20000194 0x0
- 0x20000194 __tdata_run_start__ = .
- 0x20000194 . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .)
- 0x20000194 __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run))
- 0x20000194 __tdata_run_load_end__ = __tdata_run_end__
- 0x20000194 __RAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run))
+.tdata_run 0x2000018c 0x0
+ 0x2000018c __tdata_run_start__ = .
+ 0x2000018c . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .)
+ 0x2000018c __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run))
+ 0x2000018c __tdata_run_load_end__ = __tdata_run_end__
+ 0x2000018c __RAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run))
0x00000001 . = ASSERT (((__tdata_run_end__ >= __RAM_segment_start__) && (__tdata_run_end__ <= (__RAM_segment_start__ + 0x5000))), error: .tdata_run is too large to fit in RAM memory segment)
START GROUP
LOAD THUMB Debug/../../obj/cstart.o
@@ -1549,222 +3518,72 @@ LOAD THUMB Debug/../../obj/stm32f10x_spi.o
LOAD THUMB Debug/../../obj/stm32f10x_tim.o
LOAD THUMB Debug/../../obj/stm32f10x_usart.o
LOAD THUMB Debug/../../obj/stm32f10x_wwdg.o
-LOAD THUMB Debug/../../obj/core_cm3.o
LOAD THUMB Debug/../../obj/system_stm32f10x.o
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcm_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcpp_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_targetio_impl_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libcm_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libdebugio_mempoll_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libcpp_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libdebugio_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfprintf_v7m_t_le_eabi.o
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfscanf_v7m_t_le_eabi.o
END GROUP
OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/../bin/demoprog_olimex_stm32h103.elf elf32-littlearm)
.ARM.attributes
- 0x00000000 0x10
+ 0x00000000 0x2f
.ARM.attributes
- 0x00000000 0x10 THUMB Debug/../../obj/cstart.o
+ 0x00000000 0x21 THUMB Debug/../../obj/cstart.o
.ARM.attributes
- 0x00000010 0x10 THUMB Debug/../../obj/led.o
+ 0x00000021 0x33 THUMB Debug/../../obj/led.o
.ARM.attributes
- 0x00000020 0x10 THUMB Debug/../../obj/main.o
+ 0x00000054 0x33 THUMB Debug/../../obj/main.o
.ARM.attributes
- 0x00000030 0x10 THUMB Debug/../../obj/timer.o
+ 0x00000087 0x33 THUMB Debug/../../obj/timer.o
.ARM.attributes
- 0x00000040 0x10 THUMB Debug/../../obj/vectors.o
+ 0x000000ba 0x33 THUMB Debug/../../obj/vectors.o
.ARM.attributes
- 0x00000050 0x10 THUMB Debug/../../obj/misc.o
+ 0x000000ed 0x33 THUMB Debug/../../obj/stm32f10x_gpio.o
.ARM.attributes
- 0x00000060 0x10 THUMB Debug/../../obj/stm32f10x_adc.o
- .ARM.attributes
- 0x00000070 0x10 THUMB Debug/../../obj/stm32f10x_bkp.o
- .ARM.attributes
- 0x00000080 0x10 THUMB Debug/../../obj/stm32f10x_can.o
- .ARM.attributes
- 0x00000090 0x10 THUMB Debug/../../obj/stm32f10x_cec.o
- .ARM.attributes
- 0x000000a0 0x10 THUMB Debug/../../obj/stm32f10x_crc.o
- .ARM.attributes
- 0x000000b0 0x10 THUMB Debug/../../obj/stm32f10x_dac.o
- .ARM.attributes
- 0x000000c0 0x10 THUMB Debug/../../obj/stm32f10x_dbgmcu.o
- .ARM.attributes
- 0x000000d0 0x10 THUMB Debug/../../obj/stm32f10x_dma.o
- .ARM.attributes
- 0x000000e0 0x10 THUMB Debug/../../obj/stm32f10x_exti.o
- .ARM.attributes
- 0x000000f0 0x10 THUMB Debug/../../obj/stm32f10x_flash.o
- .ARM.attributes
- 0x00000100 0x10 THUMB Debug/../../obj/stm32f10x_fsmc.o
- .ARM.attributes
- 0x00000110 0x10 THUMB Debug/../../obj/stm32f10x_gpio.o
- .ARM.attributes
- 0x00000120 0x10 THUMB Debug/../../obj/stm32f10x_i2c.o
- .ARM.attributes
- 0x00000130 0x10 THUMB Debug/../../obj/stm32f10x_iwdg.o
- .ARM.attributes
- 0x00000140 0x10 THUMB Debug/../../obj/stm32f10x_pwr.o
- .ARM.attributes
- 0x00000150 0x10 THUMB Debug/../../obj/stm32f10x_rcc.o
- .ARM.attributes
- 0x00000160 0x10 THUMB Debug/../../obj/stm32f10x_rtc.o
- .ARM.attributes
- 0x00000170 0x10 THUMB Debug/../../obj/stm32f10x_sdio.o
- .ARM.attributes
- 0x00000180 0x10 THUMB Debug/../../obj/stm32f10x_spi.o
- .ARM.attributes
- 0x00000190 0x10 THUMB Debug/../../obj/stm32f10x_tim.o
- .ARM.attributes
- 0x000001a0 0x10 THUMB Debug/../../obj/stm32f10x_usart.o
- .ARM.attributes
- 0x000001b0 0x10 THUMB Debug/../../obj/stm32f10x_wwdg.o
- .ARM.attributes
- 0x000001c0 0x10 THUMB Debug/../../obj/core_cm3.o
- .ARM.attributes
- 0x000001d0 0x10 THUMB Debug/../../obj/system_stm32f10x.o
- .ARM.attributes
- 0x000001e0 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .ARM.attributes
- 0x000001f0 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
+ 0x00000120 0x33 THUMB Debug/../../obj/stm32f10x_rcc.o
-.comment 0x00000000 0x4e
- .comment 0x00000000 0x4e THUMB Debug/../../obj/led.o
- 0x4f (size before relaxing)
- .comment 0x00000000 0x4f THUMB Debug/../../obj/main.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/timer.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/vectors.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/misc.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_adc.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_bkp.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_can.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_cec.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_crc.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_dac.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_dbgmcu.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_dma.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_exti.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_flash.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_fsmc.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_gpio.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_i2c.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_iwdg.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_pwr.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_rcc.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_rtc.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_sdio.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_spi.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_tim.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_usart.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f10x_wwdg.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/core_cm3.o
- .comment 0x00000000 0x4f THUMB Debug/../../obj/system_stm32f10x.o
- .comment 0x00000000 0x4f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .comment 0x00000000 0x4f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
+.comment 0x00000000 0x4c
+ .comment 0x00000000 0x4c THUMB Debug/../../obj/led.o
+ 0x4d (size before relaxing)
+ .comment 0x0000004c 0x4d THUMB Debug/../../obj/main.o
+ .comment 0x0000004c 0x4d THUMB Debug/../../obj/timer.o
+ .comment 0x0000004c 0x4d THUMB Debug/../../obj/vectors.o
+ .comment 0x0000004c 0x4d THUMB Debug/../../obj/stm32f10x_gpio.o
+ .comment 0x0000004c 0x4d THUMB Debug/../../obj/stm32f10x_rcc.o
-.debug_line 0x00000000 0x8035
- .debug_line 0x00000000 0xed THUMB Debug/../../obj/cstart.o
- .debug_line 0x000000ed 0x2e3 THUMB Debug/../../obj/led.o
- .debug_line 0x000003d0 0x278 THUMB Debug/../../obj/main.o
- .debug_line 0x00000648 0x295 THUMB Debug/../../obj/timer.o
- .debug_line 0x000008dd 0x12b THUMB Debug/../../obj/vectors.o
- .debug_line 0x00000a08 0x343 THUMB Debug/../../obj/misc.o
- .debug_line 0x00000d4b 0x622 THUMB Debug/../../obj/stm32f10x_adc.o
- .debug_line 0x0000136d 0x331 THUMB Debug/../../obj/stm32f10x_bkp.o
- .debug_line 0x0000169e 0x658 THUMB Debug/../../obj/stm32f10x_can.o
- .debug_line 0x00001cf6 0x412 THUMB Debug/../../obj/stm32f10x_cec.o
- .debug_line 0x00002108 0x2ca THUMB Debug/../../obj/stm32f10x_crc.o
- .debug_line 0x000023d2 0x3ee THUMB Debug/../../obj/stm32f10x_dac.o
- .debug_line 0x000027c0 0x285 THUMB Debug/../../obj/stm32f10x_dbgmcu.o
- .debug_line 0x00002a45 0x402 THUMB Debug/../../obj/stm32f10x_dma.o
- .debug_line 0x00002e47 0x3a3 THUMB Debug/../../obj/stm32f10x_exti.o
- .debug_line 0x000031ea 0x5d8 THUMB Debug/../../obj/stm32f10x_flash.o
- .debug_line 0x000037c2 0x554 THUMB Debug/../../obj/stm32f10x_fsmc.o
- .debug_line 0x00003d16 0x4ae THUMB Debug/../../obj/stm32f10x_gpio.o
- .debug_line 0x000041c4 0x5d6 THUMB Debug/../../obj/stm32f10x_i2c.o
- .debug_line 0x0000479a 0x2bb THUMB Debug/../../obj/stm32f10x_iwdg.o
- .debug_line 0x00004a55 0x335 THUMB Debug/../../obj/stm32f10x_pwr.o
- .debug_line 0x00004d8a 0x5bc THUMB Debug/../../obj/stm32f10x_rcc.o
- .debug_line 0x00005346 0x378 THUMB Debug/../../obj/stm32f10x_rtc.o
- .debug_line 0x000056be 0x54a THUMB Debug/../../obj/stm32f10x_sdio.o
- .debug_line 0x00005c08 0x521 THUMB Debug/../../obj/stm32f10x_spi.o
- .debug_line 0x00006129 0xb94 THUMB Debug/../../obj/stm32f10x_tim.o
- .debug_line 0x00006cbd 0x59a THUMB Debug/../../obj/stm32f10x_usart.o
- .debug_line 0x00007257 0x2e2 THUMB Debug/../../obj/stm32f10x_wwdg.o
- .debug_line 0x00007539 0x2ba THUMB Debug/../../obj/core_cm3.o
- .debug_line 0x000077f3 0x27e THUMB Debug/../../obj/system_stm32f10x.o
- .debug_line 0x00007a71 0x550 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .debug_line 0x00007fc1 0x74 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
+.debug_line 0x00000000 0x14d8
+ .debug_line 0x00000000 0x117 THUMB Debug/../../obj/cstart.o
+ .debug_line 0x00000117 0x2ce THUMB Debug/../../obj/led.o
+ .debug_line 0x000003e5 0x271 THUMB Debug/../../obj/main.o
+ .debug_line 0x00000656 0x287 THUMB Debug/../../obj/timer.o
+ .debug_line 0x000008dd 0x180 THUMB Debug/../../obj/vectors.o
+ .debug_line 0x00000a5d 0x4c0 THUMB Debug/../../obj/stm32f10x_gpio.o
+ .debug_line 0x00000f1d 0x5bb THUMB Debug/../../obj/stm32f10x_rcc.o
-.debug_info 0x00000000 0xcb26
+.debug_info 0x00000000 0x1b55
.debug_info 0x00000000 0xe6 THUMB Debug/../../obj/cstart.o
- .debug_info 0x000000e6 0x251 THUMB Debug/../../obj/led.o
- .debug_info 0x00000337 0x25d THUMB Debug/../../obj/main.o
- .debug_info 0x00000594 0x5e9 THUMB Debug/../../obj/timer.o
- .debug_info 0x00000b7d 0x10e THUMB Debug/../../obj/vectors.o
- .debug_info 0x00000c8b 0x53f THUMB Debug/../../obj/misc.o
- .debug_info 0x000011ca 0xc07 THUMB Debug/../../obj/stm32f10x_adc.o
- .debug_info 0x00001dd1 0x872 THUMB Debug/../../obj/stm32f10x_bkp.o
- .debug_info 0x00002643 0xc50 THUMB Debug/../../obj/stm32f10x_can.o
- .debug_info 0x00003293 0x435 THUMB Debug/../../obj/stm32f10x_cec.o
- .debug_info 0x000036c8 0x1f9 THUMB Debug/../../obj/stm32f10x_crc.o
- .debug_info 0x000038c1 0x4d1 THUMB Debug/../../obj/stm32f10x_dac.o
- .debug_info 0x00003d92 0x153 THUMB Debug/../../obj/stm32f10x_dbgmcu.o
- .debug_info 0x00003ee5 0x49b THUMB Debug/../../obj/stm32f10x_dma.o
- .debug_info 0x00004380 0x35a THUMB Debug/../../obj/stm32f10x_exti.o
- .debug_info 0x000046da 0x812 THUMB Debug/../../obj/stm32f10x_flash.o
- .debug_info 0x00004eec 0x992 THUMB Debug/../../obj/stm32f10x_fsmc.o
- .debug_info 0x0000587e 0x71c THUMB Debug/../../obj/stm32f10x_gpio.o
- .debug_info 0x00005f9a 0xb8d THUMB Debug/../../obj/stm32f10x_i2c.o
- .debug_info 0x00006b27 0x1f9 THUMB Debug/../../obj/stm32f10x_iwdg.o
- .debug_info 0x00006d20 0x454 THUMB Debug/../../obj/stm32f10x_pwr.o
- .debug_info 0x00007174 0x8fa THUMB Debug/../../obj/stm32f10x_rcc.o
- .debug_info 0x00007a6e 0x463 THUMB Debug/../../obj/stm32f10x_rtc.o
- .debug_info 0x00007ed1 0x888 THUMB Debug/../../obj/stm32f10x_sdio.o
- .debug_info 0x00008759 0x96a THUMB Debug/../../obj/stm32f10x_spi.o
- .debug_info 0x000090c3 0x1e11 THUMB Debug/../../obj/stm32f10x_tim.o
- .debug_info 0x0000aed4 0xa65 THUMB Debug/../../obj/stm32f10x_usart.o
- .debug_info 0x0000b939 0x22e THUMB Debug/../../obj/stm32f10x_wwdg.o
- .debug_info 0x0000bb67 0x53a THUMB Debug/../../obj/core_cm3.o
- .debug_info 0x0000c0a1 0x499 THUMB Debug/../../obj/system_stm32f10x.o
- .debug_info 0x0000c53a 0x51f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .debug_info 0x0000ca59 0xcd C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
+ .debug_info 0x000000e6 0x23e THUMB Debug/../../obj/led.o
+ .debug_info 0x00000324 0x232 THUMB Debug/../../obj/main.o
+ .debug_info 0x00000556 0x5de THUMB Debug/../../obj/timer.o
+ .debug_info 0x00000b34 0xfc THUMB Debug/../../obj/vectors.o
+ .debug_info 0x00000c30 0x6bc THUMB Debug/../../obj/stm32f10x_gpio.o
+ .debug_info 0x000012ec 0x869 THUMB Debug/../../obj/stm32f10x_rcc.o
-.debug_abbrev 0x00000000 0x260c
+.debug_abbrev 0x00000000 0x815
.debug_abbrev 0x00000000 0x14 THUMB Debug/../../obj/cstart.o
- .debug_abbrev 0x00000014 0xec THUMB Debug/../../obj/led.o
- .debug_abbrev 0x00000100 0xe1 THUMB Debug/../../obj/main.o
- .debug_abbrev 0x000001e1 0x195 THUMB Debug/../../obj/timer.o
- .debug_abbrev 0x00000376 0xd6 THUMB Debug/../../obj/vectors.o
- .debug_abbrev 0x0000044c 0x135 THUMB Debug/../../obj/misc.o
- .debug_abbrev 0x00000581 0x174 THUMB Debug/../../obj/stm32f10x_adc.o
- .debug_abbrev 0x000006f5 0x156 THUMB Debug/../../obj/stm32f10x_bkp.o
- .debug_abbrev 0x0000084b 0x1ac THUMB Debug/../../obj/stm32f10x_can.o
- .debug_abbrev 0x000009f7 0x189 THUMB Debug/../../obj/stm32f10x_cec.o
- .debug_abbrev 0x00000b80 0x10a THUMB Debug/../../obj/stm32f10x_crc.o
- .debug_abbrev 0x00000c8a 0x169 THUMB Debug/../../obj/stm32f10x_dac.o
- .debug_abbrev 0x00000df3 0xda THUMB Debug/../../obj/stm32f10x_dbgmcu.o
- .debug_abbrev 0x00000ecd 0x14e THUMB Debug/../../obj/stm32f10x_dma.o
- .debug_abbrev 0x0000101b 0x14a THUMB Debug/../../obj/stm32f10x_exti.o
- .debug_abbrev 0x00001165 0x162 THUMB Debug/../../obj/stm32f10x_flash.o
- .debug_abbrev 0x000012c7 0x166 THUMB Debug/../../obj/stm32f10x_fsmc.o
- .debug_abbrev 0x0000142d 0x1a4 THUMB Debug/../../obj/stm32f10x_gpio.o
- .debug_abbrev 0x000015d1 0x15d THUMB Debug/../../obj/stm32f10x_i2c.o
- .debug_abbrev 0x0000172e 0xfa THUMB Debug/../../obj/stm32f10x_iwdg.o
- .debug_abbrev 0x00001828 0x184 THUMB Debug/../../obj/stm32f10x_pwr.o
- .debug_abbrev 0x000019ac 0x191 THUMB Debug/../../obj/stm32f10x_rcc.o
- .debug_abbrev 0x00001b3d 0x166 THUMB Debug/../../obj/stm32f10x_rtc.o
- .debug_abbrev 0x00001ca3 0x1a2 THUMB Debug/../../obj/stm32f10x_sdio.o
- .debug_abbrev 0x00001e45 0x15d THUMB Debug/../../obj/stm32f10x_spi.o
- .debug_abbrev 0x00001fa2 0x172 THUMB Debug/../../obj/stm32f10x_tim.o
- .debug_abbrev 0x00002114 0x15b THUMB Debug/../../obj/stm32f10x_usart.o
- .debug_abbrev 0x0000226f 0xf8 THUMB Debug/../../obj/stm32f10x_wwdg.o
- .debug_abbrev 0x00002367 0xca THUMB Debug/../../obj/core_cm3.o
- .debug_abbrev 0x00002431 0x17e THUMB Debug/../../obj/system_stm32f10x.o
- .debug_abbrev 0x000025af 0x38 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .debug_abbrev 0x000025e7 0x25 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
+ .debug_abbrev 0x00000014 0xf4 THUMB Debug/../../obj/led.o
+ .debug_abbrev 0x00000108 0xea THUMB Debug/../../obj/main.o
+ .debug_abbrev 0x000001f2 0x1bb THUMB Debug/../../obj/timer.o
+ .debug_abbrev 0x000003ad 0xda THUMB Debug/../../obj/vectors.o
+ .debug_abbrev 0x00000487 0x1cf THUMB Debug/../../obj/stm32f10x_gpio.o
+ .debug_abbrev 0x00000656 0x1bf THUMB Debug/../../obj/stm32f10x_rcc.o
-.debug_aranges 0x00000000 0x1548
+.debug_aranges 0x00000000 0x298
.debug_aranges
0x00000000 0x20 THUMB Debug/../../obj/cstart.o
.debug_aranges
@@ -1776,218 +3595,66 @@ OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Cros
.debug_aranges
0x000000b8 0x20 THUMB Debug/../../obj/vectors.o
.debug_aranges
- 0x000000d8 0x40 THUMB Debug/../../obj/misc.o
+ 0x000000d8 0xa8 THUMB Debug/../../obj/stm32f10x_gpio.o
.debug_aranges
- 0x00000118 0x138 THUMB Debug/../../obj/stm32f10x_adc.o
- .debug_aranges
- 0x00000250 0x78 THUMB Debug/../../obj/stm32f10x_bkp.o
- .debug_aranges
- 0x000002c8 0xe0 THUMB Debug/../../obj/stm32f10x_can.o
- .debug_aranges
- 0x000003a8 0x88 THUMB Debug/../../obj/stm32f10x_cec.o
- .debug_aranges
- 0x00000430 0x48 THUMB Debug/../../obj/stm32f10x_crc.o
- .debug_aranges
- 0x00000478 0x78 THUMB Debug/../../obj/stm32f10x_dac.o
- .debug_aranges
- 0x000004f0 0x30 THUMB Debug/../../obj/stm32f10x_dbgmcu.o
- .debug_aranges
- 0x00000520 0x70 THUMB Debug/../../obj/stm32f10x_dma.o
- .debug_aranges
- 0x00000590 0x58 THUMB Debug/../../obj/stm32f10x_exti.o
- .debug_aranges
- 0x000005e8 0xf8 THUMB Debug/../../obj/stm32f10x_flash.o
- .debug_aranges
- 0x000006e0 0xb0 THUMB Debug/../../obj/stm32f10x_fsmc.o
- .debug_aranges
- 0x00000790 0xa8 THUMB Debug/../../obj/stm32f10x_gpio.o
- .debug_aranges
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diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/bin/demoprog_olimex_stm32h103.srec b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/bin/demoprog_olimex_stm32h103.srec
index 0ba6b81f..3b4732a3 100644
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diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/readme.txt b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/readme.txt
index a49767fb..a10a52ca 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/readme.txt
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/readme.txt
@@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
-Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
+Rowleys CrossWorks (version 3.7.6) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/stm32f103_crossworks.hzp b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/stm32f103_crossworks.hzp
index d7c67461..e5fcbea7 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/stm32f103_crossworks.hzp
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/stm32f103_crossworks.hzp
@@ -1,98 +1,144 @@
-
-
+
+
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+
+
@@ -100,9 +146,30 @@
-
-
-
-
-
+
+
+
+
+
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/stm32f103_crossworks.hzs b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/stm32f103_crossworks.hzs
index db603746..311235c1 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/stm32f103_crossworks.hzs
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/ide/stm32f103_crossworks.hzs
@@ -1,19 +1,22 @@
-
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@@ -23,16 +26,16 @@
-
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@@ -51,7 +54,7 @@
-
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+
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c
deleted file mode 100644
index 56fddc52..00000000
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c
+++ /dev/null
@@ -1,784 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.c
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
- mrs r0, psp
- bx lr
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
- msr psp, r0
- bx lr
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
- mrs r0, msp
- bx lr
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
- msr msp, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
- clrex
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t __get_BASEPRI(void)
-{
- mrs r0, basepri
- bx lr
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
- msr basepri, r0
- bx lr
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
- mrs r0, primask
- bx lr
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
- msr primask, r0
- bx lr
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t __get_FAULTMASK(void)
-{
- mrs r0, faultmask
- bx lr
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
- msr faultmask, r0
- bx lr
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
- mrs r0, control
- bx lr
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
- msr control, r0
- bx lr
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- __ASM("mrs r0, psp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM("msr psp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- __ASM("mrs r0, msp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM("msr msp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- __ASM("rev16 r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- __ASM("rbit r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- __ASM("ldrexb r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- __ASM("ldrexh r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- __ASM("ldrex r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- __ASM("strexb r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- __ASM("strexh r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- __ASM("strex r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, psp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, msp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- uint8_t result=0;
-
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- uint16_t result=0;
-
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h
index 2b6b51a7..efac390f 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h
@@ -1,16 +1,16 @@
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V1.30
- * @date 30. October 2009
+ * @version V3.00
+ * @date 03. February 2012
*
* @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -20,1618 +20,1354 @@
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
-
-#ifndef __CM3_CORE_H__
-#define __CM3_CORE_H__
-
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
- *
- * List of Lint messages which will be suppressed and not shown:
- * - Error 10: \n
- * register uint32_t __regBasePri __asm("basepri"); \n
- * Error 10: Expecting ';'
- * .
- * - Error 530: \n
- * return(__regBasePri); \n
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized
- * .
- * - Error 550: \n
- * __regBasePri = (basePri & 0x1ff); \n
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed
- * .
- * - Error 754: \n
- * uint32_t RESERVED0[24]; \n
- * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced
- * .
- * - Error 750: \n
- * #define __CM3_CORE_H__ \n
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
- * .
- * - Error 528: \n
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
- * .
- * - Error 751: \n
- * } InterruptType_Type; \n
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
- * .
- * Note: To re-enable a Message, insert a space before 'lint' *
- *
- */
-
-/*lint -save */
-/*lint -e10 */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core registers and bitfields
- - Cortex-M core peripheral base address
- @{
- */
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
#ifdef __cplusplus
extern "C" {
-#endif
-
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex core */
-
-#include /* Include standard types */
-
-#if defined (__ICCARM__)
- #include /* IAR Intrinsics */
#endif
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
-#ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
-#endif
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
*/
-#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
-#else
- #define __I volatile const /*!< defines 'read only' permissions */
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ /* add preprocessor checks */
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
/*******************************************************************************
* Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
******************************************************************************/
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
- @{
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
*/
-
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
@{
*/
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
typedef struct
{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
-} NVIC_Type;
-/*@}*/ /* end of group CMSIS_CM3_NVIC */
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
- memory mapped structure for System Control Block (SCB)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
@{
*/
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
typedef struct
{
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
-} SCB_Type;
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-/* SCB Interrupt Control State Register Definitions */
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Registers Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Registers Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-/*@}*/ /* end of group CMSIS_CM3_SCB */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
- memory mapped structure for SysTick
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
typedef struct
{
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
- memory mapped structure for Instrumentation Trace Macrocell (ITM)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
typedef struct
{
- __O union
+ __O union
{
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
-} ITM_Type;
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+} ITM_Type;
/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-/*@}*/ /* end of group CMSIS_CM3_ITM */
+/*@}*/ /* end of group CMSIS_ITM */
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
- memory mapped structure for Interrupt Type
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
typedef struct
{
- uint32_t RESERVED0;
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
-#else
- uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
-/* Interrupt Controller Type Register Definitions */
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-/* Auxiliary Control Register Definitions */
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
- memory mapped structure for Memory Protection Unit (MPU)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
@{
*/
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
typedef struct
{
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-/*@}*/ /* end of group CMSIS_CM3_MPU */
+/*@} end of group CMSIS_MPU */
#endif
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
- memory mapped structure for Core Debug Register
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
@{
*/
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
typedef struct
{
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register */
#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
-/*@}*/ /* end of group CMSIS_CM3_core_register */
+/*@} */
+
/*******************************************************************************
* Hardware Abstraction Layer
- ******************************************************************************/
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq __enable_fiq
-#define __disable_fault_irq __disable_fiq
-
-#define __NOP __nop
-#define __WFI __wfi
-#define __WFE __wfe
-#define __SEV __sev
-#define __ISB() __isb(0)
-#define __DSB() __dsb(0)
-#define __DMB() __dmb(0)
-#define __REV __rev
-#define __RBIT __rbit
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
-#define __STREXB(value, ptr) __strex(value, ptr)
-#define __STREXH(value, ptr) __strex(value, ptr)
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-extern void __CLREX(void);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else /* (__ARMCC_VERSION >= 400000) */
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#define __CLREX __clrex
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-static __INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & 1);
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
-
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
-static __INLINE void __WFI() { __ASM ("wfi"); }
-static __INLINE void __WFE() { __ASM ("wfe"); }
-static __INLINE void __SEV() { __ASM ("sev"); }
-static __INLINE void __CLREX() { __ASM ("clrex"); }
-
-/* intrinsic void __ISB(void) */
-/* intrinsic void __DSB(void) */
-/* intrinsic void __DMB(void) */
-/* intrinsic void __set_PRIMASK(); */
-/* intrinsic void __get_PRIMASK(); */
-/* intrinsic void __set_FAULTMASK(); */
-/* intrinsic void __get_FAULTMASK(); */
-/* intrinsic uint32_t __REV(uint32_t value); */
-/* intrinsic uint32_t __REVSH(uint32_t value); */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
-/* intrinsic unsigned long __LDREX(unsigned long *); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __NOP() { __ASM volatile ("nop"); }
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }
-static __INLINE void __SEV() { __ASM volatile ("sev"); }
-static __INLINE void __ISB() { __ASM volatile ("isb"); }
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
- Core Function Interface containing:
+ Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- - Core Reset Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
-/*@{*/
+
+
/* ########################## NVIC functions #################################### */
-
-/**
- * @brief Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param PriorityGroup is priority grouping field
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
*/
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
-
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
-/**
- * @brief Get the Priority Grouping from NVIC Interrupt Controller
- *
- * @return priority grouping field
- *
- * Get the priority grouping from NVIC Interrupt Controller.
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
}
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- *
- * @param IRQn The positive number of the external interrupt to enable
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
}
-/**
- * @brief Disable the interrupt line for external interrupt specified
- *
- * @param IRQn The positive number of the external interrupt to disable
- *
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
}
-/**
- * @brief Read the interrupt pending bit for a device specific interrupt source
- *
- * @param IRQn The number of the device specifc interrupt
- * @return 1 = interrupt pending, 0 = interrupt not pending
- *
- * Read the pending register in NVIC and return 1 if its status is pending,
- * otherwise it returns 0
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
*/
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
}
-/**
- * @brief Set the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for set pending
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
}
-/**
- * @brief Clear the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for clear pending
- *
- * Clear the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
-/**
- * @brief Read the active bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for read active bit
- * @return 1 = interrupt active, 0 = interrupt not active
- *
- * Read the active register in NVIC and returns 1 if its status is active,
- * otherwise it returns 0.
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
*/
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
}
-/**
- * @brief Set the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for set priority
- * @param priority The priority to set
- *
- * Set the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * Note: The priority cannot be set for every core interrupt.
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
*/
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
else {
NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
}
-/**
- * @brief Read the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for get priority
- * @return The priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
*/
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
else {
return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
-/**
- * @brief Encode the priority for an interrupt
- *
- * @param PriorityGroup The used priority group
- * @param PreemptPriority The preemptive priority value (starting from 0)
- * @param SubPriority The sub priority value (starting from 0)
- * @return The encoded priority for the interrupt
- *
- * Encode the priority for an interrupt with the given priority group,
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The returned priority value can be used for NVIC_SetPriority(...) function
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
@@ -1639,7 +1375,7 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
+
return (
((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
((SubPriority & ((1 << (SubPriorityBits )) - 1)))
@@ -1647,22 +1383,19 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
}
-/**
- * @brief Decode the priority of an interrupt
- *
- * @param Priority The priority for the interrupt
- * @param PriorityGroup The used priority group
- * @param pPreemptPriority The preemptive priority value (starting from 0)
- * @param pSubPriority The sub priority value (starting from 0)
- *
- * Decode an interrupt priority value with the given priority group to
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The priority value can be retrieved with NVIC_GetPriority(...) function
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
*/
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
@@ -1670,132 +1403,134 @@ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
+
*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
}
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
/* ################################## SysTick function ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/**
- * @brief Initialize and start the SysTick counter and its interrupt.
- *
- * @param ticks number of ticks between two interrupts
- * @return 1 = failed, 0 = successful
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate
- * periodical interrupts.
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
*/
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
+
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
-
-
-
-/* ################################## Reset function ############################################ */
-
-/**
- * @brief Initiate a system reset request.
- *
- * Initiate a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
+/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
-
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
- Core Debug Interface containing:
- - Core Debug Receive / Transmit Functions
- - Core Debug Defines
- - Core Debug Variables
-*/
-/*@{*/
-
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/**
- * @brief Outputs a character via the ITM channel 0
- *
- * @param ch character to output
- * @return character to output
- *
- * The function outputs a character via the ITM channel 0.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
*/
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0].u32 == 0);
ITM->PORT[0].u8 = (uint8_t) ch;
- }
+ }
return (ch);
}
-/**
- * @brief Inputs a character via variable ITM_RxBuffer
- *
- * @return received character, -1 = no character received
- *
- * The function inputs a character via variable ITM_RxBuffer.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
*/
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
-
- return (ch);
+
+ return (ch);
}
-/**
- * @brief Check if a character via variable ITM_RxBuffer is available
- *
- * @return 1 = character available, 0 = no character available
- *
- * The function checks variable ITM_RxBuffer whether a character is available or not.
- * The function returns '1' if a character is available and '0' if no character is available.
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
*/
-static __INLINE int ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
@@ -1804,15 +1539,12 @@ static __INLINE int ITM_CheckChar (void) {
}
}
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
+/*@} end of CMSIS_core_DebugFunctions */
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */
-
-#endif /* __CM3_CORE_H__ */
-
-/*lint -restore */
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/CMSIS/Include/core_cmFunc.h b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cmFunc.h
similarity index 100%
rename from Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/CMSIS/Include/core_cmFunc.h
rename to Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cmFunc.h
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/CMSIS/Include/core_cmInstr.h b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cmInstr.h
similarity index 100%
rename from Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/CMSIS/Include/core_cmInstr.h
rename to Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cmInstr.h
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CMSIS debug support.htm b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CMSIS debug support.htm
deleted file mode 100644
index efda685b..00000000
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CMSIS debug support.htm
+++ /dev/null
@@ -1,243 +0,0 @@
-
-
-
-CMSIS Debug Support
-
-
-
-
-
-
-
-
-
CMSIS Debug Support
-
-
-
-
Cortex-M3 ITM Debug Access
-
- The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
- the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
- 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
- communication channels are used by CMSIS to output the following information:
-
-
-
ITM Channel 0: used for printf-style output via the debug interface.
-
ITM Channel 31: is reserved for RTOS kernel awareness debugging.
-
-
-
Debug IN / OUT functions
-
CMSIS provides following debug functions:
-
-
ITM_SendChar (uses ITM channel 0)
-
ITM_ReceiveChar (uses global variable)
-
ITM_CheckChar (uses global variable)
-
-
-
ITM_SendChar
-
- ITM_SendChar is used to transmit a character over ITM channel 0 from
- the microcontroller system to the debug system.
- Only a 8 bit value is transmitted.
-
- ITM communication channel is only capable for OUT direction. For IN direction
- a globel variable is used. A simple mechansim detects if a character is received.
- The project to test need to be build with debug information.
-
-
-
- The globale variable ITM_RxBuffer is used to transmit a 8 bit value from debug system
- to microcontroller system. ITM_RxBuffer is 32 bit wide to enshure a proper handshake.
-
-
-extern volatile int ITM_RxBuffer; /* variable to receive characters */
-
-
- A dedicated bit pattern is used to determin if ITM_RxBuffer is empty
- or contains a valid value.
-
-
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
-
-
- ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking.
- It returns the received character or '-1' if no character was available.
-
-
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-
ITM_CheckChar
-
- ITM_CheckChar is used to check if a character is received.
-
-
-static __INLINE int ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-
-
ITM Debug Support in uVision
-
- uVision uses in a debug session the Debug (printf) Viewer window to
- display the debug data.
-
-
Direction microcontroller system -> uVision:
-
-
- Characters received via ITM communication channel 0 are written in a printf style
- to Debug (printf) Viewer window.
-
-
-
-
Direction uVision -> microcontroller system:
-
-
Check if ITM_RxBuffer variable is available (only performed once).
-
Read character from Debug (printf) Viewer window.
-
If ITM_RxBuffer empty write character to ITM_RxBuffer.
-
-
-
Note
-
-
Current solution does not use a buffer machanism for trasmitting the characters.
-
-
-
-
RTX Kernel awareness in uVision
-
- uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
- No format overhead is necessary.
- uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
- to ITM communication channel 31.
-
-
-
Following RTX events are traced:
-
-
Task Create / Delete event
-
-
32 bit access. Task start address is transmitted
-
16 bit access. Task ID and Create/Delete flag are transmitted
- High byte holds Create/Delete flag, Low byte holds TASK ID.
-
-
-
-
Task switch event
-
-
8 bit access. Task ID of current task is transmitted
-
-
-
-
-
Note
-
-
Other RTOS information could be retrieved via memory read access in a polling mode manner.
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CMSIS_changes.htm b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CMSIS_changes.htm
deleted file mode 100644
index 162ffcc9..00000000
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CMSIS_changes.htm
+++ /dev/null
@@ -1,320 +0,0 @@
-
-
-
-CMSIS Changes
-
-
-
-
-
-
-
-
-
Changes to CMSIS version V1.20
-
-
-
-
1. Removed CMSIS Middelware packages
-
- CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
-
-
-
2. SystemFrequency renamed to SystemCoreClock
-
- The variable name SystemCoreClock is more precise than SystemFrequency
- because the variable holds the clock value at which the core is running.
-
-
-
3. Changed startup concept
-
- The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
- from main) has the weakness that it does not work for controllers which need a already
- configuerd clock system to configure the external memory controller.
-
-
-
Changed startup concept
-
-
- SystemInit() is called from startup file before premain.
-
-
- SystemInit() configures the clock system and also configures
- an existing external memory controller.
-
-
- SystemInit() must not use global variables.
-
-
- SystemCoreClock is initialized with a correct predefined value.
-
-
- Additional function void SystemCoreClockUpdate (void) is provided.
- SystemCoreClockUpdate() updates the variable SystemCoreClock
- and must be called whenever the core clock is changed.
- SystemCoreClockUpdate() evaluates the clock register settings and calculates
- the current core clock.
-
-
-
-
-
4. Advanced Debug Functions
-
- ITM communication channel is only capable for OUT direction. To allow also communication for
- IN direction a simple concept is provided.
-
-
-
- Global variable volatile int ITM_RxBuffer used for IN data.
-
-
- Function int ITM_CheckChar (void) checks if a new character is available.
-
-
- Function int ITM_ReceiveChar (void) retrieves the new character.
-
-
-
-
- For detailed explanation see file CMSIS debug support.htm.
-
-
-
-
5. Core Register Bit Definitions
-
- Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
- defines correspond with the Cortex-M Technical Reference Manual.
-
- DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
- using DoxyGen.
-
-
-
8. Folder Structure
-
- The folder structure is changed to differentiate the single support packages.
-
-
-
-
CM0
-
CM3
-
-
CoreSupport
-
DeviceSupport
-
-
Vendor
-
-
Device
-
-
Startup
-
-
Toolchain
-
Toolchain
-
...
-
-
-
-
-
Device
-
...
-
-
-
Vendor
-
...
-
-
-
Example
-
-
Toolchain
-
-
Device
-
Device
-
...
-
-
-
Toolchain
-
...
-
-
-
-
-
-
Documentation
-
-
-
9. Open Points
-
- Following points need to be clarified and solved:
-
-
-
-
- Equivalent C and Assembler startup files.
-
-
- Is there a need for having C startup files although assembler startup files are
- very efficient and do not need to be changed?
-
-
-
-
- Placing of HEAP in external RAM.
-
-
- It must be possible to place HEAP in external RAM if the device supports an
- external memory controller.
-
-
-
-
- Placing of STACK /HEAP.
-
-
- STACK should always be placed at the end of internal RAM.
-
-
- If HEAP is placed in internal RAM than it should be placed after RW ZI section.
-
-
-
-
- Removing core_cm3.c and core_cm0.c.
-
-
- On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
- appropriate compiler intrinsics.
-
-
-
-
-
-
10. Limitations
-
- The following limitations are not covered with the current CMSIS version:
-
-
-
- No C startup files for ARM toolchain are provided.
-
-
- No C startup files for GNU toolchain are provided.
-
-
- No C startup files for IAR toolchain are provided.
-
-
- No Tasking projects are provided yet.
-
-
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/License.doc b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/License.doc
deleted file mode 100644
index b6b8acec..00000000
Binary files a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_Crossworks/Prog/lib/stdperiphlib/CMSIS/License.doc and /dev/null differ
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/bin/openblt_olimex_stm32p103.elf b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/bin/openblt_olimex_stm32p103.elf
index 4d28bbb7..cf513665 100644
Binary files a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/bin/openblt_olimex_stm32p103.elf and b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/bin/openblt_olimex_stm32p103.elf differ
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/bin/openblt_olimex_stm32p103.map b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/bin/openblt_olimex_stm32p103.map
index 0f9cb30f..602d8dad 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/bin/openblt_olimex_stm32p103.map
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/bin/openblt_olimex_stm32p103.map
@@ -1,17 +1,17 @@
-Archive member included because of file (symbol)
+Archive member included to satisfy reference by file (symbol)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
THUMB Debug/../../obj/file.o (isdigit)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2_asm.o)
- C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o) (memcpy)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc_asm.o)
- C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o) (__umoddi3)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- (__do_debug_operation_mempoll)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o) (__errno)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v7m_t_le.a(libm_asm.o)
- C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o) (__floatsisf)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o) (memcpy)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o) (__aeabi_uldivmod)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o) (__aeabi_i2f)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfprintf_v7m_t_le_eabi.o (frexp)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o) (fabs)
Discarded input sections
@@ -21,60 +21,33 @@ Discarded input sections
.text 0x00000000 0x0 THUMB Debug/../../obj/main.o
.data 0x00000000 0x0 THUMB Debug/../../obj/main.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/main.o
- .text 0x00000000 0x0 THUMB Debug/../../obj/core_cm3.o
- .data 0x00000000 0x0 THUMB Debug/../../obj/core_cm3.o
- .bss 0x00000000 0x0 THUMB Debug/../../obj/core_cm3.o
- .text.__get_PSP
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__set_PSP
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__get_MSP
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__set_MSP
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__get_BASEPRI
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__set_BASEPRI
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__get_PRIMASK
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__set_PRIMASK
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__get_FAULTMASK
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__set_FAULTMASK
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__get_CONTROL
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__set_CONTROL
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__REV 0x00000000 0x4 THUMB Debug/../../obj/core_cm3.o
- .text.__REV16 0x00000000 0x4 THUMB Debug/../../obj/core_cm3.o
- .text.__REVSH 0x00000000 0x4 THUMB Debug/../../obj/core_cm3.o
- .text.__RBIT 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__LDREXB
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__LDREXH
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__LDREXW
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__STREXB
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__STREXH
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__STREXW
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
.text 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f10x.o
.data 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f10x.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f10x.o
.text.SystemInit
- 0x00000000 0x130 THUMB Debug/../../obj/system_stm32f10x.o
+ 0x00000000 0x100 THUMB Debug/../../obj/system_stm32f10x.o
.text.SystemCoreClockUpdate
- 0x00000000 0xe0 THUMB Debug/../../obj/system_stm32f10x.o
+ 0x00000000 0x8c THUMB Debug/../../obj/system_stm32f10x.o
.data.AHBPrescTable
0x00000000 0x10 THUMB Debug/../../obj/system_stm32f10x.o
.data.SystemCoreClock
0x00000000 0x4 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_frame 0x00000000 0x40 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_info 0x00000000 0x492 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_abbrev 0x00000000 0x175 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_loc 0x00000000 0xe8 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_pubnames
+ 0x00000000 0x97 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_pubtypes
+ 0x00000000 0x10d THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_aranges
+ 0x00000000 0x28 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_ranges 0x00000000 0x18 THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_line 0x00000000 0x22d THUMB Debug/../../obj/system_stm32f10x.o
+ .debug_str 0x00000000 0x400 THUMB Debug/../../obj/system_stm32f10x.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/system_stm32f10x.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/system_stm32f10x.o
.text 0x00000000 0x0 THUMB Debug/../../obj/mmc.o
.data 0x00000000 0x0 THUMB Debug/../../obj/mmc.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/mmc.o
@@ -82,48 +55,48 @@ Discarded input sections
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_gpio.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_DeInit
- 0x00000000 0x11c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0xcc THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_AFIODeInit
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
- .text.GPIO_StructInit
0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_gpio.o
- .text.GPIO_ReadInputDataBit
+ .text.GPIO_StructInit
0x00000000 0x10 THUMB Debug/../../obj/stm32f10x_gpio.o
+ .text.GPIO_ReadInputDataBit
+ 0x00000000 0xc THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_ReadInputData
0x00000000 0x8 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_ReadOutputDataBit
- 0x00000000 0x10 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0xc THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_ReadOutputData
0x00000000 0x8 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_WriteBit
0x00000000 0xc THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_Write
- 0x00000000 0x8 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x4 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_PinLockConfig
- 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x10 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_EventOutputConfig
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_EventOutputCmd
0x00000000 0xc THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_PinRemapConfig
- 0x00000000 0x88 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x6c THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_EXTILineConfig
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_ETH_MediaInterfaceConfig
0x00000000 0xc THUMB Debug/../../obj/stm32f10x_gpio.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rcc.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rcc.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_DeInit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_HSEConfig
- 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_AdjustHSICalibrationValue
- 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_HSICmd
0x00000000 0xc THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_PLLConfig
- 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_PLLCmd
0x00000000 0xc THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_SYSCLKConfig
@@ -135,15 +108,15 @@ Discarded input sections
.text.RCC_PCLK1Config
0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_PCLK2Config
- 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ITConfig
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_USBCLKConfig
0x00000000 0xc THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ADCCLKConfig
0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_LSEConfig
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_LSICmd
0x00000000 0xc THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_RTCCLKConfig
@@ -151,29 +124,29 @@ Discarded input sections
.text.RCC_RTCCLKCmd
0x00000000 0xc THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_GetClocksFreq
- 0x00000000 0xe8 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0xb4 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_AHBPeriphClockCmd
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_APB2PeriphResetCmd
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_APB1PeriphResetCmd
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_BackupResetCmd
0x00000000 0xc THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ClockSecuritySystemCmd
0x00000000 0xc THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_MCOConfig
- 0x00000000 0x10 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0xc THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_GetFlagStatus
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_WaitForHSEStartUp
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ClearFlag
- 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_rcc.o
- .text.RCC_GetITStatus
- 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_rcc.o
- .text.RCC_ClearITPendingBit
0x00000000 0x10 THUMB Debug/../../obj/stm32f10x_rcc.o
+ .text.RCC_GetITStatus
+ 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_rcc.o
+ .text.RCC_ClearITPendingBit
+ 0x00000000 0xc THUMB Debug/../../obj/stm32f10x_rcc.o
.data.ADCPrescTable
0x00000000 0x4 THUMB Debug/../../obj/stm32f10x_rcc.o
.data.APBAHBPrescTable
@@ -182,69 +155,69 @@ Discarded input sections
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_spi.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_DeInit
- 0x00000000 0x7c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x64 THUMB Debug/../../obj/stm32f10x_spi.o
.text.I2S_Init
- 0x00000000 0xdc THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0xa8 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_StructInit
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_spi.o
- .text.I2S_StructInit
0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_spi.o
- .text.I2S_Cmd 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_spi.o
+ .text.I2S_StructInit
+ 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_spi.o
+ .text.I2S_Cmd 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_ITConfig
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_DMACmd
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_NSSInternalSoftwareConfig
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_SSOutputCmd
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_spi.o
- .text.SPI_DataSizeConfig
0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_spi.o
+ .text.SPI_DataSizeConfig
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_TransmitCRC
0x00000000 0xc THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_GetCRC
- 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0xc THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_GetCRCPolynomial
0x00000000 0x8 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_BiDirectionalLineConfig
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_ClearFlag
- 0x00000000 0xc THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x8 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_GetITStatus
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_ClearITPendingBit
- 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_spi.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_usart.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_usart.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_DeInit
- 0x00000000 0xcc THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0xa4 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_Init
- 0x00000000 0xf8 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0xb8 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_StructInit
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_ClockInit
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_ClockStructInit
- 0x00000000 0x10 THUMB Debug/../../obj/stm32f10x_usart.o
- .text.USART_Cmd
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_usart.o
- .text.USART_ITConfig
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
- .text.USART_DMACmd
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_usart.o
- .text.USART_SetAddress
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_usart.o
- .text.USART_WakeUpConfig
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_usart.o
- .text.USART_ReceiverWakeUpCmd
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_usart.o
- .text.USART_LINBreakDetectLengthConfig
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_usart.o
- .text.USART_LINCmd
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_usart.o
- .text.USART_ReceiveData
0x00000000 0xc THUMB Debug/../../obj/stm32f10x_usart.o
+ .text.USART_Cmd
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_usart.o
+ .text.USART_ITConfig
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_usart.o
+ .text.USART_DMACmd
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_usart.o
+ .text.USART_SetAddress
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_usart.o
+ .text.USART_WakeUpConfig
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_usart.o
+ .text.USART_ReceiverWakeUpCmd
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_usart.o
+ .text.USART_LINBreakDetectLengthConfig
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+ .text.USART_LINCmd
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+ .text.USART_ReceiveData
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.text.USART_SendBreak
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.text.USART_SetGuardTime
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.text.USART_SmartCardCmd
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- .text.USART_GetITStatus
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- .text.USART_ClearITPendingBit
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.text 0x00000000 0x0 THUMB Debug/../../obj/can.o
.data 0x00000000 0x0 THUMB Debug/../../obj/can.o
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.text 0x00000000 0x0 THUMB Debug/../../obj/cpu.o
.data 0x00000000 0x0 THUMB Debug/../../obj/cpu.o
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.text 0x00000000 0x0 THUMB Debug/../../obj/flash.o
.data 0x00000000 0x0 THUMB Debug/../../obj/flash.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/flash.o
+ .text.FlashReinit
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.data 0x00000000 0x0 THUMB Debug/../../obj/nvm.o
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.data 0x00000000 0x0 THUMB Debug/../../obj/timer.o
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.data 0x00000000 0x0 THUMB Debug/../../obj/usb.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/usb.o
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+ 0x00000000 0x2c0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.acosh
+ 0x00000000 0x108 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.asinh
+ 0x00000000 0x114 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.hypot
+ 0x00000000 0x1d4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.asin
+ 0x00000000 0x268 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.acos
+ 0x00000000 0x268 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.sqrtf
+ 0x00000000 0xb8 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.__RAL_asinacosf
+ 0x00000000 0x1d4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.acoshf
+ 0x00000000 0xc8 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.asinhf
+ 0x00000000 0xb4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.hypotf
+ 0x00000000 0x140 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.asinf
+ 0x00000000 0x184 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.acosf
+ 0x00000000 0x1a4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.cbrtf
+ 0x00000000 0xf0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.cbrt
+ 0x00000000 0x1cc C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.floor
+ 0x00000000 0x90 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.fmodf
+ 0x00000000 0xf8 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc.fmod
+ 0x00000000 0x154 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .rodata.libc.__asinacosf_a
+ 0x00000000 0x8 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .rodata.libc.__asinacosf_b
+ 0x00000000 0x8 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .rodata.libc.atanf_a
+ 0x00000000 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .rodata.libc.__asinacos_a
+ 0x00000000 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .rodata.libc.__asinacos_b
+ 0x00000000 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .debug_frame 0x00000000 0xb80 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .debug_info 0x00000000 0x847 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .debug_abbrev 0x00000000 0xdb C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .debug_aranges
+ 0x00000000 0x228 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .debug_ranges 0x00000000 0x750 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .debug_line 0x00000000 0x345 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .debug_str 0x00000000 0x364 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .comment 0x00000000 0x4d C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .ARM.attributes
+ 0x00000000 0x2d C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ .text.libc 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ .data.libc 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ .bss.libc 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ .text.libc.fabs
+ 0x00000000 0x8 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ .text.libc.fabsf
+ 0x00000000 0x8 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ .text.libc.ceilf
+ 0x00000000 0x60 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ .text.libc.floorf
+ 0x00000000 0x5c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ .text.libc.ldexpf
+ 0x00000000 0x38 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ .text.libc.frexpf
+ 0x00000000 0x2c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ .debug_frame 0x00000000 0x70 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ .ARM.attributes
+ 0x00000000 0x1b C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
Memory Configuration
@@ -1095,7 +2115,8 @@ FLASH 0x08000000 0x00006000 xr
Linker script and memory map
- 0x08004d50 __do_debug_operation = __do_debug_operation_mempoll
+ 0x00000000 __vfprintf = __vfprintf_float_long_long
+ 0x00000000 __vfscanf = __vfscanf_float_long_long_cc
0x20000000 __SRAM_segment_start__ = 0x20000000
0x20002000 __SRAM_segment_end__ = 0x20002000
0x08000000 __FLASH_segment_start__ = 0x8000000
@@ -1128,486 +2149,543 @@ Linker script and memory map
0x00000001 . = ASSERT (((__vectors_end__ >= __FLASH_segment_start__) && (__vectors_end__ <= __FLASH_segment_end__)), error: .vectors is too large to fit in FLASH memory segment)
0x08000150 __init_load_start__ = ALIGN (__vectors_end__, 0x4)
-.init 0x08000150 0x104
+.init 0x08000150 0x108
0x08000150 __init_start__ = .
*(.init .init.*)
- .init 0x08000150 0x104 THUMB Debug/../../obj/cstart.o
+ .init 0x08000150 0x108 THUMB Debug/../../obj/cstart.o
0x08000150 reset_handler
- 0x080001ce exit
- 0x08000254 __init_end__ = (__init_start__ + SIZEOF (.init))
- 0x08000254 __init_load_end__ = __init_end__
+ 0x080001d2 exit
+ 0x08000258 __init_end__ = (__init_start__ + SIZEOF (.init))
+ 0x08000258 __init_load_end__ = __init_end__
0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= __FLASH_segment_end__)), error: .init is too large to fit in FLASH memory segment)
- 0x08000254 __text_load_start__ = ALIGN (__init_end__, 0x4)
+ 0x08000258 __text_load_start__ = ALIGN (__init_end__, 0x4)
-.text 0x08000254 0x4b3c
- 0x08000254 __text_start__ = .
+.text 0x08000258 0x4318
+ 0x08000258 __text_start__ = .
*(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table .ARM.extab* .gnu.linkonce.armextab.*)
- .glue_7 0x00000000 0x0 linker stubs
- .glue_7t 0x00000000 0x0 linker stubs
+ .glue_7 0x08000258 0x0 linker stubs
+ .glue_7t 0x08000258 0x0 linker stubs
.text.FileIsFirmwareUpdateRequestedHook
- 0x08000254 0x4c THUMB Debug/../../obj/hooks.o
- 0x08000254 FileIsFirmwareUpdateRequestedHook
+ 0x08000258 0x3c THUMB Debug/../../obj/hooks.o
+ 0x08000258 FileIsFirmwareUpdateRequestedHook
.text.FileGetFirmwareFilenameHook
- 0x080002a0 0xc THUMB Debug/../../obj/hooks.o
- 0x080002a0 FileGetFirmwareFilenameHook
+ 0x08000294 0x8 THUMB Debug/../../obj/hooks.o
+ 0x08000294 FileGetFirmwareFilenameHook
.text.FileFirmwareUpdateStartedHook
- 0x080002ac 0x38 THUMB Debug/../../obj/hooks.o
- 0x080002ac FileFirmwareUpdateStartedHook
+ 0x0800029c 0x28 THUMB Debug/../../obj/hooks.o
+ 0x0800029c FileFirmwareUpdateStartedHook
.text.FileFirmwareUpdateCompletedHook
- 0x080002e4 0x58 THUMB Debug/../../obj/hooks.o
- 0x080002e4 FileFirmwareUpdateCompletedHook
+ 0x080002c4 0x48 THUMB Debug/../../obj/hooks.o
+ 0x080002c4 FileFirmwareUpdateCompletedHook
.text.FileFirmwareUpdateErrorHook
- 0x0800033c 0x24 THUMB Debug/../../obj/hooks.o
- 0x0800033c FileFirmwareUpdateErrorHook
+ 0x0800030c 0x18 THUMB Debug/../../obj/hooks.o
+ 0x0800030c FileFirmwareUpdateErrorHook
.text.FileFirmwareUpdateLogHook
- 0x08000360 0x64 THUMB Debug/../../obj/hooks.o
- 0x08000360 FileFirmwareUpdateLogHook
- .text.main 0x080003c4 0x1c0 THUMB Debug/../../obj/main.o
- 0x080003c4 main
+ 0x08000324 0x50 THUMB Debug/../../obj/hooks.o
+ 0x08000324 FileFirmwareUpdateLogHook
+ .text.main 0x08000374 0x188 THUMB Debug/../../obj/main.o
+ 0x08000374 main
.text.xchg_spi
- 0x08000584 0x38 THUMB Debug/../../obj/mmc.o
+ 0x080004fc 0x28 THUMB Debug/../../obj/mmc.o
.text.wait_ready
- 0x080005bc 0x2c THUMB Debug/../../obj/mmc.o
- .text.rcvr_spi_m
- 0x080005e8 0x10 THUMB Debug/../../obj/mmc.o
- .text.rcvr_datablock
- 0x080005f8 0x64 THUMB Debug/../../obj/mmc.o
- .text.xmit_datablock
- 0x0800065c 0x60 THUMB Debug/../../obj/mmc.o
+ 0x08000524 0x2c THUMB Debug/../../obj/mmc.o
.text.deselect
- 0x080006bc 0x20 THUMB Debug/../../obj/mmc.o
- .text.select 0x080006dc 0x34 THUMB Debug/../../obj/mmc.o
+ 0x08000550 0x18 THUMB Debug/../../obj/mmc.o
+ .text.select 0x08000568 0x2c THUMB Debug/../../obj/mmc.o
.text.send_cmd
- 0x08000710 0xac THUMB Debug/../../obj/mmc.o
+ 0x08000594 0x90 THUMB Debug/../../obj/mmc.o
+ .text.xmit_datablock
+ 0x08000624 0x5c THUMB Debug/../../obj/mmc.o
+ .text.rcvr_datablock
+ 0x08000680 0x5c THUMB Debug/../../obj/mmc.o
.text.disk_initialize
- 0x080007bc 0x364 THUMB Debug/../../obj/mmc.o
- 0x080007bc disk_initialize
+ 0x080006dc 0x2e0 THUMB Debug/../../obj/mmc.o
+ 0x080006dc disk_initialize
.text.disk_status
- 0x08000b20 0x18 THUMB Debug/../../obj/mmc.o
- 0x08000b20 disk_status
+ 0x080009bc 0x14 THUMB Debug/../../obj/mmc.o
+ 0x080009bc disk_status
.text.disk_read
- 0x08000b38 0xa8 THUMB Debug/../../obj/mmc.o
- 0x08000b38 disk_read
+ 0x080009d0 0x8c THUMB Debug/../../obj/mmc.o
+ 0x080009d0 disk_read
.text.disk_write
- 0x08000be0 0xd4 THUMB Debug/../../obj/mmc.o
- 0x08000be0 disk_write
+ 0x08000a5c 0xac THUMB Debug/../../obj/mmc.o
+ 0x08000a5c disk_write
.text.disk_ioctl
- 0x08000cb4 0x310 THUMB Debug/../../obj/mmc.o
- 0x08000cb4 disk_ioctl
- .text.get_fattime
- 0x08000fc4 0xc THUMB Debug/../../obj/mmc.o
- 0x08000fc4 get_fattime
+ 0x08000b08 0x268 THUMB Debug/../../obj/mmc.o
+ 0x08000b08 disk_ioctl
.text.GPIO_Init
- 0x08000fd0 0xc0 THUMB Debug/../../obj/stm32f10x_gpio.o
- 0x08000fd0 GPIO_Init
+ 0x08000d70 0xa0 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x08000d70 GPIO_Init
.text.GPIO_SetBits
- 0x08001090 0x8 THUMB Debug/../../obj/stm32f10x_gpio.o
- 0x08001090 GPIO_SetBits
+ 0x08000e10 0x4 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x08000e10 GPIO_SetBits
.text.GPIO_ResetBits
- 0x08001098 0x8 THUMB Debug/../../obj/stm32f10x_gpio.o
- 0x08001098 GPIO_ResetBits
+ 0x08000e14 0x4 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x08000e14 GPIO_ResetBits
.text.RCC_APB2PeriphClockCmd
- 0x080010a0 0x24 THUMB Debug/../../obj/stm32f10x_rcc.o
- 0x080010a0 RCC_APB2PeriphClockCmd
+ 0x08000e18 0x1c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x08000e18 RCC_APB2PeriphClockCmd
.text.RCC_APB1PeriphClockCmd
- 0x080010c4 0x24 THUMB Debug/../../obj/stm32f10x_rcc.o
- 0x080010c4 RCC_APB1PeriphClockCmd
+ 0x08000e34 0x1c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x08000e34 RCC_APB1PeriphClockCmd
.text.SPI_Init
- 0x080010e8 0x44 THUMB Debug/../../obj/stm32f10x_spi.o
- 0x080010e8 SPI_Init
- .text.SPI_Cmd 0x0800112c 0x20 THUMB Debug/../../obj/stm32f10x_spi.o
- 0x0800112c SPI_Cmd
+ 0x08000e50 0x40 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x08000e50 SPI_Init
+ .text.SPI_Cmd 0x08000e90 0x1c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x08000e90 SPI_Cmd
.text.SPI_I2S_SendData
- 0x0800114c 0x8 THUMB Debug/../../obj/stm32f10x_spi.o
- 0x0800114c SPI_I2S_SendData
+ 0x08000eac 0x4 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x08000eac SPI_I2S_SendData
.text.SPI_I2S_ReceiveData
- 0x08001154 0x8 THUMB Debug/../../obj/stm32f10x_spi.o
- 0x08001154 SPI_I2S_ReceiveData
+ 0x08000eb0 0x8 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x08000eb0 SPI_I2S_ReceiveData
.text.SPI_CalculateCRC
- 0x0800115c 0x20 THUMB Debug/../../obj/stm32f10x_spi.o
- 0x0800115c SPI_CalculateCRC
+ 0x08000eb8 0x1c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x08000eb8 SPI_CalculateCRC
.text.SPI_I2S_GetFlagStatus
- 0x0800117c 0x10 THUMB Debug/../../obj/stm32f10x_spi.o
- 0x0800117c SPI_I2S_GetFlagStatus
+ 0x08000ed4 0xc THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x08000ed4 SPI_I2S_GetFlagStatus
.text.USART_SendData
- 0x0800118c 0xc THUMB Debug/../../obj/stm32f10x_usart.o
- 0x0800118c USART_SendData
+ 0x08000ee0 0x8 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x08000ee0 USART_SendData
.text.USART_GetFlagStatus
- 0x08001198 0x10 THUMB Debug/../../obj/stm32f10x_usart.o
- 0x08001198 USART_GetFlagStatus
- .text.CanInit 0x080011a8 0x180 THUMB Debug/../../obj/can.o
- 0x080011a8 CanInit
+ 0x08000ee8 0xc THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x08000ee8 USART_GetFlagStatus
+ .text.CanInit 0x08000ef4 0x130 THUMB Debug/../../obj/can.o
+ 0x08000ef4 CanInit
.text.CanTransmitPacket
- 0x08001328 0xac THUMB Debug/../../obj/can.o
- 0x08001328 CanTransmitPacket
+ 0x08001024 0x98 THUMB Debug/../../obj/can.o
+ 0x08001024 CanTransmitPacket
.text.CanReceivePacket
- 0x080013d4 0x98 THUMB Debug/../../obj/can.o
- 0x080013d4 CanReceivePacket
- .text.CpuInit 0x0800146c 0xc THUMB Debug/../../obj/cpu.o
- 0x0800146c CpuInit
+ 0x080010bc 0x74 THUMB Debug/../../obj/can.o
+ 0x080010bc CanReceivePacket
+ .text.CpuInit 0x08001130 0x8 THUMB Debug/../../obj/cpu.o
+ 0x08001130 CpuInit
.text.CpuStartUserProgram
- 0x08001478 0x34 THUMB Debug/../../obj/cpu.o
- 0x08001478 CpuStartUserProgram
+ 0x08001138 0x34 THUMB Debug/../../obj/cpu.o
+ 0x08001138 CpuStartUserProgram
.text.CpuMemCopy
- 0x080014ac 0x28 THUMB Debug/../../obj/cpu.o
- 0x080014ac CpuMemCopy
- .text.FlashUnlock
- 0x080014d4 0x24 THUMB Debug/../../obj/flash.o
+ 0x0800116c 0x24 THUMB Debug/../../obj/cpu.o
+ 0x0800116c CpuMemCopy
.text.FlashLock
- 0x080014f8 0x14 THUMB Debug/../../obj/flash.o
+ 0x08001190 0x10 THUMB Debug/../../obj/flash.o
.text.FlashGetSector
- 0x0800150c 0x48 THUMB Debug/../../obj/flash.o
+ 0x080011a0 0x38 THUMB Debug/../../obj/flash.o
.text.FlashWriteBlock
- 0x08001554 0xc8 THUMB Debug/../../obj/flash.o
- .text.FlashGetSectorBaseAddr
- 0x0800161c 0x40 THUMB Debug/../../obj/flash.o
- .text.FlashInitBlock
- 0x0800165c 0x38 THUMB Debug/../../obj/flash.o
+ 0x080011d8 0xb4 THUMB Debug/../../obj/flash.o
.text.FlashSwitchBlock
- 0x08001694 0x50 THUMB Debug/../../obj/flash.o
+ 0x0800128c 0x58 THUMB Debug/../../obj/flash.o
.text.FlashAddToBlock
- 0x080016e4 0x94 THUMB Debug/../../obj/flash.o
+ 0x080012e4 0x84 THUMB Debug/../../obj/flash.o
.text.FlashInit
- 0x08001778 0x1c THUMB Debug/../../obj/flash.o
- 0x08001778 FlashInit
+ 0x08001368 0x18 THUMB Debug/../../obj/flash.o
+ 0x08001368 FlashInit
.text.FlashWrite
- 0x08001794 0x58 THUMB Debug/../../obj/flash.o
- 0x08001794 FlashWrite
+ 0x08001380 0x50 THUMB Debug/../../obj/flash.o
+ 0x08001380 FlashWrite
.text.FlashErase
- 0x080017ec 0x140 THUMB Debug/../../obj/flash.o
- 0x080017ec FlashErase
+ 0x080013d0 0x148 THUMB Debug/../../obj/flash.o
+ 0x080013d0 FlashErase
.text.FlashWriteChecksum
- 0x0800192c 0x5c THUMB Debug/../../obj/flash.o
- 0x0800192c FlashWriteChecksum
+ 0x08001518 0x50 THUMB Debug/../../obj/flash.o
+ 0x08001518 FlashWriteChecksum
.text.FlashVerifyChecksum
- 0x08001988 0x68 THUMB Debug/../../obj/flash.o
- 0x08001988 FlashVerifyChecksum
+ 0x08001568 0x50 THUMB Debug/../../obj/flash.o
+ 0x08001568 FlashVerifyChecksum
.text.FlashDone
- 0x080019f0 0x58 THUMB Debug/../../obj/flash.o
- 0x080019f0 FlashDone
+ 0x080015b8 0x3c THUMB Debug/../../obj/flash.o
+ 0x080015b8 FlashDone
.text.FlashGetUserProgBaseAddress
- 0x08001a48 0xc THUMB Debug/../../obj/flash.o
- 0x08001a48 FlashGetUserProgBaseAddress
- .text.NvmInit 0x08001a54 0xc THUMB Debug/../../obj/nvm.o
- 0x08001a54 NvmInit
+ 0x080015f4 0x8 THUMB Debug/../../obj/flash.o
+ 0x080015f4 FlashGetUserProgBaseAddress
+ .text.NvmInit 0x080015fc 0x8 THUMB Debug/../../obj/nvm.o
+ 0x080015fc NvmInit
.text.NvmWrite
- 0x08001a60 0xc THUMB Debug/../../obj/nvm.o
- 0x08001a60 NvmWrite
+ 0x08001604 0x8 THUMB Debug/../../obj/nvm.o
+ 0x08001604 NvmWrite
.text.NvmErase
- 0x08001a6c 0xc THUMB Debug/../../obj/nvm.o
- 0x08001a6c NvmErase
+ 0x0800160c 0x8 THUMB Debug/../../obj/nvm.o
+ 0x0800160c NvmErase
.text.NvmVerifyChecksum
- 0x08001a78 0xc THUMB Debug/../../obj/nvm.o
- 0x08001a78 NvmVerifyChecksum
+ 0x08001614 0x8 THUMB Debug/../../obj/nvm.o
+ 0x08001614 NvmVerifyChecksum
.text.NvmGetUserProgBaseAddress
- 0x08001a84 0xc THUMB Debug/../../obj/nvm.o
- 0x08001a84 NvmGetUserProgBaseAddress
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- 0x08001a90 NvmDone
- .text.TimerReset
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- 0x08001aa8 TimerReset
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+ 0x0800161c NvmGetUserProgBaseAddress
+ .text.NvmDone 0x08001624 0x14 THUMB Debug/../../obj/nvm.o
+ 0x08001624 NvmDone
.text.TimerInit
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- 0x08001ab8 TimerInit
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+ 0x08001638 TimerInit
+ .text.TimerReset
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+ 0x0800165c TimerReset
.text.TimerUpdate
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+ 0x08001668 TimerUpdate
.text.TimerGet
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- 0x08001b10 TimerGet
- .text.UartReceiveByte
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+ 0x08001684 TimerGet
.text.UartTransmitByte
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.text.UartInit
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.text.UartTransmitPacket
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.text.UartReceivePacket
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.text.CpuIrqDisable
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.text.CpuIrqEnable
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.text.UnusedISR
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.text.AssertFailure
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.text.BackDoorCheck
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.text.BackDoorInit
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.text.BootInit
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+ 0x08001888 BootInit
.text.BootTask
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- .text.ComTask 0x08001e30 0x5c THUMB Debug/../../obj/com.o
- 0x08001e30 ComTask
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- 0x08001e8c ComFree
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.text.ComTransmitPacket
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.text.ComGetActiveInterfaceMaxRxLen
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.text.ComGetActiveInterfaceMaxTxLen
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.text.ComIsConnected
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+ 0x08001990 ComIsConnected
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.text.CopService
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+ .text.libc.__RAL_ascii_tolower
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- 0x08004d90 __text_load_end__ = __text_end__
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.vfp11_veneer 0x00000000 0x0 linker stubs
.v4_bx 0x00000000 0x0
.v4_bx 0x00000000 0x0 linker stubs
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-.dtors 0x08004d90 0x0
- 0x08004d90 __dtors_start__ = .
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+ .iplt 0x00000000 0x0 THUMB Debug/../../obj/hooks.o
+ 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= __FLASH_segment_end__)), error: .text is too large to fit in FLASH memory segment)
+ 0x08004570 __dtors_load_start__ = ALIGN (__text_end__, 0x4)
+
+.dtors 0x08004570 0x0
+ 0x08004570 __dtors_start__ = .
*(SORT(.dtors.*))
*(.dtors)
*(.fini_array .fini_array.*)
- 0x08004d90 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
- 0x08004d90 __dtors_load_end__ = __dtors_end__
+ 0x08004570 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
+ 0x08004570 __dtors_load_end__ = __dtors_end__
0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= __FLASH_segment_end__)), error: .dtors is too large to fit in FLASH memory segment)
- 0x08004d90 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
+ 0x08004570 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
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- 0x08004d90 __ctors_start__ = .
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+ 0x08004570 __ctors_start__ = .
*(SORT(.ctors.*))
*(.ctors)
*(.init_array .init_array.*)
- 0x08004d90 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
- 0x08004d90 __ctors_load_end__ = __ctors_end__
+ 0x08004570 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
+ 0x08004570 __ctors_load_end__ = __ctors_end__
0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= __FLASH_segment_end__)), error: .ctors is too large to fit in FLASH memory segment)
- 0x08004d90 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
+ 0x08004570 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
-.rodata 0x08004d90 0xa98
- 0x08004d90 __rodata_start__ = .
+.rodata 0x08004570 0xc80
+ 0x08004570 __rodata_start__ = .
*(.rodata .rodata.* .gnu.linkonce.r.*)
.rodata.firmwareFilename
- 0x08004d90 0x20 THUMB Debug/../../obj/hooks.o
+ 0x08004570 0x20 THUMB Debug/../../obj/hooks.o
.rodata.str1.4
- 0x08004db0 0xd THUMB Debug/../../obj/hooks.o
- 0x10 (size before relaxing)
- *fill* 0x08004dbd 0x3 00
+ 0x08004590 0xd THUMB Debug/../../obj/hooks.o
+ *fill* 0x0800459d 0x3
.rodata.str1.4
- 0x08004dc0 0x63 THUMB Debug/../../obj/main.o
- 0x64 (size before relaxing)
- *fill* 0x08004e23 0x1 00
+ 0x080045a0 0x63 THUMB Debug/../../obj/main.o
+ *fill* 0x08004603 0x1
.rodata.str1.4
- 0x08004e24 0x81 THUMB Debug/../../obj/can.o
- 0x84 (size before relaxing)
- *fill* 0x08004ea5 0x3 00
+ 0x08004604 0x81 THUMB Debug/../../obj/can.o
+ *fill* 0x08004685 0x3
.rodata.canTiming
- 0x08004ea8 0x48 THUMB Debug/../../obj/can.o
+ 0x08004688 0x24 THUMB Debug/../../obj/can.o
.rodata.flashLayout
- 0x08004ef0 0x9c THUMB Debug/../../obj/flash.o
+ 0x080046ac 0x9c THUMB Debug/../../obj/flash.o
.rodata.str1.4
- 0x08004f8c 0x82 THUMB Debug/../../obj/uart.o
- 0x84 (size before relaxing)
- *fill* 0x0800500e 0x2 00
+ 0x08004748 0x82 THUMB Debug/../../obj/uart.o
+ *fill* 0x080047ca 0x2
.rodata.str1.4
- 0x08005010 0x90 THUMB Debug/../../obj/vectors.o
+ 0x080047cc 0x90 THUMB Debug/../../obj/vectors.o
.rodata.xcpStationId
- 0x080050a0 0x8 THUMB Debug/../../obj/xcp.o
+ 0x0800485c 0x8 THUMB Debug/../../obj/xcp.o
.rodata.str1.4
- 0x080050a8 0x219 THUMB Debug/../../obj/file.o
- 0x220 (size before relaxing)
- *fill* 0x080052c1 0x3 00
+ 0x08004864 0x21d THUMB Debug/../../obj/file.o
+ 0x221 (size before relaxing)
+ *fill* 0x08004a81 0x3
.rodata.str1.4
- 0x080052c4 0x14 THUMB Debug/../../obj/ff.o
- .rodata.ExCvt 0x080052d8 0x80 THUMB Debug/../../obj/ff.o
+ 0x08004a84 0x13 THUMB Debug/../../obj/ff.o
+ *fill* 0x08004a97 0x1
+ .rodata.ExCvt 0x08004a98 0x80 THUMB Debug/../../obj/ff.o
.rodata.LfnOfs
- 0x08005358 0x10 THUMB Debug/../../obj/ff.o
- .rodata.tbl_upper.984
- 0x08005368 0x1e0 THUMB Debug/../../obj/unicode.o
- .rodata.tbl_lower.983
- 0x08005548 0x1e0 THUMB Debug/../../obj/unicode.o
- .rodata.Tbl 0x08005728 0x100 THUMB Debug/../../obj/unicode.o
- 0x08005828 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
- 0x08005828 __rodata_load_end__ = __rodata_end__
+ 0x08004b18 0xd THUMB Debug/../../obj/ff.o
+ *fill* 0x08004b25 0x3
+ .rodata.Tbl 0x08004b28 0x100 THUMB Debug/../../obj/unicode.o
+ .rodata.cvt2.3900
+ 0x08004c28 0xbc THUMB Debug/../../obj/unicode.o
+ .rodata.cvt1.3899
+ 0x08004ce4 0x1f2 THUMB Debug/../../obj/unicode.o
+ *fill* 0x08004ed6 0x2
+ .rodata.libc.__RAL_c_locale_abbrev_month_names
+ 0x08004ed8 0x31 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x08004ed8 __RAL_c_locale_abbrev_month_names
+ *fill* 0x08004f09 0x3
+ .rodata.libc.__RAL_data_utf8_period
+ 0x08004f0c 0x2 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x08004f0c __RAL_data_utf8_period
+ *fill* 0x08004f0e 0x2
+ .rodata.libc.str1.4
+ 0x08004f10 0xe4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0xf1 (size before relaxing)
+ .rodata.libc.__RAL_data_empty_string
+ 0x08004ff4 0x1 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x08004ff4 __RAL_data_empty_string
+ *fill* 0x08004ff5 0x3
+ .rodata.libc.__RAL_c_locale
+ 0x08004ff8 0xc C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x08004ff8 __RAL_c_locale
+ .rodata.libc.__RAL_ascii_ctype_mask
+ 0x08005004 0xd C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ *fill* 0x08005011 0x3
+ .rodata.libc.__RAL_c_locale_day_names
+ 0x08005014 0x3a C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x08005014 __RAL_c_locale_day_names
+ *fill* 0x0800504e 0x2
+ .rodata.libc.__RAL_c_locale_abbrev_day_names
+ 0x08005050 0x1d C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x08005050 __RAL_c_locale_abbrev_day_names
+ *fill* 0x0800506d 0x3
+ .rodata.libc.__RAL_c_locale_am_pm_indicator
+ 0x08005070 0x7 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x08005070 __RAL_c_locale_am_pm_indicator
+ *fill* 0x08005077 0x1
+ .rodata.libc.__RAL_c_locale_data
+ 0x08005078 0x58 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x08005078 __RAL_c_locale_data
+ .rodata.libc.__RAL_codeset_ascii
+ 0x080050d0 0x20 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x080050d0 __RAL_codeset_ascii
+ .rodata.libc.__RAL_c_locale_month_names
+ 0x080050f0 0x57 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x080050f0 __RAL_c_locale_month_names
+ *fill* 0x08005147 0x1
+ .rodata.libc.__RAL_c_locale_date_time_format
+ 0x08005148 0xf C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x08005148 __RAL_c_locale_date_time_format
+ *fill* 0x08005157 0x1
+ .rodata.libc.__RAL_c_locale_time_format
+ 0x08005158 0x9 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x08005158 __RAL_c_locale_time_format
+ *fill* 0x08005161 0x3
+ .rodata.libc.__RAL_c_locale_date_format
+ 0x08005164 0x9 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x08005164 __RAL_c_locale_date_format
+ *fill* 0x0800516d 0x3
+ .rodata.libc.__RAL_ascii_ctype_map
+ 0x08005170 0x80 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x08005170 __RAL_ascii_ctype_map
+ 0x080051f0 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
+ 0x080051f0 __rodata_load_end__ = __rodata_end__
+
+.rel.dyn 0x08000000 0x0
+ .rel.iplt 0x08000000 0x0 THUMB Debug/../../obj/hooks.o
0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= __FLASH_segment_end__)), error: .rodata is too large to fit in FLASH memory segment)
- 0x08005828 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4)
+ 0x080051f0 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4)
-.ARM.exidx 0x08005828 0x0
- 0x08005828 __ARM.exidx_start__ = .
- 0x08005828 __exidx_start = __ARM.exidx_start__
+.ARM.exidx 0x080051f0 0x0
+ 0x080051f0 __ARM.exidx_start__ = .
+ 0x080051f0 __exidx_start = __ARM.exidx_start__
*(.ARM.exidx .ARM.exidx.*)
- 0x08005828 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx))
- 0x08005828 __exidx_end = __ARM.exidx_end__
- 0x08005828 __ARM.exidx_load_end__ = __ARM.exidx_end__
+ 0x080051f0 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx))
+ 0x080051f0 __exidx_end = __ARM.exidx_end__
+ 0x080051f0 __ARM.exidx_load_end__ = __ARM.exidx_end__
0x00000001 . = ASSERT (((__ARM.exidx_end__ >= __FLASH_segment_start__) && (__ARM.exidx_end__ <= __FLASH_segment_end__)), error: .ARM.exidx is too large to fit in FLASH memory segment)
- 0x08005828 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4)
+ 0x080051f0 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4)
-.fast 0x20000000 0x0 load address 0x08005828
+.fast 0x20000000 0x0 load address 0x080051f0
0x20000000 __fast_start__ = .
*(.fast .fast.*)
0x20000000 __fast_end__ = (__fast_start__ + SIZEOF (.fast))
- 0x08005828 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
+ 0x080051f0 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
0x00000001 . = ASSERT (((__fast_load_end__ >= __FLASH_segment_start__) && (__fast_load_end__ <= __FLASH_segment_end__)), error: .fast is too large to fit in FLASH memory segment)
.fast_run 0x20000000 0x0
@@ -1616,145 +2694,146 @@ Linker script and memory map
0x20000000 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run))
0x20000000 __fast_run_load_end__ = __fast_run_end__
0x00000001 . = ASSERT (((__fast_run_end__ >= __SRAM_segment_start__) && (__fast_run_end__ <= __SRAM_segment_end__)), error: .fast_run is too large to fit in SRAM memory segment)
- 0x08005828 __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4)
+ 0x080051f0 __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4)
-.data 0x20000000 0x8 load address 0x08005828
+.data 0x20000000 0x18 load address 0x080051f0
0x20000000 __data_start__ = .
*(.data .data.* .gnu.linkonce.d.*)
.data.Stat 0x20000000 0x1 THUMB Debug/../../obj/mmc.o
- *fill* 0x20000001 0x3 00
.data.comActiveInterface
- 0x20000004 0x4 THUMB Debug/../../obj/com.o
- 0x20000008 __data_end__ = (__data_start__ + SIZEOF (.data))
- 0x08005830 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+ 0x20000001 0x1 THUMB Debug/../../obj/com.o
+ *fill* 0x20000002 0x2
+ .data.libc.__RAL_global_locale
+ 0x20000004 0x14 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ 0x20000004 __RAL_global_locale
+ 0x20000018 __data_end__ = (__data_start__ + SIZEOF (.data))
+ 0x08005208 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+
+.igot.plt 0x00000000 0x0
+ .igot.plt 0x00000000 0x0 THUMB Debug/../../obj/hooks.o
0x00000001 . = ASSERT (((__data_load_end__ >= __FLASH_segment_start__) && (__data_load_end__ <= __FLASH_segment_end__)), error: .data is too large to fit in FLASH memory segment)
-.data_run 0x20000000 0x8 load address 0x08005828
+.data_run 0x20000000 0x18 load address 0x080051f0
0x20000000 __data_run_start__ = .
- 0x20000008 . = MAX ((__data_run_start__ + SIZEOF (.data)), .)
- *fill* 0x20000000 0x8 00
- 0x20000008 __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run))
- 0x20000008 __data_run_load_end__ = __data_run_end__
+ 0x20000018 . = MAX ((__data_run_start__ + SIZEOF (.data)), .)
+ *fill* 0x20000000 0x18
+ 0x20000018 __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run))
+ 0x20000018 __data_run_load_end__ = __data_run_end__
0x00000001 . = ASSERT (((__data_run_end__ >= __SRAM_segment_start__) && (__data_run_end__ <= __SRAM_segment_end__)), error: .data_run is too large to fit in SRAM memory segment)
- 0x20000008 __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
+ 0x20000018 __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
-.bss 0x20000008 0xf4c
- 0x20000008 __bss_start__ = .
+.bss 0x20000018 0xf48
+ 0x20000018 __bss_start__ = .
*(.bss .bss.* .gnu.linkonce.b.*)
- .bss.logfile 0x20000008 0x228 THUMB Debug/../../obj/hooks.o
- .bss.CardType 0x20000230 0x4 THUMB Debug/../../obj/mmc.o
+ .bss.logfile 0x20000018 0x22c THUMB Debug/../../obj/hooks.o
+ .bss.CardType 0x20000244 0x4 THUMB Debug/../../obj/mmc.o
.bss.bootBlockInfo
- 0x20000234 0x204 THUMB Debug/../../obj/flash.o
+ 0x20000248 0x204 THUMB Debug/../../obj/flash.o
.bss.blockInfo
- 0x20000438 0x204 THUMB Debug/../../obj/flash.o
+ 0x2000044c 0x204 THUMB Debug/../../obj/flash.o
.bss.millisecond_counter
- 0x2000063c 0x4 THUMB Debug/../../obj/timer.o
- .bss.xcpCtoRxStartTime.1129
- 0x20000640 0x4 THUMB Debug/../../obj/uart.o
- .bss.xcpCtoReqPacket.1126
- 0x20000644 0x44 THUMB Debug/../../obj/uart.o
- .bss.xcpCtoRxLength.1127
- 0x20000688 0x1 THUMB Debug/../../obj/uart.o
- .bss.xcpCtoRxInProgress.1128
- 0x20000689 0x1 THUMB Debug/../../obj/uart.o
+ 0x20000650 0x4 THUMB Debug/../../obj/timer.o
+ .bss.xcpCtoReqPacket.4042
+ 0x20000654 0x41 THUMB Debug/../../obj/uart.o
+ .bss.xcpCtoRxLength.4043
+ 0x20000695 0x1 THUMB Debug/../../obj/uart.o
+ .bss.xcpCtoRxInProgress.4044
+ 0x20000696 0x1 THUMB Debug/../../obj/uart.o
+ *fill* 0x20000697 0x1
+ .bss.xcpCtoRxStartTime.4045
+ 0x20000698 0x4 THUMB Debug/../../obj/uart.o
.bss.backdoorOpen
- 0x2000068a 0x1 THUMB Debug/../../obj/backdoor.o
- *fill* 0x2000068b 0x1 00
+ 0x2000069c 0x1 THUMB Debug/../../obj/backdoor.o
+ *fill* 0x2000069d 0x3
.bss.backdoorOpenTime
- 0x2000068c 0x4 THUMB Debug/../../obj/backdoor.o
- .bss.xcpCtoReqPacket.1110
- 0x20000690 0x40 THUMB Debug/../../obj/com.o
- .bss.xcpInfo 0x200006d0 0x4c THUMB Debug/../../obj/xcp.o
+ 0x200006a0 0x4 THUMB Debug/../../obj/backdoor.o
+ .bss.xcpCtoReqPacket.4026
+ 0x200006a4 0x40 THUMB Debug/../../obj/com.o
+ .bss.xcpInfo 0x200006e4 0x4c THUMB Debug/../../obj/xcp.o
.bss.loggingStr
- 0x2000071c 0x40 THUMB Debug/../../obj/file.o
+ 0x20000730 0x40 THUMB Debug/../../obj/file.o
.bss.firmwareUpdateState
- 0x2000075c 0x4 THUMB Debug/../../obj/file.o
+ 0x20000770 0x1 THUMB Debug/../../obj/file.o
+ *fill* 0x20000771 0x3
.bss.eraseInfo
- 0x20000760 0x8 THUMB Debug/../../obj/file.o
+ 0x20000774 0x8 THUMB Debug/../../obj/file.o
.bss.fatFsObjects
- 0x20000768 0x458 THUMB Debug/../../obj/file.o
+ 0x2000077c 0x458 THUMB Debug/../../obj/file.o
.bss.lineParseObject
- 0x20000bc0 0x184 THUMB Debug/../../obj/file.o
- .bss.LfnBuf 0x20000d44 0x200 THUMB Debug/../../obj/ff.o
- .bss.Fsid 0x20000f44 0x2 THUMB Debug/../../obj/ff.o
- *fill* 0x20000f46 0x2 00
- .bss.FatFs 0x20000f48 0x4 THUMB Debug/../../obj/ff.o
- .bss.libdebugio.dbgCommWord
- 0x20000f4c 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x20000f4c dbgCommWord
- .bss.libdebugio.dbgCntrlWord_mempoll
- 0x20000f50 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x20000f50 dbgCntrlWord_mempoll
+ 0x20000bd4 0x184 THUMB Debug/../../obj/file.o
+ .bss.LfnBuf 0x20000d58 0x200 THUMB Debug/../../obj/ff.o
+ .bss.Fsid 0x20000f58 0x2 THUMB Debug/../../obj/ff.o
+ *fill* 0x20000f5a 0x2
+ .bss.FatFs 0x20000f5c 0x4 THUMB Debug/../../obj/ff.o
*(COMMON)
- 0x20000f54 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
- 0x20000f54 __bss_load_end__ = __bss_end__
+ 0x20000f60 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
+ 0x20000f60 __bss_load_end__ = __bss_end__
0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= __SRAM_segment_end__)), error: .bss is too large to fit in SRAM memory segment)
- 0x20000f54 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
+ 0x20000f60 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
-.non_init 0x20000f54 0x0
- 0x20000f54 __non_init_start__ = .
+.non_init 0x20000f60 0x0
+ 0x20000f60 __non_init_start__ = .
*(.non_init .non_init.*)
- 0x20000f54 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
- 0x20000f54 __non_init_load_end__ = __non_init_end__
+ 0x20000f60 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
+ 0x20000f60 __non_init_load_end__ = __non_init_end__
0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= __SRAM_segment_end__)), error: .non_init is too large to fit in SRAM memory segment)
- 0x20000f54 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
+ 0x20000f60 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
-.heap 0x20000f54 0x80
- 0x20000f54 __heap_start__ = .
+.heap 0x20000f60 0x80
+ 0x20000f60 __heap_start__ = .
*(.heap .heap.*)
- 0x20000fd4 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
- *fill* 0x20000f54 0x80 00
- 0x20000fd4 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
- 0x20000fd4 __heap_load_end__ = __heap_end__
+ 0x20000fe0 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
+ *fill* 0x20000f60 0x80
+ 0x20000fe0 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
+ 0x20000fe0 __heap_load_end__ = __heap_end__
0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= __SRAM_segment_end__)), error: .heap is too large to fit in SRAM memory segment)
- 0x20000fd4 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
+ 0x20000fe0 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
-.stack 0x20000fd4 0x200
- 0x20000fd4 __stack_start__ = .
+.stack 0x20000fe0 0x200
+ 0x20000fe0 __stack_start__ = .
*(.stack .stack.*)
- 0x200011d4 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
- *fill* 0x20000fd4 0x200 00
- 0x200011d4 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
- 0x200011d4 __stack_load_end__ = __stack_end__
+ 0x200011e0 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
+ *fill* 0x20000fe0 0x200
+ 0x200011e0 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
+ 0x200011e0 __stack_load_end__ = __stack_end__
0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= __SRAM_segment_end__)), error: .stack is too large to fit in SRAM memory segment)
- 0x200011d4 __stack_process_load_start__ = ALIGN (__stack_end__, 0x4)
+ 0x200011e0 __stack_process_load_start__ = ALIGN (__stack_end__, 0x4)
-.stack_process 0x200011d4 0x0
- 0x200011d4 __stack_process_start__ = .
+.stack_process 0x200011e0 0x0
+ 0x200011e0 __stack_process_start__ = .
*(.stack_process .stack_process.*)
- 0x200011d4 . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4)
- 0x200011d4 __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process))
- 0x200011d4 __stack_process_load_end__ = __stack_process_end__
+ 0x200011e0 . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4)
+ 0x200011e0 __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process))
+ 0x200011e0 __stack_process_load_end__ = __stack_process_end__
0x00000001 . = ASSERT (((__stack_process_end__ >= __SRAM_segment_start__) && (__stack_process_end__ <= __SRAM_segment_end__)), error: .stack_process is too large to fit in SRAM memory segment)
- 0x200011d4 __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4)
+ 0x200011e0 __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4)
-.tbss 0x200011d4 0x0
- 0x200011d4 __tbss_start__ = .
+.tbss 0x200011e0 0x0
+ 0x200011e0 __tbss_start__ = .
*(.tbss .tbss.*)
- 0x200011d4 __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss))
- 0x200011d4 __tbss_load_end__ = __tbss_end__
+ 0x200011e0 __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss))
+ 0x200011e0 __tbss_load_end__ = __tbss_end__
0x00000001 . = ASSERT (((__tbss_end__ >= __SRAM_segment_start__) && (__tbss_end__ <= __SRAM_segment_end__)), error: .tbss is too large to fit in SRAM memory segment)
- 0x08005830 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
+ 0x08005208 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
-.tdata 0x200011d4 0x0 load address 0x08005830
- 0x200011d4 __tdata_start__ = .
+.tdata 0x200011e0 0x0 load address 0x08005208
+ 0x200011e0 __tdata_start__ = .
*(.tdata .tdata.*)
- 0x200011d4 __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata))
- 0x08005830 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata))
- 0x08005830 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata))
+ 0x200011e0 __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata))
+ 0x08005208 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata))
+ 0x08005208 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata))
0x00000001 . = ASSERT (((__tdata_load_end__ >= __FLASH_segment_start__) && (__tdata_load_end__ <= __FLASH_segment_end__)), error: .tdata is too large to fit in FLASH memory segment)
-.tdata_run 0x200011d4 0x0
- 0x200011d4 __tdata_run_start__ = .
- 0x200011d4 . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .)
- 0x200011d4 __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run))
- 0x200011d4 __tdata_run_load_end__ = __tdata_run_end__
- 0x200011d4 __SRAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run))
+.tdata_run 0x200011e0 0x0
+ 0x200011e0 __tdata_run_start__ = .
+ 0x200011e0 . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .)
+ 0x200011e0 __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run))
+ 0x200011e0 __tdata_run_load_end__ = __tdata_run_end__
+ 0x200011e0 __SRAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run))
0x00000001 . = ASSERT (((__tdata_run_end__ >= __SRAM_segment_start__) && (__tdata_run_end__ <= __SRAM_segment_end__)), error: .tdata_run is too large to fit in SRAM memory segment)
START GROUP
LOAD THUMB Debug/../../obj/hooks.o
LOAD THUMB Debug/../../obj/main.o
-LOAD THUMB Debug/../../obj/core_cm3.o
LOAD THUMB Debug/../../obj/system_stm32f10x.o
LOAD THUMB Debug/../../obj/mmc.o
LOAD THUMB Debug/../../obj/stm32f10x_gpio.o
@@ -1780,432 +2859,464 @@ LOAD THUMB Debug/../../obj/xcp.o
LOAD THUMB Debug/../../obj/file.o
LOAD THUMB Debug/../../obj/ff.o
LOAD THUMB Debug/../../obj/unicode.o
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcm_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcpp_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_targetio_impl_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libcm_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libdebugio_mempoll_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libcpp_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libdebugio_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfprintf_v7m_t_le_eabi.o
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfscanf_v7m_t_le_eabi.o
END GROUP
OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/../bin/openblt_olimex_stm32p103.elf elf32-littlearm)
-.debug_frame 0x00000000 0x3ec4
- .debug_frame 0x00000000 0xb8 THUMB Debug/../../obj/hooks.o
- .debug_frame 0x000000b8 0x30 THUMB Debug/../../obj/main.o
- .debug_frame 0x000000e8 0x170 THUMB Debug/../../obj/core_cm3.o
- .debug_frame 0x00000258 0x38 THUMB Debug/../../obj/system_stm32f10x.o
- .debug_frame 0x00000290 0x1bc THUMB Debug/../../obj/mmc.o
- .debug_frame 0x0000044c 0x180 THUMB Debug/../../obj/stm32f10x_gpio.o
- .debug_frame 0x000005cc 0x230 THUMB Debug/../../obj/stm32f10x_rcc.o
- .debug_frame 0x000007fc 0x1bc THUMB Debug/../../obj/stm32f10x_spi.o
- .debug_frame 0x000009b8 0x224 THUMB Debug/../../obj/stm32f10x_usart.o
- .debug_frame 0x00000bdc 0x68 THUMB Debug/../../obj/can.o
- .debug_frame 0x00000c44 0x84 THUMB Debug/../../obj/cpu.o
- .debug_frame 0x00000cc8 0x1a8 THUMB Debug/../../obj/flash.o
- .debug_frame 0x00000e70 0xb8 THUMB Debug/../../obj/nvm.o
- .debug_frame 0x00000f28 0x68 THUMB Debug/../../obj/timer.o
- .debug_frame 0x00000f90 0x90 THUMB Debug/../../obj/uart.o
- .debug_frame 0x00001020 0x30 THUMB Debug/../../obj/cpu_comp.o
- .debug_frame 0x00001050 0x2c THUMB Debug/../../obj/vectors.o
- .debug_frame 0x0000107c 0x2c THUMB Debug/../../obj/assert.o
- .debug_frame 0x000010a8 0x48 THUMB Debug/../../obj/backdoor.o
- .debug_frame 0x000010f0 0x48 THUMB Debug/../../obj/boot.o
- .debug_frame 0x00001138 0xb4 THUMB Debug/../../obj/com.o
- .debug_frame 0x000011ec 0x30 THUMB Debug/../../obj/cop.o
- .debug_frame 0x0000121c 0x80 THUMB Debug/../../obj/xcp.o
- .debug_frame 0x0000129c 0x150 THUMB Debug/../../obj/file.o
- .debug_frame 0x000013ec 0x670 THUMB Debug/../../obj/ff.o
- .debug_frame 0x00001a5c 0x30 THUMB Debug/../../obj/unicode.o
- .debug_frame 0x00001a8c 0x128c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- .debug_frame 0x00002d18 0x120 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2_asm.o)
- .debug_frame 0x00002e38 0x260 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc_asm.o)
- .debug_frame 0x00003098 0x78c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .debug_frame 0x00003824 0xa0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- .debug_frame 0x000038c4 0x600 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v7m_t_le.a(libm_asm.o)
+.debug_frame 0x00000000 0x5920
+ .debug_frame 0x00000000 0xc0 THUMB Debug/../../obj/hooks.o
+ .debug_frame 0x000000c0 0x30 THUMB Debug/../../obj/main.o
+ .debug_frame 0x000000f0 0x214 THUMB Debug/../../obj/mmc.o
+ .debug_frame 0x00000304 0x184 THUMB Debug/../../obj/stm32f10x_gpio.o
+ .debug_frame 0x00000488 0x240 THUMB Debug/../../obj/stm32f10x_rcc.o
+ .debug_frame 0x000006c8 0x1d4 THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_frame 0x0000089c 0x244 THUMB Debug/../../obj/stm32f10x_usart.o
+ .debug_frame 0x00000ae0 0x64 THUMB Debug/../../obj/can.o
+ .debug_frame 0x00000b44 0x74 THUMB Debug/../../obj/cpu.o
+ .debug_frame 0x00000bb8 0x180 THUMB Debug/../../obj/flash.o
+ .debug_frame 0x00000d38 0xd4 THUMB Debug/../../obj/nvm.o
+ .debug_frame 0x00000e0c 0x5c THUMB Debug/../../obj/timer.o
+ .debug_frame 0x00000e68 0x88 THUMB Debug/../../obj/uart.o
+ .debug_frame 0x00000ef0 0x30 THUMB Debug/../../obj/cpu_comp.o
+ .debug_frame 0x00000f20 0x2c THUMB Debug/../../obj/vectors.o
+ .debug_frame 0x00000f4c 0x2c THUMB Debug/../../obj/assert.o
+ .debug_frame 0x00000f78 0x48 THUMB Debug/../../obj/backdoor.o
+ .debug_frame 0x00000fc0 0x48 THUMB Debug/../../obj/boot.o
+ .debug_frame 0x00001008 0xb4 THUMB Debug/../../obj/com.o
+ .debug_frame 0x000010bc 0x30 THUMB Debug/../../obj/cop.o
+ .debug_frame 0x000010ec 0x70 THUMB Debug/../../obj/xcp.o
+ .debug_frame 0x0000115c 0x13c THUMB Debug/../../obj/file.o
+ .debug_frame 0x00001298 0x828 THUMB Debug/../../obj/ff.o
+ .debug_frame 0x00001ac0 0x44 THUMB Debug/../../obj/unicode.o
+ .debug_frame 0x00001b04 0x3d6c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .debug_frame 0x00005870 0xb0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
-.debug_info 0x00000000 0x9caa
- .debug_info 0x00000000 0x65e THUMB Debug/../../obj/hooks.o
- .debug_info 0x0000065e 0x395 THUMB Debug/../../obj/main.o
- .debug_info 0x000009f3 0x53d THUMB Debug/../../obj/core_cm3.o
- .debug_info 0x00000f30 0x4c6 THUMB Debug/../../obj/system_stm32f10x.o
- .debug_info 0x000013f6 0x95e THUMB Debug/../../obj/mmc.o
- .debug_info 0x00001d54 0x716 THUMB Debug/../../obj/stm32f10x_gpio.o
- .debug_info 0x0000246a 0x8ef THUMB Debug/../../obj/stm32f10x_rcc.o
- .debug_info 0x00002d59 0x959 THUMB Debug/../../obj/stm32f10x_spi.o
- .debug_info 0x000036b2 0xa51 THUMB Debug/../../obj/stm32f10x_usart.o
- .debug_info 0x00004103 0x4e8 THUMB Debug/../../obj/can.o
- .debug_info 0x000045eb 0x15a THUMB Debug/../../obj/cpu.o
- .debug_info 0x00004745 0x697 THUMB Debug/../../obj/flash.o
- .debug_info 0x00004ddc 0x182 THUMB Debug/../../obj/nvm.o
- .debug_info 0x00004f5e 0x11e THUMB Debug/../../obj/timer.o
- .debug_info 0x0000507c 0x2b4 THUMB Debug/../../obj/uart.o
- .debug_info 0x00005330 0x65 THUMB Debug/../../obj/usb.o
- .debug_info 0x00005395 0x91 THUMB Debug/../../obj/cpu_comp.o
- .debug_info 0x00005426 0x110 THUMB Debug/../../obj/cstart.o
- .debug_info 0x00005536 0xfc THUMB Debug/../../obj/vectors.o
- .debug_info 0x00005632 0xbd THUMB Debug/../../obj/assert.o
- .debug_info 0x000056ef 0xcb THUMB Debug/../../obj/backdoor.o
- .debug_info 0x000057ba 0x93 THUMB Debug/../../obj/boot.o
- .debug_info 0x0000584d 0x1e1 THUMB Debug/../../obj/com.o
- .debug_info 0x00005a2e 0x91 THUMB Debug/../../obj/cop.o
- .debug_info 0x00005abf 0x61d THUMB Debug/../../obj/xcp.o
- .debug_info 0x000060dc 0x7b6 THUMB Debug/../../obj/file.o
- .debug_info 0x00006892 0x2069 THUMB Debug/../../obj/ff.o
- .debug_info 0x000088fb 0x160 THUMB Debug/../../obj/unicode.o
- .debug_info 0x00008a5b 0xc63 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a(libc2.o)
- .debug_info 0x000096be 0x51f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .debug_info 0x00009bdd 0xcd C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
+.debug_info 0x00000000 0xde0a
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+ .debug_info 0x0000079d 0x3a2 THUMB Debug/../../obj/main.o
+ .debug_info 0x00000b3f 0x1251 THUMB Debug/../../obj/mmc.o
+ .debug_info 0x00001d90 0x859 THUMB Debug/../../obj/stm32f10x_gpio.o
+ .debug_info 0x000025e9 0x8a1 THUMB Debug/../../obj/stm32f10x_rcc.o
+ .debug_info 0x00002e8a 0x993 THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_info 0x0000381d 0xaee THUMB Debug/../../obj/stm32f10x_usart.o
+ .debug_info 0x0000430b 0x519 THUMB Debug/../../obj/can.o
+ .debug_info 0x00004824 0x1e4 THUMB Debug/../../obj/cpu.o
+ .debug_info 0x00004a08 0x8db THUMB Debug/../../obj/flash.o
+ .debug_info 0x000052e3 0x263 THUMB Debug/../../obj/nvm.o
+ .debug_info 0x00005546 0x13c THUMB Debug/../../obj/timer.o
+ .debug_info 0x00005682 0x397 THUMB Debug/../../obj/uart.o
+ .debug_info 0x00005a19 0x95 THUMB Debug/../../obj/cpu_comp.o
+ .debug_info 0x00005aae 0x110 THUMB Debug/../../obj/cstart.o
+ .debug_info 0x00005bbe 0x11f THUMB Debug/../../obj/vectors.o
+ .debug_info 0x00005cdd 0xd7 THUMB Debug/../../obj/assert.o
+ .debug_info 0x00005db4 0x14d THUMB Debug/../../obj/backdoor.o
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+ .debug_info 0x00006398 0x95 THUMB Debug/../../obj/cop.o
+ .debug_info 0x0000642d 0x85d THUMB Debug/../../obj/xcp.o
+ .debug_info 0x00006c8a 0x1284 THUMB Debug/../../obj/file.o
+ .debug_info 0x00007f0e 0x39db THUMB Debug/../../obj/ff.o
+ .debug_info 0x0000b8e9 0x1ad THUMB Debug/../../obj/unicode.o
+ .debug_info 0x0000ba96 0x2374 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
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+ .debug_abbrev 0x0000037c 0x2db THUMB Debug/../../obj/mmc.o
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+ .debug_abbrev 0x000016ad 0x14 THUMB Debug/../../obj/cstart.o
+ .debug_abbrev 0x000016c1 0xee THUMB Debug/../../obj/vectors.o
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+ .debug_abbrev 0x00001a6f 0x45 THUMB Debug/../../obj/cop.o
+ .debug_abbrev 0x00001ab4 0x214 THUMB Debug/../../obj/xcp.o
+ .debug_abbrev 0x00001cc8 0x25b THUMB Debug/../../obj/file.o
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+ .debug_abbrev 0x00002225 0xb2 THUMB Debug/../../obj/unicode.o
+ .debug_abbrev 0x000022d7 0x179 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
-.debug_loc 0x00000000 0x9604
- .debug_loc 0x00000000 0xdd THUMB Debug/../../obj/hooks.o
- .debug_loc 0x000000dd 0x82 THUMB Debug/../../obj/main.o
- .debug_loc 0x0000015f 0x2ae THUMB Debug/../../obj/core_cm3.o
- .debug_loc 0x0000040d 0x165 THUMB Debug/../../obj/system_stm32f10x.o
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diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/bin/openblt_olimex_stm32p103.srec b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/bin/openblt_olimex_stm32p103.srec
index 72580ee6..21f77b2c 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/bin/openblt_olimex_stm32p103.srec
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diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/readme.txt b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/readme.txt
index a49767fb..a10a52ca 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/readme.txt
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/readme.txt
@@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
-Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
+Rowleys CrossWorks (version 3.7.6) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/stm32f103_crossworks.hzp b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/stm32f103_crossworks.hzp
index b8251787..f052b79f 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/stm32f103_crossworks.hzp
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/stm32f103_crossworks.hzp
@@ -1,102 +1,168 @@
-
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+
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diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/stm32f103_crossworks.hzs b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/stm32f103_crossworks.hzs
index 8bf798e7..7af2a67f 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/stm32f103_crossworks.hzs
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/ide/stm32f103_crossworks.hzs
@@ -1,19 +1,28 @@
-
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@@ -21,18 +30,24 @@
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@@ -40,9 +55,9 @@
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@@ -55,7 +70,7 @@
-
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-
+
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.c b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.c
deleted file mode 100644
index 56fddc52..00000000
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.c
+++ /dev/null
@@ -1,784 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.c
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
- mrs r0, psp
- bx lr
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
- msr psp, r0
- bx lr
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
- mrs r0, msp
- bx lr
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
- msr msp, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
- clrex
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t __get_BASEPRI(void)
-{
- mrs r0, basepri
- bx lr
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
- msr basepri, r0
- bx lr
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
- mrs r0, primask
- bx lr
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
- msr primask, r0
- bx lr
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t __get_FAULTMASK(void)
-{
- mrs r0, faultmask
- bx lr
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
- msr faultmask, r0
- bx lr
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
- mrs r0, control
- bx lr
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
- msr control, r0
- bx lr
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- __ASM("mrs r0, psp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM("msr psp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- __ASM("mrs r0, msp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM("msr msp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- __ASM("rev16 r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- __ASM("rbit r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- __ASM("ldrexb r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- __ASM("ldrexh r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- __ASM("ldrex r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- __ASM("strexb r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- __ASM("strexh r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- __ASM("strex r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, psp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, msp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- uint8_t result=0;
-
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- uint16_t result=0;
-
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.h b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.h
index 2b6b51a7..efac390f 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.h
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.h
@@ -1,16 +1,16 @@
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V1.30
- * @date 30. October 2009
+ * @version V3.00
+ * @date 03. February 2012
*
* @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -20,1618 +20,1354 @@
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
-
-#ifndef __CM3_CORE_H__
-#define __CM3_CORE_H__
-
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
- *
- * List of Lint messages which will be suppressed and not shown:
- * - Error 10: \n
- * register uint32_t __regBasePri __asm("basepri"); \n
- * Error 10: Expecting ';'
- * .
- * - Error 530: \n
- * return(__regBasePri); \n
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized
- * .
- * - Error 550: \n
- * __regBasePri = (basePri & 0x1ff); \n
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed
- * .
- * - Error 754: \n
- * uint32_t RESERVED0[24]; \n
- * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced
- * .
- * - Error 750: \n
- * #define __CM3_CORE_H__ \n
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
- * .
- * - Error 528: \n
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
- * .
- * - Error 751: \n
- * } InterruptType_Type; \n
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
- * .
- * Note: To re-enable a Message, insert a space before 'lint' *
- *
- */
-
-/*lint -save */
-/*lint -e10 */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core registers and bitfields
- - Cortex-M core peripheral base address
- @{
- */
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
#ifdef __cplusplus
extern "C" {
-#endif
-
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex core */
-
-#include /* Include standard types */
-
-#if defined (__ICCARM__)
- #include /* IAR Intrinsics */
#endif
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
-#ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
-#endif
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
*/
-#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
-#else
- #define __I volatile const /*!< defines 'read only' permissions */
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ /* add preprocessor checks */
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
/*******************************************************************************
* Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
******************************************************************************/
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
- @{
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
*/
-
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
@{
*/
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
typedef struct
{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
-} NVIC_Type;
-/*@}*/ /* end of group CMSIS_CM3_NVIC */
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
- memory mapped structure for System Control Block (SCB)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
@{
*/
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
typedef struct
{
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
-} SCB_Type;
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-/* SCB Interrupt Control State Register Definitions */
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Registers Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Registers Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-/*@}*/ /* end of group CMSIS_CM3_SCB */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
- memory mapped structure for SysTick
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
typedef struct
{
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
- memory mapped structure for Instrumentation Trace Macrocell (ITM)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
typedef struct
{
- __O union
+ __O union
{
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
-} ITM_Type;
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+} ITM_Type;
/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-/*@}*/ /* end of group CMSIS_CM3_ITM */
+/*@}*/ /* end of group CMSIS_ITM */
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
- memory mapped structure for Interrupt Type
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
typedef struct
{
- uint32_t RESERVED0;
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
-#else
- uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
-/* Interrupt Controller Type Register Definitions */
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-/* Auxiliary Control Register Definitions */
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
- memory mapped structure for Memory Protection Unit (MPU)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
@{
*/
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
typedef struct
{
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-/*@}*/ /* end of group CMSIS_CM3_MPU */
+/*@} end of group CMSIS_MPU */
#endif
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
- memory mapped structure for Core Debug Register
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
@{
*/
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
typedef struct
{
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register */
#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
-/*@}*/ /* end of group CMSIS_CM3_core_register */
+/*@} */
+
/*******************************************************************************
* Hardware Abstraction Layer
- ******************************************************************************/
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq __enable_fiq
-#define __disable_fault_irq __disable_fiq
-
-#define __NOP __nop
-#define __WFI __wfi
-#define __WFE __wfe
-#define __SEV __sev
-#define __ISB() __isb(0)
-#define __DSB() __dsb(0)
-#define __DMB() __dmb(0)
-#define __REV __rev
-#define __RBIT __rbit
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
-#define __STREXB(value, ptr) __strex(value, ptr)
-#define __STREXH(value, ptr) __strex(value, ptr)
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-extern void __CLREX(void);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else /* (__ARMCC_VERSION >= 400000) */
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#define __CLREX __clrex
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-static __INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & 1);
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
-
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
-static __INLINE void __WFI() { __ASM ("wfi"); }
-static __INLINE void __WFE() { __ASM ("wfe"); }
-static __INLINE void __SEV() { __ASM ("sev"); }
-static __INLINE void __CLREX() { __ASM ("clrex"); }
-
-/* intrinsic void __ISB(void) */
-/* intrinsic void __DSB(void) */
-/* intrinsic void __DMB(void) */
-/* intrinsic void __set_PRIMASK(); */
-/* intrinsic void __get_PRIMASK(); */
-/* intrinsic void __set_FAULTMASK(); */
-/* intrinsic void __get_FAULTMASK(); */
-/* intrinsic uint32_t __REV(uint32_t value); */
-/* intrinsic uint32_t __REVSH(uint32_t value); */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
-/* intrinsic unsigned long __LDREX(unsigned long *); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __NOP() { __ASM volatile ("nop"); }
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }
-static __INLINE void __SEV() { __ASM volatile ("sev"); }
-static __INLINE void __ISB() { __ASM volatile ("isb"); }
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
- Core Function Interface containing:
+ Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- - Core Reset Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
-/*@{*/
+
+
/* ########################## NVIC functions #################################### */
-
-/**
- * @brief Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param PriorityGroup is priority grouping field
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
*/
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
-
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
-/**
- * @brief Get the Priority Grouping from NVIC Interrupt Controller
- *
- * @return priority grouping field
- *
- * Get the priority grouping from NVIC Interrupt Controller.
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
}
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- *
- * @param IRQn The positive number of the external interrupt to enable
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
}
-/**
- * @brief Disable the interrupt line for external interrupt specified
- *
- * @param IRQn The positive number of the external interrupt to disable
- *
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
}
-/**
- * @brief Read the interrupt pending bit for a device specific interrupt source
- *
- * @param IRQn The number of the device specifc interrupt
- * @return 1 = interrupt pending, 0 = interrupt not pending
- *
- * Read the pending register in NVIC and return 1 if its status is pending,
- * otherwise it returns 0
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
*/
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
}
-/**
- * @brief Set the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for set pending
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
}
-/**
- * @brief Clear the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for clear pending
- *
- * Clear the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
-/**
- * @brief Read the active bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for read active bit
- * @return 1 = interrupt active, 0 = interrupt not active
- *
- * Read the active register in NVIC and returns 1 if its status is active,
- * otherwise it returns 0.
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
*/
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
}
-/**
- * @brief Set the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for set priority
- * @param priority The priority to set
- *
- * Set the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * Note: The priority cannot be set for every core interrupt.
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
*/
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
else {
NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
}
-/**
- * @brief Read the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for get priority
- * @return The priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
*/
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
else {
return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
-/**
- * @brief Encode the priority for an interrupt
- *
- * @param PriorityGroup The used priority group
- * @param PreemptPriority The preemptive priority value (starting from 0)
- * @param SubPriority The sub priority value (starting from 0)
- * @return The encoded priority for the interrupt
- *
- * Encode the priority for an interrupt with the given priority group,
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The returned priority value can be used for NVIC_SetPriority(...) function
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
@@ -1639,7 +1375,7 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
+
return (
((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
((SubPriority & ((1 << (SubPriorityBits )) - 1)))
@@ -1647,22 +1383,19 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
}
-/**
- * @brief Decode the priority of an interrupt
- *
- * @param Priority The priority for the interrupt
- * @param PriorityGroup The used priority group
- * @param pPreemptPriority The preemptive priority value (starting from 0)
- * @param pSubPriority The sub priority value (starting from 0)
- *
- * Decode an interrupt priority value with the given priority group to
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The priority value can be retrieved with NVIC_GetPriority(...) function
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
*/
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
@@ -1670,132 +1403,134 @@ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
+
*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
}
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
/* ################################## SysTick function ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/**
- * @brief Initialize and start the SysTick counter and its interrupt.
- *
- * @param ticks number of ticks between two interrupts
- * @return 1 = failed, 0 = successful
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate
- * periodical interrupts.
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
*/
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
+
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
-
-
-
-/* ################################## Reset function ############################################ */
-
-/**
- * @brief Initiate a system reset request.
- *
- * Initiate a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
+/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
-
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
- Core Debug Interface containing:
- - Core Debug Receive / Transmit Functions
- - Core Debug Defines
- - Core Debug Variables
-*/
-/*@{*/
-
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/**
- * @brief Outputs a character via the ITM channel 0
- *
- * @param ch character to output
- * @return character to output
- *
- * The function outputs a character via the ITM channel 0.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
*/
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0].u32 == 0);
ITM->PORT[0].u8 = (uint8_t) ch;
- }
+ }
return (ch);
}
-/**
- * @brief Inputs a character via variable ITM_RxBuffer
- *
- * @return received character, -1 = no character received
- *
- * The function inputs a character via variable ITM_RxBuffer.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
*/
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
-
- return (ch);
+
+ return (ch);
}
-/**
- * @brief Check if a character via variable ITM_RxBuffer is available
- *
- * @return 1 = character available, 0 = no character available
- *
- * The function checks variable ITM_RxBuffer whether a character is available or not.
- * The function returns '1' if a character is available and '0' if no character is available.
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
*/
-static __INLINE int ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
@@ -1804,15 +1539,12 @@ static __INLINE int ITM_CheckChar (void) {
}
}
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
+/*@} end of CMSIS_core_DebugFunctions */
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */
-
-#endif /* __CM3_CORE_H__ */
-
-/*lint -restore */
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cmFunc.h b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cmFunc.h
new file mode 100644
index 00000000..adb07b5d
--- /dev/null
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cmFunc.h
@@ -0,0 +1,616 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cmInstr.h b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cmInstr.h
new file mode 100644
index 00000000..624c175f
--- /dev/null
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CM3/CoreSupport/core_cmInstr.h
@@ -0,0 +1,618 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+
+ __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
+ return(op1);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint8_t result;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint16_t result;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint8_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CMSIS debug support.htm b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CMSIS debug support.htm
deleted file mode 100644
index efda685b..00000000
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CMSIS debug support.htm
+++ /dev/null
@@ -1,243 +0,0 @@
-
-
-
-CMSIS Debug Support
-
-
-
-
-
-
-
-
-
CMSIS Debug Support
-
-
-
-
Cortex-M3 ITM Debug Access
-
- The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
- the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
- 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
- communication channels are used by CMSIS to output the following information:
-
-
-
ITM Channel 0: used for printf-style output via the debug interface.
-
ITM Channel 31: is reserved for RTOS kernel awareness debugging.
-
-
-
Debug IN / OUT functions
-
CMSIS provides following debug functions:
-
-
ITM_SendChar (uses ITM channel 0)
-
ITM_ReceiveChar (uses global variable)
-
ITM_CheckChar (uses global variable)
-
-
-
ITM_SendChar
-
- ITM_SendChar is used to transmit a character over ITM channel 0 from
- the microcontroller system to the debug system.
- Only a 8 bit value is transmitted.
-
- ITM communication channel is only capable for OUT direction. For IN direction
- a globel variable is used. A simple mechansim detects if a character is received.
- The project to test need to be build with debug information.
-
-
-
- The globale variable ITM_RxBuffer is used to transmit a 8 bit value from debug system
- to microcontroller system. ITM_RxBuffer is 32 bit wide to enshure a proper handshake.
-
-
-extern volatile int ITM_RxBuffer; /* variable to receive characters */
-
-
- A dedicated bit pattern is used to determin if ITM_RxBuffer is empty
- or contains a valid value.
-
-
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
-
-
- ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking.
- It returns the received character or '-1' if no character was available.
-
-
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-
ITM_CheckChar
-
- ITM_CheckChar is used to check if a character is received.
-
-
-static __INLINE int ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-
-
ITM Debug Support in uVision
-
- uVision uses in a debug session the Debug (printf) Viewer window to
- display the debug data.
-
-
Direction microcontroller system -> uVision:
-
-
- Characters received via ITM communication channel 0 are written in a printf style
- to Debug (printf) Viewer window.
-
-
-
-
Direction uVision -> microcontroller system:
-
-
Check if ITM_RxBuffer variable is available (only performed once).
-
Read character from Debug (printf) Viewer window.
-
If ITM_RxBuffer empty write character to ITM_RxBuffer.
-
-
-
Note
-
-
Current solution does not use a buffer machanism for trasmitting the characters.
-
-
-
-
RTX Kernel awareness in uVision
-
- uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
- No format overhead is necessary.
- uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
- to ITM communication channel 31.
-
-
-
Following RTX events are traced:
-
-
Task Create / Delete event
-
-
32 bit access. Task start address is transmitted
-
16 bit access. Task ID and Create/Delete flag are transmitted
- High byte holds Create/Delete flag, Low byte holds TASK ID.
-
-
-
-
Task switch event
-
-
8 bit access. Task ID of current task is transmitted
-
-
-
-
-
Note
-
-
Other RTOS information could be retrieved via memory read access in a polling mode manner.
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CMSIS_changes.htm b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CMSIS_changes.htm
deleted file mode 100644
index 162ffcc9..00000000
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/CMSIS_changes.htm
+++ /dev/null
@@ -1,320 +0,0 @@
-
-
-
-CMSIS Changes
-
-
-
-
-
-
-
-
-
Changes to CMSIS version V1.20
-
-
-
-
1. Removed CMSIS Middelware packages
-
- CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
-
-
-
2. SystemFrequency renamed to SystemCoreClock
-
- The variable name SystemCoreClock is more precise than SystemFrequency
- because the variable holds the clock value at which the core is running.
-
-
-
3. Changed startup concept
-
- The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
- from main) has the weakness that it does not work for controllers which need a already
- configuerd clock system to configure the external memory controller.
-
-
-
Changed startup concept
-
-
- SystemInit() is called from startup file before premain.
-
-
- SystemInit() configures the clock system and also configures
- an existing external memory controller.
-
-
- SystemInit() must not use global variables.
-
-
- SystemCoreClock is initialized with a correct predefined value.
-
-
- Additional function void SystemCoreClockUpdate (void) is provided.
- SystemCoreClockUpdate() updates the variable SystemCoreClock
- and must be called whenever the core clock is changed.
- SystemCoreClockUpdate() evaluates the clock register settings and calculates
- the current core clock.
-
-
-
-
-
4. Advanced Debug Functions
-
- ITM communication channel is only capable for OUT direction. To allow also communication for
- IN direction a simple concept is provided.
-
-
-
- Global variable volatile int ITM_RxBuffer used for IN data.
-
-
- Function int ITM_CheckChar (void) checks if a new character is available.
-
-
- Function int ITM_ReceiveChar (void) retrieves the new character.
-
-
-
-
- For detailed explanation see file CMSIS debug support.htm.
-
-
-
-
5. Core Register Bit Definitions
-
- Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
- defines correspond with the Cortex-M Technical Reference Manual.
-
- DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
- using DoxyGen.
-
-
-
8. Folder Structure
-
- The folder structure is changed to differentiate the single support packages.
-
-
-
-
CM0
-
CM3
-
-
CoreSupport
-
DeviceSupport
-
-
Vendor
-
-
Device
-
-
Startup
-
-
Toolchain
-
Toolchain
-
...
-
-
-
-
-
Device
-
...
-
-
-
Vendor
-
...
-
-
-
Example
-
-
Toolchain
-
-
Device
-
Device
-
...
-
-
-
Toolchain
-
...
-
-
-
-
-
-
Documentation
-
-
-
9. Open Points
-
- Following points need to be clarified and solved:
-
-
-
-
- Equivalent C and Assembler startup files.
-
-
- Is there a need for having C startup files although assembler startup files are
- very efficient and do not need to be changed?
-
-
-
-
- Placing of HEAP in external RAM.
-
-
- It must be possible to place HEAP in external RAM if the device supports an
- external memory controller.
-
-
-
-
- Placing of STACK /HEAP.
-
-
- STACK should always be placed at the end of internal RAM.
-
-
- If HEAP is placed in internal RAM than it should be placed after RW ZI section.
-
-
-
-
- Removing core_cm3.c and core_cm0.c.
-
-
- On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
- appropriate compiler intrinsics.
-
-
-
-
-
-
10. Limitations
-
- The following limitations are not covered with the current CMSIS version:
-
-
-
- No C startup files for ARM toolchain are provided.
-
-
- No C startup files for GNU toolchain are provided.
-
-
- No C startup files for IAR toolchain are provided.
-
-
- No Tasking projects are provided yet.
-
-
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/License.doc b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/License.doc
deleted file mode 100644
index b6b8acec..00000000
Binary files a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Boot/lib/CMSIS/License.doc and /dev/null differ
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/bin/demoprog_olimex_stm32p103.elf b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/bin/demoprog_olimex_stm32p103.elf
index 70775ba1..f99ad955 100644
Binary files a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/bin/demoprog_olimex_stm32p103.elf and b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/bin/demoprog_olimex_stm32p103.elf differ
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/bin/demoprog_olimex_stm32p103.map b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/bin/demoprog_olimex_stm32p103.map
index e4d866d9..48dbed2e 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/bin/demoprog_olimex_stm32p103.map
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/bin/demoprog_olimex_stm32p103.map
@@ -1,9 +1,17 @@
-Archive member included because of file (symbol)
+Archive member included to satisfy reference by file (symbol)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- (__do_debug_operation_mempoll)
-C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o) (__debug_io_lock)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfscanf_v7m_t_le_eabi.o (__aeabi_i2d)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfprintf_v7m_t_le_eabi.o (frexp)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a(libm2.o) (fabs)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfprintf_v7m_t_le_eabi.o (__aeabi_uldivmod)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfscanf_v7m_t_le_eabi.o (__getc)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o) (memcpy)
Discarded input sections
@@ -35,94 +43,124 @@ Discarded input sections
.data 0x00000000 0x0 THUMB Debug/../../obj/misc.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/misc.o
.text.NVIC_PriorityGroupConfig
- 0x00000000 0x28 THUMB Debug/../../obj/misc.o
+ 0x00000000 0x24 THUMB Debug/../../obj/misc.o
.text.NVIC_Init
- 0x00000000 0xe8 THUMB Debug/../../obj/misc.o
+ 0x00000000 0xc4 THUMB Debug/../../obj/misc.o
.text.NVIC_SetVectorTable
0x00000000 0x2c THUMB Debug/../../obj/misc.o
.text.NVIC_SystemLPConfig
- 0x00000000 0x54 THUMB Debug/../../obj/misc.o
+ 0x00000000 0x40 THUMB Debug/../../obj/misc.o
.text.SysTick_CLKSourceConfig
- 0x00000000 0x4c THUMB Debug/../../obj/misc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/misc.o
+ .debug_frame 0x00000000 0x150 THUMB Debug/../../obj/misc.o
+ .debug_info 0x00000000 0x527 THUMB Debug/../../obj/misc.o
+ .debug_abbrev 0x00000000 0x14a THUMB Debug/../../obj/misc.o
+ .debug_pubnames
+ 0x00000000 0xa0 THUMB Debug/../../obj/misc.o
+ .debug_pubtypes
+ 0x00000000 0x126 THUMB Debug/../../obj/misc.o
+ .debug_aranges
+ 0x00000000 0x40 THUMB Debug/../../obj/misc.o
+ .debug_ranges 0x00000000 0x30 THUMB Debug/../../obj/misc.o
+ .debug_line 0x00000000 0x333 THUMB Debug/../../obj/misc.o
+ .debug_str 0x00000000 0x490 THUMB Debug/../../obj/misc.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/misc.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/misc.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_adc.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_adc.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_DeInit
- 0x00000000 0xac THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x78 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_Init
- 0x00000000 0xb0 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0xa4 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_StructInit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_adc.o
- .text.ADC_Cmd 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
+ .text.ADC_Cmd 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_DMACmd
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_ITConfig
- 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_ResetCalibration
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_GetResetCalibrationStatus
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_StartCalibration
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_GetCalibrationStatus
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_SoftwareStartConvCmd
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_GetSoftwareStartConvStatus
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_DiscModeChannelCountConfig
- 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_DiscModeCmd
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_RegularChannelConfig
- 0x00000000 0x1bc THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x194 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_ExternalTrigConvCmd
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_GetConversionValue
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_adc.o
- .text.ADC_GetDualModeConversionValue
0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_adc.o
+ .text.ADC_GetDualModeConversionValue
+ 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_AutoInjectedConvCmd
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_InjectedDiscModeCmd
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_ExternalTrigInjectedConvConfig
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_ExternalTrigInjectedConvCmd
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
- .text.ADC_SoftwareStartInjectedConvCmd
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
- .text.ADC_GetSoftwareStartInjectedConvCmdStatus
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
+ .text.ADC_SoftwareStartInjectedConvCmd
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
+ .text.ADC_GetSoftwareStartInjectedConvCmdStatus
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_InjectedChannelConfig
- 0x00000000 0x144 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x120 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_InjectedSequencerLengthConfig
- 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_SetInjectedOffset
0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_GetInjectedConversionValue
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_AnalogWatchdogCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_AnalogWatchdogThresholdsConfig
0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_AnalogWatchdogSingleChannelConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_TempSensorVrefintCmd
- 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_GetFlagStatus
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_ClearFlag
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_GetITStatus
- 0x00000000 0x64 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_adc.o
.text.ADC_ClearITPendingBit
- 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_adc.o
+ .debug_frame 0x00000000 0x8f8 THUMB Debug/../../obj/stm32f10x_adc.o
+ .debug_info 0x00000000 0xb42 THUMB Debug/../../obj/stm32f10x_adc.o
+ .debug_abbrev 0x00000000 0x19d THUMB Debug/../../obj/stm32f10x_adc.o
+ .debug_pubnames
+ 0x00000000 0x42a THUMB Debug/../../obj/stm32f10x_adc.o
+ .debug_pubtypes
+ 0x00000000 0x132 THUMB Debug/../../obj/stm32f10x_adc.o
+ .debug_aranges
+ 0x00000000 0x138 THUMB Debug/../../obj/stm32f10x_adc.o
+ .debug_ranges 0x00000000 0x128 THUMB Debug/../../obj/stm32f10x_adc.o
+ .debug_line 0x00000000 0x62a THUMB Debug/../../obj/stm32f10x_adc.o
+ .debug_str 0x00000000 0x7c2 THUMB Debug/../../obj/stm32f10x_adc.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_adc.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/stm32f10x_adc.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_bkp.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_bkp.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_bkp.o
.text.BKP_DeInit
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_bkp.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_bkp.o
.text.BKP_TamperPinLevelConfig
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_bkp.o
.text.BKP_TamperPinCmd
@@ -130,70 +168,85 @@ Discarded input sections
.text.BKP_ITConfig
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_bkp.o
.text.BKP_RTCOutputConfig
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_bkp.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_bkp.o
.text.BKP_SetRTCCalibrationValue
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_bkp.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_bkp.o
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.text.FLASH_Lock
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- .text.FLASH_ErasePage
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- .text.FLASH_EraseAllPages
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- .text.FLASH_EraseAllBank1Pages
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- .text.FLASH_EraseOptionBytes
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- .text.FLASH_ProgramHalfWord
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- .text.FLASH_ProgramOptionByteData
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- .text.FLASH_EnableWriteProtection
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- .text.FLASH_ReadOutProtection
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- .text.FLASH_UserOptionByteConfig
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- .text.FLASH_GetUserOptionByte
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- .text.FLASH_GetWriteProtectionOptionByte
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- .text.FLASH_GetReadOutProtectionStatus
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- .text.FLASH_GetPrefetchBufferStatus
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- .text.FLASH_ITConfig
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_flash.o
- .text.FLASH_GetFlagStatus
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+ .text.FLASH_ErasePage
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+ .text.FLASH_EraseAllPages
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+ .text.FLASH_EraseAllBank1Pages
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+ .text.FLASH_EraseOptionBytes
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+ .text.FLASH_ProgramWord
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+ .text.FLASH_ProgramHalfWord
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+ .text.FLASH_ProgramOptionByteData
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+ .text.FLASH_EnableWriteProtection
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+ .text.FLASH_ReadOutProtection
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+ .text.FLASH_UserOptionByteConfig
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+ .text.FLASH_GetUserOptionByte
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+ .text.FLASH_GetWriteProtectionOptionByte
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+ .text.FLASH_GetReadOutProtectionStatus
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+ .text.FLASH_GetPrefetchBufferStatus
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+ .text.FLASH_ITConfig
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_flash.o
+ .text.FLASH_GetFlagStatus
+ 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_flash.o
.text.FLASH_ClearFlag
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_flash.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_flash.o
.text.FLASH_GetStatus
- 0x00000000 0x70 THUMB Debug/../../obj/stm32f10x_flash.o
+ 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_flash.o
.text.FLASH_GetBank1Status
- 0x00000000 0x70 THUMB Debug/../../obj/stm32f10x_flash.o
+ 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_flash.o
.text.FLASH_WaitForLastOperation
- 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_flash.o
+ 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_flash.o
.text.FLASH_WaitForLastBank1Operation
- 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_flash.o
+ 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_flash.o
+ .debug_frame 0x00000000 0x650 THUMB Debug/../../obj/stm32f10x_flash.o
+ .debug_info 0x00000000 0x783 THUMB Debug/../../obj/stm32f10x_flash.o
+ .debug_abbrev 0x00000000 0x192 THUMB Debug/../../obj/stm32f10x_flash.o
+ .debug_pubnames
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+ .debug_pubtypes
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+ .debug_aranges
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+ .debug_ranges 0x00000000 0xe8 THUMB Debug/../../obj/stm32f10x_flash.o
+ .debug_line 0x00000000 0x5bc THUMB Debug/../../obj/stm32f10x_flash.o
+ .debug_str 0x00000000 0x6af THUMB Debug/../../obj/stm32f10x_flash.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_flash.o
+ .ARM.attributes
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.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_fsmc.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_fsmc.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_NORSRAMDeInit
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_NANDDeInit
- 0x00000000 0x8c THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_PCCARDDeInit
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_fsmc.o
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.text.FSMC_NORSRAMInit
- 0x00000000 0x150 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0x134 THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_NANDInit
- 0x00000000 0x100 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0xcc THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_PCCARDInit
- 0x00000000 0xd4 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0xac THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_NORSRAMStructInit
- 0x00000000 0x108 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0xd4 THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_NANDStructInit
- 0x00000000 0x9c THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0x7c THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_PCCARDStructInit
- 0x00000000 0xa4 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0x84 THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_NORSRAMCmd
0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_NANDCmd
- 0x00000000 0x98 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0x6c THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_PCCARDCmd
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_fsmc.o
- .text.FSMC_NANDECCCmd
- 0x00000000 0x98 THUMB Debug/../../obj/stm32f10x_fsmc.o
- .text.FSMC_GetECC
0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_fsmc.o
+ .text.FSMC_NANDECCCmd
+ 0x00000000 0x6c THUMB Debug/../../obj/stm32f10x_fsmc.o
+ .text.FSMC_GetECC
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_ITConfig
- 0x00000000 0xe0 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0xa0 THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_GetFlagStatus
- 0x00000000 0x74 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0x64 THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_ClearFlag
- 0x00000000 0x7c THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_GetITStatus
- 0x00000000 0x94 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0x80 THUMB Debug/../../obj/stm32f10x_fsmc.o
.text.FSMC_ClearITPendingBit
- 0x00000000 0x88 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ 0x00000000 0x64 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ .debug_frame 0x00000000 0x4c0 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ .debug_info 0x00000000 0x8cd THUMB Debug/../../obj/stm32f10x_fsmc.o
+ .debug_abbrev 0x00000000 0x175 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ .debug_pubnames
+ 0x00000000 0x1cc THUMB Debug/../../obj/stm32f10x_fsmc.o
+ .debug_pubtypes
+ 0x00000000 0x20e THUMB Debug/../../obj/stm32f10x_fsmc.o
+ .debug_aranges
+ 0x00000000 0xb0 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ .debug_ranges 0x00000000 0xa0 THUMB Debug/../../obj/stm32f10x_fsmc.o
+ .debug_line 0x00000000 0x57d THUMB Debug/../../obj/stm32f10x_fsmc.o
+ .debug_str 0x00000000 0x84b THUMB Debug/../../obj/stm32f10x_fsmc.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_fsmc.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/stm32f10x_fsmc.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_gpio.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_gpio.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_DeInit
- 0x00000000 0x17c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0xe8 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_AFIODeInit
- 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_StructInit
- 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_ReadInputDataBit
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_ReadInputData
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_ReadOutputDataBit
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_ReadOutputData
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_WriteBit
- 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_Write
0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_PinLockConfig
0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_EventOutputConfig
- 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_EventOutputCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_EXTILineConfig
- 0x00000000 0xb0 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x84 THUMB Debug/../../obj/stm32f10x_gpio.o
.text.GPIO_ETH_MediaInterfaceConfig
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_i2c.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_i2c.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_DeInit
- 0x00000000 0x68 THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_Init
- 0x00000000 0x1b4 THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x188 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_StructInit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_i2c.o
- .text.I2C_Cmd 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ .text.I2C_Cmd 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_DMACmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_DMALastTransferCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_GenerateSTART
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_GenerateSTOP
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_AcknowledgeConfig
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_OwnAddress2Config
0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_DualAddressCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_GeneralCallCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_ITConfig
0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_SendData
@@ -475,7 +648,7 @@ Discarded input sections
.text.I2C_Send7bitAddress
0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_ReadRegister
- 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_SoftwareResetCmd
0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_NACKPositionConfig
@@ -483,31 +656,46 @@ Discarded input sections
.text.I2C_SMBusAlertConfig
0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_TransmitPEC
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_PECPositionConfig
0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_CalculatePEC
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_GetPEC
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_ARPCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_StretchClockCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_FastModeDutyCycleConfig
0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_CheckEvent
- 0x00000000 0x70 THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x60 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_GetLastEvent
- 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_GetFlagStatus
- 0x00000000 0x78 THUMB Debug/../../obj/stm32f10x_i2c.o
- .text.I2C_ClearFlag
- 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_i2c.o
- .text.I2C_GetITStatus
0x00000000 0x64 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .text.I2C_ClearFlag
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_i2c.o
+ .text.I2C_GetITStatus
+ 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_i2c.o
.text.I2C_ClearITPendingBit
- 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_i2c.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_frame 0x00000000 0x840 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_info 0x00000000 0xad2 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_abbrev 0x00000000 0x169 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_pubnames
+ 0x00000000 0x30a THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_pubtypes
+ 0x00000000 0x158 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_aranges
+ 0x00000000 0x120 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_ranges 0x00000000 0x110 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_line 0x00000000 0x5d5 THUMB Debug/../../obj/stm32f10x_i2c.o
+ .debug_str 0x00000000 0x72d THUMB Debug/../../obj/stm32f10x_i2c.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_i2c.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/stm32f10x_i2c.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_iwdg.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_iwdg.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_iwdg.o
@@ -522,75 +710,103 @@ Discarded input sections
.text.IWDG_Enable
0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_iwdg.o
.text.IWDG_GetFlagStatus
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_frame 0x00000000 0x170 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_info 0x00000000 0x1d4 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_abbrev 0x00000000 0x106 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_pubnames
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+ .debug_pubtypes
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+ .debug_aranges
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+ .debug_ranges 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_line 0x00000000 0x2ad THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .debug_str 0x00000000 0x323 THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_iwdg.o
+ .ARM.attributes
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.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_pwr.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_pwr.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_pwr.o
- .text.__WFI 0x00000000 0xc THUMB Debug/../../obj/stm32f10x_pwr.o
- .text.__WFE 0x00000000 0xc THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_DeInit
- 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_pwr.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_BackupAccessCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_PVDCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_PVDLevelConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_pwr.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_WakeUpPinCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_EnterSTOPMode
- 0x00000000 0x90 THUMB Debug/../../obj/stm32f10x_pwr.o
+ 0x00000000 0x64 THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_EnterSTANDBYMode
- 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_pwr.o
- .text.PWR_GetFlagStatus
0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_pwr.o
+ .text.PWR_GetFlagStatus
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_pwr.o
.text.PWR_ClearFlag
- 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_pwr.o
+ 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_pwr.o
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+ .debug_info 0x00000000 0x465 THUMB Debug/../../obj/stm32f10x_pwr.o
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+ .debug_pubtypes
+ 0x00000000 0x11e THUMB Debug/../../obj/stm32f10x_pwr.o
+ .debug_aranges
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+ .debug_line 0x00000000 0x319 THUMB Debug/../../obj/stm32f10x_pwr.o
+ .debug_str 0x00000000 0x3e9 THUMB Debug/../../obj/stm32f10x_pwr.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_pwr.o
+ .ARM.attributes
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.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rcc.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_DeInit
- 0x00000000 0x9c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_HSEConfig
- 0x00000000 0x88 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_WaitForHSEStartUp
- 0x00000000 0x70 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_AdjustHSICalibrationValue
- 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_HSICmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_PLLConfig
- 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_PLLCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_SYSCLKConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_GetSYSCLKSource
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_HCLKConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_PCLK1Config
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_PCLK2Config
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ITConfig
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_USBCLKConfig
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ADCCLKConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_LSEConfig
- 0x00000000 0x60 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_LSICmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_RTCCLKConfig
- 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_RTCCLKCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_AHBPeriphClockCmd
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_APB2PeriphResetCmd
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_BackupResetCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ClockSecuritySystemCmd
@@ -598,89 +814,104 @@ Discarded input sections
.text.RCC_MCOConfig
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_GetFlagStatus
- 0x00000000 0x90 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x70 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ClearFlag
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_GetITStatus
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_rcc.o
.text.RCC_ClearITPendingBit
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rcc.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rtc.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rtc.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_ITConfig
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_EnterConfigMode
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_ExitConfigMode
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_GetCounter
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_SetCounter
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_SetPrescaler
- 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_SetAlarm
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_GetDivider
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_WaitForLastTask
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_WaitForSynchro
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_GetFlagStatus
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_ClearFlag
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_GetITStatus
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_rtc.o
.text.RTC_ClearITPendingBit
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_rtc.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_frame 0x00000000 0x338 THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_info 0x00000000 0x402 THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_abbrev 0x00000000 0x192 THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_pubnames
+ 0x00000000 0x15f THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_pubtypes
+ 0x00000000 0x11e THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_aranges
+ 0x00000000 0x88 THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_ranges 0x00000000 0x78 THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_line 0x00000000 0x368 THUMB Debug/../../obj/stm32f10x_rtc.o
+ .debug_str 0x00000000 0x469 THUMB Debug/../../obj/stm32f10x_rtc.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_rtc.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/stm32f10x_rtc.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_sdio.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_sdio.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_DeInit
- 0x00000000 0x8c THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_Init
- 0x00000000 0x68 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_StructInit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_ClockCmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_SetPowerState
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetPowerState
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_ITConfig
- 0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_DMACmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_SendCommand
- 0x00000000 0x68 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_CmdStructInit
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetCommandResponse
0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetResponse
- 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_DataConfig
- 0x00000000 0x70 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_DataStructInit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetDataCounter
- 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_ReadData
0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_WriteData
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetFIFOCount
- 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x14 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_StartSDIOReadWait
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_StopSDIOReadWait
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_SetSDIOReadWaitMode
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_SetSDIOOperation
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_SendSDIOSuspendCmd
@@ -692,90 +923,120 @@ Discarded input sections
.text.SDIO_SendCEATACmd
0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetFlagStatus
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_ClearFlag
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_GetITStatus
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_sdio.o
.text.SDIO_ClearITPendingBit
- 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_sdio.o
+ 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_frame 0x00000000 0x730 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_info 0x00000000 0x7c4 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_abbrev 0x00000000 0x1b4 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_pubnames
+ 0x00000000 0x2d5 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_pubtypes
+ 0x00000000 0x158 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_aranges
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+ .debug_ranges 0x00000000 0xf8 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_line 0x00000000 0x536 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .debug_str 0x00000000 0x702 THUMB Debug/../../obj/stm32f10x_sdio.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_sdio.o
+ .ARM.attributes
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.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_spi.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_spi.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_DeInit
- 0x00000000 0xac THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x7c THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_Init
0x00000000 0x88 THUMB Debug/../../obj/stm32f10x_spi.o
.text.I2S_Init
- 0x00000000 0x1a0 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x16c THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_StructInit
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_spi.o
.text.I2S_StructInit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_spi.o
- .text.SPI_Cmd 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_spi.o
- .text.I2S_Cmd 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_spi.o
+ .text.SPI_Cmd 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_spi.o
+ .text.I2S_Cmd 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_ITConfig
- 0x00000000 0x68 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x60 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_DMACmd
0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_SendData
0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_ReceiveData
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_NSSInternalSoftwareConfig
0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_SSOutputCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_DataSizeConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_TransmitCRC
0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_CalculateCRC
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_GetCRC
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_GetCRCPolynomial
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_spi.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_BiDirectionalLineConfig
0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_spi.o
.text.SPI_I2S_GetFlagStatus
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_spi.o
- .text.SPI_I2S_ClearFlag
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_spi.o
- .text.SPI_I2S_GetITStatus
- 0x00000000 0x88 THUMB Debug/../../obj/stm32f10x_spi.o
- .text.SPI_I2S_ClearITPendingBit
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_spi.o
+ .text.SPI_I2S_ClearFlag
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_spi.o
+ .text.SPI_I2S_GetITStatus
+ 0x00000000 0x74 THUMB Debug/../../obj/stm32f10x_spi.o
+ .text.SPI_I2S_ClearITPendingBit
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_frame 0x00000000 0x5c0 THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_info 0x00000000 0x8c1 THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_abbrev 0x00000000 0x183 THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_pubnames
+ 0x00000000 0x21f THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_pubtypes
+ 0x00000000 0x15c THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_aranges
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+ .debug_ranges 0x00000000 0xc0 THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_line 0x00000000 0x51d THUMB Debug/../../obj/stm32f10x_spi.o
+ .debug_str 0x00000000 0x6c4 THUMB Debug/../../obj/stm32f10x_spi.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_spi.o
+ .ARM.attributes
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.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_tim.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_DeInit
- 0x00000000 0x37c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x234 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_TimeBaseInit
- 0x00000000 0x11c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0xf8 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC1Init
- 0x00000000 0x128 THUMB Debug/../../obj/stm32f10x_tim.o
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.text.TIM_OC2Init
- 0x00000000 0x128 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x110 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC3Init
- 0x00000000 0x120 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x10c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC4Init
- 0x00000000 0xe0 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0xd0 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ICInit
- 0x00000000 0xe8 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0xc8 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_PWMIConfig
- 0x00000000 0xfc THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0xc8 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_BDTRConfig
0x00000000 0x50 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_TimeBaseStructInit
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OCStructInit
- 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ICStructInit
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x30 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_BDTRStructInit
- 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_Cmd 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_Cmd 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_CtrlPWMOutputs
0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ITConfig
@@ -791,13 +1052,13 @@ Discarded input sections
.text.TIM_ITRxExternalClockConfig
0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_TIxExternalClockConfig
- 0x00000000 0x6c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x68 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ETRClockMode1Config
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x64 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ETRClockMode2Config
- 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ETRConfig
- 0x00000000 0x4c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_PrescalerConfig
0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_CounterModeConfig
@@ -805,73 +1066,73 @@ Discarded input sections
.text.TIM_SelectInputTrigger
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_EncoderInterfaceConfig
- 0x00000000 0x94 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x98 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ForcedOC1Config
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ForcedOC2Config
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ForcedOC3Config
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ForcedOC4Config
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ARRPreloadConfig
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_SelectCOM
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_SelectCCDMA
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_CCPreloadControl
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC1PreloadConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC2PreloadConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC3PreloadConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC4PreloadConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC1FastConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC2FastConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC3FastConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC4FastConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ClearOC1Ref
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ClearOC2Ref
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ClearOC3Ref
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ClearOC4Ref
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC1PolarityConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC1NPolarityConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_OC2PolarityConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_OC2NPolarityConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_OC3PolarityConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_OC3NPolarityConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_OC4PolarityConfig
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_CCxCmd
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_CCxNCmd
- 0x00000000 0x5c THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_SelectOCxM
- 0x00000000 0xbc THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TIM_UpdateDisableConfig
0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_OC2NPolarityConfig
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_OC3PolarityConfig
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_OC3NPolarityConfig
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_OC4PolarityConfig
+ 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_CCxCmd
+ 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_CCxNCmd
+ 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_SelectOCxM
+ 0x00000000 0xac THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TIM_UpdateDisableConfig
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_UpdateRequestConfig
0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_SelectHallSensor
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_SelectOnePulseMode
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_SelectOutputTrigger
@@ -903,46 +1164,61 @@ Discarded input sections
.text.TIM_SetClockDivision
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetCapture1
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetCapture2
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetCapture3
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetCapture4
0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetCounter
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetPrescaler
- 0x00000000 0x1c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetFlagStatus
- 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ClearFlag
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_GetITStatus
- 0x00000000 0x60 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x54 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TIM_ClearITPendingBit
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TI1_Config
- 0x00000000 0xe4 THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0xe0 THUMB Debug/../../obj/stm32f10x_tim.o
.text.TI2_Config
- 0x00000000 0x104 THUMB Debug/../../obj/stm32f10x_tim.o
- .text.TI3_Config
0x00000000 0xf4 THUMB Debug/../../obj/stm32f10x_tim.o
+ .text.TI3_Config
+ 0x00000000 0xec THUMB Debug/../../obj/stm32f10x_tim.o
.text.TI4_Config
- 0x00000000 0x10c THUMB Debug/../../obj/stm32f10x_tim.o
+ 0x00000000 0xf8 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_frame 0x00000000 0x16ac THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_info 0x00000000 0x1c26 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_abbrev 0x00000000 0x1b5 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_pubnames
+ 0x00000000 0x815 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_pubtypes
+ 0x00000000 0x17e THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_aranges
+ 0x00000000 0x2f0 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_ranges 0x00000000 0x2e0 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_line 0x00000000 0xc40 THUMB Debug/../../obj/stm32f10x_tim.o
+ .debug_str 0x00000000 0xea4 THUMB Debug/../../obj/stm32f10x_tim.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_tim.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/stm32f10x_tim.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_usart.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_usart.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_DeInit
- 0x00000000 0x114 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0xc0 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_StructInit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_ClockInit
0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_ClockStructInit
- 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_ITConfig
- 0x00000000 0xa0 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x90 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_DMACmd
0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_SetAddress
@@ -950,13 +1226,13 @@ Discarded input sections
.text.USART_WakeUpConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_ReceiverWakeUpCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_LINBreakDetectLengthConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_LINCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_SendData
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_SendBreak
0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_SetGuardTime
@@ -964,87 +1240,59 @@ Discarded input sections
.text.USART_SetPrescaler
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_SmartCardCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_SmartCardNACKCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_HalfDuplexCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_OverSampling8Cmd
0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_OneBitMethodCmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_IrDAConfig
0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_IrDACmd
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x40 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_ClearFlag
- 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_GetITStatus
- 0x00000000 0xc4 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0xb4 THUMB Debug/../../obj/stm32f10x_usart.o
.text.USART_ClearITPendingBit
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_usart.o
.text 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_wwdg.o
.data 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_wwdg.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f10x_wwdg.o
.text.WWDG_DeInit
- 0x00000000 0x2c THUMB Debug/../../obj/stm32f10x_wwdg.o
+ 0x00000000 0x20 THUMB Debug/../../obj/stm32f10x_wwdg.o
.text.WWDG_SetPrescaler
- 0x00000000 0x3c THUMB Debug/../../obj/stm32f10x_wwdg.o
+ 0x00000000 0x34 THUMB Debug/../../obj/stm32f10x_wwdg.o
.text.WWDG_SetWindowValue
- 0x00000000 0x44 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ 0x00000000 0x38 THUMB Debug/../../obj/stm32f10x_wwdg.o
.text.WWDG_EnableIT
0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_wwdg.o
.text.WWDG_SetCounter
0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_wwdg.o
.text.WWDG_Enable
- 0x00000000 0x28 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ 0x00000000 0x24 THUMB Debug/../../obj/stm32f10x_wwdg.o
.text.WWDG_GetFlagStatus
0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_wwdg.o
.text.WWDG_ClearFlag
0x00000000 0x18 THUMB Debug/../../obj/stm32f10x_wwdg.o
- .text 0x00000000 0x0 THUMB Debug/../../obj/core_cm3.o
- .data 0x00000000 0x0 THUMB Debug/../../obj/core_cm3.o
- .bss 0x00000000 0x0 THUMB Debug/../../obj/core_cm3.o
- .text.__get_PSP
- 0x00000000 0x10 THUMB Debug/../../obj/core_cm3.o
- .text.__set_PSP
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__get_MSP
- 0x00000000 0x10 THUMB Debug/../../obj/core_cm3.o
- .text.__set_MSP
- 0x00000000 0x8 THUMB Debug/../../obj/core_cm3.o
- .text.__get_BASEPRI
- 0x00000000 0x20 THUMB Debug/../../obj/core_cm3.o
- .text.__set_BASEPRI
- 0x00000000 0x18 THUMB Debug/../../obj/core_cm3.o
- .text.__get_PRIMASK
- 0x00000000 0x20 THUMB Debug/../../obj/core_cm3.o
- .text.__set_PRIMASK
- 0x00000000 0x18 THUMB Debug/../../obj/core_cm3.o
- .text.__get_FAULTMASK
- 0x00000000 0x20 THUMB Debug/../../obj/core_cm3.o
- .text.__set_FAULTMASK
- 0x00000000 0x18 THUMB Debug/../../obj/core_cm3.o
- .text.__get_CONTROL
- 0x00000000 0x20 THUMB Debug/../../obj/core_cm3.o
- .text.__set_CONTROL
- 0x00000000 0x18 THUMB Debug/../../obj/core_cm3.o
- .text.__REV 0x00000000 0x24 THUMB Debug/../../obj/core_cm3.o
- .text.__REV16 0x00000000 0x24 THUMB Debug/../../obj/core_cm3.o
- .text.__REVSH 0x00000000 0x24 THUMB Debug/../../obj/core_cm3.o
- .text.__RBIT 0x00000000 0x24 THUMB Debug/../../obj/core_cm3.o
- .text.__LDREXB
- 0x00000000 0x24 THUMB Debug/../../obj/core_cm3.o
- .text.__LDREXH
- 0x00000000 0x24 THUMB Debug/../../obj/core_cm3.o
- .text.__LDREXW
- 0x00000000 0x24 THUMB Debug/../../obj/core_cm3.o
- .text.__STREXB
- 0x00000000 0x2c THUMB Debug/../../obj/core_cm3.o
- .text.__STREXH
- 0x00000000 0x2c THUMB Debug/../../obj/core_cm3.o
- .text.__STREXW
- 0x00000000 0x28 THUMB Debug/../../obj/core_cm3.o
+ .debug_frame 0x00000000 0x1c4 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_info 0x00000000 0x207 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_abbrev 0x00000000 0x11c THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_pubnames
+ 0x00000000 0xd9 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_pubtypes
+ 0x00000000 0xf1 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_aranges
+ 0x00000000 0x58 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_ranges 0x00000000 0x48 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_line 0x00000000 0x2d4 THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .debug_str 0x00000000 0x32f THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .comment 0x00000000 0x4d THUMB Debug/../../obj/stm32f10x_wwdg.o
+ .ARM.attributes
+ 0x00000000 0x33 THUMB Debug/../../obj/stm32f10x_wwdg.o
.text 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f10x.o
.data 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f10x.o
.bss 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f10x.o
@@ -1053,170 +1301,1866 @@ Discarded input sections
.data.AHBPrescTable
0x00000000 0x10 THUMB Debug/../../obj/system_stm32f10x.o
.text.SystemInit
- 0x00000000 0xb0 THUMB Debug/../../obj/system_stm32f10x.o
+ 0x00000000 0x6c THUMB Debug/../../obj/system_stm32f10x.o
.text.SystemCoreClockUpdate
- 0x00000000 0x148 THUMB Debug/../../obj/system_stm32f10x.o
+ 0x00000000 0xd8 THUMB Debug/../../obj/system_stm32f10x.o
.text.SetSysClock
0x00000000 0x10 THUMB Debug/../../obj/system_stm32f10x.o
.text.SetSysClockTo72
- 0x00000000 0x1ac THUMB Debug/../../obj/system_stm32f10x.o
- .text 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .data 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .bss 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .text.libdebugio
- 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .text.libdebugio.__do_nvdebug_operation
- 0x00000000 0x18 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- .text.libdebugio.debug_abort
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+ .rodata.libc.__RAL_unicode_to_cp1253_range_map
+ 0x00000000 0x48 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .bss.libc.__user_format_extender
+ 0x00000000 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_unicode_to_iso8859_9_singleton_map
+ 0x00000000 0x1c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .tbss.__RAL_wcstok_state
+ 0x00000000 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .data.libc.stderr
+ 0x00000000 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_unicode_to_cp1254_range_map
+ 0x00000000 0x30 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_unicode_to_iso8859_14_range_map
+ 0x00000000 0x54 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_iso8859_15_to_unicode_map
+ 0x00000000 0x100 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_c_locale_time_format
+ 0x00000000 0x9 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .data.libc.__RAL_rand_next
+ 0x00000000 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_c_locale_date_format
+ 0x00000000 0x9 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .bss.libc.__RAL_error_decoder_head
+ 0x00000000 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .bss.libc.__atexitfns
+ 0x00000000 0x80 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_unicode_to_cp1253_singleton_map
+ 0x00000000 0x40 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_iso8859_6_to_unicode_map
+ 0x00000000 0x100 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_unicode_bmp_tolower_singleton_map
+ 0x00000000 0x13c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_codeset_utf8
+ 0x00000000 0x20 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_cp1257_to_unicode_map
+ 0x00000000 0x100 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_data_utf8_comma
+ 0x00000000 0x2 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_unicode_to_cp1258_range_map
+ 0x00000000 0x54 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .bss.libc._tm 0x00000000 0x24 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_unicode_to_iso8859_13_range_map
+ 0x00000000 0x42 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_iso8859_16_to_unicode_map
+ 0x00000000 0x100 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_unicode_bmp_toupper_range2_map
+ 0x00000000 0xd2 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_cp1252_to_unicode_map
+ 0x00000000 0x100 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_unicode_to_iso8859_4_range_map
+ 0x00000000 0x42 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_codeset_iso8859_10
+ 0x00000000 0x20 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__aeabi_ERANGE
+ 0x00000000 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_unicode_to_iso8859_9_range_map
+ 0x00000000 0x18 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_ascii_ctype_map
+ 0x00000000 0x80 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_iso8859_11_to_unicode_map
+ 0x00000000 0x100 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .rodata.libc.__RAL_unicode_to_iso8859_14_singleton_map
+ 0x00000000 0x60 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .debug_frame 0x00000000 0x3d6c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .debug_info 0x00000000 0x2374 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .debug_abbrev 0x00000000 0x179 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .debug_aranges
+ 0x00000000 0xfa0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .debug_ranges 0x00000000 0xf90 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .debug_line 0x00000000 0xb26 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .debug_str 0x00000000 0x203c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .comment 0x00000000 0x4d C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .ARM.attributes
+ 0x00000000 0x2d C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2.o)
+ .text.libc 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .data.libc 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .bss.libc 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .text.libc.longjmp
+ 0x00000000 0x14 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .text.libc.memcpy
+ 0x00000000 0x3c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .text.libc.memcpy_fast
+ 0x00000000 0x3ac C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .text.libc.memcpy_small
+ 0x00000000 0x1c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .text.libc.memset
+ 0x00000000 0x60 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .text.libc.__aeabi_memset
+ 0x00000000 0x64 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .text.libc.setjmp
+ 0x00000000 0xc C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .text.libc.strcpy
+ 0x00000000 0x44 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .text.libc.strcmp
+ 0x00000000 0x50 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .text.libc.strlen
+ 0x00000000 0x60 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .debug_frame 0x00000000 0xb0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
+ .ARM.attributes
+ 0x00000000 0x1b C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a(libc2_asm.o)
Memory Configuration
@@ -1228,7 +3172,8 @@ FLASH 0x08006000 0x0001a000 xr
Linker script and memory map
- 0x08007b4c __do_debug_operation = __do_debug_operation_mempoll
+ 0x00000000 __vfprintf = __vfprintf_float_long_long
+ 0x00000000 __vfscanf = __vfscanf_float_long_long_cc
0x20000000 __SRAM_segment_start__ = 0x20000000
0x20005000 __SRAM_segment_end__ = 0x20005000
0x08006000 __FLASH_segment_start__ = 0x8006000
@@ -1261,193 +3206,189 @@ Linker script and memory map
0x00000001 . = ASSERT (((__vectors_end__ >= __FLASH_segment_start__) && (__vectors_end__ <= __FLASH_segment_end__)), error: .vectors is too large to fit in FLASH memory segment)
0x08006154 __init_load_start__ = ALIGN (__vectors_end__, 0x4)
-.init 0x08006154 0x114
+.init 0x08006154 0x118
0x08006154 __init_start__ = .
*(.init .init.*)
- .init 0x08006154 0x114 THUMB Debug/../../obj/cstart.o
+ .init 0x08006154 0x118 THUMB Debug/../../obj/cstart.o
0x08006154 _start
- 0x080061d2 exit
- 0x080061f6 reset_handler
- 0x08006268 __init_end__ = (__init_start__ + SIZEOF (.init))
- 0x08006268 __init_load_end__ = __init_end__
+ 0x080061d6 exit
+ 0x080061fa reset_handler
+ 0x0800626c __init_end__ = (__init_start__ + SIZEOF (.init))
+ 0x0800626c __init_load_end__ = __init_end__
0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= __FLASH_segment_end__)), error: .init is too large to fit in FLASH memory segment)
- 0x08006268 __text_load_start__ = ALIGN (__init_end__, 0x4)
+ 0x0800626c __text_load_start__ = ALIGN (__init_end__, 0x4)
-.text 0x08006268 0x1924
- 0x08006268 __text_start__ = .
+.text 0x0800626c 0x1370
+ 0x0800626c __text_start__ = .
*(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table .ARM.extab* .gnu.linkonce.armextab.*)
- .glue_7 0x00000000 0x0 linker stubs
- .glue_7t 0x00000000 0x0 linker stubs
- .text.LedInit 0x08006268 0x60 THUMB Debug/../../obj/led.o
- 0x08006268 LedInit
+ .glue_7 0x0800626c 0x0 linker stubs
+ .glue_7t 0x0800626c 0x0 linker stubs
+ .text.LedInit 0x0800626c 0x48 THUMB Debug/../../obj/led.o
+ 0x0800626c LedInit
.text.LedToggle
- 0x080062c8 0x9c THUMB Debug/../../obj/led.o
- 0x080062c8 LedToggle
- .text.main 0x08006364 0x30 THUMB Debug/../../obj/main.o
- 0x08006364 main
- .text.Init 0x08006394 0x254 THUMB Debug/../../obj/main.o
+ 0x080062b4 0x6c THUMB Debug/../../obj/led.o
+ 0x080062b4 LedToggle
+ .text.main 0x08006320 0x28 THUMB Debug/../../obj/main.o
+ 0x08006320 main
+ .text.Init 0x08006348 0x160 THUMB Debug/../../obj/main.o
.text.NVIC_SetPriority
- 0x080065e8 0x58 THUMB Debug/../../obj/timer.o
+ 0x080064a8 0x54 THUMB Debug/../../obj/timer.o
.text.SysTick_Config
- 0x08006640 0x68 THUMB Debug/../../obj/timer.o
+ 0x080064fc 0x48 THUMB Debug/../../obj/timer.o
.text.TimerInit
- 0x080066a8 0x28 THUMB Debug/../../obj/timer.o
- 0x080066a8 TimerInit
+ 0x08006544 0x20 THUMB Debug/../../obj/timer.o
+ 0x08006544 TimerInit
.text.TimerSet
- 0x080066d0 0x20 THUMB Debug/../../obj/timer.o
- 0x080066d0 TimerSet
+ 0x08006564 0x1c THUMB Debug/../../obj/timer.o
+ 0x08006564 TimerSet
.text.TimerGet
- 0x080066f0 0x18 THUMB Debug/../../obj/timer.o
- 0x080066f0 TimerGet
+ 0x08006580 0x14 THUMB Debug/../../obj/timer.o
+ 0x08006580 TimerGet
.text.TimerISRHandler
- 0x08006708 0x24 THUMB Debug/../../obj/timer.o
- 0x08006708 TimerISRHandler
+ 0x08006594 0x1c THUMB Debug/../../obj/timer.o
+ 0x08006594 TimerISRHandler
.text.UnusedISR
- 0x0800672c 0x8 THUMB Debug/../../obj/vectors.o
- 0x0800672c UnusedISR
- .text.__DSB 0x08006734 0x10 THUMB Debug/../../obj/boot.o
+ 0x080065b0 0x8 THUMB Debug/../../obj/vectors.o
+ 0x080065b0 UnusedISR
.text.NVIC_SystemReset
- 0x08006744 0x34 THUMB Debug/../../obj/boot.o
+ 0x080065b8 0x28 THUMB Debug/../../obj/boot.o
.text.BootComInit
- 0x08006778 0x1c THUMB Debug/../../obj/boot.o
- 0x08006778 BootComInit
+ 0x080065e0 0x18 THUMB Debug/../../obj/boot.o
+ 0x080065e0 BootComInit
.text.BootComCheckActivationRequest
- 0x08006794 0x1c THUMB Debug/../../obj/boot.o
- 0x08006794 BootComCheckActivationRequest
+ 0x080065f8 0x18 THUMB Debug/../../obj/boot.o
+ 0x080065f8 BootComCheckActivationRequest
.text.BootActivate
- 0x080067b0 0x10 THUMB Debug/../../obj/boot.o
- 0x080067b0 BootActivate
+ 0x08006610 0x10 THUMB Debug/../../obj/boot.o
+ 0x08006610 BootActivate
.text.BootComUartInit
- 0x080067c0 0xd0 THUMB Debug/../../obj/boot.o
+ 0x08006620 0x94 THUMB Debug/../../obj/boot.o
.text.BootComUartCheckActivationRequest
- 0x08006890 0xdc THUMB Debug/../../obj/boot.o
+ 0x080066b4 0x88 THUMB Debug/../../obj/boot.o
.text.UartReceiveByte
- 0x0800696c 0x54 THUMB Debug/../../obj/boot.o
+ 0x0800673c 0x40 THUMB Debug/../../obj/boot.o
.text.CanGetSpeedConfig
- 0x080069c0 0xf4 THUMB Debug/../../obj/boot.o
+ 0x0800677c 0xc0 THUMB Debug/../../obj/boot.o
.text.BootComCanInit
- 0x08006ab4 0x184 THUMB Debug/../../obj/boot.o
+ 0x0800683c 0x128 THUMB Debug/../../obj/boot.o
.text.BootComCanCheckActivationRequest
- 0x08006c38 0x64 THUMB Debug/../../obj/boot.o
+ 0x08006964 0x54 THUMB Debug/../../obj/boot.o
.text.CAN_DeInit
- 0x08006c9c 0x68 THUMB Debug/../../obj/stm32f10x_can.o
- 0x08006c9c CAN_DeInit
+ 0x080069b8 0x4c THUMB Debug/../../obj/stm32f10x_can.o
+ 0x080069b8 CAN_DeInit
.text.CAN_Init
- 0x08006d04 0x1c0 THUMB Debug/../../obj/stm32f10x_can.o
- 0x08006d04 CAN_Init
+ 0x08006a04 0x1a0 THUMB Debug/../../obj/stm32f10x_can.o
+ 0x08006a04 CAN_Init
.text.CAN_FilterInit
- 0x08006ec4 0x20c THUMB Debug/../../obj/stm32f10x_can.o
- 0x08006ec4 CAN_FilterInit
+ 0x08006ba4 0x174 THUMB Debug/../../obj/stm32f10x_can.o
+ 0x08006ba4 CAN_FilterInit
.text.CAN_StructInit
- 0x080070d0 0x6c THUMB Debug/../../obj/stm32f10x_can.o
- 0x080070d0 CAN_StructInit
+ 0x08006d18 0x54 THUMB Debug/../../obj/stm32f10x_can.o
+ 0x08006d18 CAN_StructInit
.text.CAN_Receive
- 0x0800713c 0x1a8 THUMB Debug/../../obj/stm32f10x_can.o
- 0x0800713c CAN_Receive
+ 0x08006d6c 0x174 THUMB Debug/../../obj/stm32f10x_can.o
+ 0x08006d6c CAN_Receive
.text.CAN_MessagePending
- 0x080072e4 0x50 THUMB Debug/../../obj/stm32f10x_can.o
- 0x080072e4 CAN_MessagePending
+ 0x08006ee0 0x48 THUMB Debug/../../obj/stm32f10x_can.o
+ 0x08006ee0 CAN_MessagePending
.text.GPIO_Init
- 0x08007334 0x1b0 THUMB Debug/../../obj/stm32f10x_gpio.o
- 0x08007334 GPIO_Init
+ 0x08006f28 0x178 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x08006f28 GPIO_Init
.text.GPIO_SetBits
- 0x080074e4 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
- 0x080074e4 GPIO_SetBits
+ 0x080070a0 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x080070a0 GPIO_SetBits
.text.GPIO_ResetBits
- 0x08007500 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
- 0x08007500 GPIO_ResetBits
+ 0x080070bc 0x1c THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x080070bc GPIO_ResetBits
.text.GPIO_PinRemapConfig
- 0x0800751c 0x11c THUMB Debug/../../obj/stm32f10x_gpio.o
- 0x0800751c GPIO_PinRemapConfig
+ 0x080070d8 0xe0 THUMB Debug/../../obj/stm32f10x_gpio.o
+ 0x080070d8 GPIO_PinRemapConfig
.text.RCC_GetClocksFreq
- 0x08007638 0x1d4 THUMB Debug/../../obj/stm32f10x_rcc.o
- 0x08007638 RCC_GetClocksFreq
+ 0x080071b8 0x160 THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x080071b8 RCC_GetClocksFreq
.text.RCC_APB2PeriphClockCmd
- 0x0800780c 0x50 THUMB Debug/../../obj/stm32f10x_rcc.o
- 0x0800780c RCC_APB2PeriphClockCmd
+ 0x08007318 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x08007318 RCC_APB2PeriphClockCmd
.text.RCC_APB1PeriphClockCmd
- 0x0800785c 0x50 THUMB Debug/../../obj/stm32f10x_rcc.o
- 0x0800785c RCC_APB1PeriphClockCmd
+ 0x08007354 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x08007354 RCC_APB1PeriphClockCmd
.text.RCC_APB1PeriphResetCmd
- 0x080078ac 0x50 THUMB Debug/../../obj/stm32f10x_rcc.o
- 0x080078ac RCC_APB1PeriphResetCmd
+ 0x08007390 0x3c THUMB Debug/../../obj/stm32f10x_rcc.o
+ 0x08007390 RCC_APB1PeriphResetCmd
.text.USART_Init
- 0x080078fc 0x1b0 THUMB Debug/../../obj/stm32f10x_usart.o
- 0x080078fc USART_Init
+ 0x080073cc 0x178 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x080073cc USART_Init
.text.USART_Cmd
- 0x08007aac 0x3c THUMB Debug/../../obj/stm32f10x_usart.o
- 0x08007aac USART_Cmd
+ 0x08007544 0x40 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x08007544 USART_Cmd
.text.USART_ReceiveData
- 0x08007ae8 0x24 THUMB Debug/../../obj/stm32f10x_usart.o
- 0x08007ae8 USART_ReceiveData
+ 0x08007584 0x20 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x08007584 USART_ReceiveData
.text.USART_GetFlagStatus
- 0x08007b0c 0x40 THUMB Debug/../../obj/stm32f10x_usart.o
- 0x08007b0c USART_GetFlagStatus
- .text.libdebugio.__do_debug_operation_mempoll
- 0x08007b4c 0x38 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x08007b4c __do_debug_operation_mempoll
- .text.libc.__debug_io_lock
- 0x08007b84 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- 0x08007b84 __debug_io_lock
- .text.libc.__debug_io_unlock
- 0x08007b88 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a(user_libc.o)
- 0x08007b88 __debug_io_unlock
- 0x08007b8c __text_end__ = (__text_start__ + SIZEOF (.text))
- 0x08007b8c __text_load_end__ = __text_end__
+ 0x080075a4 0x38 THUMB Debug/../../obj/stm32f10x_usart.o
+ 0x080075a4 USART_GetFlagStatus
+ 0x080075dc __text_end__ = (__text_start__ + SIZEOF (.text))
+ 0x080075dc __text_load_end__ = __text_end__
.vfp11_veneer 0x00000000 0x0
.vfp11_veneer 0x00000000 0x0 linker stubs
.v4_bx 0x00000000 0x0
.v4_bx 0x00000000 0x0 linker stubs
- 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= __FLASH_segment_end__)), error: .text is too large to fit in FLASH memory segment)
- 0x08007b8c __dtors_load_start__ = ALIGN (__text_end__, 0x4)
-.dtors 0x08007b8c 0x0
- 0x08007b8c __dtors_start__ = .
+.iplt 0x00000000 0x0
+ .iplt 0x00000000 0x0 THUMB Debug/../../obj/cstart.o
+ 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= __FLASH_segment_end__)), error: .text is too large to fit in FLASH memory segment)
+ 0x080075dc __dtors_load_start__ = ALIGN (__text_end__, 0x4)
+
+.dtors 0x080075dc 0x0
+ 0x080075dc __dtors_start__ = .
*(SORT(.dtors.*))
*(.dtors)
*(.fini_array .fini_array.*)
- 0x08007b8c __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
- 0x08007b8c __dtors_load_end__ = __dtors_end__
+ 0x080075dc __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
+ 0x080075dc __dtors_load_end__ = __dtors_end__
0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= __FLASH_segment_end__)), error: .dtors is too large to fit in FLASH memory segment)
- 0x08007b8c __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
+ 0x080075dc __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
-.ctors 0x08007b8c 0x0
- 0x08007b8c __ctors_start__ = .
+.ctors 0x080075dc 0x0
+ 0x080075dc __ctors_start__ = .
*(SORT(.ctors.*))
*(.ctors)
*(.init_array .init_array.*)
- 0x08007b8c __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
- 0x08007b8c __ctors_load_end__ = __ctors_end__
+ 0x080075dc __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
+ 0x080075dc __ctors_load_end__ = __ctors_end__
0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= __FLASH_segment_end__)), error: .ctors is too large to fit in FLASH memory segment)
- 0x08007b8c __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
+ 0x080075dc __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
-.rodata 0x08007b8c 0x48
- 0x08007b8c __rodata_start__ = .
+.rodata 0x080075dc 0x24
+ 0x080075dc __rodata_start__ = .
*(.rodata .rodata.* .gnu.linkonce.r.*)
.rodata.canTiming
- 0x08007b8c 0x48 THUMB Debug/../../obj/boot.o
- 0x08007bd4 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
- 0x08007bd4 __rodata_load_end__ = __rodata_end__
+ 0x080075dc 0x24 THUMB Debug/../../obj/boot.o
+ 0x08007600 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
+ 0x08007600 __rodata_load_end__ = __rodata_end__
+
+.rel.dyn 0x08006000 0x0
+ .rel.iplt 0x08006000 0x0 THUMB Debug/../../obj/cstart.o
0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= __FLASH_segment_end__)), error: .rodata is too large to fit in FLASH memory segment)
- 0x08007bd4 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4)
+ 0x08007600 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4)
-.ARM.exidx 0x08007bd4 0x0
- 0x08007bd4 __ARM.exidx_start__ = .
- 0x08007bd4 __exidx_start = __ARM.exidx_start__
+.ARM.exidx 0x08007600 0x0
+ 0x08007600 __ARM.exidx_start__ = .
+ 0x08007600 __exidx_start = __ARM.exidx_start__
*(.ARM.exidx .ARM.exidx.*)
- 0x08007bd4 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx))
- 0x08007bd4 __exidx_end = __ARM.exidx_end__
- 0x08007bd4 __ARM.exidx_load_end__ = __ARM.exidx_end__
+ 0x08007600 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx))
+ 0x08007600 __exidx_end = __ARM.exidx_end__
+ 0x08007600 __ARM.exidx_load_end__ = __ARM.exidx_end__
0x00000001 . = ASSERT (((__ARM.exidx_end__ >= __FLASH_segment_start__) && (__ARM.exidx_end__ <= __FLASH_segment_end__)), error: .ARM.exidx is too large to fit in FLASH memory segment)
- 0x08007bd4 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4)
+ 0x08007600 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4)
-.fast 0x20000000 0x0 load address 0x08007bd4
+.fast 0x20000000 0x0 load address 0x08007600
0x20000000 __fast_start__ = .
*(.fast .fast.*)
0x20000000 __fast_end__ = (__fast_start__ + SIZEOF (.fast))
- 0x08007bd4 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
+ 0x08007600 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
0x00000001 . = ASSERT (((__fast_load_end__ >= __FLASH_segment_start__) && (__fast_load_end__ <= __FLASH_segment_end__)), error: .fast is too large to fit in FLASH memory segment)
.fast_run 0x20000000 0x0
@@ -1456,9 +3397,9 @@ Linker script and memory map
0x20000000 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run))
0x20000000 __fast_run_load_end__ = __fast_run_end__
0x00000001 . = ASSERT (((__fast_run_end__ >= __SRAM_segment_start__) && (__fast_run_end__ <= __SRAM_segment_end__)), error: .fast_run is too large to fit in SRAM memory segment)
- 0x08007bd4 __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4)
+ 0x08007600 __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4)
-.data 0x20000000 0x14 load address 0x08007bd4
+.data 0x20000000 0x14 load address 0x08007600
0x20000000 __data_start__ = .
*(.data .data.* .gnu.linkonce.d.*)
.data.APBAHBPrescTable
@@ -1466,107 +3407,103 @@ Linker script and memory map
.data.ADCPrescTable
0x20000010 0x4 THUMB Debug/../../obj/stm32f10x_rcc.o
0x20000014 __data_end__ = (__data_start__ + SIZEOF (.data))
- 0x08007be8 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+ 0x08007614 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+
+.igot.plt 0x00000000 0x0
+ .igot.plt 0x00000000 0x0 THUMB Debug/../../obj/cstart.o
0x00000001 . = ASSERT (((__data_load_end__ >= __FLASH_segment_start__) && (__data_load_end__ <= __FLASH_segment_end__)), error: .data is too large to fit in FLASH memory segment)
-.data_run 0x20000000 0x14 load address 0x08007bd4
+.data_run 0x20000000 0x14 load address 0x08007600
0x20000000 __data_run_start__ = .
0x20000014 . = MAX ((__data_run_start__ + SIZEOF (.data)), .)
- *fill* 0x20000000 0x14 00
+ *fill* 0x20000000 0x14
0x20000014 __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run))
0x20000014 __data_run_load_end__ = __data_run_end__
0x00000001 . = ASSERT (((__data_run_end__ >= __SRAM_segment_start__) && (__data_run_end__ <= __SRAM_segment_end__)), error: .data_run is too large to fit in SRAM memory segment)
0x20000014 __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
-.bss 0x20000014 0x60
+.bss 0x20000014 0x52
0x20000014 __bss_start__ = .
*(.bss .bss.* .gnu.linkonce.b.*)
- .bss.timer_counter_last.3152
+ .bss.timer_counter_last.6204
0x20000014 0x4 THUMB Debug/../../obj/led.o
- .bss.led_toggle_state.3151
+ .bss.led_toggle_state.6203
0x20000018 0x1 THUMB Debug/../../obj/led.o
- *fill* 0x20000019 0x3 00
+ *fill* 0x20000019 0x3
.bss.millisecond_counter
0x2000001c 0x4 THUMB Debug/../../obj/timer.o
- .bss.xcpCtoRxInProgress.3173
+ .bss.xcpCtoRxInProgress.6225
0x20000020 0x1 THUMB Debug/../../obj/boot.o
- *fill* 0x20000021 0x3 00
- .bss.xcpCtoReqPacket.3171
- 0x20000024 0x44 THUMB Debug/../../obj/boot.o
- .bss.xcpCtoRxLength.3172
- 0x20000068 0x1 THUMB Debug/../../obj/boot.o
- *fill* 0x20000069 0x3 00
- .bss.libdebugio.dbgCommWord
- 0x2000006c 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x2000006c dbgCommWord
- .bss.libdebugio.dbgCntrlWord_mempoll
- 0x20000070 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a(libdebugio.o)
- 0x20000070 dbgCntrlWord_mempoll
+ *fill* 0x20000021 0x3
+ .bss.xcpCtoReqPacket.6223
+ 0x20000024 0x41 THUMB Debug/../../obj/boot.o
+ .bss.xcpCtoRxLength.6224
+ 0x20000065 0x1 THUMB Debug/../../obj/boot.o
*(COMMON)
- 0x20000074 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
- 0x20000074 __bss_load_end__ = __bss_end__
+ 0x20000066 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
+ 0x20000066 __bss_load_end__ = __bss_end__
0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= __SRAM_segment_end__)), error: .bss is too large to fit in SRAM memory segment)
- 0x20000074 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
+ 0x20000068 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
-.non_init 0x20000074 0x0
- 0x20000074 __non_init_start__ = .
+.non_init 0x20000068 0x0
+ 0x20000068 __non_init_start__ = .
*(.non_init .non_init.*)
- 0x20000074 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
- 0x20000074 __non_init_load_end__ = __non_init_end__
+ 0x20000068 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
+ 0x20000068 __non_init_load_end__ = __non_init_end__
0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= __SRAM_segment_end__)), error: .non_init is too large to fit in SRAM memory segment)
- 0x20000074 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
+ 0x20000068 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
-.heap 0x20000074 0x80
- 0x20000074 __heap_start__ = .
+.heap 0x20000068 0x80
+ 0x20000068 __heap_start__ = .
*(.heap .heap.*)
- 0x200000f4 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
- *fill* 0x20000074 0x80 00
- 0x200000f4 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
- 0x200000f4 __heap_load_end__ = __heap_end__
+ 0x200000e8 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
+ *fill* 0x20000068 0x80
+ 0x200000e8 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
+ 0x200000e8 __heap_load_end__ = __heap_end__
0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= __SRAM_segment_end__)), error: .heap is too large to fit in SRAM memory segment)
- 0x200000f4 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
+ 0x200000e8 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
-.stack 0x200000f4 0x100
- 0x200000f4 __stack_start__ = .
+.stack 0x200000e8 0x100
+ 0x200000e8 __stack_start__ = .
*(.stack .stack.*)
- 0x200001f4 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
- *fill* 0x200000f4 0x100 00
- 0x200001f4 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
- 0x200001f4 __stack_load_end__ = __stack_end__
+ 0x200001e8 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
+ *fill* 0x200000e8 0x100
+ 0x200001e8 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
+ 0x200001e8 __stack_load_end__ = __stack_end__
0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= __SRAM_segment_end__)), error: .stack is too large to fit in SRAM memory segment)
- 0x200001f4 __stack_process_load_start__ = ALIGN (__stack_end__, 0x4)
+ 0x200001e8 __stack_process_load_start__ = ALIGN (__stack_end__, 0x4)
-.stack_process 0x200001f4 0x0
- 0x200001f4 __stack_process_start__ = .
+.stack_process 0x200001e8 0x0
+ 0x200001e8 __stack_process_start__ = .
*(.stack_process .stack_process.*)
- 0x200001f4 . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4)
- 0x200001f4 __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process))
- 0x200001f4 __stack_process_load_end__ = __stack_process_end__
+ 0x200001e8 . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4)
+ 0x200001e8 __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process))
+ 0x200001e8 __stack_process_load_end__ = __stack_process_end__
0x00000001 . = ASSERT (((__stack_process_end__ >= __SRAM_segment_start__) && (__stack_process_end__ <= __SRAM_segment_end__)), error: .stack_process is too large to fit in SRAM memory segment)
- 0x200001f4 __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4)
+ 0x200001e8 __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4)
-.tbss 0x200001f4 0x0
- 0x200001f4 __tbss_start__ = .
+.tbss 0x200001e8 0x0
+ 0x200001e8 __tbss_start__ = .
*(.tbss .tbss.*)
- 0x200001f4 __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss))
- 0x200001f4 __tbss_load_end__ = __tbss_end__
+ 0x200001e8 __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss))
+ 0x200001e8 __tbss_load_end__ = __tbss_end__
0x00000001 . = ASSERT (((__tbss_end__ >= __SRAM_segment_start__) && (__tbss_end__ <= __SRAM_segment_end__)), error: .tbss is too large to fit in SRAM memory segment)
- 0x08007be8 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
+ 0x08007614 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
-.tdata 0x200001f4 0x0 load address 0x08007be8
- 0x200001f4 __tdata_start__ = .
+.tdata 0x200001e8 0x0 load address 0x08007614
+ 0x200001e8 __tdata_start__ = .
*(.tdata .tdata.*)
- 0x200001f4 __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata))
- 0x08007be8 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata))
- 0x08007be8 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata))
+ 0x200001e8 __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata))
+ 0x08007614 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata))
+ 0x08007614 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata))
0x00000001 . = ASSERT (((__tdata_load_end__ >= __FLASH_segment_start__) && (__tdata_load_end__ <= __FLASH_segment_end__)), error: .tdata is too large to fit in FLASH memory segment)
-.tdata_run 0x200001f4 0x0
- 0x200001f4 __tdata_run_start__ = .
- 0x200001f4 . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .)
- 0x200001f4 __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run))
- 0x200001f4 __tdata_run_load_end__ = __tdata_run_end__
- 0x200001f4 __SRAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run))
+.tdata_run 0x200001e8 0x0
+ 0x200001e8 __tdata_run_start__ = .
+ 0x200001e8 . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .)
+ 0x200001e8 __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run))
+ 0x200001e8 __tdata_run_load_end__ = __tdata_run_end__
+ 0x200001e8 __SRAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run))
0x00000001 . = ASSERT (((__tdata_run_end__ >= __SRAM_segment_start__) && (__tdata_run_end__ <= __SRAM_segment_end__)), error: .tdata_run is too large to fit in SRAM memory segment)
START GROUP
LOAD THUMB Debug/../../obj/cstart.o
@@ -1598,228 +3535,90 @@ LOAD THUMB Debug/../../obj/stm32f10x_spi.o
LOAD THUMB Debug/../../obj/stm32f10x_tim.o
LOAD THUMB Debug/../../obj/stm32f10x_usart.o
LOAD THUMB Debug/../../obj/stm32f10x_wwdg.o
-LOAD THUMB Debug/../../obj/core_cm3.o
LOAD THUMB Debug/../../obj/system_stm32f10x.o
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcm_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcpp_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_targetio_impl_v7m_t_le.a
-LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7m_t_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libcm_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libdebugio_mempoll_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libm_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libc_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libcpp_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libdebugio_v7m_t_le_eabi.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfprintf_v7m_t_le_eabi.o
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 3.7/lib/libvfscanf_v7m_t_le_eabi.o
END GROUP
OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/../bin/demoprog_olimex_stm32p103.elf elf32-littlearm)
.ARM.attributes
- 0x00000000 0x10
+ 0x00000000 0x2f
.ARM.attributes
- 0x00000000 0x10 THUMB Debug/../../obj/cstart.o
+ 0x00000000 0x21 THUMB Debug/../../obj/cstart.o
.ARM.attributes
- 0x00000010 0x10 THUMB Debug/../../obj/led.o
+ 0x00000021 0x33 THUMB Debug/../../obj/led.o
.ARM.attributes
- 0x00000020 0x10 THUMB Debug/../../obj/main.o
+ 0x00000054 0x33 THUMB Debug/../../obj/main.o
.ARM.attributes
- 0x00000030 0x10 THUMB Debug/../../obj/timer.o
+ 0x00000087 0x33 THUMB Debug/../../obj/timer.o
.ARM.attributes
- 0x00000040 0x10 THUMB Debug/../../obj/vectors.o
+ 0x000000ba 0x33 THUMB Debug/../../obj/vectors.o
.ARM.attributes
- 0x00000050 0x10 THUMB Debug/../../obj/boot.o
+ 0x000000ed 0x33 THUMB Debug/../../obj/boot.o
.ARM.attributes
- 0x00000060 0x10 THUMB Debug/../../obj/misc.o
+ 0x00000120 0x33 THUMB Debug/../../obj/stm32f10x_can.o
.ARM.attributes
- 0x00000070 0x10 THUMB Debug/../../obj/stm32f10x_adc.o
+ 0x00000153 0x33 THUMB Debug/../../obj/stm32f10x_gpio.o
.ARM.attributes
- 0x00000080 0x10 THUMB Debug/../../obj/stm32f10x_bkp.o
+ 0x00000186 0x33 THUMB Debug/../../obj/stm32f10x_rcc.o
.ARM.attributes
- 0x00000090 0x10 THUMB Debug/../../obj/stm32f10x_can.o
- .ARM.attributes
- 0x000000a0 0x10 THUMB Debug/../../obj/stm32f10x_cec.o
- .ARM.attributes
- 0x000000b0 0x10 THUMB Debug/../../obj/stm32f10x_crc.o
- .ARM.attributes
- 0x000000c0 0x10 THUMB Debug/../../obj/stm32f10x_dac.o
- .ARM.attributes
- 0x000000d0 0x10 THUMB Debug/../../obj/stm32f10x_dbgmcu.o
- .ARM.attributes
- 0x000000e0 0x10 THUMB Debug/../../obj/stm32f10x_dma.o
- .ARM.attributes
- 0x000000f0 0x10 THUMB Debug/../../obj/stm32f10x_exti.o
- .ARM.attributes
- 0x00000100 0x10 THUMB Debug/../../obj/stm32f10x_flash.o
- .ARM.attributes
- 0x00000110 0x10 THUMB Debug/../../obj/stm32f10x_fsmc.o
- .ARM.attributes
- 0x00000120 0x10 THUMB Debug/../../obj/stm32f10x_gpio.o
- .ARM.attributes
- 0x00000130 0x10 THUMB Debug/../../obj/stm32f10x_i2c.o
- .ARM.attributes
- 0x00000140 0x10 THUMB Debug/../../obj/stm32f10x_iwdg.o
- .ARM.attributes
- 0x00000150 0x10 THUMB Debug/../../obj/stm32f10x_pwr.o
- .ARM.attributes
- 0x00000160 0x10 THUMB Debug/../../obj/stm32f10x_rcc.o
- .ARM.attributes
- 0x00000170 0x10 THUMB Debug/../../obj/stm32f10x_rtc.o
- .ARM.attributes
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diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/bin/demoprog_olimex_stm32p103.srec b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/bin/demoprog_olimex_stm32p103.srec
index e474f8f6..a37f2bd8 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/bin/demoprog_olimex_stm32p103.srec
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diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/readme.txt b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/readme.txt
index a49767fb..a10a52ca 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/readme.txt
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/readme.txt
@@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
-Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
+Rowleys CrossWorks (version 3.7.6) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/stm32f103_crossworks.hzp b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/stm32f103_crossworks.hzp
index 610b7fda..f76e82fb 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/stm32f103_crossworks.hzp
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/stm32f103_crossworks.hzp
@@ -1,100 +1,146 @@
-
-
+
+
-
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-
-
-
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+
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-
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-
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+
+
+
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-
-
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-
-
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+
+
+
@@ -102,9 +148,30 @@
-
-
-
-
-
+
+
+
+
+
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/stm32f103_crossworks.hzs b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/stm32f103_crossworks.hzs
index e1fdd913..29ca23fd 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/stm32f103_crossworks.hzs
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/ide/stm32f103_crossworks.hzs
@@ -1,19 +1,22 @@
-
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@@ -23,16 +26,16 @@
-
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@@ -51,7 +54,7 @@
-
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-
+
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c
deleted file mode 100644
index 56fddc52..00000000
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c
+++ /dev/null
@@ -1,784 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.c
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
- mrs r0, psp
- bx lr
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
- msr psp, r0
- bx lr
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
- mrs r0, msp
- bx lr
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
- msr msp, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
- clrex
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t __get_BASEPRI(void)
-{
- mrs r0, basepri
- bx lr
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
- msr basepri, r0
- bx lr
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
- mrs r0, primask
- bx lr
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
- msr primask, r0
- bx lr
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t __get_FAULTMASK(void)
-{
- mrs r0, faultmask
- bx lr
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
- msr faultmask, r0
- bx lr
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
- mrs r0, control
- bx lr
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
- msr control, r0
- bx lr
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- __ASM("mrs r0, psp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM("msr psp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- __ASM("mrs r0, msp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM("msr msp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- __ASM("rev16 r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- __ASM("rbit r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- __ASM("ldrexb r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- __ASM("ldrexh r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- __ASM("ldrex r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- __ASM("strexb r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- __ASM("strexh r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- __ASM("strex r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, psp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, msp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- uint8_t result=0;
-
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- uint16_t result=0;
-
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h
index 2b6b51a7..efac390f 100644
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h
@@ -1,16 +1,16 @@
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V1.30
- * @date 30. October 2009
+ * @version V3.00
+ * @date 03. February 2012
*
* @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -20,1618 +20,1354 @@
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
-
-#ifndef __CM3_CORE_H__
-#define __CM3_CORE_H__
-
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
- *
- * List of Lint messages which will be suppressed and not shown:
- * - Error 10: \n
- * register uint32_t __regBasePri __asm("basepri"); \n
- * Error 10: Expecting ';'
- * .
- * - Error 530: \n
- * return(__regBasePri); \n
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized
- * .
- * - Error 550: \n
- * __regBasePri = (basePri & 0x1ff); \n
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed
- * .
- * - Error 754: \n
- * uint32_t RESERVED0[24]; \n
- * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced
- * .
- * - Error 750: \n
- * #define __CM3_CORE_H__ \n
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
- * .
- * - Error 528: \n
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
- * .
- * - Error 751: \n
- * } InterruptType_Type; \n
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
- * .
- * Note: To re-enable a Message, insert a space before 'lint' *
- *
- */
-
-/*lint -save */
-/*lint -e10 */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core registers and bitfields
- - Cortex-M core peripheral base address
- @{
- */
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
#ifdef __cplusplus
extern "C" {
-#endif
-
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex core */
-
-#include /* Include standard types */
-
-#if defined (__ICCARM__)
- #include /* IAR Intrinsics */
#endif
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
-#ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
-#endif
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
*/
-#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
-#else
- #define __I volatile const /*!< defines 'read only' permissions */
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ /* add preprocessor checks */
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
/*******************************************************************************
* Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
******************************************************************************/
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
- @{
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
*/
-
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
@{
*/
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
typedef struct
{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
-} NVIC_Type;
-/*@}*/ /* end of group CMSIS_CM3_NVIC */
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
- memory mapped structure for System Control Block (SCB)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
@{
*/
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
typedef struct
{
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
-} SCB_Type;
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-/* SCB Interrupt Control State Register Definitions */
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Registers Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Registers Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-/*@}*/ /* end of group CMSIS_CM3_SCB */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
- memory mapped structure for SysTick
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
typedef struct
{
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
- memory mapped structure for Instrumentation Trace Macrocell (ITM)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
typedef struct
{
- __O union
+ __O union
{
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
-} ITM_Type;
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+} ITM_Type;
/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-/*@}*/ /* end of group CMSIS_CM3_ITM */
+/*@}*/ /* end of group CMSIS_ITM */
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
- memory mapped structure for Interrupt Type
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
typedef struct
{
- uint32_t RESERVED0;
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
-#else
- uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
-/* Interrupt Controller Type Register Definitions */
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-/* Auxiliary Control Register Definitions */
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
- memory mapped structure for Memory Protection Unit (MPU)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
@{
*/
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
typedef struct
{
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-/*@}*/ /* end of group CMSIS_CM3_MPU */
+/*@} end of group CMSIS_MPU */
#endif
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
- memory mapped structure for Core Debug Register
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
@{
*/
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
typedef struct
{
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register */
#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
-/*@}*/ /* end of group CMSIS_CM3_core_register */
+/*@} */
+
/*******************************************************************************
* Hardware Abstraction Layer
- ******************************************************************************/
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq __enable_fiq
-#define __disable_fault_irq __disable_fiq
-
-#define __NOP __nop
-#define __WFI __wfi
-#define __WFE __wfe
-#define __SEV __sev
-#define __ISB() __isb(0)
-#define __DSB() __dsb(0)
-#define __DMB() __dmb(0)
-#define __REV __rev
-#define __RBIT __rbit
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
-#define __STREXB(value, ptr) __strex(value, ptr)
-#define __STREXH(value, ptr) __strex(value, ptr)
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-extern void __CLREX(void);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else /* (__ARMCC_VERSION >= 400000) */
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#define __CLREX __clrex
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-static __INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & 1);
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
-
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
-static __INLINE void __WFI() { __ASM ("wfi"); }
-static __INLINE void __WFE() { __ASM ("wfe"); }
-static __INLINE void __SEV() { __ASM ("sev"); }
-static __INLINE void __CLREX() { __ASM ("clrex"); }
-
-/* intrinsic void __ISB(void) */
-/* intrinsic void __DSB(void) */
-/* intrinsic void __DMB(void) */
-/* intrinsic void __set_PRIMASK(); */
-/* intrinsic void __get_PRIMASK(); */
-/* intrinsic void __set_FAULTMASK(); */
-/* intrinsic void __get_FAULTMASK(); */
-/* intrinsic uint32_t __REV(uint32_t value); */
-/* intrinsic uint32_t __REVSH(uint32_t value); */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
-/* intrinsic unsigned long __LDREX(unsigned long *); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __NOP() { __ASM volatile ("nop"); }
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }
-static __INLINE void __SEV() { __ASM volatile ("sev"); }
-static __INLINE void __ISB() { __ASM volatile ("isb"); }
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
- Core Function Interface containing:
+ Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- - Core Reset Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
-/*@{*/
+
+
/* ########################## NVIC functions #################################### */
-
-/**
- * @brief Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param PriorityGroup is priority grouping field
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
*/
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
-
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
-/**
- * @brief Get the Priority Grouping from NVIC Interrupt Controller
- *
- * @return priority grouping field
- *
- * Get the priority grouping from NVIC Interrupt Controller.
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
}
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- *
- * @param IRQn The positive number of the external interrupt to enable
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
}
-/**
- * @brief Disable the interrupt line for external interrupt specified
- *
- * @param IRQn The positive number of the external interrupt to disable
- *
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
}
-/**
- * @brief Read the interrupt pending bit for a device specific interrupt source
- *
- * @param IRQn The number of the device specifc interrupt
- * @return 1 = interrupt pending, 0 = interrupt not pending
- *
- * Read the pending register in NVIC and return 1 if its status is pending,
- * otherwise it returns 0
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
*/
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
}
-/**
- * @brief Set the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for set pending
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
}
-/**
- * @brief Clear the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for clear pending
- *
- * Clear the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
-/**
- * @brief Read the active bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for read active bit
- * @return 1 = interrupt active, 0 = interrupt not active
- *
- * Read the active register in NVIC and returns 1 if its status is active,
- * otherwise it returns 0.
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
*/
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
}
-/**
- * @brief Set the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for set priority
- * @param priority The priority to set
- *
- * Set the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * Note: The priority cannot be set for every core interrupt.
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
*/
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
else {
NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
}
-/**
- * @brief Read the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for get priority
- * @return The priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
*/
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
else {
return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
-/**
- * @brief Encode the priority for an interrupt
- *
- * @param PriorityGroup The used priority group
- * @param PreemptPriority The preemptive priority value (starting from 0)
- * @param SubPriority The sub priority value (starting from 0)
- * @return The encoded priority for the interrupt
- *
- * Encode the priority for an interrupt with the given priority group,
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The returned priority value can be used for NVIC_SetPriority(...) function
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
@@ -1639,7 +1375,7 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
+
return (
((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
((SubPriority & ((1 << (SubPriorityBits )) - 1)))
@@ -1647,22 +1383,19 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
}
-/**
- * @brief Decode the priority of an interrupt
- *
- * @param Priority The priority for the interrupt
- * @param PriorityGroup The used priority group
- * @param pPreemptPriority The preemptive priority value (starting from 0)
- * @param pSubPriority The sub priority value (starting from 0)
- *
- * Decode an interrupt priority value with the given priority group to
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The priority value can be retrieved with NVIC_GetPriority(...) function
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
*/
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
@@ -1670,132 +1403,134 @@ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
+
*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
}
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
/* ################################## SysTick function ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/**
- * @brief Initialize and start the SysTick counter and its interrupt.
- *
- * @param ticks number of ticks between two interrupts
- * @return 1 = failed, 0 = successful
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate
- * periodical interrupts.
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
*/
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
+
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
-
-
-
-/* ################################## Reset function ############################################ */
-
-/**
- * @brief Initiate a system reset request.
- *
- * Initiate a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
+/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
-
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
- Core Debug Interface containing:
- - Core Debug Receive / Transmit Functions
- - Core Debug Defines
- - Core Debug Variables
-*/
-/*@{*/
-
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/**
- * @brief Outputs a character via the ITM channel 0
- *
- * @param ch character to output
- * @return character to output
- *
- * The function outputs a character via the ITM channel 0.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
*/
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0].u32 == 0);
ITM->PORT[0].u8 = (uint8_t) ch;
- }
+ }
return (ch);
}
-/**
- * @brief Inputs a character via variable ITM_RxBuffer
- *
- * @return received character, -1 = no character received
- *
- * The function inputs a character via variable ITM_RxBuffer.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
*/
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
-
- return (ch);
+
+ return (ch);
}
-/**
- * @brief Check if a character via variable ITM_RxBuffer is available
- *
- * @return 1 = character available, 0 = no character available
- *
- * The function checks variable ITM_RxBuffer whether a character is available or not.
- * The function returns '1' if a character is available and '0' if no character is available.
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
*/
-static __INLINE int ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
@@ -1804,15 +1539,12 @@ static __INLINE int ITM_CheckChar (void) {
}
}
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
+/*@} end of CMSIS_core_DebugFunctions */
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */
-
-#endif /* __CM3_CORE_H__ */
-
-/*lint -restore */
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cmFunc.h b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cmFunc.h
new file mode 100644
index 00000000..adb07b5d
--- /dev/null
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cmFunc.h
@@ -0,0 +1,616 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cmInstr.h b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cmInstr.h
new file mode 100644
index 00000000..624c175f
--- /dev/null
+++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cmInstr.h
@@ -0,0 +1,618 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+
+ __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
+ return(op1);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint8_t result;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint16_t result;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint8_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CMSIS debug support.htm b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CMSIS debug support.htm
deleted file mode 100644
index efda685b..00000000
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CMSIS debug support.htm
+++ /dev/null
@@ -1,243 +0,0 @@
-
-
-
-CMSIS Debug Support
-
-
-
-
-
-
-
-
-
CMSIS Debug Support
-
-
-
-
Cortex-M3 ITM Debug Access
-
- The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
- the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
- 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
- communication channels are used by CMSIS to output the following information:
-
-
-
ITM Channel 0: used for printf-style output via the debug interface.
-
ITM Channel 31: is reserved for RTOS kernel awareness debugging.
-
-
-
Debug IN / OUT functions
-
CMSIS provides following debug functions:
-
-
ITM_SendChar (uses ITM channel 0)
-
ITM_ReceiveChar (uses global variable)
-
ITM_CheckChar (uses global variable)
-
-
-
ITM_SendChar
-
- ITM_SendChar is used to transmit a character over ITM channel 0 from
- the microcontroller system to the debug system.
- Only a 8 bit value is transmitted.
-
- ITM communication channel is only capable for OUT direction. For IN direction
- a globel variable is used. A simple mechansim detects if a character is received.
- The project to test need to be build with debug information.
-
-
-
- The globale variable ITM_RxBuffer is used to transmit a 8 bit value from debug system
- to microcontroller system. ITM_RxBuffer is 32 bit wide to enshure a proper handshake.
-
-
-extern volatile int ITM_RxBuffer; /* variable to receive characters */
-
-
- A dedicated bit pattern is used to determin if ITM_RxBuffer is empty
- or contains a valid value.
-
-
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
-
-
- ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking.
- It returns the received character or '-1' if no character was available.
-
-
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-
ITM_CheckChar
-
- ITM_CheckChar is used to check if a character is received.
-
-
-static __INLINE int ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-
-
ITM Debug Support in uVision
-
- uVision uses in a debug session the Debug (printf) Viewer window to
- display the debug data.
-
-
Direction microcontroller system -> uVision:
-
-
- Characters received via ITM communication channel 0 are written in a printf style
- to Debug (printf) Viewer window.
-
-
-
-
Direction uVision -> microcontroller system:
-
-
Check if ITM_RxBuffer variable is available (only performed once).
-
Read character from Debug (printf) Viewer window.
-
If ITM_RxBuffer empty write character to ITM_RxBuffer.
-
-
-
Note
-
-
Current solution does not use a buffer machanism for trasmitting the characters.
-
-
-
-
RTX Kernel awareness in uVision
-
- uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
- No format overhead is necessary.
- uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
- to ITM communication channel 31.
-
-
-
Following RTX events are traced:
-
-
Task Create / Delete event
-
-
32 bit access. Task start address is transmitted
-
16 bit access. Task ID and Create/Delete flag are transmitted
- High byte holds Create/Delete flag, Low byte holds TASK ID.
-
-
-
-
Task switch event
-
-
8 bit access. Task ID of current task is transmitted
-
-
-
-
-
Note
-
-
Other RTOS information could be retrieved via memory read access in a polling mode manner.
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CMSIS_changes.htm b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CMSIS_changes.htm
deleted file mode 100644
index 162ffcc9..00000000
--- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_Crossworks/Prog/lib/stdperiphlib/CMSIS/CMSIS_changes.htm
+++ /dev/null
@@ -1,320 +0,0 @@
-
-
-
-CMSIS Changes
-
-
-
-
-
-
-
-
-
Changes to CMSIS version V1.20
-
-
-
-
1. Removed CMSIS Middelware packages
-
- CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
-
-
-
2. SystemFrequency renamed to SystemCoreClock
-
- The variable name SystemCoreClock is more precise than SystemFrequency
- because the variable holds the clock value at which the core is running.
-
-
-
3. Changed startup concept
-
- The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
- from main) has the weakness that it does not work for controllers which need a already
- configuerd clock system to configure the external memory controller.
-
-
-
Changed startup concept
-
-
- SystemInit() is called from startup file before premain.
-
-
- SystemInit() configures the clock system and also configures
- an existing external memory controller.
-
-
- SystemInit() must not use global variables.
-
-
- SystemCoreClock is initialized with a correct predefined value.
-
-
- Additional function void SystemCoreClockUpdate (void) is provided.
- SystemCoreClockUpdate() updates the variable SystemCoreClock
- and must be called whenever the core clock is changed.
- SystemCoreClockUpdate() evaluates the clock register settings and calculates
- the current core clock.
-
-
-
-
-
4. Advanced Debug Functions
-
- ITM communication channel is only capable for OUT direction. To allow also communication for
- IN direction a simple concept is provided.
-
-
-
- Global variable volatile int ITM_RxBuffer used for IN data.
-
-
- Function int ITM_CheckChar (void) checks if a new character is available.
-
-
- Function int ITM_ReceiveChar (void) retrieves the new character.
-
-
-
-
- For detailed explanation see file CMSIS debug support.htm.
-
-
-
-
5. Core Register Bit Definitions
-
- Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
- defines correspond with the Cortex-M Technical Reference Manual.
-
Update product define: replace "#define STM32F4XX" by "#define
-STM32F40XX" for STM32F40x/41x devices
Add new product define: "#define
-STM32F427X" for STM32F427x/437x devices.
Add new startup files "startup_stm32f427x.s"for
-all toolchains
rename startup files "startup_stm32f4xx.s" by "startup_stm32f40xx.s"for
-all toolchains
-
system_stm32f4xx.c
Prefetch Buffer enabled
Add reference to STM32F427x/437x devices and STM324x7I_EVAL board
SystemInit_ExtMemCtl() function
-
Add configuration of missing FSMC address and data lines
-
Change memory type to SRAM instead of PSRAM (PSRAM is available only on STM324xG-EVAL RevA) and update timing values
V1.0.2 / 05-March-2012
-
Main
-Changes
-
-
All source files: license disclaimer text update and add link to the License file on ST Internet.
V1.0.1 / 28-December-2011
Main
-Changes
-
All source files: update disclaimer to add reference to the new license agreement
stm32f4xx.h
Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST
V1.0.0 / 30-September-2011
Main
-Changes
-
First official release for STM32F40x/41x devices
Add startup file for TASKING toolchain
system_stm32f4xx.c: driver's comments update
V1.0.0RC2 / 26-September-2011
Main
-Changes
-
Official version (V1.0.0) Release Candidate2 for STM32F40x/41x devices
stm32f4xx.h
Add define for Cortex-M4 revision __CM4_REV
Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000
Correct some bits definition to be in line with naming used in the Reference Manual (RM0090)
GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x
GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x
SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL
RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST
DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
PWR_CR_PMODE changed to PWR_CR_VOS
PWR_CSR_REGRDY changed to PWR_CSR_VOSRDY
Add new define RCC_AHB1ENR_CCMDATARAMEN
Add new defines SRAM2_BASE, CCMDATARAM_BASE and BKPSRAM_BASE
GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28
system_stm32f4xx.c
SystemInit(): add code to enable the FPU
SetSysClock(): change PWR_CR_PMODE by PWR_CR_VOS
SystemInit_ExtMemCtl(): remove commented values
startup (for all compilers)
Delete code used to enable the FPU (moved to system_stm32f4xx.c file)
File’s header updated
V1.0.0RC1 / 25-August-2011
Main
-Changes
-
Official version (V1.0.0) Release Candidate1 for STM32F4xx devices
-
-
-
-
License
-
-
-
Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:
Unless
-required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
-the License for the specific language governing permissions and
-limitations under the License.
-
-
-
For
-complete documentation on STM32 Microcontrollers
-visit www.st.com/STM32
-
-
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c
deleted file mode 100644
index 1be82e03..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c
+++ /dev/null
@@ -1,561 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f4xx.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 24-May-2013
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
- * This file contains the system clock configuration for STM32F4xx devices,
- * and is generated by the clock configuration tool
- * stm32f4xx_Clock_Configuration_V1.1.0.xls
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
- * and Divider factors, AHB/APBx prescalers and Flash settings),
- * depending on the configuration made in the clock xls tool.
- * This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f4xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (16 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. If the system clock source selected by user fails to startup, the SystemInit()
- * function will do nothing and HSI still used as system clock source. User can
- * add some code to deal with this issue inside the SetSysClock() function.
- *
- * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
- * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
- * through PLL, and you are using different crystal you have to adapt the HSE
- * value to your own configuration.
- *
- * 5. This file configures the system clock as follows:
- *=============================================================================
- *=============================================================================
- * Supported STM32F40xx/41xx/427x/437x devices
- *-----------------------------------------------------------------------------
- * System Clock source | PLL (HSE)
- *-----------------------------------------------------------------------------
- * SYSCLK(Hz) | 168000000
- *-----------------------------------------------------------------------------
- * HCLK(Hz) | 168000000
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB1 Prescaler | 4
- *-----------------------------------------------------------------------------
- * APB2 Prescaler | 2
- *-----------------------------------------------------------------------------
- * HSE Frequency(Hz) | 12000000
- *-----------------------------------------------------------------------------
- * PLL_M | 12
- *-----------------------------------------------------------------------------
- * PLL_N | 336
- *-----------------------------------------------------------------------------
- * PLL_P | 2
- *-----------------------------------------------------------------------------
- * PLL_Q | 7
- *-----------------------------------------------------------------------------
- * PLLI2S_N | NA
- *-----------------------------------------------------------------------------
- * PLLI2S_R | NA
- *-----------------------------------------------------------------------------
- * I2S input clock | NA
- *-----------------------------------------------------------------------------
- * VDD(V) | 3,3
- *-----------------------------------------------------------------------------
- * Main regulator output voltage | Scale1 mode
- *-----------------------------------------------------------------------------
- * Flash Latency(WS) | 5
- *-----------------------------------------------------------------------------
- * Prefetch Buffer | OFF
- *-----------------------------------------------------------------------------
- * Instruction cache | ON
- *-----------------------------------------------------------------------------
- * Data cache | ON
- *-----------------------------------------------------------------------------
- * Require 48MHz for USB OTG FS, | Enabled
- * SDIO and RNG clock |
- *-----------------------------------------------------------------------------
- *=============================================================================
- ******************************************************************************
- * @attention
- *
- *
STM32F4xx
- Standard Peripherals Drivers update History
V1.1.0 / 11-Janury-2013
Main
-Changes
-
-
Official release for STM32F427x/437x devices.
stm32f4xx_cryp.c/.h
Update CRYP_Init() function : add the support for new algorithms (GCM/CCM).
Add new function : CRYP_PhaseConfig() used for new AES-GCM and AES-CCM algorithms.
CRYP_InitTypeDef structure : update all structure fields from uint16_t to uint32_t and update all driver functions parameters and the correpondant define to be declared with uint32_t type.
Replace the "CRYP_ContextSave->CR_bits9to2" by "CRYP_ContextSave->CurrentConfig".
stm32f4xx_flash.c/.h
Update FLASH sectors numbers "FLASH_Sector_x" with x = 0..23.
Update FLASH_EraseAllSectors() function to support mass erase for STM32F427x/437x devices.
stm32f4xx_gpio.c/.h
Add Alternate functions for new peripherals: SPI4, SPI5, SPI6, UART7, UART8.
Update all functions header
-comment.
stm32f4xx_hash.c/.h
Update HASH_GetDigest() function : add the HASH_DIGEST structure.
Add new function HASH_AutoStartDigest().
Update HASH_MsgDigest structure: to support SHA-224 and SHA-256 modes.
Update HASH_Context structure.
Update some define using bit definitions already declared in stm32f4xx.h.
stm32f'xx_i2c.c/.h
Add new functions:
I2C_AnalogFilterCmd(): enable/disable the analog I2C filters.
I2C_DigitalFilterConfig(): configure the digital I2C filters.
stm32f4xx_pwr.c/.h
-
Add new argument "PWR_Regulator_Voltage_Scale3"
- to PWR_MainRegulatorModeConfig() function to be in line with
- Reference Manual description.
stm32f4xx_rcc.c/.h
Add new definitions for new
-peripherals: SPI4, SPI5, SPI6,SAI1, UART7, UART8.
Add a new parameter in RCC_PLLI2SConfig() function : PLLI2SQ to specifies the division factor for SAI1 clock.
Add RCC_TIMCLKPresConfig() function : TIMER Prescaler selection.
stm32l1xx_spi.c/.h
Update to support SPI4, SPI5, SPI6.
-
Update all functions header
-comment.
stm32l1xx_usart.c/.h
Update to support UART7 and
-UART8.
-
Update all functions header
-comment.
V1.0.2 / 05-March-2012
-
Main
-Changes
-
-
All source files: license disclaimer text update and add link to the License file on ST Internet.
stm32f4xx_dcmi.c
DCMI_GetFlagStatus() function: fix test condition on RISR register, use if (dcmireg == 0x00) instead of if (dcmireg == 0x01)
stm32f4xx_pwr.c
PWR_PVDLevelConfig()
-function: remove value of the voltage threshold corresponding to each
-PVD detection level, user should refer to the electrical
-characteristics of the STM32 device datasheet to have the correct
-value
V1.0.1 / 28-December-2011
Main
-Changes
-
All source files: update disclaimer to add reference to the new license agreement
stm32f4xx_rtc.c:
In “RTC_FLAGS_MASK” define: add RTC_FLAG_RECALPF and RTC_FLAG_SHPF
RTC_DeInit() function: add reset of the following registers: SHIFTR, CALR, ALRMASSR and ALRMBSSR
RTC_SetTime() and RTC_SetDate() functions: add test condition on BYPSHAD flag before to test RSF flag (when Bypass mode is enabled, the RSF bit is never set).
V1.0.0 / 30-September-2011
Main
-Changes
-
First official release for STM32F40x/41x devices
stm32f4xx_rtc.c: remove useless code from RTC_GetDate() function
stm32f4xx_rcc.c, stm32f4xx_spi.c, stm32f4xx_wwdg.c and stm32f4xx_syscfg.c: driver's comments update
V1.0.0RC2 / 26-September-2011
Main
-Changes
-
Official version (V1.0.0) Release Candidate1for STM32F40x/STM32F41x devices
stm32f4xx_usart.h/.c
Update procedure to check on overrun error interrupt pending bit, defines for the following flag are added:
USART_IT_ORE_RX: this flag is set if overrun error interrupt occurs and RXNEIE bit is set
USART_IT_ORE_ER:this flag is set if overrun error interrupt occurs and EIE bit is set
stm32f4xx_tim.c
TIM_UpdateRequestConfig(): correct function header's comment
TIM_ICInit(): add assert macros to test if the passed TIM parameter has channel 2, 3 or 4
stm32f4xx_pwr.h/.c
Rename PWR_FLAG_REGRDY constant to PWR_CSR_REGRDY
Rename PWR_FLAG_VOSRDY constant to PWR_CSR_VOSRDY
Rename PWR_HighPerformanceModeCmd(FunctionalState NewState) function to PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
stm32f4xx_rcc.h/.c
RCC_AHB1PeriphClockCmd(): add new constant RCC_AHB1Periph_CCMDATARAMEN as value for RCC_AHB1Periph parameter
stm32f4xx_spi.h
IS_I2S_EXT_PERIPH(): add check on I2S3ext peripheral
V1.0.0RC1 / 25-August-2011
Main
-Changes
-
Official version (V1.0.0) Release Candidate1 for STM32F4xx devices
-
License
-
-
-
Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:
Unless
-required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
-the License for the specific language governing permissions and
-limitations under the License.
-
-
-
-
For
- complete documentation on STM32
- Microcontrollers visit www.st.com/STM32
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/misc.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/misc.h
deleted file mode 100644
index dec96ec2..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/misc.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/**
- ******************************************************************************
- * @file misc.h
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file contains all the functions prototypes for the miscellaneous
- * firmware library functions (add-on to CMSIS functions).
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FSMC_H
-#define __STM32F4xx_FSMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FSMC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief Timing parameters For NOR/SRAM Banks
- */
-typedef struct
-{
- uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
- This parameter can be a value between 0 and 0xF.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address hold time.
- This parameter can be a value between 0 and 0xF.
- @note This parameter is not used with synchronous NOR Flash memories.*/
-
- uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the data setup time.
- This parameter can be a value between 0 and 0xFF.
- @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
-
- uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
- the duration of the bus turnaround.
- This parameter can be a value between 0 and 0xF.
- @note This parameter is only used for multiplexed NOR Flash memories. */
-
- uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
- This parameter can be a value between 1 and 0xF.
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
-
- uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
- to the memory before getting the first data.
- The parameter value depends on the memory type as shown below:
- - It must be set to 0 in case of a CRAM
- - It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between 0 and 0xF in NOR Flash memories
- with synchronous burst mode enable */
-
- uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FSMC_Access_Mode */
-}FSMC_NORSRAMTimingInitTypeDef;
-
-/**
- * @brief FSMC NOR/SRAM Init structure definition
- */
-typedef struct
-{
- uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */
-
- uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the data bus or not.
- This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
- uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
- the corresponding memory bank.
- This parameter can be a value of @ref FSMC_Memory_Type */
-
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FSMC_Data_Width */
-
- uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
- valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FSMC_Burst_Access_Mode */
-
- uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
- valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FSMC_AsynchronousWait */
-
- uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
- the Flash memory in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
-
- uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
- memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FSMC_Wrap_Mode */
-
- uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
- clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Timing */
-
- uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
- This parameter can be a value of @ref FSMC_Write_Operation */
-
- uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
- signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal */
-
- uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FSMC_Extended_Mode */
-
- uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FSMC_Write_Burst */
-
- FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/
-
- FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/
-}FSMC_NORSRAMInitTypeDef;
-
-/**
- * @brief Timing parameters For FSMC NAND and PCCARD Banks
- */
-typedef struct
-{
- uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
- the command assertion for NAND Flash read or write access
- to common/Attribute or I/O memory space (depending on
- the memory space timing to be configured).
- This parameter can be a value between 0 and 0xFF.*/
-
- uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
- command for NAND Flash read or write access to
- common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-
- uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
- (and data for write access) after the command de-assertion
- for NAND Flash read or write access to common/Attribute
- or I/O memory space (depending on the memory space timing
- to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-
- uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
- data bus is kept in HiZ after the start of a NAND Flash
- write access to common/Attribute or I/O memory space (depending
- on the memory space timing to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-}FSMC_NAND_PCCARDTimingInitTypeDef;
-
-/**
- * @brief FSMC NAND Init structure definition
- */
-typedef struct
-{
- uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
- This parameter can be a value of @ref FSMC_NAND_Bank */
-
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FSMC_Data_Width */
-
- uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FSMC_ECC */
-
- uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FSMC_ECC_Page_Size */
-
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 0xFF. */
-
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0x0 and 0xFF */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-}FSMC_NANDInitTypeDef;
-
-/**
- * @brief FSMC PCCARD Init structure definition
- */
-
-typedef struct
-{
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 0xFF. */
-
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0x0 and 0xFF */
-
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
-}FSMC_PCCARDInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FSMC_Exported_Constants
- * @{
- */
-
-/** @defgroup FSMC_NORSRAM_Bank
- * @{
- */
-#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
-#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
-#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
-#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_Bank
- * @{
- */
-#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
-#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCCARD_Bank
- * @{
- */
-#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
-/**
- * @}
- */
-
-#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
- ((BANK) == FSMC_Bank1_NORSRAM2) || \
- ((BANK) == FSMC_Bank1_NORSRAM3) || \
- ((BANK) == FSMC_Bank1_NORSRAM4))
-
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND))
-
-#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND) || \
- ((BANK) == FSMC_Bank4_PCCARD))
-
-#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND) || \
- ((BANK) == FSMC_Bank4_PCCARD))
-
-/** @defgroup FSMC_NOR_SRAM_Controller
- * @{
- */
-
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing
- * @{
- */
-
-#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
-#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
-#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
- ((MUX) == FSMC_DataAddressMux_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Memory_Type
- * @{
- */
-
-#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
-#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
-#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
-#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
- ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
- ((MEMORY) == FSMC_MemoryType_NOR))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Width
- * @{
- */
-
-#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
-#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
-#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
- ((WIDTH) == FSMC_MemoryDataWidth_16b))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Burst_Access_Mode
- * @{
- */
-
-#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
-#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
-#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
- ((STATE) == FSMC_BurstAccessMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_AsynchronousWait
- * @{
- */
-#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
-#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
-#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
- ((STATE) == FSMC_AsynchronousWait_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal_Polarity
- * @{
- */
-#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
-#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
-#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
- ((POLARITY) == FSMC_WaitSignalPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wrap_Mode
- * @{
- */
-#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
-#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
-#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
- ((MODE) == FSMC_WrapMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Timing
- * @{
- */
-#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
-#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
- ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Operation
- * @{
- */
-#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
-#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
-#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
- ((OPERATION) == FSMC_WriteOperation_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal
- * @{
- */
-#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
-#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
-#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
- ((SIGNAL) == FSMC_WaitSignal_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Extended_Mode
- * @{
- */
-#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
-#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
-
-#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
- ((MODE) == FSMC_ExtendedMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Burst
- * @{
- */
-
-#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
-#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
-#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
- ((BURST) == FSMC_WriteBurst_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Setup_Time
- * @{
- */
-#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Hold_Time
- * @{
- */
-#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Setup_Time
- * @{
- */
-#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Bus_Turn_around_Duration
- * @{
- */
-#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_CLK_Division
- * @{
- */
-#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Latency
- * @{
- */
-#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Access_Mode
- * @{
- */
-#define FSMC_AccessMode_A ((uint32_t)0x00000000)
-#define FSMC_AccessMode_B ((uint32_t)0x10000000)
-#define FSMC_AccessMode_C ((uint32_t)0x20000000)
-#define FSMC_AccessMode_D ((uint32_t)0x30000000)
-#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
- ((MODE) == FSMC_AccessMode_B) || \
- ((MODE) == FSMC_AccessMode_C) || \
- ((MODE) == FSMC_AccessMode_D))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_PCCARD_Controller
- * @{
- */
-
-/** @defgroup FSMC_Wait_feature
- * @{
- */
-#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
-#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
- ((FEATURE) == FSMC_Waitfeature_Enable))
-/**
- * @}
- */
-
-
-/** @defgroup FSMC_ECC
- * @{
- */
-#define FSMC_ECC_Disable ((uint32_t)0x00000000)
-#define FSMC_ECC_Enable ((uint32_t)0x00000040)
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
- ((STATE) == FSMC_ECC_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_ECC_Page_Size
- * @{
- */
-#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
-#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
-#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
-#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
-#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
-#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_8192Bytes))
-/**
- * @}
- */
-
-/** @defgroup FSMC_TCLR_Setup_Time
- * @{
- */
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_TAR_Setup_Time
- * @{
- */
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Setup_Time
- * @{
- */
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Setup_Time
- * @{
- */
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Hold_Setup_Time
- * @{
- */
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_HiZ_Setup_Time
- * @{
- */
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Interrupt_sources
- * @{
- */
-#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
-#define FSMC_IT_Level ((uint32_t)0x00000010)
-#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
-#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
- ((IT) == FSMC_IT_Level) || \
- ((IT) == FSMC_IT_FallingEdge))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Flags
- * @{
- */
-#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
-#define FSMC_FLAG_Level ((uint32_t)0x00000002)
-#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
-#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
-#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
- ((FLAG) == FSMC_FLAG_Level) || \
- ((FLAG) == FSMC_FLAG_FallingEdge) || \
- ((FLAG) == FSMC_FLAG_FEMPT))
-
-#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* NOR/SRAM Controller functions **********************************************/
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-
-/* NAND Controller functions **************************************************/
-void FSMC_NANDDeInit(uint32_t FSMC_Bank);
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
-
-/* PCCARD Controller functions ************************************************/
-void FSMC_PCCARDDeInit(void);
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_PCCARDCmd(FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_FSMC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h
deleted file mode 100644
index 0cf96c5b..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h
+++ /dev/null
@@ -1,423 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_gpio.h
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file contains all the functions prototypes for the GPIO firmware
- * library.
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_I2C_H
-#define __STM32F4xx_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief I2C Init structure definition
- */
-
-typedef struct
-{
- uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
- This parameter must be set to a value lower than 400kHz */
-
- uint16_t I2C_Mode; /*!< Specifies the I2C mode.
- This parameter can be a value of @ref I2C_mode */
-
- uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
- This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
- uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
- This parameter can be a value of @ref I2C_acknowledgement */
-
- uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
- This parameter can be a value of @ref I2C_acknowledged_address */
-}I2C_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup I2C_Exported_Constants
- * @{
- */
-
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
- ((PERIPH) == I2C2) || \
- ((PERIPH) == I2C3))
-
-/** @defgroup I2C_Digital_Filter
- * @{
- */
-
-#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
-/**
- * @}
- */
-
-
-/** @defgroup I2C_mode
- * @{
- */
-
-#define I2C_Mode_I2C ((uint16_t)0x0000)
-#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
-#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
- ((MODE) == I2C_Mode_SMBusDevice) || \
- ((MODE) == I2C_Mode_SMBusHost))
-/**
- * @}
- */
-
-/** @defgroup I2C_duty_cycle_in_fast_mode
- * @{
- */
-
-#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
-#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
- ((CYCLE) == I2C_DutyCycle_2))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledgement
- * @{
- */
-
-#define I2C_Ack_Enable ((uint16_t)0x0400)
-#define I2C_Ack_Disable ((uint16_t)0x0000)
-#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
- ((STATE) == I2C_Ack_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2C_transfer_direction
- * @{
- */
-
-#define I2C_Direction_Transmitter ((uint8_t)0x00)
-#define I2C_Direction_Receiver ((uint8_t)0x01)
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
- ((DIRECTION) == I2C_Direction_Receiver))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledged_address
- * @{
- */
-
-#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
-#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
-/**
- * @}
- */
-
-/** @defgroup I2C_registers
- * @{
- */
-
-#define I2C_Register_CR1 ((uint8_t)0x00)
-#define I2C_Register_CR2 ((uint8_t)0x04)
-#define I2C_Register_OAR1 ((uint8_t)0x08)
-#define I2C_Register_OAR2 ((uint8_t)0x0C)
-#define I2C_Register_DR ((uint8_t)0x10)
-#define I2C_Register_SR1 ((uint8_t)0x14)
-#define I2C_Register_SR2 ((uint8_t)0x18)
-#define I2C_Register_CCR ((uint8_t)0x1C)
-#define I2C_Register_TRISE ((uint8_t)0x20)
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
- ((REGISTER) == I2C_Register_CR2) || \
- ((REGISTER) == I2C_Register_OAR1) || \
- ((REGISTER) == I2C_Register_OAR2) || \
- ((REGISTER) == I2C_Register_DR) || \
- ((REGISTER) == I2C_Register_SR1) || \
- ((REGISTER) == I2C_Register_SR2) || \
- ((REGISTER) == I2C_Register_CCR) || \
- ((REGISTER) == I2C_Register_TRISE))
-/**
- * @}
- */
-
-/** @defgroup I2C_NACK_position
- * @{
- */
-
-#define I2C_NACKPosition_Next ((uint16_t)0x0800)
-#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
-#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
- ((POSITION) == I2C_NACKPosition_Current))
-/**
- * @}
- */
-
-/** @defgroup I2C_SMBus_alert_pin_level
- * @{
- */
-
-#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
-#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
-#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
- ((ALERT) == I2C_SMBusAlert_High))
-/**
- * @}
- */
-
-/** @defgroup I2C_PEC_position
- * @{
- */
-
-#define I2C_PECPosition_Next ((uint16_t)0x0800)
-#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
-#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
- ((POSITION) == I2C_PECPosition_Current))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_BUF ((uint16_t)0x0400)
-#define I2C_IT_EVT ((uint16_t)0x0200)
-#define I2C_IT_ERR ((uint16_t)0x0100)
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
-#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
-#define I2C_IT_PECERR ((uint32_t)0x01001000)
-#define I2C_IT_OVR ((uint32_t)0x01000800)
-#define I2C_IT_AF ((uint32_t)0x01000400)
-#define I2C_IT_ARLO ((uint32_t)0x01000200)
-#define I2C_IT_BERR ((uint32_t)0x01000100)
-#define I2C_IT_TXE ((uint32_t)0x06000080)
-#define I2C_IT_RXNE ((uint32_t)0x06000040)
-#define I2C_IT_STOPF ((uint32_t)0x02000010)
-#define I2C_IT_ADD10 ((uint32_t)0x02000008)
-#define I2C_IT_BTF ((uint32_t)0x02000004)
-#define I2C_IT_ADDR ((uint32_t)0x02000002)
-#define I2C_IT_SB ((uint32_t)0x02000001)
-
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
-
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
- ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
- ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
- ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
- ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_flags_definition
- * @{
- */
-
-/**
- * @brief SR2 register flags
- */
-
-#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
-#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
-#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
-#define I2C_FLAG_TRA ((uint32_t)0x00040000)
-#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
-#define I2C_FLAG_MSL ((uint32_t)0x00010000)
-
-/**
- * @brief SR1 register flags
- */
-
-#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
-#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
-#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
-#define I2C_FLAG_OVR ((uint32_t)0x10000800)
-#define I2C_FLAG_AF ((uint32_t)0x10000400)
-#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
-#define I2C_FLAG_BERR ((uint32_t)0x10000100)
-#define I2C_FLAG_TXE ((uint32_t)0x10000080)
-#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
-#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
-#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
-#define I2C_FLAG_BTF ((uint32_t)0x10000004)
-#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
-#define I2C_FLAG_SB ((uint32_t)0x10000001)
-
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
-
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
- ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
- ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
- ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
- ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
- ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
- ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
- ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
- ((FLAG) == I2C_FLAG_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_Events
- * @{
- */
-
-/**
- ===============================================================================
- I2C Master Events (Events grouped in order of communication)
- ===============================================================================
- */
-
-/**
- * @brief Communication start
- *
- * After sending the START condition (I2C_GenerateSTART() function) the master
- * has to wait for this event. It means that the Start condition has been correctly
- * released on the I2C bus (the bus is free, no other devices is communicating).
- *
- */
-/* --EV5 */
-#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
-
-/**
- * @brief Address Acknowledge
- *
- * After checking on EV5 (start condition correctly released on the bus), the
- * master sends the address of the slave(s) with which it will communicate
- * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
- * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
- * his address. If an acknowledge is sent on the bus, one of the following events will
- * be set:
- *
- * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
- * event is set.
- *
- * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
- * is set
- *
- * 3) In case of 10-Bit addressing mode, the master (just after generating the START
- * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
- * function). Then master should wait on EV9. It means that the 10-bit addressing
- * header has been correctly sent on the bus. Then master should send the second part of
- * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
- * should wait for event EV6.
- *
- */
-
-/* --EV6 */
-#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
-#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
-/* --EV9 */
-#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
-
-/**
- * @brief Communication events
- *
- * If a communication is established (START condition generated and slave address
- * acknowledged) then the master has to check on one of the following events for
- * communication procedures:
- *
- * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
- * the data received from the slave (I2C_ReceiveData() function).
- *
- * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
- * function) then to wait on event EV8 or EV8_2.
- * These two events are similar:
- * - EV8 means that the data has been written in the data register and is
- * being shifted out.
- * - EV8_2 means that the data has been physically shifted out and output
- * on the bus.
- * In most cases, using EV8 is sufficient for the application.
- * Using EV8_2 leads to a slower communication but ensure more reliable test.
- * EV8_2 is also more suitable than EV8 for testing on the last data transmission
- * (before Stop condition generation).
- *
- * @note In case the user software does not guarantee that this event EV7 is
- * managed before the current byte end of transfer, then user may check on EV7
- * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Master RECEIVER mode -----------------------------*/
-/* --EV7 */
-#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
-
-/* Master TRANSMITTER mode --------------------------*/
-/* --EV8 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
-/* --EV8_2 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
-
-
-/**
- ===============================================================================
- I2C Slave Events (Events grouped in order of communication)
- ===============================================================================
- */
-
-
-/**
- * @brief Communication start events
- *
- * Wait on one of these events at the start of the communication. It means that
- * the I2C peripheral detected a Start condition on the bus (generated by master
- * device) followed by the peripheral address. The peripheral generates an ACK
- * condition on the bus (if the acknowledge feature is enabled through function
- * I2C_AcknowledgeConfig()) and the events listed above are set :
- *
- * 1) In normal case (only one address managed by the slave), when the address
- * sent by the master matches the own address of the peripheral (configured by
- * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
- * (where XXX could be TRANSMITTER or RECEIVER).
- *
- * 2) In case the address sent by the master matches the second address of the
- * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
- * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
- * (where XXX could be TRANSMITTER or RECEIVER) are set.
- *
- * 3) In case the address sent by the master is General Call (address 0x00) and
- * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
- * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
- *
- */
-
-/* --EV1 (all the events below are variants of EV1) */
-/* 1) Case of One Single Address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
-
-/* 2) Case of Dual address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
-
-/* 3) Case of General Call enabled for the slave */
-#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
-
-/**
- * @brief Communication events
- *
- * Wait on one of these events when EV1 has already been checked and:
- *
- * - Slave RECEIVER mode:
- * - EV2: When the application is expecting a data byte to be received.
- * - EV4: When the application is expecting the end of the communication: master
- * sends a stop condition and data transmission is stopped.
- *
- * - Slave Transmitter mode:
- * - EV3: When a byte has been transmitted by the slave and the application is expecting
- * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
- * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
- * used when the user software doesn't guarantee the EV3 is managed before the
- * current byte end of transfer.
- * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
- * shall end (before sending the STOP condition). In this case slave has to stop sending
- * data bytes and expect a Stop condition on the bus.
- *
- * @note In case the user software does not guarantee that the event EV2 is
- * managed before the current byte end of transfer, then user may check on EV2
- * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Slave RECEIVER mode --------------------------*/
-/* --EV2 */
-#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
-/* --EV4 */
-#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
-
-/* Slave TRANSMITTER mode -----------------------*/
-/* --EV3 */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
-/* --EV3_2 */
-#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
-
-/*
- ===============================================================================
- End of Events Description
- ===============================================================================
- */
-
-#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
- ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
- ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
-/**
- * @}
- */
-
-/** @defgroup I2C_own_address1
- * @{
- */
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
-/**
- * @}
- */
-
-/** @defgroup I2C_clock_speed
- * @{
- */
-
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the I2C configuration to the default reset state *****/
-void I2C_DeInit(I2C_TypeDef* I2Cx);
-
-/* Initialization and Configuration functions *********************************/
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter);
-void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
-
-/* PEC management functions ***************************************************/
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
-
-/* DMA transfers management functions *****************************************/
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Interrupts, events and flags management functions **************************/
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
-
-/*
- ===============================================================================
- I2C State Monitoring Functions
- ===============================================================================
- This I2C driver provides three different ways for I2C state monitoring
- depending on the application requirements and constraints:
-
-
- 1. Basic state monitoring (Using I2C_CheckEvent() function)
- -----------------------------------------------------------
- It compares the status registers (SR1 and SR2) content to a given event
- (can be the combination of one or more flags).
- It returns SUCCESS if the current status includes the given flags
- and returns ERROR if one or more flags are missing in the current status.
-
- - When to use
- - This function is suitable for most applications as well as for startup
- activity since the events are fully described in the product reference
- manual (RM0090).
- - It is also suitable for users who need to define their own events.
-
- - Limitations
- - If an error occurs (ie. error flags are set besides to the monitored
- flags), the I2C_CheckEvent() function may return SUCCESS despite
- the communication hold or corrupted real state.
- In this case, it is advised to use error interrupts to monitor
- the error events and handle them in the interrupt IRQ handler.
-
- Note
- For error management, it is advised to use the following functions:
- - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
- Where x is the peripheral instance (I2C1, I2C2 ...)
- - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
- I2Cx_ER_IRQHandler() function in order to determine which error occurred.
- - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- and/or I2C_GenerateStop() in order to clear the error flag and source
- and return to correct communication status.
-
-
- 2. Advanced state monitoring (Using the function I2C_GetLastEvent())
- --------------------------------------------------------------------
- Using the function I2C_GetLastEvent() which returns the image of both status
- registers in a single word (uint32_t) (Status Register 2 value is shifted left
- by 16 bits and concatenated to Status Register 1).
-
- - When to use
- - This function is suitable for the same applications above but it
- allows to overcome the mentioned limitation of I2C_GetFlagStatus()
- function.
- - The returned value could be compared to events already defined in
- this file or to custom values defined by user.
- This function is suitable when multiple flags are monitored at the
- same time.
- - At the opposite of I2C_CheckEvent() function, this function allows
- user to choose when an event is accepted (when all events flags are
- set and no other flags are set or just when the needed flags are set
- like I2C_CheckEvent() function.
-
- - Limitations
- - User may need to define his own events.
- - Same remark concerning the error management is applicable for this
- function if user decides to check only regular communication flags
- (and ignores error flags).
-
-
- 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
- -----------------------------------------------------------------------
-
- Using the function I2C_GetFlagStatus() which simply returns the status of
- one single flag (ie. I2C_FLAG_RXNE ...).
-
- - When to use
- - This function could be used for specific applications or in debug
- phase.
- - It is suitable when only one flag checking is needed (most I2C
- events are monitored through multiple flags).
- - Limitations:
- - When calling this function, the Status register is accessed.
- Some flags are cleared when the status register is accessed.
- So checking the status of one Flag, may clear other ones.
- - Function may need to be called twice or more in order to monitor
- one single event.
- */
-
-/*
- ===============================================================================
- 1. Basic state monitoring
- ===============================================================================
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
-/*
- ===============================================================================
- 2. Advanced state monitoring
- ===============================================================================
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
-/*
- ===============================================================================
- 3. Flag-based state monitoring
- ===============================================================================
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-
-
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_I2C_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h
deleted file mode 100644
index e0e69661..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_iwdg.h
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file contains all the functions prototypes for the IWDG
- * firmware library.
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "misc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup MISC
- * @brief MISC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup MISC_Private_Functions
- * @{
- */
-
-/**
- * @brief Configures the priority grouping: pre-emption priority and subpriority.
- * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
- * 4 bits for subpriority
- * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
- * 3 bits for subpriority
- * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
- * 2 bits for subpriority
- * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
- * 1 bits for subpriority
- * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
- * 0 bits for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
- SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
-}
-
-/**
- * @brief Initializes the NVIC peripheral according to the specified
- * parameters in the NVIC_InitStruct.
- * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
- * function should be called before.
- * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
- * the configuration information for the specified NVIC peripheral.
- * @retval None
- */
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
- uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
- assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
-
- if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
- {
- /* Compute the Corresponding IRQ Priority --------------------------------*/
- tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
- tmppre = (0x4 - tmppriority);
- tmpsub = tmpsub >> tmppriority;
-
- tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
- tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
-
- tmppriority = tmppriority << 0x04;
-
- NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
-
- /* Enable the Selected IRQ Channels --------------------------------------*/
- NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
- else
- {
- /* Disable the Selected IRQ Channels -------------------------------------*/
- NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
-}
-
-/**
- * @brief Sets the vector table location and Offset.
- * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
- * This parameter can be one of the following values:
- * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
- * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
- * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
- * @retval None
- */
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
- assert_param(IS_NVIC_OFFSET(Offset));
-
- SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
-}
-
-/**
- * @brief Selects the condition for the system to enter low power mode.
- * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
- * This parameter can be one of the following values:
- * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
- * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
- * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
- * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_LP(LowPowerMode));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- SCB->SCR |= LowPowerMode;
- }
- else
- {
- SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
- }
-}
-
-/**
- * @brief Configures the SysTick clock source.
- * @param SysTick_CLKSource: specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
- if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
- {
- SysTick->CTRL |= SysTick_CLKSource_HCLK;
- }
- else
- {
- SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
deleted file mode 100644
index 8f6a492d..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
+++ /dev/null
@@ -1,1741 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_adc.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC) peripheral:
- * + Initialization and Configuration (in addition to ADC multi mode
- * selection)
- * + Analog Watchdog configuration
- * + Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT
- * management
- * + Regular Channels Configuration
- * + Regular Channels DMA Configuration
- * + Injected channels Configuration
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable the ADC interface clock using
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE);
-
- (#) ADC pins configuration
- (++) Enable the clock for the ADC GPIOs using the following function:
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
- (++) Configure these ADC pins in analog mode using GPIO_Init();
-
- (#) Configure the ADC Prescaler, conversion resolution and data
- alignment using the ADC_Init() function.
- (#) Activate the ADC peripheral using ADC_Cmd() function.
-
- *** Regular channels group configuration ***
- ============================================
- [..]
- (+) To configure the ADC regular channels group features, use
- ADC_Init() and ADC_RegularChannelConfig() functions.
- (+) To activate the continuous mode, use the ADC_continuousModeCmd()
- function.
- (+) To configurate and activate the Discontinuous mode, use the
- ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
- (+) To read the ADC converted values, use the ADC_GetConversionValue()
- function.
-
- *** Multi mode ADCs Regular channels configuration ***
- ======================================================
- [..]
- (+) Refer to "Regular channels group configuration" description to
- configure the ADC1, ADC2 and ADC3 regular channels.
- (+) Select the Multi mode ADC regular channels features (dual or
- triple mode) using ADC_CommonInit() function and configure
- the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd()
- functions.
- (+) Read the ADCs converted values using the
- ADC_GetMultiModeConversionValue() function.
-
- *** DMA for Regular channels group features configuration ***
- =============================================================
- [..]
- (+) To enable the DMA mode for regular channels group, use the
- ADC_DMACmd() function.
- (+) To enable the generation of DMA requests continuously at the end
- of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
- function.
-
- *** Injected channels group configuration ***
- =============================================
- [..]
- (+) To configure the ADC Injected channels group features, use
- ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()
- functions.
- (+) To activate the continuous mode, use the ADC_continuousModeCmd()
- function.
- (+) To activate the Injected Discontinuous mode, use the
- ADC_InjectedDiscModeCmd() function.
- (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
- function.
- (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue()
- function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_adc.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup ADC
- * @brief ADC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ADC DISCNUM mask */
-#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
-
-/* ADC AWDCH mask */
-#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
-
-/* ADC Analog watchdog enable mode mask */
-#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF)
-
-/* CR1 register Mask */
-#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)
-
-/* ADC EXTEN mask */
-#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF)
-
-/* ADC JEXTEN mask */
-#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)
-
-/* ADC JEXTSEL mask */
-#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)
-
-/* CR2 register Mask */
-#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)
-
-/* ADC SQx mask */
-#define SQR3_SQ_SET ((uint32_t)0x0000001F)
-#define SQR2_SQ_SET ((uint32_t)0x0000001F)
-#define SQR1_SQ_SET ((uint32_t)0x0000001F)
-
-/* ADC L Mask */
-#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF)
-
-/* ADC JSQx mask */
-#define JSQR_JSQ_SET ((uint32_t)0x0000001F)
-
-/* ADC JL mask */
-#define JSQR_JL_SET ((uint32_t)0x00300000)
-#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
-
-/* ADC SMPx mask */
-#define SMPR1_SMP_SET ((uint32_t)0x00000007)
-#define SMPR2_SMP_SET ((uint32_t)0x00000007)
-
-/* ADC JDRx registers offset */
-#define JDR_OFFSET ((uint8_t)0x28)
-
-/* ADC CDR register base address */
-#define CDR_ADDRESS ((uint32_t)0x40012308)
-
-/* ADC CCR register Mask */
-#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Functions
- * @{
- */
-
-/** @defgroup ADC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the ADC Prescaler
- (+) ADC Conversion Resolution (12bit..6bit)
- (+) Scan Conversion Mode (multichannel or one channel) for regular group
- (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for
- regular group
- (+) External trigger Edge and source of regular group,
- (+) Converted data alignment (left or right)
- (+) The number of ADC conversions that will be done using the sequencer for
- regular channel group
- (+) Multi ADC mode selection
- (+) Direct memory access mode selection for multi ADC mode
- (+) Delay between 2 sampling phases (used in dual or triple interleaved modes)
- (+) Enable or disable the ADC peripheral
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes all ADCs peripherals registers to their default reset
- * values.
- * @param None
- * @retval None
- */
-void ADC_DeInit(void)
-{
- /* Enable all ADCs reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE);
-
- /* Release all ADCs from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE);
-}
-
-/**
- * @brief Initializes the ADCx peripheral according to the specified parameters
- * in the ADC_InitStruct.
- * @note This function is used to configure the global features of the ADC (
- * Resolution and Data Alignment), however, the rest of the configuration
- * parameters are specific to the regular channels group (scan mode
- * activation, continuous mode activation, External trigger source and
- * edge, number of conversion in the regular channels group sequencer).
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
- * the configuration information for the specified ADC peripheral.
- * @retval None
- */
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
-{
- uint32_t tmpreg1 = 0;
- uint8_t tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
- assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));
- assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
- assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
- assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));
-
- /*---------------------------- ADCx CR1 Configuration -----------------*/
- /* Get the ADCx CR1 value */
- tmpreg1 = ADCx->CR1;
-
- /* Clear RES and SCAN bits */
- tmpreg1 &= CR1_CLEAR_MASK;
-
- /* Configure ADCx: scan conversion mode and resolution */
- /* Set SCAN bit according to ADC_ScanConvMode value */
- /* Set RES bit according to ADC_Resolution value */
- tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \
- ADC_InitStruct->ADC_Resolution);
- /* Write to ADCx CR1 */
- ADCx->CR1 = tmpreg1;
- /*---------------------------- ADCx CR2 Configuration -----------------*/
- /* Get the ADCx CR2 value */
- tmpreg1 = ADCx->CR2;
-
- /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
- tmpreg1 &= CR2_CLEAR_MASK;
-
- /* Configure ADCx: external trigger event and edge, data alignment and
- continuous conversion mode */
- /* Set ALIGN bit according to ADC_DataAlign value */
- /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */
- /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
- /* Set CONT bit according to ADC_ContinuousConvMode value */
- tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \
- ADC_InitStruct->ADC_ExternalTrigConv |
- ADC_InitStruct->ADC_ExternalTrigConvEdge | \
- ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
-
- /* Write to ADCx CR2 */
- ADCx->CR2 = tmpreg1;
- /*---------------------------- ADCx SQR1 Configuration -----------------*/
- /* Get the ADCx SQR1 value */
- tmpreg1 = ADCx->SQR1;
-
- /* Clear L bits */
- tmpreg1 &= SQR1_L_RESET;
-
- /* Configure ADCx: regular channel sequence length */
- /* Set L bits according to ADC_NbrOfConversion value */
- tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
- tmpreg1 |= ((uint32_t)tmpreg2 << 20);
-
- /* Write to ADCx SQR1 */
- ADCx->SQR1 = tmpreg1;
-}
-
-/**
- * @brief Fills each ADC_InitStruct member with its default value.
- * @note This function is used to initialize the global features of the ADC (
- * Resolution and Data Alignment), however, the rest of the configuration
- * parameters are specific to the regular channels group (scan mode
- * activation, continuous mode activation, External trigger source and
- * edge, number of conversion in the regular channels group sequencer).
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
-{
- /* Initialize the ADC_Mode member */
- ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
-
- /* initialize the ADC_ScanConvMode member */
- ADC_InitStruct->ADC_ScanConvMode = DISABLE;
-
- /* Initialize the ADC_ContinuousConvMode member */
- ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
-
- /* Initialize the ADC_ExternalTrigConvEdge member */
- ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
-
- /* Initialize the ADC_ExternalTrigConv member */
- ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
-
- /* Initialize the ADC_DataAlign member */
- ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
-
- /* Initialize the ADC_NbrOfConversion member */
- ADC_InitStruct->ADC_NbrOfConversion = 1;
-}
-
-/**
- * @brief Initializes the ADCs peripherals according to the specified parameters
- * in the ADC_CommonInitStruct.
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
- * that contains the configuration information for All ADCs peripherals.
- * @retval None
- */
-void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
-{
- uint32_t tmpreg1 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));
- assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
- assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
- assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
- /*---------------------------- ADC CCR Configuration -----------------*/
- /* Get the ADC CCR value */
- tmpreg1 = ADC->CCR;
-
- /* Clear MULTI, DELAY, DMA and ADCPRE bits */
- tmpreg1 &= CR_CLEAR_MASK;
-
- /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler,
- and DMA access mode for multimode */
- /* Set MULTI bits according to ADC_Mode value */
- /* Set ADCPRE bits according to ADC_Prescaler value */
- /* Set DMA bits according to ADC_DMAAccessMode value */
- /* Set DELAY bits according to ADC_TwoSamplingDelay value */
- tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode |
- ADC_CommonInitStruct->ADC_Prescaler |
- ADC_CommonInitStruct->ADC_DMAAccessMode |
- ADC_CommonInitStruct->ADC_TwoSamplingDelay);
-
- /* Write to ADC CCR */
- ADC->CCR = tmpreg1;
-}
-
-/**
- * @brief Fills each ADC_CommonInitStruct member with its default value.
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
-{
- /* Initialize the ADC_Mode member */
- ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
-
- /* initialize the ADC_Prescaler member */
- ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2;
-
- /* Initialize the ADC_DMAAccessMode member */
- ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
-
- /* Initialize the ADC_TwoSamplingDelay member */
- ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
-}
-
-/**
- * @brief Enables or disables the specified ADC peripheral.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the ADCx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the ADON bit to wake up the ADC from power down mode */
- ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;
- }
- else
- {
- /* Disable the selected ADC peripheral */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group2 Analog Watchdog configuration functions
- * @brief Analog Watchdog configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Analog Watchdog configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the Analog Watchdog
- (AWD) feature in the ADC.
-
- [..] A typical configuration Analog Watchdog is done following these steps :
- (#) the ADC guarded channel(s) is (are) selected using the
- ADC_AnalogWatchdogSingleChannelConfig() function.
- (#) The Analog watchdog lower and higher threshold are configured using the
- ADC_AnalogWatchdogThresholdsConfig() function.
- (#) The Analog watchdog is enabled and configured to enable the check, on one
- or more channels, using the ADC_AnalogWatchdogCmd() function.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the analog watchdog on single/all regular or
- * injected channels
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
- * This parameter can be one of the following values:
- * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
- * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
- * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
- * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
- * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
- * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
- * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
- * @retval None
- */
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
-
- /* Get the old register value */
- tmpreg = ADCx->CR1;
-
- /* Clear AWDEN, JAWDEN and AWDSGL bits */
- tmpreg &= CR1_AWDMode_RESET;
-
- /* Set the analog watchdog enable mode */
- tmpreg |= ADC_AnalogWatchdog;
-
- /* Store the new register value */
- ADCx->CR1 = tmpreg;
-}
-
-/**
- * @brief Configures the high and low thresholds of the analog watchdog.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param HighThreshold: the ADC analog watchdog High threshold value.
- * This parameter must be a 12-bit value.
- * @param LowThreshold: the ADC analog watchdog Low threshold value.
- * This parameter must be a 12-bit value.
- * @retval None
- */
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
- uint16_t LowThreshold)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_THRESHOLD(HighThreshold));
- assert_param(IS_ADC_THRESHOLD(LowThreshold));
-
- /* Set the ADCx high threshold */
- ADCx->HTR = HighThreshold;
-
- /* Set the ADCx low threshold */
- ADCx->LTR = LowThreshold;
-}
-
-/**
- * @brief Configures the analog watchdog guarded single channel
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @retval None
- */
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
-
- /* Get the old register value */
- tmpreg = ADCx->CR1;
-
- /* Clear the Analog watchdog channel select bits */
- tmpreg &= CR1_AWDCH_RESET;
-
- /* Set the Analog watchdog channel */
- tmpreg |= ADC_Channel;
-
- /* Store the new register value */
- ADCx->CR1 = tmpreg;
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal)
- * and VBAT (Voltage BATtery) management functions
- * @brief Temperature Sensor, Vrefint and VBAT management functions
- *
-@verbatim
- ===============================================================================
- ##### Temperature Sensor, Vrefint and VBAT management functions #####
- ===============================================================================
- [..] This section provides functions allowing to enable/ disable the internal
- connections between the ADC and the Temperature Sensor, the Vrefint and
- the Vbat sources.
-
- [..] A typical configuration to get the Temperature sensor and Vrefint channels
- voltages is done following these steps :
- (#) Enable the internal connection of Temperature sensor and Vrefint sources
- with the ADC channels using ADC_TempSensorVrefintCmd() function.
- (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using
- ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions
- (#) Get the voltage values, using ADC_GetConversionValue() or
- ADC_GetInjectedConversionValue().
-
- [..] A typical configuration to get the VBAT channel voltage is done following
- these steps :
- (#) Enable the internal connection of VBAT source with the ADC channel using
- ADC_VBATCmd() function.
- (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or
- ADC_InjectedChannelConfig() functions
- (#) Get the voltage value, using ADC_GetConversionValue() or
- ADC_GetInjectedConversionValue().
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Enables or disables the temperature sensor and Vrefint channels.
- * @param NewState: new state of the temperature sensor and Vrefint channels.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_TempSensorVrefintCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the temperature sensor and Vrefint channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;
- }
- else
- {
- /* Disable the temperature sensor and Vrefint channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);
- }
-}
-
-/**
- * @brief Enables or disables the VBAT (Voltage Battery) channel.
- * @param NewState: new state of the VBAT channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_VBATCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the VBAT channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_VBATE;
- }
- else
- {
- /* Disable the VBAT channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group4 Regular Channels Configuration functions
- * @brief Regular Channels Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Regular Channels Configuration functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to manage the ADC's regular channels,
- it is composed of 2 sub sections :
-
- (#) Configuration and management functions for regular channels: This subsection
- provides functions allowing to configure the ADC regular channels :
- (++) Configure the rank in the regular group sequencer for each channel
- (++) Configure the sampling time for each channel
- (++) select the conversion Trigger for regular channels
- (++) select the desired EOC event behavior configuration
- (++) Activate the continuous Mode (*)
- (++) Activate the Discontinuous Mode
- -@@- Please Note that the following features for regular channels
- are configurated using the ADC_Init() function :
- (+@@) scan mode activation
- (+@@) continuous mode activation (**)
- (+@@) External trigger source
- (+@@) External trigger edge
- (+@@) number of conversion in the regular channels group sequencer.
-
- -@@- (*) and (**) are performing the same configuration
-
- (#) Get the conversion data: This subsection provides an important function in
- the ADC peripheral since it returns the converted data of the current
- regular channel. When the Conversion value is read, the EOC Flag is
- automatically cleared.
-
- -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions
- results data (in the selected multi mode) can be returned in the same
- time using ADC_GetMultiModeConversionValue() function.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Configures for the selected ADC regular channel its corresponding
- * rank in the sequencer and its sample time.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @param Rank: The rank in the regular group sequencer.
- * This parameter must be between 1 to 16.
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
- * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
- * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
- * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
- * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
- * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
- * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
- * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
- * @retval None
- */
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_REGULAR_RANK(Rank));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
-
- /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
- if (ADC_Channel > ADC_Channel_9)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR1;
-
- /* Calculate the mask to clear */
- tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10));
-
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
-
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SMPR1 = tmpreg1;
- }
- else /* ADC_Channel include in ADC_Channel_[0..9] */
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR2;
-
- /* Calculate the mask to clear */
- tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
-
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
-
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SMPR2 = tmpreg1;
- }
- /* For Rank 1 to 6 */
- if (Rank < 7)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR3;
-
- /* Calculate the mask to clear */
- tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1));
-
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
-
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SQR3 = tmpreg1;
- }
- /* For Rank 7 to 12 */
- else if (Rank < 13)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR2;
-
- /* Calculate the mask to clear */
- tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7));
-
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
-
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SQR2 = tmpreg1;
- }
- /* For Rank 13 to 16 */
- else
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR1;
-
- /* Calculate the mask to clear */
- tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13));
-
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
-
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SQR1 = tmpreg1;
- }
-}
-
-/**
- * @brief Enables the selected ADC software start conversion of the regular channels.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval None
- */
-void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Enable the selected ADC conversion for regular group */
- ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-}
-
-/**
- * @brief Gets the selected ADC Software start regular conversion Status.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The new state of ADC software start conversion (SET or RESET).
- */
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of SWSTART bit */
- if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
- {
- /* SWSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* SWSTART bit is reset */
- bitstatus = RESET;
- }
-
- /* Return the SWSTART bit status */
- return bitstatus;
-}
-
-
-/**
- * @brief Enables or disables the EOC on each regular channel conversion
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC EOC flag rising
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC EOC rising on each regular channel conversion */
- ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS;
- }
- else
- {
- /* Disable the selected ADC EOC rising on each regular channel conversion */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS);
- }
-}
-
-/**
- * @brief Enables or disables the ADC continuous conversion mode
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC continuous conversion mode
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC continuous conversion mode */
- ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;
- }
- else
- {
- /* Disable the selected ADC continuous conversion mode */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);
- }
-}
-
-/**
- * @brief Configures the discontinuous mode for the selected ADC regular group
- * channel.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param Number: specifies the discontinuous mode regular channel count value.
- * This number must be between 1 and 8.
- * @retval None
- */
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
-
- /* Get the old register value */
- tmpreg1 = ADCx->CR1;
-
- /* Clear the old discontinuous mode channel count */
- tmpreg1 &= CR1_DISCNUM_RESET;
-
- /* Set the discontinuous mode channel count */
- tmpreg2 = Number - 1;
- tmpreg1 |= tmpreg2 << 13;
-
- /* Store the new register value */
- ADCx->CR1 = tmpreg1;
-}
-
-/**
- * @brief Enables or disables the discontinuous mode on regular group channel
- * for the specified ADC
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC discontinuous mode on
- * regular group channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC regular discontinuous mode */
- ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;
- }
- else
- {
- /* Disable the selected ADC regular discontinuous mode */
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);
- }
-}
-
-/**
- * @brief Returns the last ADCx conversion result data for regular channel.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Return the selected ADC conversion value */
- return (uint16_t) ADCx->DR;
-}
-
-/**
- * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
- * data in the selected multi mode.
- * @param None
- * @retval The Data conversion value.
- * @note In dual mode, the value returned by this function is as following
- * Data[15:0] : these bits contain the regular data of ADC1.
- * Data[31:16]: these bits contain the regular data of ADC2.
- * @note In triple mode, the value returned by this function is as following
- * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.
- * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.
- */
-uint32_t ADC_GetMultiModeConversionValue(void)
-{
- /* Return the multi mode conversion value */
- return (*(__IO uint32_t *) CDR_ADDRESS);
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
- * @brief Regular Channels DMA Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Regular Channels DMA Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the DMA for ADC
- regular channels.
- Since converted regular channel values are stored into a unique data
- register, it is useful to use DMA for conversion of more than one regular
- channel. This avoids the loss of the data already stored in the ADC
- Data register.
- When the DMA mode is enabled (using the ADC_DMACmd() function), after each
- conversion of a regular channel, a DMA request is generated.
- [..] Depending on the "DMA disable selection for Independent ADC mode"
- configuration (using the ADC_DMARequestAfterLastTransferCmd() function),
- at the end of the last DMA transfer, two possibilities are allowed:
- (+) No new DMA request is issued to the DMA controller (feature DISABLED)
- (+) Requests can continue to be generated (feature ENABLED).
- [..] Depending on the "DMA disable selection for multi ADC mode" configuration
- (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function),
- at the end of the last DMA transfer, two possibilities are allowed:
- (+) No new DMA request is issued to the DMA controller (feature DISABLED)
- (+) Requests can continue to be generated (feature ENABLED).
-
-@endverbatim
- * @{
- */
-
- /**
- * @brief Enables or disables the specified ADC DMA request.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request */
- ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;
- }
- else
- {
- /* Disable the selected ADC DMA request */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);
- }
-}
-
-/**
- * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC DMA request after last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request after last transfer */
- ADCx->CR2 |= (uint32_t)ADC_CR2_DDS;
- }
- else
- {
- /* Disable the selected ADC DMA request after last transfer */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS);
- }
-}
-
-/**
- * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode
- * @param NewState: new state of the selected ADC DMA request after last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @note if Enabled, DMA requests are issued as long as data are converted and
- * DMA mode for multi ADC mode (selected using ADC_CommonInit() function
- * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is
- * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3.
- * @retval None
- */
-void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request after last transfer */
- ADC->CCR |= (uint32_t)ADC_CCR_DDS;
- }
- else
- {
- /* Disable the selected ADC DMA request after last transfer */
- ADC->CCR &= (uint32_t)(~ADC_CCR_DDS);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group6 Injected channels Configuration functions
- * @brief Injected channels Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Injected channels Configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to configure the ADC Injected channels,
- it is composed of 2 sub sections :
-
- (#) Configuration functions for Injected channels: This subsection provides
- functions allowing to configure the ADC injected channels :
- (++) Configure the rank in the injected group sequencer for each channel
- (++) Configure the sampling time for each channel
- (++) Activate the Auto injected Mode
- (++) Activate the Discontinuous Mode
- (++) scan mode activation
- (++) External/software trigger source
- (++) External trigger edge
- (++) injected channels sequencer.
-
- (#) Get the Specified Injected channel conversion data: This subsection
- provides an important function in the ADC peripheral since it returns the
- converted data of the specific injected channel.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Configures for the selected ADC injected channel its corresponding
- * rank in the sequencer and its sample time.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @param Rank: The rank in the injected group sequencer.
- * This parameter must be between 1 to 4.
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
- * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
- * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
- * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
- * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
- * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
- * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
- * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
- * @retval None
- */
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_INJECTED_RANK(Rank));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
- /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
- if (ADC_Channel > ADC_Channel_9)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR1;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10));
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR1 = tmpreg1;
- }
- else /* ADC_Channel include in ADC_Channel_[0..9] */
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR2;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR2 = tmpreg1;
- }
- /* Rank configuration */
- /* Get the old register value */
- tmpreg1 = ADCx->JSQR;
- /* Get JL value: Number = JL+1 */
- tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;
- /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
- tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
- /* Clear the old JSQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
- /* Set the JSQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->JSQR = tmpreg1;
-}
-
-/**
- * @brief Configures the sequencer length for injected channels
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param Length: The sequencer length.
- * This parameter must be a number between 1 to 4.
- * @retval None
- */
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_LENGTH(Length));
-
- /* Get the old register value */
- tmpreg1 = ADCx->JSQR;
-
- /* Clear the old injected sequence length JL bits */
- tmpreg1 &= JSQR_JL_RESET;
-
- /* Set the injected sequence length JL bits */
- tmpreg2 = Length - 1;
- tmpreg1 |= tmpreg2 << 20;
-
- /* Store the new register value */
- ADCx->JSQR = tmpreg1;
-}
-
-/**
- * @brief Set the injected channels conversion value offset
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
- * This parameter can be one of the following values:
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected
- * @param Offset: the offset value for the selected ADC injected channel
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
-{
- __IO uint32_t tmp = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
- assert_param(IS_ADC_OFFSET(Offset));
-
- tmp = (uint32_t)ADCx;
- tmp += ADC_InjectedChannel;
-
- /* Set the selected injected channel data offset */
- *(__IO uint32_t *) tmp = (uint32_t)Offset;
-}
-
- /**
- * @brief Configures the ADCx external trigger for injected channels conversion.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
- * This parameter can be one of the following values:
- * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
- * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected
- * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
- * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
- * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
- * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected
- * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected
- * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
- * @retval None
- */
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
-
- /* Get the old register value */
- tmpreg = ADCx->CR2;
-
- /* Clear the old external event selection for injected group */
- tmpreg &= CR2_JEXTSEL_RESET;
-
- /* Set the external event selection for injected group */
- tmpreg |= ADC_ExternalTrigInjecConv;
-
- /* Store the new register value */
- ADCx->CR2 = tmpreg;
-}
-
-/**
- * @brief Configures the ADCx external trigger edge for injected channels conversion.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge
- * to start injected conversion.
- * This parameter can be one of the following values:
- * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for
- * injected conversion
- * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge
- * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge
- * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising
- * and falling edge
- * @retval None
- */
-void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));
- /* Get the old register value */
- tmpreg = ADCx->CR2;
- /* Clear the old external trigger edge for injected group */
- tmpreg &= CR2_JEXTEN_RESET;
- /* Set the new external trigger edge for injected group */
- tmpreg |= ADC_ExternalTrigInjecConvEdge;
- /* Store the new register value */
- ADCx->CR2 = tmpreg;
-}
-
-/**
- * @brief Enables the selected ADC software start conversion of the injected channels.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval None
- */
-void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Enable the selected ADC conversion for injected group */
- ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;
-}
-
-/**
- * @brief Gets the selected ADC Software start injected conversion Status.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The new state of ADC software start injected conversion (SET or RESET).
- */
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of JSWSTART bit */
- if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
- {
- /* JSWSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* JSWSTART bit is reset */
- bitstatus = RESET;
- }
- /* Return the JSWSTART bit status */
- return bitstatus;
-}
-
-/**
- * @brief Enables or disables the selected ADC automatic injected group
- * conversion after regular one.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC auto injected conversion
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC automatic injected group conversion */
- ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;
- }
- else
- {
- /* Disable the selected ADC automatic injected group conversion */
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);
- }
-}
-
-/**
- * @brief Enables or disables the discontinuous mode for injected group
- * channel for the specified ADC
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC discontinuous mode on injected
- * group channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC injected discontinuous mode */
- ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;
- }
- else
- {
- /* Disable the selected ADC injected discontinuous mode */
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);
- }
-}
-
-/**
- * @brief Returns the ADC injected channel conversion result
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InjectedChannel: the converted ADC injected channel.
- * This parameter can be one of the following values:
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
-
- tmp = (uint32_t)ADCx;
- tmp += ADC_InjectedChannel + JDR_OFFSET;
-
- /* Returns the selected injected channel conversion data value */
- return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the ADC Interrupts
- and to get the status and clear flags and Interrupts pending bits.
-
- [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided
- into 3 groups:
-
- *** Flags and Interrupts for ADC regular channels ***
- =====================================================
- [..]
- (+) Flags :
- (##) ADC_FLAG_OVR : Overrun detection when regular converted data are lost
-
- (##) ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate
- (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() )
- the end of:
- (+++) a regular CHANNEL conversion
- (+++) sequence of regular GROUP conversions .
-
- (##) ADC_FLAG_STRT: Regular channel start ==> to indicate when regular
- CHANNEL conversion starts.
- [..]
- (+) Interrupts :
- (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection
- event.
- (##) ADC_IT_EOC : specifies the interrupt source for Regular channel end
- of conversion event.
-
-
- *** Flags and Interrupts for ADC Injected channels ***
- ======================================================
- [..]
- (+) Flags :
- (##) ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate
- at the end of injected GROUP conversion
-
- (##) ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when
- injected GROUP conversion starts.
- [..]
- (+) Interrupts :
- (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel
- end of conversion event.
-
- *** General Flags and Interrupts for the ADC ***
- ================================================
- [..]
- (+)Flags :
- (##) ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage
- crosses the programmed thresholds values.
- [..]
- (+) Interrupts :
- (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event.
-
-
- [..] The user should identify which mode will be used in his application to
- manage the ADC controller events: Polling mode or Interrupt mode.
-
- [..] In the Polling Mode it is advised to use the following functions:
- (+) ADC_GetFlagStatus() : to check if flags events occur.
- (+) ADC_ClearFlag() : to clear the flags events.
-
- [..] In the Interrupt Mode it is advised to use the following functions:
- (+) ADC_ITConfig() : to enable or disable the interrupt source.
- (+) ADC_GetITStatus() : to check if Interrupt occurs.
- (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-@endverbatim
- * @{
- */
-/**
- * @brief Enables or disables the specified ADC interrupts.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @arg ADC_IT_OVR: Overrun interrupt enable
- * @param NewState: new state of the specified ADC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
-{
- uint32_t itmask = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_ADC_IT(ADC_IT));
-
- /* Get the ADC IT index */
- itmask = (uint8_t)ADC_IT;
- itmask = (uint32_t)0x01 << itmask;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC interrupts */
- ADCx->CR1 |= itmask;
- }
- else
- {
- /* Disable the selected ADC interrupts */
- ADCx->CR1 &= (~(uint32_t)itmask);
- }
-}
-
-/**
- * @brief Checks whether the specified ADC flag is set or not.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag
- * @arg ADC_FLAG_OVR: Overrun flag
- * @retval The new state of ADC_FLAG (SET or RESET).
- */
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
-
- /* Check the status of the specified ADC flag */
- if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
- {
- /* ADC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's pending flags.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag
- * @arg ADC_FLAG_OVR: Overrun flag
- * @retval None
- */
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
-
- /* Clear the selected ADC flags */
- ADCx->SR = ~(uint32_t)ADC_FLAG;
-}
-
-/**
- * @brief Checks whether the specified ADC interrupt has occurred or not.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @arg ADC_IT_OVR: Overrun interrupt mask
- * @retval The new state of ADC_IT (SET or RESET).
- */
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_IT(ADC_IT));
-
- /* Get the ADC IT index */
- itmask = ADC_IT >> 8;
-
- /* Get the ADC_IT enable bit status */
- enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ;
-
- /* Check the status of the specified ADC interrupt */
- if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
- {
- /* ADC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's interrupt pending bits.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @arg ADC_IT_OVR: Overrun interrupt mask
- * @retval None
- */
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
-{
- uint8_t itmask = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_IT(ADC_IT));
- /* Get the ADC IT index */
- itmask = (uint8_t)(ADC_IT >> 8);
- /* Clear the selected ADC interrupt pending bits */
- ADCx->SR = ~(uint32_t)itmask;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
deleted file mode 100644
index a54466b6..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
+++ /dev/null
@@ -1,1701 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_can.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Controller area network (CAN) peripheral:
- * + Initialization and Configuration
- * + CAN Frames Transmission
- * + CAN Frames Reception
- * + Operation modes switch
- * + Error management
- * + Interrupts and flags
- *
-@verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable the CAN controller interface clock using
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1
- and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2
- -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
-
- (#) CAN pins configuration
- (++) Enable the clock for the CAN GPIOs using the following function:
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
- (++) Connect the involved CAN pins to AF9 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx);
- (++) Configure these CAN pins in alternate function mode by calling
- the function GPIO_Init();
-
- (#) Initialise and configure the CAN using CAN_Init() and
- CAN_FilterInit() functions.
-
- (#) Transmit the desired CAN frame using CAN_Transmit() function.
-
- (#) Check the transmission of a CAN frame using CAN_TransmitStatus()
- function.
-
- (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit()
- function.
-
- (#) Receive a CAN frame using CAN_Recieve() function.
-
- (#) Release the receive FIFOs using CAN_FIFORelease() function.
-
- (#) Return the number of pending received frames using
- CAN_MessagePending() function.
-
- (#) To control CAN events you can use one of the following two methods:
- (++) Check on CAN flags using the CAN_GetFlagStatus() function.
- (++) Use CAN interrupts through the function CAN_ITConfig() at
- initialization phase and CAN_GetITStatus() function into
- interrupt routines to check if the event has occurred or not.
- After checking on a flag you should clear it using CAN_ClearFlag()
- function. And after checking on an interrupt event you should
- clear it using CAN_ClearITPendingBit() function.
-
-
-@endverbatim
-
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_crc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRC
- * @brief CRC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRC_Private_Functions
- * @{
- */
-
-/**
- * @brief Resets the CRC Data register (DR).
- * @param None
- * @retval None
- */
-void CRC_ResetDR(void)
-{
- /* Reset CRC generator */
- CRC->CR = CRC_CR_RESET;
-}
-
-/**
- * @brief Computes the 32-bit CRC of a given data word(32-bit).
- * @param Data: data word(32-bit) to compute its CRC
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcCRC(uint32_t Data)
-{
- CRC->DR = Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
- * @param pBuffer: pointer to the buffer containing the data to be computed
- * @param BufferLength: length of the buffer to be computed
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0;
-
- for(index = 0; index < BufferLength; index++)
- {
- CRC->DR = pBuffer[index];
- }
- return (CRC->DR);
-}
-
-/**
- * @brief Returns the current CRC value.
- * @param None
- * @retval 32-bit CRC
- */
-uint32_t CRC_GetCRC(void)
-{
- return (CRC->DR);
-}
-
-/**
- * @brief Stores a 8-bit data in the Independent Data(ID) register.
- * @param IDValue: 8-bit value to be stored in the ID register
- * @retval None
- */
-void CRC_SetIDRegister(uint8_t IDValue)
-{
- CRC->IDR = IDValue;
-}
-
-/**
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register
- * @param None
- * @retval 8-bit value of the ID register
- */
-uint8_t CRC_GetIDRegister(void)
-{
- return (CRC->IDR);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
deleted file mode 100644
index 824ccfbb..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
+++ /dev/null
@@ -1,934 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_cryp.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Cryptographic processor (CRYP) peripheral:
- * + Initialization and Configuration functions
- * + Data treatment functions
- * + Context swapping functions
- * + DMA interface function
- * + Interrupts and flags management
- *
-@verbatim
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable the CRYP controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
-
- (#) Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if needed
- CRYP_IVInit().
-
- (#) Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.
-
- (#) Enable the CRYP controller using the CRYP_Cmd() function.
-
- (#) If using DMA for Data input and output transfer, activate the needed DMA
- Requests using CRYP_DMACmd() function
-
- (#) If DMA is not used for data transfer, use CRYP_DataIn() and CRYP_DataOut()
- functions to enter data to IN FIFO and get result from OUT FIFO.
-
- (#) To control CRYP events you can use one of the following two methods:
- (++) Check on CRYP flags using the CRYP_GetFlagStatus() function.
- (++) Use CRYP interrupts through the function CRYP_ITConfig() at
- initialization phase and CRYP_GetITStatus() function into interrupt
- routines in processing phase.
-
- (#) Save and restore Cryptographic processor context using CRYP_SaveContext()
- and CRYP_RestoreContext() functions.
-
-
- *** Procedure to perform an encryption or a decryption ***
- ==========================================================
-
- *** Initialization ***
- ======================
- [..]
- (#) Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and CRYP_IVInit
- functions:
- (++) Configure the key size (128-, 192- or 256-bit, in the AES only)
- (++) Enter the symmetric key
- (++) Configure the data type
- (++) In case of decryption in AES-ECB or AES-CBC, you must prepare
- the key: configure the key preparation mode. Then Enable the CRYP
- peripheral using CRYP_Cmd() function: the BUSY flag is set.
- Wait until BUSY flag is reset : the key is prepared for decryption
- (++) Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the
- AES in ECB/CBC/CTR)
- (++) Configure the direction (encryption/decryption).
- (++) Write the initialization vectors (in CBC or CTR modes only)
-
- (#) Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function
-
-
- *** Basic Processing mode (polling mode) ***
- ============================================
- [..]
- (#) Enable the cryptographic processor using CRYP_Cmd() function.
-
- (#) Write the first blocks in the input FIFO (2 to 8 words) using
- CRYP_DataIn() function.
-
- (#) Repeat the following sequence until the complete message has been
- processed:
-
- (++) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus()
- function), then read the OUT-FIFO using CRYP_DataOut() function
- (1 block or until the FIFO is empty)
-
- (++) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus()
- function then write the IN FIFO using CRYP_DataIn() function
- (1 block or until the FIFO is full)
-
- (#) At the end of the processing, CRYP_FLAG_BUSY flag will be reset and
- both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is
- reset). You can disable the peripheral using CRYP_Cmd() function.
-
- *** Interrupts Processing mode ***
- ==================================
- [..] In this mode, Processing is done when the data are transferred by the
- CPU during interrupts.
-
- (#) Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using CRYP_ITConfig()
- function.
-
- (#) Enable the cryptographic processor using CRYP_Cmd() function.
-
- (#) In the CRYP_IT_INI interrupt handler : load the input message into the
- IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a
- time, or load data until the IN FIFO is full. When the last word of
- the message has been entered into the IN FIFO, disable the CRYP_IT_INI
- interrupt (using CRYP_ITConfig() function).
-
- (#) In the CRYP_IT_OUTI interrupt handler : read the output message from
- the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or
- 4 words) at a time or read data until the FIFO is empty.
- When the last word has been read, INIM=0, BUSY=0 and both FIFOs are
- empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset).
- You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig()
- function) and you can disable the peripheral using CRYP_Cmd() function.
-
- *** DMA Processing mode ***
- ===========================
- [..] In this mode, Processing is done when the DMA is used to transfer the
- data from/to the memory.
-
- (#) Configure the DMA controller to transfer the input data from the
- memory using DMA_Init() function.
- The transfer length is the length of the message.
- As message padding is not managed by the peripheral, the message
- length must be an entire number of blocks. The data are transferred
- in burst mode. The burst length is 4 words in the AES and 2 or 4
- words in the DES/TDES. The DMA should be configured to set an
- interrupt on transfer completion of the output data to indicate that
- the processing is finished.
- Refer to DMA peripheral driver for more details.
-
- (#) Enable the cryptographic processor using CRYP_Cmd() function.
- Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT
- using CRYP_DMACmd() function.
-
- (#) All the transfers and processing are managed by the DMA and the
- cryptographic processor. The DMA transfer complete interrupt indicates
- that the processing is complete. Both FIFOs are normally empty and
- CRYP_FLAG_BUSY flag is reset.
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRYP
- * @brief CRYP driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define FLAG_MASK ((uint8_t)0x20)
-#define MAX_TIMEOUT ((uint16_t)0xFFFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRYP_Private_Functions
- * @{
- */
-
-/** @defgroup CRYP_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initialize the cryptographic Processor using CRYP_Init() function
- (++) Encrypt or Decrypt
- (++) mode : TDES-ECB, TDES-CBC,
- DES-ECB, DES-CBC,
- AES-ECB, AES-CBC, AES-CTR, AES-Key, AES-GCM, AES-CCM
- (++) DataType : 32-bit data, 16-bit data, bit data or bit-string
- (++) Key Size (only in AES modes)
- (+) Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function
- (+) Configure the Initialization Vectors(IV) for CBC and CTR modes using
- CRYP_IVInit() function.
- (+) Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function.
- (+) Enable or disable the CRYP Processor using CRYP_Cmd() function
-
-@endverbatim
- * @{
- */
-/**
- * @brief Deinitializes the CRYP peripheral registers to their default reset values
- * @param None
- * @retval None
- */
-void CRYP_DeInit(void)
-{
- /* Enable CRYP reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE);
-
- /* Release CRYP from reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE);
-}
-
-/**
- * @brief Initializes the CRYP peripheral according to the specified parameters
- * in the CRYP_InitStruct.
- * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains
- * the configuration information for the CRYP peripheral.
- * @retval None
- */
-void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct)
-{
- /* Check the parameters */
- assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode));
- assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType));
- assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir));
-
- /* Select Algorithm mode*/
- CRYP->CR &= ~CRYP_CR_ALGOMODE;
- CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode;
-
- /* Select dataType */
- CRYP->CR &= ~CRYP_CR_DATATYPE;
- CRYP->CR |= CRYP_InitStruct->CRYP_DataType;
-
- /* select Key size (used only with AES algorithm) */
- if ((CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_ECB) &&
- (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_CBC) &&
- (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_ECB) &&
- (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_CBC))
- {
- assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize));
- CRYP->CR &= ~CRYP_CR_KEYSIZE;
- CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be
- configured once the key has
- been prepared */
- }
-
- /* Select data Direction */
- CRYP->CR &= ~CRYP_CR_ALGODIR;
- CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir;
-}
-
-/**
- * @brief Fills each CRYP_InitStruct member with its default value.
- * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct)
-{
- /* Initialize the CRYP_AlgoDir member */
- CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
-
- /* initialize the CRYP_AlgoMode member */
- CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
-
- /* initialize the CRYP_DataType member */
- CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b;
-
- /* Initialize the CRYP_KeySize member */
- CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b;
-}
-
-/**
- * @brief Initializes the CRYP Keys according to the specified parameters in
- * the CRYP_KeyInitStruct.
- * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that
- * contains the configuration information for the CRYP Keys.
- * @retval None
- */
-void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
-{
- /* Key Initialisation */
- CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;
- CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;
- CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;
- CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;
- CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;
- CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;
- CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
- CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
-}
-
-/**
- * @brief Fills each CRYP_KeyInitStruct member with its default value.
- * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
-{
- CRYP_KeyInitStruct->CRYP_Key0Left = 0;
- CRYP_KeyInitStruct->CRYP_Key0Right = 0;
- CRYP_KeyInitStruct->CRYP_Key1Left = 0;
- CRYP_KeyInitStruct->CRYP_Key1Right = 0;
- CRYP_KeyInitStruct->CRYP_Key2Left = 0;
- CRYP_KeyInitStruct->CRYP_Key2Right = 0;
- CRYP_KeyInitStruct->CRYP_Key3Left = 0;
- CRYP_KeyInitStruct->CRYP_Key3Right = 0;
-}
-/**
- * @brief Initializes the CRYP Initialization Vectors(IV) according to the
- * specified parameters in the CRYP_IVInitStruct.
- * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains
- * the configuration information for the CRYP Initialization Vectors(IV).
- * @retval None
- */
-void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
-{
- CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left;
- CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right;
- CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left;
- CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right;
-}
-
-/**
- * @brief Fills each CRYP_IVInitStruct member with its default value.
- * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization
- * Vectors(IV) structure which will be initialized.
- * @retval None
- */
-void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
-{
- CRYP_IVInitStruct->CRYP_IV0Left = 0;
- CRYP_IVInitStruct->CRYP_IV0Right = 0;
- CRYP_IVInitStruct->CRYP_IV1Left = 0;
- CRYP_IVInitStruct->CRYP_IV1Right = 0;
-}
-
-/**
- * @brief Configures the AES-CCM and AES-GCM phases
- * @note This function is used only with AES-CCM or AES-GCM Algorithms
- * @param CRYP_Phase: specifies the CRYP AES-CCM and AES-GCM phase to be configured.
- * This parameter can be one of the following values:
- * @arg CRYP_Phase_Init: Initialization phase
- * @arg CRYP_Phase_Header: Header phase
- * @arg CRYP_Phase_Payload: Payload phase
- * @arg CRYP_Phase_Final: Final phase
- * @retval None
- */
-void CRYP_PhaseConfig(uint32_t CRYP_Phase)
-{ uint32_t tempcr = 0;
-
- /* Check the parameter */
- assert_param(IS_CRYP_PHASE(CRYP_Phase));
-
- /* Get the CR register */
- tempcr = CRYP->CR;
-
- /* Reset the phase configuration bits: GCMP_CCMPH */
- tempcr &= (uint32_t)(~CRYP_CR_GCM_CCMPH);
- /* Set the selected phase */
- tempcr |= (uint32_t)CRYP_Phase;
-
- /* Set the CR register */
- CRYP->CR = tempcr;
-}
-
-/**
- * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the
- * FIFOs are reset)
- * @note The FIFOs must be flushed only when BUSY flag is reset.
- * @param None
- * @retval None
- */
-void CRYP_FIFOFlush(void)
-{
- /* Reset the read and write pointers of the FIFOs */
- CRYP->CR |= CRYP_CR_FFLUSH;
-}
-
-/**
- * @brief Enables or disables the CRYP peripheral.
- * @param NewState: new state of the CRYP peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRYP_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Cryptographic processor */
- CRYP->CR |= CRYP_CR_CRYPEN;
- }
- else
- {
- /* Disable the Cryptographic processor */
- CRYP->CR &= ~CRYP_CR_CRYPEN;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group2 CRYP Data processing functions
- * @brief CRYP Data processing functions
- *
-@verbatim
- ===============================================================================
- ##### CRYP Data processing functions #####
- ===============================================================================
- [..] This section provides functions allowing the encryption and decryption
- operations:
- (+) Enter data to be treated in the IN FIFO : using CRYP_DataIn() function.
- (+) Get the data result from the OUT FIFO : using CRYP_DataOut() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes data in the Data Input register (DIN).
- * @note After the DIN register has been read once or several times,
- * the FIFO must be flushed (using CRYP_FIFOFlush() function).
- * @param Data: data to write in Data Input register
- * @retval None
- */
-void CRYP_DataIn(uint32_t Data)
-{
- CRYP->DR = Data;
-}
-
-/**
- * @brief Returns the last data entered into the output FIFO.
- * @param None
- * @retval Last data entered into the output FIFO.
- */
-uint32_t CRYP_DataOut(void)
-{
- return CRYP->DOUT;
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group3 Context swapping functions
- * @brief Context swapping functions
- *
-@verbatim
- ===============================================================================
- ##### Context swapping functions #####
- ===============================================================================
- [..] This section provides functions allowing to save and store CRYP Context
-
- [..] It is possible to interrupt an encryption/ decryption/ key generation process
- to perform another processing with a higher priority, and to complete the
- interrupted process later on, when the higher-priority task is complete. To do
- so, the context of the interrupted task must be saved from the CRYP registers
- to memory, and then be restored from memory to the CRYP registers.
-
- (#) To save the current context, use CRYP_SaveContext() function
- (#) To restore the saved context, use CRYP_RestoreContext() function
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Saves the CRYP peripheral Context.
- * @note This function stops DMA transfer before to save the context. After
- * restoring the context, you have to enable the DMA again (if the DMA
- * was previously used).
- * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains
- * the repository for current context.
- * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that
- * contains the configuration information for the CRYP Keys.
- * @retval None
- */
-ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
- CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
-{
- __IO uint32_t timeout = 0;
- uint32_t ckeckmask = 0, bitstatus;
- ErrorStatus status = ERROR;
-
- /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */
- CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN;
-
- /* Wait until both the IN and OUT FIFOs are empty
- (IFEM=1 and OFNE=0 in the CRYP_SR register) and the
- BUSY bit is cleared. */
-
- if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */
- {
- ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ;
- }
- else /* AES or DES */
- {
- ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE;
- }
-
- do
- {
- bitstatus = CRYP->SR & ckeckmask;
- timeout++;
- }
- while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM));
-
- if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM)
- {
- status = ERROR;
- }
- else
- {
- /* Stop DMA transfers on the OUT FIFO by
- - writing the DOEN bit to 0 in the CRYP_DMACR register
- - and clear the CRYPEN bit. */
-
- CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN;
- CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN;
-
- /* Save the current configuration (bit 19, bit[17:16] and bits [9:2] in the CRYP_CR register) */
- CRYP_ContextSave->CR_CurrentConfig = CRYP->CR & (CRYP_CR_GCM_CCMPH |
- CRYP_CR_KEYSIZE |
- CRYP_CR_DATATYPE |
- CRYP_CR_ALGOMODE |
- CRYP_CR_ALGODIR);
-
- /* and, if not in ECB mode, the initialization vectors. */
- CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR;
- CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR;
- CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR;
- CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR;
-
- /* save The key value */
- CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;
- CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;
- CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;
- CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;
- CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;
- CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;
- CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
- CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
-
- /* Save the content of context swap registers */
- CRYP_ContextSave->CRYP_CSGCMCCMR[0] = CRYP->CSGCMCCM0R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[1] = CRYP->CSGCMCCM1R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[2] = CRYP->CSGCMCCM2R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[3] = CRYP->CSGCMCCM3R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[4] = CRYP->CSGCMCCM4R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[5] = CRYP->CSGCMCCM5R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[6] = CRYP->CSGCMCCM6R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[7] = CRYP->CSGCMCCM7R;
-
- CRYP_ContextSave->CRYP_CSGCMR[0] = CRYP->CSGCM0R;
- CRYP_ContextSave->CRYP_CSGCMR[1] = CRYP->CSGCM1R;
- CRYP_ContextSave->CRYP_CSGCMR[2] = CRYP->CSGCM2R;
- CRYP_ContextSave->CRYP_CSGCMR[3] = CRYP->CSGCM3R;
- CRYP_ContextSave->CRYP_CSGCMR[4] = CRYP->CSGCM4R;
- CRYP_ContextSave->CRYP_CSGCMR[5] = CRYP->CSGCM5R;
- CRYP_ContextSave->CRYP_CSGCMR[6] = CRYP->CSGCM6R;
- CRYP_ContextSave->CRYP_CSGCMR[7] = CRYP->CSGCM7R;
-
- /* When needed, save the DMA status (pointers for IN and OUT messages,
- number of remaining bytes, etc.) */
-
- status = SUCCESS;
- }
-
- return status;
-}
-
-/**
- * @brief Restores the CRYP peripheral Context.
- * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function,
- * after restoring the context, you have to enable the DMA again (if the
- * DMA was previously used).
- * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains
- * the repository for saved context.
- * @note The data that were saved during context saving must be rewrited into
- * the IN FIFO.
- * @retval None
- */
-void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore)
-{
-
- /* Configure the processor with the saved configuration */
- CRYP->CR = CRYP_ContextRestore->CR_CurrentConfig;
-
- /* restore The key value */
- CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR;
- CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR;
- CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR;
- CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR;
- CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR;
- CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR;
- CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR;
- CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR;
-
- /* and the initialization vectors. */
- CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR;
- CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR;
- CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR;
- CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR;
-
- /* Restore the content of context swap registers */
- CRYP->CSGCMCCM0R = CRYP_ContextRestore->CRYP_CSGCMCCMR[0];
- CRYP->CSGCMCCM1R = CRYP_ContextRestore->CRYP_CSGCMCCMR[1];
- CRYP->CSGCMCCM2R = CRYP_ContextRestore->CRYP_CSGCMCCMR[2];
- CRYP->CSGCMCCM3R = CRYP_ContextRestore->CRYP_CSGCMCCMR[3];
- CRYP->CSGCMCCM4R = CRYP_ContextRestore->CRYP_CSGCMCCMR[4];
- CRYP->CSGCMCCM5R = CRYP_ContextRestore->CRYP_CSGCMCCMR[5];
- CRYP->CSGCMCCM6R = CRYP_ContextRestore->CRYP_CSGCMCCMR[6];
- CRYP->CSGCMCCM7R = CRYP_ContextRestore->CRYP_CSGCMCCMR[7];
-
- CRYP->CSGCM0R = CRYP_ContextRestore->CRYP_CSGCMR[0];
- CRYP->CSGCM1R = CRYP_ContextRestore->CRYP_CSGCMR[1];
- CRYP->CSGCM2R = CRYP_ContextRestore->CRYP_CSGCMR[2];
- CRYP->CSGCM3R = CRYP_ContextRestore->CRYP_CSGCMR[3];
- CRYP->CSGCM4R = CRYP_ContextRestore->CRYP_CSGCMR[4];
- CRYP->CSGCM5R = CRYP_ContextRestore->CRYP_CSGCMR[5];
- CRYP->CSGCM6R = CRYP_ContextRestore->CRYP_CSGCMR[6];
- CRYP->CSGCM7R = CRYP_ContextRestore->CRYP_CSGCMR[7];
-
- /* Enable the cryptographic processor */
- CRYP->CR |= CRYP_CR_CRYPEN;
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function
- * @brief CRYP's DMA interface Configuration function
- *
-@verbatim
- ===============================================================================
- ##### CRYP's DMA interface Configuration function #####
- ===============================================================================
- [..] This section provides functions allowing to configure the DMA interface for
- CRYP data input and output transfer.
-
- [..] When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be
- transferred:
- (+) From memory to the CRYP IN FIFO using the DMA peripheral by enabling
- the CRYP_DMAReq_DataIN request.
- (+) From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling
- the CRYP_DMAReq_DataOUT request.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the CRYP DMA interface.
- * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer
- * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer
- * @param NewState: new state of the selected CRYP DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CRYP DMA request */
- CRYP->DMACR |= CRYP_DMAReq;
- }
- else
- {
- /* Disable the selected CRYP DMA request */
- CRYP->DMACR &= (uint8_t)~CRYP_DMAReq;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the CRYP Interrupts and
- to get the status and Interrupts pending bits.
-
- [..] The CRYP provides 2 Interrupts sources and 7 Flags:
-
- *** Flags : ***
- ===============
- [..]
- (#) CRYP_FLAG_IFEM : Set when Input FIFO is empty. This Flag is cleared only
- by hardware.
-
- (#) CRYP_FLAG_IFNF : Set when Input FIFO is not full. This Flag is cleared
- only by hardware.
-
-
- (#) CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending it gives
- the raw interrupt state prior to masking of the input FIFO service interrupt.
- This Flag is cleared only by hardware.
-
- (#) CRYP_FLAG_OFNE : Set when Output FIFO not empty. This Flag is cleared
- only by hardware.
-
- (#) CRYP_FLAG_OFFU : Set when Output FIFO is full. This Flag is cleared only
- by hardware.
-
- (#) CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending it gives
- the raw interrupt state prior to masking of the output FIFO service interrupt.
- This Flag is cleared only by hardware.
-
- (#) CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a block
- of data or a key preparation (for AES decryption). This Flag is cleared
- only by hardware. To clear it, the CRYP core must be disabled and the last
- processing has completed.
-
- *** Interrupts : ***
- ====================
- [..]
- (#) CRYP_IT_INI : The input FIFO service interrupt is asserted when there
- are less than 4 words in the input FIFO. This interrupt is associated to
- CRYP_FLAG_INRIS flag.
-
- -@- This interrupt is cleared by performing write operations to the input FIFO
- until it holds 4 or more words. The input FIFO service interrupt INMIS is
- enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the
- INMIS signal is low even if the input FIFO is empty.
-
-
-
- (#) CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there
- is one or more (32-bit word) data items in the output FIFO. This interrupt
- is associated to CRYP_FLAG_OUTRIS flag.
-
- -@- This interrupt is cleared by reading data from the output FIFO until there
- is no valid (32-bit) word left (that is, the interrupt follows the state
- of the OFNE (output FIFO not empty) flag).
-
- *** Managing the CRYP controller events : ***
- =============================================
- [..] The user should identify which mode will be used in his application to manage
- the CRYP controller events: Polling mode or Interrupt mode.
-
- (#) In the Polling Mode it is advised to use the following functions:
- (++) CRYP_GetFlagStatus() : to check if flags events occur.
-
- -@@- The CRYPT flags do not need to be cleared since they are cleared as
- soon as the associated event are reset.
-
-
- (#) In the Interrupt Mode it is advised to use the following functions:
- (++) CRYP_ITConfig() : to enable or disable the interrupt source.
- (++) CRYP_GetITStatus() : to check if Interrupt occurs.
-
- -@@- The CRYPT interrupts have no pending bits, the interrupt is cleared as
- soon as the associated event is reset.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified CRYP interrupts.
- * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg CRYP_IT_INI: Input FIFO interrupt
- * @arg CRYP_IT_OUTI: Output FIFO interrupt
- * @param NewState: new state of the specified CRYP interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CRYP_CONFIG_IT(CRYP_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CRYP interrupt */
- CRYP->IMSCR |= CRYP_IT;
- }
- else
- {
- /* Disable the selected CRYP interrupt */
- CRYP->IMSCR &= (uint8_t)~CRYP_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified CRYP interrupt has occurred or not.
- * @note This function checks the status of the masked interrupt (i.e the
- * interrupt should be previously enabled).
- * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CRYP_IT_INI: Input FIFO interrupt
- * @arg CRYP_IT_OUTI: Output FIFO interrupt
- * @retval The new state of CRYP_IT (SET or RESET).
- */
-ITStatus CRYP_GetITStatus(uint8_t CRYP_IT)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_CRYP_GET_IT(CRYP_IT));
-
- /* Check the status of the specified CRYP interrupt */
- if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET)
- {
- /* CRYP_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* CRYP_IT is reset */
- bitstatus = RESET;
- }
- /* Return the CRYP_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Returns whether CRYP peripheral is enabled or disabled.
- * @param none.
- * @retval Current state of the CRYP peripheral (ENABLE or DISABLE).
- */
-FunctionalState CRYP_GetCmdStatus(void)
-{
- FunctionalState state = DISABLE;
-
- if ((CRYP->CR & CRYP_CR_CRYPEN) != 0)
- {
- /* CRYPEN bit is set */
- state = ENABLE;
- }
- else
- {
- /* CRYPEN bit is reset */
- state = DISABLE;
- }
- return state;
-}
-
-/**
- * @brief Checks whether the specified CRYP flag is set or not.
- * @param CRYP_FLAG: specifies the CRYP flag to check.
- * This parameter can be one of the following values:
- * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag.
- * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag.
- * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag.
- * @arg CRYP_FLAG_OFFU: Output FIFO Full flag.
- * @arg CRYP_FLAG_BUSY: Busy flag.
- * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag.
- * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag.
- * @retval The new state of CRYP_FLAG (SET or RESET).
- */
-FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tempreg = 0;
-
- /* Check the parameters */
- assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG));
-
- /* check if the FLAG is in RISR register */
- if ((CRYP_FLAG & FLAG_MASK) != 0x00)
- {
- tempreg = CRYP->RISR;
- }
- else /* The FLAG is in SR register */
- {
- tempreg = CRYP->SR;
- }
-
-
- /* Check the status of the specified CRYP flag */
- if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET)
- {
- /* CRYP_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CRYP_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the CRYP_FLAG status */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
deleted file mode 100644
index 4c5920b5..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
+++ /dev/null
@@ -1,1676 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_cryp_aes.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides high level functions to encrypt and decrypt an
- * input message using AES in ECB/CBC/CTR/GCM/CCM modes.
- * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
- * peripheral.
- * AES-ECB/CBC/CTR/GCM/CCM modes are available on STM32F437x Devices.
- * For STM32F41xx Devices, only AES-ECB/CBC/CTR modes are available.
- *
-@verbatim
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable The CRYP controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
-
- (#) Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() function.
-
- (#) Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() function.
-
- (#) Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() function.
-
- (#) Encrypt and decrypt using AES in GCM Mode using CRYP_AES_GCM() function.
-
- (#) Encrypt and decrypt using AES in CCM Mode using CRYP_AES_CCM() function.
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dbgmcu.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DBGMCU
- * @brief DBGMCU driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Private_Functions
- * @{
- */
-
-/**
- * @brief Returns the device revision identifier.
- * @param None
- * @retval Device revision identifier
- */
-uint32_t DBGMCU_GetREVID(void)
-{
- return(DBGMCU->IDCODE >> 16);
-}
-
-/**
- * @brief Returns the device identifier.
- * @param None
- * @retval Device identifier
- */
-uint32_t DBGMCU_GetDEVID(void)
-{
- return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
-}
-
-/**
- * @brief Configures low power mode behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the low power mode.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
- * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
- * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
- * @param NewState: new state of the specified low power mode in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- DBGMCU->CR |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->CR &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB1 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
- * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
- * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
- * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
- * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
- * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
- * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
- * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
- * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
- * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted.
- * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
- * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
- * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted
- * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB1FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB1FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB2 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
- * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
- * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
- * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
- * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
- * @param NewState: new state of the specified peripheral in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB2FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB2FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
deleted file mode 100644
index d6eef0b9..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
+++ /dev/null
@@ -1,538 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dcmi.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the DCMI peripheral:
- * + Initialization and Configuration
- * + Image capture functions
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The sequence below describes how to use this driver to capture image
- from a camera module connected to the DCMI Interface.
- This sequence does not take into account the configuration of the
- camera module, which should be made before to configure and enable
- the DCMI to capture images.
-
- (#) Enable the clock for the DCMI and associated GPIOs using the following
- functions:
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) DCMI pins configuration
- (++) Connect the involved DCMI pins to AF13 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI);
- (++) Configure these DCMI pins in alternate function mode by calling
- the function GPIO_Init();
-
- (#) Declare a DCMI_InitTypeDef structure, for example:
- DCMI_InitTypeDef DCMI_InitStructure;
- and fill the DCMI_InitStructure variable with the allowed values
- of the structure member.
-
- (#) Initialize the DCMI interface by calling the function
- DCMI_Init(&DCMI_InitStructure);
-
- (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
- register to the destination memory buffer.
-
- (#) Enable DCMI interface using the function
- DCMI_Cmd(ENABLE);
-
- (#) Start the image capture using the function
- DCMI_CaptureCmd(ENABLE);
-
- (#) At this stage the DCMI interface waits for the first start of frame,
- then a DMA request is generated continuously/once (depending on the
- mode used, Continuous/Snapshot) to transfer the received data into
- the destination memory.
-
- -@- If you need to capture only a rectangular window from the received
- image, you have to use the DCMI_CROPConfig() function to configure
- the coordinates and size of the window to be captured, then enable
- the Crop feature using DCMI_CROPCmd(ENABLE);
- In this case, the Crop configuration should be made before to enable
- and start the DCMI interface.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DCMI
- * @brief DCMI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DCMI_Private_Functions
- * @{
- */
-
-/** @defgroup DCMI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the DCMI registers to their default reset values.
- * @param None
- * @retval None
- */
-void DCMI_DeInit(void)
-{
- DCMI->CR = 0x0;
- DCMI->IER = 0x0;
- DCMI->ICR = 0x1F;
- DCMI->ESCR = 0x0;
- DCMI->ESUR = 0x0;
- DCMI->CWSTRTR = 0x0;
- DCMI->CWSIZER = 0x0;
-}
-
-/**
- * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct.
- * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains
- * the configuration information for the DCMI.
- * @retval None
- */
-void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct)
-{
- uint32_t temp = 0x0;
-
- /* Check the parameters */
- assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode));
- assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode));
- assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity));
- assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity));
- assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity));
- assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate));
- assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode));
-
- /* The DCMI configuration registers should be programmed correctly before
- enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */
- DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE);
-
- /* Reset the old DCMI configuration */
- temp = DCMI->CR;
-
- temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL |
- DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 |
- DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1);
-
- /* Sets the new configuration of the DCMI peripheral */
- temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode |
- DCMI_InitStruct->DCMI_SynchroMode |
- DCMI_InitStruct->DCMI_PCKPolarity |
- DCMI_InitStruct->DCMI_VSPolarity |
- DCMI_InitStruct->DCMI_HSPolarity |
- DCMI_InitStruct->DCMI_CaptureRate |
- DCMI_InitStruct->DCMI_ExtendedDataMode);
-
- DCMI->CR = temp;
-}
-
-/**
- * @brief Fills each DCMI_InitStruct member with its default value.
- * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct)
-{
- /* Set the default configuration */
- DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous;
- DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware;
- DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling;
- DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low;
- DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low;
- DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame;
- DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b;
-}
-
-/**
- * @brief Initializes the DCMI peripheral CROP mode according to the specified
- * parameters in the DCMI_CROPInitStruct.
- * @note This function should be called before to enable and start the DCMI interface.
- * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that
- * contains the configuration information for the DCMI peripheral CROP mode.
- * @retval None
- */
-void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct)
-{
- /* Sets the CROP window coordinates */
- DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount |
- ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16));
-
- /* Sets the CROP window size */
- DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount |
- ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16));
-}
-
-/**
- * @brief Enables or disables the DCMI Crop feature.
- * @note This function should be called before to enable and start the DCMI interface.
- * @param NewState: new state of the DCMI Crop feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_CROPCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI Crop feature */
- DCMI->CR |= (uint32_t)DCMI_CR_CROP;
- }
- else
- {
- /* Disable the DCMI Crop feature */
- DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;
- }
-}
-
-/**
- * @brief Sets the embedded synchronization codes
- * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that
- * contains the embedded synchronization codes for the DCMI peripheral.
- * @retval None
- */
-void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct)
-{
- DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode |
- ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)|
- ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)|
- ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24));
-}
-
-/**
- * @brief Enables or disables the DCMI JPEG format.
- * @note The Crop and Embedded Synchronization features cannot be used in this mode.
- * @param NewState: new state of the DCMI JPEG format.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_JPEGCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI JPEG format */
- DCMI->CR |= (uint32_t)DCMI_CR_JPEG;
- }
- else
- {
- /* Disable the DCMI JPEG format */
- DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup DCMI_Group2 Image capture functions
- * @brief Image capture functions
- *
-@verbatim
- ===============================================================================
- ##### Image capture functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the DCMI interface.
- * @param NewState: new state of the DCMI interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI by setting ENABLE bit */
- DCMI->CR |= (uint32_t)DCMI_CR_ENABLE;
- }
- else
- {
- /* Disable the DCMI by clearing ENABLE bit */
- DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE;
- }
-}
-
-/**
- * @brief Enables or disables the DCMI Capture.
- * @param NewState: new state of the DCMI capture.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_CaptureCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI Capture */
- DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE;
- }
- else
- {
- /* Disable the DCMI Capture */
- DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE;
- }
-}
-
-/**
- * @brief Reads the data stored in the DR register.
- * @param None
- * @retval Data register value
- */
-uint32_t DCMI_ReadData(void)
-{
- return DCMI->DR;
-}
-/**
- * @}
- */
-
-/** @defgroup DCMI_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the DCMI interface interrupts.
- * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @param NewState: new state of the specified DCMI interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DCMI_CONFIG_IT(DCMI_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- DCMI->IER |= DCMI_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- DCMI->IER &= (uint16_t)(~DCMI_IT);
- }
-}
-
-/**
- * @brief Checks whether the DCMI interface flag is set or not.
- * @param DCMI_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
- * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
- * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
- * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
- * @arg DCMI_FLAG_LINERI: Line Raw flag mask
- * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask
- * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask
- * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask
- * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask
- * @arg DCMI_FLAG_LINEMI: Line Masked flag mask
- * @arg DCMI_FLAG_HSYNC: HSYNC flag mask
- * @arg DCMI_FLAG_VSYNC: VSYNC flag mask
- * @arg DCMI_FLAG_FNE: Fifo not empty flag mask
- * @retval The new state of DCMI_FLAG (SET or RESET).
- */
-FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t dcmireg, tempreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG));
-
- /* Get the DCMI register index */
- dcmireg = (((uint16_t)DCMI_FLAG) >> 12);
-
- if (dcmireg == 0x00) /* The FLAG is in RISR register */
- {
- tempreg= DCMI->RISR;
- }
- else if (dcmireg == 0x02) /* The FLAG is in SR register */
- {
- tempreg = DCMI->SR;
- }
- else /* The FLAG is in MISR register */
- {
- tempreg = DCMI->MISR;
- }
-
- if ((tempreg & DCMI_FLAG) != (uint16_t)RESET )
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the DCMI_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DCMI's pending flags.
- * @param DCMI_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
- * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
- * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
- * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
- * @arg DCMI_FLAG_LINERI: Line Raw flag mask
- * @retval None
- */
-void DCMI_ClearFlag(uint16_t DCMI_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG));
-
- /* Clear the flag by writing in the ICR register 1 in the corresponding
- Flag position*/
-
- DCMI->ICR = DCMI_FLAG;
-}
-
-/**
- * @brief Checks whether the DCMI interrupt has occurred or not.
- * @param DCMI_IT: specifies the DCMI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval The new state of DCMI_IT (SET or RESET).
- */
-ITStatus DCMI_GetITStatus(uint16_t DCMI_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t itstatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DCMI_GET_IT(DCMI_IT));
-
- itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */
-
- if ((itstatus != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the DCMI's interrupt pending bits.
- * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval None
- */
-void DCMI_ClearITPendingBit(uint16_t DCMI_IT)
-{
- /* Clear the interrupt pending Bit by writing in the ICR register 1 in the
- corresponding pending Bit position*/
-
- DCMI->ICR = DCMI_IT;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
deleted file mode 100644
index 1678c17d..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
+++ /dev/null
@@ -1,1301 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dma.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Direct Memory Access controller (DMA):
- * + Initialization and Configuration
- * + Data Counter
- * + Double Buffer mode configuration and command
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE)
- function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE)
- function for DMA2.
-
- (#) Enable and configure the peripheral to be connected to the DMA Stream
- (except for internal SRAM / FLASH memories: no initialization is
- necessary).
-
- (#) For a given Stream, program the required configuration through following parameters:
- Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination
- data formats, Circular or Normal mode, Stream Priority level, Source and Destination
- Incrementation mode, FIFO mode and its Threshold (if needed), Burst
- mode for Source and/or Destination (if needed) using the DMA_Init() function.
- To avoid filling unneccessary fields, you can call DMA_StructInit() function
- to initialize a given structure with default values (reset values), the modify
- only necessary fields
- (ie. Source and Destination addresses, Transfer size and Data Formats).
-
- (#) Enable the NVIC and the corresponding interrupt(s) using the function
- DMA_ITConfig() if you need to use DMA interrupts.
-
- (#) Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring
- the second Memory address and the first Memory to be used through the function
- DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function
- DMA_DoubleBufferModeCmd(). These operations must be done before step 6.
-
- (#) Enable the DMA stream using the DMA_Cmd() function.
-
- (#) Activate the needed Stream Request using PPP_DMACmd() function for
- any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
- The function allowing this operation is provided in each PPP peripheral
- driver (ie. SPI_DMACmd for SPI peripheral).
- Once the Stream is enabled, it is not possible to modify its configuration
- unless the stream is stopped and disabled.
- After enabling the Stream, it is advised to monitor the EN bit status using
- the function DMA_GetCmdStatus(). In case of configuration errors or bus errors
- this bit will remain reset and all transfers on this Stream will remain on hold.
-
- (#) Optionally, you can configure the number of data to be transferred
- when the Stream is disabled (ie. after each Transfer Complete event
- or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
- And you can get the number of remaining data to be transferred using
- the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is
- enabled and running).
-
- (#) To control DMA events you can use one of the following two methods:
- (##) Check on DMA Stream flags using the function DMA_GetFlagStatus().
- (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
- phase and DMA_GetITStatus() function into interrupt routines in
- communication phase.
- [..]
- After checking on a flag you should clear it using DMA_ClearFlag()
- function. And after checking on an interrupt event you should
- clear it using DMA_ClearITPendingBit() function.
-
- (#) Optionally, if Circular mode and Double Buffer mode are enabled, you can modify
- the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that
- the Memory Address to be modified is not the one currently in use by DMA Stream.
- This condition can be monitored using the function DMA_GetCurrentMemoryTarget().
-
- (#) Optionally, Pause-Resume operations may be performed:
- The DMA_Cmd() function may be used to perform Pause-Resume operation.
- When a transfer is ongoing, calling this function to disable the
- Stream will cause the transfer to be paused. All configuration registers
- and the number of remaining data will be preserved. When calling again
- this function to re-enable the Stream, the transfer will be resumed from
- the point where it was paused.
-
- -@- Memory-to-Memory transfer is possible by setting the address of the memory into
- the Peripheral registers. In this mode, Circular mode and Double Buffer mode
- are not allowed.
-
- -@- The FIFO is used mainly to reduce bus usage and to allow data
- packing/unpacking: it is possible to set different Data Sizes for
- the Peripheral and the Memory (ie. you can set Half-Word data size
- for the peripheral to access its data register and set Word data size
- for the Memory to gain in access time. Each two Half-words will be
- packed and written in a single access to a Word in the Memory).
-
- -@- When FIFO is disabled, it is not allowed to configure different
- Data Sizes for Source and Destination. In this case the Peripheral
- Data Size will be applied to both Source and Destination.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dma.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DMA
- * @brief DMA driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Masks Definition */
-#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \
- DMA_SxCR_TEIE | DMA_SxCR_DMEIE)
-
-#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \
- DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \
- DMA_LISR_TCIF0)
-
-#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6)
-#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16)
-#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22)
-#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000)
-#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000)
-#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000)
-#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000)
-#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C
-#define HIGH_ISR_MASK (uint32_t)0x20000000
-#define RESERVED_MASK (uint32_t)0x0F7D0F7D
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-
-/** @defgroup DMA_Private_Functions
- * @{
- */
-
-/** @defgroup DMA_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to initialize the DMA Stream source
- and destination addresses, incrementation and data sizes, transfer direction,
- buffer size, circular/normal mode selection, memory-to-memory mode selection
- and Stream priority value.
- [..]
- The DMA_Init() function follows the DMA configuration procedures as described in
- reference manual (RM0090) except the first point: waiting on EN bit to be reset.
- This condition should be checked by user application using the function DMA_GetCmdStatus()
- before calling the DMA_Init() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitialize the DMAy Streamx registers to their default reset values.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval None
- */
-void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Disable the selected DMAy Streamx */
- DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN);
-
- /* Reset DMAy Streamx control register */
- DMAy_Streamx->CR = 0;
-
- /* Reset DMAy Streamx Number of Data to Transfer register */
- DMAy_Streamx->NDTR = 0;
-
- /* Reset DMAy Streamx peripheral address register */
- DMAy_Streamx->PAR = 0;
-
- /* Reset DMAy Streamx memory 0 address register */
- DMAy_Streamx->M0AR = 0;
-
- /* Reset DMAy Streamx memory 1 address register */
- DMAy_Streamx->M1AR = 0;
-
- /* Reset DMAy Streamx FIFO control register */
- DMAy_Streamx->FCR = (uint32_t)0x00000021;
-
- /* Reset interrupt pending bits for the selected stream */
- if (DMAy_Streamx == DMA1_Stream0)
- {
- /* Reset interrupt pending bits for DMA1 Stream0 */
- DMA1->LIFCR = DMA_Stream0_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream1)
- {
- /* Reset interrupt pending bits for DMA1 Stream1 */
- DMA1->LIFCR = DMA_Stream1_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream2)
- {
- /* Reset interrupt pending bits for DMA1 Stream2 */
- DMA1->LIFCR = DMA_Stream2_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream3)
- {
- /* Reset interrupt pending bits for DMA1 Stream3 */
- DMA1->LIFCR = DMA_Stream3_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream4)
- {
- /* Reset interrupt pending bits for DMA1 Stream4 */
- DMA1->HIFCR = DMA_Stream4_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream5)
- {
- /* Reset interrupt pending bits for DMA1 Stream5 */
- DMA1->HIFCR = DMA_Stream5_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream6)
- {
- /* Reset interrupt pending bits for DMA1 Stream6 */
- DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream7)
- {
- /* Reset interrupt pending bits for DMA1 Stream7 */
- DMA1->HIFCR = DMA_Stream7_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream0)
- {
- /* Reset interrupt pending bits for DMA2 Stream0 */
- DMA2->LIFCR = DMA_Stream0_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream1)
- {
- /* Reset interrupt pending bits for DMA2 Stream1 */
- DMA2->LIFCR = DMA_Stream1_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream2)
- {
- /* Reset interrupt pending bits for DMA2 Stream2 */
- DMA2->LIFCR = DMA_Stream2_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream3)
- {
- /* Reset interrupt pending bits for DMA2 Stream3 */
- DMA2->LIFCR = DMA_Stream3_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream4)
- {
- /* Reset interrupt pending bits for DMA2 Stream4 */
- DMA2->HIFCR = DMA_Stream4_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream5)
- {
- /* Reset interrupt pending bits for DMA2 Stream5 */
- DMA2->HIFCR = DMA_Stream5_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream6)
- {
- /* Reset interrupt pending bits for DMA2 Stream6 */
- DMA2->HIFCR = DMA_Stream6_IT_MASK;
- }
- else
- {
- if (DMAy_Streamx == DMA2_Stream7)
- {
- /* Reset interrupt pending bits for DMA2 Stream7 */
- DMA2->HIFCR = DMA_Stream7_IT_MASK;
- }
- }
-}
-
-/**
- * @brief Initializes the DMAy Streamx according to the specified parameters in
- * the DMA_InitStruct structure.
- * @note Before calling this function, it is recommended to check that the Stream
- * is actually disabled using the function DMA_GetCmdStatus().
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval None
- */
-void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel));
- assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR));
- assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
- assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode));
- assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold));
- assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst));
- assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst));
-
- /*------------------------- DMAy Streamx CR Configuration ------------------*/
- /* Get the DMAy_Streamx CR value */
- tmpreg = DMAy_Streamx->CR;
-
- /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
- tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
- DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
- DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
- DMA_SxCR_DIR));
-
- /* Configure DMAy Streamx: */
- /* Set CHSEL bits according to DMA_CHSEL value */
- /* Set DIR bits according to DMA_DIR value */
- /* Set PINC bit according to DMA_PeripheralInc value */
- /* Set MINC bit according to DMA_MemoryInc value */
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */
- /* Set MSIZE bits according to DMA_MemoryDataSize value */
- /* Set CIRC bit according to DMA_Mode value */
- /* Set PL bits according to DMA_Priority value */
- /* Set MBURST bits according to DMA_MemoryBurst value */
- /* Set PBURST bits according to DMA_PeripheralBurst value */
- tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR |
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
- DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority |
- DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst;
-
- /* Write to DMAy Streamx CR register */
- DMAy_Streamx->CR = tmpreg;
-
- /*------------------------- DMAy Streamx FCR Configuration -----------------*/
- /* Get the DMAy_Streamx FCR value */
- tmpreg = DMAy_Streamx->FCR;
-
- /* Clear DMDIS and FTH bits */
- tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
-
- /* Configure DMAy Streamx FIFO:
- Set DMDIS bits according to DMA_FIFOMode value
- Set FTH bits according to DMA_FIFOThreshold value */
- tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold;
-
- /* Write to DMAy Streamx CR */
- DMAy_Streamx->FCR = tmpreg;
-
- /*------------------------- DMAy Streamx NDTR Configuration ----------------*/
- /* Write to DMAy Streamx NDTR register */
- DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize;
-
- /*------------------------- DMAy Streamx PAR Configuration -----------------*/
- /* Write to DMAy Streamx PAR */
- DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
-
- /*------------------------- DMAy Streamx M0AR Configuration ----------------*/
- /* Write to DMAy Streamx M0AR */
- DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr;
-}
-
-/**
- * @brief Fills each DMA_InitStruct member with its default value.
- * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
-{
- /*-------------- Reset DMA init structure parameters values ----------------*/
- /* Initialize the DMA_Channel member */
- DMA_InitStruct->DMA_Channel = 0;
-
- /* Initialize the DMA_PeripheralBaseAddr member */
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
-
- /* Initialize the DMA_Memory0BaseAddr member */
- DMA_InitStruct->DMA_Memory0BaseAddr = 0;
-
- /* Initialize the DMA_DIR member */
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory;
-
- /* Initialize the DMA_BufferSize member */
- DMA_InitStruct->DMA_BufferSize = 0;
-
- /* Initialize the DMA_PeripheralInc member */
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-
- /* Initialize the DMA_MemoryInc member */
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
-
- /* Initialize the DMA_PeripheralDataSize member */
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-
- /* Initialize the DMA_MemoryDataSize member */
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-
- /* Initialize the DMA_Mode member */
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
-
- /* Initialize the DMA_Priority member */
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
-
- /* Initialize the DMA_FIFOMode member */
- DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable;
-
- /* Initialize the DMA_FIFOThreshold member */
- DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
-
- /* Initialize the DMA_MemoryBurst member */
- DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single;
-
- /* Initialize the DMA_PeripheralBurst member */
- DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
-}
-
-/**
- * @brief Enables or disables the specified DMAy Streamx.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param NewState: new state of the DMAy Streamx.
- * This parameter can be: ENABLE or DISABLE.
- *
- * @note This function may be used to perform Pause-Resume operation. When a
- * transfer is ongoing, calling this function to disable the Stream will
- * cause the transfer to be paused. All configuration registers and the
- * number of remaining data will be preserved. When calling again this
- * function to re-enable the Stream, the transfer will be resumed from
- * the point where it was paused.
- *
- * @note After configuring the DMA Stream (DMA_Init() function) and enabling the
- * stream, it is recommended to check (or wait until) the DMA Stream is
- * effectively enabled. A Stream may remain disabled if a configuration
- * parameter is wrong.
- * After disabling a DMA Stream, it is also recommended to check (or wait
- * until) the DMA Stream is effectively disabled. If a Stream is disabled
- * while a data transfer is ongoing, the current data will be transferred
- * and the Stream will be effectively disabled only after the transfer of
- * this single data is finished.
- *
- * @retval None
- */
-void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMAy Streamx by setting EN bit */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN;
- }
- else
- {
- /* Disable the selected DMAy Streamx by clearing EN bit */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN;
- }
-}
-
-/**
- * @brief Configures, when the PINC (Peripheral Increment address mode) bit is
- * set, if the peripheral address should be incremented with the data
- * size (configured with PSIZE bits) or by a fixed offset equal to 4
- * (32-bit aligned addresses).
- *
- * @note This function has no effect if the Peripheral Increment mode is disabled.
- *
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_Pincos: specifies the Peripheral increment offset size.
- * This parameter can be one of the following values:
- * @arg DMA_PINCOS_Psize: Peripheral address increment is done
- * accordingly to PSIZE parameter.
- * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is
- * fixed to 4 (32-bit aligned addresses).
- * @retval None
- */
-void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos));
-
- /* Check the needed Peripheral increment offset */
- if(DMA_Pincos != DMA_PINCOS_Psize)
- {
- /* Configure DMA_SxCR_PINCOS bit with the input parameter */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS;
- }
- else
- {
- /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS;
- }
-}
-
-/**
- * @brief Configures, when the DMAy Streamx is disabled, the flow controller for
- * the next transactions (Peripheral or Memory).
- *
- * @note Before enabling this feature, check if the used peripheral supports
- * the Flow Controller mode or not.
- *
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_FlowCtrl: specifies the DMA flow controller.
- * This parameter can be one of the following values:
- * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is
- * the DMA controller.
- * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller
- * is the peripheral.
- * @retval None
- */
-void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl));
-
- /* Check the needed flow controller */
- if(DMA_FlowCtrl != DMA_FlowCtrl_Memory)
- {
- /* Configure DMA_SxCR_PFCTRL bit with the input parameter */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL;
- }
- else
- {
- /* Clear the PFCTRL bit: Memory is the flow controller */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup DMA_Group2 Data Counter functions
- * @brief Data Counter functions
- *
-@verbatim
- ===============================================================================
- ##### Data Counter functions #####
- ===============================================================================
- [..]
- This subsection provides function allowing to configure and read the buffer size
- (number of data to be transferred).
- [..]
- The DMA data counter can be written only when the DMA Stream is disabled
- (ie. after transfer complete event).
- [..]
- The following function can be used to write the Stream data counter value:
- (+) void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
- -@- It is advised to use this function rather than DMA_Init() in situations
- where only the Data buffer needs to be reloaded.
- -@- If the Source and Destination Data Sizes are different, then the value
- written in data counter, expressing the number of transfers, is relative
- to the number of transfers from the Peripheral point of view.
- ie. If Memory data size is Word, Peripheral data size is Half-Words,
- then the value to be configured in the data counter is the number
- of Half-Words to be transferred from/to the peripheral.
- [..]
- The DMA data counter can be read to indicate the number of remaining transfers for
- the relative DMA Stream. This counter is decremented at the end of each data
- transfer and when the transfer is complete:
- (+) If Normal mode is selected: the counter is set to 0.
- (+) If Circular mode is selected: the counter is reloaded with the initial value
- (configured before enabling the DMA Stream)
- [..]
- The following function can be used to read the Stream data counter value:
- (+) uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes the number of data units to be transferred on the DMAy Streamx.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param Counter: Number of data units to be transferred (from 0 to 65535)
- * Number of data items depends only on the Peripheral data format.
- *
- * @note If Peripheral data format is Bytes: number of data units is equal
- * to total number of bytes to be transferred.
- *
- * @note If Peripheral data format is Half-Word: number of data units is
- * equal to total number of bytes to be transferred / 2.
- *
- * @note If Peripheral data format is Word: number of data units is equal
- * to total number of bytes to be transferred / 4.
- *
- * @note In Memory-to-Memory transfer mode, the memory buffer pointed by
- * DMAy_SxPAR register is considered as Peripheral.
- *
- * @retval The number of remaining data units in the current DMAy Streamx transfer.
- */
-void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Write the number of data units to be transferred */
- DMAy_Streamx->NDTR = (uint16_t)Counter;
-}
-
-/**
- * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval The number of remaining data units in the current DMAy Streamx transfer.
- */
-uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Return the number of remaining data units for DMAy Streamx */
- return ((uint16_t)(DMAy_Streamx->NDTR));
-}
-/**
- * @}
- */
-
-/** @defgroup DMA_Group3 Double Buffer mode functions
- * @brief Double Buffer mode functions
- *
-@verbatim
- ===============================================================================
- ##### Double Buffer mode functions #####
- ===============================================================================
- [..]
- This subsection provides function allowing to configure and control the double
- buffer mode parameters.
-
- [..]
- The Double Buffer mode can be used only when Circular mode is enabled.
- The Double Buffer mode cannot be used when transferring data from Memory to Memory.
-
- [..]
- The Double Buffer mode allows to set two different Memory addresses from/to which
- the DMA controller will access alternatively (after completing transfer to/from
- target memory 0, it will start transfer to/from target memory 1).
- This allows to reduce software overhead for double buffering and reduce the CPU
- access time.
-
- [..]
- Two functions must be called before calling the DMA_Init() function:
- (+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx,
- uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory);
- (+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
-
- [..]
- DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address
- and the first Memory target from/to which the transfer will start after
- enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called
- to enable the Double Buffer mode (or disable it when it should not be used).
-
- [..]
- Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is
- stopped) to modify on of the target Memories addresses or to check wich Memory target is currently
- used:
- (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx,
- uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget);
- (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
-
- [..]
- DMA_MemoryTargetConfig() can be called to modify the base address of one of
- the two target Memories.
- The Memory of which the base address will be modified must not be currently
- be used by the DMA Stream (ie. if the DMA Stream is currently transferring
- from Memory 1 then you can only modify base address of target Memory 0 and vice versa).
- To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which
- returns the index of the Memory target currently in use by the DMA Stream.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode
- * and the current memory target.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param Memory1BaseAddr: the base address of the second buffer (Memory 1)
- * @param DMA_CurrentMemory: specifies which memory will be first buffer for
- * the transactions when the Stream will be enabled.
- * This parameter can be one of the following values:
- * @arg DMA_Memory_0: Memory 0 is the current buffer.
- * @arg DMA_Memory_1: Memory 1 is the current buffer.
- *
- * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init().
- *
- * @retval None
- */
-void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
- uint32_t DMA_CurrentMemory)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory));
-
- if (DMA_CurrentMemory != DMA_Memory_0)
- {
- /* Set Memory 1 as current memory address */
- DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT);
- }
- else
- {
- /* Set Memory 0 as current memory address */
- DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT);
- }
-
- /* Write to DMAy Streamx M1AR */
- DMAy_Streamx->M1AR = Memory1BaseAddr;
-}
-
-/**
- * @brief Enables or disables the double buffer mode for the selected DMA stream.
- * @note This function can be called only when the DMA Stream is disabled.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param NewState: new state of the DMAy Streamx double buffer mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Configure the Double Buffer mode */
- if (NewState != DISABLE)
- {
- /* Enable the Double buffer mode */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM;
- }
- else
- {
- /* Disable the Double buffer mode */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM;
- }
-}
-
-/**
- * @brief Configures the Memory address for the next buffer transfer in double
- * buffer mode (for dynamic use). This function can be called when the
- * DMA Stream is enabled and when the transfer is ongoing.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param MemoryBaseAddr: The base address of the target memory buffer
- * @param DMA_MemoryTarget: Next memory target to be used.
- * This parameter can be one of the following values:
- * @arg DMA_Memory_0: To use the memory address 0
- * @arg DMA_Memory_1: To use the memory address 1
- *
- * @note It is not allowed to modify the Base Address of a target Memory when
- * this target is involved in the current transfer. ie. If the DMA Stream
- * is currently transferring to/from Memory 1, then it not possible to
- * modify Base address of Memory 1, but it is possible to modify Base
- * address of Memory 0.
- * To know which Memory is currently used, you can use the function
- * DMA_GetCurrentMemoryTarget().
- *
- * @retval None
- */
-void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
- uint32_t DMA_MemoryTarget)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget));
-
- /* Check the Memory target to be configured */
- if (DMA_MemoryTarget != DMA_Memory_0)
- {
- /* Write to DMAy Streamx M1AR */
- DMAy_Streamx->M1AR = MemoryBaseAddr;
- }
- else
- {
- /* Write to DMAy Streamx M0AR */
- DMAy_Streamx->M0AR = MemoryBaseAddr;
- }
-}
-
-/**
- * @brief Returns the current memory target used by double buffer transfer.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval The memory target number: 0 for Memory0 or 1 for Memory1.
- */
-uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Get the current memory target */
- if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0)
- {
- /* Current memory buffer used is Memory 1 */
- tmp = 1;
- }
- else
- {
- /* Current memory buffer used is Memory 0 */
- tmp = 0;
- }
- return tmp;
-}
-/**
- * @}
- */
-
-/** @defgroup DMA_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DMA enable status
- (+) Check the FIFO status
- (+) Configure the DMA Interrupts sources and check or clear the flags or
- pending bits status.
-
- [..]
- (#) DMA Enable status:
- After configuring the DMA Stream (DMA_Init() function) and enabling
- the stream, it is recommended to check (or wait until) the DMA Stream
- is effectively enabled. A Stream may remain disabled if a configuration
- parameter is wrong. After disabling a DMA Stream, it is also recommended
- to check (or wait until) the DMA Stream is effectively disabled.
- If a Stream is disabled while a data transfer is ongoing, the current
- data will be transferred and the Stream will be effectively disabled
- only after this data transfer completion.
- To monitor this state it is possible to use the following function:
- (++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-
- (#) FIFO Status:
- It is possible to monitor the FIFO status when a transfer is ongoing
- using the following function:
- (++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-
- (#) DMA Interrupts and Flags:
- The user should identify which mode will be used in his application
- to manage the DMA controller events: Polling mode or Interrupt mode.
-
- *** Polling Mode ***
- ====================
- [..]
- Each DMA stream can be managed through 4 event Flags:
- (x : DMA Stream number )
- (#) DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred.
- (#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred.
- (#) DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred.
- (#) DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred.
- (#) DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred .
- [..]
- In this Mode it is advised to use the following functions:
- (+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
- (+) void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..]
- Each DMA Stream can be managed through 4 Interrupts:
-
- *** Interrupt Source ***
- ========================
- [..]
- (#) DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event.
- (#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event.
- (#) DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event.
- (#) DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event.
- (#) DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event.
- [..]
- In this Mode it is advised to use the following functions:
- (+) void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
- (+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
- (+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the status of EN bit for the specified DMAy Streamx.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- *
- * @note After configuring the DMA Stream (DMA_Init() function) and enabling
- * the stream, it is recommended to check (or wait until) the DMA Stream
- * is effectively enabled. A Stream may remain disabled if a configuration
- * parameter is wrong.
- * After disabling a DMA Stream, it is also recommended to check (or wait
- * until) the DMA Stream is effectively disabled. If a Stream is disabled
- * while a data transfer is ongoing, the current data will be transferred
- * and the Stream will be effectively disabled only after the transfer
- * of this single data is finished.
- *
- * @retval Current state of the DMAy Streamx (ENABLE or DISABLE).
- */
-FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- FunctionalState state = DISABLE;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0)
- {
- /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */
- state = ENABLE;
- }
- else
- {
- /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and
- all transfers are complete) */
- state = DISABLE;
- }
- return state;
-}
-
-/**
- * @brief Returns the current DMAy Streamx FIFO filled level.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval The FIFO filling state.
- * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
- * and not empty.
- * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
- * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
- * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
- * - DMA_FIFOStatus_Empty: when FIFO is empty
- * - DMA_FIFOStatus_Full: when FIFO is full
- */
-uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Get the FIFO level bits */
- tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS));
-
- return tmpreg;
-}
-
-/**
- * @brief Checks whether the specified DMAy Streamx flag is set or not.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag
- * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Streamx transfer error flag
- * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
- * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval The new state of DMA_FLAG (SET or RESET).
- */
-FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
-{
- FlagStatus bitstatus = RESET;
- DMA_TypeDef* DMAy;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if the flag is in HISR or LISR */
- if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Get DMAy HISR register value */
- tmpreg = DMAy->HISR;
- }
- else
- {
- /* Get DMAy LISR register value */
- tmpreg = DMAy->LISR;
- }
-
- /* Mask the reserved bits */
- tmpreg &= (uint32_t)RESERVED_MASK;
-
- /* Check the status of the specified DMA flag */
- if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
- {
- /* DMA_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the DMA_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Streamx's pending flags.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag
- * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Streamx transfer error flag
- * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
- * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval None
- */
-void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
-{
- DMA_TypeDef* DMAy;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if LIFCR or HIFCR register is targeted */
- if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Set DMAy HIFCR register clear flag bits */
- DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
- }
- else
- {
- /* Set DMAy LIFCR register clear flag bits */
- DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
- }
-}
-
-/**
- * @brief Enables or disables the specified DMAy Streamx interrupts.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @arg DMA_IT_FE: FIFO error interrupt mask
- * @param NewState: new state of the specified DMA interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Check if the DMA_IT parameter contains a FIFO interrupt */
- if ((DMA_IT & DMA_IT_FE) != 0)
- {
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA FIFO interrupts */
- DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE;
- }
- else
- {
- /* Disable the selected DMA FIFO interrupts */
- DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE;
- }
- }
-
- /* Check if the DMA_IT parameter contains a Transfer interrupt */
- if (DMA_IT != DMA_IT_FE)
- {
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA transfer interrupts */
- DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
- }
- else
- {
- /* Disable the selected DMA transfer interrupts */
- DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
- }
- }
-}
-
-/**
- * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_IT: specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt
- * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt
- * @arg DMA_IT_TEIFx: Streamx transfer error interrupt
- * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
- * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval The new state of DMA_IT (SET or RESET).
- */
-ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
-{
- ITStatus bitstatus = RESET;
- DMA_TypeDef* DMAy;
- uint32_t tmpreg = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_GET_IT(DMA_IT));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if the interrupt enable bit is in the CR or FCR register */
- if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
- {
- /* Get the interrupt enable position mask in CR register */
- tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);
-
- /* Check the enable bit in CR register */
- enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
- }
- else
- {
- /* Check the enable bit in FCR register */
- enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE);
- }
-
- /* Check if the interrupt pending flag is in LISR or HISR */
- if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Get DMAy HISR register value */
- tmpreg = DMAy->HISR ;
- }
- else
- {
- /* Get DMAy LISR register value */
- tmpreg = DMAy->LISR ;
- }
-
- /* mask all reserved bits */
- tmpreg &= (uint32_t)RESERVED_MASK;
-
- /* Check the status of the specified DMA interrupt */
- if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
- {
- /* DMA_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_IT is reset */
- bitstatus = RESET;
- }
-
- /* Return the DMA_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Streamx's interrupt pending bits.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt
- * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt
- * @arg DMA_IT_TEIFx: Streamx transfer error interrupt
- * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
- * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval None
- */
-void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
-{
- DMA_TypeDef* DMAy;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CLEAR_IT(DMA_IT));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if LIFCR or HIFCR register is targeted */
- if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Set DMAy HIFCR register clear interrupt bits */
- DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
- }
- else
- {
- /* Set DMAy LIFCR register clear interrupt bits */
- DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
deleted file mode 100644
index 0de36e9e..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_exti.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the EXTI peripheral:
- * + Initialization and Configuration
- * + Interrupts and flags management
- *
-@verbatim
-
- ===================================================================
- ##### EXTI features #####
- ===================================================================
-
- [..] External interrupt/event lines are mapped as following:
- (#) All available GPIO pins are connected to the 16 external
- interrupt/event lines from EXTI0 to EXTI15.
- (#) EXTI line 16 is connected to the PVD Output
- (#) EXTI line 17 is connected to the RTC Alarm event
- (#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event
- (#) EXTI line 19 is connected to the Ethernet Wakeup event
- (#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event
- (#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events
- (#) EXTI line 22 is connected to the RTC Wakeup event
-
-
- ##### How to use this driver #####
- ===================================================================
-
- [..] In order to use an I/O pin as an external interrupt source, follow steps
- below:
- (#) Configure the I/O in input mode using GPIO_Init()
- (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
- (#) Select the mode(interrupt, event) and configure the trigger
- selection (Rising, falling or both) using EXTI_Init()
- (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
-
- [..]
- (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
- registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_flash.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FLASH
- * @brief FLASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FLASH_Private_Functions
- * @{
- */
-
-/** @defgroup FLASH_Group1 FLASH Interface configuration functions
- * @brief FLASH Interface configuration functions
- *
-
-@verbatim
- ===============================================================================
- ##### FLASH Interface configuration functions #####
- ===============================================================================
- [..]
- This group includes the following functions:
- (+) void FLASH_SetLatency(uint32_t FLASH_Latency)
- To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device.
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
- |---------------|----------------|----------------|-----------------|-----------------|
- |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
- +-------------------------------------------------------------------------------------+
-
- [..]
- +-------------------------------------------------------------------------------------------------------------------+
- | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V |
- |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
- |Max Parallelism| x32 | x16 | x8 | x64 |
- |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
- |PSIZE[1:0] | 10 | 01 | 00 | 11 |
- +-------------------------------------------------------------------------------------------------------------------+
- -@- When VOS bit (in PWR_CR register) is reset to 0 , the maximum value of HCLK is 144 MHz.
- You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
- -@- On STM32F40xx/41xx devices:
- (++) when VOS = '0', the maximum value of fHCLK = 144MHz.
- (++) when VOS = '1', the maximum value of fHCLK = 168MHz.
- [..]
- On STM32F427x/437x devices:
- (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz.
- (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz.
- (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz
- You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
-
- (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
- (+) void FLASH_InstructionCacheCmd(FunctionalState NewState)
- (+) void FLASH_DataCacheCmd(FunctionalState NewState)
- (+) void FLASH_InstructionCacheReset(void)
- (+) void FLASH_DataCacheReset(void)
-
- [..]
- The unlock sequence is not needed for these functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the code latency value.
- * @param FLASH_Latency: specifies the FLASH Latency value.
- * This parameter can be one of the following values:
- * @arg FLASH_Latency_0: FLASH Zero Latency cycle
- * @arg FLASH_Latency_1: FLASH One Latency cycle
- * @arg FLASH_Latency_2: FLASH Two Latency cycles
- * @arg FLASH_Latency_3: FLASH Three Latency cycles
- * @arg FLASH_Latency_4: FLASH Four Latency cycles
- * @arg FLASH_Latency_5: FLASH Five Latency cycles
- * @arg FLASH_Latency_6: FLASH Six Latency cycles
- * @arg FLASH_Latency_7: FLASH Seven Latency cycles
- * For STM32F40xx/41xx and STM32F427x/437x devices this parameter can be
- * a value between FLASH_Latency_0 and FLASH_Latency_7.
- * @retval None
- */
-void FLASH_SetLatency(uint32_t FLASH_Latency)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));
-
- /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */
- *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;
-}
-
-/**
- * @brief Enables or disables the Prefetch Buffer.
- * @param NewState: new state of the Prefetch Buffer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_PrefetchBufferCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Enable or disable the Prefetch Buffer */
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_PRFTEN;
- }
- else
- {
- FLASH->ACR &= (~FLASH_ACR_PRFTEN);
- }
-}
-
-/**
- * @brief Enables or disables the Instruction Cache feature.
- * @param NewState: new state of the Instruction Cache.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_InstructionCacheCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_ICEN;
- }
- else
- {
- FLASH->ACR &= (~FLASH_ACR_ICEN);
- }
-}
-
-/**
- * @brief Enables or disables the Data Cache feature.
- * @param NewState: new state of the Data Cache.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_DataCacheCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_DCEN;
- }
- else
- {
- FLASH->ACR &= (~FLASH_ACR_DCEN);
- }
-}
-
-/**
- * @brief Resets the Instruction Cache.
- * @note This function must be used only when the Instruction Cache is disabled.
- * @param None
- * @retval None
- */
-void FLASH_InstructionCacheReset(void)
-{
- FLASH->ACR |= FLASH_ACR_ICRST;
-}
-
-/**
- * @brief Resets the Data Cache.
- * @note This function must be used only when the Data Cache is disabled.
- * @param None
- * @retval None
- */
-void FLASH_DataCacheReset(void)
-{
- FLASH->ACR |= FLASH_ACR_DCRST;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group2 FLASH Memory Programming functions
- * @brief FLASH Memory Programming functions
- *
-@verbatim
- ===============================================================================
- ##### FLASH Memory Programming functions #####
- ===============================================================================
- [..]
- This group includes the following functions:
- (+) void FLASH_Unlock(void)
- (+) void FLASH_Lock(void)
- (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
- (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
- (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
- (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
- (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
- (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
- [..]
- Any operation of erase or program should follow these steps:
- (#) Call the FLASH_Unlock() function to enable the FLASH control register access
-
- (#) Call the desired function to erase sector(s) or program data
-
- (#) Call the FLASH_Lock() function to disable the FLASH control register access
- (recommended to protect the FLASH memory against possible unwanted operation)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the FLASH control register access
- * @param None
- * @retval None
- */
-void FLASH_Unlock(void)
-{
- if((FLASH->CR & FLASH_CR_LOCK) != RESET)
- {
- /* Authorize the FLASH Registers access */
- FLASH->KEYR = FLASH_KEY1;
- FLASH->KEYR = FLASH_KEY2;
- }
-}
-
-/**
- * @brief Locks the FLASH control register access
- * @param None
- * @retval None
- */
-void FLASH_Lock(void)
-{
- /* Set the LOCK Bit to lock the FLASH Registers access */
- FLASH->CR |= FLASH_CR_LOCK;
-}
-
-/**
- * @brief Erases a specified FLASH Sector.
- *
- * @note If an erase and a program operations are requested simustaneously,
- * the erase operation is performed before the program one.
- *
- * @param FLASH_Sector: The Sector number to be erased.
- * For STM32F40xx/41xx devices this parameter can be a value between
- * FLASH_Sector_0 and FLASH_Sector_11.
- * For STM32F427x/437x devices this parameter can be a value between
- * FLASH_Sector_0 and FLASH_Sector_23.
- *
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
- * This parameter can be one of the following values:
- * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
- * the operation will be done by byte (8-bit)
- * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
- * the operation will be done by half word (16-bit)
- * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
- * the operation will be done by word (32-bit)
- * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
- * the operation will be done by double word (64-bit)
- *
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
-{
- uint32_t tmp_psize = 0x0;
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_SECTOR(FLASH_Sector));
- assert_param(IS_VOLTAGERANGE(VoltageRange));
-
- if(VoltageRange == VoltageRange_1)
- {
- tmp_psize = FLASH_PSIZE_BYTE;
- }
- else if(VoltageRange == VoltageRange_2)
- {
- tmp_psize = FLASH_PSIZE_HALF_WORD;
- }
- else if(VoltageRange == VoltageRange_3)
- {
- tmp_psize = FLASH_PSIZE_WORD;
- }
- else
- {
- tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
- }
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase the sector */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR &= SECTOR_MASK;
- FLASH->CR |= FLASH_CR_SER | FLASH_Sector;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the erase operation is completed, disable the SER Bit */
- FLASH->CR &= (~FLASH_CR_SER);
- FLASH->CR &= SECTOR_MASK;
- }
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Erases all FLASH Sectors.
- *
- * @note If an erase and a program operations are requested simustaneously,
- * the erase operation is performed before the program one.
- *
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
- * This parameter can be one of the following values:
- * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
- * the operation will be done by byte (8-bit)
- * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
- * the operation will be done by half word (16-bit)
- * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
- * the operation will be done by word (32-bit)
- * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
- * the operation will be done by double word (64-bit)
- *
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
-{
-#if defined (STM32F427X) || (STM32F40XX)
- uint32_t tmp_psize = 0x0;
-#endif
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
- assert_param(IS_VOLTAGERANGE(VoltageRange));
-
-#if defined (STM32F427X) || (STM32F40XX)
- if(VoltageRange == VoltageRange_1)
- {
- tmp_psize = FLASH_PSIZE_BYTE;
- }
- else if(VoltageRange == VoltageRange_2)
- {
- tmp_psize = FLASH_PSIZE_HALF_WORD;
- }
- else if(VoltageRange == VoltageRange_3)
- {
- tmp_psize = FLASH_PSIZE_WORD;
- }
- else
- {
- tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
- }
-#endif
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all sectors */
-#if defined (STM32F427X)
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2);
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the erase operation is completed, disable the MER Bit */
- FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2);
-#endif /* STM32F427X */
-
-#ifdef STM32F40XX
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR |= FLASH_CR_MER;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the erase operation is completed, disable the MER Bit */
- FLASH->CR &= (~FLASH_CR_MER);
-#endif /* STM32F40XX */
-
- }
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Programs a double word (64-bit) at a specified address.
- * @note This function must be used when the device voltage range is from
- * 2.7V to 3.6V and an External Vpp is present.
- *
- * @note If an erase and a program operations are requested simustaneously,
- * the erase operation is performed before the program one.
- *
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint64_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a word (32-bit) at a specified address.
- *
- * @note This function must be used when the device voltage range is from 2.7V to 3.6V.
- *
- * @note If an erase and a program operations are requested simustaneously,
- * the erase operation is performed before the program one.
- *
- * @param Address: specifies the address to be programmed.
- * This parameter can be any address in Program memory zone or in OTP zone.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_WORD;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint32_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a half word (16-bit) at a specified address.
- * @note This function must be used when the device voltage range is from 2.1V to 3.6V.
- *
- * @note If an erase and a program operations are requested simustaneously,
- * the erase operation is performed before the program one.
- *
- * @param Address: specifies the address to be programmed.
- * This parameter can be any address in Program memory zone or in OTP zone.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_HALF_WORD;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a byte (8-bit) at a specified address.
- * @note This function can be used within all the device supply voltage ranges.
- *
- * @note If an erase and a program operations are requested simustaneously,
- * the erase operation is performed before the program one.
- *
- * @param Address: specifies the address to be programmed.
- * This parameter can be any address in Program memory zone or in OTP zone.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_BYTE;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint8_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group3 Option Bytes Programming functions
- * @brief Option Bytes Programming functions
- *
-@verbatim
- ===============================================================================
- ##### Option Bytes Programming functions #####
- ===============================================================================
- [..]
- This group includes the following functions:
- (+) void FLASH_OB_Unlock(void)
- (+) void FLASH_OB_Lock(void)
- (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
- (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
- (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP)
- (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
- (+) void FLASH_OB_BORConfig(uint8_t OB_BOR)
- (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)
- (+) FLASH_Status FLASH_OB_Launch(void)
- (+) uint32_t FLASH_OB_GetUser(void)
- (+) uint8_t FLASH_OB_GetWRP(void)
- (+) uint8_t FLASH_OB_GetWRP1(void)
- (+) uint8_t FLASH_OB_GetRDP(void)
- (+) uint8_t FLASH_OB_GetBOR(void)
- [..]
- Any operation of erase or program should follow these steps:
- (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control
- register access
-
- (#) Call one or several functions to program the desired Option Bytes:
- (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
- => to Enable/Disable the desired sector write protection
- (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read
- Protection Level
- (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
- => to configure the user Option Bytes.
- (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level
-
- (#) Once all needed Option Bytes to be programmed are correctly written,
- call the FLASH_OB_Launch() function to launch the Option Bytes
- programming process.
-
- -@- When changing the IWDG mode from HW to SW or from SW to HW, a system
- reset is needed to make the change effective.
-
- (#) Call the FLASH_OB_Lock() function to disable the FLASH option control
- register access (recommended to protect the Option Bytes against
- possible unwanted operations)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the FLASH Option Control Registers access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Unlock(void)
-{
- if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
- {
- /* Authorizes the Option Byte register programming */
- FLASH->OPTKEYR = FLASH_OPT_KEY1;
- FLASH->OPTKEYR = FLASH_OPT_KEY2;
- }
-}
-
-/**
- * @brief Locks the FLASH Option Control Registers access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Lock(void)
-{
- /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
- FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
-}
-
-/**
- * @brief Enables or disables the write protection of the desired sectors
- *
- * @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase the flash sector i if CortexM4
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
- *
- * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
- * This parameter can be one of the following values:
- * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11
- * @arg OB_WRP_Sector_All
- * @param Newstate: new state of the Write Protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(OB_WRP));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- if(NewState != DISABLE)
- {
- *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);
- }
- else
- {
- *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
- }
- }
-}
-
-/**
- * @brief Enables or disables the write protection of the desired sectors
- * @note This function can be used only for STM32F427x/437x devices.
- * @note When the memory read out protection is selected (RDP level = 1),
- * it is not possible to program or erase the flash sector i if CortexM4
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
- *
- * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
- * This parameter can be one of the following values:
- * @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23
- * @arg OB_WRP_Sector_All
- * @param Newstate: new state of the Write Protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(OB_WRP));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- if(NewState != DISABLE)
- {
- *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP);
- }
- else
- {
- *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
- }
- }
-}
-
-/**
- * @brief Sets the read protection level.
- * @param OB_RDP: specifies the read protection level.
- * This parameter can be one of the following values:
- * @arg OB_RDP_Level_0: No protection
- * @arg OB_RDP_Level_1: Read protection of the memory
- * @arg OB_RDP_Level_2: Full chip protection
- *
- * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
- *
- * @retval None
- */
-void FLASH_OB_RDPConfig(uint8_t OB_RDP)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_RDP(OB_RDP));
-
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP;
-
- }
-}
-
-/**
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
- * @param OB_IWDG: Selects the IWDG mode
- * This parameter can be one of the following values:
- * @arg OB_IWDG_SW: Software IWDG selected
- * @arg OB_IWDG_HW: Hardware IWDG selected
- * @param OB_STOP: Reset event when entering STOP mode.
- * This parameter can be one of the following values:
- * @arg OB_STOP_NoRST: No reset generated when entering in STOP
- * @arg OB_STOP_RST: Reset generated when entering in STOP
- * @param OB_STDBY: Reset event when entering Standby mode.
- * This parameter can be one of the following values:
- * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
- * @retval None
- */
-void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
-{
- uint8_t optiontmp = 0xFF;
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
- optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F);
-
- /* Update User Option Byte */
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp)));
- }
-}
-
-/**
- * @brief Sets the BOR Level.
- * @param OB_BOR: specifies the Option Bytes BOR Reset Level.
- * This parameter can be one of the following values:
- * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
- * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
- * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
- * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
- * @retval None
- */
-void FLASH_OB_BORConfig(uint8_t OB_BOR)
-{
- /* Check the parameters */
- assert_param(IS_OB_BOR(OB_BOR));
-
- /* Set the BOR Level */
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR;
-
-}
-
-/**
- * @brief Launch the option byte loading.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_OB_Launch(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Set the OPTSTRT bit in OPTCR register */
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- return status;
-}
-
-/**
- * @brief Returns the FLASH User Option Bytes values.
- * @param None
- * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
- * and RST_STDBY(Bit2).
- */
-uint8_t FLASH_OB_GetUser(void)
-{
- /* Return the User Option Byte */
- return (uint8_t)(FLASH->OPTCR >> 5);
-}
-
-/**
- * @brief Returns the FLASH Write Protection Option Bytes value.
- * @param None
- * @retval The FLASH Write Protection Option Bytes value
- */
-uint16_t FLASH_OB_GetWRP(void)
-{
- /* Return the FLASH write protection Register value */
- return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
-}
-
-/**
- * @brief Returns the FLASH Write Protection Option Bytes value.
- * @note This function can be used only for STM32F427x/437x devices.
- * @param None
- * @retval The FLASH Write Protection Option Bytes value
- */
-uint16_t FLASH_OB_GetWRP1(void)
-{
- /* Return the FLASH write protection Register value */
- return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
-}
-
-/**
- * @brief Returns the FLASH Read Protection level.
- * @param None
- * @retval FLASH ReadOut Protection Status:
- * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
- * - RESET, when OB_RDP_Level_0 is set
- */
-FlagStatus FLASH_OB_GetRDP(void)
-{
- FlagStatus readstatus = RESET;
-
- if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))
- {
- readstatus = SET;
- }
- else
- {
- readstatus = RESET;
- }
- return readstatus;
-}
-
-/**
- * @brief Returns the FLASH BOR level.
- * @param None
- * @retval The FLASH BOR level:
- * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
- * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
- * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
- * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
- */
-uint8_t FLASH_OB_GetBOR(void)
-{
- /* Return the FLASH BOR level */
- return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified FLASH interrupts.
- * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_ERR: FLASH Error Interrupt
- * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
- * @retval None
- */
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_IT(FLASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR |= FLASH_IT;
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR &= ~(uint32_t)FLASH_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified FLASH flag is set or not.
- * @param FLASH_FLAG: specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
- * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
- * @arg FLASH_FLAG_BSY: FLASH Busy flag
- * @retval The new state of FLASH_FLAG (SET or RESET).
- */
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
-
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the new state of FLASH_FLAG (SET or RESET) */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FLASH's pending flags.
- * @param FLASH_FLAG: specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
- * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
- * @retval None
- */
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
-
- /* Clear the flags */
- FLASH->SR = FLASH_FLAG;
-}
-
-/**
- * @brief Returns the FLASH Status.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_GetStatus(void)
-{
- FLASH_Status flashstatus = FLASH_COMPLETE;
-
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
- {
- flashstatus = FLASH_BUSY;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_WRP;
- }
- else
- {
- if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_PROGRAM;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_OPERATION;
- }
- else
- {
- flashstatus = FLASH_COMPLETE;
- }
- }
- }
- }
- /* Return the FLASH Status */
- return flashstatus;
-}
-
-/**
- * @brief Waits for a FLASH operation to complete.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_WaitForLastOperation(void)
-{
- __IO FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the FLASH Status */
- status = FLASH_GetStatus();
-
- /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
- Even if the FLASH operation fails, the BUSY flag will be reset and an error
- flag will be set */
- while(status == FLASH_BUSY)
- {
- status = FLASH_GetStatus();
- }
- /* Return the operation status */
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
deleted file mode 100644
index c01fc629..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
+++ /dev/null
@@ -1,989 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_fsmc.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the FSMC peripheral:
- * + Interface with SRAM, PSRAM, NOR and OneNAND memories
- * + Interface with NAND memories
- * + Interface with 16-bit PC Card compatible memories
- * + Interrupts and flags management
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_gpio.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup GPIO
- * @brief GPIO driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Private_Functions
- * @{
- */
-
-/** @defgroup GPIO_Group1 Initialization and Configuration
- * @brief Initialization and Configuration
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the GPIOx peripheral registers to their default reset values.
- * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @retval None
- */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- if (GPIOx == GPIOA)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
- }
- else if (GPIOx == GPIOB)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
- }
- else if (GPIOx == GPIOC)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
- }
- else if (GPIOx == GPIOD)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
- }
- else if (GPIOx == GPIOE)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
- }
- else if (GPIOx == GPIOF)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
- }
- else if (GPIOx == GPIOG)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
- }
- else if (GPIOx == GPIOH)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
- }
- else
- {
- if (GPIOx == GPIOI)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
- assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
- assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
-
- /* ------------------------- Configure the port pins ---------------- */
- /*-- GPIO Mode Configuration --*/
- for (pinpos = 0x00; pinpos < 0x10; pinpos++)
- {
- pos = ((uint32_t)0x01) << pinpos;
- /* Get the port pins position */
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
- if (currentpin == pos)
- {
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
- GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
-
- if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
- {
- /* Check Speed mode parameters */
- assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-
- /* Speed mode configuration */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
- GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
-
- /* Check Output mode parameters */
- assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
-
- /* Output mode configuration*/
- GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
- GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
- }
-
- /* Pull-up Pull down resistor configuration*/
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
- GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
- }
- }
-}
-
-/**
- * @brief Fills each GPIO_InitStruct member with its default value.
- * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
- GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
-}
-
-/**
- * @brief Locks GPIO Pins configuration registers.
- * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
- * @note The configuration of the locked GPIO pins can no longer be modified
- * until the next reset.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: specifies the port bit to be locked.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- __IO uint32_t tmp = 0x00010000;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- tmp |= GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Reset LCKK bit */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group2 GPIO Read and Write
- * @brief GPIO Read and Write
- *
-@verbatim
- ===============================================================================
- ##### GPIO Read and Write #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_Pin_x where x can be (0..15).
- * @retval The input port pin value.
- */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO input data port.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @retval GPIO input data port value.
- */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->IDR);
-}
-
-/**
- * @brief Reads the specified output data port bit.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_Pin_x where x can be (0..15).
- * @retval The output port pin value.
- */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO output data port.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @retval GPIO output data port value.
- */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->ODR);
-}
-
-/**
- * @brief Sets the selected data port bits.
- * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: specifies the port bits to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRRL = GPIO_Pin;
-}
-
-/**
- * @brief Clears the selected data port bits.
- * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: specifies the port bits to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRRH = GPIO_Pin;
-}
-
-/**
- * @brief Sets or clears the selected data port bit.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be one of GPIO_Pin_x where x can be (0..15).
- * @param BitVal: specifies the value to be written to the selected bit.
- * This parameter can be one of the BitAction enum values:
- * @arg Bit_RESET: to clear the port pin
- * @arg Bit_SET: to set the port pin
- * @retval None
- */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
- if (BitVal != Bit_RESET)
- {
- GPIOx->BSRRL = GPIO_Pin;
- }
- else
- {
- GPIOx->BSRRH = GPIO_Pin ;
- }
-}
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param PortVal: specifies the value to be written to the port output data register.
- * @retval None
- */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR = PortVal;
-}
-
-/**
- * @brief Toggles the specified GPIO pins..
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: Specifies the pins to be toggled.
- * @retval None
- */
-void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR ^= GPIO_Pin;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
- * @brief GPIO Alternate functions configuration function
- *
-@verbatim
- ===============================================================================
- ##### GPIO Alternate functions configuration function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Changes the mapping of the specified pin.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_PinSource: specifies the pin for the Alternate function.
- * This parameter can be GPIO_PinSourcex where x can be (0..15).
- * @param GPIO_AFSelection: selects the pin to used as Alternate function.
- * This parameter can be one of the following values:
- * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset)
- * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset)
- * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset)
- * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset)
- * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
- * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
- * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
- * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
- * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
- * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
- * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
- * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
- * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
- * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
- * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
- * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
- * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
- * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
- * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
- * @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5
- * @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5
- * @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5
- * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
- * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
- * @arg GPIO_AF_USART1: Connect USART1 pins to AF7
- * @arg GPIO_AF_USART2: Connect USART2 pins to AF7
- * @arg GPIO_AF_USART3: Connect USART3 pins to AF7
- * @arg GPIO_AF_UART4: Connect UART4 pins to AF8
- * @arg GPIO_AF_UART5: Connect UART5 pins to AF8
- * @arg GPIO_AF_USART6: Connect USART6 pins to AF8
- * @arg GPIO_AF_UART7: Connect UART7 pins to AF8
- * @arg GPIO_AF_UART8: Connect UART8 pins to AF8
- * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
- * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
- * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
- * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
- * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
- * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
- * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
- * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
- * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
- * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
- * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
- * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
- * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
- * @retval None
- */
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
-{
- uint32_t temp = 0x00;
- uint32_t temp_2 = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
- assert_param(IS_GPIO_AF(GPIO_AF));
-
- temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
- GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
- temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
- GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
deleted file mode 100644
index 2bd2ae7b..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
+++ /dev/null
@@ -1,726 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hash.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the HASH / HMAC Processor (HASH) peripheral:
- * - Initialization and Configuration functions
- * - Message Digest generation functions
- * - context swapping functions
- * - DMA interface function
- * - Interrupts and flags management
- *
-@verbatim
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
-
- *** HASH operation : ***
- ========================
- [..]
- (#) Enable the HASH controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.
-
- (#) Initialise the HASH using HASH_Init() function.
-
- (#) Reset the HASH processor core, so that the HASH will be ready
- to compute he message digest of a new message by using HASH_Reset() function.
-
- (#) Enable the HASH controller using the HASH_Cmd() function.
-
- (#) if using DMA for Data input transfer, Activate the DMA Request
- using HASH_DMACmd() function
-
- (#) if DMA is not used for data transfer, use HASH_DataIn() function
- to enter data to IN FIFO.
-
-
- (#) Configure the Number of valid bits in last word of the message
- using HASH_SetLastWordValidBitsNbr() function.
-
- (#) if the message length is not an exact multiple of 512 bits,
- then the function HASH_StartDigest() must be called to launch the computation
- of the final digest.
-
- (#) Once computed, the digest can be read using HASH_GetDigest() function.
-
- (#) To control HASH events you can use one of the following wo methods:
- (++) Check on HASH flags using the HASH_GetFlagStatus() function.
- (++) Use HASH interrupts through the function HASH_ITConfig() at
- initialization phase and HASH_GetITStatus() function into
- interrupt routines in hashing phase.
- After checking on a flag you should clear it using HASH_ClearFlag()
- function. And after checking on an interrupt event you should
- clear it using HASH_ClearITPendingBit() function.
-
- (#) Save and restore hash processor context using
- HASH_SaveContext() and HASH_RestoreContext() functions.
-
-
-
- *** HMAC operation : ***
- ========================
- [..] The HMAC algorithm is used for message authentication, by
- irreversibly binding the message being processed to a key chosen
- by the user.
- For HMAC specifications, refer to "HMAC: keyed-hashing for message
- authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997"
-
- [..] Basically, the HMAC algorithm consists of two nested hash operations:
- HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)]
- where:
- (+) "pad" is a sequence of zeroes needed to extend the key to the
- length of the underlying hash function data block (that is
- 512 bits for both the SHA-1 and MD5 hash algorithms)
- (+) "|" represents the concatenation operator
-
-
- [..]To compute the HMAC, four different phases are required:
- (#) Initialise the HASH using HASH_Init() function to do HMAC
- operation.
-
- (#) The key (to be used for the inner hash function) is then given to the core.
- This operation follows the same mechanism as the one used to send the
- message in the hash operation (that is, by HASH_DataIn() function and,
- finally, HASH_StartDigest() function.
-
- (#) Once the last word has been entered and computation has started,
- the hash processor elaborates the key. It is then ready to accept the message
- text using the same mechanism as the one used to send the message in the
- hash operation.
-
- (#) After the first hash round, the hash processor returns "ready" to indicate
- that it is ready to receive the key to be used for the outer hash function
- (normally, this key is the same as the one used for the inner hash function).
- When the last word of the key is entered and computation starts, the HMAC
- result is made available using HASH_GetDigest() function.
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup HASH
- * @brief HASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HASH_Private_Functions
- * @{
- */
-
-/** @defgroup HASH_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initialize the HASH peripheral
- (+) Configure the HASH Processor
- (+) MD5/SHA1,
- (+) HASH/HMAC,
- (+) datatype
- (+) HMAC Key (if mode = HMAC)
- (+) Reset the HASH Processor
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the HASH peripheral registers to their default reset values
- * @param None
- * @retval None
- */
-void HASH_DeInit(void)
-{
- /* Enable HASH reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE);
- /* Release HASH from reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE);
-}
-
-/**
- * @brief Initializes the HASH peripheral according to the specified parameters
- * in the HASH_InitStruct structure.
- * @note the hash processor is reset when calling this function so that the
- * HASH will be ready to compute the message digest of a new message.
- * There is no need to call HASH_Reset() function.
- * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains
- * the configuration information for the HASH peripheral.
- * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only
- * if the algorithm mode is HMAC.
- * @retval None
- */
-void HASH_Init(HASH_InitTypeDef* HASH_InitStruct)
-{
- /* Check the parameters */
- assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection));
- assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType));
- assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode));
-
- /* Configure the Algorithm used, algorithm mode and the datatype */
- HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
- HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \
- HASH_InitStruct->HASH_DataType | \
- HASH_InitStruct->HASH_AlgoMode);
-
- /* if algorithm mode is HMAC, set the Key */
- if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC)
- {
- assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType));
- HASH->CR &= ~HASH_CR_LKEY;
- HASH->CR |= HASH_InitStruct->HASH_HMACKeyType;
- }
-
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
-}
-
-/**
- * @brief Fills each HASH_InitStruct member with its default value.
- * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will
- * be initialized.
- * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1,
- * Data type selected is 32b and HMAC Key Type is short key.
- * @retval None
- */
-void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct)
-{
- /* Initialize the HASH_AlgoSelection member */
- HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
-
- /* Initialize the HASH_AlgoMode member */
- HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH;
-
- /* Initialize the HASH_DataType member */
- HASH_InitStruct->HASH_DataType = HASH_DataType_32b;
-
- /* Initialize the HASH_HMACKeyType member */
- HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
-}
-
-/**
- * @brief Resets the HASH processor core, so that the HASH will be ready
- * to compute the message digest of a new message.
- * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation
- * completion interrupt status) bit corresponding to HASH_IT_DCI
- * interrupt and HASH_FLAG_DCIS flag.
- * @param None
- * @retval None
- */
-void HASH_Reset(void)
-{
- /* Reset the HASH processor core */
- HASH->CR |= HASH_CR_INIT;
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group2 Message Digest generation functions
- * @brief Message Digest generation functions
- *
-@verbatim
- ===============================================================================
- ##### Message Digest generation functions #####
- ===============================================================================
- [..] This section provides functions allowing the generation of message digest:
- (+) Push data in the IN FIFO : using HASH_DataIn()
- (+) Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr()
- (+) set the last word valid bits number using HASH_SetLastWordValidBitsNbr()
- (+) start digest calculation : using HASH_StartDigest()
- (+) Get the Digest message : using HASH_GetDigest()
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Configure the Number of valid bits in last word of the message
- * @param ValidNumber: Number of valid bits in last word of the message.
- * This parameter must be a number between 0 and 0x1F.
- * - 0x00: All 32 bits of the last data written are valid
- * - 0x01: Only bit [0] of the last data written is valid
- * - 0x02: Only bits[1:0] of the last data written are valid
- * - 0x03: Only bits[2:0] of the last data written are valid
- * - ...
- * - 0x1F: Only bits[30:0] of the last data written are valid
- * @note The Number of valid bits must be set before to start the message
- * digest competition (in Hash and HMAC) and key treatment(in HMAC).
- * @retval None
- */
-void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber)
-{
- /* Check the parameters */
- assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber));
-
- /* Configure the Number of valid bits in last word of the message */
- HASH->STR &= ~(HASH_STR_NBW);
- HASH->STR |= ValidNumber;
-}
-
-/**
- * @brief Writes data in the Data Input FIFO
- * @param Data: new data of the message to be processed.
- * @retval None
- */
-void HASH_DataIn(uint32_t Data)
-{
- /* Write in the DIN register a new data */
- HASH->DIN = Data;
-}
-
-/**
- * @brief Returns the number of words already pushed into the IN FIFO.
- * @param None
- * @retval The value of words already pushed into the IN FIFO.
- */
-uint8_t HASH_GetInFIFOWordsNbr(void)
-{
- /* Return the value of NBW bits */
- return ((HASH->CR & HASH_CR_NBW) >> 8);
-}
-
-/**
- * @brief Provides the message digest result.
- * @note In MD5 mode, Data[7] to Data[4] filed of HASH_MsgDigest structure is not used
- * and is read as zero.
- * In SHA-1 mode, Data[7] to Data[5] filed of HASH_MsgDigest structure is not used
- * and is read as zero.
- * In SHA-224 mode, Data[7] filed of HASH_MsgDigest structure is not used
- * and is read as zero.
- * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will
- * hold the message digest result
- * @retval None
- */
-void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest)
-{
- /* Get the data field */
- HASH_MessageDigest->Data[0] = HASH->HR[0];
- HASH_MessageDigest->Data[1] = HASH->HR[1];
- HASH_MessageDigest->Data[2] = HASH->HR[2];
- HASH_MessageDigest->Data[3] = HASH->HR[3];
- HASH_MessageDigest->Data[4] = HASH->HR[4];
- HASH_MessageDigest->Data[5] = HASH_DIGEST->HR[5];
- HASH_MessageDigest->Data[6] = HASH_DIGEST->HR[6];
- HASH_MessageDigest->Data[7] = HASH_DIGEST->HR[7];
-}
-
-/**
- * @brief Starts the message padding and calculation of the final message
- * @param None
- * @retval None
- */
-void HASH_StartDigest(void)
-{
- /* Start the Digest calculation */
- HASH->STR |= HASH_STR_DCAL;
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group3 Context swapping functions
- * @brief Context swapping functions
- *
-@verbatim
- ===============================================================================
- ##### Context swapping functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to save and store HASH Context
-
- [..] It is possible to interrupt a HASH/HMAC process to perform another processing
- with a higher priority, and to complete the interrupted process later on, when
- the higher priority task is complete. To do so, the context of the interrupted
- task must be saved from the HASH registers to memory, and then be restored
- from memory to the HASH registers.
-
- (#) To save the current context, use HASH_SaveContext() function
- (#) To restore the saved context, use HASH_RestoreContext() function
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Save the Hash peripheral Context.
- * @note The context can be saved only when no block is currently being
- * processed. So user must wait for DINIS = 1 (the last block has been
- * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not
- * full and no processing is ongoing).
- * @param HASH_ContextSave: pointer to a HASH_Context structure that contains
- * the repository for current context.
- * @retval None
- */
-void HASH_SaveContext(HASH_Context* HASH_ContextSave)
-{
- uint8_t i = 0;
-
- /* save context registers */
- HASH_ContextSave->HASH_IMR = HASH->IMR;
- HASH_ContextSave->HASH_STR = HASH->STR;
- HASH_ContextSave->HASH_CR = HASH->CR;
- for(i=0; i<=53;i++)
- {
- HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i];
- }
-}
-
-/**
- * @brief Restore the Hash peripheral Context.
- * @note After calling this function, user can restart the processing from the
- * point where it has been interrupted.
- * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains
- * the repository for saved context.
- * @retval None
- */
-void HASH_RestoreContext(HASH_Context* HASH_ContextRestore)
-{
- uint8_t i = 0;
-
- /* restore context registers */
- HASH->IMR = HASH_ContextRestore->HASH_IMR;
- HASH->STR = HASH_ContextRestore->HASH_STR;
- HASH->CR = HASH_ContextRestore->HASH_CR;
-
- /* Initialize the hash processor */
- HASH->CR |= HASH_CR_INIT;
-
- /* continue restoring context registers */
- for(i=0; i<=53;i++)
- {
- HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i];
- }
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group4 HASH's DMA interface Configuration function
- * @brief HASH's DMA interface Configuration function
- *
-@verbatim
- ===============================================================================
- ##### HASH's DMA interface Configuration function #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the DMA interface for
- HASH/ HMAC data input transfer.
-
- [..] When the DMA mode is enabled (using the HASH_DMACmd() function), data can be
- sent to the IN FIFO using the DMA peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables auto-start message padding and
- * calculation of the final message digest at the end of DMA transfer.
- * @param NewState: new state of the selected HASH DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HASH_AutoStartDigest(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the auto start of the final message digest at the end of DMA transfer */
- HASH->CR &= ~HASH_CR_MDMAT;
- }
- else
- {
- /* Disable the auto start of the final message digest at the end of DMA transfer */
- HASH->CR |= HASH_CR_MDMAT;
- }
-}
-
-/**
- * @brief Enables or disables the HASH DMA interface.
- * @note The DMA is disabled by hardware after the end of transfer.
- * @param NewState: new state of the selected HASH DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HASH_DMACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the HASH DMA request */
- HASH->CR |= HASH_CR_DMAE;
- }
- else
- {
- /* Disable the HASH DMA request */
- HASH->CR &= ~HASH_CR_DMAE;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the HASH Interrupts and
- to get the status and clear flags and Interrupts pending bits.
-
- [..] The HASH provides 2 Interrupts sources and 5 Flags:
-
- *** Flags : ***
- ===============
- [..]
- (#) HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO
- which means that a new block (512 bit) can be entered into the input buffer.
-
- (#) HASH_FLAG_DCIS : set when Digest calculation is complete
-
- (#) HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or
- a transfer is ongoing. This Flag is cleared only by hardware.
-
- (#) HASH_FLAG_BUSY : set when The hash core is processing a block of data
- This Flag is cleared only by hardware.
-
- (#) HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that
- the Data IN FIFO contains at least one word of data. This Flag is cleared
- only by hardware.
-
- *** Interrupts : ***
- ====================
- [..]
- (#) HASH_IT_DINI : if enabled, this interrupt source is pending when 16
- locations are free in the Data IN FIFO which means that a new block (512 bit)
- can be entered into the input buffer. This interrupt source is cleared using
- HASH_ClearITPendingBit(HASH_IT_DINI) function.
-
- (#) HASH_IT_DCI : if enabled, this interrupt source is pending when Digest
- calculation is complete. This interrupt source is cleared using
- HASH_ClearITPendingBit(HASH_IT_DCI) function.
-
- *** Managing the HASH controller events : ***
- =============================================
- [..] The user should identify which mode will be used in his application to manage
- the HASH controller events: Polling mode or Interrupt mode.
-
- (#) In the Polling Mode it is advised to use the following functions:
- (++) HASH_GetFlagStatus() : to check if flags events occur.
- (++) HASH_ClearFlag() : to clear the flags events.
-
- (#) In the Interrupt Mode it is advised to use the following functions:
- (++) HASH_ITConfig() : to enable or disable the interrupt source.
- (++) HASH_GetITStatus() : to check if Interrupt occurs.
- (++) HASH_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified HASH interrupts.
- * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg HASH_IT_DINI: Data Input interrupt
- * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
- * @param NewState: new state of the specified HASH interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_HASH_IT(HASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected HASH interrupt */
- HASH->IMR |= HASH_IT;
- }
- else
- {
- /* Disable the selected HASH interrupt */
- HASH->IMR &= (uint32_t)(~HASH_IT);
- }
-}
-
-/**
- * @brief Checks whether the specified HASH flag is set or not.
- * @param HASH_FLAG: specifies the HASH flag to check.
- * This parameter can be one of the following values:
- * @arg HASH_FLAG_DINIS: Data input interrupt status flag
- * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag
- * @arg HASH_FLAG_BUSY: Busy flag
- * @arg HASH_FLAG_DMAS: DMAS Status flag
- * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag
- * @retval The new state of HASH_FLAG (SET or RESET)
- */
-FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tempreg = 0;
-
- /* Check the parameters */
- assert_param(IS_HASH_GET_FLAG(HASH_FLAG));
-
- /* check if the FLAG is in CR register */
- if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint32_t)RESET )
- {
- tempreg = HASH->CR;
- }
- else /* The FLAG is in SR register */
- {
- tempreg = HASH->SR;
- }
-
- /* Check the status of the specified HASH flag */
- if ((tempreg & HASH_FLAG) != (uint32_t)RESET)
- {
- /* HASH is set */
- bitstatus = SET;
- }
- else
- {
- /* HASH_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the HASH_FLAG status */
- return bitstatus;
-}
-/**
- * @brief Clears the HASH flags.
- * @param HASH_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg HASH_FLAG_DINIS: Data Input Flag
- * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag
- * @retval None
- */
-void HASH_ClearFlag(uint32_t HASH_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG));
-
- /* Clear the selected HASH flags */
- HASH->SR = ~(uint32_t)HASH_FLAG;
-}
-/**
- * @brief Checks whether the specified HASH interrupt has occurred or not.
- * @param HASH_IT: specifies the HASH interrupt source to check.
- * This parameter can be one of the following values:
- * @arg HASH_IT_DINI: Data Input interrupt
- * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
- * @retval The new state of HASH_IT (SET or RESET).
- */
-ITStatus HASH_GetITStatus(uint32_t HASH_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_HASH_GET_IT(HASH_IT));
-
-
- /* Check the status of the specified HASH interrupt */
- tmpreg = HASH->SR;
-
- if (((HASH->IMR & tmpreg) & HASH_IT) != RESET)
- {
- /* HASH_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* HASH_IT is reset */
- bitstatus = RESET;
- }
- /* Return the HASH_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the HASH interrupt pending bit(s).
- * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear.
- * This parameter can be any combination of the following values:
- * @arg HASH_IT_DINI: Data Input interrupt
- * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
- * @retval None
- */
-void HASH_ClearITPendingBit(uint32_t HASH_IT)
-{
- /* Check the parameters */
- assert_param(IS_HASH_IT(HASH_IT));
-
- /* Clear the selected HASH interrupt pending bit */
- HASH->SR = (uint32_t)(~HASH_IT);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
deleted file mode 100644
index f7549dec..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hash_md5.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides high level functions to compute the HASH MD5 and
- * HMAC MD5 Digest of an input message.
- * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
- * peripheral.
- *
-@verbatim
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable The HASH controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
-
- (#) Calculate the HASH MD5 Digest using HASH_MD5() function.
-
- (#) Calculate the HMAC MD5 Digest using HMAC_MD5() function.
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hash.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup HASH
- * @brief HASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HASH_Private_Functions
- * @{
- */
-
-/** @defgroup HASH_Group6 High Level SHA1 functions
- * @brief High Level SHA1 Hash and HMAC functions
- *
-@verbatim
- ===============================================================================
- ##### High Level SHA1 Hash and HMAC functions #####
- ===============================================================================
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Compute the HASH SHA1 digest.
- * @param Input: pointer to the Input buffer to be treated.
- * @param Ilen: length of the Input buffer.
- * @param Output: the returned digest
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: digest computation done
- * - ERROR: digest computation failed
- */
-ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
-{
- HASH_InitTypeDef SHA1_HASH_InitStructure;
- HASH_MsgDigest SHA1_MessageDigest;
- __IO uint16_t nbvalidbitsdata = 0;
- uint32_t i = 0;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
- /* Number of valid bits in last word of the Input data */
- nbvalidbitsdata = 8 * (Ilen % 4);
-
- /* HASH peripheral initialization */
- HASH_DeInit();
-
- /* HASH Configuration */
- SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
- SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
- SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
- HASH_Init(&SHA1_HASH_InitStructure);
-
- /* Configure the number of valid bits in last word of the data */
- HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
-
- /* Write the Input block in the IN FIFO */
- for(i=0; i 64)
- {
- /* HMAC long Key */
- SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
- }
- else
- {
- /* HMAC short Key */
- SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
- }
- HASH_Init(&SHA1_HASH_InitStructure);
-
- /* Configure the number of valid bits in last word of the Key */
- HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
-
- /* Write the Key */
- for(i=0; iGPIO_Mode = GPIO_Mode_AF
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function
- Recommended configuration is Push-Pull, Pull-up, Open-Drain.
- Add an external pull up if necessary (typically 4.7 KOhm).
-
- (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged
- Address using the I2C_Init() function.
-
- (#) Optionally you can enable/configure the following parameters without
- re-initialization (i.e there is no need to call again I2C_Init() function):
- (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function
- (++) Enable the dual addressing mode using I2C_DualAddressCmd() function
- (++) Enable the general call using the I2C_GeneralCallCmd() function
- (++) Enable the clock stretching using I2C_StretchClockCmd() function
- (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()
- function.
- (++) Configure the NACK position for Master Receiver mode in case of
- 2 bytes reception using the function I2C_NACKPositionConfig().
- (++) Enable the PEC Calculation using I2C_CalculatePEC() function
- (++) For SMBus Mode:
- (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function
- (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- I2C_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function
- (++) Active the needed channel Request using I2C_DMACmd() or
- I2C_DMALastTransferCmd() function.
- -@@- When using DMA mode, I2C interrupts may be used at the same time to
- control the communication flow (Start/Stop/Ack... events and errors).
-
- (#) Enable the I2C using the I2C_Cmd() function.
-
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
- transfers.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_i2c.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup I2C
- * @brief I2C driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed));
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
- assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
-
-/*---------------------------- I2Cx CR2 Configuration ------------------------*/
- /* Get the I2Cx CR2 value */
- tmpreg = I2Cx->CR2;
- /* Clear frequency FREQ[5:0] bits */
- tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);
- /* Get pclk1 frequency value */
- RCC_GetClocksFreq(&rcc_clocks);
- pclk1 = rcc_clocks.PCLK1_Frequency;
- /* Set frequency bits depending on pclk1 value */
- freqrange = (uint16_t)(pclk1 / 1000000);
- tmpreg |= freqrange;
- /* Write to I2Cx CR2 */
- I2Cx->CR2 = tmpreg;
-
-/*---------------------------- I2Cx CCR Configuration ------------------------*/
- /* Disable the selected I2C peripheral to configure TRISE */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
- /* Reset tmpreg value */
- /* Clear F/S, DUTY and CCR[11:0] bits */
- tmpreg = 0;
-
- /* Configure speed in standard mode */
- if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
- {
- /* Standard mode speed calculate */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
- /* Test if CCR value is under 0x4*/
- if (result < 0x04)
- {
- /* Set minimum allowed value */
- result = 0x04;
- }
- /* Set speed value for standard mode */
- tmpreg |= result;
- /* Set Maximum Rise Time for standard mode */
- I2Cx->TRISE = freqrange + 1;
- }
- /* Configure speed in fast mode */
- /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral
- input clock) must be a multiple of 10 MHz */
- else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
- {
- if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
- {
- /* Fast mode speed calculate: Tlow/Thigh = 2 */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
- }
- else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
- {
- /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
- /* Set DUTY bit */
- result |= I2C_DutyCycle_16_9;
- }
-
- /* Test if CCR value is under 0x1*/
- if ((result & I2C_CCR_CCR) == 0)
- {
- /* Set minimum allowed value */
- result |= (uint16_t)0x0001;
- }
- /* Set speed value and set F/S bit for fast mode */
- tmpreg |= (uint16_t)(result | I2C_CCR_FS);
- /* Set Maximum Rise Time for fast mode */
- I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
- }
-
- /* Write to I2Cx CCR */
- I2Cx->CCR = tmpreg;
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
-
-/*---------------------------- I2Cx CR1 Configuration ------------------------*/
- /* Get the I2Cx CR1 value */
- tmpreg = I2Cx->CR1;
- /* Clear ACK, SMBTYPE and SMBUS bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure I2Cx: mode and acknowledgement */
- /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
- /* Set ACK bit according to I2C_Ack value */
- tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
- /* Write to I2Cx CR1 */
- I2Cx->CR1 = tmpreg;
-
-/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
- /* Set I2Cx Own Address1 and acknowledged address */
- I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
-}
-
-/**
- * @brief Fills each I2C_InitStruct member with its default value.
- * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
-{
-/*---------------- Reset I2C init structure parameters values ----------------*/
- /* initialize the I2C_ClockSpeed member */
- I2C_InitStruct->I2C_ClockSpeed = 5000;
- /* Initialize the I2C_Mode member */
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
- /* Initialize the I2C_DutyCycle member */
- I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
- /* Initialize the I2C_OwnAddress1 member */
- I2C_InitStruct->I2C_OwnAddress1 = 0;
- /* Initialize the I2C_Ack member */
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
- /* Initialize the I2C_AcknowledgedAddress member */
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-}
-
-/**
- * @brief Enables or disables the specified I2C peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
- }
- else
- {
- /* Disable the selected I2C peripheral */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
- }
-}
-
-/**
- * @brief Enables or disables the Analog filter of I2C peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the Analog filter.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function should be called before initializing and enabling
- the I2C Peripheral.
- * @retval None
- */
-void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the analog filter */
- I2Cx->FLTR &= (uint16_t)~((uint16_t)I2C_FLTR_ANOFF);
- }
- else
- {
- /* Disable the analog filter */
- I2Cx->FLTR |= I2C_FLTR_ANOFF;
- }
-}
-
-/**
- * @brief Configures the Digital noise filter of I2C peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_DigitalFilter: Coefficient of digital noise filter.
- * This parameter can be a number between 0x00 and 0x0F.
- * @note This function should be called before initializing and enabling
- the I2C Peripheral.
- * @retval None
- */
-void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter)
-{
- uint16_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DIGITAL_FILTER(I2C_DigitalFilter));
-
- /* Get the old register value */
- tmpreg = I2Cx->FLTR;
-
- /* Reset I2Cx DNF bit [3:0] */
- tmpreg &= (uint16_t)~((uint16_t)I2C_FLTR_DNF);
-
- /* Set I2Cx DNF coefficient */
- tmpreg |= (uint16_t)((uint16_t)I2C_DigitalFilter & I2C_FLTR_DNF);
-
- /* Store the new register value */
- I2Cx->FLTR = tmpreg;
-}
-
-/**
- * @brief Generates I2Cx communication START condition.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C START condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Generate a START condition */
- I2Cx->CR1 |= I2C_CR1_START;
- }
- else
- {
- /* Disable the START condition generation */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);
- }
-}
-
-/**
- * @brief Generates I2Cx communication STOP condition.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C STOP condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Generate a STOP condition */
- I2Cx->CR1 |= I2C_CR1_STOP;
- }
- else
- {
- /* Disable the STOP condition generation */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);
- }
-}
-
-/**
- * @brief Transmits the address byte to select the slave device.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param Address: specifies the slave address which will be transmitted
- * @param I2C_Direction: specifies whether the I2C device will be a Transmitter
- * or a Receiver.
- * This parameter can be one of the following values
- * @arg I2C_Direction_Transmitter: Transmitter mode
- * @arg I2C_Direction_Receiver: Receiver mode
- * @retval None.
- */
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DIRECTION(I2C_Direction));
- /* Test on the direction to set/reset the read/write bit */
- if (I2C_Direction != I2C_Direction_Transmitter)
- {
- /* Set the address bit0 for read */
- Address |= I2C_OAR1_ADD0;
- }
- else
- {
- /* Reset the address bit0 for write */
- Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);
- }
- /* Send the address */
- I2Cx->DR = Address;
-}
-
-/**
- * @brief Enables or disables the specified I2C acknowledge feature.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C Acknowledgement.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the acknowledgement */
- I2Cx->CR1 |= I2C_CR1_ACK;
- }
- else
- {
- /* Disable the acknowledgement */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);
- }
-}
-
-/**
- * @brief Configures the specified I2C own address2.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param Address: specifies the 7bit I2C own address2.
- * @retval None.
- */
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
-{
- uint16_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Get the old register value */
- tmpreg = I2Cx->OAR2;
-
- /* Reset I2Cx Own address2 bit [7:1] */
- tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);
-
- /* Set I2Cx Own address2 */
- tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
-
- /* Store the new register value */
- I2Cx->OAR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the specified I2C dual addressing mode.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C dual addressing mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable dual addressing mode */
- I2Cx->OAR2 |= I2C_OAR2_ENDUAL;
- }
- else
- {
- /* Disable dual addressing mode */
- I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C general call feature.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C General call.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable generall call */
- I2Cx->CR1 |= I2C_CR1_ENGC;
- }
- else
- {
- /* Disable generall call */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C software reset.
- * @note When software reset is enabled, the I2C IOs are released (this can
- * be useful to recover from bus errors).
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C software reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Peripheral under reset */
- I2Cx->CR1 |= I2C_CR1_SWRST;
- }
- else
- {
- /* Peripheral not under reset */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C Clock stretching.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Clock stretching.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState == DISABLE)
- {
- /* Enable the selected I2C Clock stretching */
- I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
- }
- else
- {
- /* Disable the selected I2C Clock stretching */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);
- }
-}
-
-/**
- * @brief Selects the specified I2C fast mode duty cycle.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_DutyCycle: specifies the fast mode duty cycle.
- * This parameter can be one of the following values:
- * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
- * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
- * @retval None
- */
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
- if (I2C_DutyCycle != I2C_DutyCycle_16_9)
- {
- /* I2C fast mode Tlow/Thigh=2 */
- I2Cx->CCR &= I2C_DutyCycle_2;
- }
- else
- {
- /* I2C fast mode Tlow/Thigh=16/9 */
- I2Cx->CCR |= I2C_DutyCycle_16_9;
- }
-}
-
-/**
- * @brief Selects the specified I2C NACK position in master receiver mode.
- * @note This function is useful in I2C Master Receiver mode when the number
- * of data to be received is equal to 2. In this case, this function
- * should be called (with parameter I2C_NACKPosition_Next) before data
- * reception starts,as described in the 2-byte reception procedure
- * recommended in Reference Manual in Section: Master receiver.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_NACKPosition: specifies the NACK position.
- * This parameter can be one of the following values:
- * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
- * received byte.
- * @arg I2C_NACKPosition_Current: indicates that current byte is the last
- * received byte.
- *
- * @note This function configures the same bit (POS) as I2C_PECPositionConfig()
- * but is intended to be used in I2C mode while I2C_PECPositionConfig()
- * is intended to used in SMBUS mode.
- *
- * @retval None
- */
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
-
- /* Check the input parameter */
- if (I2C_NACKPosition == I2C_NACKPosition_Next)
- {
- /* Next byte in shift register is the last received byte */
- I2Cx->CR1 |= I2C_NACKPosition_Next;
- }
- else
- {
- /* Current byte in shift register is the last received byte */
- I2Cx->CR1 &= I2C_NACKPosition_Current;
- }
-}
-
-/**
- * @brief Drives the SMBusAlert pin high or low for the specified I2C.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_SMBusAlert: specifies SMBAlert pin level.
- * This parameter can be one of the following values:
- * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
- * @arg I2C_SMBusAlert_High: SMBAlert pin driven high
- * @retval None
- */
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
- if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
- {
- /* Drive the SMBusAlert pin Low */
- I2Cx->CR1 |= I2C_SMBusAlert_Low;
- }
- else
- {
- /* Drive the SMBusAlert pin High */
- I2Cx->CR1 &= I2C_SMBusAlert_High;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C ARP.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx ARP.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C ARP */
- I2Cx->CR1 |= I2C_CR1_ENARP;
- }
- else
- {
- /* Disable the selected I2C ARP */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup I2C_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sends a data byte through the I2Cx peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param Data: Byte to be transmitted..
- * @retval None
- */
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Write in the DR register the data to be sent */
- I2Cx->DR = Data;
-}
-
-/**
- * @brief Returns the most recent received data by the I2Cx peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @retval The value of the received data.
- */
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Return the data in the DR register */
- return (uint8_t)I2Cx->DR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group3 PEC management functions
- * @brief PEC management functions
- *
-@verbatim
- ===============================================================================
- ##### PEC management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified I2C PEC transfer.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C PEC transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC transmission */
- I2Cx->CR1 |= I2C_CR1_PEC;
- }
- else
- {
- /* Disable the selected I2C PEC transmission */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);
- }
-}
-
-/**
- * @brief Selects the specified I2C PEC position.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_PECPosition: specifies the PEC position.
- * This parameter can be one of the following values:
- * @arg I2C_PECPosition_Next: indicates that the next byte is PEC
- * @arg I2C_PECPosition_Current: indicates that current byte is PEC
- *
- * @note This function configures the same bit (POS) as I2C_NACKPositionConfig()
- * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig()
- * is intended to used in I2C mode.
- *
- * @retval None
- */
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
- if (I2C_PECPosition == I2C_PECPosition_Next)
- {
- /* Next byte in shift register is PEC */
- I2Cx->CR1 |= I2C_PECPosition_Next;
- }
- else
- {
- /* Current byte in shift register is PEC */
- I2Cx->CR1 &= I2C_PECPosition_Current;
- }
-}
-
-/**
- * @brief Enables or disables the PEC value calculation of the transferred bytes.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx PEC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC calculation */
- I2Cx->CR1 |= I2C_CR1_ENPEC;
- }
- else
- {
- /* Disable the selected I2C PEC calculation */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);
- }
-}
-
-/**
- * @brief Returns the PEC value for the specified I2C.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @retval The PEC value.
- */
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Return the selected I2C PEC value */
- return ((I2Cx->SR2) >> 8);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group4 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
- This section provides functions allowing to configure the I2C DMA channels
- requests.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified I2C DMA requests.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C DMA requests */
- I2Cx->CR2 |= I2C_CR2_DMAEN;
- }
- else
- {
- /* Disable the selected I2C DMA requests */
- I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);
- }
-}
-
-/**
- * @brief Specifies that the next DMA transfer is the last one.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C DMA last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Next DMA transfer is the last transfer */
- I2Cx->CR2 |= I2C_CR2_LAST;
- }
- else
- {
- /* Next DMA transfer is not the last transfer */
- I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group5 Interrupts events and flags management functions
- * @brief Interrupts, events and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts, events and flags management functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to configure the I2C Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
-
- ##### I2C State Monitoring Functions #####
- ===============================================================================
- [..]
- This I2C driver provides three different ways for I2C state monitoring
- depending on the application requirements and constraints:
-
-
- (#) Basic state monitoring (Using I2C_CheckEvent() function)
-
- It compares the status registers (SR1 and SR2) content to a given event
- (can be the combination of one or more flags).
- It returns SUCCESS if the current status includes the given flags
- and returns ERROR if one or more flags are missing in the current status.
-
- (++) When to use
- (+++) This function is suitable for most applications as well as for startup
- activity since the events are fully described in the product reference
- manual (RM0090).
- (+++) It is also suitable for users who need to define their own events.
-
- (++) Limitations
- If an error occurs (ie. error flags are set besides to the monitored
- flags), the I2C_CheckEvent() function may return SUCCESS despite
- the communication hold or corrupted real state.
- In this case, it is advised to use error interrupts to monitor
- the error events and handle them in the interrupt IRQ handler.
-
- -@@- For error management, it is advised to use the following functions:
- (+@@) I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
- Where x is the peripheral instance (I2C1, I2C2 ...)
- (+@@) I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
- I2Cx_ER_IRQHandler() function in order to determine which error occurred.
- (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- and/or I2C_GenerateStop() in order to clear the error flag and source
- and return to correct communication status.
-
-
- (#) Advanced state monitoring (Using the function I2C_GetLastEvent())
-
- Using the function I2C_GetLastEvent() which returns the image of both status
- registers in a single word (uint32_t) (Status Register 2 value is shifted left
- by 16 bits and concatenated to Status Register 1).
-
- (++) When to use
- (+++) This function is suitable for the same applications above but it
- allows to overcome the mentioned limitation of I2C_GetFlagStatus()
- function.
- (+++) The returned value could be compared to events already defined in
- the library (stm32f4xx_i2c.h) or to custom values defined by user.
- This function is suitable when multiple flags are monitored at the
- same time.
- (+++) At the opposite of I2C_CheckEvent() function, this function allows
- user to choose when an event is accepted (when all events flags are
- set and no other flags are set or just when the needed flags are set
- like I2C_CheckEvent() function.
-
- (++) Limitations
- (+++) User may need to define his own events.
- (+++) Same remark concerning the error management is applicable for this
- function if user decides to check only regular communication flags
- (and ignores error flags).
-
-
- (#) Flag-based state monitoring (Using the function I2C_GetFlagStatus())
-
- Using the function I2C_GetFlagStatus() which simply returns the status of
- one single flag (ie. I2C_FLAG_RXNE ...).
-
- (++) When to use
- (+++) This function could be used for specific applications or in debug
- phase.
- (+++) It is suitable when only one flag checking is needed (most I2C
- events are monitored through multiple flags).
- (++) Limitations:
- (+++) When calling this function, the Status register is accessed.
- Some flags are cleared when the status register is accessed.
- So checking the status of one Flag, may clear other ones.
- (+++) Function may need to be called twice or more in order to monitor
- one single event.
-
- For detailed description of Events, please refer to section I2C_Events in
- stm32f4xx_i2c.h file.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified I2C register and returns its value.
- * @param I2C_Register: specifies the register to read.
- * This parameter can be one of the following values:
- * @arg I2C_Register_CR1: CR1 register.
- * @arg I2C_Register_CR2: CR2 register.
- * @arg I2C_Register_OAR1: OAR1 register.
- * @arg I2C_Register_OAR2: OAR2 register.
- * @arg I2C_Register_DR: DR register.
- * @arg I2C_Register_SR1: SR1 register.
- * @arg I2C_Register_SR2: SR2 register.
- * @arg I2C_Register_CCR: CCR register.
- * @arg I2C_Register_TRISE: TRISE register.
- * @retval The value of the read register.
- */
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_REGISTER(I2C_Register));
-
- tmp = (uint32_t) I2Cx;
- tmp += I2C_Register;
-
- /* Return the selected register value */
- return (*(__IO uint16_t *) tmp);
-}
-
-/**
- * @brief Enables or disables the specified I2C interrupts.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_BUF: Buffer interrupt mask
- * @arg I2C_IT_EVT: Event interrupt mask
- * @arg I2C_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified I2C interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C interrupts */
- I2Cx->CR2 |= I2C_IT;
- }
- else
- {
- /* Disable the selected I2C interrupts */
- I2Cx->CR2 &= (uint16_t)~I2C_IT;
- }
-}
-
-/*
- ===============================================================================
- 1. Basic state monitoring
- ===============================================================================
- */
-
-/**
- * @brief Checks whether the last I2Cx Event is equal to the one passed
- * as parameter.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_EVENT: specifies the event to be checked.
- * This parameter can be one of the following values:
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2
- * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3
- * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2
- * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4
- * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5
- * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6
- * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6
- * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2
- * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9
- *
- * @note For detailed description of Events, please refer to section I2C_Events
- * in stm32f4xx_i2c.h file.
- *
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Last event is equal to the I2C_EVENT
- * - ERROR: Last event is different from the I2C_EVENT
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
-{
- uint32_t lastevent = 0;
- uint32_t flag1 = 0, flag2 = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_EVENT(I2C_EVENT));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
- flag2 = I2Cx->SR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_MASK;
-
- /* Check whether the last event contains the I2C_EVENT */
- if ((lastevent & I2C_EVENT) == I2C_EVENT)
- {
- /* SUCCESS: last event is equal to I2C_EVENT */
- status = SUCCESS;
- }
- else
- {
- /* ERROR: last event is different from I2C_EVENT */
- status = ERROR;
- }
- /* Return status */
- return status;
-}
-
-/*
- ===============================================================================
- 2. Advanced state monitoring
- ===============================================================================
- */
-
-/**
- * @brief Returns the last I2Cx Event.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- *
- * @note For detailed description of Events, please refer to section I2C_Events
- * in stm32f4xx_i2c.h file.
- *
- * @retval The last event
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
-{
- uint32_t lastevent = 0;
- uint32_t flag1 = 0, flag2 = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
- flag2 = I2Cx->SR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_MASK;
-
- /* Return status */
- return lastevent;
-}
-
-/*
- ===============================================================================
- 3. Flag-based state monitoring
- ===============================================================================
- */
-
-/**
- * @brief Checks whether the specified I2C flag is set or not.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
- * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
- * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
- * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
- * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
- * @arg I2C_FLAG_BUSY: Bus busy flag
- * @arg I2C_FLAG_MSL: Master/Slave flag
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
- * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
- * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
- * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
- * @arg I2C_FLAG_BTF: Byte transfer finished flag
- * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
- * Address matched flag (Slave mode)"ENDAD"
- * @arg I2C_FLAG_SB: Start bit flag (Master mode)
- * @retval The new state of I2C_FLAG (SET or RESET).
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- FlagStatus bitstatus = RESET;
- __IO uint32_t i2creg = 0, i2cxbase = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
-
- /* Get the I2Cx peripheral base address */
- i2cxbase = (uint32_t)I2Cx;
-
- /* Read flag register index */
- i2creg = I2C_FLAG >> 28;
-
- /* Get bit[23:0] of the flag */
- I2C_FLAG &= FLAG_MASK;
-
- if(i2creg != 0)
- {
- /* Get the I2Cx SR1 register address */
- i2cxbase += 0x14;
- }
- else
- {
- /* Flag in I2Cx SR2 Register */
- I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
- /* Get the I2Cx SR2 register address */
- i2cxbase += 0x18;
- }
-
- if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
- {
- /* I2C_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the I2C_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's pending flags.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- *
- * @note STOPF (STOP detection) is cleared by software sequence: a read operation
- * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
- * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
- * @note ADD10 (10-bit header sent) is cleared by software sequence: a read
- * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
- * second byte of the address in DR register.
- * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read
- * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
- * read/write to I2C_DR register (I2C_SendData()).
- * @note ADDR (Address sent) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
- * I2C_SR2 register ((void)(I2Cx->SR2)).
- * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
- * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
- * register (I2C_SendData()).
- *
- * @retval None
- */
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- uint32_t flagpos = 0;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
- /* Get the I2C flag position */
- flagpos = I2C_FLAG & FLAG_MASK;
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @brief Checks whether the specified I2C interrupt has occurred or not.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2C_IT_SMBALERT: SMBus Alert flag
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_IT_PECERR: PEC error in reception flag
- * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_IT_AF: Acknowledge failure flag
- * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_IT_BERR: Bus error flag
- * @arg I2C_IT_TXE: Data register empty flag (Transmitter)
- * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
- * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
- * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
- * @arg I2C_IT_BTF: Byte transfer finished flag
- * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
- * Address matched flag (Slave mode)"ENDAD"
- * @arg I2C_IT_SB: Start bit flag (Master mode)
- * @retval The new state of I2C_IT (SET or RESET).
- */
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_IT(I2C_IT));
-
- /* Check if the interrupt source is enabled or not */
- enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;
-
- /* Get bit[23:0] of the flag */
- I2C_IT &= FLAG_MASK;
-
- /* Check the status of the specified I2C flag */
- if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
- {
- /* I2C_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_IT is reset */
- bitstatus = RESET;
- }
- /* Return the I2C_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's interrupt pending bits.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_SMBALERT: SMBus Alert interrupt
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
- * @arg I2C_IT_PECERR: PEC error in reception interrupt
- * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
- * @arg I2C_IT_AF: Acknowledge failure interrupt
- * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
- * @arg I2C_IT_BERR: Bus error interrupt
- *
- * @note STOPF (STOP detection) is cleared by software sequence: a read operation
- * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
- * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
- * @note ADD10 (10-bit header sent) is cleared by software sequence: a read
- * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
- * byte of the address in I2C_DR register.
- * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read
- * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
- * read/write to I2C_DR register (I2C_SendData()).
- * @note ADDR (Address sent) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
- * I2C_SR2 register ((void)(I2Cx->SR2)).
- * @note SB (Start Bit) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
- * I2C_DR register (I2C_SendData()).
- * @retval None
- */
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- uint32_t flagpos = 0;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));
-
- /* Get the I2C flag position */
- flagpos = I2C_IT & FLAG_MASK;
-
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
deleted file mode 100644
index 5f6cb547..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_iwdg.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Independent watchdog (IWDG) peripheral:
- * + Prescaler and Counter configuration
- * + IWDG activation
- * + Flag management
- *
- @verbatim
- ===============================================================================
- ##### IWDG features #####
- ===============================================================================
- [..]
- The IWDG can be started by either software or hardware (configurable
- through option byte).
-
- The IWDG is clocked by its own dedicated low-speed clock (LSI) and
- thus stays active even if the main clock fails.
- Once the IWDG is started, the LSI is forced ON and cannot be disabled
- (LSI cannot be disabled too), and the counter starts counting down from
- the reset value of 0xFFF. When it reaches the end of count value (0x000)
- a system reset is generated.
- The IWDG counter should be reloaded at regular intervals to prevent
- an MCU reset.
-
- The IWDG is implemented in the VDD voltage domain that is still functional
- in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
-
- IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
- reset occurs.
-
- Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
- The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
- devices provide the capability to measure the LSI frequency (LSI clock
- connected internally to TIM5 CH4 input capture). The measured value
- can be used to have an IWDG timeout with an acceptable accuracy.
- For more information, please refer to the STM32F4xx Reference manual
-
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable write access to IWDG_PR and IWDG_RLR registers using
- IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
-
- (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function
-
- (#) Configure the IWDG counter value using IWDG_SetReload() function.
- This value will be loaded in the IWDG counter each time the counter
- is reloaded, then the IWDG will start counting down from this value.
-
- (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used
- in software mode (no need to enable the LSI, it will be enabled
- by hardware)
-
- (#) Then the application program must reload the IWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
- IWDG_ReloadCounter() function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_pwr.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup PWR
- * @brief PWR driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* --------- PWR registers bit address in the alias region ---------- */
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-
-/* Alias word address of DBP bit */
-#define CR_OFFSET (PWR_OFFSET + 0x00)
-#define DBP_BitNumber 0x08
-#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BitNumber 0x04
-#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
-
-/* Alias word address of FPDS bit */
-#define FPDS_BitNumber 0x09
-#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
-
-/* Alias word address of PMODE bit */
-#define PMODE_BitNumber 0x0E
-#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
-
-
-/* --- CSR Register ---*/
-
-/* Alias word address of EWUP bit */
-#define CSR_OFFSET (PWR_OFFSET + 0x04)
-#define EWUP_BitNumber 0x08
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
-
-/* Alias word address of BRE bit */
-#define BRE_BitNumber 0x09
-#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
-
-/* ------------------ PWR registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
-#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
-#define CR_VOS_MASK ((uint32_t)0xFFFF3FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Private_Functions
- * @{
- */
-
-/** @defgroup PWR_Group1 Backup Domain Access function
- * @brief Backup Domain Access function
- *
-@verbatim
- ===============================================================================
- ##### Backup Domain Access function #####
- ===============================================================================
- [..]
- After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted
- write accesses.
- To enable access to the RTC Domain and RTC registers, proceed as follows:
- (+) Enable the Power Controller (PWR) APB1 interface clock using the
- RCC_APB1PeriphClockCmd() function.
- (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the PWR peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void PWR_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
-}
-
-/**
- * @brief Enables or disables access to the backup domain (RTC registers, RTC
- * backup data registers and backup SRAM).
- * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @param NewState: new state of the access to the backup domain.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_BackupAccessCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group2 PVD configuration functions
- * @brief PVD configuration functions
- *
-@verbatim
- ===============================================================================
- ##### PVD configuration functions #####
- ===============================================================================
- [..]
- (+) The PVD is used to monitor the VDD power supply by comparing it to a
- threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
- (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
- than the PVD threshold. This event is internally connected to the EXTI
- line16 and can generate an interrupt if enabled through the EXTI registers.
- (+) The PVD is stopped in Standby mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @param PWR_PVDLevel: specifies the PVD detection level
- * This parameter can be one of the following values:
- * @arg PWR_PVDLevel_0
- * @arg PWR_PVDLevel_1
- * @arg PWR_PVDLevel_2
- * @arg PWR_PVDLevel_3
- * @arg PWR_PVDLevel_4
- * @arg PWR_PVDLevel_5
- * @arg PWR_PVDLevel_6
- * @arg PWR_PVDLevel_7
- * @note Refer to the electrical characteristics of your device datasheet for
- * more details about the voltage threshold corresponding to each
- * detection level.
- * @retval None
- */
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
-
- tmpreg = PWR->CR;
-
- /* Clear PLS[7:5] bits */
- tmpreg &= CR_PLS_MASK;
-
- /* Set PLS[7:5] bits according to PWR_PVDLevel value */
- tmpreg |= PWR_PVDLevel;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Power Voltage Detector(PVD).
- * @param NewState: new state of the PVD.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_PVDCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group3 WakeUp pin configuration functions
- * @brief WakeUp pin configuration functions
- *
-@verbatim
- ===============================================================================
- ##### WakeUp pin configuration functions #####
- ===============================================================================
- [..]
- (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
- forced in input pull down configuration and is active on rising edges.
- (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the WakeUp Pin functionality.
- * @param NewState: new state of the WakeUp Pin functionality.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_WakeUpPinCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions
- * @brief Main and Backup Regulators configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Main and Backup Regulators configuration functions #####
- ===============================================================================
- [..]
- (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
- the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
- retained even in Standby or VBAT mode when the low power backup regulator
- is enabled. It can be considered as an internal EEPROM when VBAT is
- always present. You can use the PWR_BackupRegulatorCmd() function to
- enable the low power backup regulator and use the PWR_GetFlagStatus
- (PWR_FLAG_BRR) to check if it is ready or not.
-
- (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
- the backup SRAM is powered from VDD which replaces the VBAT power supply to
- save battery life.
-
- (+) The backup SRAM is not mass erased by an tamper event. It is read
- protected to prevent confidential data, such as cryptographic private
- key, from being accessed. The backup SRAM can be erased only through
- the Flash interface when a protection level change from level 1 to
- level 0 is requested.
- -@- Refer to the description of Read protection (RDP) in the Flash
- programming manual.
-
- (+) The main internal regulator can be configured to have a tradeoff between
- performance and power consumption when the device does not operate at
- the maximum frequency. This is done through PWR_MainRegulatorModeConfig()
- function which configure VOS bit in PWR_CR register:
- (++) When this bit is set (Regulator voltage output Scale 1 mode selected)
- the System frequency can go up to 168 MHz.
- (++) When this bit is reset (Regulator voltage output Scale 2 mode selected)
- the System frequency can go up to 144 MHz.
-
- Refer to the datasheets for more details.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the Backup Regulator.
- * @param NewState: new state of the Backup Regulator.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_BackupRegulatorCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the main internal regulator output voltage.
- * @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve
- * a tradeoff between performance and power consumption when the device does
- * not operate at the maximum frequency (refer to the datasheets for more details).
- * This parameter can be one of the following values:
- * @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode,
- * System frequency up to 168 MHz.
- * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode,
- * System frequency up to 144 MHz.
- * @arg PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode,
- * System frequency up to 120 MHz
- * @retval None
- */
-void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
-
- tmpreg = PWR->CR;
-
- /* Clear VOS[15:14] bits */
- tmpreg &= CR_VOS_MASK;
-
- /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */
- tmpreg |= PWR_Regulator_Voltage;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group5 FLASH Power Down configuration functions
- * @brief FLASH Power Down configuration functions
- *
-@verbatim
- ===============================================================================
- ##### FLASH Power Down configuration functions #####
- ===============================================================================
- [..]
- (+) By setting the FPDS bit in the PWR_CR register by using the
- PWR_FlashPowerDownCmd() function, the Flash memory also enters power
- down mode when the device enters Stop mode. When the Flash memory
- is in power down mode, an additional startup delay is incurred when
- waking up from Stop mode.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the Flash Power Down in STOP mode.
- * @param NewState: new state of the Flash power mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_FlashPowerDownCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group6 Low Power modes configuration functions
- * @brief Low Power modes configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Low Power modes configuration functions #####
- ===============================================================================
- [..]
- The devices feature 3 low-power modes:
- (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
- (+) Stop mode: all clocks are stopped, regulator running, regulator
- in low power mode
- (+) Standby mode: 1.2V domain powered off.
-
- *** Sleep mode ***
- ==================
- [..]
- (+) Entry:
- (++) The Sleep mode is entered by using the __WFI() or __WFE() functions.
- (+) Exit:
- (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
- controller (NVIC) can wake up the device from Sleep mode.
-
- *** Stop mode ***
- =================
- [..]
- In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
- and the HSE RC oscillators are disabled. Internal SRAM and register contents
- are preserved.
- The voltage regulator can be configured either in normal or low-power mode.
- To minimize the consumption In Stop mode, FLASH can be powered off before
- entering the Stop mode. It can be switched on again by software after exiting
- the Stop mode using the PWR_FlashPowerDownCmd() function.
-
- (+) Entry:
- (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
- function with regulator in LowPower or with Regulator ON.
- (+) Exit:
- (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
-
- *** Standby mode ***
- ====================
- [..]
- The Standby mode allows to achieve the lowest power consumption. It is based
- on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
- The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
- the HSE oscillator are also switched off. SRAM and register contents are lost
- except for the RTC registers, RTC backup registers, backup SRAM and Standby
- circuitry.
-
- The voltage regulator is OFF.
-
- (+) Entry:
- (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
- (+) Exit:
- (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
- tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
-
- *** Auto-wakeup (AWU) from low-power mode ***
- =============================================
- [..]
- The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
- Wakeup event, a tamper event, a time-stamp event, or a comparator event,
- without depending on an external interrupt (Auto-wakeup mode).
-
- (#) RTC auto-wakeup (AWU) from the Stop mode
-
- (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
- (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
- and RTC_AlarmCmd() functions.
- (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
- is necessary to:
- (+++) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
- function
- (+++) Configure the RTC to detect the tamper or time stamp event using the
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
- functions.
- (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
- (+++) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
- RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
-
- (#) RTC auto-wakeup (AWU) from the Standby mode
-
- (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
- (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
- and RTC_AlarmCmd() functions.
- (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
- is necessary to:
- (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
- function
- (+++) Configure the RTC to detect the tamper or time stamp event using the
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
- functions.
- (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
- (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
- RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enters STOP mode.
- *
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock.
- * @note When the voltage regulator operates in low power mode, an additional
- * startup delay is incurred when waking up from Stop mode.
- * By keeping the internal regulator ON during Stop mode, the consumption
- * is higher although the startup time is reduced.
- *
- * @param PWR_Regulator: specifies the regulator state in STOP mode.
- * This parameter can be one of the following values:
- * @arg PWR_Regulator_ON: STOP mode with regulator ON
- * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
- * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
- * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
- * @retval None
- */
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
-
- /* Select the regulator state in STOP mode ---------------------------------*/
- tmpreg = PWR->CR;
- /* Clear PDDS and LPDSR bits */
- tmpreg &= CR_DS_MASK;
-
- /* Set LPDSR bit according to PWR_Regulator value */
- tmpreg |= PWR_Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Select STOP mode entry --------------------------------------------------*/
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __WFE();
- }
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-}
-
-/**
- * @brief Enters STANDBY mode.
- * @note In Standby mode, all I/O pins are high impedance except for:
- * - Reset pad (still available)
- * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
- * Alarm out, or RTC clock calibration out.
- * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
- * - WKUP pin 1 (PA0) if enabled.
- * @param None
- * @retval None
- */
-void PWR_EnterSTANDBYMode(void)
-{
- /* Clear Wakeup flag */
- PWR->CR |= PWR_CR_CWUF;
-
- /* Select STANDBY mode */
- PWR->CR |= PWR_CR_PDDS;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-/* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM )
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group7 Flags management functions
- * @brief Flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified PWR flag is set or not.
- * @param PWR_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
- * was received from the WKUP pin or from the RTC alarm (Alarm A
- * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
- * An additional wakeup event is detected if the WKUP pin is enabled
- * (by setting the EWUP bit) when the WKUP pin level is already high.
- * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
- * resumed from StandBy mode.
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
- * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode
- * For this reason, this bit is equal to 0 after Standby or reset
- * until the PVDE bit is set.
- * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
- * when the device wakes up from Standby mode or by a system reset
- * or power reset.
- * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
- * scaling output selection is ready.
- * @retval The new state of PWR_FLAG (SET or RESET).
- */
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
-
- if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the PWR's pending flags.
- * @param PWR_FLAG: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- * @retval None
- */
-void PWR_ClearFlag(uint32_t PWR_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
-
- PWR->CR |= PWR_FLAG << 2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
deleted file mode 100644
index 967798e4..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
+++ /dev/null
@@ -1,1872 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_rcc.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Reset and clock control (RCC) peripheral:
- * + Internal/external clocks, PLL, CSS and MCO configuration
- * + System, AHB and APB busses clocks configuration
- * + Peripheral clocks configuration
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### RCC specific features #####
- ===============================================================================
- [..]
- After reset the device is running from Internal High Speed oscillator
- (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
- and I-Cache are disabled, and all peripherals are off except internal
- SRAM, Flash and JTAG.
- (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
- all peripherals mapped on these busses are running at HSI speed.
- (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
- (+) All GPIOs are in input floating state, except the JTAG pins which
- are assigned to be used for debug purpose.
- [..]
- Once the device started from reset, the user application has to:
- (+) Configure the clock source to be used to drive the System clock
- (if the application needs higher frequency/performance)
- (+) Configure the System clock frequency and Flash settings
- (+) Configure the AHB and APB busses prescalers
- (+) Enable the clock for the peripheral(s) to be used
- (+) Configure the clock source(s) for peripherals which clocks are not
- derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RCC
- * @brief RCC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define CR_OFFSET (RCC_OFFSET + 0x00)
-#define HSION_BitNumber 0x00
-#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
-/* Alias word address of CSSON bit */
-#define CSSON_BitNumber 0x13
-#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
-/* Alias word address of PLLON bit */
-#define PLLON_BitNumber 0x18
-#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
-/* Alias word address of PLLI2SON bit */
-#define PLLI2SON_BitNumber 0x1A
-#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
-
-/* --- CFGR Register ---*/
-/* Alias word address of I2SSRC bit */
-#define CFGR_OFFSET (RCC_OFFSET + 0x08)
-#define I2SSRC_BitNumber 0x17
-#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
-
-/* --- BDCR Register ---*/
-/* Alias word address of RTCEN bit */
-#define BDCR_OFFSET (RCC_OFFSET + 0x70)
-#define RTCEN_BitNumber 0x0F
-#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
-/* Alias word address of BDRST bit */
-#define BDRST_BitNumber 0x10
-#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define CSR_OFFSET (RCC_OFFSET + 0x74)
-#define LSION_BitNumber 0x00
-#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
-
-/* --- DCKCFGR Register ---*/
-/* Alias word address of TIMPRE bit */
-#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
-#define TIMPRE_BitNumber 0x18
-#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
-/* ---------------------- RCC registers bit mask ------------------------ */
-/* CFGR register bit mask */
-#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
-#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
-
-/* RCC Flag Mask */
-#define FLAG_MASK ((uint8_t)0x1F)
-
-/* CR register byte 3 (Bits[23:16]) base address */
-#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
-
-/* BDCR register base address */
-#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Private_Functions
- * @{
- */
-
-/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
- * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
- *
-@verbatim
- ===================================================================================
- ##### Internal and external clocks, PLL, CSS and MCO configuration functions #####
- ===================================================================================
- [..]
- This section provide functions allowing to configure the internal/external clocks,
- PLLs, CSS and MCO pins.
-
- (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
- the PLL as System clock source.
-
- (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
- clock source.
-
- (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
-
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
-
- (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
- (++) The first output is used to generate the high speed system clock (up to 168 MHz)
- (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
- the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
-
- (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve
- high-quality audio performance on the I2S interface.
-
- (#) CSS (Clock security system), once enable and if a HSE clock failure occurs
- (HSE used directly or through PLL as System clock source), the System clock
- is automatically switched to HSI and an interrupt is generated if enabled.
- The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
- exception vector.
-
- (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
- clock (through a configurable prescaler) on PA8 pin.
-
- (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
- clock (through a configurable prescaler) on PC9 pin.
- @endverbatim
- * @{
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE, PLL and PLLI2S OFF
- * - AHB, APB1 and APB2 prescaler set to 1.
- * - CSS, MCO1 and MCO2 OFF
- * - All interrupts disabled
- * @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @param None
- * @retval None
- */
-void RCC_DeInit(void)
-{
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON, PLLON and PLLI2S bits */
- RCC->CR &= (uint32_t)0xFAF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
- /* Reset PLLI2SCFGR register */
- RCC->PLLI2SCFGR = 0x20003000;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
-#ifdef STM32F427X
- /* Disable Timers clock prescalers selection */
- RCC->DCKCFGR = 0x00000000;
-#endif /* STM32F427X */
-
-}
-
-/**
- * @brief Configures the External High Speed oscillator (HSE).
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function reset the CSSON bit, so if the Clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param RCC_HSE: specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg RCC_HSE_ON: turn ON the HSE oscillator
- * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_HSEConfig(uint8_t RCC_HSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_HSE));
-
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
-
- /* Set the new HSE configuration -------------------------------------------*/
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
-}
-
-/**
- * @brief Waits for HSE start-up.
- * @note This functions waits on HSERDY flag to be set and return SUCCESS if
- * this flag is set, otherwise returns ERROR if the timeout is reached
- * and this flag is not set. The timeout value is defined by the constant
- * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending
- * on the HSE crystal used in your application.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: HSE oscillator is stable and ready to use
- * - ERROR: HSE oscillator not yet ready
- */
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
- __IO uint32_t startupcounter = 0;
- ErrorStatus status = ERROR;
- FlagStatus hsestatus = RESET;
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
- startupcounter++;
- } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
-
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- return (status);
-}
-
-/**
- * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param HSICalibrationValue: specifies the calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- * @retval None
- */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
-
- tmpreg = RCC->CR;
-
- /* Clear HSITRIM[4:0] bits */
- tmpreg &= ~RCC_CR_HSITRIM;
-
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
- tmpreg |= (uint32_t)HSICalibrationValue << 3;
-
- /* Store the new value */
- RCC->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after startup
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
- * of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * @param NewState: new state of the HSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_HSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE).
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param RCC_LSE: specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg RCC_LSE_ON: turn ON the LSE oscillator
- * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_LSEConfig(uint8_t RCC_LSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_LSE));
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
- /* Reset LSEON bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-
- /* Reset LSEBYP bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-
- /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
- switch (RCC_LSE)
- {
- case RCC_LSE_ON:
- /* Set LSEON bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
- break;
- case RCC_LSE_Bypass:
- /* Set LSEBYP and LSEON bits */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Enables or disables the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @param NewState: new state of the LSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_LSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the main PLL clock source, multiplication and division factors.
- * @note This function must be used only when the main PLL is disabled.
- *
- * @param RCC_PLLSource: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
- * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- *
- * @param PLLM: specifies the division factor for PLL VCO input clock
- * This parameter must be a number between 0 and 63.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
- * of 2 MHz to limit PLL jitter.
- *
- * @param PLLN: specifies the multiplication factor for PLL VCO output clock
- * This parameter must be a number between 192 and 432.
- * @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
- *
- * @param PLLP: specifies the division factor for main system clock (SYSCLK)
- * This parameter must be a number in the range {2, 4, 6, or 8}.
- * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
- * the System clock frequency.
- *
- * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
- * This parameter must be a number between 4 and 15.
- * @note If the USB OTG FS is used in your application, you have to set the
- * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
- * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
- * correctly.
- *
- * @retval None
- */
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
- assert_param(IS_RCC_PLLM_VALUE(PLLM));
- assert_param(IS_RCC_PLLN_VALUE(PLLN));
- assert_param(IS_RCC_PLLP_VALUE(PLLP));
- assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
-
- RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
- (PLLQ << 24);
-}
-
-/**
- * @brief Enables or disables the main PLL.
- * @note After enabling the main PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The main PLL can not be disabled if it is used as system clock source
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the PLLI2S clock multiplication and division factors.
- *
- * @note This function must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * RCC_PLLConfig function )
- *
- * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between 192 and 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
- *
- * @param PLLI2SR: specifies the division factor for I2S clock
- * This parameter must be a number between 2 and 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
- *
- * @retval None
- */
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
- assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
-
- RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
-}
-
-/**
- * @brief Enables or disables the PLLI2S.
- * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLI2SCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
- * @param NewState: new state of the Clock Security System.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Selects the clock source to output on MCO1 pin(PA8).
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCO1Source: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
- * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
- * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
- * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
- * @param RCC_MCO1Div: specifies the MCO1 prescaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCO1Div_1: no division applied to MCO1 clock
- * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
- * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
- * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
- * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
- * @retval None
- */
-void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
- assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));
-
- tmpreg = RCC->CFGR;
-
- /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
- tmpreg &= CFGR_MCO1_RESET_MASK;
-
- /* Select MCO1 clock source and prescaler */
- tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Selects the clock source to output on MCO2 pin(PC9).
- * @note PC9 should be configured in alternate function mode.
- * @param RCC_MCO2Source: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
- * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
- * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
- * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
- * @param RCC_MCO2Div: specifies the MCO2 prescaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCO2Div_1: no division applied to MCO2 clock
- * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
- * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
- * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
- * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
- * @retval None
- */
-void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
- assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
-
- tmpreg = RCC->CFGR;
-
- /* Clear MCO2 and MCO2PRE[2:0] bits */
- tmpreg &= CFGR_MCO2_RESET_MASK;
-
- /* Select MCO2 clock source and prescaler */
- tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
- * @brief System, AHB and APB busses clocks configuration functions
- *
-@verbatim
- ===============================================================================
- ##### System, AHB and APB busses clocks configuration functions #####
- ===============================================================================
- [..]
- This section provide functions allowing to configure the System, AHB, APB1 and
- APB2 busses clocks.
-
- (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable
- prescaler and used to clock the CPU, memory and peripherals mapped
- on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
- from AHB clock through configurable prescalers and used to clock
- the peripherals mapped on these busses. You can use
- "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
-
- -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
- (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
- from an external clock mapped on the I2S_CKIN pin.
- You have to use RCC_I2SCLKConfig() function to configure this clock.
- (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
- divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
- functions to configure this clock.
- (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
- to work correctly, while the SDIO require a frequency equal or lower than
- to 48. This clock is derived of the main PLL through PLLQ divider.
- (+@) IWDG clock which is always the LSI clock.
-
- (#) The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz
- and PCLK1 42 MHz. Depending on the device voltage range, the maximum
- frequency should be adapted accordingly:
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120|
- +-------------------------------------------------------------------------------------+
- -@- When VOS bits (in PWR_CR register) is reset to 0 , the maximum value of HCLK is 144 MHz.
- You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the system clock (SYSCLK).
- * @note The HSI is used (enabled by hardware) as system clock source after
- * startup from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * You can use RCC_GetSYSCLKSource() function to know which clock is
- * currently used as system clock source.
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
- * @retval None
- */
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-
- tmpreg = RCC->CFGR;
-
- /* Clear SW[1:0] bits */
- tmpreg &= ~RCC_CFGR_SW;
-
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
- tmpreg |= RCC_SYSCLKSource;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the clock source used as system clock.
- * @param None
- * @retval The clock source used as system clock. The returned value can be one
- * of the following:
- * - 0x00: HSI used as system clock
- * - 0x04: HSE used as system clock
- * - 0x08: PLL used as system clock
- */
-uint8_t RCC_GetSYSCLKSource(void)
-{
- return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
-}
-
-/**
- * @brief Configures the AHB clock (HCLK).
- * @note Depending on the device voltage range, the software has to set correctly
- * these bits to ensure that HCLK not exceed the maximum allowed frequency
- * (for more details refer to section above
- * "CPU, AHB and APB busses clocks configuration functions")
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
- * the system clock (SYSCLK).
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
- * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
- * @retval None
- */
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear HPRE[3:0] bits */
- tmpreg &= ~RCC_CFGR_HPRE;
-
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
- tmpreg |= RCC_SYSCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-
-/**
- * @brief Configures the Low Speed APB clock (PCLK1).
- * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB1 clock = HCLK
- * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK1Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE1[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE1;
-
- /* Set PPRE1[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the High Speed APB clock (PCLK2).
- * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB2 clock = HCLK
- * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK2Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE2[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE2;
-
- /* Set PPRE2[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK << 3;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK,
- * PCLK1 and PCLK2.
- *
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
- * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
- * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
- * the clocks frequencies.
- *
- * @note This function can be used by the user application to compute the
- * baudrate for the communication peripherals or configure other parameters.
- * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
- * must be called to update the structure's field. Otherwise, any
- * configuration based on this function will be incorrect.
- *
- * @retval None
- */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
- uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock source */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLP
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
- break;
- default:
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- }
- /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
-
- /* Get HCLK prescaler */
- tmp = RCC->CFGR & RCC_CFGR_HPRE;
- tmp = tmp >> 4;
- presc = APBAHBPrescTable[tmp];
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
-
- /* Get PCLK1 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE1;
- tmp = tmp >> 10;
- presc = APBAHBPrescTable[tmp];
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-
- /* Get PCLK2 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE2;
- tmp = tmp >> 13;
- presc = APBAHBPrescTable[tmp];
- /* PCLK2 clock frequency */
- RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group3 Peripheral clocks configuration functions
- * @brief Peripheral clocks configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral clocks configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to configure the Peripheral clocks.
-
- (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided
- by 2 to 31.
-
- (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
- except internal SRAM, Flash and JTAG. Before to start using a peripheral
- you have to enable its interface clock. You can do this using
- RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
-
- (#) To reset the peripherals configuration (to the default state after device reset)
- you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
- RCC_APB1PeriphResetCmd() functions.
-
- (#) To further reduce power consumption in SLEEP mode the peripheral clocks
- can be disabled prior to executing the WFI or WFE instructions.
- You can do this using RCC_AHBPeriphClockLPModeCmd(),
- RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using PWR_BackupAccessCmd(ENABLE) function before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the
- * Backup domain is reset using RCC_BackupResetCmd() function, or by
- * a Power On Reset (POR).
- *
- * @param RCC_RTCCLKSource: specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
- * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
- * as RTC clock, where x:[2,31]
- *
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
- * RTC clock source).
- *
- * @retval None
- */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-
- if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
- { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
- tmpreg = RCC->CFGR;
-
- /* Clear RTCPRE[4:0] bits */
- tmpreg &= ~RCC_CFGR_RTCPRE;
-
- /* Configure HSE division factor for RTC clock */
- tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
- }
-
- /* Select the RTC clock source */
- RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
-}
-
-/**
- * @brief Enables or disables the RTC clock.
- * @note This function must be used only after the RTC clock source was selected
- * using the RCC_RTCCLKConfig function.
- * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Forces or releases the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_CSR register.
- * @note The BKPSRAM is not affected by this reset.
- * @param NewState: new state of the Backup domain reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_BackupResetCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the I2S clock source (I2SCLK).
- * @note This function must be called before enabling the I2S APB clock.
- * @param RCC_I2SCLKSource: specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
- * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
- * used as I2S clock source
- * @retval None
- */
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
-
- *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
-}
-
-/**
- * @brief Configures the Timers clocks prescalers selection.
- *
- * @note This feature is only available with STM32F427x/437x Devices.
- * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection
- * This parameter can be one of the following values:
- * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is
- * equal to HPRE if PPREx is corresponding to division by 1 or 2,
- * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
- * division by 4 or more.
- *
- * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is
- * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
- * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
- * to division by 8 or more.
- * @retval None
- */
-void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
-{
- /* Check the parameters */
- assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler));
-
- *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler;
-
-}
-
-/**
- * @brief Enables or disables the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
- * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
- * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
- * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
-
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB1ENR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1ENR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB2ENR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2ENR &= ~RCC_AHB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB3 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
- * This parameter must be: RCC_AHB3Periph_FSMC
- *
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB3ENR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3ENR &= ~RCC_AHB3Periph;
- }
-}
-
-/**
- * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @arg RCC_APB1Periph_UART7: UART7 clock
- * @arg RCC_APB1Periph_UART8: UART8 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1ENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1ENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SPI4: SPI4 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @arg RCC_APB2Periph_SPI5: SPI5 clock
- * @arg RCC_APB2Periph_SPI6: SPI6 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2ENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2ENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB1 peripheral reset.
- * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- *
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB1RSTR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1RSTR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB2 peripheral reset.
- * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB2RSTR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2RSTR &= ~RCC_AHB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB3 peripheral reset.
- * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
- * This parameter must be: RCC_AHB3Periph_FSMC
- *
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB3RSTR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3RSTR &= ~RCC_AHB3Periph;
- }
-}
-
-/**
- * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @arg RCC_APB1Periph_UART7: UART7 clock
- * @arg RCC_APB1Periph_UART8: UART8 clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB1RSTR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1RSTR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases High Speed APB (APB2) peripheral reset.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SPI4: SPI4 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @arg RCC_APB2Periph_SPI5: SPI5 clock
- * @arg RCC_APB2Periph_SPI6: SPI6 clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB2RSTR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2RSTR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
- * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
- * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB1LPENR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1LPENR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB2LPENR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2LPENR &= ~RCC_AHB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
- * This parameter must be: RCC_AHB3Periph_FSMC
- *
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB3LPENR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3LPENR &= ~RCC_AHB3Periph;
- }
-}
-
-/**
- * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @arg RCC_APB1Periph_UART7: UART7 clock
- * @arg RCC_APB1Periph_UART8: UART8 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB1LPENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1LPENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SPI4: SPI4 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @arg RCC_APB2Periph_SPI5: SPI5 clock
- * @arg RCC_APB2Periph_SPI6: SPI6 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB2LPENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2LPENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RCC interrupts.
- * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- *
- * @param NewState: new state of the specified RCC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_IT(RCC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
- }
- else
- {
- /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified RCC flag is set or not.
- * @param RCC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
- * @arg RCC_FLAG_PLLRDY: main PLL clock ready
- * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
- * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
- * @arg RCC_FLAG_PINRST: Pin reset
- * @arg RCC_FLAG_PORRST: POR/PDR reset
- * @arg RCC_FLAG_SFTRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPWRRST: Low Power reset
- * @retval The new state of RCC_FLAG (SET or RESET).
- */
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
-{
- uint32_t tmp = 0;
- uint32_t statusreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_FLAG(RCC_FLAG));
-
- /* Get the RCC register index */
- tmp = RCC_FLAG >> 5;
- if (tmp == 1) /* The flag to check is in CR register */
- {
- statusreg = RCC->CR;
- }
- else if (tmp == 2) /* The flag to check is in BDCR register */
- {
- statusreg = RCC->BDCR;
- }
- else /* The flag to check is in CSR register */
- {
- statusreg = RCC->CSR;
- }
-
- /* Get the flag position */
- tmp = RCC_FLAG & FLAG_MASK;
- if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC reset flags.
- * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
- * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
- * @param None
- * @retval None
- */
-void RCC_ClearFlag(void)
-{
- /* Set RMVF bit to clear the reset flags */
- RCC->CSR |= RCC_CSR_RMVF;
-}
-
-/**
- * @brief Checks whether the specified RCC interrupt has occurred or not.
- * @param RCC_IT: specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval The new state of RCC_IT (SET or RESET).
- */
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_GET_IT(RCC_IT));
-
- /* Check the status of the specified RCC interrupt */
- if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the RCC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC's interrupt pending bits.
- * @param RCC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval None
- */
-void RCC_ClearITPendingBit(uint8_t RCC_IT)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
- pending bits */
- *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
deleted file mode 100644
index 6d0e65d9..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
+++ /dev/null
@@ -1,397 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_rng.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Random Number Generator (RNG) peripheral:
- * + Initialization and Configuration
- * + Get 32 bit Random number
- * + Interrupts and flags management
- *
-@verbatim
-
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable The RNG controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function.
-
- (#) Activate the RNG peripheral using RNG_Cmd() function.
-
- (#) Wait until the 32 bit Random number Generator contains a valid random data
- (using polling/interrupt mode). For more details, refer to "Interrupts and
- flags management functions" module description.
-
- (#) Get the 32 bit Random number using RNG_GetRandomNumber() function
-
- (#) To get another 32 bit Random number, go to step 3.
-
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RNG
- * @brief RNG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RNG_Private_Functions
- * @{
- */
-
-/** @defgroup RNG_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initialize the RNG peripheral
- (+) Enable or disable the RNG peripheral
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the RNG peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void RNG_DeInit(void)
-{
- /* Enable RNG reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE);
-
- /* Release RNG from reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE);
-}
-
-/**
- * @brief Enables or disables the RNG peripheral.
- * @param NewState: new state of the RNG peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RNG_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the RNG */
- RNG->CR |= RNG_CR_RNGEN;
- }
- else
- {
- /* Disable the RNG */
- RNG->CR &= ~RNG_CR_RNGEN;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup RNG_Group2 Get 32 bit Random number function
- * @brief Get 32 bit Random number function
- *
-
-@verbatim
- ===============================================================================
- ##### Get 32 bit Random number function #####
- ===============================================================================
- [..] This section provides a function allowing to get the 32 bit Random number
-
- (@) Before to call this function you have to wait till DRDY flag is set,
- using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Returns a 32-bit random number.
- *
- * @note Before to call this function you have to wait till DRDY (data ready)
- * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
- * @note Each time the the Random number data is read (using RNG_GetRandomNumber()
- * function), the RNG_FLAG_DRDY flag is automatically cleared.
- * @note In the case of a seed error, the generation of random numbers is
- * interrupted for as long as the SECS bit is '1'. If a number is
- * available in the RNG_DR register, it must not be used because it may
- * not have enough entropy. In this case, it is recommended to clear the
- * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable
- * and enable the RNG peripheral (using RNG_Cmd() function) to
- * reinitialize and restart the RNG.
- * @note In the case of a clock error, the RNG is no more able to generate
- * random numbers because the PLL48CLK clock is not correct. User have
- * to check that the clock controller is correctly configured to provide
- * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS)
- * function) . The clock error has no impact on the previously generated
- * random numbers, and the RNG_DR register contents can be used.
- *
- * @param None
- * @retval 32-bit random number.
- */
-uint32_t RNG_GetRandomNumber(void)
-{
- /* Return the 32 bit random number from the DR register */
- return RNG->DR;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup RNG_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the RNG Interrupts and
- to get the status and clear flags and Interrupts pending bits.
-
- [..] The RNG provides 3 Interrupts sources and 3 Flags:
-
- *** Flags : ***
- ===============
- [..]
- (#) RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid
- random data. it is cleared by reading the valid data(using
- RNG_GetRandomNumber() function).
-
- (#) RNG_FLAG_CECS : In the case of a seed error detection.
-
- (#) RNG_FLAG_SECS : In the case of a clock error detection.
-
- *** Interrupts ***
- ==================
- [..] If enabled, an RNG interrupt is pending :
-
- (#) In the case of the RNG_DR register contains valid random data.
- This interrupt source is cleared once the RNG_DR register has been read
- (using RNG_GetRandomNumber() function) until a new valid value is
- computed; or
- (#) In the case of a seed error : One of the following faulty sequences has
- been detected:
- (++) More than 64 consecutive bits at the same value (0 or 1)
- (++) More than 32 consecutive alternance of 0 and 1 (0101010101...01)
- This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI)
- function; or
- (#) In the case of a clock error : the PLL48CLK (RNG peripheral clock source)
- was not correctly detected (fPLL48CLK< fHCLK/16). This interrupt source is
- cleared using RNG_ClearITPendingBit(RNG_IT_CEI) function.
- -@- note In this case, User have to check that the clock controller is
- correctly configured to provide the RNG clock.
-
- *** Managing the RNG controller events : ***
- ============================================
- [..] The user should identify which mode will be used in his application to manage
- the RNG controller events: Polling mode or Interrupt mode.
-
- (#) In the Polling Mode it is advised to use the following functions:
- (++) RNG_GetFlagStatus() : to check if flags events occur.
- (++) RNG_ClearFlag() : to clear the flags events.
-
- -@@- RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only
- by reading the Random number data.
-
- (#) In the Interrupt Mode it is advised to use the following functions:
- (++) RNG_ITConfig() : to enable or disable the interrupt source.
- (++) RNG_GetITStatus() : to check if Interrupt occurs.
- (++) RNG_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the RNG interrupt.
- * @note The RNG provides 3 interrupt sources,
- * - Computed data is ready event (DRDY), and
- * - Seed error Interrupt (SEI) and
- * - Clock error Interrupt (CEI),
- * all these interrupts sources are enabled by setting the IE bit in
- * CR register. However, each interrupt have its specific status bit
- * (see RNG_GetITStatus() function) and clear bit except the DRDY event
- * (see RNG_ClearITPendingBit() function).
- * @param NewState: new state of the RNG interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RNG_ITConfig(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the RNG interrupt */
- RNG->CR |= RNG_CR_IE;
- }
- else
- {
- /* Disable the RNG interrupt */
- RNG->CR &= ~RNG_CR_IE;
- }
-}
-
-/**
- * @brief Checks whether the specified RNG flag is set or not.
- * @param RNG_FLAG: specifies the RNG flag to check.
- * This parameter can be one of the following values:
- * @arg RNG_FLAG_DRDY: Data Ready flag.
- * @arg RNG_FLAG_CECS: Clock Error Current flag.
- * @arg RNG_FLAG_SECS: Seed Error Current flag.
- * @retval The new state of RNG_FLAG (SET or RESET).
- */
-FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_RNG_GET_FLAG(RNG_FLAG));
-
- /* Check the status of the specified RNG flag */
- if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET)
- {
- /* RNG_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* RNG_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the RNG_FLAG status */
- return bitstatus;
-}
-
-
-/**
- * @brief Clears the RNG flags.
- * @param RNG_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg RNG_FLAG_CECS: Clock Error Current flag.
- * @arg RNG_FLAG_SECS: Seed Error Current flag.
- * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function.
- * This flag is cleared only by reading the Random number data (using
- * RNG_GetRandomNumber() function).
- * @retval None
- */
-void RNG_ClearFlag(uint8_t RNG_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG));
- /* Clear the selected RNG flags */
- RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4);
-}
-
-/**
- * @brief Checks whether the specified RNG interrupt has occurred or not.
- * @param RNG_IT: specifies the RNG interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RNG_IT_CEI: Clock Error Interrupt.
- * @arg RNG_IT_SEI: Seed Error Interrupt.
- * @retval The new state of RNG_IT (SET or RESET).
- */
-ITStatus RNG_GetITStatus(uint8_t RNG_IT)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_RNG_GET_IT(RNG_IT));
-
- /* Check the status of the specified RNG interrupt */
- if ((RNG->SR & RNG_IT) != (uint8_t)RESET)
- {
- /* RNG_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* RNG_IT is reset */
- bitstatus = RESET;
- }
- /* Return the RNG_IT status */
- return bitstatus;
-}
-
-
-/**
- * @brief Clears the RNG interrupt pending bit(s).
- * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear.
- * This parameter can be any combination of the following values:
- * @arg RNG_IT_CEI: Clock Error Interrupt.
- * @arg RNG_IT_SEI: Seed Error Interrupt.
- * @retval None
- */
-void RNG_ClearITPendingBit(uint8_t RNG_IT)
-{
- /* Check the parameters */
- assert_param(IS_RNG_IT(RNG_IT));
-
- /* Clear the selected RNG interrupt pending bit */
- RNG->SR = (uint8_t)~RNG_IT;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
deleted file mode 100644
index d4b22d29..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
+++ /dev/null
@@ -1,2761 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_rtc.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Real-Time Clock (RTC) peripheral:
- * + Initialization
- * + Calendar (Time and Date) configuration
- * + Alarms (Alarm A and Alarm B) configuration
- * + WakeUp Timer configuration
- * + Daylight Saving configuration
- * + Output pin Configuration
- * + Coarse digital Calibration configuration
- * + Smooth digital Calibration configuration
- * + TimeStamp configuration
- * + Tampers configuration
- * + Backup Data Registers configuration
- * + Shift control synchronisation
- * + RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
- * + Interrupts and flags management
- *
-@verbatim
-
- ===================================================================
- ##### Backup Domain Operating Condition #####
- ===================================================================
- [..] The real-time clock (RTC), the RTC backup registers, and the backup
- SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
- VDD supply is powered off.
- To retain the content of the RTC backup registers, backup SRAM, and supply
- the RTC when VDD is turned off, VBAT pin can be connected to an optional
- standby voltage supplied by a battery or by another source.
-
- [..] To allow the RTC to operate even when the main digital supply (VDD) is turned
- off, the VBAT pin powers the following blocks:
- (#) The RTC
- (#) The LSE oscillator
- (#) The backup SRAM when the low power backup regulator is enabled
- (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
-
- [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
- the following functions are available:
- (#) PC14 and PC15 can be used as either GPIO or LSE pins
- (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
- (#) PI8 can be used as a GPIO or as the RTC_AF2 pin
-
- [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
- because VDD is not present), the following functions are available:
- (#) PC14 and PC15 can be used as LSE pins only
- (#) PC13 can be used as the RTC_AF1 pin
- (#) PI8 can be used as the RTC_AF2 pin
-
-
- ##### Backup Domain Reset #####
- ===================================================================
- [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
- to their reset values. The BKPSRAM is not affected by this reset. The only
- way of resetting the BKPSRAM is through the Flash interface by requesting
- a protection level change from 1 to 0.
- [..] A backup domain reset is generated when one of the following events occurs:
- (#) Software reset, triggered by setting the BDRST bit in the
- RCC Backup domain control register (RCC_BDCR). You can use the
- RCC_BackupResetCmd().
- (#) VDD or VBAT power on, if both supplies have previously been powered off.
-
-
- ##### Backup Domain Access #####
- ===================================================================
- [..] After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted write
- accesses.
- [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
- (+) Enable the Power Controller (PWR) APB1 interface clock using the
- RCC_APB1PeriphClockCmd() function.
- (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function.
- (+) Select the RTC clock source using the RCC_RTCCLKConfig() function.
- (+) Enable RTC Clock using the RCC_RTCCLKCmd() function.
-
-
- ##### How to use RTC Driver #####
- ===================================================================
- [..]
- (+) Enable the RTC domain access (see description in the section above)
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
- format using the RTC_Init() function.
-
- *** Time and Date configuration ***
- ===================================
- [..]
- (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
- and RTC_SetDate() functions.
- (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() functions.
- (+) Use the RTC_DayLightSavingConfig() function to add or sub one
- hour to the RTC Calendar.
-
- *** Alarm configuration ***
- ===========================
- [..]
- (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
- (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function
- (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
- (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
-
- *** RTC Wakeup configuration ***
- ================================
- [..]
- (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
- function.
- (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() function
- (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function
- (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter()
- function.
-
- *** Outputs configuration ***
- =============================
- [..] The RTC has 2 different outputs:
- (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
- and WaKeUp signals. To output the selected RTC signal on RTC_AF1 pin, use the
- RTC_OutputConfig() function.
- (+) AFO_CALIB: this output is 512Hz signal or 1Hz. To output the RTC Clock on
- RTC_AF1 pin, use the RTC_CalibOutputCmd() function.
-
- *** Smooth digital Calibration configuration ***
- ================================================
- [..]
- (+) Configure the RTC Original Digital Calibration Value and the corresponding
- calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
- function.
-
- *** Coarse digital Calibration configuration ***
- ================================================
- [..]
- (+) Configure the RTC Coarse Calibration Value and the corresponding
- sign using the RTC_CoarseCalibConfig() function.
- (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() function
-
- *** TimeStamp configuration ***
- ===============================
- [..]
- (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp using the RTC
- _TimeStampCmd() function.
- (+) To read the RTC TimeStamp Time and Date register, use the RTC_GetTimeStamp()
- function.
- (+) To read the RTC TimeStamp SubSecond register, use the
- RTC_GetTimeStampSubSecond() function.
- (+) The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13)
- or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in
- RTC_TAFCR register. You can use the RTC_TamperPinSelection() function to
- select the corresponding pin.
-
- *** Tamper configuration ***
- ============================
- [..]
- (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
- (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
- function.
- (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper
- filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig()
- function.
- (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
- function.
- (+) Configure the Tamper precharge or discharge duration using
- RTC_TamperPinsPrechargeDuration() function.
- (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
- (+) Enable the Time stamp on Tamper detection event using
- TC_TSOnTamperDetecCmd() function.
- (+) The TIMESTAMP alternate function can be mapped to either RTC_AF1
- or RTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR
- register. You can use the RTC_TimeStampPinSelection() function to select
- the corresponding pin.
-
- *** Backup Data Registers configuration ***
- ===========================================
- [..]
- (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
- function.
- (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
- function.
-
-
- ##### RTC and low power modes #####
- ===================================================================
- [..] The MCU can be woken up from a low power mode by an RTC alternate
- function.
- [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
- RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
- These RTC alternate functions can wake up the system from the Stop and
- Standby lowpower modes.
- [..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm
- or the RTC wakeup events.
- [..] The RTC provides a programmable time base for waking up from the
- Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC clock source
- is LSE or LSI.
-
-
- ##### Selection of RTC_AF1 alternate functions #####
- ===================================================================
- [..] The RTC_AF1 pin (PC13) can be used for the following purposes:
- (+) AFO_ALARM output
- (+) AFO_CALIB output
- (+) AFI_TAMPER
- (+) AFI_TIMESTAMP
-
- [..]
- +-------------------------------------------------------------------------------------------------------------+
- | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |
- | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |
- | and function | | | | | selection | selection |Configuration |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | Alarm out | | | | | Don't | Don't | |
- | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | Alarm out | | | | | Don't | Don't | |
- | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | Calibration out | | | | | Don't | Don't | |
- | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | TAMPER input | | | | | | Don't | |
- | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | TIMESTAMP and | | | | | | | |
- | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care |
- | floating | | | | | | | |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | TIMESTAMP input | | | | | Don't | | |
- | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care |
- +-------------------------------------------------------------------------------------------------------------+
-
-
- ##### Selection of RTC_AF2 alternate functions #####
- ===================================================================
- [..] The RTC_AF2 pin (PI8) can be used for the following purposes:
- (+) AFI_TAMPER
- (+) AFI_TIMESTAMP
- [..]
- +---------------------------------------------------------------------------------------+
- | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |
- | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |
- | and function | | | selection | selection |Configuration |
- |-----------------|-----------|--------------|------------|--------------|--------------|
- | TAMPER input | | | | Don't | |
- | floating | 1 | 0 | 1 | care | Don't care |
- |-----------------|-----------|--------------|------------|--------------|--------------|
- | TIMESTAMP and | | | | | |
- | TAMPER input | 1 | 1 | 1 | 1 | Don't care |
- | floating | | | | | |
- |-----------------|-----------|--------------|------------|--------------|--------------|
- | TIMESTAMP input | | | Don't | | |
- | floating | 0 | 1 | care | 1 | Don't care |
- |-----------------|-----------|--------------|------------|--------------|--------------|
- | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care |
- +---------------------------------------------------------------------------------------+
-
-
-@endverbatim
-
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_sdio.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SDIO
- * @brief SDIO driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ------------ SDIO registers bit address in the alias region ----------- */
-#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
-
-/* --- CLKCR Register ---*/
-/* Alias word address of CLKEN bit */
-#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
-#define CLKEN_BitNumber 0x08
-#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
-
-/* --- CMD Register ---*/
-/* Alias word address of SDIOSUSPEND bit */
-#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
-#define SDIOSUSPEND_BitNumber 0x0B
-#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
-
-/* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BitNumber 0x0C
-#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
-
-/* Alias word address of NIEN bit */
-#define NIEN_BitNumber 0x0D
-#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
-
-/* Alias word address of ATACMD bit */
-#define ATACMD_BitNumber 0x0E
-#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
-
-/* --- DCTRL Register ---*/
-/* Alias word address of DMAEN bit */
-#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
-#define DMAEN_BitNumber 0x03
-#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
-
-/* Alias word address of RWSTART bit */
-#define RWSTART_BitNumber 0x08
-#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
-
-/* Alias word address of RWSTOP bit */
-#define RWSTOP_BitNumber 0x09
-#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
-
-/* Alias word address of RWMOD bit */
-#define RWMOD_BitNumber 0x0A
-#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
-
-/* Alias word address of SDIOEN bit */
-#define SDIOEN_BitNumber 0x0B
-#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
-
-/* ---------------------- SDIO registers bit mask ------------------------ */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */
-#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
-
-/* --- PWRCTRL Register ---*/
-/* SDIO PWRCTRL Mask */
-#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
-
-/* --- DCTRL Register ---*/
-/* SDIO DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
-
-/* SDIO RESP Registers Address */
-#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SDIO_Private_Functions
- * @{
- */
-
-/** @defgroup SDIO_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the SDIO peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void SDIO_DeInit(void)
-{
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE);
-}
-
-/**
- * @brief Initializes the SDIO peripheral according to the specified
- * parameters in the SDIO_InitStruct.
- * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
- * that contains the configuration information for the SDIO peripheral.
- * @retval None
- */
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
- assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
- assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
- assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
- assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
-
-/*---------------------------- SDIO CLKCR Configuration ------------------------*/
- /* Get the SDIO CLKCR value */
- tmpreg = SDIO->CLKCR;
-
- /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
- tmpreg &= CLKCR_CLEAR_MASK;
-
- /* Set CLKDIV bits according to SDIO_ClockDiv value */
- /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
- /* Set BYPASS bit according to SDIO_ClockBypass value */
- /* Set WIDBUS bits according to SDIO_BusWide value */
- /* Set NEGEDGE bits according to SDIO_ClockEdge value */
- /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
- tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
- SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
- SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
-
- /* Write to SDIO CLKCR */
- SDIO->CLKCR = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_InitStruct member with its default value.
- * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
-{
- /* SDIO_InitStruct members default value */
- SDIO_InitStruct->SDIO_ClockDiv = 0x00;
- SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
- SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
- SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
- SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
- SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
-}
-
-/**
- * @brief Enables or disables the SDIO Clock.
- * @param NewState: new state of the SDIO Clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_ClockCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Sets the power status of the controller.
- * @param SDIO_PowerState: new state of the Power state.
- * This parameter can be one of the following values:
- * @arg SDIO_PowerState_OFF: SDIO Power OFF
- * @arg SDIO_PowerState_ON: SDIO Power ON
- * @retval None
- */
-void SDIO_SetPowerState(uint32_t SDIO_PowerState)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
-
- SDIO->POWER = SDIO_PowerState;
-}
-
-/**
- * @brief Gets the power status of the controller.
- * @param None
- * @retval Power status of the controller. The returned value can be one of the
- * following values:
- * - 0x00: Power OFF
- * - 0x02: Power UP
- * - 0x03: Power ON
- */
-uint32_t SDIO_GetPowerState(void)
-{
- return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions
- * @brief Command path state machine (CPSM) management functions
- *
-@verbatim
- ===============================================================================
- ##### Command path state machine (CPSM) management functions #####
- ===============================================================================
-
- This section provide functions allowing to program and read the Command path
- state machine (CPSM).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SDIO Command according to the specified
- * parameters in the SDIO_CmdInitStruct and send the command.
- * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
- * structure that contains the configuration information for the SDIO
- * command.
- * @retval None
- */
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
- assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
- assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
- assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
-
-/*---------------------------- SDIO ARG Configuration ------------------------*/
- /* Set the SDIO Argument value */
- SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
-
-/*---------------------------- SDIO CMD Configuration ------------------------*/
- /* Get the SDIO CMD value */
- tmpreg = SDIO->CMD;
- /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
- tmpreg &= CMD_CLEAR_MASK;
- /* Set CMDINDEX bits according to SDIO_CmdIndex value */
- /* Set WAITRESP bits according to SDIO_Response value */
- /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
- /* Set CPSMEN bits according to SDIO_CPSM value */
- tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
- | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
-
- /* Write to SDIO CMD */
- SDIO->CMD = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_CmdInitStruct member with its default value.
- * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
-{
- /* SDIO_CmdInitStruct members default value */
- SDIO_CmdInitStruct->SDIO_Argument = 0x00;
- SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
- SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
- SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
- SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
-}
-
-/**
- * @brief Returns command index of last command for which response received.
- * @param None
- * @retval Returns the command index of the last command response received.
- */
-uint8_t SDIO_GetCommandResponse(void)
-{
- return (uint8_t)(SDIO->RESPCMD);
-}
-
-/**
- * @brief Returns response received from the card for the last command.
- * @param SDIO_RESP: Specifies the SDIO response register.
- * This parameter can be one of the following values:
- * @arg SDIO_RESP1: Response Register 1
- * @arg SDIO_RESP2: Response Register 2
- * @arg SDIO_RESP3: Response Register 3
- * @arg SDIO_RESP4: Response Register 4
- * @retval The Corresponding response register value.
- */
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_RESP(SDIO_RESP));
-
- tmp = SDIO_RESP_ADDR + SDIO_RESP;
-
- return (*(__IO uint32_t *) tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions
- * @brief Data path state machine (DPSM) management functions
- *
-@verbatim
- ===============================================================================
- ##### Data path state machine (DPSM) management functions #####
- ===============================================================================
-
- This section provide functions allowing to program and read the Data path
- state machine (DPSM).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SDIO data path according to the specified
- * parameters in the SDIO_DataInitStruct.
- * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure
- * that contains the configuration information for the SDIO command.
- * @retval None
- */
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
- assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
- assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
- assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
- assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
-
-/*---------------------------- SDIO DTIMER Configuration ---------------------*/
- /* Set the SDIO Data TimeOut value */
- SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
-
-/*---------------------------- SDIO DLEN Configuration -----------------------*/
- /* Set the SDIO DataLength value */
- SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
-
-/*---------------------------- SDIO DCTRL Configuration ----------------------*/
- /* Get the SDIO DCTRL value */
- tmpreg = SDIO->DCTRL;
- /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
- tmpreg &= DCTRL_CLEAR_MASK;
- /* Set DEN bit according to SDIO_DPSM value */
- /* Set DTMODE bit according to SDIO_TransferMode value */
- /* Set DTDIR bit according to SDIO_TransferDir value */
- /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
- tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
- | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
-
- /* Write to SDIO DCTRL */
- SDIO->DCTRL = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_DataInitStruct member with its default value.
- * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
- /* SDIO_DataInitStruct members default value */
- SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
- SDIO_DataInitStruct->SDIO_DataLength = 0x00;
- SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
- SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
- SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
- SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
-}
-
-/**
- * @brief Returns number of remaining data bytes to be transferred.
- * @param None
- * @retval Number of remaining data bytes to be transferred
- */
-uint32_t SDIO_GetDataCounter(void)
-{
- return SDIO->DCOUNT;
-}
-
-/**
- * @brief Read one data word from Rx FIFO.
- * @param None
- * @retval Data received
- */
-uint32_t SDIO_ReadData(void)
-{
- return SDIO->FIFO;
-}
-
-/**
- * @brief Write one data word to Tx FIFO.
- * @param Data: 32-bit data word to write.
- * @retval None
- */
-void SDIO_WriteData(uint32_t Data)
-{
- SDIO->FIFO = Data;
-}
-
-/**
- * @brief Returns the number of words left to be written to or read from FIFO.
- * @param None
- * @retval Remaining number of words.
- */
-uint32_t SDIO_GetFIFOCount(void)
-{
- return SDIO->FIFOCNT;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions
- * @brief SDIO IO Cards mode management functions
- *
-@verbatim
- ===============================================================================
- ##### SDIO IO Cards mode management functions #####
- ===============================================================================
-
- This section provide functions allowing to program and read the SDIO IO Cards.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the SD I/O Read Wait operation.
- * @param NewState: new state of the Start SDIO Read Wait operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_StartSDIOReadWait(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
-}
-
-/**
- * @brief Stops the SD I/O Read Wait operation.
- * @param NewState: new state of the Stop SDIO Read Wait operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_StopSDIOReadWait(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
-}
-
-/**
- * @brief Sets one of the two options of inserting read wait interval.
- * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
- * This parameter can be:
- * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
- * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
- * @retval None
- */
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
-
- *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
-}
-
-/**
- * @brief Enables or disables the SD I/O Mode Operation.
- * @param NewState: new state of SDIO specific operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SetSDIOOperation(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the SD I/O Mode suspend command sending.
- * @param NewState: new state of the SD I/O Mode suspend command.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group5 CE-ATA mode management functions
- * @brief CE-ATA mode management functions
- *
-@verbatim
- ===============================================================================
- ##### CE-ATA mode management functions #####
- ===============================================================================
-
- This section provide functions allowing to program and read the CE-ATA card.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the command completion signal.
- * @param NewState: new state of command completion signal.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_CommandCompletionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the CE-ATA interrupt.
- * @param NewState: new state of CE-ATA interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_CEATAITCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
-}
-
-/**
- * @brief Sends CE-ATA command (CMD61).
- * @param NewState: new state of CE-ATA command.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SendCEATACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group6 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
-
- This section provide functions allowing to program SDIO DMA transfer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SDIO DMA request.
- * @param NewState: new state of the selected SDIO DMA request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_DMACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SDIO interrupts.
- * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
- * @param NewState: new state of the specified SDIO interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_IT(SDIO_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the SDIO interrupts */
- SDIO->MASK |= SDIO_IT;
- }
- else
- {
- /* Disable the SDIO interrupts */
- SDIO->MASK &= ~SDIO_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified SDIO flag is set or not.
- * @param SDIO_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress
- * @arg SDIO_FLAG_TXACT: Data transmit in progress
- * @arg SDIO_FLAG_RXACT: Data receive in progress
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval The new state of SDIO_FLAG (SET or RESET).
- */
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SDIO_FLAG(SDIO_FLAG));
-
- if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the SDIO's pending flags.
- * @param SDIO_FLAG: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval None
- */
-void SDIO_ClearFlag(uint32_t SDIO_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
-
- SDIO->ICR = SDIO_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SDIO interrupt has occurred or not.
- * @param SDIO_IT: specifies the SDIO interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
- * @retval The new state of SDIO_IT (SET or RESET).
- */
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SDIO_GET_IT(SDIO_IT));
- if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the SDIO's interrupt pending bits.
- * @param SDIO_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval None
- */
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
-
- SDIO->ICR = SDIO_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
deleted file mode 100644
index f0526c47..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
+++ /dev/null
@@ -1,1312 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_spi.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Serial peripheral interface (SPI):
- * + Initialization and Configuration
- * + Data transfers functions
- * + Hardware CRC Calculation
- * + DMA transfers management
- * + Interrupts and flags management
- *
-@verbatim
-
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable peripheral clock using the following functions
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI4
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI5
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI6.
-
- (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd()
- function. In I2S mode, if an external clock source is used then the I2S
- CKIN pin GPIO clock should also be enabled.
-
- (#) Peripherals alternate function:
- (++) Connect the pin to the desired peripherals' Alternate Function (AF)
- using GPIO_PinAFConfig() function
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd,
- GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function In I2S mode, if an external clock source is
- used then the I2S CKIN pin should be also configured in Alternate
- function Push-pull pull-up mode.
-
- (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
- Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function.
- In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio
- frequency and Polarity using I2S_Init() function. For I2S mode, make sure
- that either:
- (++) I2S PLL is configured using the functions
- RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), RCC_PLLI2SCmd(ENABLE) and
- RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY); or
- (++) External clock source is configured using the function
- RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly
- the define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file.
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- SPI_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function
- (++) Active the needed channel Request using SPI_I2S_DMACmd() function
-
- (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
- I2S_Cmd().
-
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.
-
- (#) Optionally, you can enable/configure the following parameters without
- re-initialization (i.e there is no need to call again SPI_Init() function):
- (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
- is programmed as Data direction parameter using the SPI_Init() function
- it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
- using the SPI_BiDirectionalLineConfig() function.
- (++) When SPI_NSS_Soft is selected as Slave Select Management parameter
- using the SPI_Init() function it can be possible to manage the
- NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
- (++) Reconfigure the data size using the SPI_DataSizeConfig() function
- (++) Enable or disable the SS output using the SPI_SSOutputCmd() function
-
- (#) To use the CRC Hardware calculation feature refer to the Peripheral
- CRC hardware Calculation subsection.
-
-
- [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI
- peripheral is able to manage sending and receiving data simultaneously
- using two data lines. Each SPI peripheral has an extended block called I2Sxext
- (ie. I2S2ext for SPI2 and I2S3ext for SPI3).
- The extension block is not a full SPI IP, it is used only as I2S slave to
- implement full duplex mode. The extension block uses the same clock sources
- as its master.
- To configure I2S full duplex you have to:
-
- (#) Configure SPIx in I2S mode (I2S_Init() function) as described above.
-
- (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to
- I2S_Init() function.
-
- (#) Call I2S_Cmd() for SPIx then for its extended block.
-
- (#) To configure interrupts or DMA requests and to get/clear flag status,
- use I2Sxext instance for the extension block.
-
- [..] Functions that can be called with I2Sxext instances are: I2S_Cmd(),
- I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(),
- SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(),
- SPI_I2S_ClearFlag(), SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().
-
- Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
-
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
- I2S_StructInit(&I2SInitStruct);
- I2SInitStruct.Mode = I2S_Mode_MasterTx;
- I2S_Init(SPI3, &I2SInitStruct);
- I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)
- I2S_Cmd(SPI3, ENABLE);
- I2S_Cmd(SPI3ext, ENABLE);
- ...
- while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
- {}
- SPI_I2S_SendData(SPI3, txdata[i]);
- ...
- while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)
- {}
- rxdata[i] = SPI_I2S_ReceiveData(I2S3ext);
- ...
-
- [..]
- (@) In I2S mode: if an external clock is used as source clock for the I2S,
- then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should
- be enabled and set to the value of the source clock frequency (in Hz).
-
- (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd()
- just after calling the function SPI_Init().
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_spi.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SPI
- * @brief SPI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* SPI registers Masks */
-#define CR1_CLEAR_MASK ((uint16_t)0x3040)
-#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040)
-
-/* RCC PLLs masks */
-#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000)
-#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0)
-
-#define SPI_CR2_FRF ((uint16_t)0x0010)
-#define SPI_SR_TIFRFE ((uint16_t)0x0100)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SPI_Private_Functions
- * @{
- */
-
-/** @defgroup SPI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to initialize the SPI
- Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS
- Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
-
- [..] The SPI_Init() function follows the SPI configuration procedures for Master
- mode and Slave mode (details for these procedures are available in reference
- manual (RM0090)).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initialize the SPIx peripheral registers to their default reset values.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode.
- *
- * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are de-initialized
- * when the relative I2S peripheral is de-initialized (the extended block's clock
- * is managed by the I2S peripheral clock).
- *
- * @retval None
- */
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- if (SPIx == SPI1)
- {
- /* Enable SPI1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
- /* Release SPI1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
- }
- else if (SPIx == SPI2)
- {
- /* Enable SPI2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
- /* Release SPI2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
- }
- else if (SPIx == SPI3)
- {
- /* Enable SPI3 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
- /* Release SPI3 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
- }
- else if (SPIx == SPI4)
- {
- /* Enable SPI4 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE);
- /* Release SPI4 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, DISABLE);
- }
- else if (SPIx == SPI5)
- {
- /* Enable SPI5 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, ENABLE);
- /* Release SPI5 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, DISABLE);
- }
- else
- {
- if (SPIx == SPI6)
- {
- /* Enable SPI6 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, ENABLE);
- /* Release SPI6 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the SPI_InitStruct.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral.
- * @retval None
- */
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
- uint16_t tmpreg = 0;
-
- /* check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Check the SPI parameters */
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
- assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
-/*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
- master/salve mode, CPOL and CPHA */
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
- /* Set LSBFirst bit according to SPI_FirstBit value */
- /* Set BR bits according to SPI_BaudRatePrescaler value */
- /* Set CPOL bit according to SPI_CPOL value */
- /* Set CPHA bit according to SPI_CPHA value */
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
- SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
- SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
- SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
-
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
- /* Write to SPIx CRCPOLY */
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the I2S_InitStruct.
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode).
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral
- * configured in I2S mode.
- *
- * @note The function calculates the optimal prescaler needed to obtain the most
- * accurate audio frequency (depending on the I2S clock source, the PLL values
- * and the product configuration). But in case the prescaler value is greater
- * than 511, the default value (0x02) will be configured instead.
- *
- * @note if an external clock is used as source clock for the I2S, then the define
- * I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set
- * to the value of the the source clock frequency (in Hz).
- *
- * @retval None
- */
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
- uint32_t tmp = 0, i2sclk = 0;
-#ifndef I2S_EXTERNAL_CLOCK_VAL
- uint32_t pllm = 0, plln = 0, pllr = 0;
-#endif /* I2S_EXTERNAL_CLOCK_VAL */
-
- /* Check the I2S parameters */
- assert_param(IS_SPI_23_PERIPH(SPIx));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK;
- SPIx->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = SPIx->I2SCFGR;
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
- {
- i2sodd = (uint16_t)0;
- i2sdiv = (uint16_t)2;
- }
- /* If the requested audio frequency is not the default, compute the prescaler */
- else
- {
- /* Check the frame length (For the Prescaler computing) *******************/
- if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
- {
- /* Packet length is 16 bits */
- packetlength = 1;
- }
- else
- {
- /* Packet length is 32 bits */
- packetlength = 2;
- }
-
- /* Get I2S source Clock frequency ****************************************/
-
- /* If an external I2S clock has to be used, this define should be set
- in the project configuration or in the stm32f4xx_conf.h file */
- #ifdef I2S_EXTERNAL_CLOCK_VAL
- /* Set external clock as I2S clock source */
- if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
- {
- RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Set the I2S clock to the external clock value */
- i2sclk = I2S_EXTERNAL_CLOCK_VAL;
-
- #else /* There is no define for External I2S clock source */
- /* Set PLLI2S as I2S clock source */
- if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
- {
- RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Get the PLLI2SN value */
- plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \
- (RCC_PLLI2SCFGR_PLLI2SN >> 6));
-
- /* Get the PLLI2SR value */
- pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \
- (RCC_PLLI2SCFGR_PLLI2SR >> 28));
-
- /* Get the PLLM value */
- pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
-
- /* Get the I2S source clock value */
- i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);
- #endif /* I2S_EXTERNAL_CLOCK_VAL */
-
- /* Compute the Real divider depending on the MCLK output state, with a floating point */
- if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
-
- /* Remove the flatting point */
- tmp = tmp / 10;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t) (i2sodd << 8);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2) || (i2sdiv > 0xFF))
- {
- /* Set the default values */
- i2sdiv = 2;
- i2sodd = 0;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
- (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
- /* Write to SPIx I2SCFGR */
- SPIx->I2SCFGR = tmpreg;
-}
-
-/**
- * @brief Fills each SPI_InitStruct member with its default value.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
- /* Initialize the SPI_Direction member */
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- /* initialize the SPI_Mode member */
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
- /* initialize the SPI_DataSize member */
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
- /* Initialize the SPI_CPOL member */
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
- /* Initialize the SPI_CPHA member */
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
- /* Initialize the SPI_NSS member */
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
- /* Initialize the SPI_BaudRatePrescaler member */
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
- /* Initialize the SPI_FirstBit member */
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
- /* Initialize the SPI_CRCPolynomial member */
- SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-/**
- * @brief Fills each I2S_InitStruct member with its default value.
- * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
-{
-/*--------------- Reset I2S init structure parameters values -----------------*/
- /* Initialize the I2S_Mode member */
- I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
-
- /* Initialize the I2S_Standard member */
- I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
-
- /* Initialize the I2S_DataFormat member */
- I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
-
- /* Initialize the I2S_MCLKOutput member */
- I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-
- /* Initialize the I2S_AudioFreq member */
- I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
-
- /* Initialize the I2S_CPOL member */
- I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral */
- SPIx->CR1 |= SPI_CR1_SPE;
- }
- else
- {
- /* Disable the selected SPI peripheral */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
- }
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral (in I2S mode).
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext
- * for full duplex mode).
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_23_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral (in I2S mode) */
- SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
- }
- else
- {
- /* Disable the selected SPI peripheral in I2S mode */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
- }
-}
-
-/**
- * @brief Configures the data size for the selected SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_DataSize: specifies the SPI data size.
- * This parameter can be one of the following values:
- * @arg SPI_DataSize_16b: Set data frame format to 16bit
- * @arg SPI_DataSize_8b: Set data frame format to 8bit
- * @retval None
- */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DATASIZE(SPI_DataSize));
- /* Clear DFF bit */
- SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
- /* Set new DFF bit value */
- SPIx->CR1 |= SPI_DataSize;
-}
-
-/**
- * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
- * This parameter can be one of the following values:
- * @arg SPI_Direction_Tx: Selects Tx transmission direction
- * @arg SPI_Direction_Rx: Selects Rx receive direction
- * @retval None
- */
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DIRECTION(SPI_Direction));
- if (SPI_Direction == SPI_Direction_Tx)
- {
- /* Set the Tx only mode */
- SPIx->CR1 |= SPI_Direction_Tx;
- }
- else
- {
- /* Set the Rx only mode */
- SPIx->CR1 &= SPI_Direction_Rx;
- }
-}
-
-/**
- * @brief Configures internally by software the NSS pin for the selected SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
- * This parameter can be one of the following values:
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
- * @retval None
- */
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
- {
- /* Set NSS pin internally by software */
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;
- }
- else
- {
- /* Reset NSS pin internally by software */
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the SS output for the selected SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param NewState: new state of the SPIx SS output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI SS output */
- SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
- }
- else
- {
- /* Disable the selected SPI SS output */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
- }
-}
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- *
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
- * are not taken into consideration and are configured by hardware
- * respectively to the TI mode requirements.
- *
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6
- * @param NewState: new state of the selected SPI TI communication mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TI mode for the selected SPI peripheral */
- SPIx->CR2 |= SPI_CR2_FRF;
- }
- else
- {
- /* Disable the TI mode for the selected SPI peripheral */
- SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF;
- }
-}
-
-/**
- * @brief Configures the full duplex mode for the I2Sx peripheral using its
- * extension I2Sxext according to the specified parameters in the
- * I2S_InitStruct.
- * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block.
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified I2S peripheral
- * extension.
- *
- * @note The structure pointed by I2S_InitStruct parameter should be the same
- * used for the master I2S peripheral. In this case, if the master is
- * configured as transmitter, the slave will be receiver and vice versa.
- * Or you can force a different mode by modifying the field I2S_Mode to the
- * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration.
- *
- * @note The I2S full duplex extension can be configured in slave mode only.
- *
- * @retval None
- */
-void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, tmp = 0;
-
- /* Check the I2S parameters */
- assert_param(IS_I2S_EXT_PERIPH(I2Sxext));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK;
- I2Sxext->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = I2Sxext->I2SCFGR;
-
- /* Get the mode to be configured for the extended I2S */
- if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
- {
- tmp = I2S_Mode_SlaveRx;
- }
- else
- {
- if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
- {
- tmp = I2S_Mode_SlaveTx;
- }
- }
-
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
- (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
- /* Write to SPIx I2SCFGR */
- I2Sxext->I2SCFGR = tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
-
- [..] This section provides a set of functions allowing to manage the SPI data
- transfers. In reception, data are received and then stored into an internal
- Rx buffer while. In transmission, data are first stored into an internal Tx
- buffer before being transmitted.
-
- [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
- function and returns the Rx buffered value. Whereas a write access to the SPI_DR
- can be done using SPI_I2S_SendData() function and stores the written data into
- Tx buffer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @retval The value of the received data.
- */
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
-
- /* Return the data in the DR register */
- return SPIx->DR;
-}
-
-/**
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
-
- /* Write in the DR register the data to be sent */
- SPIx->DR = Data;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group3 Hardware CRC Calculation functions
- * @brief Hardware CRC Calculation functions
- *
-@verbatim
- ===============================================================================
- ##### Hardware CRC Calculation functions #####
- ===============================================================================
-
- [..] This section provides a set of functions allowing to manage the SPI CRC hardware
- calculation
-
- [..] SPI communication using CRC is possible through the following procedure:
- (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
- Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function.
- (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
- (#) Enable the SPI using the SPI_Cmd() function
- (#) Before writing the last data to the TX buffer, set the CRCNext bit using the
- SPI_TransmitCRC() function to indicate that after transmission of the last
- data, the CRC should be transmitted.
- (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
- bit is reset. The CRC is also received and compared against the SPI_RXCRCR
- value.
- If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
- can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
-
- [..]
- (@) It is advised not to read the calculated CRC values during the communication.
-
- (@) When the SPI is in slave mode, be careful to enable CRC calculation only
- when the clock is stable, that is, when the clock is in the steady state.
- If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
- to the SCK slave input clock as soon as CRCEN is set, and this, whatever
- the value of the SPE bit.
-
- (@) With high bitrate frequencies, be careful when transmitting the CRC.
- As the number of used CPU cycles has to be as low as possible in the CRC
- transfer phase, it is forbidden to call software functions in the CRC
- transmission sequence to avoid errors in the last data and CRC reception.
- In fact, CRCNEXT bit has to be written before the end of the transmission/reception
- of the last data.
-
- (@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
- degradation of the SPI speed performance due to CPU accesses impacting the
- SPI bandwidth.
-
- (@) When the STM32F4xx is configured as slave and the NSS hardware mode is
- used, the NSS pin needs to be kept low between the data phase and the CRC
- phase.
-
- (@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
- calculation takes place even if a high level is applied on the NSS pin.
- This may happen for example in case of a multi-slave environment where the
- communication master addresses slaves alternately.
-
- (@) Between a slave de-selection (high level on NSS) and a new slave selection
- (low level on NSS), the CRC value should be cleared on both master and slave
- sides in order to resynchronize the master and slave for their respective
- CRC calculation.
-
- (@) To clear the CRC, follow the procedure below:
- (#@) Disable SPI using the SPI_Cmd() function
- (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
- (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
- (#@) Enable SPI using the SPI_Cmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the CRC value calculation of the transferred bytes.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param NewState: new state of the SPIx CRC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI CRC calculation */
- SPIx->CR1 |= SPI_CR1_CRCEN;
- }
- else
- {
- /* Disable the selected SPI CRC calculation */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
- }
-}
-
-/**
- * @brief Transmit the SPIx CRC value.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @retval None
- */
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Enable the selected SPI CRC transmission */
- SPIx->CR1 |= SPI_CR1_CRCNEXT;
-}
-
-/**
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_CRC: specifies the CRC register to be read.
- * This parameter can be one of the following values:
- * @arg SPI_CRC_Tx: Selects Tx CRC register
- * @arg SPI_CRC_Rx: Selects Rx CRC register
- * @retval The selected CRC register value..
- */
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
-{
- uint16_t crcreg = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC(SPI_CRC));
- if (SPI_CRC != SPI_CRC_Rx)
- {
- /* Get the Tx CRC register */
- crcreg = SPIx->TXCRCR;
- }
- else
- {
- /* Get the Rx CRC register */
- crcreg = SPIx->RXCRCR;
- }
- /* Return the selected CRC register */
- return crcreg;
-}
-
-/**
- * @brief Returns the CRC Polynomial register value for the specified SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @retval The CRC Polynomial register value.
- */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the CRC polynomial register */
- return SPIx->CRCPR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group4 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
- * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
- * @param NewState: new state of the selected SPI DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI DMA requests */
- SPIx->CR2 |= SPI_I2S_DMAReq;
- }
- else
- {
- /* Disable the selected SPI DMA requests */
- SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides a set of functions allowing to configure the SPI Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- *** Polling Mode ***
- ====================
-[..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
- (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
- (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
- (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
- (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur
- (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur
- (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
- (#) I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs.
- (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
- (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
-
- (@) Do not use the BSY flag to handle each data transmission or reception. It is
- better to use the TXE and RXNE flags instead.
-
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
- (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources
- and 7 pending bits:
- (+) Pending Bits:
- (##) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
- (##) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
- (##) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only)
- (##) SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only)
- (##) SPI_I2S_IT_OVR : to indicate if an Overrun error occur
- (##) I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only).
- (##) I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only).
-
- (+) Interrupt Source:
- (##) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
- interrupt.
- (##) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
- empty interrupt.
- (##) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
-
- [..] In this Mode it is advised to use the following functions:
- (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
- (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
- (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
- *** DMA Mode ***
- ================
- [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
- (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request
- (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request
-
- [..] In this Mode it is advised to use the following function:
- (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState
- NewState);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified SPI/I2S interrupts.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
- * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
- * @arg SPI_I2S_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified SPI interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
-{
- uint16_t itpos = 0, itmask = 0 ;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
-
- /* Get the SPI IT index */
- itpos = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = (uint16_t)1 << (uint16_t)itpos;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI interrupt */
- SPIx->CR2 |= itmask;
- }
- else
- {
- /* Disable the selected SPI interrupt */
- SPIx->CR2 &= (uint16_t)~itmask;
- }
-}
-
-/**
- * @brief Checks whether the specified SPIx/I2Sx flag is set or not.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_FLAG: specifies the SPI flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
- * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
- * @arg SPI_I2S_FLAG_BSY: Busy flag.
- * @arg SPI_I2S_FLAG_OVR: Overrun flag.
- * @arg SPI_FLAG_MODF: Mode Fault flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- * @arg SPI_I2S_FLAG_TIFRFE: Format Error.
- * @arg I2S_FLAG_UDR: Underrun Error flag.
- * @arg I2S_FLAG_CHSIDE: Channel Side flag.
- * @retval The new state of SPI_I2S_FLAG (SET or RESET).
- */
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
-
- /* Check the status of the specified SPI flag */
- if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
- {
- /* SPI_I2S_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) flag.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
- * This function clears only CRCERR flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- *
- * @note OVR (OverRun error) flag is cleared by software sequence: a read
- * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
- * @note UDR (UnderRun error) flag is cleared by a read operation to
- * SPI_SR register (SPI_I2S_GetFlagStatus()).
- * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
- * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
- *
- * @retval None
- */
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
-
- /* Clear the selected SPI CRC Error (CRCERR) flag */
- SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
- * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
- * @arg SPI_I2S_IT_OVR: Overrun interrupt.
- * @arg SPI_IT_MODF: Mode Fault interrupt.
- * @arg SPI_IT_CRCERR: CRC Error interrupt.
- * @arg I2S_IT_UDR: Underrun interrupt.
- * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt.
- * @retval The new state of SPI_I2S_IT (SET or RESET).
- */
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
-
- /* Get the SPI_I2S_IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Get the SPI_I2S_IT IT mask */
- itmask = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = 0x01 << itmask;
-
- /* Get the SPI_I2S_IT enable bit status */
- enablestatus = (SPIx->CR2 & itmask) ;
-
- /* Check the status of the specified SPI interrupt */
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
- {
- /* SPI_I2S_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_IT is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
- * This function clears only CRCERR interrupt pending bit.
- * @arg SPI_IT_CRCERR: CRC Error interrupt.
- *
- * @note OVR (OverRun Error) interrupt pending bit is cleared by software
- * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
- * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
- * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read
- * operation to SPI_SR register (SPI_I2S_GetITStatus()).
- * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
- * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
- * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
- * the SPI).
- * @retval None
- */
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- uint16_t itpos = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
-
- /* Get the SPI_I2S IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
- SPIx->SR = (uint16_t)~itpos;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
deleted file mode 100644
index 160181c5..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_syscfg.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the SYSCFG peripheral.
- *
- @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..] This driver provides functions for:
-
- (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
-
- (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
-
- (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
-
- -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
- using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_syscfg.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SYSCFG
- * @brief SYSCFG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
-
-/* --- PMC Register ---*/
-/* Alias word address of MII_RMII_SEL bit */
-#define PMC_OFFSET (SYSCFG_OFFSET + 0x04)
-#define MII_RMII_SEL_BitNumber ((uint8_t)0x17)
-#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
-
-/* --- CMPCR Register ---*/
-/* Alias word address of CMP_PD bit */
-#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20)
-#define CMP_PD_BitNumber ((uint8_t)0x00)
-#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SYSCFG_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the Alternate Functions (remap and EXTI configuration)
- * registers to their default reset values.
- * @param None
- * @retval None
- */
-void SYSCFG_DeInit(void)
-{
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
-}
-
-/**
- * @brief Changes the mapping of the specified pin.
- * @param SYSCFG_Memory: selects the memory remapping.
- * This parameter can be one of the following values:
- * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
- * @retval None
- */
-void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
-
- SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
-}
-
-/**
- * @brief Selects the GPIO pin used as EXTI Line.
- * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
- * EXTI lines where x can be (A..I) for STM32F40xx/STM32F41xx
- * and STM32F427x/STM32F437x devices.
- *
- * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
- * This parameter can be EXTI_PinSourcex where x can be (0..15, except
- * for EXTI_PortSourceGPIOI x can be (0..11) for STM32F40xx/STM32F41xx
- * and STM32F427x/STM32F437x devices.
- *
- * @retval None
- */
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
-{
- uint32_t tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
- assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
-
- tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
-}
-
-/**
- * @brief Selects the ETHERNET media interface
- * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode.
- * This parameter can be one of the following values:
- * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected
- * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected
- * @retval None
- */
-void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface)
-{
- assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface));
- /* Configure MII_RMII selection bit */
- *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface;
-}
-
-/**
- * @brief Enables or disables the I/O Compensation Cell.
- * @note The I/O compensation cell can be used only when the device supply
- * voltage ranges from 2.4 to 3.6 V.
- * @param NewState: new state of the I/O Compensation Cell.
- * This parameter can be one of the following values:
- * @arg ENABLE: I/O compensation cell enabled
- * @arg DISABLE: I/O compensation cell power-down mode
- * @retval None
- */
-void SYSCFG_CompensationCellCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Checks whether the I/O Compensation Cell ready flag is set or not.
- * @param None
- * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
- */
-FlagStatus SYSCFG_GetCompensationCellStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
deleted file mode 100644
index 1616a625..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
+++ /dev/null
@@ -1,3365 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_tim.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the TIM peripheral:
- * + TimeBase management
- * + Output Compare management
- * + Input Capture management
- * + Advanced-control timers (TIM1 and TIM8) specific features
- * + Interrupts, DMA and flags management
- * + Clocks management
- * + Synchronization management
- * + Specific interface management
- * + Specific remapping management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- This driver provides functions to configure and program the TIM
- of all STM32F4xx devices.
- These functions are split in 9 groups:
-
- (#) TIM TimeBase management: this group includes all needed functions
- to configure the TM Timebase unit:
- (++) Set/Get Prescaler
- (++) Set/Get Autoreload
- (++) Counter modes configuration
- (++) Set Clock division
- (++) Select the One Pulse mode
- (++) Update Request Configuration
- (++) Update Disable Configuration
- (++) Auto-Preload Configuration
- (++) Enable/Disable the counter
-
- (#) TIM Output Compare management: this group includes all needed
- functions to configure the Capture/Compare unit used in Output
- compare mode:
- (++) Configure each channel, independently, in Output Compare mode
- (++) Select the output compare modes
- (++) Select the Polarities of each channel
- (++) Set/Get the Capture/Compare register values
- (++) Select the Output Compare Fast mode
- (++) Select the Output Compare Forced mode
- (++) Output Compare-Preload Configuration
- (++) Clear Output Compare Reference
- (++) Select the OCREF Clear signal
- (++) Enable/Disable the Capture/Compare Channels
-
- (#) TIM Input Capture management: this group includes all needed
- functions to configure the Capture/Compare unit used in
- Input Capture mode:
- (++) Configure each channel in input capture mode
- (++) Configure Channel1/2 in PWM Input mode
- (++) Set the Input Capture Prescaler
- (++) Get the Capture/Compare values
-
- (#) Advanced-control timers (TIM1 and TIM8) specific features
- (++) Configures the Break input, dead time, Lock level, the OSSI,
- the OSSR State and the AOE(automatic output enable)
- (++) Enable/Disable the TIM peripheral Main Outputs
- (++) Select the Commutation event
- (++) Set/Reset the Capture Compare Preload Control bit
-
- (#) TIM interrupts, DMA and flags management
- (++) Enable/Disable interrupt sources
- (++) Get flags status
- (++) Clear flags/ Pending bits
- (++) Enable/Disable DMA requests
- (++) Configure DMA burst mode
- (++) Select CaptureCompare DMA request
-
- (#) TIM clocks management: this group includes all needed functions
- to configure the clock controller unit:
- (++) Select internal/External clock
- (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
-
- (#) TIM synchronization management: this group includes all needed
- functions to configure the Synchronization unit:
- (++) Select Input Trigger
- (++) Select Output Trigger
- (++) Select Master Slave Mode
- (++) ETR Configuration when used as external trigger
-
- (#) TIM specific interface management, this group includes all
- needed functions to use the specific TIM interface:
- (++) Encoder Interface Configuration
- (++) Select Hall Sensor
-
- (#) TIM specific remapping management includes the Remapping
- configuration of specific timers
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_tim.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup TIM
- * @brief TIM driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define SMCR_ETR_MASK ((uint16_t)0x00FF)
-#define CCMR_OFFSET ((uint16_t)0x0018)
-#define CCER_CCE_SET ((uint16_t)0x0001)
-#define CCER_CCNE_SET ((uint16_t)0x0004)
-#define CCMR_OC13M_MASK ((uint16_t)0xFF8F)
-#define CCMR_OC24M_MASK ((uint16_t)0x8FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIM_Private_Functions
- * @{
- */
-
-/** @defgroup TIM_Group1 TimeBase management functions
- * @brief TimeBase management functions
- *
-@verbatim
- ===============================================================================
- ##### TimeBase management functions #####
- ===============================================================================
-
-
- ##### TIM Driver: how to use it in Timing(Time base) Mode #####
- ===============================================================================
- [..]
- To use the Timer in Timing(Time base) mode, the following steps are mandatory:
-
- (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
-
- (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
-
- (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit
- with the corresponding configuration
-
- (#) Enable the NVIC if you need to generate the update interrupt.
-
- (#) Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update)
-
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-
- -@- All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @retval None
-
- */
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- if (TIMx == TIM1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
- }
- else if (TIMx == TIM2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
- }
- else if (TIMx == TIM3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
- }
- else if (TIMx == TIM4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
- }
- else if (TIMx == TIM5)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
- }
- else if (TIMx == TIM6)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
- }
- else if (TIMx == TIM7)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
- }
- else if (TIMx == TIM8)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
- }
- else if (TIMx == TIM9)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
- }
- else if (TIMx == TIM10)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
- }
- else if (TIMx == TIM11)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
- }
- else if (TIMx == TIM12)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
- }
- else if (TIMx == TIM13)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
- }
- else
- {
- if (TIMx == TIM14)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the TIMx Time Base Unit peripheral according to
- * the specified parameters in the TIM_TimeBaseInitStruct.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
- tmpcr1 = TIMx->CR1;
-
- if((TIMx == TIM1) || (TIMx == TIM8)||
- (TIMx == TIM2) || (TIMx == TIM3)||
- (TIMx == TIM4) || (TIMx == TIM5))
- {
- /* Select the Counter Mode */
- tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
- }
-
- if((TIMx != TIM6) && (TIMx != TIM7))
- {
- /* Set the clock division */
- tmpcr1 &= (uint16_t)(~TIM_CR1_CKD);
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
- }
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-
- if ((TIMx == TIM1) || (TIMx == TIM8))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediatly */
- TIMx->EGR = TIM_PSCReloadMode_Immediate;
-}
-
-/**
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
- * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- /* Set the default configuration */
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
-}
-
-/**
- * @brief Configures the TIMx Prescaler.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param Prescaler: specifies the Prescaler Register value
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
- * This parameter can be one of the following values:
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
- * @retval None
- */
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
- /* Set the Prescaler value */
- TIMx->PSC = Prescaler;
- /* Set or reset the UG Bit */
- TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/**
- * @brief Specifies the TIMx Counter Mode to be used.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_CounterMode: specifies the Counter Mode to be used
- * This parameter can be one of the following values:
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
- * @retval None
- */
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
-
- tmpcr1 = TIMx->CR1;
-
- /* Reset the CMS and DIR Bits */
- tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
-
- /* Set the Counter Mode */
- tmpcr1 |= TIM_CounterMode;
-
- /* Write to TIMx CR1 register */
- TIMx->CR1 = tmpcr1;
-}
-
-/**
- * @brief Sets the TIMx Counter Register value
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param Counter: specifies the Counter register new value.
- * @retval None
- */
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Counter Register value */
- TIMx->CNT = Counter;
-}
-
-/**
- * @brief Sets the TIMx Autoreload Register value
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param Autoreload: specifies the Autoreload register new value.
- * @retval None
- */
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Autoreload Register value */
- TIMx->ARR = Autoreload;
-}
-
-/**
- * @brief Gets the TIMx Counter value.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @retval Counter Register value
- */
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Counter Register value */
- return TIMx->CNT;
-}
-
-/**
- * @brief Gets the TIMx Prescaler value.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @retval Prescaler Register value.
- */
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Prescaler Register value */
- return TIMx->PSC;
-}
-
-/**
- * @brief Enables or Disables the TIMx Update event.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param NewState: new state of the TIMx UDIS bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the Update Disable Bit */
- TIMx->CR1 |= TIM_CR1_UDIS;
- }
- else
- {
- /* Reset the Update Disable Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
- }
-}
-
-/**
- * @brief Configures the TIMx Update Request Interrupt source.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_UpdateSource: specifies the Update source.
- * This parameter can be one of the following values:
- * @arg TIM_UpdateSource_Global: Source of update is the counter
- * overflow/underflow or the setting of UG bit, or an update
- * generation through the slave mode controller.
- * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.
- * @retval None
- */
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
-
- if (TIM_UpdateSource != TIM_UpdateSource_Global)
- {
- /* Set the URS Bit */
- TIMx->CR1 |= TIM_CR1_URS;
- }
- else
- {
- /* Reset the URS Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
- }
-}
-
-/**
- * @brief Enables or disables TIMx peripheral Preload register on ARR.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param NewState: new state of the TIMx peripheral Preload register
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ARR Preload Bit */
- TIMx->CR1 |= TIM_CR1_ARPE;
- }
- else
- {
- /* Reset the ARR Preload Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
- }
-}
-
-/**
- * @brief Selects the TIMx's One Pulse Mode.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_OPMode: specifies the OPM Mode to be used.
- * This parameter can be one of the following values:
- * @arg TIM_OPMode_Single
- * @arg TIM_OPMode_Repetitive
- * @retval None
- */
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
-
- /* Reset the OPM Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
-
- /* Configure the OPM Mode */
- TIMx->CR1 |= TIM_OPMode;
-}
-
-/**
- * @brief Sets the TIMx Clock Division value.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_CKD: specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
- * @retval None
- */
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));
-
- /* Reset the CKD Bits */
- TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
-
- /* Set the CKD value */
- TIMx->CR1 |= TIM_CKD;
-}
-
-/**
- * @brief Enables or disables the specified TIM peripheral.
- * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
- * @param NewState: new state of the TIMx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Counter */
- TIMx->CR1 |= TIM_CR1_CEN;
- }
- else
- {
- /* Disable the TIM Counter */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group2 Output Compare management functions
- * @brief Output Compare management functions
- *
-@verbatim
- ===============================================================================
- ##### Output Compare management functions #####
- ===============================================================================
-
-
- ##### TIM Driver: how to use it in Output Compare Mode #####
- ===============================================================================
- [..]
- To use the Timer in Output Compare mode, the following steps are mandatory:
-
- (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
- function
-
- (#) Configure the TIM pins by configuring the corresponding GPIO pins
-
- (#) Configure the Time base unit as described in the first part of this driver,
- (++) if needed, else the Timer will run with the default configuration:
- Autoreload value = 0xFFFF
- (++) Prescaler value = 0x0000
- (++) Counter mode = Up counting
- (++) Clock Division = TIM_CKD_DIV1
-
- (#) Fill the TIM_OCInitStruct with the desired parameters including:
- (++) The TIM Output Compare mode: TIM_OCMode
- (++) TIM Output State: TIM_OutputState
- (++) TIM Pulse value: TIM_Pulse
- (++) TIM Output Compare Polarity : TIM_OCPolarity
-
- (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired
- channel with the corresponding configuration
-
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-
- -@- All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
- -@- In case of PWM mode, this function is mandatory:
- TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE);
-
- -@- If the corresponding interrupt or DMA request are needed, the user should:
- (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
- (+@) Enable the corresponding interrupt (or DMA request) using the function
- TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIMx Channel1 according to the specified parameters in
- * the TIM_OCInitStruct.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M;
- tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S;
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC1P;
- /* Set the Output Compare Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-
- /* Set the Output State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
- /* Set the Output N Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
- /* Reset the Output N State */
- tmpccer &= (uint16_t)~TIM_CCER_CC1NE;
-
- /* Set the Output N State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS1;
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N;
- /* Set the Output Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel2 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M;
- tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC2P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
- /* Reset the Output N State */
- tmpccer &= (uint16_t)~TIM_CCER_CC2NE;
-
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS2;
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N;
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel3 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M;
- tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S;
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC3P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
- /* Reset the Output N State */
- tmpccer &= (uint16_t)~TIM_CCER_CC3NE;
-
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS3;
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N;
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel4 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M;
- tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC4P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
- /* Reset the Output Compare IDLE State */
- tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4;
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Fills each TIM_OCInitStruct member with its default value.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- /* Set the default configuration */
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
- TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
- TIM_OCInitStruct->TIM_Pulse = 0x00000000;
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
- TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-/**
- * @brief Selects the TIM Output Compare Mode.
- * @note This function disables the selected channel before changing the Output
- * Compare Mode. If needed, user has to enable this channel using
- * TIM_CCxCmd() and TIM_CCxNCmd() functions.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.
- * This parameter can be one of the following values:
- * @arg TIM_OCMode_Timing
- * @arg TIM_OCMode_Active
- * @arg TIM_OCMode_Toggle
- * @arg TIM_OCMode_PWM1
- * @arg TIM_OCMode_PWM2
- * @arg TIM_ForcedAction_Active
- * @arg TIM_ForcedAction_InActive
- * @retval None
- */
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
-{
- uint32_t tmp = 0;
- uint16_t tmp1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_OCM(TIM_OCMode));
-
- tmp = (uint32_t) TIMx;
- tmp += CCMR_OFFSET;
-
- tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
-
- /* Disable the Channel: Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t) ~tmp1;
-
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
- {
- tmp += (TIM_Channel>>1);
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= TIM_OCMode;
- }
- else
- {
- tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
- }
-}
-
-/**
- * @brief Sets the TIMx Capture Compare1 Register value
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param Compare1: specifies the Capture Compare1 register new value.
- * @retval None
- */
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-
- /* Set the Capture Compare1 Register value */
- TIMx->CCR1 = Compare1;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare2 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param Compare2: specifies the Capture Compare2 register new value.
- * @retval None
- */
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Set the Capture Compare2 Register value */
- TIMx->CCR2 = Compare2;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare3 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare3: specifies the Capture Compare3 register new value.
- * @retval None
- */
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare3 Register value */
- TIMx->CCR3 = Compare3;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare4 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare4: specifies the Capture Compare4 register new value.
- * @retval None
- */
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare4 Register value */
- TIMx->CCR4 = Compare4;
-}
-
-/**
- * @brief Forces the TIMx output 1 waveform to active or inactive level.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
- * @retval None
- */
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1M Bits */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M;
-
- /* Configure The Forced output Mode */
- tmpccmr1 |= TIM_ForcedAction;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 2 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
- * @retval None
- */
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2M Bits */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M;
-
- /* Configure The Forced output Mode */
- tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 3 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
- * @retval None
- */
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC1M Bits */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M;
-
- /* Configure The Forced output Mode */
- tmpccmr2 |= TIM_ForcedAction;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Forces the TIMx output 4 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
- * @retval None
- */
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC2M Bits */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M;
-
- /* Configure The Forced output Mode */
- tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1PE Bit */
- tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= TIM_OCPreload;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2PE Bit */
- tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3PE Bit */
- tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= TIM_OCPreload;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4PE Bit */
- tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 1 Fast feature.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1FE Bit */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= TIM_OCFast;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 2 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2FE Bit */
- tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 3 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3FE Bit */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= TIM_OCFast;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 4 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4FE Bit */
- tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF1 signal on an external event
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1CE Bit */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= TIM_OCClear;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF2 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2CE Bit */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF3 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3CE Bit */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= TIM_OCClear;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF4 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4CE Bit */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx channel 1 polarity.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC1 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC1P Bit */
- tmpccer &= (uint16_t)(~TIM_CCER_CC1P);
- tmpccer |= TIM_OCPolarity;
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 1N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC1N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC1NP Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
- tmpccer |= TIM_OCNPolarity;
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 2 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCPolarity: specifies the OC2 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC2P Bit */
- tmpccer &= (uint16_t)(~TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 2N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC2N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC2NP Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 3 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC3 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC3P Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC3P;
- tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 3N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC3N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC3NP Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 4 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC4 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC4P Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC4P;
- tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCX(TIM_CCx));
-
- tmp = CCER_CCE_SET << TIM_Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t)~ tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
- * @retval None
- */
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCXN(TIM_CCxN));
-
- tmp = CCER_CCNE_SET << TIM_Channel;
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= (uint16_t) ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group3 Input Capture management functions
- * @brief Input Capture management functions
- *
-@verbatim
- ===============================================================================
- ##### Input Capture management functions #####
- ===============================================================================
-
- ##### TIM Driver: how to use it in Input Capture Mode #####
- ===============================================================================
- [..]
- To use the Timer in Input Capture mode, the following steps are mandatory:
-
- (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
- function
-
- (#) Configure the TIM pins by configuring the corresponding GPIO pins
-
- (#) Configure the Time base unit as described in the first part of this driver,
- if needed, else the Timer will run with the default configuration:
- (++) Autoreload value = 0xFFFF
- (++) Prescaler value = 0x0000
- (++) Counter mode = Up counting
- (++) Clock Division = TIM_CKD_DIV1
-
- (#) Fill the TIM_ICInitStruct with the desired parameters including:
- (++) TIM Channel: TIM_Channel
- (++) TIM Input Capture polarity: TIM_ICPolarity
- (++) TIM Input Capture selection: TIM_ICSelection
- (++) TIM Input Capture Prescaler: TIM_ICPrescaler
- (++) TIM Input CApture filter value: TIM_ICFilter
-
- (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel
- with the corresponding configuration and to measure only frequency
- or duty cycle of the input signal, or, Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct)
- to configure the desired channels with the corresponding configuration
- and to measure the frequency and the duty cycle of the input signal
-
- (#) Enable the NVIC or the DMA to read the measured frequency.
-
- (#) Enable the corresponding interrupt (or DMA request) to read the Captured
- value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx)
- (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
-
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-
- (#) Use TIM_GetCapturex(TIMx); to read the captured value.
-
- -@- All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIM peripheral according to the specified parameters
- * in the TIM_ICInitStruct.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
-
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
- {
- /* TI2 Configuration */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
- {
- /* TI3 Configuration */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI4 Configuration */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Fills each TIM_ICInitStruct member with its default value.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
- TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/**
- * @brief Configures the TIM peripheral according to the specified parameters
- * in the TIM_ICInitStruct to measure an external PWM signal.
- * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Select the Opposite Input Polarity */
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
- {
- icoppositepolarity = TIM_ICPolarity_Falling;
- }
- else
- {
- icoppositepolarity = TIM_ICPolarity_Rising;
- }
- /* Select the Opposite Input */
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
- {
- icoppositeselection = TIM_ICSelection_IndirectTI;
- }
- else
- {
- icoppositeselection = TIM_ICSelection_DirectTI;
- }
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI2 Configuration */
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI1 Configuration */
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Gets the TIMx Input Capture 1 value.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @retval Capture Compare 1 Register value.
- */
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-
- /* Get the Capture 1 Register value */
- return TIMx->CCR1;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 2 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @retval Capture Compare 2 Register value.
- */
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Get the Capture 2 Register value */
- return TIMx->CCR2;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 3 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @retval Capture Compare 3 Register value.
- */
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 3 Register value */
- return TIMx->CCR3;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 4 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @retval Capture Compare 4 Register value.
- */
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 4 Register value */
- return TIMx->CCR4;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 1 prescaler.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC1PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC;
-
- /* Set the IC1PSC value */
- TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 2 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC2PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC;
-
- /* Set the IC2PSC value */
- TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @brief Sets the TIMx Input Capture 3 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC3PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
-
- /* Set the IC3PSC value */
- TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 4 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC4PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
-
- /* Set the IC4PSC value */
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
- * @brief Advanced-control timers (TIM1 and TIM8) specific features
- *
-@verbatim
- ===============================================================================
- ##### Advanced-control timers (TIM1 and TIM8) specific features #####
- ===============================================================================
-
- ##### TIM Driver: how to use the Break feature #####
- ===============================================================================
- [..]
- After configuring the Timer channel(s) in the appropriate Output Compare mode:
-
- (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
- Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
- AOE(automatic output enable).
-
- (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
-
- (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
-
- (#) Once the break even occurs, the Timer's output signals are put in reset
- state or in a known state (according to the configuration made in
- TIM_BDTRConfig() function).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param TIMx: where x can be 1 or 8 to select the TIM
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @retval None
- */
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
- assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
- assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
- assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
- assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
- TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
- TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
- TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
- TIM_BDTRInitStruct->TIM_AutomaticOutput;
-}
-
-/**
- * @brief Fills each TIM_BDTRInitStruct member with its default value.
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
- TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
- TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
- TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
- TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
- TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
- TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-/**
- * @brief Enables or disables the TIM peripheral Main Outputs.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
- * @param NewState: new state of the TIM peripheral Main Outputs.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Main Output */
- TIMx->BDTR |= TIM_BDTR_MOE;
- }
- else
- {
- /* Disable the TIM Main Output */
- TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
- }
-}
-
-/**
- * @brief Selects the TIM peripheral Commutation event.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
- * @param NewState: new state of the Commutation event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the COM Bit */
- TIMx->CR2 |= TIM_CR2_CCUS;
- }
- else
- {
- /* Reset the COM Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
- }
-}
-
-/**
- * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
- * @param NewState: new state of the Capture Compare Preload Control bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the CCPC Bit */
- TIMx->CR2 |= TIM_CR2_CCPC;
- }
- else
- {
- /* Reset the CCPC Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
- * @brief Interrupts, DMA and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts, DMA and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified TIM interrupts.
- * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
- * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
- * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
- * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
- * be used: TIM_IT_Update or TIM_IT_CC1
- * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8
- *
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- TIMx->DIER |= TIM_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- TIMx->DIER &= (uint16_t)~TIM_IT;
- }
-}
-
-/**
- * @brief Configures the TIMx event to be generate by software.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_EventSource: specifies the event source.
- * This parameter can be one or more of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_COM: Timer COM event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @arg TIM_EventSource_Break: Timer Break event source
- *
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
-
- /* Set the event sources */
- TIMx->EGR = TIM_EventSource;
-}
-
-/**
- * @brief Checks whether the specified TIM flag is set or not.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
- *
- * @retval The new state of TIM_FLAG (SET or RESET).
- */
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
-
-
- if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's pending flags.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Clear the flags */
- TIMx->SR = (uint16_t)~TIM_FLAG;
-}
-
-/**
- * @brief Checks whether the TIM interrupt has occurred or not.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_IT: specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
- *
- * @retval The new state of the TIM_IT(SET or RESET).
- */
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itstatus = 0x0, itenable = 0x0;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_IT(TIM_IT));
-
- itstatus = TIMx->SR & TIM_IT;
-
- itenable = TIMx->DIER & TIM_IT;
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's interrupt pending bits.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_IT: specifies the pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM1 update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Clear the IT pending Bit */
- TIMx->SR = (uint16_t)~TIM_IT;
-}
-
-/**
- * @brief Configures the TIMx's DMA interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_DMABase: DMA Base address.
- * This parameter can be one of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM1_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_RCR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_BDTR
- * @arg TIM_DMABase_DCR
- * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
- * @retval None
- */
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
-
- /* Set the DMA Base and the DMA Burst Length */
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/**
- * @brief Enables or disables the TIMx's DMA Requests.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
- * @param TIM_DMASource: specifies the DMA Request sources.
- * This parameter can be any combination of the following values:
- * @arg TIM_DMA_Update: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA sources */
- TIMx->DIER |= TIM_DMASource;
- }
- else
- {
- /* Disable the DMA sources */
- TIMx->DIER &= (uint16_t)~TIM_DMASource;
- }
-}
-
-/**
- * @brief Selects the TIMx peripheral Capture Compare DMA source.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param NewState: new state of the Capture Compare DMA source
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the CCDS Bit */
- TIMx->CR2 |= TIM_CR2_CCDS;
- }
- else
- {
- /* Reset the CCDS Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group6 Clocks management functions
- * @brief Clocks management functions
- *
-@verbatim
- ===============================================================================
- ##### Clocks management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx internal Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @retval None
- */
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
-}
-
-/**
- * @brief Configures the TIMx Internal Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_InputTriggerSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @retval None
- */
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Select the Internal Trigger */
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
-
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the TIMx Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
- * to select the TIM peripheral.
- * @param TIM_TIxExternalCLKSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
- * @param TIM_ICPolarity: specifies the TIx Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param ICFilter: specifies the filter value.
- * This parameter must be a value between 0x0 and 0xF.
- * @retval None
- */
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
- assert_param(IS_TIM_IC_FILTER(ICFilter));
-
- /* Configure the Timer Input Clock Source */
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
- {
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- else
- {
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- /* Select the Trigger source */
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the External clock Mode1
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the SMS Bits */
- tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
-
- /* Select the External clock mode1 */
- tmpsmcr |= TIM_SlaveMode_External1;
-
- /* Select the Trigger selection : ETRF */
- tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
- tmpsmcr |= TIM_TS_ETRF;
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the External clock Mode2
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Enable the External clock mode2 */
- TIMx->SMCR |= TIM_SMCR_ECE;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group7 Synchronization management functions
- * @brief Synchronization management functions
- *
-@verbatim
- ===============================================================================
- ##### Synchronization management functions #####
- ===============================================================================
-
- ##### TIM Driver: how to use it in synchronization Mode #####
- ===============================================================================
- [..]
-
- *** Case of two/several Timers ***
- ==================================
- [..]
- (#) Configure the Master Timers using the following functions:
- (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
- (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
- (#) Configure the Slave Timers using the following functions:
- (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
- (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-
- *** Case of Timers and external trigger(ETR pin) ***
- ====================================================
- [..]
- (#) Configure the External trigger using this function:
- (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
- (#) Configure the Slave Timers using the following functions:
- (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
- (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
- * to select the TIM peripheral.
- * @param TIM_InputTriggerSource: The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the TS Bits */
- tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
-
- /* Set the Input Trigger source */
- tmpsmcr |= TIM_InputTriggerSource;
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Selects the TIMx Trigger Output Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
- *
- * @param TIM_TRGOSource: specifies the Trigger Output source.
- * This parameter can be one of the following values:
- *
- * - For all TIMx
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
- *
- * - For all TIMx except TIM6 and TIM7
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
- * is to be set, as soon as a capture or compare match occurs(TRGO)
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
- *
- * @retval None
- */
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
-
- /* Reset the MMS Bits */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
- /* Select the TRGO source */
- TIMx->CR2 |= TIM_TRGOSource;
-}
-
-/**
- * @brief Selects the TIMx Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize
- * the counter and triggers an update of the registers
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
- * @retval None
- */
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
-
- /* Reset the SMS Bits */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
-
- /* Select the Slave Mode */
- TIMx->SMCR |= TIM_SlaveMode;
-}
-
-/**
- * @brief Sets or Resets the TIMx Master/Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
- * and its slaves (through TRGO)
- * @arg TIM_MasterSlaveMode_Disable: No action
- * @retval None
- */
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
-
- /* Reset the MSM Bit */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
-
- /* Set or Reset the MSM Bit */
- TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the ETR Bits */
- tmpsmcr &= SMCR_ETR_MASK;
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group8 Specific interface management functions
- * @brief Specific interface management functions
- *
-@verbatim
- ===============================================================================
- ##### Specific interface management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx Encoder Interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
- * This parameter can be one of the following values:
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
- * on the level of the other input.
- * @param TIM_IC1Polarity: specifies the IC1 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @param TIM_IC2Polarity: specifies the IC2 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @retval None
- */
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
-{
- uint16_t tmpsmcr = 0;
- uint16_t tmpccmr1 = 0;
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
- tmpsmcr |= TIM_EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIMx's Hall sensor interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param NewState: new state of the TIMx Hall sensor interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the TI1S Bit */
- TIMx->CR2 |= TIM_CR2_TI1S;
- }
- else
- {
- /* Reset the TI1S Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group9 Specific remapping management function
- * @brief Specific remapping management function
- *
-@verbatim
- ===============================================================================
- ##### Specific remapping management function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
- * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral.
- * @param TIM_Remap: specifies the TIM input remapping source.
- * This parameter can be one of the following values:
- * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
- * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output.
- * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
- * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
- * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
- * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
- * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
- * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
- * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
- * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
- * (HSE divided by a programmable prescaler)
- * @retval None
- */
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_REMAP(TIM_Remap));
-
- /* Set the Timer remapping configuration */
- TIMx->OR = TIM_Remap;
-}
-/**
- * @}
- */
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
- * to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input and set the filter */
- tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
- tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 4);
-
- /* Select the Input and set the filter */
- tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
- tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
- tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 8);
-
- /* Select the Input and set the filter */
- tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 12);
-
- /* Select the Input and set the filter */
- tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
-
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer ;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
deleted file mode 100644
index 40f2391e..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
+++ /dev/null
@@ -1,1486 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_usart.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Universal synchronous asynchronous receiver
- * transmitter (USART):
- * + Initialization and Configuration
- * + Data transfers
- * + Multi-Processor Communication
- * + LIN mode
- * + Half-duplex mode
- * + Smartcard mode
- * + IrDA mode
- * + DMA transfers management
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable peripheral clock using the following functions
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3,
- UART4 or UART5.
-
- (#) According to the USART mode, enable the GPIO clocks using
- RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS,
- or/and SCLK).
-
- (#) Peripheral's alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function
-
- (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) using the USART_Init()
- function.
-
- (#) For synchronous mode, enable the clock and program the polarity,
- phase and last bit using the USART_ClockInit() function.
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- USART_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function
- (++) Active the needed channel Request using USART_DMACmd() function
-
- (#) Enable the USART using the USART_Cmd() function.
-
- (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
-
- -@- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
- for more details
-
- [..]
- In order to reach higher communication baudrates, it is possible to
- enable the oversampling by 8 mode using the function USART_OverSampling8Cmd().
- This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd())
- and before calling the function USART_Init().
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_usart.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup USART
- * @brief USART driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */
-#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \
- USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE))
-
-/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */
-#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
- USART_CR2_CPHA | USART_CR2_LBCL))
-
-/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */
-#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-
-/*!< USART Interrupts mask */
-#define IT_MASK ((uint16_t)0x001F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup USART_Private_Functions
- * @{
- */
-
-/** @defgroup USART_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible USART frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
- (++) Hardware flow control
- (++) Receiver/transmitter modes
-
- [..]
- The USART_Init() function follows the USART asynchronous configuration
- procedure (details for the procedure are available in reference manual (RM0090)).
-
- (+) For the synchronous mode in addition to the asynchronous mode parameters these
- parameters should be also configured:
- (++) USART Clock Enabled
- (++) USART polarity
- (++) USART phase
- (++) USART LastBit
-
- [..]
- These parameters can be configured using the USART_ClockInit() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @retval None
- */
-void USART_DeInit(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- if (USARTx == USART1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
- }
- else if (USARTx == USART2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
- }
- else if (USARTx == USART3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
- }
- else if (USARTx == UART4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
- }
- else if (USARTx == UART5)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
- }
- else if (USARTx == USART6)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
- }
- else if (USARTx == UART7)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE);
- }
- else
- {
- if (USARTx == UART8)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the USARTx peripheral according to the specified
- * parameters in the USART_InitStruct .
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains
- * the configuration information for the specified USART peripheral.
- * @retval None
- */
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
- uint32_t tmpreg = 0x00, apbclock = 0x00;
- uint32_t integerdivider = 0x00;
- uint32_t fractionaldivider = 0x00;
- RCC_ClocksTypeDef RCC_ClocksStatus;
-
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
-
- /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
- if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
-
- /* Clear STOP[13:12] bits */
- tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit :
- Set STOP[13:12] bits according to USART_StopBits value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
-
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = USARTx->CR1;
-
- /* Clear M, PCE, PS, TE and RE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
-
- /* Configure the USART Word Length, Parity and mode:
- Set the M bits according to USART_WordLength value
- Set PCE and PS bits according to USART_Parity value
- Set TE and RE bits according to USART_Mode value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
- USART_InitStruct->USART_Mode;
-
- /* Write to USART CR1 */
- USARTx->CR1 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR3 Configuration -----------------------*/
- tmpreg = USARTx->CR3;
-
- /* Clear CTSE and RTSE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
-
- /* Configure the USART HFC :
- Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
-
- /* Write to USART CR3 */
- USARTx->CR3 = (uint16_t)tmpreg;
-
-/*---------------------------- USART BRR Configuration -----------------------*/
- /* Configure the USART Baud Rate */
- RCC_GetClocksFreq(&RCC_ClocksStatus);
-
- if ((USARTx == USART1) || (USARTx == USART6))
- {
- apbclock = RCC_ClocksStatus.PCLK2_Frequency;
- }
- else
- {
- apbclock = RCC_ClocksStatus.PCLK1_Frequency;
- }
-
- /* Determine the integer part */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- /* Integer part computing in case Oversampling mode is 8 Samples */
- integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
- }
- else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
- {
- /* Integer part computing in case Oversampling mode is 16 Samples */
- integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
- }
- tmpreg = (integerdivider / 100) << 4;
-
- /* Determine the fractional part */
- fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
-
- /* Implement the fractional part in the register */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
- }
- else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
- {
- tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
- }
-
- /* Write to USART BRR register */
- USARTx->BRR = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_InitStruct member with its default value.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
- /* USART_InitStruct members default value */
- USART_InitStruct->USART_BaudRate = 9600;
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;
- USART_InitStruct->USART_StopBits = USART_StopBits_1;
- USART_InitStruct->USART_Parity = USART_Parity_No ;
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-}
-
-/**
- * @brief Initializes the USARTx peripheral Clock according to the
- * specified parameters in the USART_ClockInitStruct .
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that
- * contains the configuration information for the specified USART peripheral.
- * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
- * @retval None
- */
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- uint32_t tmpreg = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear CLKEN, CPOL, CPHA and LBCL bits */
- tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
- /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
- /* Set CLKEN bit according to USART_Clock value */
- /* Set CPOL bit according to USART_CPOL value */
- /* Set CPHA bit according to USART_CPHA value */
- /* Set LBCL bit according to USART_LastBit value */
- tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_ClockInitStruct member with its default value.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- /* USART_ClockInitStruct members default value */
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/**
- * @brief Enables or disables the specified USART peripheral.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USARTx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART by setting the UE bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_UE;
- }
- else
- {
- /* Disable the selected USART by clearing the UE bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);
- }
-}
-
-/**
- * @brief Sets the system clock prescaler.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_Prescaler: specifies the prescaler clock.
- * @note The function is used for IrDA mode with UART4 and UART5.
- * @retval None
- */
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Clear the USART prescaler */
- USARTx->GTPR &= USART_GTPR_GT;
- /* Set the USART prescaler */
- USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
- * @brief Enables or disables the USART's 8x oversampling mode.
- * @note This function has to be called before calling USART_Init() function
- * in order to have correct baudrate Divider value.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART 8x oversampling mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_OVER8;
- }
- else
- {
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);
- }
-}
-
-/**
- * @brief Enables or disables the USART's one bit sampling method.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART one bit sampling method.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_ONEBIT;
- }
- else
- {
- /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART data
- transfers.
- [..]
- During an USART reception, data shifts in least significant bit first through
- the RX pin. In this mode, the USART_DR register consists of a buffer (RDR)
- between the internal bus and the received shift register.
- [..]
- When a transmission is taking place, a write instruction to the USART_DR register
- stores the data in the TDR register and which is copied in the shift register
- at the end of the current transmission.
- [..]
- The read access of the USART_DR register can be done using the USART_ReceiveData()
- function and returns the RDR buffered value. Whereas a write access to the USART_DR
- can be done using USART_SendData() function and stores the written data into
- TDR buffer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits single data through the USARTx peripheral.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param Data: the data to transmit.
- * @retval None
- */
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DATA(Data));
-
- /* Transmit Data */
- USARTx->DR = (Data & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Returns the most recent received data by the USARTx peripheral.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @retval The received data.
- */
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Receive Data */
- return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group3 MultiProcessor Communication functions
- * @brief Multi-Processor Communication functions
- *
-@verbatim
- ===============================================================================
- ##### Multi-Processor Communication functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART
- multiprocessor communication.
- [..]
- For instance one of the USARTs can be the master, its TX output is connected
- to the RX input of the other USART. The others are slaves, their respective
- TX outputs are logically ANDed together and connected to the RX input of the
- master.
- [..]
- USART multiprocessor communication is possible through the following procedure:
- (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode
- transmitter or Mode receiver and hardware flow control values using
- the USART_Init() function.
- (#) Configures the USART address using the USART_SetAddress() function.
- (#) Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)
- using USART_WakeUpConfig() function only for the slaves.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.
- [..]
- The USART Slave exit from mute mode when receive the wake up condition.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the address of the USART node.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_Address: Indicates the address of the USART node.
- * @retval None
- */
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_ADDRESS(USART_Address));
-
- /* Clear the USART address */
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);
- /* Set the USART address node */
- USARTx->CR2 |= USART_Address;
-}
-
-/**
- * @brief Determines if the USART is in mute mode or not.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART mute mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_RWU;
- }
- else
- {
- /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);
- }
-}
-/**
- * @brief Selects the USART WakeUp method.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_WakeUp: specifies the USART wakeup method.
- * This parameter can be one of the following values:
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
- * @retval None
- */
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_WAKEUP(USART_WakeUp));
-
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);
- USARTx->CR1 |= USART_WakeUp;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group4 LIN mode functions
- * @brief LIN mode functions
- *
-@verbatim
- ===============================================================================
- ##### LIN mode functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART LIN
- Mode communication.
- [..]
- In LIN mode, 8-bit data format with 1 stop bit is required in accordance with
- the LIN standard.
- [..]
- Only this LIN Feature is supported by the USART IP:
- (+) LIN Master Synchronous Break send capability and LIN slave break detection
- capability : 13-bit break generation and 10/11 bit break detection
-
- [..]
- USART LIN Master transmitter communication is possible through the following
- procedure:
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values using
- the USART_Init() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enable the LIN mode using the USART_LINCmd() function.
- (#) Send the break character using USART_SendBreak() function.
- [..]
- USART LIN Master receiver communication is possible through the following procedure:
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values using
- the USART_Init() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Configures the break detection length using the USART_LINBreakDetectLengthConfig()
- function.
- (#) Enable the LIN mode using the USART_LINCmd() function.
-
- -@- In LIN mode, the following bits must be kept cleared:
- (+@) CLKEN in the USART_CR2 register,
- (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the USART LIN Break detection length.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
- * @retval None
- */
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);
- USARTx->CR2 |= USART_LINBreakDetectLength;
-}
-
-/**
- * @brief Enables or disables the USART's LIN mode.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART LIN mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_LINEN;
- }
- else
- {
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);
- }
-}
-
-/**
- * @brief Transmits break characters.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @retval None
- */
-void USART_SendBreak(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Send break characters */
- USARTx->CR1 |= USART_CR1_SBK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group5 Halfduplex mode function
- * @brief Half-duplex mode function
- *
-@verbatim
- ===============================================================================
- ##### Half-duplex mode function #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART
- Half-duplex communication.
- [..]
- The USART can be configured to follow a single-wire half-duplex protocol where
- the TX and RX lines are internally connected.
- [..]
- USART Half duplex communication is possible through the following procedure:
- (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter
- or Mode receiver and hardware flow control values using the USART_Init()
- function.
- (#) Configures the USART address using the USART_SetAddress() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
-
-
- -@- The RX pin is no longer used
- -@- In Half-duplex mode the following bits must be kept cleared:
- (+@) LINEN and CLKEN bits in the USART_CR2 register.
- (+@) SCEN and IREN bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's Half Duplex communication.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART Communication.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_HDSEL;
- }
- else
- {
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);
- }
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group6 Smartcard mode functions
- * @brief Smartcard mode functions
- *
-@verbatim
- ===============================================================================
- ##### Smartcard mode functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART
- Smartcard communication.
- [..]
- The Smartcard interface is designed to support asynchronous protocol Smartcards as
- defined in the ISO 7816-3 standard.
- [..]
- The USART can provide a clock to the smartcard through the SCLK output.
- In smartcard mode, SCLK is not associated to the communication but is simply derived
- from the internal peripheral input clock through a 5-bit prescaler.
- [..]
- Smartcard communication is possible through the following procedure:
- (#) Configures the Smartcard Prescaler using the USART_SetPrescaler() function.
- (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() function.
- (#) Program the USART clock using the USART_ClockInit() function as following:
- (++) USART Clock enabled
- (++) USART CPOL Low
- (++) USART CPHA on first edge
- (++) USART Last Bit Clock Enabled
- (#) Program the Smartcard interface using the USART_Init() function as following:
- (++) Word Length = 9 Bits
- (++) 1.5 Stop Bit
- (++) Even parity
- (++) BaudRate = 12096 baud
- (++) Hardware flow control disabled (RTS and CTS signals)
- (++) Tx and Rx enabled
- (#) POptionally you can enable the parity error interrupt using the USART_ITConfig()
- function
- (#) PEnable the USART using the USART_Cmd() function.
- (#) PEnable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
- (#) PEnable the Smartcard interface using the USART_SmartCardCmd() function.
-
- Please refer to the ISO 7816-3 specification for more details.
-
- -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended
- to use 1.5 stop bits for both transmitting and receiving to avoid switching
- between the two configurations.
- -@- In smartcard mode, the following bits must be kept cleared:
- (+@) LINEN bit in the USART_CR2 register.
- (+@) HDSEL and IREN bits in the USART_CR3 register.
- -@- Smartcard mode is available on USART peripherals only (not available on UART4
- and UART5 peripherals).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the specified USART guard time.
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
- * UART peripheral.
- * @param USART_GuardTime: specifies the guard time.
- * @retval None
- */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
-
- /* Clear the USART Guard time */
- USARTx->GTPR &= USART_GTPR_PSC;
- /* Set the USART guard time */
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
- * @brief Enables or disables the USART's Smart Card mode.
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the Smart Card mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_SCEN;
- }
- else
- {
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);
- }
-}
-
-/**
- * @brief Enables or disables NACK transmission.
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the NACK transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_NACK;
- }
- else
- {
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group7 IrDA mode functions
- * @brief IrDA mode functions
- *
-@verbatim
- ===============================================================================
- ##### IrDA mode functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART
- IrDA communication.
- [..]
- IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
- on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
- is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
- While receiving data, transmission should be avoided as the data to be transmitted
- could be corrupted.
- [..]
- IrDA communication is possible through the following procedure:
- (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver
- modes and hardware flow control values using the USART_Init() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Configures the IrDA pulse width by configuring the prescaler using
- the USART_SetPrescaler() function.
- (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode
- using the USART_IrDAConfig() function.
- (#) Enable the IrDA using the USART_IrDACmd() function.
-
- -@- A pulse of width less than two and greater than one PSC period(s) may or may
- not be rejected.
- -@- The receiver set up time should be managed by software. The IrDA physical layer
- specification specifies a minimum of 10 ms delay between transmission and
- reception (IrDA is a half duplex protocol).
- -@- In IrDA mode, the following bits must be kept cleared:
- (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
- (+@) SCEN and HDSEL bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the USART's IrDA interface.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_IrDAMode: specifies the IrDA mode.
- * This parameter can be one of the following values:
- * @arg USART_IrDAMode_LowPower
- * @arg USART_IrDAMode_Normal
- * @retval None
- */
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);
- USARTx->CR3 |= USART_IrDAMode;
-}
-
-/**
- * @brief Enables or disables the USART's IrDA interface.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the IrDA mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_IREN;
- }
- else
- {
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group8 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's DMA interface.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_DMAReq: specifies the DMA request.
- * This parameter can be any combination of the following values:
- * @arg USART_DMAReq_Tx: USART DMA transmit request
- * @arg USART_DMAReq_Rx: USART DMA receive request
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DMAREQ(USART_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 |= USART_DMAReq;
- }
- else
- {
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 &= (uint16_t)~USART_DMAReq;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group9 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to configure the USART
- Interrupts sources, DMA channels requests and check or clear the flags or
- pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- *** Polling Mode ***
- ====================
- [..]
- In Polling Mode, the SPI communication can be managed by 10 flags:
- (#) USART_FLAG_TXE : to indicate the status of the transmit buffer register
- (#) USART_FLAG_RXNE : to indicate the status of the receive buffer register
- (#) USART_FLAG_TC : to indicate the status of the transmit operation
- (#) USART_FLAG_IDLE : to indicate the status of the Idle Line
- (#) USART_FLAG_CTS : to indicate the status of the nCTS input
- (#) USART_FLAG_LBD : to indicate the status of the LIN break detection
- (#) USART_FLAG_NE : to indicate if a noise error occur
- (#) USART_FLAG_FE : to indicate if a frame error occur
- (#) USART_FLAG_PE : to indicate if a parity error occur
- (#) USART_FLAG_ORE : to indicate if an Overrun error occur
- [..]
- In this Mode it is advised to use the following functions:
- (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
- (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..]
- In Interrupt Mode, the USART communication can be managed by 8 interrupt sources
- and 10 pending bits:
-
- (#) Pending Bits:
-
- (##) USART_IT_TXE : to indicate the status of the transmit buffer register
- (##) USART_IT_RXNE : to indicate the status of the receive buffer register
- (##) USART_IT_TC : to indicate the status of the transmit operation
- (##) USART_IT_IDLE : to indicate the status of the Idle Line
- (##) USART_IT_CTS : to indicate the status of the nCTS input
- (##) USART_IT_LBD : to indicate the status of the LIN break detection
- (##) USART_IT_NE : to indicate if a noise error occur
- (##) USART_IT_FE : to indicate if a frame error occur
- (##) USART_IT_PE : to indicate if a parity error occur
- (##) USART_IT_ORE : to indicate if an Overrun error occur
-
- (#) Interrupt Source:
-
- (##) USART_IT_TXE : specifies the interrupt source for the Tx buffer empty
- interrupt.
- (##) USART_IT_RXNE : specifies the interrupt source for the Rx buffer not
- empty interrupt.
- (##) USART_IT_TC : specifies the interrupt source for the Transmit complete
- interrupt.
- (##) USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt.
- (##) USART_IT_CTS : specifies the interrupt source for the CTS interrupt.
- (##) USART_IT_LBD : specifies the interrupt source for the LIN break detection
- interrupt.
- (##) USART_IT_PE : specifies the interrupt source for the parity error interrupt.
- (##) USART_IT_ERR : specifies the interrupt source for the errors interrupt.
-
- -@@- Some parameters are coded in order to use them as interrupt source
- or as pending bits.
- [..]
- In this Mode it is advised to use the following functions:
- (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
- (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
- (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
-
- *** DMA Mode ***
- ================
- [..]
- In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:
- (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request
- (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request
- [..]
- In this Mode it is advised to use the following function:
- (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified USART interrupts.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified USARTx interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
-{
- uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
- uint32_t usartxbase = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CONFIG_IT(USART_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- usartxbase = (uint32_t)USARTx;
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
-
- /* Get the interrupt position */
- itpos = USART_IT & IT_MASK;
- itmask = (((uint32_t)0x01) << itpos);
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- usartxbase += 0x0C;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- usartxbase += 0x10;
- }
- else /* The IT is in CR3 register */
- {
- usartxbase += 0x14;
- }
- if (NewState != DISABLE)
- {
- *(__IO uint32_t*)usartxbase |= itmask;
- }
- else
- {
- *(__IO uint32_t*)usartxbase &= ~itmask;
- }
-}
-
-/**
- * @brief Checks whether the specified USART flag is set or not.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
- * @arg USART_FLAG_LBD: LIN Break detection flag
- * @arg USART_FLAG_TXE: Transmit data register empty flag
- * @arg USART_FLAG_TC: Transmission Complete flag
- * @arg USART_FLAG_RXNE: Receive data register not empty flag
- * @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
- * @arg USART_FLAG_NE: Noise Error flag
- * @arg USART_FLAG_FE: Framing Error flag
- * @arg USART_FLAG_PE: Parity Error flag
- * @retval The new state of USART_FLAG (SET or RESET).
- */
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_FLAG(USART_FLAG));
-
- /* The CTS flag is not available for UART4 and UART5 */
- if (USART_FLAG == USART_FLAG_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's pending flags.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
- * @arg USART_FLAG_LBD: LIN Break detection flag.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) flags are cleared by software
- * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
- * followed by a read operation to USART_DR register (USART_ReceiveData()).
- * @note RXNE flag can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * @note TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register (USART_GetFlagStatus()) followed by a write operation
- * to USART_DR register (USART_SendData()).
- * @note TXE flag is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- *
- * @retval None
- */
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
-
- /* The CTS flag is not available for UART4 and UART5 */
- if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- USARTx->SR = (uint16_t)~USART_FLAG;
-}
-
-/**
- * @brief Checks whether the specified USART interrupt has occurred or not.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_IT: specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set
- * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set
- * @arg USART_IT_NE: Noise Error interrupt
- * @arg USART_IT_FE: Framing Error interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @retval The new state of USART_IT (SET or RESET).
- */
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_GET_IT(USART_IT));
-
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
- /* Get the interrupt position */
- itmask = USART_IT & IT_MASK;
- itmask = (uint32_t)0x01 << itmask;
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- itmask &= USARTx->CR1;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- itmask &= USARTx->CR2;
- }
- else /* The IT is in CR3 register */
- {
- itmask &= USARTx->CR3;
- }
-
- bitpos = USART_IT >> 0x08;
- bitpos = (uint32_t)0x01 << bitpos;
- bitpos &= USARTx->SR;
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's interrupt pending bits.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) pending bits are cleared by
- * software sequence: a read operation to USART_SR register
- * (USART_GetITStatus()) followed by a read operation to USART_DR register
- * (USART_ReceiveData()).
- * @note RXNE pending bit can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * @note TC pending bit can be also cleared by software sequence: a read
- * operation to USART_SR register (USART_GetITStatus()) followed by a write
- * operation to USART_DR register (USART_SendData()).
- * @note TXE pending bit is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- *
- * @retval None
- */
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint16_t bitpos = 0x00, itmask = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_IT(USART_IT));
-
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- bitpos = USART_IT >> 0x08;
- itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
- USARTx->SR = (uint16_t)~itmask;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
deleted file mode 100644
index d3e651b3..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_wwdg.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Window watchdog (WWDG) peripheral:
- * + Prescaler, Refresh window and Counter configuration
- * + WWDG activation
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### WWDG features #####
- ===============================================================================
- [..]
- Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the counter (downcounter)
- before to reach 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3F).
- An MCU reset is also generated if the counter value is refreshed
- before the counter has reached the refresh window value. This
- implies that the counter must be refreshed in a limited window.
-
- Once enabled the WWDG cannot be disabled except by a system reset.
-
- WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
- reset occurs.
-
- The WWDG counter input clock is derived from the APB clock divided
- by a programmable prescaler.
-
- WWDG counter clock = PCLK1 / Prescaler
- WWDG timeout = (WWDG counter clock) * (counter value)
-
- Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
-
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function
-
- (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function
-
- (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function
-
- (#) Set the WWDG counter value and start it using WWDG_Enable() function.
- When the WWDG is enabled the counter value should be configured to
- a value greater than 0x40 to prevent generating an immediate reset.
-
- (#) Optionally you can enable the Early wakeup interrupt which is
- generated when the counter reach 0x40.
- Once enabled this interrupt cannot be disabled except by a system reset.
-
- (#) Then the application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
- WWDG_SetCounter() function. This operation must occur only when
- the counter value is lower than the refresh window value,
- programmed using WWDG_SetWindowValue().
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CONF_H
-#define __STM32F4xx_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment the line below to enable peripheral header file inclusion */
-#include "stm32f4xx_adc.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_crc.h"
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_dac.h"
-#include "stm32f4xx_dbgmcu.h"
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_dma.h"
-#include "stm32f4xx_exti.h"
-#include "stm32f4xx_flash.h"
-#include "stm32f4xx_fsmc.h"
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_gpio.h"
-#include "stm32f4xx_i2c.h"
-#include "stm32f4xx_iwdg.h"
-#include "stm32f4xx_pwr.h"
-#include "stm32f4xx_rcc.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_rtc.h"
-#include "stm32f4xx_sdio.h"
-#include "stm32f4xx_spi.h"
-#include "stm32f4xx_syscfg.h"
-#include "stm32f4xx_tim.h"
-#include "stm32f4xx_usart.h"
-#include "stm32f4xx_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* If an external clock source is used, then the value of the following define
- should be set to the value of the external clock source, else, if no external
- clock is used, keep this define commented */
-/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
-
-
-/* Uncomment the line below to expanse the "assert_param" macro in the
- Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT 1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F4xx_CONF_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/clock-arch.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/clock-arch.c
deleted file mode 100644
index 1e213136..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/clock-arch.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (c) 2006, Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Institute nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * This file is part of the uIP TCP/IP stack
- *
- * $Id: clock-arch.c,v 1.2 2006/06/12 08:00:31 adam Exp $
- */
-
-/**
- * \file
- * Implementation of architecture-specific clock functionality
- * \author
- * Adam Dunkels
- */
-
-#include "clock-arch.h"
-#include "boot.h"
-
-/*---------------------------------------------------------------------------*/
-clock_time_t
-clock_time(void)
-{
- return (clock_time_t)TimerGet();
-}
-/*---------------------------------------------------------------------------*/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/clock-arch.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/clock-arch.h
deleted file mode 100644
index aa97f0e7..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/clock-arch.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2006, Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Institute nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * This file is part of the uIP TCP/IP stack
- *
- * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $
- */
-
-#ifndef __CLOCK_ARCH_H__
-#define __CLOCK_ARCH_H__
-
-typedef int clock_time_t;
-#define CLOCK_CONF_SECOND 1000
-
-#endif /* __CLOCK_ARCH_H__ */
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/netdev.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/netdev.c
deleted file mode 100644
index 09d0d2a7..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/netdev.c
+++ /dev/null
@@ -1,451 +0,0 @@
-/*
- * Copyright (c) 2001, Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the Institute nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * Author: Adam Dunkels
- *
- * $Id: netdev.c,v 1.8 2006/06/07 08:39:58 adam Exp $
- */
-
-
-/*---------------------------------------------------------------------------*/
-#include "uip.h"
-#include "uip_arp.h"
-#include "boot.h"
-#include "stm32f4xx.h" /* STM32 registers */
-#include "stm32f4xx_conf.h" /* STM32 peripheral drivers */
-#include "stm32_eth.h" /* STM32 ethernet library */
-#include /* for memcpy */
-
-
-/*---------------------------------------------------------------------------*/
-#define NETDEV_DEFAULT_MACADDR0 (0x08)
-#define NETDEV_DEFAULT_MACADDR1 (0x00)
-#define NETDEV_DEFAULT_MACADDR2 (0x27)
-#define NETDEV_DEFAULT_MACADDR3 (0x69)
-#define NETDEV_DEFAULT_MACADDR4 (0x5B)
-#define NETDEV_DEFAULT_MACADDR5 (0x45)
-
-
-/*---------------------------------------------------------------------------*/
-static void netdev_TxDscrInit(void);
-static void netdev_RxDscrInit(void);
-
-/*---------------------------------------------------------------------------*/
-typedef union _TranDesc0_t
-{
- uint32_t Data;
- struct {
- uint32_t DB : 1;
- uint32_t UF : 1;
- uint32_t ED : 1;
- uint32_t CC : 4;
- uint32_t VF : 1;
- uint32_t EC : 1;
- uint32_t LC : 1;
- uint32_t NC : 1;
- uint32_t LSC : 1;
- uint32_t IPE : 1;
- uint32_t FF : 1;
- uint32_t JT : 1;
- uint32_t ES : 1;
- uint32_t IHE : 1;
- uint32_t : 3;
- uint32_t TCH : 1;
- uint32_t TER : 1;
- uint32_t CIC : 2;
- uint32_t : 2;
- uint32_t DP : 1;
- uint32_t DC : 1;
- uint32_t FS : 1;
- uint32_t LSEG : 1;
- uint32_t IC : 1;
- uint32_t OWN : 1;
- };
-} TranDesc0_t, * pTranDesc0_t;
-
-typedef union _TranDesc1_t
-{
- uint32_t Data;
- struct {
- uint32_t TBS1 :13;
- uint32_t : 3;
- uint32_t TBS2 :12;
- uint32_t : 3;
- };
-} TranDesc1_t, * pTranDesc1_t;
-
-typedef union _RecDesc0_t
-{
- uint32_t Data;
- struct {
- uint32_t RMAM_PCE : 1;
- uint32_t CE : 1;
- uint32_t DE : 1;
- uint32_t RE : 1;
- uint32_t RWT : 1;
- uint32_t FT : 1;
- uint32_t LC : 1;
- uint32_t IPHCE : 1;
- uint32_t LS : 1;
- uint32_t FS : 1;
- uint32_t VLAN : 1;
- uint32_t OE : 1;
- uint32_t LE : 1;
- uint32_t SAF : 1;
- uint32_t DERR : 1;
- uint32_t ES : 1;
- uint32_t FL :14;
- uint32_t AFM : 1;
- uint32_t OWN : 1;
- };
-} RecDesc0_t, * pRecDesc0_t;
-
-typedef union _recDesc1_t
-{
- uint32_t Data;
- struct {
- uint32_t RBS1 :13;
- uint32_t : 1;
- uint32_t RCH : 1;
- uint32_t RER : 1;
- uint32_t RBS2 :14;
- uint32_t DIC : 1;
- };
-} RecDesc1_t, * pRecDesc1_t;
-
-typedef union _EnetDmaDesc_t
-{
- uint32_t Data[4];
- // Rx DMA descriptor
- struct
- {
- RecDesc0_t RxDesc0;
- RecDesc1_t RxDesc1;
- uint32_t * pBuffer;
- union
- {
- uint32_t * pBuffer2;
- union _EnetDmaDesc_t * pEnetDmaNextDesc;
- };
- } Rx;
- // Tx DMA descriptor
- struct
- {
- TranDesc0_t TxDesc0;
- TranDesc1_t TxDesc1;
- uint32_t * pBuffer1;
- union
- {
- uint32_t * pBuffer2;
- union _EnetDmaDesc_t * pEnetDmaNextDesc;
- };
- } Tx;
-} EnetDmaDesc_t, * pEnetDmaDesc_t;
-
-
-/*---------------------------------------------------------------------------*/
-uint8_t RxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4)));
-uint8_t TxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4)));
-
-EnetDmaDesc_t EnetDmaRx __attribute__((aligned (128)));
-EnetDmaDesc_t EnetDmaTx __attribute__ ((aligned (128)));
-
-
-/*---------------------------------------------------------------------------*/
-void netdev_init(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
- ETH_InitTypeDef ETH_InitStructure;
-
- /* Enable ETHERNET clocks */
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |
- RCC_AHB1Periph_ETH_MAC_Rx | RCC_AHB1Periph_ETH_MAC_PTP, ENABLE);
-
-
- /* Enable GPIOs clocks */
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB |
- RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG, ENABLE);
-
- /* Enable SYSCFG clock */
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- /*Select RMII Interface*/
- SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
-
- /* ETHERNET pins configuration */
- /* PA
- ETH_RMII_REF_CLK: PA1
- ETH_RMII_MDIO: PA2
- ETH_RMII_MDINT: PA3
- ETH_RMII_CRS_DV: PA7
- */
-
- /* Configure PA1, PA2, PA3 and PA7*/
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_7;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* Connect PA1, PA2, PA3 and PA7 to ethernet module*/
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_ETH);
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
-
- /* PB
- ETH_RMII_TX_EN: PG11
- */
-
- /* Configure PG11*/
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOG, &GPIO_InitStructure);
-
- /* Connect PG11 to ethernet module*/
- GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH);
-
- /* PC
- ETH_RMII_MDC: PC1
- ETH_RMII_RXD0: PC4
- ETH_RMII_RXD1: PC5
- */
-
- /* Configure PC1, PC4 and PC5*/
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOC, &GPIO_InitStructure);
-
- /* Connect PC1, PC4 and PC5 to ethernet module*/
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
-
- /* PG
- ETH_RMII_TXD0: PG13
- ETH_RMII_TXD1: PG14
- */
-
- /* Configure PG13 and PG14*/
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOG, &GPIO_InitStructure);
-
- /* Connect PG13 and PG14 to ethernet module*/
- GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH);
- GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH);
-
- /* Reset ETHERNET on AHB Bus */
- ETH_DeInit();
-
- /* Software reset */
- ETH_SoftwareReset();
-
- /* Wait for software reset */
- while(ETH_GetSoftwareResetStatus()==SET);
-
- /* ETHERNET Configuration ------------------------------------------------------*/
- /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
- ETH_StructInit(Ð_InitStructure);
-
- /* Fill ETH_InitStructure parametrs */
- /*------------------------ MAC -----------------------------------*/
- ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable ;
- ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
- ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
- ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
- ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable;
- ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
- ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
- ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
- ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
- ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;
- ETH_InitStructure.ETH_Speed = ETH_Speed_100M;
-
- unsigned int PhyAddr;
- union {
- uint32_t HI_LO;
- struct
- {
- uint16_t LO;
- uint16_t HI;
- };
- } PHYID;
- for(PhyAddr = 0; 32 > PhyAddr; PhyAddr++)
- {
- // datasheet for the ks8721bl ethernet controller (http://www.micrel.com/_PDF/Ethernet/datasheets/ks8721bl-sl.pdf)
- // page 20 --> PHY Identifier 1 and 2
- PHYID.HI = ETH_ReadPHYRegister(PhyAddr,2); // 0x0022
- PHYID.LO = ETH_ReadPHYRegister(PhyAddr,3); // 0x1619
- if ((0x00221619 == PHYID.HI_LO) || (0x0007C0F1 == PHYID.HI_LO))
- break;
- }
- if (32 < PhyAddr)
- {
- ASSERT_RT(BLT_FALSE);
- }
- /* Configure Ethernet */
- if(0 == ETH_Init(Ð_InitStructure, PhyAddr))
- {
- ASSERT_RT(BLT_FALSE);
- }
-
- netdev_TxDscrInit();
- netdev_RxDscrInit();
- ETH_Start();
-}
-
-
-/*---------------------------------------------------------------------------*/
-void netdev_init_mac(void)
-{
- struct uip_eth_addr macAddress;
-
- /* set the default MAC address */
- macAddress.addr[0] = NETDEV_DEFAULT_MACADDR0;
- macAddress.addr[1] = NETDEV_DEFAULT_MACADDR1;
- macAddress.addr[2] = NETDEV_DEFAULT_MACADDR2;
- macAddress.addr[3] = NETDEV_DEFAULT_MACADDR3;
- macAddress.addr[4] = NETDEV_DEFAULT_MACADDR4;
- macAddress.addr[5] = NETDEV_DEFAULT_MACADDR5;
- uip_setethaddr(macAddress);
-}
-
-
-/*---------------------------------------------------------------------------*/
-unsigned int netdev_read(void)
-{
- uint32_t size;
- /*check for validity*/
- if(0 == EnetDmaRx.Rx.RxDesc0.OWN)
- {
- /*Get the size of the packet*/
- size = EnetDmaRx.Rx.RxDesc0.FL; // CRC
- memcpy(uip_buf, RxBuff, size); //string.h library*/
- }
- else
- {
- return 0;
- }
- /* Give the buffer back to ENET */
- EnetDmaRx.Rx.RxDesc0.OWN = 1;
- /* Start the receive operation */
- ETH->DMARPDR = 1;
- /* Return no error */
- return size;
-}
-
-
-/*---------------------------------------------------------------------------*/
-void netdev_send(void)
-{
- while(EnetDmaTx.Tx.TxDesc0.OWN);
-
- /* Copy the application buffer to the driver buffer
- Using this MEMCOPY_L2L_BY4 makes the copy routine faster
- than memcpy */
- memcpy(TxBuff, uip_buf, uip_len);
-
- /* Assign ENET address to Temp Tx Array */
- EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff;
-
- /* Setting the Frame Length*/
- EnetDmaTx.Tx.TxDesc0.Data = 0;
- EnetDmaTx.Tx.TxDesc0.TCH = 1;
- EnetDmaTx.Tx.TxDesc0.LSEG = 1;
- EnetDmaTx.Tx.TxDesc0.FS = 1;
- EnetDmaTx.Tx.TxDesc0.DC = 0;
- EnetDmaTx.Tx.TxDesc0.DP = 0;
-
- EnetDmaTx.Tx.TxDesc1.Data = 0;
- EnetDmaTx.Tx.TxDesc1.TBS1 = (uip_len&0xFFF);
-
- /* Start the ENET by setting the VALID bit in dmaPackStatus of current descr*/
- EnetDmaTx.Tx.TxDesc0.OWN = 1;
-
- /* Start the transmit operation */
- ETH->DMATPDR = 1;
-}
-
-
-/*---------------------------------------------------------------------------*/
-static void netdev_RxDscrInit(void)
-{
- /* Initialization */
- /* Assign temp Rx array to the ENET buffer */
- EnetDmaRx.Rx.pBuffer = (uint32_t *)RxBuff;
-
- /* Initialize RX ENET Status and control */
- EnetDmaRx.Rx.RxDesc0.Data = 0;
-
- /* Initialize the next descriptor- In our case its single descriptor */
- EnetDmaRx.Rx.pEnetDmaNextDesc = &EnetDmaRx;
-
- EnetDmaRx.Rx.RxDesc1.Data = 0;
- EnetDmaRx.Rx.RxDesc1.RER = 0; // end of ring
- EnetDmaRx.Rx.RxDesc1.RCH = 1; // end of ring
-
- /* Set the max packet size */
- EnetDmaRx.Rx.RxDesc1.RBS1 = UIP_CONF_BUFFER_SIZE;
-
- /* Setting the VALID bit */
- EnetDmaRx.Rx.RxDesc0.OWN = 1;
- /* Setting the RX NEXT Descriptor Register inside the ENET */
- ETH->DMARDLAR = (uint32_t)&EnetDmaRx;
-}
-
-
-/*---------------------------------------------------------------------------*/
-static void netdev_TxDscrInit(void)
-{
- /* ENET Start Address */
- EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff;
-
- /* Next Descriptor Address */
- EnetDmaTx.Tx.pEnetDmaNextDesc = &EnetDmaTx;
-
- /* Initialize ENET status and control */
- EnetDmaTx.Tx.TxDesc0.TCH = 1;
- EnetDmaTx.Tx.TxDesc0.Data = 0;
- EnetDmaTx.Tx.TxDesc1.Data = 0;
- /* Tx next set to Tx descriptor base */
- ETH->DMATDLAR = (uint32_t)&EnetDmaTx;
-
-}
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/netdev.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/netdev.h
deleted file mode 100644
index 4ea59ce5..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/netdev.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2001, Adam Dunkels.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Adam Dunkels.
- * 4. The name of the author may not be used to endorse or promote
- * products derived from this software without specific prior
- * written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * This file is part of the uIP TCP/IP stack.
- *
- * $Id: netdev.h,v 1.1 2002/01/10 06:22:56 adam Exp $
- *
- */
-
-#ifndef __NETDEV_H__
-#define __NETDEV_H__
-
-void netdev_init(void);
-void netdev_init_mac(void);
-unsigned int netdev_read(void);
-void netdev_send(void);
-
-#endif /* __NETDEV_H__ */
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/uip-conf.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/uip-conf.h
deleted file mode 100644
index fd9ba0dd..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/uip/uip-conf.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/**
- * \addtogroup uipopt
- * @{
- */
-
-/**
- * \name Project-specific configuration options
- * @{
- *
- * uIP has a number of configuration options that can be overridden
- * for each project. These are kept in a project-specific uip-conf.h
- * file and all configuration names have the prefix UIP_CONF.
- */
-
-/*
- * Copyright (c) 2006, Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Institute nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * This file is part of the uIP TCP/IP stack
- *
- * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $
- */
-
-/**
- * \file
- * An example uIP configuration file
- * \author
- * Adam Dunkels
- */
-
-#ifndef __UIP_CONF_H__
-#define __UIP_CONF_H__
-
-
-/**
- * 8 bit datatype
- *
- * This typedef defines the 8-bit type used throughout uIP.
- *
- * \hideinitializer
- */
-typedef unsigned char u8_t;
-
-/**
- * 16 bit datatype
- *
- * This typedef defines the 16-bit type used throughout uIP.
- *
- * \hideinitializer
- */
-typedef unsigned short u16_t;
-
-/**
- * Statistics datatype
- *
- * This typedef defines the dataype used for keeping statistics in
- * uIP.
- *
- * \hideinitializer
- */
-typedef unsigned short uip_stats_t;
-
-/**
- * Maximum number of TCP connections.
- *
- * \hideinitializer
- */
-#define UIP_CONF_MAX_CONNECTIONS 1
-
-/**
- * Maximum number of listening TCP ports.
- *
- * \hideinitializer
- */
-#define UIP_CONF_MAX_LISTENPORTS 1
-
-/**
- * uIP buffer size.
- *
- * \hideinitializer
- */
-#define UIP_CONF_BUFFER_SIZE 1600
-
-/**
- * CPU byte order.
- *
- * \hideinitializer
- */
-#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN
-
-/**
- * Logging on or off
- *
- * \hideinitializer
- */
-#define UIP_CONF_LOGGING 0
-
-/**
- * UDP support on or off
- *
- * \hideinitializer
- */
-#define UIP_CONF_UDP 0
-
-/**
- * UDP checksums on or off
- *
- * \hideinitializer
- */
-#define UIP_CONF_UDP_CHECKSUMS 1
-
-/**
- * uIP statistics on or off
- *
- * \hideinitializer
- */
-#define UIP_CONF_STATISTICS 0
-
-/* Here we include the header file for the application(s) we use in
- our project. */
-#include "boot.h"
-#include "net.h"
-
-#endif /* __UIP_CONF_H__ */
-
-/** @} */
-/** @} */
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/usbdevicelib/Core/inc/usbd_core.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/usbdevicelib/Core/inc/usbd_core.h
deleted file mode 100644
index e0884cac..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/usbdevicelib/Core/inc/usbd_core.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_core.h
- * @author MCD Application Team
- * @version V1.1.0
- * @date 19-March-2012
- * @brief Header file for usbd_core.c
- ******************************************************************************
- * @attention
- *
- *
All source files: license disclaimer text update and add link to the License file on ST Internet.
Handle test mode in the set feature request
Handle dynamically the USB SELF POWERED feature
Handle correctly the USBD_CtlError process to take into account error during Control OUT stage
Miscellaneous bug fix
V1.0.0 / 22-July-2011
Main
-Changes
-
First official version for STM32F105/7xx and STM32F2xx devices
-
License
-
Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:
Unless
-required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
-the License for the specific language governing permissions and
-limitations under the License.
-
-
-
-
For
- complete documentation on STM32
- Microcontrollers visit www.st.com/STM32
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/usbotgdriver/Release_Notes.html b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/usbotgdriver/Release_Notes.html
deleted file mode 100644
index 1116edd3..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/usbotgdriver/Release_Notes.html
+++ /dev/null
@@ -1,950 +0,0 @@
-
-
-
-
-
-
-
-
-Release Notes for STM32F105/7xx, STM32F2xx and STM32F4xx USB OTG Driver
-
-
-
-
-
-
All source files: license disclaimer text update and add link to the License file on ST Internet
Unmask Session request interrupt to handle the connect event during the core start-up
Remove any reference to the USB HS external I2C PHY
Update optimization pragma for AR Compiler
Handle Correctly the Low Speed device connection in HS mode
Add a wrapper to isolate the library from the low level driver: connection done through ISR structure
Miscellaneous bug fix
V2.0.0 / 22-July-2011
Main
-Changes
-
Second official version supporting STM32F105/7 and STM32F2xx devices
Rename the Library from "STM32_USB_HOST_Driver" to "STM32_USB_OTG_Driver"
Add support for STM32F2xx devices
Add support for Device and OTG modes
Change HCD layer to support High speed core
Change the Low level driver to support multi core support for Host mode
Add Stop mechanism for Host and Device modes
Change VBUS enabling method, to use the external or the internal VBUS when using the ULPI
V1.0.0 - 11/29/2010
-
Created
License
-
Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:
Unless
-required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
-the License for the specific language governing permissions and
-limitations under the License.
-
-
-
-
For
- complete documentation on STM32
- Microcontrollers visit www.st.com/STM32
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/usbotgdriver/inc/usb_bsp.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/usbotgdriver/inc/usb_bsp.h
deleted file mode 100644
index 29763a90..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/lib/usbotgdriver/inc/usb_bsp.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
- ******************************************************************************
- * @file usb_bsp.h
- * @author MCD Application Team
- * @version V2.1.0
- * @date 19-March-2012
- * @brief Specific api's relative to the used hardware platform
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_CONF__H__
-#define __USB_CONF__H__
-
-/* Includes ------------------------------------------------------------------*/
- #include "stm32f4xx.h"
-
-
-/** @addtogroup USB_OTG_DRIVER
- * @{
- */
-
-/** @defgroup USB_CONF
- * @brief USB low level driver configuration file
- * @{
- */
-
-/** @defgroup USB_CONF_Exported_Defines
- * @{
- */
-
-/* USB Core and PHY interface configuration.
- Tip: To avoid modifying these defines each time you need to change the USB
- configuration, you can declare the needed define in your toolchain
- compiler preprocessor.
- */
-/****************** USB OTG FS PHY CONFIGURATION *******************************
-* The USB OTG FS Core supports one on-chip Full Speed PHY.
-*
-* The USE_EMBEDDED_PHY symbol is defined in the project compiler preprocessor
-* when FS core is used.
-*******************************************************************************/
-#ifndef USE_USB_OTG_FS
- //#define USE_USB_OTG_FS
-#endif /* USE_USB_OTG_FS */
-
-#ifdef USE_USB_OTG_FS
- #define USB_OTG_FS_CORE
-#endif
-
-/****************** USB OTG HS PHY CONFIGURATION *******************************
-* The USB OTG HS Core supports two PHY interfaces:
-* (i) An ULPI interface for the external High Speed PHY: the USB HS Core will
-* operate in High speed mode
-* (ii) An on-chip Full Speed PHY: the USB HS Core will operate in Full speed mode
-*
-* You can select the PHY to be used using one of these two defines:
-* (i) USE_ULPI_PHY: if the USB OTG HS Core is to be used in High speed mode
-* (ii) USE_EMBEDDED_PHY: if the USB OTG HS Core is to be used in Full speed mode
-*
-* Notes:
-* - The USE_ULPI_PHY symbol is defined in the project compiler preprocessor as
-* default PHY when HS core is used.
-* - On STM322xG-EVAL and STM324xG-EVAL boards, only configuration(i) is available.
-* Configuration (ii) need a different hardware, for more details refer to your
-* STM32 device datasheet.
-*******************************************************************************/
-#ifndef USE_USB_OTG_HS
- //#define USE_USB_OTG_HS
-#endif /* USE_USB_OTG_HS */
-
-#ifndef USE_ULPI_PHY
- //#define USE_ULPI_PHY
-#endif /* USE_ULPI_PHY */
-
-#ifndef USE_EMBEDDED_PHY
- //#define USE_EMBEDDED_PHY
-#endif /* USE_EMBEDDED_PHY */
-
-#ifdef USE_USB_OTG_HS
- #define USB_OTG_HS_CORE
-#endif
-
-/*******************************************************************************
-* FIFO Size Configuration in Device mode
-*
-* (i) Receive data FIFO size = RAM for setup packets +
-* OUT endpoint control information +
-* data OUT packets + miscellaneous
-* Space = ONE 32-bits words
-* --> RAM for setup packets = 10 spaces
-* (n is the nbr of CTRL EPs the device core supports)
-* --> OUT EP CTRL info = 1 space
-* (one space for status information written to the FIFO along with each
-* received packet)
-* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces
-* (MINIMUM to receive packets)
-* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces
-* (if high-bandwidth EP is enabled or multiple isochronous EPs)
-* --> miscellaneous = 1 space per OUT EP
-* (one space for transfer complete status information also pushed to the
-* FIFO with each endpoint's last packet)
-*
-* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for
-* that particular IN EP. More space allocated in the IN EP Tx FIFO results
-* in a better performance on the USB and can hide latencies on the AHB.
-*
-* (iii) TXn min size = 16 words. (n : Transmit FIFO index)
-* (iv) When a TxFIFO is not used, the Configuration should be as follows:
-* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
-* --> Txm can use the space allocated for Txn.
-* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
-* --> Txn should be configured with the minimum space of 16 words
-* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top
-* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
-* (vi) In HS case 12 FIFO locations should be reserved for internal DMA registers
-* so total FIFO size should be 1012 Only instead of 1024
-*******************************************************************************/
-
-/****************** USB OTG HS CONFIGURATION **********************************/
-#ifdef USB_OTG_HS_CORE
- #define RX_FIFO_HS_SIZE 512
- #define TX0_FIFO_HS_SIZE 64
- #define TX1_FIFO_HS_SIZE 372
- #define TX2_FIFO_HS_SIZE 64
- #define TX3_FIFO_HS_SIZE 0
- #define TX4_FIFO_HS_SIZE 0
- #define TX5_FIFO_HS_SIZE 0
-
-// #define USB_OTG_HS_SOF_OUTPUT_ENABLED
-
- #ifdef USE_ULPI_PHY
- #define USB_OTG_ULPI_PHY_ENABLED
- #endif
- #ifdef USE_EMBEDDED_PHY
- #define USB_OTG_EMBEDDED_PHY_ENABLED
- /* wakeup is working only when HS core is configured in FS mode */
- #define USB_OTG_HS_LOW_PWR_MGMT_SUPPORT
- #endif
- /* #define USB_OTG_HS_INTERNAL_DMA_ENABLED */ /* Be aware that enabling DMA mode will result in data being sent only by
- multiple of 4 packet sizes. This is due to the fact that USB DMA does
- not allow sending data from non word-aligned addresses.
- For this specific application, it is advised to not enable this option
- unless required. */
- #define USB_OTG_HS_DEDICATED_EP1_ENABLED
-#endif
-
-/****************** USB OTG FS CONFIGURATION **********************************/
-#ifdef USB_OTG_FS_CORE
- #define RX_FIFO_FS_SIZE 128
- #define TX0_FIFO_FS_SIZE 32
- #define TX1_FIFO_FS_SIZE 128
- #define TX2_FIFO_FS_SIZE 32
- #define TX3_FIFO_FS_SIZE 0
-
-// #define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
-// #define USB_OTG_FS_SOF_OUTPUT_ENABLED
-#endif
-
-/****************** USB OTG MISC CONFIGURATION ********************************/
-#define VBUS_SENSING_ENABLED
-
-/****************** USB OTG MODE CONFIGURATION ********************************/
-//#define USE_HOST_MODE
-#define USE_DEVICE_MODE
-//#define USE_OTG_MODE
-
-#ifndef USB_OTG_FS_CORE
- #ifndef USB_OTG_HS_CORE
- #error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined"
- #endif
-#endif
-
-#ifndef USE_DEVICE_MODE
- #ifndef USE_HOST_MODE
- #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
- #endif
-#endif
-
-#ifndef USE_USB_OTG_HS
- #ifndef USE_USB_OTG_FS
- #error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined"
- #endif
-#else //USE_USB_OTG_HS
- #ifndef USE_ULPI_PHY
- #ifndef USE_EMBEDDED_PHY
- #error "USE_ULPI_PHY or USE_EMBEDDED_PHY should be defined"
- #endif
- #endif
-#endif
-
-/****************** C Compilers dependant keywords ****************************/
-/* In HS mode and when the DMA is used, all variables and data structures dealing
- with the DMA during the transaction process should be 4-bytes aligned */
-#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
- #if defined (__GNUC__) /* GNU Compiler */
- #define __ALIGN_END __attribute__ ((aligned (4)))
- #define __ALIGN_BEGIN
- #else
- #define __ALIGN_END
- #if defined (__CC_ARM) /* ARM Compiler */
- #define __ALIGN_BEGIN __align(4)
- #elif defined (__ICCARM__) /* IAR Compiler */
- #define __ALIGN_BEGIN
- #elif defined (__TASKING__) /* TASKING Compiler */
- #define __ALIGN_BEGIN __align(4)
- #endif /* __CC_ARM */
- #endif /* __GNUC__ */
-#else
- #define __ALIGN_BEGIN
- #define __ALIGN_END
-#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
-
-/* __packed keyword used to decrease the data type alignment to 1-byte */
-#if defined (__CC_ARM) /* ARM Compiler */
- #define __packed __packed
-#elif defined (__ICCARM__) /* IAR Compiler */
- #define __packed __packed
-#elif defined ( __GNUC__ ) /* GNU Compiler */
- #define __packed __attribute__ ((__packed__))
-#elif defined (__TASKING__) /* TASKING Compiler */
- #define __packed __unaligned
-#endif /* __CC_ARM */
-
-/**
- * @}
- */
-
-
-/** @defgroup USB_CONF_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USB_CONF_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_CONF_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USB_CONF_Exported_FunctionsPrototype
- * @{
- */
-/**
- * @}
- */
-
-
-#endif //__USB_CONF__H__
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/usbd_bulk.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/usbd_bulk.c
deleted file mode 100644
index 6bd165b6..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Boot/usbd_bulk.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_bulk.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 19-March-2012
- * @brief This file provides the high layer firmware functions to manage a
- * USB bulk device.
- *
- ******************************************************************************
- * @attention
- *
- *
Update product define: replace "#define STM32F4XX" by "#define
-STM32F40XX" for STM32F40x/41x devices
Add new product define: "#define
-STM32F427X" for STM32F427x/437x devices.
Add new startup files "startup_stm32f427x.s"for
-all toolchains
rename startup files "startup_stm32f4xx.s" by "startup_stm32f40xx.s"for
-all toolchains
-
system_stm32f4xx.c
Prefetch Buffer enabled
Add reference to STM32F427x/437x devices and STM324x7I_EVAL board
SystemInit_ExtMemCtl() function
-
Add configuration of missing FSMC address and data lines
-
Change memory type to SRAM instead of PSRAM (PSRAM is available only on STM324xG-EVAL RevA) and update timing values
V1.0.2 / 05-March-2012
-
Main
-Changes
-
-
All source files: license disclaimer text update and add link to the License file on ST Internet.
V1.0.1 / 28-December-2011
Main
-Changes
-
All source files: update disclaimer to add reference to the new license agreement
stm32f4xx.h
Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST
V1.0.0 / 30-September-2011
Main
-Changes
-
First official release for STM32F40x/41x devices
Add startup file for TASKING toolchain
system_stm32f4xx.c: driver's comments update
V1.0.0RC2 / 26-September-2011
Main
-Changes
-
Official version (V1.0.0) Release Candidate2 for STM32F40x/41x devices
stm32f4xx.h
Add define for Cortex-M4 revision __CM4_REV
Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000
Correct some bits definition to be in line with naming used in the Reference Manual (RM0090)
GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x
GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x
SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL
RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST
DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
PWR_CR_PMODE changed to PWR_CR_VOS
PWR_CSR_REGRDY changed to PWR_CSR_VOSRDY
Add new define RCC_AHB1ENR_CCMDATARAMEN
Add new defines SRAM2_BASE, CCMDATARAM_BASE and BKPSRAM_BASE
GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28
system_stm32f4xx.c
SystemInit(): add code to enable the FPU
SetSysClock(): change PWR_CR_PMODE by PWR_CR_VOS
SystemInit_ExtMemCtl(): remove commented values
startup (for all compilers)
Delete code used to enable the FPU (moved to system_stm32f4xx.c file)
File’s header updated
V1.0.0RC1 / 25-August-2011
Main
-Changes
-
Official version (V1.0.0) Release Candidate1 for STM32F4xx devices
-
-
-
-
License
-
-
-
Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:
Unless
-required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
-the License for the specific language governing permissions and
-limitations under the License.
-
-
-
For
-complete documentation on STM32 Microcontrollers
-visit www.st.com/STM32
-
-
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c
deleted file mode 100644
index c839011c..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c
+++ /dev/null
@@ -1,562 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f4xx.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 24-May-2013
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
- * This file contains the system clock configuration for STM32F4xx devices,
- * and is generated by the clock configuration tool
- * stm32f4xx_Clock_Configuration_V1.1.0.xls
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
- * and Divider factors, AHB/APBx prescalers and Flash settings),
- * depending on the configuration made in the clock xls tool.
- * This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f4xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (16 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. If the system clock source selected by user fails to startup, the SystemInit()
- * function will do nothing and HSI still used as system clock source. User can
- * add some code to deal with this issue inside the SetSysClock() function.
- *
- * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
- * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
- * through PLL, and you are using different crystal you have to adapt the HSE
- * value to your own configuration.
- *
- * 5. This file configures the system clock as follows:
- *=============================================================================
- *=============================================================================
- * Supported STM32F40xx/41xx/427x/437x devices
- *-----------------------------------------------------------------------------
- * System Clock source | PLL (HSE)
- *-----------------------------------------------------------------------------
- * SYSCLK(Hz) | 168000000
- *-----------------------------------------------------------------------------
- * HCLK(Hz) | 168000000
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB1 Prescaler | 4
- *-----------------------------------------------------------------------------
- * APB2 Prescaler | 2
- *-----------------------------------------------------------------------------
- * HSE Frequency(Hz) | 12000000
- *-----------------------------------------------------------------------------
- * PLL_M | 12
- *-----------------------------------------------------------------------------
- * PLL_N | 336
- *-----------------------------------------------------------------------------
- * PLL_P | 2
- *-----------------------------------------------------------------------------
- * PLL_Q | 7
- *-----------------------------------------------------------------------------
- * PLLI2S_N | NA
- *-----------------------------------------------------------------------------
- * PLLI2S_R | NA
- *-----------------------------------------------------------------------------
- * I2S input clock | NA
- *-----------------------------------------------------------------------------
- * VDD(V) | 3,3
- *-----------------------------------------------------------------------------
- * Main regulator output voltage | Scale1 mode
- *-----------------------------------------------------------------------------
- * Flash Latency(WS) | 5
- *-----------------------------------------------------------------------------
- * Prefetch Buffer | OFF
- *-----------------------------------------------------------------------------
- * Instruction cache | ON
- *-----------------------------------------------------------------------------
- * Data cache | ON
- *-----------------------------------------------------------------------------
- * Require 48MHz for USB OTG FS, | Enabled
- * SDIO and RNG clock |
- *-----------------------------------------------------------------------------
- *=============================================================================
- ******************************************************************************
- * @attention
- *
- *
STM32F4xx
- Standard Peripherals Drivers update History
V1.1.0 / 11-Janury-2013
Main
-Changes
-
-
Official release for STM32F427x/437x devices.
stm32f4xx_cryp.c/.h
Update CRYP_Init() function : add the support for new algorithms (GCM/CCM).
Add new function : CRYP_PhaseConfig() used for new AES-GCM and AES-CCM algorithms.
CRYP_InitTypeDef structure : update all structure fields from uint16_t to uint32_t and update all driver functions parameters and the correpondant define to be declared with uint32_t type.
Replace the "CRYP_ContextSave->CR_bits9to2" by "CRYP_ContextSave->CurrentConfig".
stm32f4xx_flash.c/.h
Update FLASH sectors numbers "FLASH_Sector_x" with x = 0..23.
Update FLASH_EraseAllSectors() function to support mass erase for STM32F427x/437x devices.
stm32f4xx_gpio.c/.h
Add Alternate functions for new peripherals: SPI4, SPI5, SPI6, UART7, UART8.
Update all functions header
-comment.
stm32f4xx_hash.c/.h
Update HASH_GetDigest() function : add the HASH_DIGEST structure.
Add new function HASH_AutoStartDigest().
Update HASH_MsgDigest structure: to support SHA-224 and SHA-256 modes.
Update HASH_Context structure.
Update some define using bit definitions already declared in stm32f4xx.h.
stm32f'xx_i2c.c/.h
Add new functions:
I2C_AnalogFilterCmd(): enable/disable the analog I2C filters.
I2C_DigitalFilterConfig(): configure the digital I2C filters.
stm32f4xx_pwr.c/.h
-
Add new argument "PWR_Regulator_Voltage_Scale3"
- to PWR_MainRegulatorModeConfig() function to be in line with
- Reference Manual description.
stm32f4xx_rcc.c/.h
Add new definitions for new
-peripherals: SPI4, SPI5, SPI6,SAI1, UART7, UART8.
Add a new parameter in RCC_PLLI2SConfig() function : PLLI2SQ to specifies the division factor for SAI1 clock.
Add RCC_TIMCLKPresConfig() function : TIMER Prescaler selection.
stm32l1xx_spi.c/.h
Update to support SPI4, SPI5, SPI6.
-
Update all functions header
-comment.
stm32l1xx_usart.c/.h
Update to support UART7 and
-UART8.
-
Update all functions header
-comment.
V1.0.2 / 05-March-2012
-
Main
-Changes
-
-
All source files: license disclaimer text update and add link to the License file on ST Internet.
stm32f4xx_dcmi.c
DCMI_GetFlagStatus() function: fix test condition on RISR register, use if (dcmireg == 0x00) instead of if (dcmireg == 0x01)
stm32f4xx_pwr.c
PWR_PVDLevelConfig()
-function: remove value of the voltage threshold corresponding to each
-PVD detection level, user should refer to the electrical
-characteristics of the STM32 device datasheet to have the correct
-value
V1.0.1 / 28-December-2011
Main
-Changes
-
All source files: update disclaimer to add reference to the new license agreement
stm32f4xx_rtc.c:
In “RTC_FLAGS_MASK” define: add RTC_FLAG_RECALPF and RTC_FLAG_SHPF
RTC_DeInit() function: add reset of the following registers: SHIFTR, CALR, ALRMASSR and ALRMBSSR
RTC_SetTime() and RTC_SetDate() functions: add test condition on BYPSHAD flag before to test RSF flag (when Bypass mode is enabled, the RSF bit is never set).
V1.0.0 / 30-September-2011
Main
-Changes
-
First official release for STM32F40x/41x devices
stm32f4xx_rtc.c: remove useless code from RTC_GetDate() function
stm32f4xx_rcc.c, stm32f4xx_spi.c, stm32f4xx_wwdg.c and stm32f4xx_syscfg.c: driver's comments update
V1.0.0RC2 / 26-September-2011
Main
-Changes
-
Official version (V1.0.0) Release Candidate1for STM32F40x/STM32F41x devices
stm32f4xx_usart.h/.c
Update procedure to check on overrun error interrupt pending bit, defines for the following flag are added:
USART_IT_ORE_RX: this flag is set if overrun error interrupt occurs and RXNEIE bit is set
USART_IT_ORE_ER:this flag is set if overrun error interrupt occurs and EIE bit is set
stm32f4xx_tim.c
TIM_UpdateRequestConfig(): correct function header's comment
TIM_ICInit(): add assert macros to test if the passed TIM parameter has channel 2, 3 or 4
stm32f4xx_pwr.h/.c
Rename PWR_FLAG_REGRDY constant to PWR_CSR_REGRDY
Rename PWR_FLAG_VOSRDY constant to PWR_CSR_VOSRDY
Rename PWR_HighPerformanceModeCmd(FunctionalState NewState) function to PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
stm32f4xx_rcc.h/.c
RCC_AHB1PeriphClockCmd(): add new constant RCC_AHB1Periph_CCMDATARAMEN as value for RCC_AHB1Periph parameter
stm32f4xx_spi.h
IS_I2S_EXT_PERIPH(): add check on I2S3ext peripheral
V1.0.0RC1 / 25-August-2011
Main
-Changes
-
Official version (V1.0.0) Release Candidate1 for STM32F4xx devices
-
License
-
-
-
Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:
Unless
-required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
-the License for the specific language governing permissions and
-limitations under the License.
-
-
-
-
For
- complete documentation on STM32
- Microcontrollers visit www.st.com/STM32
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/misc.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/misc.h
deleted file mode 100644
index dec96ec2..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/misc.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/**
- ******************************************************************************
- * @file misc.h
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file contains all the functions prototypes for the miscellaneous
- * firmware library functions (add-on to CMSIS functions).
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FSMC_H
-#define __STM32F4xx_FSMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FSMC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief Timing parameters For NOR/SRAM Banks
- */
-typedef struct
-{
- uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
- This parameter can be a value between 0 and 0xF.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address hold time.
- This parameter can be a value between 0 and 0xF.
- @note This parameter is not used with synchronous NOR Flash memories.*/
-
- uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the data setup time.
- This parameter can be a value between 0 and 0xFF.
- @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
-
- uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
- the duration of the bus turnaround.
- This parameter can be a value between 0 and 0xF.
- @note This parameter is only used for multiplexed NOR Flash memories. */
-
- uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
- This parameter can be a value between 1 and 0xF.
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
-
- uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
- to the memory before getting the first data.
- The parameter value depends on the memory type as shown below:
- - It must be set to 0 in case of a CRAM
- - It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between 0 and 0xF in NOR Flash memories
- with synchronous burst mode enable */
-
- uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FSMC_Access_Mode */
-}FSMC_NORSRAMTimingInitTypeDef;
-
-/**
- * @brief FSMC NOR/SRAM Init structure definition
- */
-typedef struct
-{
- uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */
-
- uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the data bus or not.
- This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
- uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
- the corresponding memory bank.
- This parameter can be a value of @ref FSMC_Memory_Type */
-
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FSMC_Data_Width */
-
- uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
- valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FSMC_Burst_Access_Mode */
-
- uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
- valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FSMC_AsynchronousWait */
-
- uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
- the Flash memory in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
-
- uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
- memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FSMC_Wrap_Mode */
-
- uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
- clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Timing */
-
- uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
- This parameter can be a value of @ref FSMC_Write_Operation */
-
- uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
- signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal */
-
- uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FSMC_Extended_Mode */
-
- uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FSMC_Write_Burst */
-
- FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/
-
- FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/
-}FSMC_NORSRAMInitTypeDef;
-
-/**
- * @brief Timing parameters For FSMC NAND and PCCARD Banks
- */
-typedef struct
-{
- uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
- the command assertion for NAND Flash read or write access
- to common/Attribute or I/O memory space (depending on
- the memory space timing to be configured).
- This parameter can be a value between 0 and 0xFF.*/
-
- uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
- command for NAND Flash read or write access to
- common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-
- uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
- (and data for write access) after the command de-assertion
- for NAND Flash read or write access to common/Attribute
- or I/O memory space (depending on the memory space timing
- to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-
- uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
- data bus is kept in HiZ after the start of a NAND Flash
- write access to common/Attribute or I/O memory space (depending
- on the memory space timing to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-}FSMC_NAND_PCCARDTimingInitTypeDef;
-
-/**
- * @brief FSMC NAND Init structure definition
- */
-typedef struct
-{
- uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
- This parameter can be a value of @ref FSMC_NAND_Bank */
-
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FSMC_Data_Width */
-
- uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FSMC_ECC */
-
- uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FSMC_ECC_Page_Size */
-
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 0xFF. */
-
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0x0 and 0xFF */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-}FSMC_NANDInitTypeDef;
-
-/**
- * @brief FSMC PCCARD Init structure definition
- */
-
-typedef struct
-{
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 0xFF. */
-
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0x0 and 0xFF */
-
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
-}FSMC_PCCARDInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FSMC_Exported_Constants
- * @{
- */
-
-/** @defgroup FSMC_NORSRAM_Bank
- * @{
- */
-#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
-#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
-#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
-#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_Bank
- * @{
- */
-#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
-#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCCARD_Bank
- * @{
- */
-#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
-/**
- * @}
- */
-
-#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
- ((BANK) == FSMC_Bank1_NORSRAM2) || \
- ((BANK) == FSMC_Bank1_NORSRAM3) || \
- ((BANK) == FSMC_Bank1_NORSRAM4))
-
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND))
-
-#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND) || \
- ((BANK) == FSMC_Bank4_PCCARD))
-
-#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND) || \
- ((BANK) == FSMC_Bank4_PCCARD))
-
-/** @defgroup FSMC_NOR_SRAM_Controller
- * @{
- */
-
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing
- * @{
- */
-
-#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
-#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
-#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
- ((MUX) == FSMC_DataAddressMux_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Memory_Type
- * @{
- */
-
-#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
-#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
-#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
-#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
- ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
- ((MEMORY) == FSMC_MemoryType_NOR))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Width
- * @{
- */
-
-#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
-#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
-#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
- ((WIDTH) == FSMC_MemoryDataWidth_16b))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Burst_Access_Mode
- * @{
- */
-
-#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
-#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
-#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
- ((STATE) == FSMC_BurstAccessMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_AsynchronousWait
- * @{
- */
-#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
-#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
-#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
- ((STATE) == FSMC_AsynchronousWait_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal_Polarity
- * @{
- */
-#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
-#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
-#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
- ((POLARITY) == FSMC_WaitSignalPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wrap_Mode
- * @{
- */
-#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
-#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
-#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
- ((MODE) == FSMC_WrapMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Timing
- * @{
- */
-#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
-#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
- ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Operation
- * @{
- */
-#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
-#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
-#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
- ((OPERATION) == FSMC_WriteOperation_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal
- * @{
- */
-#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
-#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
-#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
- ((SIGNAL) == FSMC_WaitSignal_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Extended_Mode
- * @{
- */
-#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
-#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
-
-#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
- ((MODE) == FSMC_ExtendedMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Burst
- * @{
- */
-
-#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
-#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
-#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
- ((BURST) == FSMC_WriteBurst_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Setup_Time
- * @{
- */
-#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Hold_Time
- * @{
- */
-#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Setup_Time
- * @{
- */
-#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Bus_Turn_around_Duration
- * @{
- */
-#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_CLK_Division
- * @{
- */
-#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Latency
- * @{
- */
-#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Access_Mode
- * @{
- */
-#define FSMC_AccessMode_A ((uint32_t)0x00000000)
-#define FSMC_AccessMode_B ((uint32_t)0x10000000)
-#define FSMC_AccessMode_C ((uint32_t)0x20000000)
-#define FSMC_AccessMode_D ((uint32_t)0x30000000)
-#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
- ((MODE) == FSMC_AccessMode_B) || \
- ((MODE) == FSMC_AccessMode_C) || \
- ((MODE) == FSMC_AccessMode_D))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_PCCARD_Controller
- * @{
- */
-
-/** @defgroup FSMC_Wait_feature
- * @{
- */
-#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
-#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
- ((FEATURE) == FSMC_Waitfeature_Enable))
-/**
- * @}
- */
-
-
-/** @defgroup FSMC_ECC
- * @{
- */
-#define FSMC_ECC_Disable ((uint32_t)0x00000000)
-#define FSMC_ECC_Enable ((uint32_t)0x00000040)
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
- ((STATE) == FSMC_ECC_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_ECC_Page_Size
- * @{
- */
-#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
-#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
-#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
-#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
-#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
-#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_8192Bytes))
-/**
- * @}
- */
-
-/** @defgroup FSMC_TCLR_Setup_Time
- * @{
- */
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_TAR_Setup_Time
- * @{
- */
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Setup_Time
- * @{
- */
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Setup_Time
- * @{
- */
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Hold_Setup_Time
- * @{
- */
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_HiZ_Setup_Time
- * @{
- */
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Interrupt_sources
- * @{
- */
-#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
-#define FSMC_IT_Level ((uint32_t)0x00000010)
-#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
-#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
- ((IT) == FSMC_IT_Level) || \
- ((IT) == FSMC_IT_FallingEdge))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Flags
- * @{
- */
-#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
-#define FSMC_FLAG_Level ((uint32_t)0x00000002)
-#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
-#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
-#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
- ((FLAG) == FSMC_FLAG_Level) || \
- ((FLAG) == FSMC_FLAG_FallingEdge) || \
- ((FLAG) == FSMC_FLAG_FEMPT))
-
-#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* NOR/SRAM Controller functions **********************************************/
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-
-/* NAND Controller functions **************************************************/
-void FSMC_NANDDeInit(uint32_t FSMC_Bank);
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
-
-/* PCCARD Controller functions ************************************************/
-void FSMC_PCCARDDeInit(void);
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_PCCARDCmd(FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_FSMC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h
deleted file mode 100644
index 0cf96c5b..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h
+++ /dev/null
@@ -1,423 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_gpio.h
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file contains all the functions prototypes for the GPIO firmware
- * library.
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_I2C_H
-#define __STM32F4xx_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief I2C Init structure definition
- */
-
-typedef struct
-{
- uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
- This parameter must be set to a value lower than 400kHz */
-
- uint16_t I2C_Mode; /*!< Specifies the I2C mode.
- This parameter can be a value of @ref I2C_mode */
-
- uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
- This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
- uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
- This parameter can be a value of @ref I2C_acknowledgement */
-
- uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
- This parameter can be a value of @ref I2C_acknowledged_address */
-}I2C_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup I2C_Exported_Constants
- * @{
- */
-
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
- ((PERIPH) == I2C2) || \
- ((PERIPH) == I2C3))
-
-/** @defgroup I2C_Digital_Filter
- * @{
- */
-
-#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
-/**
- * @}
- */
-
-
-/** @defgroup I2C_mode
- * @{
- */
-
-#define I2C_Mode_I2C ((uint16_t)0x0000)
-#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
-#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
- ((MODE) == I2C_Mode_SMBusDevice) || \
- ((MODE) == I2C_Mode_SMBusHost))
-/**
- * @}
- */
-
-/** @defgroup I2C_duty_cycle_in_fast_mode
- * @{
- */
-
-#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
-#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
- ((CYCLE) == I2C_DutyCycle_2))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledgement
- * @{
- */
-
-#define I2C_Ack_Enable ((uint16_t)0x0400)
-#define I2C_Ack_Disable ((uint16_t)0x0000)
-#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
- ((STATE) == I2C_Ack_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2C_transfer_direction
- * @{
- */
-
-#define I2C_Direction_Transmitter ((uint8_t)0x00)
-#define I2C_Direction_Receiver ((uint8_t)0x01)
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
- ((DIRECTION) == I2C_Direction_Receiver))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledged_address
- * @{
- */
-
-#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
-#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
-/**
- * @}
- */
-
-/** @defgroup I2C_registers
- * @{
- */
-
-#define I2C_Register_CR1 ((uint8_t)0x00)
-#define I2C_Register_CR2 ((uint8_t)0x04)
-#define I2C_Register_OAR1 ((uint8_t)0x08)
-#define I2C_Register_OAR2 ((uint8_t)0x0C)
-#define I2C_Register_DR ((uint8_t)0x10)
-#define I2C_Register_SR1 ((uint8_t)0x14)
-#define I2C_Register_SR2 ((uint8_t)0x18)
-#define I2C_Register_CCR ((uint8_t)0x1C)
-#define I2C_Register_TRISE ((uint8_t)0x20)
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
- ((REGISTER) == I2C_Register_CR2) || \
- ((REGISTER) == I2C_Register_OAR1) || \
- ((REGISTER) == I2C_Register_OAR2) || \
- ((REGISTER) == I2C_Register_DR) || \
- ((REGISTER) == I2C_Register_SR1) || \
- ((REGISTER) == I2C_Register_SR2) || \
- ((REGISTER) == I2C_Register_CCR) || \
- ((REGISTER) == I2C_Register_TRISE))
-/**
- * @}
- */
-
-/** @defgroup I2C_NACK_position
- * @{
- */
-
-#define I2C_NACKPosition_Next ((uint16_t)0x0800)
-#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
-#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
- ((POSITION) == I2C_NACKPosition_Current))
-/**
- * @}
- */
-
-/** @defgroup I2C_SMBus_alert_pin_level
- * @{
- */
-
-#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
-#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
-#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
- ((ALERT) == I2C_SMBusAlert_High))
-/**
- * @}
- */
-
-/** @defgroup I2C_PEC_position
- * @{
- */
-
-#define I2C_PECPosition_Next ((uint16_t)0x0800)
-#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
-#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
- ((POSITION) == I2C_PECPosition_Current))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_BUF ((uint16_t)0x0400)
-#define I2C_IT_EVT ((uint16_t)0x0200)
-#define I2C_IT_ERR ((uint16_t)0x0100)
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
-#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
-#define I2C_IT_PECERR ((uint32_t)0x01001000)
-#define I2C_IT_OVR ((uint32_t)0x01000800)
-#define I2C_IT_AF ((uint32_t)0x01000400)
-#define I2C_IT_ARLO ((uint32_t)0x01000200)
-#define I2C_IT_BERR ((uint32_t)0x01000100)
-#define I2C_IT_TXE ((uint32_t)0x06000080)
-#define I2C_IT_RXNE ((uint32_t)0x06000040)
-#define I2C_IT_STOPF ((uint32_t)0x02000010)
-#define I2C_IT_ADD10 ((uint32_t)0x02000008)
-#define I2C_IT_BTF ((uint32_t)0x02000004)
-#define I2C_IT_ADDR ((uint32_t)0x02000002)
-#define I2C_IT_SB ((uint32_t)0x02000001)
-
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
-
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
- ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
- ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
- ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
- ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_flags_definition
- * @{
- */
-
-/**
- * @brief SR2 register flags
- */
-
-#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
-#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
-#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
-#define I2C_FLAG_TRA ((uint32_t)0x00040000)
-#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
-#define I2C_FLAG_MSL ((uint32_t)0x00010000)
-
-/**
- * @brief SR1 register flags
- */
-
-#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
-#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
-#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
-#define I2C_FLAG_OVR ((uint32_t)0x10000800)
-#define I2C_FLAG_AF ((uint32_t)0x10000400)
-#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
-#define I2C_FLAG_BERR ((uint32_t)0x10000100)
-#define I2C_FLAG_TXE ((uint32_t)0x10000080)
-#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
-#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
-#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
-#define I2C_FLAG_BTF ((uint32_t)0x10000004)
-#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
-#define I2C_FLAG_SB ((uint32_t)0x10000001)
-
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
-
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
- ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
- ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
- ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
- ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
- ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
- ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
- ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
- ((FLAG) == I2C_FLAG_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_Events
- * @{
- */
-
-/**
- ===============================================================================
- I2C Master Events (Events grouped in order of communication)
- ===============================================================================
- */
-
-/**
- * @brief Communication start
- *
- * After sending the START condition (I2C_GenerateSTART() function) the master
- * has to wait for this event. It means that the Start condition has been correctly
- * released on the I2C bus (the bus is free, no other devices is communicating).
- *
- */
-/* --EV5 */
-#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
-
-/**
- * @brief Address Acknowledge
- *
- * After checking on EV5 (start condition correctly released on the bus), the
- * master sends the address of the slave(s) with which it will communicate
- * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
- * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
- * his address. If an acknowledge is sent on the bus, one of the following events will
- * be set:
- *
- * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
- * event is set.
- *
- * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
- * is set
- *
- * 3) In case of 10-Bit addressing mode, the master (just after generating the START
- * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
- * function). Then master should wait on EV9. It means that the 10-bit addressing
- * header has been correctly sent on the bus. Then master should send the second part of
- * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
- * should wait for event EV6.
- *
- */
-
-/* --EV6 */
-#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
-#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
-/* --EV9 */
-#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
-
-/**
- * @brief Communication events
- *
- * If a communication is established (START condition generated and slave address
- * acknowledged) then the master has to check on one of the following events for
- * communication procedures:
- *
- * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
- * the data received from the slave (I2C_ReceiveData() function).
- *
- * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
- * function) then to wait on event EV8 or EV8_2.
- * These two events are similar:
- * - EV8 means that the data has been written in the data register and is
- * being shifted out.
- * - EV8_2 means that the data has been physically shifted out and output
- * on the bus.
- * In most cases, using EV8 is sufficient for the application.
- * Using EV8_2 leads to a slower communication but ensure more reliable test.
- * EV8_2 is also more suitable than EV8 for testing on the last data transmission
- * (before Stop condition generation).
- *
- * @note In case the user software does not guarantee that this event EV7 is
- * managed before the current byte end of transfer, then user may check on EV7
- * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Master RECEIVER mode -----------------------------*/
-/* --EV7 */
-#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
-
-/* Master TRANSMITTER mode --------------------------*/
-/* --EV8 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
-/* --EV8_2 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
-
-
-/**
- ===============================================================================
- I2C Slave Events (Events grouped in order of communication)
- ===============================================================================
- */
-
-
-/**
- * @brief Communication start events
- *
- * Wait on one of these events at the start of the communication. It means that
- * the I2C peripheral detected a Start condition on the bus (generated by master
- * device) followed by the peripheral address. The peripheral generates an ACK
- * condition on the bus (if the acknowledge feature is enabled through function
- * I2C_AcknowledgeConfig()) and the events listed above are set :
- *
- * 1) In normal case (only one address managed by the slave), when the address
- * sent by the master matches the own address of the peripheral (configured by
- * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
- * (where XXX could be TRANSMITTER or RECEIVER).
- *
- * 2) In case the address sent by the master matches the second address of the
- * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
- * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
- * (where XXX could be TRANSMITTER or RECEIVER) are set.
- *
- * 3) In case the address sent by the master is General Call (address 0x00) and
- * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
- * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
- *
- */
-
-/* --EV1 (all the events below are variants of EV1) */
-/* 1) Case of One Single Address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
-
-/* 2) Case of Dual address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
-
-/* 3) Case of General Call enabled for the slave */
-#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
-
-/**
- * @brief Communication events
- *
- * Wait on one of these events when EV1 has already been checked and:
- *
- * - Slave RECEIVER mode:
- * - EV2: When the application is expecting a data byte to be received.
- * - EV4: When the application is expecting the end of the communication: master
- * sends a stop condition and data transmission is stopped.
- *
- * - Slave Transmitter mode:
- * - EV3: When a byte has been transmitted by the slave and the application is expecting
- * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
- * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
- * used when the user software doesn't guarantee the EV3 is managed before the
- * current byte end of transfer.
- * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
- * shall end (before sending the STOP condition). In this case slave has to stop sending
- * data bytes and expect a Stop condition on the bus.
- *
- * @note In case the user software does not guarantee that the event EV2 is
- * managed before the current byte end of transfer, then user may check on EV2
- * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Slave RECEIVER mode --------------------------*/
-/* --EV2 */
-#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
-/* --EV4 */
-#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
-
-/* Slave TRANSMITTER mode -----------------------*/
-/* --EV3 */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
-/* --EV3_2 */
-#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
-
-/*
- ===============================================================================
- End of Events Description
- ===============================================================================
- */
-
-#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
- ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
- ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
-/**
- * @}
- */
-
-/** @defgroup I2C_own_address1
- * @{
- */
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
-/**
- * @}
- */
-
-/** @defgroup I2C_clock_speed
- * @{
- */
-
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the I2C configuration to the default reset state *****/
-void I2C_DeInit(I2C_TypeDef* I2Cx);
-
-/* Initialization and Configuration functions *********************************/
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter);
-void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
-
-/* PEC management functions ***************************************************/
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
-
-/* DMA transfers management functions *****************************************/
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Interrupts, events and flags management functions **************************/
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
-
-/*
- ===============================================================================
- I2C State Monitoring Functions
- ===============================================================================
- This I2C driver provides three different ways for I2C state monitoring
- depending on the application requirements and constraints:
-
-
- 1. Basic state monitoring (Using I2C_CheckEvent() function)
- -----------------------------------------------------------
- It compares the status registers (SR1 and SR2) content to a given event
- (can be the combination of one or more flags).
- It returns SUCCESS if the current status includes the given flags
- and returns ERROR if one or more flags are missing in the current status.
-
- - When to use
- - This function is suitable for most applications as well as for startup
- activity since the events are fully described in the product reference
- manual (RM0090).
- - It is also suitable for users who need to define their own events.
-
- - Limitations
- - If an error occurs (ie. error flags are set besides to the monitored
- flags), the I2C_CheckEvent() function may return SUCCESS despite
- the communication hold or corrupted real state.
- In this case, it is advised to use error interrupts to monitor
- the error events and handle them in the interrupt IRQ handler.
-
- Note
- For error management, it is advised to use the following functions:
- - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
- Where x is the peripheral instance (I2C1, I2C2 ...)
- - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
- I2Cx_ER_IRQHandler() function in order to determine which error occurred.
- - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- and/or I2C_GenerateStop() in order to clear the error flag and source
- and return to correct communication status.
-
-
- 2. Advanced state monitoring (Using the function I2C_GetLastEvent())
- --------------------------------------------------------------------
- Using the function I2C_GetLastEvent() which returns the image of both status
- registers in a single word (uint32_t) (Status Register 2 value is shifted left
- by 16 bits and concatenated to Status Register 1).
-
- - When to use
- - This function is suitable for the same applications above but it
- allows to overcome the mentioned limitation of I2C_GetFlagStatus()
- function.
- - The returned value could be compared to events already defined in
- this file or to custom values defined by user.
- This function is suitable when multiple flags are monitored at the
- same time.
- - At the opposite of I2C_CheckEvent() function, this function allows
- user to choose when an event is accepted (when all events flags are
- set and no other flags are set or just when the needed flags are set
- like I2C_CheckEvent() function.
-
- - Limitations
- - User may need to define his own events.
- - Same remark concerning the error management is applicable for this
- function if user decides to check only regular communication flags
- (and ignores error flags).
-
-
- 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
- -----------------------------------------------------------------------
-
- Using the function I2C_GetFlagStatus() which simply returns the status of
- one single flag (ie. I2C_FLAG_RXNE ...).
-
- - When to use
- - This function could be used for specific applications or in debug
- phase.
- - It is suitable when only one flag checking is needed (most I2C
- events are monitored through multiple flags).
- - Limitations:
- - When calling this function, the Status register is accessed.
- Some flags are cleared when the status register is accessed.
- So checking the status of one Flag, may clear other ones.
- - Function may need to be called twice or more in order to monitor
- one single event.
- */
-
-/*
- ===============================================================================
- 1. Basic state monitoring
- ===============================================================================
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
-/*
- ===============================================================================
- 2. Advanced state monitoring
- ===============================================================================
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
-/*
- ===============================================================================
- 3. Flag-based state monitoring
- ===============================================================================
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-
-
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_I2C_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h
deleted file mode 100644
index e0e69661..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_iwdg.h
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file contains all the functions prototypes for the IWDG
- * firmware library.
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "misc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup MISC
- * @brief MISC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup MISC_Private_Functions
- * @{
- */
-
-/**
- * @brief Configures the priority grouping: pre-emption priority and subpriority.
- * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
- * 4 bits for subpriority
- * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
- * 3 bits for subpriority
- * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
- * 2 bits for subpriority
- * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
- * 1 bits for subpriority
- * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
- * 0 bits for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
- SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
-}
-
-/**
- * @brief Initializes the NVIC peripheral according to the specified
- * parameters in the NVIC_InitStruct.
- * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
- * function should be called before.
- * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
- * the configuration information for the specified NVIC peripheral.
- * @retval None
- */
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
- uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
- assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
-
- if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
- {
- /* Compute the Corresponding IRQ Priority --------------------------------*/
- tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
- tmppre = (0x4 - tmppriority);
- tmpsub = tmpsub >> tmppriority;
-
- tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
- tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
-
- tmppriority = tmppriority << 0x04;
-
- NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
-
- /* Enable the Selected IRQ Channels --------------------------------------*/
- NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
- else
- {
- /* Disable the Selected IRQ Channels -------------------------------------*/
- NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
-}
-
-/**
- * @brief Sets the vector table location and Offset.
- * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
- * This parameter can be one of the following values:
- * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
- * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
- * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
- * @retval None
- */
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
- assert_param(IS_NVIC_OFFSET(Offset));
-
- SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
-}
-
-/**
- * @brief Selects the condition for the system to enter low power mode.
- * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
- * This parameter can be one of the following values:
- * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
- * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
- * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
- * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_LP(LowPowerMode));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- SCB->SCR |= LowPowerMode;
- }
- else
- {
- SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
- }
-}
-
-/**
- * @brief Configures the SysTick clock source.
- * @param SysTick_CLKSource: specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
- if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
- {
- SysTick->CTRL |= SysTick_CLKSource_HCLK;
- }
- else
- {
- SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
deleted file mode 100644
index 8f6a492d..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
+++ /dev/null
@@ -1,1741 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_adc.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC) peripheral:
- * + Initialization and Configuration (in addition to ADC multi mode
- * selection)
- * + Analog Watchdog configuration
- * + Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT
- * management
- * + Regular Channels Configuration
- * + Regular Channels DMA Configuration
- * + Injected channels Configuration
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable the ADC interface clock using
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE);
-
- (#) ADC pins configuration
- (++) Enable the clock for the ADC GPIOs using the following function:
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
- (++) Configure these ADC pins in analog mode using GPIO_Init();
-
- (#) Configure the ADC Prescaler, conversion resolution and data
- alignment using the ADC_Init() function.
- (#) Activate the ADC peripheral using ADC_Cmd() function.
-
- *** Regular channels group configuration ***
- ============================================
- [..]
- (+) To configure the ADC regular channels group features, use
- ADC_Init() and ADC_RegularChannelConfig() functions.
- (+) To activate the continuous mode, use the ADC_continuousModeCmd()
- function.
- (+) To configurate and activate the Discontinuous mode, use the
- ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
- (+) To read the ADC converted values, use the ADC_GetConversionValue()
- function.
-
- *** Multi mode ADCs Regular channels configuration ***
- ======================================================
- [..]
- (+) Refer to "Regular channels group configuration" description to
- configure the ADC1, ADC2 and ADC3 regular channels.
- (+) Select the Multi mode ADC regular channels features (dual or
- triple mode) using ADC_CommonInit() function and configure
- the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd()
- functions.
- (+) Read the ADCs converted values using the
- ADC_GetMultiModeConversionValue() function.
-
- *** DMA for Regular channels group features configuration ***
- =============================================================
- [..]
- (+) To enable the DMA mode for regular channels group, use the
- ADC_DMACmd() function.
- (+) To enable the generation of DMA requests continuously at the end
- of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
- function.
-
- *** Injected channels group configuration ***
- =============================================
- [..]
- (+) To configure the ADC Injected channels group features, use
- ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()
- functions.
- (+) To activate the continuous mode, use the ADC_continuousModeCmd()
- function.
- (+) To activate the Injected Discontinuous mode, use the
- ADC_InjectedDiscModeCmd() function.
- (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
- function.
- (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue()
- function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_adc.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup ADC
- * @brief ADC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ADC DISCNUM mask */
-#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
-
-/* ADC AWDCH mask */
-#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
-
-/* ADC Analog watchdog enable mode mask */
-#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF)
-
-/* CR1 register Mask */
-#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)
-
-/* ADC EXTEN mask */
-#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF)
-
-/* ADC JEXTEN mask */
-#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)
-
-/* ADC JEXTSEL mask */
-#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)
-
-/* CR2 register Mask */
-#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)
-
-/* ADC SQx mask */
-#define SQR3_SQ_SET ((uint32_t)0x0000001F)
-#define SQR2_SQ_SET ((uint32_t)0x0000001F)
-#define SQR1_SQ_SET ((uint32_t)0x0000001F)
-
-/* ADC L Mask */
-#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF)
-
-/* ADC JSQx mask */
-#define JSQR_JSQ_SET ((uint32_t)0x0000001F)
-
-/* ADC JL mask */
-#define JSQR_JL_SET ((uint32_t)0x00300000)
-#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
-
-/* ADC SMPx mask */
-#define SMPR1_SMP_SET ((uint32_t)0x00000007)
-#define SMPR2_SMP_SET ((uint32_t)0x00000007)
-
-/* ADC JDRx registers offset */
-#define JDR_OFFSET ((uint8_t)0x28)
-
-/* ADC CDR register base address */
-#define CDR_ADDRESS ((uint32_t)0x40012308)
-
-/* ADC CCR register Mask */
-#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Functions
- * @{
- */
-
-/** @defgroup ADC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the ADC Prescaler
- (+) ADC Conversion Resolution (12bit..6bit)
- (+) Scan Conversion Mode (multichannel or one channel) for regular group
- (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for
- regular group
- (+) External trigger Edge and source of regular group,
- (+) Converted data alignment (left or right)
- (+) The number of ADC conversions that will be done using the sequencer for
- regular channel group
- (+) Multi ADC mode selection
- (+) Direct memory access mode selection for multi ADC mode
- (+) Delay between 2 sampling phases (used in dual or triple interleaved modes)
- (+) Enable or disable the ADC peripheral
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes all ADCs peripherals registers to their default reset
- * values.
- * @param None
- * @retval None
- */
-void ADC_DeInit(void)
-{
- /* Enable all ADCs reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE);
-
- /* Release all ADCs from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE);
-}
-
-/**
- * @brief Initializes the ADCx peripheral according to the specified parameters
- * in the ADC_InitStruct.
- * @note This function is used to configure the global features of the ADC (
- * Resolution and Data Alignment), however, the rest of the configuration
- * parameters are specific to the regular channels group (scan mode
- * activation, continuous mode activation, External trigger source and
- * edge, number of conversion in the regular channels group sequencer).
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
- * the configuration information for the specified ADC peripheral.
- * @retval None
- */
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
-{
- uint32_t tmpreg1 = 0;
- uint8_t tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
- assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));
- assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
- assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
- assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));
-
- /*---------------------------- ADCx CR1 Configuration -----------------*/
- /* Get the ADCx CR1 value */
- tmpreg1 = ADCx->CR1;
-
- /* Clear RES and SCAN bits */
- tmpreg1 &= CR1_CLEAR_MASK;
-
- /* Configure ADCx: scan conversion mode and resolution */
- /* Set SCAN bit according to ADC_ScanConvMode value */
- /* Set RES bit according to ADC_Resolution value */
- tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \
- ADC_InitStruct->ADC_Resolution);
- /* Write to ADCx CR1 */
- ADCx->CR1 = tmpreg1;
- /*---------------------------- ADCx CR2 Configuration -----------------*/
- /* Get the ADCx CR2 value */
- tmpreg1 = ADCx->CR2;
-
- /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
- tmpreg1 &= CR2_CLEAR_MASK;
-
- /* Configure ADCx: external trigger event and edge, data alignment and
- continuous conversion mode */
- /* Set ALIGN bit according to ADC_DataAlign value */
- /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */
- /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
- /* Set CONT bit according to ADC_ContinuousConvMode value */
- tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \
- ADC_InitStruct->ADC_ExternalTrigConv |
- ADC_InitStruct->ADC_ExternalTrigConvEdge | \
- ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
-
- /* Write to ADCx CR2 */
- ADCx->CR2 = tmpreg1;
- /*---------------------------- ADCx SQR1 Configuration -----------------*/
- /* Get the ADCx SQR1 value */
- tmpreg1 = ADCx->SQR1;
-
- /* Clear L bits */
- tmpreg1 &= SQR1_L_RESET;
-
- /* Configure ADCx: regular channel sequence length */
- /* Set L bits according to ADC_NbrOfConversion value */
- tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
- tmpreg1 |= ((uint32_t)tmpreg2 << 20);
-
- /* Write to ADCx SQR1 */
- ADCx->SQR1 = tmpreg1;
-}
-
-/**
- * @brief Fills each ADC_InitStruct member with its default value.
- * @note This function is used to initialize the global features of the ADC (
- * Resolution and Data Alignment), however, the rest of the configuration
- * parameters are specific to the regular channels group (scan mode
- * activation, continuous mode activation, External trigger source and
- * edge, number of conversion in the regular channels group sequencer).
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
-{
- /* Initialize the ADC_Mode member */
- ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
-
- /* initialize the ADC_ScanConvMode member */
- ADC_InitStruct->ADC_ScanConvMode = DISABLE;
-
- /* Initialize the ADC_ContinuousConvMode member */
- ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
-
- /* Initialize the ADC_ExternalTrigConvEdge member */
- ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
-
- /* Initialize the ADC_ExternalTrigConv member */
- ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
-
- /* Initialize the ADC_DataAlign member */
- ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
-
- /* Initialize the ADC_NbrOfConversion member */
- ADC_InitStruct->ADC_NbrOfConversion = 1;
-}
-
-/**
- * @brief Initializes the ADCs peripherals according to the specified parameters
- * in the ADC_CommonInitStruct.
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
- * that contains the configuration information for All ADCs peripherals.
- * @retval None
- */
-void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
-{
- uint32_t tmpreg1 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));
- assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
- assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
- assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
- /*---------------------------- ADC CCR Configuration -----------------*/
- /* Get the ADC CCR value */
- tmpreg1 = ADC->CCR;
-
- /* Clear MULTI, DELAY, DMA and ADCPRE bits */
- tmpreg1 &= CR_CLEAR_MASK;
-
- /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler,
- and DMA access mode for multimode */
- /* Set MULTI bits according to ADC_Mode value */
- /* Set ADCPRE bits according to ADC_Prescaler value */
- /* Set DMA bits according to ADC_DMAAccessMode value */
- /* Set DELAY bits according to ADC_TwoSamplingDelay value */
- tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode |
- ADC_CommonInitStruct->ADC_Prescaler |
- ADC_CommonInitStruct->ADC_DMAAccessMode |
- ADC_CommonInitStruct->ADC_TwoSamplingDelay);
-
- /* Write to ADC CCR */
- ADC->CCR = tmpreg1;
-}
-
-/**
- * @brief Fills each ADC_CommonInitStruct member with its default value.
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
-{
- /* Initialize the ADC_Mode member */
- ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
-
- /* initialize the ADC_Prescaler member */
- ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2;
-
- /* Initialize the ADC_DMAAccessMode member */
- ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
-
- /* Initialize the ADC_TwoSamplingDelay member */
- ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
-}
-
-/**
- * @brief Enables or disables the specified ADC peripheral.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the ADCx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the ADON bit to wake up the ADC from power down mode */
- ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;
- }
- else
- {
- /* Disable the selected ADC peripheral */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group2 Analog Watchdog configuration functions
- * @brief Analog Watchdog configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Analog Watchdog configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the Analog Watchdog
- (AWD) feature in the ADC.
-
- [..] A typical configuration Analog Watchdog is done following these steps :
- (#) the ADC guarded channel(s) is (are) selected using the
- ADC_AnalogWatchdogSingleChannelConfig() function.
- (#) The Analog watchdog lower and higher threshold are configured using the
- ADC_AnalogWatchdogThresholdsConfig() function.
- (#) The Analog watchdog is enabled and configured to enable the check, on one
- or more channels, using the ADC_AnalogWatchdogCmd() function.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the analog watchdog on single/all regular or
- * injected channels
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
- * This parameter can be one of the following values:
- * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
- * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
- * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
- * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
- * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
- * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
- * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
- * @retval None
- */
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
-
- /* Get the old register value */
- tmpreg = ADCx->CR1;
-
- /* Clear AWDEN, JAWDEN and AWDSGL bits */
- tmpreg &= CR1_AWDMode_RESET;
-
- /* Set the analog watchdog enable mode */
- tmpreg |= ADC_AnalogWatchdog;
-
- /* Store the new register value */
- ADCx->CR1 = tmpreg;
-}
-
-/**
- * @brief Configures the high and low thresholds of the analog watchdog.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param HighThreshold: the ADC analog watchdog High threshold value.
- * This parameter must be a 12-bit value.
- * @param LowThreshold: the ADC analog watchdog Low threshold value.
- * This parameter must be a 12-bit value.
- * @retval None
- */
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
- uint16_t LowThreshold)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_THRESHOLD(HighThreshold));
- assert_param(IS_ADC_THRESHOLD(LowThreshold));
-
- /* Set the ADCx high threshold */
- ADCx->HTR = HighThreshold;
-
- /* Set the ADCx low threshold */
- ADCx->LTR = LowThreshold;
-}
-
-/**
- * @brief Configures the analog watchdog guarded single channel
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @retval None
- */
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
-
- /* Get the old register value */
- tmpreg = ADCx->CR1;
-
- /* Clear the Analog watchdog channel select bits */
- tmpreg &= CR1_AWDCH_RESET;
-
- /* Set the Analog watchdog channel */
- tmpreg |= ADC_Channel;
-
- /* Store the new register value */
- ADCx->CR1 = tmpreg;
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal)
- * and VBAT (Voltage BATtery) management functions
- * @brief Temperature Sensor, Vrefint and VBAT management functions
- *
-@verbatim
- ===============================================================================
- ##### Temperature Sensor, Vrefint and VBAT management functions #####
- ===============================================================================
- [..] This section provides functions allowing to enable/ disable the internal
- connections between the ADC and the Temperature Sensor, the Vrefint and
- the Vbat sources.
-
- [..] A typical configuration to get the Temperature sensor and Vrefint channels
- voltages is done following these steps :
- (#) Enable the internal connection of Temperature sensor and Vrefint sources
- with the ADC channels using ADC_TempSensorVrefintCmd() function.
- (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using
- ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions
- (#) Get the voltage values, using ADC_GetConversionValue() or
- ADC_GetInjectedConversionValue().
-
- [..] A typical configuration to get the VBAT channel voltage is done following
- these steps :
- (#) Enable the internal connection of VBAT source with the ADC channel using
- ADC_VBATCmd() function.
- (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or
- ADC_InjectedChannelConfig() functions
- (#) Get the voltage value, using ADC_GetConversionValue() or
- ADC_GetInjectedConversionValue().
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Enables or disables the temperature sensor and Vrefint channels.
- * @param NewState: new state of the temperature sensor and Vrefint channels.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_TempSensorVrefintCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the temperature sensor and Vrefint channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;
- }
- else
- {
- /* Disable the temperature sensor and Vrefint channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);
- }
-}
-
-/**
- * @brief Enables or disables the VBAT (Voltage Battery) channel.
- * @param NewState: new state of the VBAT channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_VBATCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the VBAT channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_VBATE;
- }
- else
- {
- /* Disable the VBAT channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group4 Regular Channels Configuration functions
- * @brief Regular Channels Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Regular Channels Configuration functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to manage the ADC's regular channels,
- it is composed of 2 sub sections :
-
- (#) Configuration and management functions for regular channels: This subsection
- provides functions allowing to configure the ADC regular channels :
- (++) Configure the rank in the regular group sequencer for each channel
- (++) Configure the sampling time for each channel
- (++) select the conversion Trigger for regular channels
- (++) select the desired EOC event behavior configuration
- (++) Activate the continuous Mode (*)
- (++) Activate the Discontinuous Mode
- -@@- Please Note that the following features for regular channels
- are configurated using the ADC_Init() function :
- (+@@) scan mode activation
- (+@@) continuous mode activation (**)
- (+@@) External trigger source
- (+@@) External trigger edge
- (+@@) number of conversion in the regular channels group sequencer.
-
- -@@- (*) and (**) are performing the same configuration
-
- (#) Get the conversion data: This subsection provides an important function in
- the ADC peripheral since it returns the converted data of the current
- regular channel. When the Conversion value is read, the EOC Flag is
- automatically cleared.
-
- -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions
- results data (in the selected multi mode) can be returned in the same
- time using ADC_GetMultiModeConversionValue() function.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Configures for the selected ADC regular channel its corresponding
- * rank in the sequencer and its sample time.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @param Rank: The rank in the regular group sequencer.
- * This parameter must be between 1 to 16.
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
- * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
- * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
- * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
- * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
- * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
- * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
- * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
- * @retval None
- */
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_REGULAR_RANK(Rank));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
-
- /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
- if (ADC_Channel > ADC_Channel_9)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR1;
-
- /* Calculate the mask to clear */
- tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10));
-
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
-
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SMPR1 = tmpreg1;
- }
- else /* ADC_Channel include in ADC_Channel_[0..9] */
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR2;
-
- /* Calculate the mask to clear */
- tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
-
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
-
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SMPR2 = tmpreg1;
- }
- /* For Rank 1 to 6 */
- if (Rank < 7)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR3;
-
- /* Calculate the mask to clear */
- tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1));
-
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
-
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SQR3 = tmpreg1;
- }
- /* For Rank 7 to 12 */
- else if (Rank < 13)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR2;
-
- /* Calculate the mask to clear */
- tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7));
-
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
-
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SQR2 = tmpreg1;
- }
- /* For Rank 13 to 16 */
- else
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR1;
-
- /* Calculate the mask to clear */
- tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13));
-
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
-
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
-
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
-
- /* Store the new register value */
- ADCx->SQR1 = tmpreg1;
- }
-}
-
-/**
- * @brief Enables the selected ADC software start conversion of the regular channels.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval None
- */
-void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Enable the selected ADC conversion for regular group */
- ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;
-}
-
-/**
- * @brief Gets the selected ADC Software start regular conversion Status.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The new state of ADC software start conversion (SET or RESET).
- */
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of SWSTART bit */
- if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
- {
- /* SWSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* SWSTART bit is reset */
- bitstatus = RESET;
- }
-
- /* Return the SWSTART bit status */
- return bitstatus;
-}
-
-
-/**
- * @brief Enables or disables the EOC on each regular channel conversion
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC EOC flag rising
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC EOC rising on each regular channel conversion */
- ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS;
- }
- else
- {
- /* Disable the selected ADC EOC rising on each regular channel conversion */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS);
- }
-}
-
-/**
- * @brief Enables or disables the ADC continuous conversion mode
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC continuous conversion mode
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC continuous conversion mode */
- ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;
- }
- else
- {
- /* Disable the selected ADC continuous conversion mode */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);
- }
-}
-
-/**
- * @brief Configures the discontinuous mode for the selected ADC regular group
- * channel.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param Number: specifies the discontinuous mode regular channel count value.
- * This number must be between 1 and 8.
- * @retval None
- */
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
-
- /* Get the old register value */
- tmpreg1 = ADCx->CR1;
-
- /* Clear the old discontinuous mode channel count */
- tmpreg1 &= CR1_DISCNUM_RESET;
-
- /* Set the discontinuous mode channel count */
- tmpreg2 = Number - 1;
- tmpreg1 |= tmpreg2 << 13;
-
- /* Store the new register value */
- ADCx->CR1 = tmpreg1;
-}
-
-/**
- * @brief Enables or disables the discontinuous mode on regular group channel
- * for the specified ADC
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC discontinuous mode on
- * regular group channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC regular discontinuous mode */
- ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;
- }
- else
- {
- /* Disable the selected ADC regular discontinuous mode */
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);
- }
-}
-
-/**
- * @brief Returns the last ADCx conversion result data for regular channel.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Return the selected ADC conversion value */
- return (uint16_t) ADCx->DR;
-}
-
-/**
- * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
- * data in the selected multi mode.
- * @param None
- * @retval The Data conversion value.
- * @note In dual mode, the value returned by this function is as following
- * Data[15:0] : these bits contain the regular data of ADC1.
- * Data[31:16]: these bits contain the regular data of ADC2.
- * @note In triple mode, the value returned by this function is as following
- * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.
- * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.
- */
-uint32_t ADC_GetMultiModeConversionValue(void)
-{
- /* Return the multi mode conversion value */
- return (*(__IO uint32_t *) CDR_ADDRESS);
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
- * @brief Regular Channels DMA Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Regular Channels DMA Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the DMA for ADC
- regular channels.
- Since converted regular channel values are stored into a unique data
- register, it is useful to use DMA for conversion of more than one regular
- channel. This avoids the loss of the data already stored in the ADC
- Data register.
- When the DMA mode is enabled (using the ADC_DMACmd() function), after each
- conversion of a regular channel, a DMA request is generated.
- [..] Depending on the "DMA disable selection for Independent ADC mode"
- configuration (using the ADC_DMARequestAfterLastTransferCmd() function),
- at the end of the last DMA transfer, two possibilities are allowed:
- (+) No new DMA request is issued to the DMA controller (feature DISABLED)
- (+) Requests can continue to be generated (feature ENABLED).
- [..] Depending on the "DMA disable selection for multi ADC mode" configuration
- (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function),
- at the end of the last DMA transfer, two possibilities are allowed:
- (+) No new DMA request is issued to the DMA controller (feature DISABLED)
- (+) Requests can continue to be generated (feature ENABLED).
-
-@endverbatim
- * @{
- */
-
- /**
- * @brief Enables or disables the specified ADC DMA request.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request */
- ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;
- }
- else
- {
- /* Disable the selected ADC DMA request */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);
- }
-}
-
-/**
- * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC DMA request after last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request after last transfer */
- ADCx->CR2 |= (uint32_t)ADC_CR2_DDS;
- }
- else
- {
- /* Disable the selected ADC DMA request after last transfer */
- ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS);
- }
-}
-
-/**
- * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode
- * @param NewState: new state of the selected ADC DMA request after last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @note if Enabled, DMA requests are issued as long as data are converted and
- * DMA mode for multi ADC mode (selected using ADC_CommonInit() function
- * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is
- * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3.
- * @retval None
- */
-void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request after last transfer */
- ADC->CCR |= (uint32_t)ADC_CCR_DDS;
- }
- else
- {
- /* Disable the selected ADC DMA request after last transfer */
- ADC->CCR &= (uint32_t)(~ADC_CCR_DDS);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group6 Injected channels Configuration functions
- * @brief Injected channels Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Injected channels Configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to configure the ADC Injected channels,
- it is composed of 2 sub sections :
-
- (#) Configuration functions for Injected channels: This subsection provides
- functions allowing to configure the ADC injected channels :
- (++) Configure the rank in the injected group sequencer for each channel
- (++) Configure the sampling time for each channel
- (++) Activate the Auto injected Mode
- (++) Activate the Discontinuous Mode
- (++) scan mode activation
- (++) External/software trigger source
- (++) External trigger edge
- (++) injected channels sequencer.
-
- (#) Get the Specified Injected channel conversion data: This subsection
- provides an important function in the ADC peripheral since it returns the
- converted data of the specific injected channel.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Configures for the selected ADC injected channel its corresponding
- * rank in the sequencer and its sample time.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @param Rank: The rank in the injected group sequencer.
- * This parameter must be between 1 to 4.
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
- * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
- * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
- * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
- * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
- * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
- * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
- * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
- * @retval None
- */
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_INJECTED_RANK(Rank));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
- /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
- if (ADC_Channel > ADC_Channel_9)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR1;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10));
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR1 = tmpreg1;
- }
- else /* ADC_Channel include in ADC_Channel_[0..9] */
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR2;
- /* Calculate the mask to clear */
- tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
- /* Clear the old sample time */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
- /* Set the new sample time */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SMPR2 = tmpreg1;
- }
- /* Rank configuration */
- /* Get the old register value */
- tmpreg1 = ADCx->JSQR;
- /* Get JL value: Number = JL+1 */
- tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;
- /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
- tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
- /* Clear the old JSQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
- /* Set the JSQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->JSQR = tmpreg1;
-}
-
-/**
- * @brief Configures the sequencer length for injected channels
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param Length: The sequencer length.
- * This parameter must be a number between 1 to 4.
- * @retval None
- */
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_LENGTH(Length));
-
- /* Get the old register value */
- tmpreg1 = ADCx->JSQR;
-
- /* Clear the old injected sequence length JL bits */
- tmpreg1 &= JSQR_JL_RESET;
-
- /* Set the injected sequence length JL bits */
- tmpreg2 = Length - 1;
- tmpreg1 |= tmpreg2 << 20;
-
- /* Store the new register value */
- ADCx->JSQR = tmpreg1;
-}
-
-/**
- * @brief Set the injected channels conversion value offset
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
- * This parameter can be one of the following values:
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected
- * @param Offset: the offset value for the selected ADC injected channel
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
-{
- __IO uint32_t tmp = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
- assert_param(IS_ADC_OFFSET(Offset));
-
- tmp = (uint32_t)ADCx;
- tmp += ADC_InjectedChannel;
-
- /* Set the selected injected channel data offset */
- *(__IO uint32_t *) tmp = (uint32_t)Offset;
-}
-
- /**
- * @brief Configures the ADCx external trigger for injected channels conversion.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
- * This parameter can be one of the following values:
- * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
- * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected
- * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
- * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
- * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
- * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected
- * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected
- * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected
- * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected
- * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
- * @retval None
- */
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
-
- /* Get the old register value */
- tmpreg = ADCx->CR2;
-
- /* Clear the old external event selection for injected group */
- tmpreg &= CR2_JEXTSEL_RESET;
-
- /* Set the external event selection for injected group */
- tmpreg |= ADC_ExternalTrigInjecConv;
-
- /* Store the new register value */
- ADCx->CR2 = tmpreg;
-}
-
-/**
- * @brief Configures the ADCx external trigger edge for injected channels conversion.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge
- * to start injected conversion.
- * This parameter can be one of the following values:
- * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for
- * injected conversion
- * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge
- * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge
- * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising
- * and falling edge
- * @retval None
- */
-void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));
- /* Get the old register value */
- tmpreg = ADCx->CR2;
- /* Clear the old external trigger edge for injected group */
- tmpreg &= CR2_JEXTEN_RESET;
- /* Set the new external trigger edge for injected group */
- tmpreg |= ADC_ExternalTrigInjecConvEdge;
- /* Store the new register value */
- ADCx->CR2 = tmpreg;
-}
-
-/**
- * @brief Enables the selected ADC software start conversion of the injected channels.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval None
- */
-void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Enable the selected ADC conversion for injected group */
- ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;
-}
-
-/**
- * @brief Gets the selected ADC Software start injected conversion Status.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @retval The new state of ADC software start injected conversion (SET or RESET).
- */
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of JSWSTART bit */
- if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
- {
- /* JSWSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* JSWSTART bit is reset */
- bitstatus = RESET;
- }
- /* Return the JSWSTART bit status */
- return bitstatus;
-}
-
-/**
- * @brief Enables or disables the selected ADC automatic injected group
- * conversion after regular one.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC auto injected conversion
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC automatic injected group conversion */
- ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;
- }
- else
- {
- /* Disable the selected ADC automatic injected group conversion */
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);
- }
-}
-
-/**
- * @brief Enables or disables the discontinuous mode for injected group
- * channel for the specified ADC
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC discontinuous mode on injected
- * group channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC injected discontinuous mode */
- ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;
- }
- else
- {
- /* Disable the selected ADC injected discontinuous mode */
- ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);
- }
-}
-
-/**
- * @brief Returns the ADC injected channel conversion result
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_InjectedChannel: the converted ADC injected channel.
- * This parameter can be one of the following values:
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
-
- tmp = (uint32_t)ADCx;
- tmp += ADC_InjectedChannel + JDR_OFFSET;
-
- /* Returns the selected injected channel conversion data value */
- return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-/**
- * @}
- */
-
-/** @defgroup ADC_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the ADC Interrupts
- and to get the status and clear flags and Interrupts pending bits.
-
- [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided
- into 3 groups:
-
- *** Flags and Interrupts for ADC regular channels ***
- =====================================================
- [..]
- (+) Flags :
- (##) ADC_FLAG_OVR : Overrun detection when regular converted data are lost
-
- (##) ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate
- (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() )
- the end of:
- (+++) a regular CHANNEL conversion
- (+++) sequence of regular GROUP conversions .
-
- (##) ADC_FLAG_STRT: Regular channel start ==> to indicate when regular
- CHANNEL conversion starts.
- [..]
- (+) Interrupts :
- (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection
- event.
- (##) ADC_IT_EOC : specifies the interrupt source for Regular channel end
- of conversion event.
-
-
- *** Flags and Interrupts for ADC Injected channels ***
- ======================================================
- [..]
- (+) Flags :
- (##) ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate
- at the end of injected GROUP conversion
-
- (##) ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when
- injected GROUP conversion starts.
- [..]
- (+) Interrupts :
- (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel
- end of conversion event.
-
- *** General Flags and Interrupts for the ADC ***
- ================================================
- [..]
- (+)Flags :
- (##) ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage
- crosses the programmed thresholds values.
- [..]
- (+) Interrupts :
- (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event.
-
-
- [..] The user should identify which mode will be used in his application to
- manage the ADC controller events: Polling mode or Interrupt mode.
-
- [..] In the Polling Mode it is advised to use the following functions:
- (+) ADC_GetFlagStatus() : to check if flags events occur.
- (+) ADC_ClearFlag() : to clear the flags events.
-
- [..] In the Interrupt Mode it is advised to use the following functions:
- (+) ADC_ITConfig() : to enable or disable the interrupt source.
- (+) ADC_GetITStatus() : to check if Interrupt occurs.
- (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-@endverbatim
- * @{
- */
-/**
- * @brief Enables or disables the specified ADC interrupts.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @arg ADC_IT_OVR: Overrun interrupt enable
- * @param NewState: new state of the specified ADC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
-{
- uint32_t itmask = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_ADC_IT(ADC_IT));
-
- /* Get the ADC IT index */
- itmask = (uint8_t)ADC_IT;
- itmask = (uint32_t)0x01 << itmask;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC interrupts */
- ADCx->CR1 |= itmask;
- }
- else
- {
- /* Disable the selected ADC interrupts */
- ADCx->CR1 &= (~(uint32_t)itmask);
- }
-}
-
-/**
- * @brief Checks whether the specified ADC flag is set or not.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag
- * @arg ADC_FLAG_OVR: Overrun flag
- * @retval The new state of ADC_FLAG (SET or RESET).
- */
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
-
- /* Check the status of the specified ADC flag */
- if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
- {
- /* ADC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's pending flags.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag
- * @arg ADC_FLAG_OVR: Overrun flag
- * @retval None
- */
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
-
- /* Clear the selected ADC flags */
- ADCx->SR = ~(uint32_t)ADC_FLAG;
-}
-
-/**
- * @brief Checks whether the specified ADC interrupt has occurred or not.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @arg ADC_IT_OVR: Overrun interrupt mask
- * @retval The new state of ADC_IT (SET or RESET).
- */
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_IT(ADC_IT));
-
- /* Get the ADC IT index */
- itmask = ADC_IT >> 8;
-
- /* Get the ADC_IT enable bit status */
- enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ;
-
- /* Check the status of the specified ADC interrupt */
- if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
- {
- /* ADC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's interrupt pending bits.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg ADC_IT_EOC: End of conversion interrupt mask
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
- * @arg ADC_IT_OVR: Overrun interrupt mask
- * @retval None
- */
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
-{
- uint8_t itmask = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_IT(ADC_IT));
- /* Get the ADC IT index */
- itmask = (uint8_t)(ADC_IT >> 8);
- /* Clear the selected ADC interrupt pending bits */
- ADCx->SR = ~(uint32_t)itmask;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
deleted file mode 100644
index a54466b6..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
+++ /dev/null
@@ -1,1701 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_can.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Controller area network (CAN) peripheral:
- * + Initialization and Configuration
- * + CAN Frames Transmission
- * + CAN Frames Reception
- * + Operation modes switch
- * + Error management
- * + Interrupts and flags
- *
-@verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable the CAN controller interface clock using
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1
- and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2
- -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
-
- (#) CAN pins configuration
- (++) Enable the clock for the CAN GPIOs using the following function:
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
- (++) Connect the involved CAN pins to AF9 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx);
- (++) Configure these CAN pins in alternate function mode by calling
- the function GPIO_Init();
-
- (#) Initialise and configure the CAN using CAN_Init() and
- CAN_FilterInit() functions.
-
- (#) Transmit the desired CAN frame using CAN_Transmit() function.
-
- (#) Check the transmission of a CAN frame using CAN_TransmitStatus()
- function.
-
- (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit()
- function.
-
- (#) Receive a CAN frame using CAN_Recieve() function.
-
- (#) Release the receive FIFOs using CAN_FIFORelease() function.
-
- (#) Return the number of pending received frames using
- CAN_MessagePending() function.
-
- (#) To control CAN events you can use one of the following two methods:
- (++) Check on CAN flags using the CAN_GetFlagStatus() function.
- (++) Use CAN interrupts through the function CAN_ITConfig() at
- initialization phase and CAN_GetITStatus() function into
- interrupt routines to check if the event has occurred or not.
- After checking on a flag you should clear it using CAN_ClearFlag()
- function. And after checking on an interrupt event you should
- clear it using CAN_ClearITPendingBit() function.
-
-
-@endverbatim
-
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_crc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRC
- * @brief CRC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRC_Private_Functions
- * @{
- */
-
-/**
- * @brief Resets the CRC Data register (DR).
- * @param None
- * @retval None
- */
-void CRC_ResetDR(void)
-{
- /* Reset CRC generator */
- CRC->CR = CRC_CR_RESET;
-}
-
-/**
- * @brief Computes the 32-bit CRC of a given data word(32-bit).
- * @param Data: data word(32-bit) to compute its CRC
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcCRC(uint32_t Data)
-{
- CRC->DR = Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
- * @param pBuffer: pointer to the buffer containing the data to be computed
- * @param BufferLength: length of the buffer to be computed
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0;
-
- for(index = 0; index < BufferLength; index++)
- {
- CRC->DR = pBuffer[index];
- }
- return (CRC->DR);
-}
-
-/**
- * @brief Returns the current CRC value.
- * @param None
- * @retval 32-bit CRC
- */
-uint32_t CRC_GetCRC(void)
-{
- return (CRC->DR);
-}
-
-/**
- * @brief Stores a 8-bit data in the Independent Data(ID) register.
- * @param IDValue: 8-bit value to be stored in the ID register
- * @retval None
- */
-void CRC_SetIDRegister(uint8_t IDValue)
-{
- CRC->IDR = IDValue;
-}
-
-/**
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register
- * @param None
- * @retval 8-bit value of the ID register
- */
-uint8_t CRC_GetIDRegister(void)
-{
- return (CRC->IDR);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
deleted file mode 100644
index 824ccfbb..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
+++ /dev/null
@@ -1,934 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_cryp.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Cryptographic processor (CRYP) peripheral:
- * + Initialization and Configuration functions
- * + Data treatment functions
- * + Context swapping functions
- * + DMA interface function
- * + Interrupts and flags management
- *
-@verbatim
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable the CRYP controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
-
- (#) Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if needed
- CRYP_IVInit().
-
- (#) Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.
-
- (#) Enable the CRYP controller using the CRYP_Cmd() function.
-
- (#) If using DMA for Data input and output transfer, activate the needed DMA
- Requests using CRYP_DMACmd() function
-
- (#) If DMA is not used for data transfer, use CRYP_DataIn() and CRYP_DataOut()
- functions to enter data to IN FIFO and get result from OUT FIFO.
-
- (#) To control CRYP events you can use one of the following two methods:
- (++) Check on CRYP flags using the CRYP_GetFlagStatus() function.
- (++) Use CRYP interrupts through the function CRYP_ITConfig() at
- initialization phase and CRYP_GetITStatus() function into interrupt
- routines in processing phase.
-
- (#) Save and restore Cryptographic processor context using CRYP_SaveContext()
- and CRYP_RestoreContext() functions.
-
-
- *** Procedure to perform an encryption or a decryption ***
- ==========================================================
-
- *** Initialization ***
- ======================
- [..]
- (#) Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and CRYP_IVInit
- functions:
- (++) Configure the key size (128-, 192- or 256-bit, in the AES only)
- (++) Enter the symmetric key
- (++) Configure the data type
- (++) In case of decryption in AES-ECB or AES-CBC, you must prepare
- the key: configure the key preparation mode. Then Enable the CRYP
- peripheral using CRYP_Cmd() function: the BUSY flag is set.
- Wait until BUSY flag is reset : the key is prepared for decryption
- (++) Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the
- AES in ECB/CBC/CTR)
- (++) Configure the direction (encryption/decryption).
- (++) Write the initialization vectors (in CBC or CTR modes only)
-
- (#) Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function
-
-
- *** Basic Processing mode (polling mode) ***
- ============================================
- [..]
- (#) Enable the cryptographic processor using CRYP_Cmd() function.
-
- (#) Write the first blocks in the input FIFO (2 to 8 words) using
- CRYP_DataIn() function.
-
- (#) Repeat the following sequence until the complete message has been
- processed:
-
- (++) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus()
- function), then read the OUT-FIFO using CRYP_DataOut() function
- (1 block or until the FIFO is empty)
-
- (++) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus()
- function then write the IN FIFO using CRYP_DataIn() function
- (1 block or until the FIFO is full)
-
- (#) At the end of the processing, CRYP_FLAG_BUSY flag will be reset and
- both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is
- reset). You can disable the peripheral using CRYP_Cmd() function.
-
- *** Interrupts Processing mode ***
- ==================================
- [..] In this mode, Processing is done when the data are transferred by the
- CPU during interrupts.
-
- (#) Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using CRYP_ITConfig()
- function.
-
- (#) Enable the cryptographic processor using CRYP_Cmd() function.
-
- (#) In the CRYP_IT_INI interrupt handler : load the input message into the
- IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a
- time, or load data until the IN FIFO is full. When the last word of
- the message has been entered into the IN FIFO, disable the CRYP_IT_INI
- interrupt (using CRYP_ITConfig() function).
-
- (#) In the CRYP_IT_OUTI interrupt handler : read the output message from
- the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or
- 4 words) at a time or read data until the FIFO is empty.
- When the last word has been read, INIM=0, BUSY=0 and both FIFOs are
- empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset).
- You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig()
- function) and you can disable the peripheral using CRYP_Cmd() function.
-
- *** DMA Processing mode ***
- ===========================
- [..] In this mode, Processing is done when the DMA is used to transfer the
- data from/to the memory.
-
- (#) Configure the DMA controller to transfer the input data from the
- memory using DMA_Init() function.
- The transfer length is the length of the message.
- As message padding is not managed by the peripheral, the message
- length must be an entire number of blocks. The data are transferred
- in burst mode. The burst length is 4 words in the AES and 2 or 4
- words in the DES/TDES. The DMA should be configured to set an
- interrupt on transfer completion of the output data to indicate that
- the processing is finished.
- Refer to DMA peripheral driver for more details.
-
- (#) Enable the cryptographic processor using CRYP_Cmd() function.
- Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT
- using CRYP_DMACmd() function.
-
- (#) All the transfers and processing are managed by the DMA and the
- cryptographic processor. The DMA transfer complete interrupt indicates
- that the processing is complete. Both FIFOs are normally empty and
- CRYP_FLAG_BUSY flag is reset.
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRYP
- * @brief CRYP driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define FLAG_MASK ((uint8_t)0x20)
-#define MAX_TIMEOUT ((uint16_t)0xFFFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRYP_Private_Functions
- * @{
- */
-
-/** @defgroup CRYP_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initialize the cryptographic Processor using CRYP_Init() function
- (++) Encrypt or Decrypt
- (++) mode : TDES-ECB, TDES-CBC,
- DES-ECB, DES-CBC,
- AES-ECB, AES-CBC, AES-CTR, AES-Key, AES-GCM, AES-CCM
- (++) DataType : 32-bit data, 16-bit data, bit data or bit-string
- (++) Key Size (only in AES modes)
- (+) Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function
- (+) Configure the Initialization Vectors(IV) for CBC and CTR modes using
- CRYP_IVInit() function.
- (+) Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function.
- (+) Enable or disable the CRYP Processor using CRYP_Cmd() function
-
-@endverbatim
- * @{
- */
-/**
- * @brief Deinitializes the CRYP peripheral registers to their default reset values
- * @param None
- * @retval None
- */
-void CRYP_DeInit(void)
-{
- /* Enable CRYP reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE);
-
- /* Release CRYP from reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE);
-}
-
-/**
- * @brief Initializes the CRYP peripheral according to the specified parameters
- * in the CRYP_InitStruct.
- * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains
- * the configuration information for the CRYP peripheral.
- * @retval None
- */
-void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct)
-{
- /* Check the parameters */
- assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode));
- assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType));
- assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir));
-
- /* Select Algorithm mode*/
- CRYP->CR &= ~CRYP_CR_ALGOMODE;
- CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode;
-
- /* Select dataType */
- CRYP->CR &= ~CRYP_CR_DATATYPE;
- CRYP->CR |= CRYP_InitStruct->CRYP_DataType;
-
- /* select Key size (used only with AES algorithm) */
- if ((CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_ECB) &&
- (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_CBC) &&
- (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_ECB) &&
- (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_CBC))
- {
- assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize));
- CRYP->CR &= ~CRYP_CR_KEYSIZE;
- CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be
- configured once the key has
- been prepared */
- }
-
- /* Select data Direction */
- CRYP->CR &= ~CRYP_CR_ALGODIR;
- CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir;
-}
-
-/**
- * @brief Fills each CRYP_InitStruct member with its default value.
- * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct)
-{
- /* Initialize the CRYP_AlgoDir member */
- CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
-
- /* initialize the CRYP_AlgoMode member */
- CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
-
- /* initialize the CRYP_DataType member */
- CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b;
-
- /* Initialize the CRYP_KeySize member */
- CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b;
-}
-
-/**
- * @brief Initializes the CRYP Keys according to the specified parameters in
- * the CRYP_KeyInitStruct.
- * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that
- * contains the configuration information for the CRYP Keys.
- * @retval None
- */
-void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
-{
- /* Key Initialisation */
- CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;
- CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;
- CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;
- CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;
- CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;
- CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;
- CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
- CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
-}
-
-/**
- * @brief Fills each CRYP_KeyInitStruct member with its default value.
- * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
-{
- CRYP_KeyInitStruct->CRYP_Key0Left = 0;
- CRYP_KeyInitStruct->CRYP_Key0Right = 0;
- CRYP_KeyInitStruct->CRYP_Key1Left = 0;
- CRYP_KeyInitStruct->CRYP_Key1Right = 0;
- CRYP_KeyInitStruct->CRYP_Key2Left = 0;
- CRYP_KeyInitStruct->CRYP_Key2Right = 0;
- CRYP_KeyInitStruct->CRYP_Key3Left = 0;
- CRYP_KeyInitStruct->CRYP_Key3Right = 0;
-}
-/**
- * @brief Initializes the CRYP Initialization Vectors(IV) according to the
- * specified parameters in the CRYP_IVInitStruct.
- * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains
- * the configuration information for the CRYP Initialization Vectors(IV).
- * @retval None
- */
-void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
-{
- CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left;
- CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right;
- CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left;
- CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right;
-}
-
-/**
- * @brief Fills each CRYP_IVInitStruct member with its default value.
- * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization
- * Vectors(IV) structure which will be initialized.
- * @retval None
- */
-void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
-{
- CRYP_IVInitStruct->CRYP_IV0Left = 0;
- CRYP_IVInitStruct->CRYP_IV0Right = 0;
- CRYP_IVInitStruct->CRYP_IV1Left = 0;
- CRYP_IVInitStruct->CRYP_IV1Right = 0;
-}
-
-/**
- * @brief Configures the AES-CCM and AES-GCM phases
- * @note This function is used only with AES-CCM or AES-GCM Algorithms
- * @param CRYP_Phase: specifies the CRYP AES-CCM and AES-GCM phase to be configured.
- * This parameter can be one of the following values:
- * @arg CRYP_Phase_Init: Initialization phase
- * @arg CRYP_Phase_Header: Header phase
- * @arg CRYP_Phase_Payload: Payload phase
- * @arg CRYP_Phase_Final: Final phase
- * @retval None
- */
-void CRYP_PhaseConfig(uint32_t CRYP_Phase)
-{ uint32_t tempcr = 0;
-
- /* Check the parameter */
- assert_param(IS_CRYP_PHASE(CRYP_Phase));
-
- /* Get the CR register */
- tempcr = CRYP->CR;
-
- /* Reset the phase configuration bits: GCMP_CCMPH */
- tempcr &= (uint32_t)(~CRYP_CR_GCM_CCMPH);
- /* Set the selected phase */
- tempcr |= (uint32_t)CRYP_Phase;
-
- /* Set the CR register */
- CRYP->CR = tempcr;
-}
-
-/**
- * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the
- * FIFOs are reset)
- * @note The FIFOs must be flushed only when BUSY flag is reset.
- * @param None
- * @retval None
- */
-void CRYP_FIFOFlush(void)
-{
- /* Reset the read and write pointers of the FIFOs */
- CRYP->CR |= CRYP_CR_FFLUSH;
-}
-
-/**
- * @brief Enables or disables the CRYP peripheral.
- * @param NewState: new state of the CRYP peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRYP_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Cryptographic processor */
- CRYP->CR |= CRYP_CR_CRYPEN;
- }
- else
- {
- /* Disable the Cryptographic processor */
- CRYP->CR &= ~CRYP_CR_CRYPEN;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group2 CRYP Data processing functions
- * @brief CRYP Data processing functions
- *
-@verbatim
- ===============================================================================
- ##### CRYP Data processing functions #####
- ===============================================================================
- [..] This section provides functions allowing the encryption and decryption
- operations:
- (+) Enter data to be treated in the IN FIFO : using CRYP_DataIn() function.
- (+) Get the data result from the OUT FIFO : using CRYP_DataOut() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes data in the Data Input register (DIN).
- * @note After the DIN register has been read once or several times,
- * the FIFO must be flushed (using CRYP_FIFOFlush() function).
- * @param Data: data to write in Data Input register
- * @retval None
- */
-void CRYP_DataIn(uint32_t Data)
-{
- CRYP->DR = Data;
-}
-
-/**
- * @brief Returns the last data entered into the output FIFO.
- * @param None
- * @retval Last data entered into the output FIFO.
- */
-uint32_t CRYP_DataOut(void)
-{
- return CRYP->DOUT;
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group3 Context swapping functions
- * @brief Context swapping functions
- *
-@verbatim
- ===============================================================================
- ##### Context swapping functions #####
- ===============================================================================
- [..] This section provides functions allowing to save and store CRYP Context
-
- [..] It is possible to interrupt an encryption/ decryption/ key generation process
- to perform another processing with a higher priority, and to complete the
- interrupted process later on, when the higher-priority task is complete. To do
- so, the context of the interrupted task must be saved from the CRYP registers
- to memory, and then be restored from memory to the CRYP registers.
-
- (#) To save the current context, use CRYP_SaveContext() function
- (#) To restore the saved context, use CRYP_RestoreContext() function
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Saves the CRYP peripheral Context.
- * @note This function stops DMA transfer before to save the context. After
- * restoring the context, you have to enable the DMA again (if the DMA
- * was previously used).
- * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains
- * the repository for current context.
- * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that
- * contains the configuration information for the CRYP Keys.
- * @retval None
- */
-ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
- CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
-{
- __IO uint32_t timeout = 0;
- uint32_t ckeckmask = 0, bitstatus;
- ErrorStatus status = ERROR;
-
- /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */
- CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN;
-
- /* Wait until both the IN and OUT FIFOs are empty
- (IFEM=1 and OFNE=0 in the CRYP_SR register) and the
- BUSY bit is cleared. */
-
- if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */
- {
- ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ;
- }
- else /* AES or DES */
- {
- ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE;
- }
-
- do
- {
- bitstatus = CRYP->SR & ckeckmask;
- timeout++;
- }
- while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM));
-
- if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM)
- {
- status = ERROR;
- }
- else
- {
- /* Stop DMA transfers on the OUT FIFO by
- - writing the DOEN bit to 0 in the CRYP_DMACR register
- - and clear the CRYPEN bit. */
-
- CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN;
- CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN;
-
- /* Save the current configuration (bit 19, bit[17:16] and bits [9:2] in the CRYP_CR register) */
- CRYP_ContextSave->CR_CurrentConfig = CRYP->CR & (CRYP_CR_GCM_CCMPH |
- CRYP_CR_KEYSIZE |
- CRYP_CR_DATATYPE |
- CRYP_CR_ALGOMODE |
- CRYP_CR_ALGODIR);
-
- /* and, if not in ECB mode, the initialization vectors. */
- CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR;
- CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR;
- CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR;
- CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR;
-
- /* save The key value */
- CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;
- CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;
- CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;
- CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;
- CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;
- CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;
- CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
- CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
-
- /* Save the content of context swap registers */
- CRYP_ContextSave->CRYP_CSGCMCCMR[0] = CRYP->CSGCMCCM0R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[1] = CRYP->CSGCMCCM1R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[2] = CRYP->CSGCMCCM2R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[3] = CRYP->CSGCMCCM3R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[4] = CRYP->CSGCMCCM4R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[5] = CRYP->CSGCMCCM5R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[6] = CRYP->CSGCMCCM6R;
- CRYP_ContextSave->CRYP_CSGCMCCMR[7] = CRYP->CSGCMCCM7R;
-
- CRYP_ContextSave->CRYP_CSGCMR[0] = CRYP->CSGCM0R;
- CRYP_ContextSave->CRYP_CSGCMR[1] = CRYP->CSGCM1R;
- CRYP_ContextSave->CRYP_CSGCMR[2] = CRYP->CSGCM2R;
- CRYP_ContextSave->CRYP_CSGCMR[3] = CRYP->CSGCM3R;
- CRYP_ContextSave->CRYP_CSGCMR[4] = CRYP->CSGCM4R;
- CRYP_ContextSave->CRYP_CSGCMR[5] = CRYP->CSGCM5R;
- CRYP_ContextSave->CRYP_CSGCMR[6] = CRYP->CSGCM6R;
- CRYP_ContextSave->CRYP_CSGCMR[7] = CRYP->CSGCM7R;
-
- /* When needed, save the DMA status (pointers for IN and OUT messages,
- number of remaining bytes, etc.) */
-
- status = SUCCESS;
- }
-
- return status;
-}
-
-/**
- * @brief Restores the CRYP peripheral Context.
- * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function,
- * after restoring the context, you have to enable the DMA again (if the
- * DMA was previously used).
- * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains
- * the repository for saved context.
- * @note The data that were saved during context saving must be rewrited into
- * the IN FIFO.
- * @retval None
- */
-void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore)
-{
-
- /* Configure the processor with the saved configuration */
- CRYP->CR = CRYP_ContextRestore->CR_CurrentConfig;
-
- /* restore The key value */
- CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR;
- CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR;
- CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR;
- CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR;
- CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR;
- CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR;
- CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR;
- CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR;
-
- /* and the initialization vectors. */
- CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR;
- CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR;
- CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR;
- CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR;
-
- /* Restore the content of context swap registers */
- CRYP->CSGCMCCM0R = CRYP_ContextRestore->CRYP_CSGCMCCMR[0];
- CRYP->CSGCMCCM1R = CRYP_ContextRestore->CRYP_CSGCMCCMR[1];
- CRYP->CSGCMCCM2R = CRYP_ContextRestore->CRYP_CSGCMCCMR[2];
- CRYP->CSGCMCCM3R = CRYP_ContextRestore->CRYP_CSGCMCCMR[3];
- CRYP->CSGCMCCM4R = CRYP_ContextRestore->CRYP_CSGCMCCMR[4];
- CRYP->CSGCMCCM5R = CRYP_ContextRestore->CRYP_CSGCMCCMR[5];
- CRYP->CSGCMCCM6R = CRYP_ContextRestore->CRYP_CSGCMCCMR[6];
- CRYP->CSGCMCCM7R = CRYP_ContextRestore->CRYP_CSGCMCCMR[7];
-
- CRYP->CSGCM0R = CRYP_ContextRestore->CRYP_CSGCMR[0];
- CRYP->CSGCM1R = CRYP_ContextRestore->CRYP_CSGCMR[1];
- CRYP->CSGCM2R = CRYP_ContextRestore->CRYP_CSGCMR[2];
- CRYP->CSGCM3R = CRYP_ContextRestore->CRYP_CSGCMR[3];
- CRYP->CSGCM4R = CRYP_ContextRestore->CRYP_CSGCMR[4];
- CRYP->CSGCM5R = CRYP_ContextRestore->CRYP_CSGCMR[5];
- CRYP->CSGCM6R = CRYP_ContextRestore->CRYP_CSGCMR[6];
- CRYP->CSGCM7R = CRYP_ContextRestore->CRYP_CSGCMR[7];
-
- /* Enable the cryptographic processor */
- CRYP->CR |= CRYP_CR_CRYPEN;
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function
- * @brief CRYP's DMA interface Configuration function
- *
-@verbatim
- ===============================================================================
- ##### CRYP's DMA interface Configuration function #####
- ===============================================================================
- [..] This section provides functions allowing to configure the DMA interface for
- CRYP data input and output transfer.
-
- [..] When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be
- transferred:
- (+) From memory to the CRYP IN FIFO using the DMA peripheral by enabling
- the CRYP_DMAReq_DataIN request.
- (+) From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling
- the CRYP_DMAReq_DataOUT request.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the CRYP DMA interface.
- * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer
- * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer
- * @param NewState: new state of the selected CRYP DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CRYP DMA request */
- CRYP->DMACR |= CRYP_DMAReq;
- }
- else
- {
- /* Disable the selected CRYP DMA request */
- CRYP->DMACR &= (uint8_t)~CRYP_DMAReq;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup CRYP_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the CRYP Interrupts and
- to get the status and Interrupts pending bits.
-
- [..] The CRYP provides 2 Interrupts sources and 7 Flags:
-
- *** Flags : ***
- ===============
- [..]
- (#) CRYP_FLAG_IFEM : Set when Input FIFO is empty. This Flag is cleared only
- by hardware.
-
- (#) CRYP_FLAG_IFNF : Set when Input FIFO is not full. This Flag is cleared
- only by hardware.
-
-
- (#) CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending it gives
- the raw interrupt state prior to masking of the input FIFO service interrupt.
- This Flag is cleared only by hardware.
-
- (#) CRYP_FLAG_OFNE : Set when Output FIFO not empty. This Flag is cleared
- only by hardware.
-
- (#) CRYP_FLAG_OFFU : Set when Output FIFO is full. This Flag is cleared only
- by hardware.
-
- (#) CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending it gives
- the raw interrupt state prior to masking of the output FIFO service interrupt.
- This Flag is cleared only by hardware.
-
- (#) CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a block
- of data or a key preparation (for AES decryption). This Flag is cleared
- only by hardware. To clear it, the CRYP core must be disabled and the last
- processing has completed.
-
- *** Interrupts : ***
- ====================
- [..]
- (#) CRYP_IT_INI : The input FIFO service interrupt is asserted when there
- are less than 4 words in the input FIFO. This interrupt is associated to
- CRYP_FLAG_INRIS flag.
-
- -@- This interrupt is cleared by performing write operations to the input FIFO
- until it holds 4 or more words. The input FIFO service interrupt INMIS is
- enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the
- INMIS signal is low even if the input FIFO is empty.
-
-
-
- (#) CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there
- is one or more (32-bit word) data items in the output FIFO. This interrupt
- is associated to CRYP_FLAG_OUTRIS flag.
-
- -@- This interrupt is cleared by reading data from the output FIFO until there
- is no valid (32-bit) word left (that is, the interrupt follows the state
- of the OFNE (output FIFO not empty) flag).
-
- *** Managing the CRYP controller events : ***
- =============================================
- [..] The user should identify which mode will be used in his application to manage
- the CRYP controller events: Polling mode or Interrupt mode.
-
- (#) In the Polling Mode it is advised to use the following functions:
- (++) CRYP_GetFlagStatus() : to check if flags events occur.
-
- -@@- The CRYPT flags do not need to be cleared since they are cleared as
- soon as the associated event are reset.
-
-
- (#) In the Interrupt Mode it is advised to use the following functions:
- (++) CRYP_ITConfig() : to enable or disable the interrupt source.
- (++) CRYP_GetITStatus() : to check if Interrupt occurs.
-
- -@@- The CRYPT interrupts have no pending bits, the interrupt is cleared as
- soon as the associated event is reset.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified CRYP interrupts.
- * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg CRYP_IT_INI: Input FIFO interrupt
- * @arg CRYP_IT_OUTI: Output FIFO interrupt
- * @param NewState: new state of the specified CRYP interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CRYP_CONFIG_IT(CRYP_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CRYP interrupt */
- CRYP->IMSCR |= CRYP_IT;
- }
- else
- {
- /* Disable the selected CRYP interrupt */
- CRYP->IMSCR &= (uint8_t)~CRYP_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified CRYP interrupt has occurred or not.
- * @note This function checks the status of the masked interrupt (i.e the
- * interrupt should be previously enabled).
- * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CRYP_IT_INI: Input FIFO interrupt
- * @arg CRYP_IT_OUTI: Output FIFO interrupt
- * @retval The new state of CRYP_IT (SET or RESET).
- */
-ITStatus CRYP_GetITStatus(uint8_t CRYP_IT)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_CRYP_GET_IT(CRYP_IT));
-
- /* Check the status of the specified CRYP interrupt */
- if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET)
- {
- /* CRYP_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* CRYP_IT is reset */
- bitstatus = RESET;
- }
- /* Return the CRYP_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Returns whether CRYP peripheral is enabled or disabled.
- * @param none.
- * @retval Current state of the CRYP peripheral (ENABLE or DISABLE).
- */
-FunctionalState CRYP_GetCmdStatus(void)
-{
- FunctionalState state = DISABLE;
-
- if ((CRYP->CR & CRYP_CR_CRYPEN) != 0)
- {
- /* CRYPEN bit is set */
- state = ENABLE;
- }
- else
- {
- /* CRYPEN bit is reset */
- state = DISABLE;
- }
- return state;
-}
-
-/**
- * @brief Checks whether the specified CRYP flag is set or not.
- * @param CRYP_FLAG: specifies the CRYP flag to check.
- * This parameter can be one of the following values:
- * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag.
- * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag.
- * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag.
- * @arg CRYP_FLAG_OFFU: Output FIFO Full flag.
- * @arg CRYP_FLAG_BUSY: Busy flag.
- * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag.
- * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag.
- * @retval The new state of CRYP_FLAG (SET or RESET).
- */
-FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tempreg = 0;
-
- /* Check the parameters */
- assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG));
-
- /* check if the FLAG is in RISR register */
- if ((CRYP_FLAG & FLAG_MASK) != 0x00)
- {
- tempreg = CRYP->RISR;
- }
- else /* The FLAG is in SR register */
- {
- tempreg = CRYP->SR;
- }
-
-
- /* Check the status of the specified CRYP flag */
- if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET)
- {
- /* CRYP_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CRYP_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the CRYP_FLAG status */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
deleted file mode 100644
index 4c5920b5..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
+++ /dev/null
@@ -1,1676 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_cryp_aes.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides high level functions to encrypt and decrypt an
- * input message using AES in ECB/CBC/CTR/GCM/CCM modes.
- * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
- * peripheral.
- * AES-ECB/CBC/CTR/GCM/CCM modes are available on STM32F437x Devices.
- * For STM32F41xx Devices, only AES-ECB/CBC/CTR modes are available.
- *
-@verbatim
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable The CRYP controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
-
- (#) Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() function.
-
- (#) Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() function.
-
- (#) Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() function.
-
- (#) Encrypt and decrypt using AES in GCM Mode using CRYP_AES_GCM() function.
-
- (#) Encrypt and decrypt using AES in CCM Mode using CRYP_AES_CCM() function.
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dbgmcu.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DBGMCU
- * @brief DBGMCU driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Private_Functions
- * @{
- */
-
-/**
- * @brief Returns the device revision identifier.
- * @param None
- * @retval Device revision identifier
- */
-uint32_t DBGMCU_GetREVID(void)
-{
- return(DBGMCU->IDCODE >> 16);
-}
-
-/**
- * @brief Returns the device identifier.
- * @param None
- * @retval Device identifier
- */
-uint32_t DBGMCU_GetDEVID(void)
-{
- return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
-}
-
-/**
- * @brief Configures low power mode behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the low power mode.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
- * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
- * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
- * @param NewState: new state of the specified low power mode in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- DBGMCU->CR |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->CR &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB1 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
- * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
- * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
- * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
- * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
- * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
- * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
- * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
- * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
- * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted.
- * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
- * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
- * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
- * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted
- * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB1FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB1FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB2 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
- * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
- * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
- * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
- * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
- * @param NewState: new state of the specified peripheral in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB2FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB2FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
deleted file mode 100644
index d6eef0b9..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
+++ /dev/null
@@ -1,538 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dcmi.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the DCMI peripheral:
- * + Initialization and Configuration
- * + Image capture functions
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The sequence below describes how to use this driver to capture image
- from a camera module connected to the DCMI Interface.
- This sequence does not take into account the configuration of the
- camera module, which should be made before to configure and enable
- the DCMI to capture images.
-
- (#) Enable the clock for the DCMI and associated GPIOs using the following
- functions:
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) DCMI pins configuration
- (++) Connect the involved DCMI pins to AF13 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI);
- (++) Configure these DCMI pins in alternate function mode by calling
- the function GPIO_Init();
-
- (#) Declare a DCMI_InitTypeDef structure, for example:
- DCMI_InitTypeDef DCMI_InitStructure;
- and fill the DCMI_InitStructure variable with the allowed values
- of the structure member.
-
- (#) Initialize the DCMI interface by calling the function
- DCMI_Init(&DCMI_InitStructure);
-
- (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
- register to the destination memory buffer.
-
- (#) Enable DCMI interface using the function
- DCMI_Cmd(ENABLE);
-
- (#) Start the image capture using the function
- DCMI_CaptureCmd(ENABLE);
-
- (#) At this stage the DCMI interface waits for the first start of frame,
- then a DMA request is generated continuously/once (depending on the
- mode used, Continuous/Snapshot) to transfer the received data into
- the destination memory.
-
- -@- If you need to capture only a rectangular window from the received
- image, you have to use the DCMI_CROPConfig() function to configure
- the coordinates and size of the window to be captured, then enable
- the Crop feature using DCMI_CROPCmd(ENABLE);
- In this case, the Crop configuration should be made before to enable
- and start the DCMI interface.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DCMI
- * @brief DCMI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DCMI_Private_Functions
- * @{
- */
-
-/** @defgroup DCMI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the DCMI registers to their default reset values.
- * @param None
- * @retval None
- */
-void DCMI_DeInit(void)
-{
- DCMI->CR = 0x0;
- DCMI->IER = 0x0;
- DCMI->ICR = 0x1F;
- DCMI->ESCR = 0x0;
- DCMI->ESUR = 0x0;
- DCMI->CWSTRTR = 0x0;
- DCMI->CWSIZER = 0x0;
-}
-
-/**
- * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct.
- * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains
- * the configuration information for the DCMI.
- * @retval None
- */
-void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct)
-{
- uint32_t temp = 0x0;
-
- /* Check the parameters */
- assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode));
- assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode));
- assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity));
- assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity));
- assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity));
- assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate));
- assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode));
-
- /* The DCMI configuration registers should be programmed correctly before
- enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */
- DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE);
-
- /* Reset the old DCMI configuration */
- temp = DCMI->CR;
-
- temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL |
- DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 |
- DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1);
-
- /* Sets the new configuration of the DCMI peripheral */
- temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode |
- DCMI_InitStruct->DCMI_SynchroMode |
- DCMI_InitStruct->DCMI_PCKPolarity |
- DCMI_InitStruct->DCMI_VSPolarity |
- DCMI_InitStruct->DCMI_HSPolarity |
- DCMI_InitStruct->DCMI_CaptureRate |
- DCMI_InitStruct->DCMI_ExtendedDataMode);
-
- DCMI->CR = temp;
-}
-
-/**
- * @brief Fills each DCMI_InitStruct member with its default value.
- * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct)
-{
- /* Set the default configuration */
- DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous;
- DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware;
- DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling;
- DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low;
- DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low;
- DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame;
- DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b;
-}
-
-/**
- * @brief Initializes the DCMI peripheral CROP mode according to the specified
- * parameters in the DCMI_CROPInitStruct.
- * @note This function should be called before to enable and start the DCMI interface.
- * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that
- * contains the configuration information for the DCMI peripheral CROP mode.
- * @retval None
- */
-void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct)
-{
- /* Sets the CROP window coordinates */
- DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount |
- ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16));
-
- /* Sets the CROP window size */
- DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount |
- ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16));
-}
-
-/**
- * @brief Enables or disables the DCMI Crop feature.
- * @note This function should be called before to enable and start the DCMI interface.
- * @param NewState: new state of the DCMI Crop feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_CROPCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI Crop feature */
- DCMI->CR |= (uint32_t)DCMI_CR_CROP;
- }
- else
- {
- /* Disable the DCMI Crop feature */
- DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;
- }
-}
-
-/**
- * @brief Sets the embedded synchronization codes
- * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that
- * contains the embedded synchronization codes for the DCMI peripheral.
- * @retval None
- */
-void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct)
-{
- DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode |
- ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)|
- ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)|
- ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24));
-}
-
-/**
- * @brief Enables or disables the DCMI JPEG format.
- * @note The Crop and Embedded Synchronization features cannot be used in this mode.
- * @param NewState: new state of the DCMI JPEG format.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_JPEGCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI JPEG format */
- DCMI->CR |= (uint32_t)DCMI_CR_JPEG;
- }
- else
- {
- /* Disable the DCMI JPEG format */
- DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup DCMI_Group2 Image capture functions
- * @brief Image capture functions
- *
-@verbatim
- ===============================================================================
- ##### Image capture functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the DCMI interface.
- * @param NewState: new state of the DCMI interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI by setting ENABLE bit */
- DCMI->CR |= (uint32_t)DCMI_CR_ENABLE;
- }
- else
- {
- /* Disable the DCMI by clearing ENABLE bit */
- DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE;
- }
-}
-
-/**
- * @brief Enables or disables the DCMI Capture.
- * @param NewState: new state of the DCMI capture.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_CaptureCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DCMI Capture */
- DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE;
- }
- else
- {
- /* Disable the DCMI Capture */
- DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE;
- }
-}
-
-/**
- * @brief Reads the data stored in the DR register.
- * @param None
- * @retval Data register value
- */
-uint32_t DCMI_ReadData(void)
-{
- return DCMI->DR;
-}
-/**
- * @}
- */
-
-/** @defgroup DCMI_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the DCMI interface interrupts.
- * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @param NewState: new state of the specified DCMI interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DCMI_CONFIG_IT(DCMI_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- DCMI->IER |= DCMI_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- DCMI->IER &= (uint16_t)(~DCMI_IT);
- }
-}
-
-/**
- * @brief Checks whether the DCMI interface flag is set or not.
- * @param DCMI_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
- * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
- * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
- * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
- * @arg DCMI_FLAG_LINERI: Line Raw flag mask
- * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask
- * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask
- * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask
- * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask
- * @arg DCMI_FLAG_LINEMI: Line Masked flag mask
- * @arg DCMI_FLAG_HSYNC: HSYNC flag mask
- * @arg DCMI_FLAG_VSYNC: VSYNC flag mask
- * @arg DCMI_FLAG_FNE: Fifo not empty flag mask
- * @retval The new state of DCMI_FLAG (SET or RESET).
- */
-FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t dcmireg, tempreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG));
-
- /* Get the DCMI register index */
- dcmireg = (((uint16_t)DCMI_FLAG) >> 12);
-
- if (dcmireg == 0x00) /* The FLAG is in RISR register */
- {
- tempreg= DCMI->RISR;
- }
- else if (dcmireg == 0x02) /* The FLAG is in SR register */
- {
- tempreg = DCMI->SR;
- }
- else /* The FLAG is in MISR register */
- {
- tempreg = DCMI->MISR;
- }
-
- if ((tempreg & DCMI_FLAG) != (uint16_t)RESET )
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the DCMI_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DCMI's pending flags.
- * @param DCMI_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
- * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
- * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
- * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
- * @arg DCMI_FLAG_LINERI: Line Raw flag mask
- * @retval None
- */
-void DCMI_ClearFlag(uint16_t DCMI_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG));
-
- /* Clear the flag by writing in the ICR register 1 in the corresponding
- Flag position*/
-
- DCMI->ICR = DCMI_FLAG;
-}
-
-/**
- * @brief Checks whether the DCMI interrupt has occurred or not.
- * @param DCMI_IT: specifies the DCMI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval The new state of DCMI_IT (SET or RESET).
- */
-ITStatus DCMI_GetITStatus(uint16_t DCMI_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t itstatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DCMI_GET_IT(DCMI_IT));
-
- itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */
-
- if ((itstatus != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the DCMI's interrupt pending bits.
- * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval None
- */
-void DCMI_ClearITPendingBit(uint16_t DCMI_IT)
-{
- /* Clear the interrupt pending Bit by writing in the ICR register 1 in the
- corresponding pending Bit position*/
-
- DCMI->ICR = DCMI_IT;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
deleted file mode 100644
index 1678c17d..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
+++ /dev/null
@@ -1,1301 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_dma.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Direct Memory Access controller (DMA):
- * + Initialization and Configuration
- * + Data Counter
- * + Double Buffer mode configuration and command
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE)
- function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE)
- function for DMA2.
-
- (#) Enable and configure the peripheral to be connected to the DMA Stream
- (except for internal SRAM / FLASH memories: no initialization is
- necessary).
-
- (#) For a given Stream, program the required configuration through following parameters:
- Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination
- data formats, Circular or Normal mode, Stream Priority level, Source and Destination
- Incrementation mode, FIFO mode and its Threshold (if needed), Burst
- mode for Source and/or Destination (if needed) using the DMA_Init() function.
- To avoid filling unneccessary fields, you can call DMA_StructInit() function
- to initialize a given structure with default values (reset values), the modify
- only necessary fields
- (ie. Source and Destination addresses, Transfer size and Data Formats).
-
- (#) Enable the NVIC and the corresponding interrupt(s) using the function
- DMA_ITConfig() if you need to use DMA interrupts.
-
- (#) Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring
- the second Memory address and the first Memory to be used through the function
- DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function
- DMA_DoubleBufferModeCmd(). These operations must be done before step 6.
-
- (#) Enable the DMA stream using the DMA_Cmd() function.
-
- (#) Activate the needed Stream Request using PPP_DMACmd() function for
- any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
- The function allowing this operation is provided in each PPP peripheral
- driver (ie. SPI_DMACmd for SPI peripheral).
- Once the Stream is enabled, it is not possible to modify its configuration
- unless the stream is stopped and disabled.
- After enabling the Stream, it is advised to monitor the EN bit status using
- the function DMA_GetCmdStatus(). In case of configuration errors or bus errors
- this bit will remain reset and all transfers on this Stream will remain on hold.
-
- (#) Optionally, you can configure the number of data to be transferred
- when the Stream is disabled (ie. after each Transfer Complete event
- or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
- And you can get the number of remaining data to be transferred using
- the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is
- enabled and running).
-
- (#) To control DMA events you can use one of the following two methods:
- (##) Check on DMA Stream flags using the function DMA_GetFlagStatus().
- (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
- phase and DMA_GetITStatus() function into interrupt routines in
- communication phase.
- [..]
- After checking on a flag you should clear it using DMA_ClearFlag()
- function. And after checking on an interrupt event you should
- clear it using DMA_ClearITPendingBit() function.
-
- (#) Optionally, if Circular mode and Double Buffer mode are enabled, you can modify
- the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that
- the Memory Address to be modified is not the one currently in use by DMA Stream.
- This condition can be monitored using the function DMA_GetCurrentMemoryTarget().
-
- (#) Optionally, Pause-Resume operations may be performed:
- The DMA_Cmd() function may be used to perform Pause-Resume operation.
- When a transfer is ongoing, calling this function to disable the
- Stream will cause the transfer to be paused. All configuration registers
- and the number of remaining data will be preserved. When calling again
- this function to re-enable the Stream, the transfer will be resumed from
- the point where it was paused.
-
- -@- Memory-to-Memory transfer is possible by setting the address of the memory into
- the Peripheral registers. In this mode, Circular mode and Double Buffer mode
- are not allowed.
-
- -@- The FIFO is used mainly to reduce bus usage and to allow data
- packing/unpacking: it is possible to set different Data Sizes for
- the Peripheral and the Memory (ie. you can set Half-Word data size
- for the peripheral to access its data register and set Word data size
- for the Memory to gain in access time. Each two Half-words will be
- packed and written in a single access to a Word in the Memory).
-
- -@- When FIFO is disabled, it is not allowed to configure different
- Data Sizes for Source and Destination. In this case the Peripheral
- Data Size will be applied to both Source and Destination.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_dma.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DMA
- * @brief DMA driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Masks Definition */
-#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \
- DMA_SxCR_TEIE | DMA_SxCR_DMEIE)
-
-#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \
- DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \
- DMA_LISR_TCIF0)
-
-#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6)
-#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16)
-#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22)
-#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000)
-#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000)
-#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000)
-#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000)
-#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C
-#define HIGH_ISR_MASK (uint32_t)0x20000000
-#define RESERVED_MASK (uint32_t)0x0F7D0F7D
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-
-/** @defgroup DMA_Private_Functions
- * @{
- */
-
-/** @defgroup DMA_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to initialize the DMA Stream source
- and destination addresses, incrementation and data sizes, transfer direction,
- buffer size, circular/normal mode selection, memory-to-memory mode selection
- and Stream priority value.
- [..]
- The DMA_Init() function follows the DMA configuration procedures as described in
- reference manual (RM0090) except the first point: waiting on EN bit to be reset.
- This condition should be checked by user application using the function DMA_GetCmdStatus()
- before calling the DMA_Init() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitialize the DMAy Streamx registers to their default reset values.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval None
- */
-void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Disable the selected DMAy Streamx */
- DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN);
-
- /* Reset DMAy Streamx control register */
- DMAy_Streamx->CR = 0;
-
- /* Reset DMAy Streamx Number of Data to Transfer register */
- DMAy_Streamx->NDTR = 0;
-
- /* Reset DMAy Streamx peripheral address register */
- DMAy_Streamx->PAR = 0;
-
- /* Reset DMAy Streamx memory 0 address register */
- DMAy_Streamx->M0AR = 0;
-
- /* Reset DMAy Streamx memory 1 address register */
- DMAy_Streamx->M1AR = 0;
-
- /* Reset DMAy Streamx FIFO control register */
- DMAy_Streamx->FCR = (uint32_t)0x00000021;
-
- /* Reset interrupt pending bits for the selected stream */
- if (DMAy_Streamx == DMA1_Stream0)
- {
- /* Reset interrupt pending bits for DMA1 Stream0 */
- DMA1->LIFCR = DMA_Stream0_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream1)
- {
- /* Reset interrupt pending bits for DMA1 Stream1 */
- DMA1->LIFCR = DMA_Stream1_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream2)
- {
- /* Reset interrupt pending bits for DMA1 Stream2 */
- DMA1->LIFCR = DMA_Stream2_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream3)
- {
- /* Reset interrupt pending bits for DMA1 Stream3 */
- DMA1->LIFCR = DMA_Stream3_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream4)
- {
- /* Reset interrupt pending bits for DMA1 Stream4 */
- DMA1->HIFCR = DMA_Stream4_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream5)
- {
- /* Reset interrupt pending bits for DMA1 Stream5 */
- DMA1->HIFCR = DMA_Stream5_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream6)
- {
- /* Reset interrupt pending bits for DMA1 Stream6 */
- DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK;
- }
- else if (DMAy_Streamx == DMA1_Stream7)
- {
- /* Reset interrupt pending bits for DMA1 Stream7 */
- DMA1->HIFCR = DMA_Stream7_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream0)
- {
- /* Reset interrupt pending bits for DMA2 Stream0 */
- DMA2->LIFCR = DMA_Stream0_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream1)
- {
- /* Reset interrupt pending bits for DMA2 Stream1 */
- DMA2->LIFCR = DMA_Stream1_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream2)
- {
- /* Reset interrupt pending bits for DMA2 Stream2 */
- DMA2->LIFCR = DMA_Stream2_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream3)
- {
- /* Reset interrupt pending bits for DMA2 Stream3 */
- DMA2->LIFCR = DMA_Stream3_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream4)
- {
- /* Reset interrupt pending bits for DMA2 Stream4 */
- DMA2->HIFCR = DMA_Stream4_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream5)
- {
- /* Reset interrupt pending bits for DMA2 Stream5 */
- DMA2->HIFCR = DMA_Stream5_IT_MASK;
- }
- else if (DMAy_Streamx == DMA2_Stream6)
- {
- /* Reset interrupt pending bits for DMA2 Stream6 */
- DMA2->HIFCR = DMA_Stream6_IT_MASK;
- }
- else
- {
- if (DMAy_Streamx == DMA2_Stream7)
- {
- /* Reset interrupt pending bits for DMA2 Stream7 */
- DMA2->HIFCR = DMA_Stream7_IT_MASK;
- }
- }
-}
-
-/**
- * @brief Initializes the DMAy Streamx according to the specified parameters in
- * the DMA_InitStruct structure.
- * @note Before calling this function, it is recommended to check that the Stream
- * is actually disabled using the function DMA_GetCmdStatus().
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval None
- */
-void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel));
- assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR));
- assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
- assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode));
- assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold));
- assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst));
- assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst));
-
- /*------------------------- DMAy Streamx CR Configuration ------------------*/
- /* Get the DMAy_Streamx CR value */
- tmpreg = DMAy_Streamx->CR;
-
- /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
- tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
- DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
- DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
- DMA_SxCR_DIR));
-
- /* Configure DMAy Streamx: */
- /* Set CHSEL bits according to DMA_CHSEL value */
- /* Set DIR bits according to DMA_DIR value */
- /* Set PINC bit according to DMA_PeripheralInc value */
- /* Set MINC bit according to DMA_MemoryInc value */
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */
- /* Set MSIZE bits according to DMA_MemoryDataSize value */
- /* Set CIRC bit according to DMA_Mode value */
- /* Set PL bits according to DMA_Priority value */
- /* Set MBURST bits according to DMA_MemoryBurst value */
- /* Set PBURST bits according to DMA_PeripheralBurst value */
- tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR |
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
- DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority |
- DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst;
-
- /* Write to DMAy Streamx CR register */
- DMAy_Streamx->CR = tmpreg;
-
- /*------------------------- DMAy Streamx FCR Configuration -----------------*/
- /* Get the DMAy_Streamx FCR value */
- tmpreg = DMAy_Streamx->FCR;
-
- /* Clear DMDIS and FTH bits */
- tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
-
- /* Configure DMAy Streamx FIFO:
- Set DMDIS bits according to DMA_FIFOMode value
- Set FTH bits according to DMA_FIFOThreshold value */
- tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold;
-
- /* Write to DMAy Streamx CR */
- DMAy_Streamx->FCR = tmpreg;
-
- /*------------------------- DMAy Streamx NDTR Configuration ----------------*/
- /* Write to DMAy Streamx NDTR register */
- DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize;
-
- /*------------------------- DMAy Streamx PAR Configuration -----------------*/
- /* Write to DMAy Streamx PAR */
- DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
-
- /*------------------------- DMAy Streamx M0AR Configuration ----------------*/
- /* Write to DMAy Streamx M0AR */
- DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr;
-}
-
-/**
- * @brief Fills each DMA_InitStruct member with its default value.
- * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
-{
- /*-------------- Reset DMA init structure parameters values ----------------*/
- /* Initialize the DMA_Channel member */
- DMA_InitStruct->DMA_Channel = 0;
-
- /* Initialize the DMA_PeripheralBaseAddr member */
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
-
- /* Initialize the DMA_Memory0BaseAddr member */
- DMA_InitStruct->DMA_Memory0BaseAddr = 0;
-
- /* Initialize the DMA_DIR member */
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory;
-
- /* Initialize the DMA_BufferSize member */
- DMA_InitStruct->DMA_BufferSize = 0;
-
- /* Initialize the DMA_PeripheralInc member */
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-
- /* Initialize the DMA_MemoryInc member */
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
-
- /* Initialize the DMA_PeripheralDataSize member */
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-
- /* Initialize the DMA_MemoryDataSize member */
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-
- /* Initialize the DMA_Mode member */
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
-
- /* Initialize the DMA_Priority member */
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
-
- /* Initialize the DMA_FIFOMode member */
- DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable;
-
- /* Initialize the DMA_FIFOThreshold member */
- DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
-
- /* Initialize the DMA_MemoryBurst member */
- DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single;
-
- /* Initialize the DMA_PeripheralBurst member */
- DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
-}
-
-/**
- * @brief Enables or disables the specified DMAy Streamx.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param NewState: new state of the DMAy Streamx.
- * This parameter can be: ENABLE or DISABLE.
- *
- * @note This function may be used to perform Pause-Resume operation. When a
- * transfer is ongoing, calling this function to disable the Stream will
- * cause the transfer to be paused. All configuration registers and the
- * number of remaining data will be preserved. When calling again this
- * function to re-enable the Stream, the transfer will be resumed from
- * the point where it was paused.
- *
- * @note After configuring the DMA Stream (DMA_Init() function) and enabling the
- * stream, it is recommended to check (or wait until) the DMA Stream is
- * effectively enabled. A Stream may remain disabled if a configuration
- * parameter is wrong.
- * After disabling a DMA Stream, it is also recommended to check (or wait
- * until) the DMA Stream is effectively disabled. If a Stream is disabled
- * while a data transfer is ongoing, the current data will be transferred
- * and the Stream will be effectively disabled only after the transfer of
- * this single data is finished.
- *
- * @retval None
- */
-void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMAy Streamx by setting EN bit */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN;
- }
- else
- {
- /* Disable the selected DMAy Streamx by clearing EN bit */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN;
- }
-}
-
-/**
- * @brief Configures, when the PINC (Peripheral Increment address mode) bit is
- * set, if the peripheral address should be incremented with the data
- * size (configured with PSIZE bits) or by a fixed offset equal to 4
- * (32-bit aligned addresses).
- *
- * @note This function has no effect if the Peripheral Increment mode is disabled.
- *
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_Pincos: specifies the Peripheral increment offset size.
- * This parameter can be one of the following values:
- * @arg DMA_PINCOS_Psize: Peripheral address increment is done
- * accordingly to PSIZE parameter.
- * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is
- * fixed to 4 (32-bit aligned addresses).
- * @retval None
- */
-void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos));
-
- /* Check the needed Peripheral increment offset */
- if(DMA_Pincos != DMA_PINCOS_Psize)
- {
- /* Configure DMA_SxCR_PINCOS bit with the input parameter */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS;
- }
- else
- {
- /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS;
- }
-}
-
-/**
- * @brief Configures, when the DMAy Streamx is disabled, the flow controller for
- * the next transactions (Peripheral or Memory).
- *
- * @note Before enabling this feature, check if the used peripheral supports
- * the Flow Controller mode or not.
- *
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_FlowCtrl: specifies the DMA flow controller.
- * This parameter can be one of the following values:
- * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is
- * the DMA controller.
- * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller
- * is the peripheral.
- * @retval None
- */
-void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl));
-
- /* Check the needed flow controller */
- if(DMA_FlowCtrl != DMA_FlowCtrl_Memory)
- {
- /* Configure DMA_SxCR_PFCTRL bit with the input parameter */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL;
- }
- else
- {
- /* Clear the PFCTRL bit: Memory is the flow controller */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup DMA_Group2 Data Counter functions
- * @brief Data Counter functions
- *
-@verbatim
- ===============================================================================
- ##### Data Counter functions #####
- ===============================================================================
- [..]
- This subsection provides function allowing to configure and read the buffer size
- (number of data to be transferred).
- [..]
- The DMA data counter can be written only when the DMA Stream is disabled
- (ie. after transfer complete event).
- [..]
- The following function can be used to write the Stream data counter value:
- (+) void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
- -@- It is advised to use this function rather than DMA_Init() in situations
- where only the Data buffer needs to be reloaded.
- -@- If the Source and Destination Data Sizes are different, then the value
- written in data counter, expressing the number of transfers, is relative
- to the number of transfers from the Peripheral point of view.
- ie. If Memory data size is Word, Peripheral data size is Half-Words,
- then the value to be configured in the data counter is the number
- of Half-Words to be transferred from/to the peripheral.
- [..]
- The DMA data counter can be read to indicate the number of remaining transfers for
- the relative DMA Stream. This counter is decremented at the end of each data
- transfer and when the transfer is complete:
- (+) If Normal mode is selected: the counter is set to 0.
- (+) If Circular mode is selected: the counter is reloaded with the initial value
- (configured before enabling the DMA Stream)
- [..]
- The following function can be used to read the Stream data counter value:
- (+) uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes the number of data units to be transferred on the DMAy Streamx.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param Counter: Number of data units to be transferred (from 0 to 65535)
- * Number of data items depends only on the Peripheral data format.
- *
- * @note If Peripheral data format is Bytes: number of data units is equal
- * to total number of bytes to be transferred.
- *
- * @note If Peripheral data format is Half-Word: number of data units is
- * equal to total number of bytes to be transferred / 2.
- *
- * @note If Peripheral data format is Word: number of data units is equal
- * to total number of bytes to be transferred / 4.
- *
- * @note In Memory-to-Memory transfer mode, the memory buffer pointed by
- * DMAy_SxPAR register is considered as Peripheral.
- *
- * @retval The number of remaining data units in the current DMAy Streamx transfer.
- */
-void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Write the number of data units to be transferred */
- DMAy_Streamx->NDTR = (uint16_t)Counter;
-}
-
-/**
- * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval The number of remaining data units in the current DMAy Streamx transfer.
- */
-uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Return the number of remaining data units for DMAy Streamx */
- return ((uint16_t)(DMAy_Streamx->NDTR));
-}
-/**
- * @}
- */
-
-/** @defgroup DMA_Group3 Double Buffer mode functions
- * @brief Double Buffer mode functions
- *
-@verbatim
- ===============================================================================
- ##### Double Buffer mode functions #####
- ===============================================================================
- [..]
- This subsection provides function allowing to configure and control the double
- buffer mode parameters.
-
- [..]
- The Double Buffer mode can be used only when Circular mode is enabled.
- The Double Buffer mode cannot be used when transferring data from Memory to Memory.
-
- [..]
- The Double Buffer mode allows to set two different Memory addresses from/to which
- the DMA controller will access alternatively (after completing transfer to/from
- target memory 0, it will start transfer to/from target memory 1).
- This allows to reduce software overhead for double buffering and reduce the CPU
- access time.
-
- [..]
- Two functions must be called before calling the DMA_Init() function:
- (+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx,
- uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory);
- (+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
-
- [..]
- DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address
- and the first Memory target from/to which the transfer will start after
- enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called
- to enable the Double Buffer mode (or disable it when it should not be used).
-
- [..]
- Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is
- stopped) to modify on of the target Memories addresses or to check wich Memory target is currently
- used:
- (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx,
- uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget);
- (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
-
- [..]
- DMA_MemoryTargetConfig() can be called to modify the base address of one of
- the two target Memories.
- The Memory of which the base address will be modified must not be currently
- be used by the DMA Stream (ie. if the DMA Stream is currently transferring
- from Memory 1 then you can only modify base address of target Memory 0 and vice versa).
- To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which
- returns the index of the Memory target currently in use by the DMA Stream.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode
- * and the current memory target.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param Memory1BaseAddr: the base address of the second buffer (Memory 1)
- * @param DMA_CurrentMemory: specifies which memory will be first buffer for
- * the transactions when the Stream will be enabled.
- * This parameter can be one of the following values:
- * @arg DMA_Memory_0: Memory 0 is the current buffer.
- * @arg DMA_Memory_1: Memory 1 is the current buffer.
- *
- * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init().
- *
- * @retval None
- */
-void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
- uint32_t DMA_CurrentMemory)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory));
-
- if (DMA_CurrentMemory != DMA_Memory_0)
- {
- /* Set Memory 1 as current memory address */
- DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT);
- }
- else
- {
- /* Set Memory 0 as current memory address */
- DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT);
- }
-
- /* Write to DMAy Streamx M1AR */
- DMAy_Streamx->M1AR = Memory1BaseAddr;
-}
-
-/**
- * @brief Enables or disables the double buffer mode for the selected DMA stream.
- * @note This function can be called only when the DMA Stream is disabled.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param NewState: new state of the DMAy Streamx double buffer mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Configure the Double Buffer mode */
- if (NewState != DISABLE)
- {
- /* Enable the Double buffer mode */
- DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM;
- }
- else
- {
- /* Disable the Double buffer mode */
- DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM;
- }
-}
-
-/**
- * @brief Configures the Memory address for the next buffer transfer in double
- * buffer mode (for dynamic use). This function can be called when the
- * DMA Stream is enabled and when the transfer is ongoing.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param MemoryBaseAddr: The base address of the target memory buffer
- * @param DMA_MemoryTarget: Next memory target to be used.
- * This parameter can be one of the following values:
- * @arg DMA_Memory_0: To use the memory address 0
- * @arg DMA_Memory_1: To use the memory address 1
- *
- * @note It is not allowed to modify the Base Address of a target Memory when
- * this target is involved in the current transfer. ie. If the DMA Stream
- * is currently transferring to/from Memory 1, then it not possible to
- * modify Base address of Memory 1, but it is possible to modify Base
- * address of Memory 0.
- * To know which Memory is currently used, you can use the function
- * DMA_GetCurrentMemoryTarget().
- *
- * @retval None
- */
-void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
- uint32_t DMA_MemoryTarget)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget));
-
- /* Check the Memory target to be configured */
- if (DMA_MemoryTarget != DMA_Memory_0)
- {
- /* Write to DMAy Streamx M1AR */
- DMAy_Streamx->M1AR = MemoryBaseAddr;
- }
- else
- {
- /* Write to DMAy Streamx M0AR */
- DMAy_Streamx->M0AR = MemoryBaseAddr;
- }
-}
-
-/**
- * @brief Returns the current memory target used by double buffer transfer.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval The memory target number: 0 for Memory0 or 1 for Memory1.
- */
-uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Get the current memory target */
- if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0)
- {
- /* Current memory buffer used is Memory 1 */
- tmp = 1;
- }
- else
- {
- /* Current memory buffer used is Memory 0 */
- tmp = 0;
- }
- return tmp;
-}
-/**
- * @}
- */
-
-/** @defgroup DMA_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DMA enable status
- (+) Check the FIFO status
- (+) Configure the DMA Interrupts sources and check or clear the flags or
- pending bits status.
-
- [..]
- (#) DMA Enable status:
- After configuring the DMA Stream (DMA_Init() function) and enabling
- the stream, it is recommended to check (or wait until) the DMA Stream
- is effectively enabled. A Stream may remain disabled if a configuration
- parameter is wrong. After disabling a DMA Stream, it is also recommended
- to check (or wait until) the DMA Stream is effectively disabled.
- If a Stream is disabled while a data transfer is ongoing, the current
- data will be transferred and the Stream will be effectively disabled
- only after this data transfer completion.
- To monitor this state it is possible to use the following function:
- (++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-
- (#) FIFO Status:
- It is possible to monitor the FIFO status when a transfer is ongoing
- using the following function:
- (++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-
- (#) DMA Interrupts and Flags:
- The user should identify which mode will be used in his application
- to manage the DMA controller events: Polling mode or Interrupt mode.
-
- *** Polling Mode ***
- ====================
- [..]
- Each DMA stream can be managed through 4 event Flags:
- (x : DMA Stream number )
- (#) DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred.
- (#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred.
- (#) DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred.
- (#) DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred.
- (#) DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred .
- [..]
- In this Mode it is advised to use the following functions:
- (+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
- (+) void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..]
- Each DMA Stream can be managed through 4 Interrupts:
-
- *** Interrupt Source ***
- ========================
- [..]
- (#) DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event.
- (#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event.
- (#) DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event.
- (#) DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event.
- (#) DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event.
- [..]
- In this Mode it is advised to use the following functions:
- (+) void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
- (+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
- (+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the status of EN bit for the specified DMAy Streamx.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- *
- * @note After configuring the DMA Stream (DMA_Init() function) and enabling
- * the stream, it is recommended to check (or wait until) the DMA Stream
- * is effectively enabled. A Stream may remain disabled if a configuration
- * parameter is wrong.
- * After disabling a DMA Stream, it is also recommended to check (or wait
- * until) the DMA Stream is effectively disabled. If a Stream is disabled
- * while a data transfer is ongoing, the current data will be transferred
- * and the Stream will be effectively disabled only after the transfer
- * of this single data is finished.
- *
- * @retval Current state of the DMAy Streamx (ENABLE or DISABLE).
- */
-FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- FunctionalState state = DISABLE;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0)
- {
- /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */
- state = ENABLE;
- }
- else
- {
- /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and
- all transfers are complete) */
- state = DISABLE;
- }
- return state;
-}
-
-/**
- * @brief Returns the current DMAy Streamx FIFO filled level.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @retval The FIFO filling state.
- * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
- * and not empty.
- * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
- * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
- * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
- * - DMA_FIFOStatus_Empty: when FIFO is empty
- * - DMA_FIFOStatus_Full: when FIFO is full
- */
-uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
-
- /* Get the FIFO level bits */
- tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS));
-
- return tmpreg;
-}
-
-/**
- * @brief Checks whether the specified DMAy Streamx flag is set or not.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag
- * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Streamx transfer error flag
- * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
- * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval The new state of DMA_FLAG (SET or RESET).
- */
-FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
-{
- FlagStatus bitstatus = RESET;
- DMA_TypeDef* DMAy;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if the flag is in HISR or LISR */
- if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Get DMAy HISR register value */
- tmpreg = DMAy->HISR;
- }
- else
- {
- /* Get DMAy LISR register value */
- tmpreg = DMAy->LISR;
- }
-
- /* Mask the reserved bits */
- tmpreg &= (uint32_t)RESERVED_MASK;
-
- /* Check the status of the specified DMA flag */
- if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
- {
- /* DMA_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the DMA_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Streamx's pending flags.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag
- * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Streamx transfer error flag
- * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
- * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval None
- */
-void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
-{
- DMA_TypeDef* DMAy;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if LIFCR or HIFCR register is targeted */
- if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Set DMAy HIFCR register clear flag bits */
- DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
- }
- else
- {
- /* Set DMAy LIFCR register clear flag bits */
- DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
- }
-}
-
-/**
- * @brief Enables or disables the specified DMAy Streamx interrupts.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @arg DMA_IT_FE: FIFO error interrupt mask
- * @param NewState: new state of the specified DMA interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Check if the DMA_IT parameter contains a FIFO interrupt */
- if ((DMA_IT & DMA_IT_FE) != 0)
- {
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA FIFO interrupts */
- DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE;
- }
- else
- {
- /* Disable the selected DMA FIFO interrupts */
- DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE;
- }
- }
-
- /* Check if the DMA_IT parameter contains a Transfer interrupt */
- if (DMA_IT != DMA_IT_FE)
- {
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA transfer interrupts */
- DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
- }
- else
- {
- /* Disable the selected DMA transfer interrupts */
- DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
- }
- }
-}
-
-/**
- * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_IT: specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt
- * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt
- * @arg DMA_IT_TEIFx: Streamx transfer error interrupt
- * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
- * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval The new state of DMA_IT (SET or RESET).
- */
-ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
-{
- ITStatus bitstatus = RESET;
- DMA_TypeDef* DMAy;
- uint32_t tmpreg = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_GET_IT(DMA_IT));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if the interrupt enable bit is in the CR or FCR register */
- if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
- {
- /* Get the interrupt enable position mask in CR register */
- tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);
-
- /* Check the enable bit in CR register */
- enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
- }
- else
- {
- /* Check the enable bit in FCR register */
- enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE);
- }
-
- /* Check if the interrupt pending flag is in LISR or HISR */
- if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Get DMAy HISR register value */
- tmpreg = DMAy->HISR ;
- }
- else
- {
- /* Get DMAy LISR register value */
- tmpreg = DMAy->LISR ;
- }
-
- /* mask all reserved bits */
- tmpreg &= (uint32_t)RESERVED_MASK;
-
- /* Check the status of the specified DMA interrupt */
- if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
- {
- /* DMA_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_IT is reset */
- bitstatus = RESET;
- }
-
- /* Return the DMA_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Streamx's interrupt pending bits.
- * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
- * to 7 to select the DMA Stream.
- * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt
- * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt
- * @arg DMA_IT_TEIFx: Streamx transfer error interrupt
- * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
- * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt
- * Where x can be 0 to 7 to select the DMA Stream.
- * @retval None
- */
-void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
-{
- DMA_TypeDef* DMAy;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
- assert_param(IS_DMA_CLEAR_IT(DMA_IT));
-
- /* Determine the DMA to which belongs the stream */
- if (DMAy_Streamx < DMA2_Stream0)
- {
- /* DMAy_Streamx belongs to DMA1 */
- DMAy = DMA1;
- }
- else
- {
- /* DMAy_Streamx belongs to DMA2 */
- DMAy = DMA2;
- }
-
- /* Check if LIFCR or HIFCR register is targeted */
- if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
- {
- /* Set DMAy HIFCR register clear interrupt bits */
- DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
- }
- else
- {
- /* Set DMAy LIFCR register clear interrupt bits */
- DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
deleted file mode 100644
index 0de36e9e..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_exti.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the EXTI peripheral:
- * + Initialization and Configuration
- * + Interrupts and flags management
- *
-@verbatim
-
- ===================================================================
- ##### EXTI features #####
- ===================================================================
-
- [..] External interrupt/event lines are mapped as following:
- (#) All available GPIO pins are connected to the 16 external
- interrupt/event lines from EXTI0 to EXTI15.
- (#) EXTI line 16 is connected to the PVD Output
- (#) EXTI line 17 is connected to the RTC Alarm event
- (#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event
- (#) EXTI line 19 is connected to the Ethernet Wakeup event
- (#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event
- (#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events
- (#) EXTI line 22 is connected to the RTC Wakeup event
-
-
- ##### How to use this driver #####
- ===================================================================
-
- [..] In order to use an I/O pin as an external interrupt source, follow steps
- below:
- (#) Configure the I/O in input mode using GPIO_Init()
- (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
- (#) Select the mode(interrupt, event) and configure the trigger
- selection (Rising, falling or both) using EXTI_Init()
- (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
-
- [..]
- (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
- registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_flash.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FLASH
- * @brief FLASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FLASH_Private_Functions
- * @{
- */
-
-/** @defgroup FLASH_Group1 FLASH Interface configuration functions
- * @brief FLASH Interface configuration functions
- *
-
-@verbatim
- ===============================================================================
- ##### FLASH Interface configuration functions #####
- ===============================================================================
- [..]
- This group includes the following functions:
- (+) void FLASH_SetLatency(uint32_t FLASH_Latency)
- To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device.
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
- |---------------|----------------|----------------|-----------------|-----------------|
- |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
- +-------------------------------------------------------------------------------------+
-
- [..]
- +-------------------------------------------------------------------------------------------------------------------+
- | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V |
- |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
- |Max Parallelism| x32 | x16 | x8 | x64 |
- |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
- |PSIZE[1:0] | 10 | 01 | 00 | 11 |
- +-------------------------------------------------------------------------------------------------------------------+
- -@- When VOS bit (in PWR_CR register) is reset to 0 , the maximum value of HCLK is 144 MHz.
- You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
- -@- On STM32F40xx/41xx devices:
- (++) when VOS = '0', the maximum value of fHCLK = 144MHz.
- (++) when VOS = '1', the maximum value of fHCLK = 168MHz.
- [..]
- On STM32F427x/437x devices:
- (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz.
- (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz.
- (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz
- You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
-
- (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
- (+) void FLASH_InstructionCacheCmd(FunctionalState NewState)
- (+) void FLASH_DataCacheCmd(FunctionalState NewState)
- (+) void FLASH_InstructionCacheReset(void)
- (+) void FLASH_DataCacheReset(void)
-
- [..]
- The unlock sequence is not needed for these functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the code latency value.
- * @param FLASH_Latency: specifies the FLASH Latency value.
- * This parameter can be one of the following values:
- * @arg FLASH_Latency_0: FLASH Zero Latency cycle
- * @arg FLASH_Latency_1: FLASH One Latency cycle
- * @arg FLASH_Latency_2: FLASH Two Latency cycles
- * @arg FLASH_Latency_3: FLASH Three Latency cycles
- * @arg FLASH_Latency_4: FLASH Four Latency cycles
- * @arg FLASH_Latency_5: FLASH Five Latency cycles
- * @arg FLASH_Latency_6: FLASH Six Latency cycles
- * @arg FLASH_Latency_7: FLASH Seven Latency cycles
- * For STM32F40xx/41xx and STM32F427x/437x devices this parameter can be
- * a value between FLASH_Latency_0 and FLASH_Latency_7.
- * @retval None
- */
-void FLASH_SetLatency(uint32_t FLASH_Latency)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));
-
- /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */
- *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;
-}
-
-/**
- * @brief Enables or disables the Prefetch Buffer.
- * @param NewState: new state of the Prefetch Buffer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_PrefetchBufferCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Enable or disable the Prefetch Buffer */
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_PRFTEN;
- }
- else
- {
- FLASH->ACR &= (~FLASH_ACR_PRFTEN);
- }
-}
-
-/**
- * @brief Enables or disables the Instruction Cache feature.
- * @param NewState: new state of the Instruction Cache.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_InstructionCacheCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_ICEN;
- }
- else
- {
- FLASH->ACR &= (~FLASH_ACR_ICEN);
- }
-}
-
-/**
- * @brief Enables or disables the Data Cache feature.
- * @param NewState: new state of the Data Cache.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_DataCacheCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_DCEN;
- }
- else
- {
- FLASH->ACR &= (~FLASH_ACR_DCEN);
- }
-}
-
-/**
- * @brief Resets the Instruction Cache.
- * @note This function must be used only when the Instruction Cache is disabled.
- * @param None
- * @retval None
- */
-void FLASH_InstructionCacheReset(void)
-{
- FLASH->ACR |= FLASH_ACR_ICRST;
-}
-
-/**
- * @brief Resets the Data Cache.
- * @note This function must be used only when the Data Cache is disabled.
- * @param None
- * @retval None
- */
-void FLASH_DataCacheReset(void)
-{
- FLASH->ACR |= FLASH_ACR_DCRST;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group2 FLASH Memory Programming functions
- * @brief FLASH Memory Programming functions
- *
-@verbatim
- ===============================================================================
- ##### FLASH Memory Programming functions #####
- ===============================================================================
- [..]
- This group includes the following functions:
- (+) void FLASH_Unlock(void)
- (+) void FLASH_Lock(void)
- (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
- (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
- (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
- (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
- (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
- (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
- [..]
- Any operation of erase or program should follow these steps:
- (#) Call the FLASH_Unlock() function to enable the FLASH control register access
-
- (#) Call the desired function to erase sector(s) or program data
-
- (#) Call the FLASH_Lock() function to disable the FLASH control register access
- (recommended to protect the FLASH memory against possible unwanted operation)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the FLASH control register access
- * @param None
- * @retval None
- */
-void FLASH_Unlock(void)
-{
- if((FLASH->CR & FLASH_CR_LOCK) != RESET)
- {
- /* Authorize the FLASH Registers access */
- FLASH->KEYR = FLASH_KEY1;
- FLASH->KEYR = FLASH_KEY2;
- }
-}
-
-/**
- * @brief Locks the FLASH control register access
- * @param None
- * @retval None
- */
-void FLASH_Lock(void)
-{
- /* Set the LOCK Bit to lock the FLASH Registers access */
- FLASH->CR |= FLASH_CR_LOCK;
-}
-
-/**
- * @brief Erases a specified FLASH Sector.
- *
- * @note If an erase and a program operations are requested simustaneously,
- * the erase operation is performed before the program one.
- *
- * @param FLASH_Sector: The Sector number to be erased.
- * For STM32F40xx/41xx devices this parameter can be a value between
- * FLASH_Sector_0 and FLASH_Sector_11.
- * For STM32F427x/437x devices this parameter can be a value between
- * FLASH_Sector_0 and FLASH_Sector_23.
- *
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
- * This parameter can be one of the following values:
- * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
- * the operation will be done by byte (8-bit)
- * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
- * the operation will be done by half word (16-bit)
- * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
- * the operation will be done by word (32-bit)
- * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
- * the operation will be done by double word (64-bit)
- *
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
-{
- uint32_t tmp_psize = 0x0;
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_SECTOR(FLASH_Sector));
- assert_param(IS_VOLTAGERANGE(VoltageRange));
-
- if(VoltageRange == VoltageRange_1)
- {
- tmp_psize = FLASH_PSIZE_BYTE;
- }
- else if(VoltageRange == VoltageRange_2)
- {
- tmp_psize = FLASH_PSIZE_HALF_WORD;
- }
- else if(VoltageRange == VoltageRange_3)
- {
- tmp_psize = FLASH_PSIZE_WORD;
- }
- else
- {
- tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
- }
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase the sector */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR &= SECTOR_MASK;
- FLASH->CR |= FLASH_CR_SER | FLASH_Sector;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the erase operation is completed, disable the SER Bit */
- FLASH->CR &= (~FLASH_CR_SER);
- FLASH->CR &= SECTOR_MASK;
- }
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Erases all FLASH Sectors.
- *
- * @note If an erase and a program operations are requested simustaneously,
- * the erase operation is performed before the program one.
- *
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
- * This parameter can be one of the following values:
- * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
- * the operation will be done by byte (8-bit)
- * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
- * the operation will be done by half word (16-bit)
- * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
- * the operation will be done by word (32-bit)
- * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
- * the operation will be done by double word (64-bit)
- *
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
-{
-#if defined (STM32F427X) || (STM32F40XX)
- uint32_t tmp_psize = 0x0;
-#endif
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
- assert_param(IS_VOLTAGERANGE(VoltageRange));
-
-#if defined (STM32F427X) || (STM32F40XX)
- if(VoltageRange == VoltageRange_1)
- {
- tmp_psize = FLASH_PSIZE_BYTE;
- }
- else if(VoltageRange == VoltageRange_2)
- {
- tmp_psize = FLASH_PSIZE_HALF_WORD;
- }
- else if(VoltageRange == VoltageRange_3)
- {
- tmp_psize = FLASH_PSIZE_WORD;
- }
- else
- {
- tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
- }
-#endif
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all sectors */
-#if defined (STM32F427X)
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2);
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the erase operation is completed, disable the MER Bit */
- FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2);
-#endif /* STM32F427X */
-
-#ifdef STM32F40XX
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR |= FLASH_CR_MER;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the erase operation is completed, disable the MER Bit */
- FLASH->CR &= (~FLASH_CR_MER);
-#endif /* STM32F40XX */
-
- }
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Programs a double word (64-bit) at a specified address.
- * @note This function must be used when the device voltage range is from
- * 2.7V to 3.6V and an External Vpp is present.
- *
- * @note If an erase and a program operations are requested simustaneously,
- * the erase operation is performed before the program one.
- *
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint64_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a word (32-bit) at a specified address.
- *
- * @note This function must be used when the device voltage range is from 2.7V to 3.6V.
- *
- * @note If an erase and a program operations are requested simustaneously,
- * the erase operation is performed before the program one.
- *
- * @param Address: specifies the address to be programmed.
- * This parameter can be any address in Program memory zone or in OTP zone.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_WORD;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint32_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a half word (16-bit) at a specified address.
- * @note This function must be used when the device voltage range is from 2.1V to 3.6V.
- *
- * @note If an erase and a program operations are requested simustaneously,
- * the erase operation is performed before the program one.
- *
- * @param Address: specifies the address to be programmed.
- * This parameter can be any address in Program memory zone or in OTP zone.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_HALF_WORD;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a byte (8-bit) at a specified address.
- * @note This function can be used within all the device supply voltage ranges.
- *
- * @note If an erase and a program operations are requested simustaneously,
- * the erase operation is performed before the program one.
- *
- * @param Address: specifies the address to be programmed.
- * This parameter can be any address in Program memory zone or in OTP zone.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= FLASH_PSIZE_BYTE;
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint8_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- /* if the program operation is completed, disable the PG Bit */
- FLASH->CR &= (~FLASH_CR_PG);
- }
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group3 Option Bytes Programming functions
- * @brief Option Bytes Programming functions
- *
-@verbatim
- ===============================================================================
- ##### Option Bytes Programming functions #####
- ===============================================================================
- [..]
- This group includes the following functions:
- (+) void FLASH_OB_Unlock(void)
- (+) void FLASH_OB_Lock(void)
- (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
- (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
- (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP)
- (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
- (+) void FLASH_OB_BORConfig(uint8_t OB_BOR)
- (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)
- (+) FLASH_Status FLASH_OB_Launch(void)
- (+) uint32_t FLASH_OB_GetUser(void)
- (+) uint8_t FLASH_OB_GetWRP(void)
- (+) uint8_t FLASH_OB_GetWRP1(void)
- (+) uint8_t FLASH_OB_GetRDP(void)
- (+) uint8_t FLASH_OB_GetBOR(void)
- [..]
- Any operation of erase or program should follow these steps:
- (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control
- register access
-
- (#) Call one or several functions to program the desired Option Bytes:
- (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
- => to Enable/Disable the desired sector write protection
- (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read
- Protection Level
- (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
- => to configure the user Option Bytes.
- (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level
-
- (#) Once all needed Option Bytes to be programmed are correctly written,
- call the FLASH_OB_Launch() function to launch the Option Bytes
- programming process.
-
- -@- When changing the IWDG mode from HW to SW or from SW to HW, a system
- reset is needed to make the change effective.
-
- (#) Call the FLASH_OB_Lock() function to disable the FLASH option control
- register access (recommended to protect the Option Bytes against
- possible unwanted operations)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the FLASH Option Control Registers access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Unlock(void)
-{
- if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
- {
- /* Authorizes the Option Byte register programming */
- FLASH->OPTKEYR = FLASH_OPT_KEY1;
- FLASH->OPTKEYR = FLASH_OPT_KEY2;
- }
-}
-
-/**
- * @brief Locks the FLASH Option Control Registers access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Lock(void)
-{
- /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
- FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
-}
-
-/**
- * @brief Enables or disables the write protection of the desired sectors
- *
- * @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase the flash sector i if CortexM4
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
- *
- * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
- * This parameter can be one of the following values:
- * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11
- * @arg OB_WRP_Sector_All
- * @param Newstate: new state of the Write Protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(OB_WRP));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- if(NewState != DISABLE)
- {
- *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);
- }
- else
- {
- *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
- }
- }
-}
-
-/**
- * @brief Enables or disables the write protection of the desired sectors
- * @note This function can be used only for STM32F427x/437x devices.
- * @note When the memory read out protection is selected (RDP level = 1),
- * it is not possible to program or erase the flash sector i if CortexM4
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
- *
- * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
- * This parameter can be one of the following values:
- * @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23
- * @arg OB_WRP_Sector_All
- * @param Newstate: new state of the Write Protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(OB_WRP));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- if(NewState != DISABLE)
- {
- *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP);
- }
- else
- {
- *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
- }
- }
-}
-
-/**
- * @brief Sets the read protection level.
- * @param OB_RDP: specifies the read protection level.
- * This parameter can be one of the following values:
- * @arg OB_RDP_Level_0: No protection
- * @arg OB_RDP_Level_1: Read protection of the memory
- * @arg OB_RDP_Level_2: Full chip protection
- *
- * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
- *
- * @retval None
- */
-void FLASH_OB_RDPConfig(uint8_t OB_RDP)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_RDP(OB_RDP));
-
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP;
-
- }
-}
-
-/**
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
- * @param OB_IWDG: Selects the IWDG mode
- * This parameter can be one of the following values:
- * @arg OB_IWDG_SW: Software IWDG selected
- * @arg OB_IWDG_HW: Hardware IWDG selected
- * @param OB_STOP: Reset event when entering STOP mode.
- * This parameter can be one of the following values:
- * @arg OB_STOP_NoRST: No reset generated when entering in STOP
- * @arg OB_STOP_RST: Reset generated when entering in STOP
- * @param OB_STDBY: Reset event when entering Standby mode.
- * This parameter can be one of the following values:
- * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
- * @retval None
- */
-void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
-{
- uint8_t optiontmp = 0xFF;
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- if(status == FLASH_COMPLETE)
- {
- /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
- optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F);
-
- /* Update User Option Byte */
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp)));
- }
-}
-
-/**
- * @brief Sets the BOR Level.
- * @param OB_BOR: specifies the Option Bytes BOR Reset Level.
- * This parameter can be one of the following values:
- * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
- * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
- * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
- * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
- * @retval None
- */
-void FLASH_OB_BORConfig(uint8_t OB_BOR)
-{
- /* Check the parameters */
- assert_param(IS_OB_BOR(OB_BOR));
-
- /* Set the BOR Level */
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR;
-
-}
-
-/**
- * @brief Launch the option byte loading.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_OB_Launch(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Set the OPTSTRT bit in OPTCR register */
- *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation();
-
- return status;
-}
-
-/**
- * @brief Returns the FLASH User Option Bytes values.
- * @param None
- * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
- * and RST_STDBY(Bit2).
- */
-uint8_t FLASH_OB_GetUser(void)
-{
- /* Return the User Option Byte */
- return (uint8_t)(FLASH->OPTCR >> 5);
-}
-
-/**
- * @brief Returns the FLASH Write Protection Option Bytes value.
- * @param None
- * @retval The FLASH Write Protection Option Bytes value
- */
-uint16_t FLASH_OB_GetWRP(void)
-{
- /* Return the FLASH write protection Register value */
- return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
-}
-
-/**
- * @brief Returns the FLASH Write Protection Option Bytes value.
- * @note This function can be used only for STM32F427x/437x devices.
- * @param None
- * @retval The FLASH Write Protection Option Bytes value
- */
-uint16_t FLASH_OB_GetWRP1(void)
-{
- /* Return the FLASH write protection Register value */
- return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
-}
-
-/**
- * @brief Returns the FLASH Read Protection level.
- * @param None
- * @retval FLASH ReadOut Protection Status:
- * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
- * - RESET, when OB_RDP_Level_0 is set
- */
-FlagStatus FLASH_OB_GetRDP(void)
-{
- FlagStatus readstatus = RESET;
-
- if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))
- {
- readstatus = SET;
- }
- else
- {
- readstatus = RESET;
- }
- return readstatus;
-}
-
-/**
- * @brief Returns the FLASH BOR level.
- * @param None
- * @retval The FLASH BOR level:
- * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
- * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
- * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
- * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
- */
-uint8_t FLASH_OB_GetBOR(void)
-{
- /* Return the FLASH BOR level */
- return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified FLASH interrupts.
- * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_ERR: FLASH Error Interrupt
- * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
- * @retval None
- */
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_IT(FLASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR |= FLASH_IT;
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR &= ~(uint32_t)FLASH_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified FLASH flag is set or not.
- * @param FLASH_FLAG: specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
- * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
- * @arg FLASH_FLAG_BSY: FLASH Busy flag
- * @retval The new state of FLASH_FLAG (SET or RESET).
- */
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
-
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the new state of FLASH_FLAG (SET or RESET) */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FLASH's pending flags.
- * @param FLASH_FLAG: specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
- * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
- * @retval None
- */
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
-
- /* Clear the flags */
- FLASH->SR = FLASH_FLAG;
-}
-
-/**
- * @brief Returns the FLASH Status.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_GetStatus(void)
-{
- FLASH_Status flashstatus = FLASH_COMPLETE;
-
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
- {
- flashstatus = FLASH_BUSY;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_WRP;
- }
- else
- {
- if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_PROGRAM;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_OPERATION;
- }
- else
- {
- flashstatus = FLASH_COMPLETE;
- }
- }
- }
- }
- /* Return the FLASH Status */
- return flashstatus;
-}
-
-/**
- * @brief Waits for a FLASH operation to complete.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_WaitForLastOperation(void)
-{
- __IO FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the FLASH Status */
- status = FLASH_GetStatus();
-
- /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
- Even if the FLASH operation fails, the BUSY flag will be reset and an error
- flag will be set */
- while(status == FLASH_BUSY)
- {
- status = FLASH_GetStatus();
- }
- /* Return the operation status */
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
deleted file mode 100644
index c01fc629..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
+++ /dev/null
@@ -1,989 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_fsmc.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the FSMC peripheral:
- * + Interface with SRAM, PSRAM, NOR and OneNAND memories
- * + Interface with NAND memories
- * + Interface with 16-bit PC Card compatible memories
- * + Interrupts and flags management
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_gpio.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup GPIO
- * @brief GPIO driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Private_Functions
- * @{
- */
-
-/** @defgroup GPIO_Group1 Initialization and Configuration
- * @brief Initialization and Configuration
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the GPIOx peripheral registers to their default reset values.
- * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @retval None
- */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- if (GPIOx == GPIOA)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
- }
- else if (GPIOx == GPIOB)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
- }
- else if (GPIOx == GPIOC)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
- }
- else if (GPIOx == GPIOD)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
- }
- else if (GPIOx == GPIOE)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
- }
- else if (GPIOx == GPIOF)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
- }
- else if (GPIOx == GPIOG)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
- }
- else if (GPIOx == GPIOH)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
- }
- else
- {
- if (GPIOx == GPIOI)
- {
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
- RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
- assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
- assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
-
- /* ------------------------- Configure the port pins ---------------- */
- /*-- GPIO Mode Configuration --*/
- for (pinpos = 0x00; pinpos < 0x10; pinpos++)
- {
- pos = ((uint32_t)0x01) << pinpos;
- /* Get the port pins position */
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
- if (currentpin == pos)
- {
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
- GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
-
- if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
- {
- /* Check Speed mode parameters */
- assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-
- /* Speed mode configuration */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
- GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
-
- /* Check Output mode parameters */
- assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
-
- /* Output mode configuration*/
- GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
- GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
- }
-
- /* Pull-up Pull down resistor configuration*/
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
- GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
- }
- }
-}
-
-/**
- * @brief Fills each GPIO_InitStruct member with its default value.
- * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
- GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
-}
-
-/**
- * @brief Locks GPIO Pins configuration registers.
- * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
- * @note The configuration of the locked GPIO pins can no longer be modified
- * until the next reset.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: specifies the port bit to be locked.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- __IO uint32_t tmp = 0x00010000;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- tmp |= GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Reset LCKK bit */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group2 GPIO Read and Write
- * @brief GPIO Read and Write
- *
-@verbatim
- ===============================================================================
- ##### GPIO Read and Write #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_Pin_x where x can be (0..15).
- * @retval The input port pin value.
- */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO input data port.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @retval GPIO input data port value.
- */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->IDR);
-}
-
-/**
- * @brief Reads the specified output data port bit.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_Pin_x where x can be (0..15).
- * @retval The output port pin value.
- */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO output data port.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @retval GPIO output data port value.
- */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->ODR);
-}
-
-/**
- * @brief Sets the selected data port bits.
- * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: specifies the port bits to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRRL = GPIO_Pin;
-}
-
-/**
- * @brief Clears the selected data port bits.
- * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: specifies the port bits to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRRH = GPIO_Pin;
-}
-
-/**
- * @brief Sets or clears the selected data port bit.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be one of GPIO_Pin_x where x can be (0..15).
- * @param BitVal: specifies the value to be written to the selected bit.
- * This parameter can be one of the BitAction enum values:
- * @arg Bit_RESET: to clear the port pin
- * @arg Bit_SET: to set the port pin
- * @retval None
- */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
- if (BitVal != Bit_RESET)
- {
- GPIOx->BSRRL = GPIO_Pin;
- }
- else
- {
- GPIOx->BSRRH = GPIO_Pin ;
- }
-}
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param PortVal: specifies the value to be written to the port output data register.
- * @retval None
- */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR = PortVal;
-}
-
-/**
- * @brief Toggles the specified GPIO pins..
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_Pin: Specifies the pins to be toggled.
- * @retval None
- */
-void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR ^= GPIO_Pin;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
- * @brief GPIO Alternate functions configuration function
- *
-@verbatim
- ===============================================================================
- ##### GPIO Alternate functions configuration function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Changes the mapping of the specified pin.
- * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
- * STM32F40xx/41xx and STM32F427x/437x devices.
- * @param GPIO_PinSource: specifies the pin for the Alternate function.
- * This parameter can be GPIO_PinSourcex where x can be (0..15).
- * @param GPIO_AFSelection: selects the pin to used as Alternate function.
- * This parameter can be one of the following values:
- * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset)
- * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset)
- * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset)
- * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset)
- * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
- * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
- * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
- * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
- * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
- * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
- * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
- * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
- * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
- * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
- * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
- * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
- * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
- * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
- * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
- * @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5
- * @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5
- * @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5
- * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
- * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
- * @arg GPIO_AF_USART1: Connect USART1 pins to AF7
- * @arg GPIO_AF_USART2: Connect USART2 pins to AF7
- * @arg GPIO_AF_USART3: Connect USART3 pins to AF7
- * @arg GPIO_AF_UART4: Connect UART4 pins to AF8
- * @arg GPIO_AF_UART5: Connect UART5 pins to AF8
- * @arg GPIO_AF_USART6: Connect USART6 pins to AF8
- * @arg GPIO_AF_UART7: Connect UART7 pins to AF8
- * @arg GPIO_AF_UART8: Connect UART8 pins to AF8
- * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
- * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
- * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
- * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
- * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
- * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
- * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
- * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
- * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
- * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
- * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
- * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
- * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
- * @retval None
- */
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
-{
- uint32_t temp = 0x00;
- uint32_t temp_2 = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
- assert_param(IS_GPIO_AF(GPIO_AF));
-
- temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
- GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
- temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
- GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
deleted file mode 100644
index 2bd2ae7b..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
+++ /dev/null
@@ -1,726 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hash.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the HASH / HMAC Processor (HASH) peripheral:
- * - Initialization and Configuration functions
- * - Message Digest generation functions
- * - context swapping functions
- * - DMA interface function
- * - Interrupts and flags management
- *
-@verbatim
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
-
- *** HASH operation : ***
- ========================
- [..]
- (#) Enable the HASH controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.
-
- (#) Initialise the HASH using HASH_Init() function.
-
- (#) Reset the HASH processor core, so that the HASH will be ready
- to compute he message digest of a new message by using HASH_Reset() function.
-
- (#) Enable the HASH controller using the HASH_Cmd() function.
-
- (#) if using DMA for Data input transfer, Activate the DMA Request
- using HASH_DMACmd() function
-
- (#) if DMA is not used for data transfer, use HASH_DataIn() function
- to enter data to IN FIFO.
-
-
- (#) Configure the Number of valid bits in last word of the message
- using HASH_SetLastWordValidBitsNbr() function.
-
- (#) if the message length is not an exact multiple of 512 bits,
- then the function HASH_StartDigest() must be called to launch the computation
- of the final digest.
-
- (#) Once computed, the digest can be read using HASH_GetDigest() function.
-
- (#) To control HASH events you can use one of the following wo methods:
- (++) Check on HASH flags using the HASH_GetFlagStatus() function.
- (++) Use HASH interrupts through the function HASH_ITConfig() at
- initialization phase and HASH_GetITStatus() function into
- interrupt routines in hashing phase.
- After checking on a flag you should clear it using HASH_ClearFlag()
- function. And after checking on an interrupt event you should
- clear it using HASH_ClearITPendingBit() function.
-
- (#) Save and restore hash processor context using
- HASH_SaveContext() and HASH_RestoreContext() functions.
-
-
-
- *** HMAC operation : ***
- ========================
- [..] The HMAC algorithm is used for message authentication, by
- irreversibly binding the message being processed to a key chosen
- by the user.
- For HMAC specifications, refer to "HMAC: keyed-hashing for message
- authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997"
-
- [..] Basically, the HMAC algorithm consists of two nested hash operations:
- HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)]
- where:
- (+) "pad" is a sequence of zeroes needed to extend the key to the
- length of the underlying hash function data block (that is
- 512 bits for both the SHA-1 and MD5 hash algorithms)
- (+) "|" represents the concatenation operator
-
-
- [..]To compute the HMAC, four different phases are required:
- (#) Initialise the HASH using HASH_Init() function to do HMAC
- operation.
-
- (#) The key (to be used for the inner hash function) is then given to the core.
- This operation follows the same mechanism as the one used to send the
- message in the hash operation (that is, by HASH_DataIn() function and,
- finally, HASH_StartDigest() function.
-
- (#) Once the last word has been entered and computation has started,
- the hash processor elaborates the key. It is then ready to accept the message
- text using the same mechanism as the one used to send the message in the
- hash operation.
-
- (#) After the first hash round, the hash processor returns "ready" to indicate
- that it is ready to receive the key to be used for the outer hash function
- (normally, this key is the same as the one used for the inner hash function).
- When the last word of the key is entered and computation starts, the HMAC
- result is made available using HASH_GetDigest() function.
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup HASH
- * @brief HASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HASH_Private_Functions
- * @{
- */
-
-/** @defgroup HASH_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initialize the HASH peripheral
- (+) Configure the HASH Processor
- (+) MD5/SHA1,
- (+) HASH/HMAC,
- (+) datatype
- (+) HMAC Key (if mode = HMAC)
- (+) Reset the HASH Processor
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the HASH peripheral registers to their default reset values
- * @param None
- * @retval None
- */
-void HASH_DeInit(void)
-{
- /* Enable HASH reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE);
- /* Release HASH from reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE);
-}
-
-/**
- * @brief Initializes the HASH peripheral according to the specified parameters
- * in the HASH_InitStruct structure.
- * @note the hash processor is reset when calling this function so that the
- * HASH will be ready to compute the message digest of a new message.
- * There is no need to call HASH_Reset() function.
- * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains
- * the configuration information for the HASH peripheral.
- * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only
- * if the algorithm mode is HMAC.
- * @retval None
- */
-void HASH_Init(HASH_InitTypeDef* HASH_InitStruct)
-{
- /* Check the parameters */
- assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection));
- assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType));
- assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode));
-
- /* Configure the Algorithm used, algorithm mode and the datatype */
- HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
- HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \
- HASH_InitStruct->HASH_DataType | \
- HASH_InitStruct->HASH_AlgoMode);
-
- /* if algorithm mode is HMAC, set the Key */
- if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC)
- {
- assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType));
- HASH->CR &= ~HASH_CR_LKEY;
- HASH->CR |= HASH_InitStruct->HASH_HMACKeyType;
- }
-
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
-}
-
-/**
- * @brief Fills each HASH_InitStruct member with its default value.
- * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will
- * be initialized.
- * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1,
- * Data type selected is 32b and HMAC Key Type is short key.
- * @retval None
- */
-void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct)
-{
- /* Initialize the HASH_AlgoSelection member */
- HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
-
- /* Initialize the HASH_AlgoMode member */
- HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH;
-
- /* Initialize the HASH_DataType member */
- HASH_InitStruct->HASH_DataType = HASH_DataType_32b;
-
- /* Initialize the HASH_HMACKeyType member */
- HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
-}
-
-/**
- * @brief Resets the HASH processor core, so that the HASH will be ready
- * to compute the message digest of a new message.
- * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation
- * completion interrupt status) bit corresponding to HASH_IT_DCI
- * interrupt and HASH_FLAG_DCIS flag.
- * @param None
- * @retval None
- */
-void HASH_Reset(void)
-{
- /* Reset the HASH processor core */
- HASH->CR |= HASH_CR_INIT;
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group2 Message Digest generation functions
- * @brief Message Digest generation functions
- *
-@verbatim
- ===============================================================================
- ##### Message Digest generation functions #####
- ===============================================================================
- [..] This section provides functions allowing the generation of message digest:
- (+) Push data in the IN FIFO : using HASH_DataIn()
- (+) Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr()
- (+) set the last word valid bits number using HASH_SetLastWordValidBitsNbr()
- (+) start digest calculation : using HASH_StartDigest()
- (+) Get the Digest message : using HASH_GetDigest()
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Configure the Number of valid bits in last word of the message
- * @param ValidNumber: Number of valid bits in last word of the message.
- * This parameter must be a number between 0 and 0x1F.
- * - 0x00: All 32 bits of the last data written are valid
- * - 0x01: Only bit [0] of the last data written is valid
- * - 0x02: Only bits[1:0] of the last data written are valid
- * - 0x03: Only bits[2:0] of the last data written are valid
- * - ...
- * - 0x1F: Only bits[30:0] of the last data written are valid
- * @note The Number of valid bits must be set before to start the message
- * digest competition (in Hash and HMAC) and key treatment(in HMAC).
- * @retval None
- */
-void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber)
-{
- /* Check the parameters */
- assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber));
-
- /* Configure the Number of valid bits in last word of the message */
- HASH->STR &= ~(HASH_STR_NBW);
- HASH->STR |= ValidNumber;
-}
-
-/**
- * @brief Writes data in the Data Input FIFO
- * @param Data: new data of the message to be processed.
- * @retval None
- */
-void HASH_DataIn(uint32_t Data)
-{
- /* Write in the DIN register a new data */
- HASH->DIN = Data;
-}
-
-/**
- * @brief Returns the number of words already pushed into the IN FIFO.
- * @param None
- * @retval The value of words already pushed into the IN FIFO.
- */
-uint8_t HASH_GetInFIFOWordsNbr(void)
-{
- /* Return the value of NBW bits */
- return ((HASH->CR & HASH_CR_NBW) >> 8);
-}
-
-/**
- * @brief Provides the message digest result.
- * @note In MD5 mode, Data[7] to Data[4] filed of HASH_MsgDigest structure is not used
- * and is read as zero.
- * In SHA-1 mode, Data[7] to Data[5] filed of HASH_MsgDigest structure is not used
- * and is read as zero.
- * In SHA-224 mode, Data[7] filed of HASH_MsgDigest structure is not used
- * and is read as zero.
- * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will
- * hold the message digest result
- * @retval None
- */
-void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest)
-{
- /* Get the data field */
- HASH_MessageDigest->Data[0] = HASH->HR[0];
- HASH_MessageDigest->Data[1] = HASH->HR[1];
- HASH_MessageDigest->Data[2] = HASH->HR[2];
- HASH_MessageDigest->Data[3] = HASH->HR[3];
- HASH_MessageDigest->Data[4] = HASH->HR[4];
- HASH_MessageDigest->Data[5] = HASH_DIGEST->HR[5];
- HASH_MessageDigest->Data[6] = HASH_DIGEST->HR[6];
- HASH_MessageDigest->Data[7] = HASH_DIGEST->HR[7];
-}
-
-/**
- * @brief Starts the message padding and calculation of the final message
- * @param None
- * @retval None
- */
-void HASH_StartDigest(void)
-{
- /* Start the Digest calculation */
- HASH->STR |= HASH_STR_DCAL;
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group3 Context swapping functions
- * @brief Context swapping functions
- *
-@verbatim
- ===============================================================================
- ##### Context swapping functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to save and store HASH Context
-
- [..] It is possible to interrupt a HASH/HMAC process to perform another processing
- with a higher priority, and to complete the interrupted process later on, when
- the higher priority task is complete. To do so, the context of the interrupted
- task must be saved from the HASH registers to memory, and then be restored
- from memory to the HASH registers.
-
- (#) To save the current context, use HASH_SaveContext() function
- (#) To restore the saved context, use HASH_RestoreContext() function
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Save the Hash peripheral Context.
- * @note The context can be saved only when no block is currently being
- * processed. So user must wait for DINIS = 1 (the last block has been
- * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not
- * full and no processing is ongoing).
- * @param HASH_ContextSave: pointer to a HASH_Context structure that contains
- * the repository for current context.
- * @retval None
- */
-void HASH_SaveContext(HASH_Context* HASH_ContextSave)
-{
- uint8_t i = 0;
-
- /* save context registers */
- HASH_ContextSave->HASH_IMR = HASH->IMR;
- HASH_ContextSave->HASH_STR = HASH->STR;
- HASH_ContextSave->HASH_CR = HASH->CR;
- for(i=0; i<=53;i++)
- {
- HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i];
- }
-}
-
-/**
- * @brief Restore the Hash peripheral Context.
- * @note After calling this function, user can restart the processing from the
- * point where it has been interrupted.
- * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains
- * the repository for saved context.
- * @retval None
- */
-void HASH_RestoreContext(HASH_Context* HASH_ContextRestore)
-{
- uint8_t i = 0;
-
- /* restore context registers */
- HASH->IMR = HASH_ContextRestore->HASH_IMR;
- HASH->STR = HASH_ContextRestore->HASH_STR;
- HASH->CR = HASH_ContextRestore->HASH_CR;
-
- /* Initialize the hash processor */
- HASH->CR |= HASH_CR_INIT;
-
- /* continue restoring context registers */
- for(i=0; i<=53;i++)
- {
- HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i];
- }
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group4 HASH's DMA interface Configuration function
- * @brief HASH's DMA interface Configuration function
- *
-@verbatim
- ===============================================================================
- ##### HASH's DMA interface Configuration function #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the DMA interface for
- HASH/ HMAC data input transfer.
-
- [..] When the DMA mode is enabled (using the HASH_DMACmd() function), data can be
- sent to the IN FIFO using the DMA peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables auto-start message padding and
- * calculation of the final message digest at the end of DMA transfer.
- * @param NewState: new state of the selected HASH DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HASH_AutoStartDigest(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the auto start of the final message digest at the end of DMA transfer */
- HASH->CR &= ~HASH_CR_MDMAT;
- }
- else
- {
- /* Disable the auto start of the final message digest at the end of DMA transfer */
- HASH->CR |= HASH_CR_MDMAT;
- }
-}
-
-/**
- * @brief Enables or disables the HASH DMA interface.
- * @note The DMA is disabled by hardware after the end of transfer.
- * @param NewState: new state of the selected HASH DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HASH_DMACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the HASH DMA request */
- HASH->CR |= HASH_CR_DMAE;
- }
- else
- {
- /* Disable the HASH DMA request */
- HASH->CR &= ~HASH_CR_DMAE;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup HASH_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the HASH Interrupts and
- to get the status and clear flags and Interrupts pending bits.
-
- [..] The HASH provides 2 Interrupts sources and 5 Flags:
-
- *** Flags : ***
- ===============
- [..]
- (#) HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO
- which means that a new block (512 bit) can be entered into the input buffer.
-
- (#) HASH_FLAG_DCIS : set when Digest calculation is complete
-
- (#) HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or
- a transfer is ongoing. This Flag is cleared only by hardware.
-
- (#) HASH_FLAG_BUSY : set when The hash core is processing a block of data
- This Flag is cleared only by hardware.
-
- (#) HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that
- the Data IN FIFO contains at least one word of data. This Flag is cleared
- only by hardware.
-
- *** Interrupts : ***
- ====================
- [..]
- (#) HASH_IT_DINI : if enabled, this interrupt source is pending when 16
- locations are free in the Data IN FIFO which means that a new block (512 bit)
- can be entered into the input buffer. This interrupt source is cleared using
- HASH_ClearITPendingBit(HASH_IT_DINI) function.
-
- (#) HASH_IT_DCI : if enabled, this interrupt source is pending when Digest
- calculation is complete. This interrupt source is cleared using
- HASH_ClearITPendingBit(HASH_IT_DCI) function.
-
- *** Managing the HASH controller events : ***
- =============================================
- [..] The user should identify which mode will be used in his application to manage
- the HASH controller events: Polling mode or Interrupt mode.
-
- (#) In the Polling Mode it is advised to use the following functions:
- (++) HASH_GetFlagStatus() : to check if flags events occur.
- (++) HASH_ClearFlag() : to clear the flags events.
-
- (#) In the Interrupt Mode it is advised to use the following functions:
- (++) HASH_ITConfig() : to enable or disable the interrupt source.
- (++) HASH_GetITStatus() : to check if Interrupt occurs.
- (++) HASH_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified HASH interrupts.
- * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg HASH_IT_DINI: Data Input interrupt
- * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
- * @param NewState: new state of the specified HASH interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_HASH_IT(HASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected HASH interrupt */
- HASH->IMR |= HASH_IT;
- }
- else
- {
- /* Disable the selected HASH interrupt */
- HASH->IMR &= (uint32_t)(~HASH_IT);
- }
-}
-
-/**
- * @brief Checks whether the specified HASH flag is set or not.
- * @param HASH_FLAG: specifies the HASH flag to check.
- * This parameter can be one of the following values:
- * @arg HASH_FLAG_DINIS: Data input interrupt status flag
- * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag
- * @arg HASH_FLAG_BUSY: Busy flag
- * @arg HASH_FLAG_DMAS: DMAS Status flag
- * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag
- * @retval The new state of HASH_FLAG (SET or RESET)
- */
-FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tempreg = 0;
-
- /* Check the parameters */
- assert_param(IS_HASH_GET_FLAG(HASH_FLAG));
-
- /* check if the FLAG is in CR register */
- if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint32_t)RESET )
- {
- tempreg = HASH->CR;
- }
- else /* The FLAG is in SR register */
- {
- tempreg = HASH->SR;
- }
-
- /* Check the status of the specified HASH flag */
- if ((tempreg & HASH_FLAG) != (uint32_t)RESET)
- {
- /* HASH is set */
- bitstatus = SET;
- }
- else
- {
- /* HASH_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the HASH_FLAG status */
- return bitstatus;
-}
-/**
- * @brief Clears the HASH flags.
- * @param HASH_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg HASH_FLAG_DINIS: Data Input Flag
- * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag
- * @retval None
- */
-void HASH_ClearFlag(uint32_t HASH_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG));
-
- /* Clear the selected HASH flags */
- HASH->SR = ~(uint32_t)HASH_FLAG;
-}
-/**
- * @brief Checks whether the specified HASH interrupt has occurred or not.
- * @param HASH_IT: specifies the HASH interrupt source to check.
- * This parameter can be one of the following values:
- * @arg HASH_IT_DINI: Data Input interrupt
- * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
- * @retval The new state of HASH_IT (SET or RESET).
- */
-ITStatus HASH_GetITStatus(uint32_t HASH_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_HASH_GET_IT(HASH_IT));
-
-
- /* Check the status of the specified HASH interrupt */
- tmpreg = HASH->SR;
-
- if (((HASH->IMR & tmpreg) & HASH_IT) != RESET)
- {
- /* HASH_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* HASH_IT is reset */
- bitstatus = RESET;
- }
- /* Return the HASH_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the HASH interrupt pending bit(s).
- * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear.
- * This parameter can be any combination of the following values:
- * @arg HASH_IT_DINI: Data Input interrupt
- * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
- * @retval None
- */
-void HASH_ClearITPendingBit(uint32_t HASH_IT)
-{
- /* Check the parameters */
- assert_param(IS_HASH_IT(HASH_IT));
-
- /* Clear the selected HASH interrupt pending bit */
- HASH->SR = (uint32_t)(~HASH_IT);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
deleted file mode 100644
index f7549dec..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_hash_md5.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides high level functions to compute the HASH MD5 and
- * HMAC MD5 Digest of an input message.
- * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
- * peripheral.
- *
-@verbatim
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable The HASH controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
-
- (#) Calculate the HASH MD5 Digest using HASH_MD5() function.
-
- (#) Calculate the HMAC MD5 Digest using HMAC_MD5() function.
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hash.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup HASH
- * @brief HASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HASH_Private_Functions
- * @{
- */
-
-/** @defgroup HASH_Group6 High Level SHA1 functions
- * @brief High Level SHA1 Hash and HMAC functions
- *
-@verbatim
- ===============================================================================
- ##### High Level SHA1 Hash and HMAC functions #####
- ===============================================================================
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Compute the HASH SHA1 digest.
- * @param Input: pointer to the Input buffer to be treated.
- * @param Ilen: length of the Input buffer.
- * @param Output: the returned digest
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: digest computation done
- * - ERROR: digest computation failed
- */
-ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
-{
- HASH_InitTypeDef SHA1_HASH_InitStructure;
- HASH_MsgDigest SHA1_MessageDigest;
- __IO uint16_t nbvalidbitsdata = 0;
- uint32_t i = 0;
- __IO uint32_t counter = 0;
- uint32_t busystatus = 0;
- ErrorStatus status = SUCCESS;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
- /* Number of valid bits in last word of the Input data */
- nbvalidbitsdata = 8 * (Ilen % 4);
-
- /* HASH peripheral initialization */
- HASH_DeInit();
-
- /* HASH Configuration */
- SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
- SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
- SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
- HASH_Init(&SHA1_HASH_InitStructure);
-
- /* Configure the number of valid bits in last word of the data */
- HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
-
- /* Write the Input block in the IN FIFO */
- for(i=0; i 64)
- {
- /* HMAC long Key */
- SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
- }
- else
- {
- /* HMAC short Key */
- SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
- }
- HASH_Init(&SHA1_HASH_InitStructure);
-
- /* Configure the number of valid bits in last word of the Key */
- HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
-
- /* Write the Key */
- for(i=0; iGPIO_Mode = GPIO_Mode_AF
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function
- Recommended configuration is Push-Pull, Pull-up, Open-Drain.
- Add an external pull up if necessary (typically 4.7 KOhm).
-
- (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged
- Address using the I2C_Init() function.
-
- (#) Optionally you can enable/configure the following parameters without
- re-initialization (i.e there is no need to call again I2C_Init() function):
- (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function
- (++) Enable the dual addressing mode using I2C_DualAddressCmd() function
- (++) Enable the general call using the I2C_GeneralCallCmd() function
- (++) Enable the clock stretching using I2C_StretchClockCmd() function
- (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()
- function.
- (++) Configure the NACK position for Master Receiver mode in case of
- 2 bytes reception using the function I2C_NACKPositionConfig().
- (++) Enable the PEC Calculation using I2C_CalculatePEC() function
- (++) For SMBus Mode:
- (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function
- (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- I2C_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function
- (++) Active the needed channel Request using I2C_DMACmd() or
- I2C_DMALastTransferCmd() function.
- -@@- When using DMA mode, I2C interrupts may be used at the same time to
- control the communication flow (Start/Stop/Ack... events and errors).
-
- (#) Enable the I2C using the I2C_Cmd() function.
-
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
- transfers.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_i2c.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup I2C
- * @brief I2C driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed));
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
- assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
-
-/*---------------------------- I2Cx CR2 Configuration ------------------------*/
- /* Get the I2Cx CR2 value */
- tmpreg = I2Cx->CR2;
- /* Clear frequency FREQ[5:0] bits */
- tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);
- /* Get pclk1 frequency value */
- RCC_GetClocksFreq(&rcc_clocks);
- pclk1 = rcc_clocks.PCLK1_Frequency;
- /* Set frequency bits depending on pclk1 value */
- freqrange = (uint16_t)(pclk1 / 1000000);
- tmpreg |= freqrange;
- /* Write to I2Cx CR2 */
- I2Cx->CR2 = tmpreg;
-
-/*---------------------------- I2Cx CCR Configuration ------------------------*/
- /* Disable the selected I2C peripheral to configure TRISE */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
- /* Reset tmpreg value */
- /* Clear F/S, DUTY and CCR[11:0] bits */
- tmpreg = 0;
-
- /* Configure speed in standard mode */
- if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
- {
- /* Standard mode speed calculate */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
- /* Test if CCR value is under 0x4*/
- if (result < 0x04)
- {
- /* Set minimum allowed value */
- result = 0x04;
- }
- /* Set speed value for standard mode */
- tmpreg |= result;
- /* Set Maximum Rise Time for standard mode */
- I2Cx->TRISE = freqrange + 1;
- }
- /* Configure speed in fast mode */
- /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral
- input clock) must be a multiple of 10 MHz */
- else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
- {
- if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
- {
- /* Fast mode speed calculate: Tlow/Thigh = 2 */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
- }
- else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
- {
- /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
- /* Set DUTY bit */
- result |= I2C_DutyCycle_16_9;
- }
-
- /* Test if CCR value is under 0x1*/
- if ((result & I2C_CCR_CCR) == 0)
- {
- /* Set minimum allowed value */
- result |= (uint16_t)0x0001;
- }
- /* Set speed value and set F/S bit for fast mode */
- tmpreg |= (uint16_t)(result | I2C_CCR_FS);
- /* Set Maximum Rise Time for fast mode */
- I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
- }
-
- /* Write to I2Cx CCR */
- I2Cx->CCR = tmpreg;
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
-
-/*---------------------------- I2Cx CR1 Configuration ------------------------*/
- /* Get the I2Cx CR1 value */
- tmpreg = I2Cx->CR1;
- /* Clear ACK, SMBTYPE and SMBUS bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure I2Cx: mode and acknowledgement */
- /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
- /* Set ACK bit according to I2C_Ack value */
- tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
- /* Write to I2Cx CR1 */
- I2Cx->CR1 = tmpreg;
-
-/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
- /* Set I2Cx Own Address1 and acknowledged address */
- I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
-}
-
-/**
- * @brief Fills each I2C_InitStruct member with its default value.
- * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
-{
-/*---------------- Reset I2C init structure parameters values ----------------*/
- /* initialize the I2C_ClockSpeed member */
- I2C_InitStruct->I2C_ClockSpeed = 5000;
- /* Initialize the I2C_Mode member */
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
- /* Initialize the I2C_DutyCycle member */
- I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
- /* Initialize the I2C_OwnAddress1 member */
- I2C_InitStruct->I2C_OwnAddress1 = 0;
- /* Initialize the I2C_Ack member */
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
- /* Initialize the I2C_AcknowledgedAddress member */
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-}
-
-/**
- * @brief Enables or disables the specified I2C peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
- }
- else
- {
- /* Disable the selected I2C peripheral */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
- }
-}
-
-/**
- * @brief Enables or disables the Analog filter of I2C peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the Analog filter.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function should be called before initializing and enabling
- the I2C Peripheral.
- * @retval None
- */
-void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the analog filter */
- I2Cx->FLTR &= (uint16_t)~((uint16_t)I2C_FLTR_ANOFF);
- }
- else
- {
- /* Disable the analog filter */
- I2Cx->FLTR |= I2C_FLTR_ANOFF;
- }
-}
-
-/**
- * @brief Configures the Digital noise filter of I2C peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_DigitalFilter: Coefficient of digital noise filter.
- * This parameter can be a number between 0x00 and 0x0F.
- * @note This function should be called before initializing and enabling
- the I2C Peripheral.
- * @retval None
- */
-void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter)
-{
- uint16_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DIGITAL_FILTER(I2C_DigitalFilter));
-
- /* Get the old register value */
- tmpreg = I2Cx->FLTR;
-
- /* Reset I2Cx DNF bit [3:0] */
- tmpreg &= (uint16_t)~((uint16_t)I2C_FLTR_DNF);
-
- /* Set I2Cx DNF coefficient */
- tmpreg |= (uint16_t)((uint16_t)I2C_DigitalFilter & I2C_FLTR_DNF);
-
- /* Store the new register value */
- I2Cx->FLTR = tmpreg;
-}
-
-/**
- * @brief Generates I2Cx communication START condition.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C START condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Generate a START condition */
- I2Cx->CR1 |= I2C_CR1_START;
- }
- else
- {
- /* Disable the START condition generation */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);
- }
-}
-
-/**
- * @brief Generates I2Cx communication STOP condition.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C STOP condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Generate a STOP condition */
- I2Cx->CR1 |= I2C_CR1_STOP;
- }
- else
- {
- /* Disable the STOP condition generation */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);
- }
-}
-
-/**
- * @brief Transmits the address byte to select the slave device.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param Address: specifies the slave address which will be transmitted
- * @param I2C_Direction: specifies whether the I2C device will be a Transmitter
- * or a Receiver.
- * This parameter can be one of the following values
- * @arg I2C_Direction_Transmitter: Transmitter mode
- * @arg I2C_Direction_Receiver: Receiver mode
- * @retval None.
- */
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DIRECTION(I2C_Direction));
- /* Test on the direction to set/reset the read/write bit */
- if (I2C_Direction != I2C_Direction_Transmitter)
- {
- /* Set the address bit0 for read */
- Address |= I2C_OAR1_ADD0;
- }
- else
- {
- /* Reset the address bit0 for write */
- Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);
- }
- /* Send the address */
- I2Cx->DR = Address;
-}
-
-/**
- * @brief Enables or disables the specified I2C acknowledge feature.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C Acknowledgement.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the acknowledgement */
- I2Cx->CR1 |= I2C_CR1_ACK;
- }
- else
- {
- /* Disable the acknowledgement */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);
- }
-}
-
-/**
- * @brief Configures the specified I2C own address2.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param Address: specifies the 7bit I2C own address2.
- * @retval None.
- */
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
-{
- uint16_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Get the old register value */
- tmpreg = I2Cx->OAR2;
-
- /* Reset I2Cx Own address2 bit [7:1] */
- tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);
-
- /* Set I2Cx Own address2 */
- tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
-
- /* Store the new register value */
- I2Cx->OAR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the specified I2C dual addressing mode.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C dual addressing mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable dual addressing mode */
- I2Cx->OAR2 |= I2C_OAR2_ENDUAL;
- }
- else
- {
- /* Disable dual addressing mode */
- I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C general call feature.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C General call.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable generall call */
- I2Cx->CR1 |= I2C_CR1_ENGC;
- }
- else
- {
- /* Disable generall call */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C software reset.
- * @note When software reset is enabled, the I2C IOs are released (this can
- * be useful to recover from bus errors).
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C software reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Peripheral under reset */
- I2Cx->CR1 |= I2C_CR1_SWRST;
- }
- else
- {
- /* Peripheral not under reset */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C Clock stretching.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Clock stretching.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState == DISABLE)
- {
- /* Enable the selected I2C Clock stretching */
- I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
- }
- else
- {
- /* Disable the selected I2C Clock stretching */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);
- }
-}
-
-/**
- * @brief Selects the specified I2C fast mode duty cycle.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_DutyCycle: specifies the fast mode duty cycle.
- * This parameter can be one of the following values:
- * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
- * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
- * @retval None
- */
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
- if (I2C_DutyCycle != I2C_DutyCycle_16_9)
- {
- /* I2C fast mode Tlow/Thigh=2 */
- I2Cx->CCR &= I2C_DutyCycle_2;
- }
- else
- {
- /* I2C fast mode Tlow/Thigh=16/9 */
- I2Cx->CCR |= I2C_DutyCycle_16_9;
- }
-}
-
-/**
- * @brief Selects the specified I2C NACK position in master receiver mode.
- * @note This function is useful in I2C Master Receiver mode when the number
- * of data to be received is equal to 2. In this case, this function
- * should be called (with parameter I2C_NACKPosition_Next) before data
- * reception starts,as described in the 2-byte reception procedure
- * recommended in Reference Manual in Section: Master receiver.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_NACKPosition: specifies the NACK position.
- * This parameter can be one of the following values:
- * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
- * received byte.
- * @arg I2C_NACKPosition_Current: indicates that current byte is the last
- * received byte.
- *
- * @note This function configures the same bit (POS) as I2C_PECPositionConfig()
- * but is intended to be used in I2C mode while I2C_PECPositionConfig()
- * is intended to used in SMBUS mode.
- *
- * @retval None
- */
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
-
- /* Check the input parameter */
- if (I2C_NACKPosition == I2C_NACKPosition_Next)
- {
- /* Next byte in shift register is the last received byte */
- I2Cx->CR1 |= I2C_NACKPosition_Next;
- }
- else
- {
- /* Current byte in shift register is the last received byte */
- I2Cx->CR1 &= I2C_NACKPosition_Current;
- }
-}
-
-/**
- * @brief Drives the SMBusAlert pin high or low for the specified I2C.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_SMBusAlert: specifies SMBAlert pin level.
- * This parameter can be one of the following values:
- * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
- * @arg I2C_SMBusAlert_High: SMBAlert pin driven high
- * @retval None
- */
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
- if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
- {
- /* Drive the SMBusAlert pin Low */
- I2Cx->CR1 |= I2C_SMBusAlert_Low;
- }
- else
- {
- /* Drive the SMBusAlert pin High */
- I2Cx->CR1 &= I2C_SMBusAlert_High;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C ARP.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx ARP.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C ARP */
- I2Cx->CR1 |= I2C_CR1_ENARP;
- }
- else
- {
- /* Disable the selected I2C ARP */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup I2C_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sends a data byte through the I2Cx peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param Data: Byte to be transmitted..
- * @retval None
- */
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Write in the DR register the data to be sent */
- I2Cx->DR = Data;
-}
-
-/**
- * @brief Returns the most recent received data by the I2Cx peripheral.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @retval The value of the received data.
- */
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Return the data in the DR register */
- return (uint8_t)I2Cx->DR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group3 PEC management functions
- * @brief PEC management functions
- *
-@verbatim
- ===============================================================================
- ##### PEC management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified I2C PEC transfer.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C PEC transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC transmission */
- I2Cx->CR1 |= I2C_CR1_PEC;
- }
- else
- {
- /* Disable the selected I2C PEC transmission */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);
- }
-}
-
-/**
- * @brief Selects the specified I2C PEC position.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_PECPosition: specifies the PEC position.
- * This parameter can be one of the following values:
- * @arg I2C_PECPosition_Next: indicates that the next byte is PEC
- * @arg I2C_PECPosition_Current: indicates that current byte is PEC
- *
- * @note This function configures the same bit (POS) as I2C_NACKPositionConfig()
- * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig()
- * is intended to used in I2C mode.
- *
- * @retval None
- */
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
- if (I2C_PECPosition == I2C_PECPosition_Next)
- {
- /* Next byte in shift register is PEC */
- I2Cx->CR1 |= I2C_PECPosition_Next;
- }
- else
- {
- /* Current byte in shift register is PEC */
- I2Cx->CR1 &= I2C_PECPosition_Current;
- }
-}
-
-/**
- * @brief Enables or disables the PEC value calculation of the transferred bytes.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx PEC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC calculation */
- I2Cx->CR1 |= I2C_CR1_ENPEC;
- }
- else
- {
- /* Disable the selected I2C PEC calculation */
- I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);
- }
-}
-
-/**
- * @brief Returns the PEC value for the specified I2C.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @retval The PEC value.
- */
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Return the selected I2C PEC value */
- return ((I2Cx->SR2) >> 8);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group4 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
- This section provides functions allowing to configure the I2C DMA channels
- requests.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified I2C DMA requests.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C DMA requests */
- I2Cx->CR2 |= I2C_CR2_DMAEN;
- }
- else
- {
- /* Disable the selected I2C DMA requests */
- I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);
- }
-}
-
-/**
- * @brief Specifies that the next DMA transfer is the last one.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param NewState: new state of the I2C DMA last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Next DMA transfer is the last transfer */
- I2Cx->CR2 |= I2C_CR2_LAST;
- }
- else
- {
- /* Next DMA transfer is not the last transfer */
- I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group5 Interrupts events and flags management functions
- * @brief Interrupts, events and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts, events and flags management functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to configure the I2C Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
-
- ##### I2C State Monitoring Functions #####
- ===============================================================================
- [..]
- This I2C driver provides three different ways for I2C state monitoring
- depending on the application requirements and constraints:
-
-
- (#) Basic state monitoring (Using I2C_CheckEvent() function)
-
- It compares the status registers (SR1 and SR2) content to a given event
- (can be the combination of one or more flags).
- It returns SUCCESS if the current status includes the given flags
- and returns ERROR if one or more flags are missing in the current status.
-
- (++) When to use
- (+++) This function is suitable for most applications as well as for startup
- activity since the events are fully described in the product reference
- manual (RM0090).
- (+++) It is also suitable for users who need to define their own events.
-
- (++) Limitations
- If an error occurs (ie. error flags are set besides to the monitored
- flags), the I2C_CheckEvent() function may return SUCCESS despite
- the communication hold or corrupted real state.
- In this case, it is advised to use error interrupts to monitor
- the error events and handle them in the interrupt IRQ handler.
-
- -@@- For error management, it is advised to use the following functions:
- (+@@) I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
- Where x is the peripheral instance (I2C1, I2C2 ...)
- (+@@) I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
- I2Cx_ER_IRQHandler() function in order to determine which error occurred.
- (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- and/or I2C_GenerateStop() in order to clear the error flag and source
- and return to correct communication status.
-
-
- (#) Advanced state monitoring (Using the function I2C_GetLastEvent())
-
- Using the function I2C_GetLastEvent() which returns the image of both status
- registers in a single word (uint32_t) (Status Register 2 value is shifted left
- by 16 bits and concatenated to Status Register 1).
-
- (++) When to use
- (+++) This function is suitable for the same applications above but it
- allows to overcome the mentioned limitation of I2C_GetFlagStatus()
- function.
- (+++) The returned value could be compared to events already defined in
- the library (stm32f4xx_i2c.h) or to custom values defined by user.
- This function is suitable when multiple flags are monitored at the
- same time.
- (+++) At the opposite of I2C_CheckEvent() function, this function allows
- user to choose when an event is accepted (when all events flags are
- set and no other flags are set or just when the needed flags are set
- like I2C_CheckEvent() function.
-
- (++) Limitations
- (+++) User may need to define his own events.
- (+++) Same remark concerning the error management is applicable for this
- function if user decides to check only regular communication flags
- (and ignores error flags).
-
-
- (#) Flag-based state monitoring (Using the function I2C_GetFlagStatus())
-
- Using the function I2C_GetFlagStatus() which simply returns the status of
- one single flag (ie. I2C_FLAG_RXNE ...).
-
- (++) When to use
- (+++) This function could be used for specific applications or in debug
- phase.
- (+++) It is suitable when only one flag checking is needed (most I2C
- events are monitored through multiple flags).
- (++) Limitations:
- (+++) When calling this function, the Status register is accessed.
- Some flags are cleared when the status register is accessed.
- So checking the status of one Flag, may clear other ones.
- (+++) Function may need to be called twice or more in order to monitor
- one single event.
-
- For detailed description of Events, please refer to section I2C_Events in
- stm32f4xx_i2c.h file.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified I2C register and returns its value.
- * @param I2C_Register: specifies the register to read.
- * This parameter can be one of the following values:
- * @arg I2C_Register_CR1: CR1 register.
- * @arg I2C_Register_CR2: CR2 register.
- * @arg I2C_Register_OAR1: OAR1 register.
- * @arg I2C_Register_OAR2: OAR2 register.
- * @arg I2C_Register_DR: DR register.
- * @arg I2C_Register_SR1: SR1 register.
- * @arg I2C_Register_SR2: SR2 register.
- * @arg I2C_Register_CCR: CCR register.
- * @arg I2C_Register_TRISE: TRISE register.
- * @retval The value of the read register.
- */
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_REGISTER(I2C_Register));
-
- tmp = (uint32_t) I2Cx;
- tmp += I2C_Register;
-
- /* Return the selected register value */
- return (*(__IO uint16_t *) tmp);
-}
-
-/**
- * @brief Enables or disables the specified I2C interrupts.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_BUF: Buffer interrupt mask
- * @arg I2C_IT_EVT: Event interrupt mask
- * @arg I2C_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified I2C interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C interrupts */
- I2Cx->CR2 |= I2C_IT;
- }
- else
- {
- /* Disable the selected I2C interrupts */
- I2Cx->CR2 &= (uint16_t)~I2C_IT;
- }
-}
-
-/*
- ===============================================================================
- 1. Basic state monitoring
- ===============================================================================
- */
-
-/**
- * @brief Checks whether the last I2Cx Event is equal to the one passed
- * as parameter.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_EVENT: specifies the event to be checked.
- * This parameter can be one of the following values:
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1
- * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2
- * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3
- * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2
- * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4
- * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5
- * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6
- * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6
- * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2
- * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9
- *
- * @note For detailed description of Events, please refer to section I2C_Events
- * in stm32f4xx_i2c.h file.
- *
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Last event is equal to the I2C_EVENT
- * - ERROR: Last event is different from the I2C_EVENT
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
-{
- uint32_t lastevent = 0;
- uint32_t flag1 = 0, flag2 = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_EVENT(I2C_EVENT));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
- flag2 = I2Cx->SR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_MASK;
-
- /* Check whether the last event contains the I2C_EVENT */
- if ((lastevent & I2C_EVENT) == I2C_EVENT)
- {
- /* SUCCESS: last event is equal to I2C_EVENT */
- status = SUCCESS;
- }
- else
- {
- /* ERROR: last event is different from I2C_EVENT */
- status = ERROR;
- }
- /* Return status */
- return status;
-}
-
-/*
- ===============================================================================
- 2. Advanced state monitoring
- ===============================================================================
- */
-
-/**
- * @brief Returns the last I2Cx Event.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- *
- * @note For detailed description of Events, please refer to section I2C_Events
- * in stm32f4xx_i2c.h file.
- *
- * @retval The last event
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
-{
- uint32_t lastevent = 0;
- uint32_t flag1 = 0, flag2 = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
- flag2 = I2Cx->SR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_MASK;
-
- /* Return status */
- return lastevent;
-}
-
-/*
- ===============================================================================
- 3. Flag-based state monitoring
- ===============================================================================
- */
-
-/**
- * @brief Checks whether the specified I2C flag is set or not.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
- * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
- * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
- * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
- * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
- * @arg I2C_FLAG_BUSY: Bus busy flag
- * @arg I2C_FLAG_MSL: Master/Slave flag
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
- * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
- * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
- * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
- * @arg I2C_FLAG_BTF: Byte transfer finished flag
- * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
- * Address matched flag (Slave mode)"ENDAD"
- * @arg I2C_FLAG_SB: Start bit flag (Master mode)
- * @retval The new state of I2C_FLAG (SET or RESET).
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- FlagStatus bitstatus = RESET;
- __IO uint32_t i2creg = 0, i2cxbase = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
-
- /* Get the I2Cx peripheral base address */
- i2cxbase = (uint32_t)I2Cx;
-
- /* Read flag register index */
- i2creg = I2C_FLAG >> 28;
-
- /* Get bit[23:0] of the flag */
- I2C_FLAG &= FLAG_MASK;
-
- if(i2creg != 0)
- {
- /* Get the I2Cx SR1 register address */
- i2cxbase += 0x14;
- }
- else
- {
- /* Flag in I2Cx SR2 Register */
- I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
- /* Get the I2Cx SR2 register address */
- i2cxbase += 0x18;
- }
-
- if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
- {
- /* I2C_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the I2C_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's pending flags.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- *
- * @note STOPF (STOP detection) is cleared by software sequence: a read operation
- * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
- * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
- * @note ADD10 (10-bit header sent) is cleared by software sequence: a read
- * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
- * second byte of the address in DR register.
- * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read
- * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
- * read/write to I2C_DR register (I2C_SendData()).
- * @note ADDR (Address sent) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
- * I2C_SR2 register ((void)(I2Cx->SR2)).
- * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
- * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
- * register (I2C_SendData()).
- *
- * @retval None
- */
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- uint32_t flagpos = 0;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
- /* Get the I2C flag position */
- flagpos = I2C_FLAG & FLAG_MASK;
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @brief Checks whether the specified I2C interrupt has occurred or not.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2C_IT_SMBALERT: SMBus Alert flag
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_IT_PECERR: PEC error in reception flag
- * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_IT_AF: Acknowledge failure flag
- * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_IT_BERR: Bus error flag
- * @arg I2C_IT_TXE: Data register empty flag (Transmitter)
- * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
- * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
- * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
- * @arg I2C_IT_BTF: Byte transfer finished flag
- * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
- * Address matched flag (Slave mode)"ENDAD"
- * @arg I2C_IT_SB: Start bit flag (Master mode)
- * @retval The new state of I2C_IT (SET or RESET).
- */
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_IT(I2C_IT));
-
- /* Check if the interrupt source is enabled or not */
- enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;
-
- /* Get bit[23:0] of the flag */
- I2C_IT &= FLAG_MASK;
-
- /* Check the status of the specified I2C flag */
- if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
- {
- /* I2C_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_IT is reset */
- bitstatus = RESET;
- }
- /* Return the I2C_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's interrupt pending bits.
- * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_SMBALERT: SMBus Alert interrupt
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
- * @arg I2C_IT_PECERR: PEC error in reception interrupt
- * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
- * @arg I2C_IT_AF: Acknowledge failure interrupt
- * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
- * @arg I2C_IT_BERR: Bus error interrupt
- *
- * @note STOPF (STOP detection) is cleared by software sequence: a read operation
- * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
- * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
- * @note ADD10 (10-bit header sent) is cleared by software sequence: a read
- * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
- * byte of the address in I2C_DR register.
- * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read
- * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
- * read/write to I2C_DR register (I2C_SendData()).
- * @note ADDR (Address sent) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
- * I2C_SR2 register ((void)(I2Cx->SR2)).
- * @note SB (Start Bit) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
- * I2C_DR register (I2C_SendData()).
- * @retval None
- */
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- uint32_t flagpos = 0;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));
-
- /* Get the I2C flag position */
- flagpos = I2C_IT & FLAG_MASK;
-
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
deleted file mode 100644
index 5f6cb547..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_iwdg.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Independent watchdog (IWDG) peripheral:
- * + Prescaler and Counter configuration
- * + IWDG activation
- * + Flag management
- *
- @verbatim
- ===============================================================================
- ##### IWDG features #####
- ===============================================================================
- [..]
- The IWDG can be started by either software or hardware (configurable
- through option byte).
-
- The IWDG is clocked by its own dedicated low-speed clock (LSI) and
- thus stays active even if the main clock fails.
- Once the IWDG is started, the LSI is forced ON and cannot be disabled
- (LSI cannot be disabled too), and the counter starts counting down from
- the reset value of 0xFFF. When it reaches the end of count value (0x000)
- a system reset is generated.
- The IWDG counter should be reloaded at regular intervals to prevent
- an MCU reset.
-
- The IWDG is implemented in the VDD voltage domain that is still functional
- in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
-
- IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
- reset occurs.
-
- Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
- The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
- devices provide the capability to measure the LSI frequency (LSI clock
- connected internally to TIM5 CH4 input capture). The measured value
- can be used to have an IWDG timeout with an acceptable accuracy.
- For more information, please refer to the STM32F4xx Reference manual
-
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable write access to IWDG_PR and IWDG_RLR registers using
- IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
-
- (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function
-
- (#) Configure the IWDG counter value using IWDG_SetReload() function.
- This value will be loaded in the IWDG counter each time the counter
- is reloaded, then the IWDG will start counting down from this value.
-
- (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used
- in software mode (no need to enable the LSI, it will be enabled
- by hardware)
-
- (#) Then the application program must reload the IWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
- IWDG_ReloadCounter() function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_pwr.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup PWR
- * @brief PWR driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* --------- PWR registers bit address in the alias region ---------- */
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-
-/* Alias word address of DBP bit */
-#define CR_OFFSET (PWR_OFFSET + 0x00)
-#define DBP_BitNumber 0x08
-#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BitNumber 0x04
-#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
-
-/* Alias word address of FPDS bit */
-#define FPDS_BitNumber 0x09
-#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
-
-/* Alias word address of PMODE bit */
-#define PMODE_BitNumber 0x0E
-#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
-
-
-/* --- CSR Register ---*/
-
-/* Alias word address of EWUP bit */
-#define CSR_OFFSET (PWR_OFFSET + 0x04)
-#define EWUP_BitNumber 0x08
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
-
-/* Alias word address of BRE bit */
-#define BRE_BitNumber 0x09
-#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
-
-/* ------------------ PWR registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
-#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
-#define CR_VOS_MASK ((uint32_t)0xFFFF3FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Private_Functions
- * @{
- */
-
-/** @defgroup PWR_Group1 Backup Domain Access function
- * @brief Backup Domain Access function
- *
-@verbatim
- ===============================================================================
- ##### Backup Domain Access function #####
- ===============================================================================
- [..]
- After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted
- write accesses.
- To enable access to the RTC Domain and RTC registers, proceed as follows:
- (+) Enable the Power Controller (PWR) APB1 interface clock using the
- RCC_APB1PeriphClockCmd() function.
- (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the PWR peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void PWR_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
-}
-
-/**
- * @brief Enables or disables access to the backup domain (RTC registers, RTC
- * backup data registers and backup SRAM).
- * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @param NewState: new state of the access to the backup domain.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_BackupAccessCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group2 PVD configuration functions
- * @brief PVD configuration functions
- *
-@verbatim
- ===============================================================================
- ##### PVD configuration functions #####
- ===============================================================================
- [..]
- (+) The PVD is used to monitor the VDD power supply by comparing it to a
- threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
- (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
- than the PVD threshold. This event is internally connected to the EXTI
- line16 and can generate an interrupt if enabled through the EXTI registers.
- (+) The PVD is stopped in Standby mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @param PWR_PVDLevel: specifies the PVD detection level
- * This parameter can be one of the following values:
- * @arg PWR_PVDLevel_0
- * @arg PWR_PVDLevel_1
- * @arg PWR_PVDLevel_2
- * @arg PWR_PVDLevel_3
- * @arg PWR_PVDLevel_4
- * @arg PWR_PVDLevel_5
- * @arg PWR_PVDLevel_6
- * @arg PWR_PVDLevel_7
- * @note Refer to the electrical characteristics of your device datasheet for
- * more details about the voltage threshold corresponding to each
- * detection level.
- * @retval None
- */
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
-
- tmpreg = PWR->CR;
-
- /* Clear PLS[7:5] bits */
- tmpreg &= CR_PLS_MASK;
-
- /* Set PLS[7:5] bits according to PWR_PVDLevel value */
- tmpreg |= PWR_PVDLevel;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Power Voltage Detector(PVD).
- * @param NewState: new state of the PVD.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_PVDCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group3 WakeUp pin configuration functions
- * @brief WakeUp pin configuration functions
- *
-@verbatim
- ===============================================================================
- ##### WakeUp pin configuration functions #####
- ===============================================================================
- [..]
- (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
- forced in input pull down configuration and is active on rising edges.
- (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the WakeUp Pin functionality.
- * @param NewState: new state of the WakeUp Pin functionality.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_WakeUpPinCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions
- * @brief Main and Backup Regulators configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Main and Backup Regulators configuration functions #####
- ===============================================================================
- [..]
- (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
- the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
- retained even in Standby or VBAT mode when the low power backup regulator
- is enabled. It can be considered as an internal EEPROM when VBAT is
- always present. You can use the PWR_BackupRegulatorCmd() function to
- enable the low power backup regulator and use the PWR_GetFlagStatus
- (PWR_FLAG_BRR) to check if it is ready or not.
-
- (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
- the backup SRAM is powered from VDD which replaces the VBAT power supply to
- save battery life.
-
- (+) The backup SRAM is not mass erased by an tamper event. It is read
- protected to prevent confidential data, such as cryptographic private
- key, from being accessed. The backup SRAM can be erased only through
- the Flash interface when a protection level change from level 1 to
- level 0 is requested.
- -@- Refer to the description of Read protection (RDP) in the Flash
- programming manual.
-
- (+) The main internal regulator can be configured to have a tradeoff between
- performance and power consumption when the device does not operate at
- the maximum frequency. This is done through PWR_MainRegulatorModeConfig()
- function which configure VOS bit in PWR_CR register:
- (++) When this bit is set (Regulator voltage output Scale 1 mode selected)
- the System frequency can go up to 168 MHz.
- (++) When this bit is reset (Regulator voltage output Scale 2 mode selected)
- the System frequency can go up to 144 MHz.
-
- Refer to the datasheets for more details.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the Backup Regulator.
- * @param NewState: new state of the Backup Regulator.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_BackupRegulatorCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the main internal regulator output voltage.
- * @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve
- * a tradeoff between performance and power consumption when the device does
- * not operate at the maximum frequency (refer to the datasheets for more details).
- * This parameter can be one of the following values:
- * @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode,
- * System frequency up to 168 MHz.
- * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode,
- * System frequency up to 144 MHz.
- * @arg PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode,
- * System frequency up to 120 MHz
- * @retval None
- */
-void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
-
- tmpreg = PWR->CR;
-
- /* Clear VOS[15:14] bits */
- tmpreg &= CR_VOS_MASK;
-
- /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */
- tmpreg |= PWR_Regulator_Voltage;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group5 FLASH Power Down configuration functions
- * @brief FLASH Power Down configuration functions
- *
-@verbatim
- ===============================================================================
- ##### FLASH Power Down configuration functions #####
- ===============================================================================
- [..]
- (+) By setting the FPDS bit in the PWR_CR register by using the
- PWR_FlashPowerDownCmd() function, the Flash memory also enters power
- down mode when the device enters Stop mode. When the Flash memory
- is in power down mode, an additional startup delay is incurred when
- waking up from Stop mode.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the Flash Power Down in STOP mode.
- * @param NewState: new state of the Flash power mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_FlashPowerDownCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group6 Low Power modes configuration functions
- * @brief Low Power modes configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Low Power modes configuration functions #####
- ===============================================================================
- [..]
- The devices feature 3 low-power modes:
- (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
- (+) Stop mode: all clocks are stopped, regulator running, regulator
- in low power mode
- (+) Standby mode: 1.2V domain powered off.
-
- *** Sleep mode ***
- ==================
- [..]
- (+) Entry:
- (++) The Sleep mode is entered by using the __WFI() or __WFE() functions.
- (+) Exit:
- (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
- controller (NVIC) can wake up the device from Sleep mode.
-
- *** Stop mode ***
- =================
- [..]
- In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
- and the HSE RC oscillators are disabled. Internal SRAM and register contents
- are preserved.
- The voltage regulator can be configured either in normal or low-power mode.
- To minimize the consumption In Stop mode, FLASH can be powered off before
- entering the Stop mode. It can be switched on again by software after exiting
- the Stop mode using the PWR_FlashPowerDownCmd() function.
-
- (+) Entry:
- (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
- function with regulator in LowPower or with Regulator ON.
- (+) Exit:
- (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
-
- *** Standby mode ***
- ====================
- [..]
- The Standby mode allows to achieve the lowest power consumption. It is based
- on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
- The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
- the HSE oscillator are also switched off. SRAM and register contents are lost
- except for the RTC registers, RTC backup registers, backup SRAM and Standby
- circuitry.
-
- The voltage regulator is OFF.
-
- (+) Entry:
- (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
- (+) Exit:
- (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
- tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
-
- *** Auto-wakeup (AWU) from low-power mode ***
- =============================================
- [..]
- The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
- Wakeup event, a tamper event, a time-stamp event, or a comparator event,
- without depending on an external interrupt (Auto-wakeup mode).
-
- (#) RTC auto-wakeup (AWU) from the Stop mode
-
- (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
- (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
- and RTC_AlarmCmd() functions.
- (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
- is necessary to:
- (+++) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
- function
- (+++) Configure the RTC to detect the tamper or time stamp event using the
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
- functions.
- (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
- (+++) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
- RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
-
- (#) RTC auto-wakeup (AWU) from the Standby mode
-
- (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
- (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
- and RTC_AlarmCmd() functions.
- (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
- is necessary to:
- (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
- function
- (+++) Configure the RTC to detect the tamper or time stamp event using the
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
- functions.
- (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
- (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
- RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enters STOP mode.
- *
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock.
- * @note When the voltage regulator operates in low power mode, an additional
- * startup delay is incurred when waking up from Stop mode.
- * By keeping the internal regulator ON during Stop mode, the consumption
- * is higher although the startup time is reduced.
- *
- * @param PWR_Regulator: specifies the regulator state in STOP mode.
- * This parameter can be one of the following values:
- * @arg PWR_Regulator_ON: STOP mode with regulator ON
- * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
- * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
- * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
- * @retval None
- */
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
-
- /* Select the regulator state in STOP mode ---------------------------------*/
- tmpreg = PWR->CR;
- /* Clear PDDS and LPDSR bits */
- tmpreg &= CR_DS_MASK;
-
- /* Set LPDSR bit according to PWR_Regulator value */
- tmpreg |= PWR_Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Select STOP mode entry --------------------------------------------------*/
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __WFE();
- }
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-}
-
-/**
- * @brief Enters STANDBY mode.
- * @note In Standby mode, all I/O pins are high impedance except for:
- * - Reset pad (still available)
- * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
- * Alarm out, or RTC clock calibration out.
- * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
- * - WKUP pin 1 (PA0) if enabled.
- * @param None
- * @retval None
- */
-void PWR_EnterSTANDBYMode(void)
-{
- /* Clear Wakeup flag */
- PWR->CR |= PWR_CR_CWUF;
-
- /* Select STANDBY mode */
- PWR->CR |= PWR_CR_PDDS;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-/* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM )
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group7 Flags management functions
- * @brief Flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified PWR flag is set or not.
- * @param PWR_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
- * was received from the WKUP pin or from the RTC alarm (Alarm A
- * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
- * An additional wakeup event is detected if the WKUP pin is enabled
- * (by setting the EWUP bit) when the WKUP pin level is already high.
- * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
- * resumed from StandBy mode.
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
- * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode
- * For this reason, this bit is equal to 0 after Standby or reset
- * until the PVDE bit is set.
- * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
- * when the device wakes up from Standby mode or by a system reset
- * or power reset.
- * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
- * scaling output selection is ready.
- * @retval The new state of PWR_FLAG (SET or RESET).
- */
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
-
- if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the PWR's pending flags.
- * @param PWR_FLAG: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- * @retval None
- */
-void PWR_ClearFlag(uint32_t PWR_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
-
- PWR->CR |= PWR_FLAG << 2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
deleted file mode 100644
index 967798e4..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
+++ /dev/null
@@ -1,1872 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_rcc.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Reset and clock control (RCC) peripheral:
- * + Internal/external clocks, PLL, CSS and MCO configuration
- * + System, AHB and APB busses clocks configuration
- * + Peripheral clocks configuration
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### RCC specific features #####
- ===============================================================================
- [..]
- After reset the device is running from Internal High Speed oscillator
- (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
- and I-Cache are disabled, and all peripherals are off except internal
- SRAM, Flash and JTAG.
- (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
- all peripherals mapped on these busses are running at HSI speed.
- (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
- (+) All GPIOs are in input floating state, except the JTAG pins which
- are assigned to be used for debug purpose.
- [..]
- Once the device started from reset, the user application has to:
- (+) Configure the clock source to be used to drive the System clock
- (if the application needs higher frequency/performance)
- (+) Configure the System clock frequency and Flash settings
- (+) Configure the AHB and APB busses prescalers
- (+) Enable the clock for the peripheral(s) to be used
- (+) Configure the clock source(s) for peripherals which clocks are not
- derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RCC
- * @brief RCC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define CR_OFFSET (RCC_OFFSET + 0x00)
-#define HSION_BitNumber 0x00
-#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
-/* Alias word address of CSSON bit */
-#define CSSON_BitNumber 0x13
-#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
-/* Alias word address of PLLON bit */
-#define PLLON_BitNumber 0x18
-#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
-/* Alias word address of PLLI2SON bit */
-#define PLLI2SON_BitNumber 0x1A
-#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
-
-/* --- CFGR Register ---*/
-/* Alias word address of I2SSRC bit */
-#define CFGR_OFFSET (RCC_OFFSET + 0x08)
-#define I2SSRC_BitNumber 0x17
-#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
-
-/* --- BDCR Register ---*/
-/* Alias word address of RTCEN bit */
-#define BDCR_OFFSET (RCC_OFFSET + 0x70)
-#define RTCEN_BitNumber 0x0F
-#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
-/* Alias word address of BDRST bit */
-#define BDRST_BitNumber 0x10
-#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define CSR_OFFSET (RCC_OFFSET + 0x74)
-#define LSION_BitNumber 0x00
-#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
-
-/* --- DCKCFGR Register ---*/
-/* Alias word address of TIMPRE bit */
-#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
-#define TIMPRE_BitNumber 0x18
-#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
-/* ---------------------- RCC registers bit mask ------------------------ */
-/* CFGR register bit mask */
-#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
-#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
-
-/* RCC Flag Mask */
-#define FLAG_MASK ((uint8_t)0x1F)
-
-/* CR register byte 3 (Bits[23:16]) base address */
-#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
-
-/* BDCR register base address */
-#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Private_Functions
- * @{
- */
-
-/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
- * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
- *
-@verbatim
- ===================================================================================
- ##### Internal and external clocks, PLL, CSS and MCO configuration functions #####
- ===================================================================================
- [..]
- This section provide functions allowing to configure the internal/external clocks,
- PLLs, CSS and MCO pins.
-
- (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
- the PLL as System clock source.
-
- (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
- clock source.
-
- (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
-
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
-
- (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
- (++) The first output is used to generate the high speed system clock (up to 168 MHz)
- (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
- the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
-
- (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve
- high-quality audio performance on the I2S interface.
-
- (#) CSS (Clock security system), once enable and if a HSE clock failure occurs
- (HSE used directly or through PLL as System clock source), the System clock
- is automatically switched to HSI and an interrupt is generated if enabled.
- The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
- exception vector.
-
- (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
- clock (through a configurable prescaler) on PA8 pin.
-
- (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
- clock (through a configurable prescaler) on PC9 pin.
- @endverbatim
- * @{
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE, PLL and PLLI2S OFF
- * - AHB, APB1 and APB2 prescaler set to 1.
- * - CSS, MCO1 and MCO2 OFF
- * - All interrupts disabled
- * @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @param None
- * @retval None
- */
-void RCC_DeInit(void)
-{
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON, PLLON and PLLI2S bits */
- RCC->CR &= (uint32_t)0xFAF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
- /* Reset PLLI2SCFGR register */
- RCC->PLLI2SCFGR = 0x20003000;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
-#ifdef STM32F427X
- /* Disable Timers clock prescalers selection */
- RCC->DCKCFGR = 0x00000000;
-#endif /* STM32F427X */
-
-}
-
-/**
- * @brief Configures the External High Speed oscillator (HSE).
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function reset the CSSON bit, so if the Clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param RCC_HSE: specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg RCC_HSE_ON: turn ON the HSE oscillator
- * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_HSEConfig(uint8_t RCC_HSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_HSE));
-
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
-
- /* Set the new HSE configuration -------------------------------------------*/
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
-}
-
-/**
- * @brief Waits for HSE start-up.
- * @note This functions waits on HSERDY flag to be set and return SUCCESS if
- * this flag is set, otherwise returns ERROR if the timeout is reached
- * and this flag is not set. The timeout value is defined by the constant
- * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending
- * on the HSE crystal used in your application.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: HSE oscillator is stable and ready to use
- * - ERROR: HSE oscillator not yet ready
- */
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
- __IO uint32_t startupcounter = 0;
- ErrorStatus status = ERROR;
- FlagStatus hsestatus = RESET;
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
- startupcounter++;
- } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
-
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- return (status);
-}
-
-/**
- * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param HSICalibrationValue: specifies the calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- * @retval None
- */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
-
- tmpreg = RCC->CR;
-
- /* Clear HSITRIM[4:0] bits */
- tmpreg &= ~RCC_CR_HSITRIM;
-
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
- tmpreg |= (uint32_t)HSICalibrationValue << 3;
-
- /* Store the new value */
- RCC->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after startup
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
- * of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * @param NewState: new state of the HSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_HSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE).
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param RCC_LSE: specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg RCC_LSE_ON: turn ON the LSE oscillator
- * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_LSEConfig(uint8_t RCC_LSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_LSE));
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
- /* Reset LSEON bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-
- /* Reset LSEBYP bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-
- /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
- switch (RCC_LSE)
- {
- case RCC_LSE_ON:
- /* Set LSEON bit */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
- break;
- case RCC_LSE_Bypass:
- /* Set LSEBYP and LSEON bits */
- *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Enables or disables the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @param NewState: new state of the LSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_LSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the main PLL clock source, multiplication and division factors.
- * @note This function must be used only when the main PLL is disabled.
- *
- * @param RCC_PLLSource: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
- * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- *
- * @param PLLM: specifies the division factor for PLL VCO input clock
- * This parameter must be a number between 0 and 63.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
- * of 2 MHz to limit PLL jitter.
- *
- * @param PLLN: specifies the multiplication factor for PLL VCO output clock
- * This parameter must be a number between 192 and 432.
- * @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
- *
- * @param PLLP: specifies the division factor for main system clock (SYSCLK)
- * This parameter must be a number in the range {2, 4, 6, or 8}.
- * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
- * the System clock frequency.
- *
- * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
- * This parameter must be a number between 4 and 15.
- * @note If the USB OTG FS is used in your application, you have to set the
- * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
- * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
- * correctly.
- *
- * @retval None
- */
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
- assert_param(IS_RCC_PLLM_VALUE(PLLM));
- assert_param(IS_RCC_PLLN_VALUE(PLLN));
- assert_param(IS_RCC_PLLP_VALUE(PLLP));
- assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
-
- RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
- (PLLQ << 24);
-}
-
-/**
- * @brief Enables or disables the main PLL.
- * @note After enabling the main PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The main PLL can not be disabled if it is used as system clock source
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the PLLI2S clock multiplication and division factors.
- *
- * @note This function must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * RCC_PLLConfig function )
- *
- * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between 192 and 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
- *
- * @param PLLI2SR: specifies the division factor for I2S clock
- * This parameter must be a number between 2 and 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
- *
- * @retval None
- */
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
- assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
-
- RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
-}
-
-/**
- * @brief Enables or disables the PLLI2S.
- * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLI2SCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
- * @param NewState: new state of the Clock Security System.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Selects the clock source to output on MCO1 pin(PA8).
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCO1Source: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
- * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
- * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
- * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
- * @param RCC_MCO1Div: specifies the MCO1 prescaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCO1Div_1: no division applied to MCO1 clock
- * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
- * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
- * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
- * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
- * @retval None
- */
-void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
- assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));
-
- tmpreg = RCC->CFGR;
-
- /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
- tmpreg &= CFGR_MCO1_RESET_MASK;
-
- /* Select MCO1 clock source and prescaler */
- tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Selects the clock source to output on MCO2 pin(PC9).
- * @note PC9 should be configured in alternate function mode.
- * @param RCC_MCO2Source: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
- * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
- * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
- * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
- * @param RCC_MCO2Div: specifies the MCO2 prescaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCO2Div_1: no division applied to MCO2 clock
- * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
- * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
- * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
- * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
- * @retval None
- */
-void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
- assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
-
- tmpreg = RCC->CFGR;
-
- /* Clear MCO2 and MCO2PRE[2:0] bits */
- tmpreg &= CFGR_MCO2_RESET_MASK;
-
- /* Select MCO2 clock source and prescaler */
- tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
- * @brief System, AHB and APB busses clocks configuration functions
- *
-@verbatim
- ===============================================================================
- ##### System, AHB and APB busses clocks configuration functions #####
- ===============================================================================
- [..]
- This section provide functions allowing to configure the System, AHB, APB1 and
- APB2 busses clocks.
-
- (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable
- prescaler and used to clock the CPU, memory and peripherals mapped
- on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
- from AHB clock through configurable prescalers and used to clock
- the peripherals mapped on these busses. You can use
- "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
-
- -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
- (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
- from an external clock mapped on the I2S_CKIN pin.
- You have to use RCC_I2SCLKConfig() function to configure this clock.
- (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
- divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
- functions to configure this clock.
- (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
- to work correctly, while the SDIO require a frequency equal or lower than
- to 48. This clock is derived of the main PLL through PLLQ divider.
- (+@) IWDG clock which is always the LSI clock.
-
- (#) The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz
- and PCLK1 42 MHz. Depending on the device voltage range, the maximum
- frequency should be adapted accordingly:
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120|
- +-------------------------------------------------------------------------------------+
- -@- When VOS bits (in PWR_CR register) is reset to 0 , the maximum value of HCLK is 144 MHz.
- You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the system clock (SYSCLK).
- * @note The HSI is used (enabled by hardware) as system clock source after
- * startup from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * You can use RCC_GetSYSCLKSource() function to know which clock is
- * currently used as system clock source.
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
- * @retval None
- */
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-
- tmpreg = RCC->CFGR;
-
- /* Clear SW[1:0] bits */
- tmpreg &= ~RCC_CFGR_SW;
-
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
- tmpreg |= RCC_SYSCLKSource;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the clock source used as system clock.
- * @param None
- * @retval The clock source used as system clock. The returned value can be one
- * of the following:
- * - 0x00: HSI used as system clock
- * - 0x04: HSE used as system clock
- * - 0x08: PLL used as system clock
- */
-uint8_t RCC_GetSYSCLKSource(void)
-{
- return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
-}
-
-/**
- * @brief Configures the AHB clock (HCLK).
- * @note Depending on the device voltage range, the software has to set correctly
- * these bits to ensure that HCLK not exceed the maximum allowed frequency
- * (for more details refer to section above
- * "CPU, AHB and APB busses clocks configuration functions")
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
- * the system clock (SYSCLK).
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
- * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
- * @retval None
- */
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear HPRE[3:0] bits */
- tmpreg &= ~RCC_CFGR_HPRE;
-
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
- tmpreg |= RCC_SYSCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-
-/**
- * @brief Configures the Low Speed APB clock (PCLK1).
- * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB1 clock = HCLK
- * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK1Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE1[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE1;
-
- /* Set PPRE1[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the High Speed APB clock (PCLK2).
- * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB2 clock = HCLK
- * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK2Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE2[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE2;
-
- /* Set PPRE2[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK << 3;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK,
- * PCLK1 and PCLK2.
- *
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
- * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
- * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
- * the clocks frequencies.
- *
- * @note This function can be used by the user application to compute the
- * baudrate for the communication peripherals or configure other parameters.
- * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
- * must be called to update the structure's field. Otherwise, any
- * configuration based on this function will be incorrect.
- *
- * @retval None
- */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
- uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock source */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLP
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
- break;
- default:
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- }
- /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
-
- /* Get HCLK prescaler */
- tmp = RCC->CFGR & RCC_CFGR_HPRE;
- tmp = tmp >> 4;
- presc = APBAHBPrescTable[tmp];
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
-
- /* Get PCLK1 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE1;
- tmp = tmp >> 10;
- presc = APBAHBPrescTable[tmp];
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-
- /* Get PCLK2 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE2;
- tmp = tmp >> 13;
- presc = APBAHBPrescTable[tmp];
- /* PCLK2 clock frequency */
- RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group3 Peripheral clocks configuration functions
- * @brief Peripheral clocks configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral clocks configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to configure the Peripheral clocks.
-
- (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided
- by 2 to 31.
-
- (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
- except internal SRAM, Flash and JTAG. Before to start using a peripheral
- you have to enable its interface clock. You can do this using
- RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
-
- (#) To reset the peripherals configuration (to the default state after device reset)
- you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
- RCC_APB1PeriphResetCmd() functions.
-
- (#) To further reduce power consumption in SLEEP mode the peripheral clocks
- can be disabled prior to executing the WFI or WFE instructions.
- You can do this using RCC_AHBPeriphClockLPModeCmd(),
- RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using PWR_BackupAccessCmd(ENABLE) function before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the
- * Backup domain is reset using RCC_BackupResetCmd() function, or by
- * a Power On Reset (POR).
- *
- * @param RCC_RTCCLKSource: specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
- * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
- * as RTC clock, where x:[2,31]
- *
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
- * RTC clock source).
- *
- * @retval None
- */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-
- if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
- { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
- tmpreg = RCC->CFGR;
-
- /* Clear RTCPRE[4:0] bits */
- tmpreg &= ~RCC_CFGR_RTCPRE;
-
- /* Configure HSE division factor for RTC clock */
- tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
- }
-
- /* Select the RTC clock source */
- RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
-}
-
-/**
- * @brief Enables or disables the RTC clock.
- * @note This function must be used only after the RTC clock source was selected
- * using the RCC_RTCCLKConfig function.
- * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Forces or releases the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_CSR register.
- * @note The BKPSRAM is not affected by this reset.
- * @param NewState: new state of the Backup domain reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_BackupResetCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the I2S clock source (I2SCLK).
- * @note This function must be called before enabling the I2S APB clock.
- * @param RCC_I2SCLKSource: specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
- * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
- * used as I2S clock source
- * @retval None
- */
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
-
- *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
-}
-
-/**
- * @brief Configures the Timers clocks prescalers selection.
- *
- * @note This feature is only available with STM32F427x/437x Devices.
- * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection
- * This parameter can be one of the following values:
- * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is
- * equal to HPRE if PPREx is corresponding to division by 1 or 2,
- * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
- * division by 4 or more.
- *
- * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is
- * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
- * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
- * to division by 8 or more.
- * @retval None
- */
-void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
-{
- /* Check the parameters */
- assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler));
-
- *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler;
-
-}
-
-/**
- * @brief Enables or disables the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
- * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
- * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
- * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
-
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB1ENR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1ENR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB2ENR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2ENR &= ~RCC_AHB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB3 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
- * This parameter must be: RCC_AHB3Periph_FSMC
- *
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB3ENR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3ENR &= ~RCC_AHB3Periph;
- }
-}
-
-/**
- * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @arg RCC_APB1Periph_UART7: UART7 clock
- * @arg RCC_APB1Periph_UART8: UART8 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1ENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1ENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SPI4: SPI4 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @arg RCC_APB2Periph_SPI5: SPI5 clock
- * @arg RCC_APB2Periph_SPI6: SPI6 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2ENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2ENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB1 peripheral reset.
- * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- *
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB1RSTR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1RSTR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB2 peripheral reset.
- * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB2RSTR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2RSTR &= ~RCC_AHB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB3 peripheral reset.
- * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
- * This parameter must be: RCC_AHB3Periph_FSMC
- *
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHB3RSTR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3RSTR &= ~RCC_AHB3Periph;
- }
-}
-
-/**
- * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @arg RCC_APB1Periph_UART7: UART7 clock
- * @arg RCC_APB1Periph_UART8: UART8 clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB1RSTR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1RSTR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases High Speed APB (APB2) peripheral reset.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SPI4: SPI4 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @arg RCC_APB2Periph_SPI5: SPI5 clock
- * @arg RCC_APB2Periph_SPI6: SPI6 clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB2RSTR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2RSTR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
- * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
- * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
- * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
- * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
- * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
- * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
- * @arg RCC_AHB1Periph_CRC: CRC clock
- * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
- * @arg RCC_AHB1Periph_DMA1: DMA1 clock
- * @arg RCC_AHB1Periph_DMA2: DMA2 clock
- * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
- * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
- * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
- * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB1LPENR |= RCC_AHB1Periph;
- }
- else
- {
- RCC->AHB1LPENR &= ~RCC_AHB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHB2Periph_DCMI: DCMI clock
- * @arg RCC_AHB2Periph_CRYP: CRYP clock
- * @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
- * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB2LPENR |= RCC_AHB2Periph;
- }
- else
- {
- RCC->AHB2LPENR &= ~RCC_AHB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
- * This parameter must be: RCC_AHB3Periph_FSMC
- *
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->AHB3LPENR |= RCC_AHB3Periph;
- }
- else
- {
- RCC->AHB3LPENR &= ~RCC_AHB3Periph;
- }
-}
-
-/**
- * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM4: TIM4 clock
- * @arg RCC_APB1Periph_TIM5: TIM5 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock
- * @arg RCC_APB1Periph_TIM12: TIM12 clock
- * @arg RCC_APB1Periph_TIM13: TIM13 clock
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_SPI3: SPI3 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_UART4: UART4 clock
- * @arg RCC_APB1Periph_UART5: UART5 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_I2C3: I2C3 clock
- * @arg RCC_APB1Periph_CAN1: CAN1 clock
- * @arg RCC_APB1Periph_CAN2: CAN2 clock
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock
- * @arg RCC_APB1Periph_UART7: UART7 clock
- * @arg RCC_APB1Periph_UART8: UART8 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB1LPENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1LPENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_TIM8: TIM8 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_USART6: USART6 clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_ADC2: ADC2 clock
- * @arg RCC_APB2Periph_ADC3: ADC3 clock
- * @arg RCC_APB2Periph_SDIO: SDIO clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_SPI4: SPI4 clock
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_TIM9: TIM9 clock
- * @arg RCC_APB2Periph_TIM10: TIM10 clock
- * @arg RCC_APB2Periph_TIM11: TIM11 clock
- * @arg RCC_APB2Periph_SPI5: SPI5 clock
- * @arg RCC_APB2Periph_SPI6: SPI6 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- RCC->APB2LPENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2LPENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RCC interrupts.
- * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- *
- * @param NewState: new state of the specified RCC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_IT(RCC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
- }
- else
- {
- /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified RCC flag is set or not.
- * @param RCC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
- * @arg RCC_FLAG_PLLRDY: main PLL clock ready
- * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
- * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
- * @arg RCC_FLAG_PINRST: Pin reset
- * @arg RCC_FLAG_PORRST: POR/PDR reset
- * @arg RCC_FLAG_SFTRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPWRRST: Low Power reset
- * @retval The new state of RCC_FLAG (SET or RESET).
- */
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
-{
- uint32_t tmp = 0;
- uint32_t statusreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_FLAG(RCC_FLAG));
-
- /* Get the RCC register index */
- tmp = RCC_FLAG >> 5;
- if (tmp == 1) /* The flag to check is in CR register */
- {
- statusreg = RCC->CR;
- }
- else if (tmp == 2) /* The flag to check is in BDCR register */
- {
- statusreg = RCC->BDCR;
- }
- else /* The flag to check is in CSR register */
- {
- statusreg = RCC->CSR;
- }
-
- /* Get the flag position */
- tmp = RCC_FLAG & FLAG_MASK;
- if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC reset flags.
- * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
- * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
- * @param None
- * @retval None
- */
-void RCC_ClearFlag(void)
-{
- /* Set RMVF bit to clear the reset flags */
- RCC->CSR |= RCC_CSR_RMVF;
-}
-
-/**
- * @brief Checks whether the specified RCC interrupt has occurred or not.
- * @param RCC_IT: specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval The new state of RCC_IT (SET or RESET).
- */
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_GET_IT(RCC_IT));
-
- /* Check the status of the specified RCC interrupt */
- if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the RCC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC's interrupt pending bits.
- * @param RCC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval None
- */
-void RCC_ClearITPendingBit(uint8_t RCC_IT)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
- pending bits */
- *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
deleted file mode 100644
index 6d0e65d9..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
+++ /dev/null
@@ -1,397 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_rng.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Random Number Generator (RNG) peripheral:
- * + Initialization and Configuration
- * + Get 32 bit Random number
- * + Interrupts and flags management
- *
-@verbatim
-
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable The RNG controller clock using
- RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function.
-
- (#) Activate the RNG peripheral using RNG_Cmd() function.
-
- (#) Wait until the 32 bit Random number Generator contains a valid random data
- (using polling/interrupt mode). For more details, refer to "Interrupts and
- flags management functions" module description.
-
- (#) Get the 32 bit Random number using RNG_GetRandomNumber() function
-
- (#) To get another 32 bit Random number, go to step 3.
-
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RNG
- * @brief RNG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RNG_Private_Functions
- * @{
- */
-
-/** @defgroup RNG_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initialize the RNG peripheral
- (+) Enable or disable the RNG peripheral
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the RNG peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void RNG_DeInit(void)
-{
- /* Enable RNG reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE);
-
- /* Release RNG from reset state */
- RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE);
-}
-
-/**
- * @brief Enables or disables the RNG peripheral.
- * @param NewState: new state of the RNG peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RNG_Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the RNG */
- RNG->CR |= RNG_CR_RNGEN;
- }
- else
- {
- /* Disable the RNG */
- RNG->CR &= ~RNG_CR_RNGEN;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup RNG_Group2 Get 32 bit Random number function
- * @brief Get 32 bit Random number function
- *
-
-@verbatim
- ===============================================================================
- ##### Get 32 bit Random number function #####
- ===============================================================================
- [..] This section provides a function allowing to get the 32 bit Random number
-
- (@) Before to call this function you have to wait till DRDY flag is set,
- using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Returns a 32-bit random number.
- *
- * @note Before to call this function you have to wait till DRDY (data ready)
- * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
- * @note Each time the the Random number data is read (using RNG_GetRandomNumber()
- * function), the RNG_FLAG_DRDY flag is automatically cleared.
- * @note In the case of a seed error, the generation of random numbers is
- * interrupted for as long as the SECS bit is '1'. If a number is
- * available in the RNG_DR register, it must not be used because it may
- * not have enough entropy. In this case, it is recommended to clear the
- * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable
- * and enable the RNG peripheral (using RNG_Cmd() function) to
- * reinitialize and restart the RNG.
- * @note In the case of a clock error, the RNG is no more able to generate
- * random numbers because the PLL48CLK clock is not correct. User have
- * to check that the clock controller is correctly configured to provide
- * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS)
- * function) . The clock error has no impact on the previously generated
- * random numbers, and the RNG_DR register contents can be used.
- *
- * @param None
- * @retval 32-bit random number.
- */
-uint32_t RNG_GetRandomNumber(void)
-{
- /* Return the 32 bit random number from the DR register */
- return RNG->DR;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup RNG_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the RNG Interrupts and
- to get the status and clear flags and Interrupts pending bits.
-
- [..] The RNG provides 3 Interrupts sources and 3 Flags:
-
- *** Flags : ***
- ===============
- [..]
- (#) RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid
- random data. it is cleared by reading the valid data(using
- RNG_GetRandomNumber() function).
-
- (#) RNG_FLAG_CECS : In the case of a seed error detection.
-
- (#) RNG_FLAG_SECS : In the case of a clock error detection.
-
- *** Interrupts ***
- ==================
- [..] If enabled, an RNG interrupt is pending :
-
- (#) In the case of the RNG_DR register contains valid random data.
- This interrupt source is cleared once the RNG_DR register has been read
- (using RNG_GetRandomNumber() function) until a new valid value is
- computed; or
- (#) In the case of a seed error : One of the following faulty sequences has
- been detected:
- (++) More than 64 consecutive bits at the same value (0 or 1)
- (++) More than 32 consecutive alternance of 0 and 1 (0101010101...01)
- This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI)
- function; or
- (#) In the case of a clock error : the PLL48CLK (RNG peripheral clock source)
- was not correctly detected (fPLL48CLK< fHCLK/16). This interrupt source is
- cleared using RNG_ClearITPendingBit(RNG_IT_CEI) function.
- -@- note In this case, User have to check that the clock controller is
- correctly configured to provide the RNG clock.
-
- *** Managing the RNG controller events : ***
- ============================================
- [..] The user should identify which mode will be used in his application to manage
- the RNG controller events: Polling mode or Interrupt mode.
-
- (#) In the Polling Mode it is advised to use the following functions:
- (++) RNG_GetFlagStatus() : to check if flags events occur.
- (++) RNG_ClearFlag() : to clear the flags events.
-
- -@@- RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only
- by reading the Random number data.
-
- (#) In the Interrupt Mode it is advised to use the following functions:
- (++) RNG_ITConfig() : to enable or disable the interrupt source.
- (++) RNG_GetITStatus() : to check if Interrupt occurs.
- (++) RNG_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the RNG interrupt.
- * @note The RNG provides 3 interrupt sources,
- * - Computed data is ready event (DRDY), and
- * - Seed error Interrupt (SEI) and
- * - Clock error Interrupt (CEI),
- * all these interrupts sources are enabled by setting the IE bit in
- * CR register. However, each interrupt have its specific status bit
- * (see RNG_GetITStatus() function) and clear bit except the DRDY event
- * (see RNG_ClearITPendingBit() function).
- * @param NewState: new state of the RNG interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RNG_ITConfig(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the RNG interrupt */
- RNG->CR |= RNG_CR_IE;
- }
- else
- {
- /* Disable the RNG interrupt */
- RNG->CR &= ~RNG_CR_IE;
- }
-}
-
-/**
- * @brief Checks whether the specified RNG flag is set or not.
- * @param RNG_FLAG: specifies the RNG flag to check.
- * This parameter can be one of the following values:
- * @arg RNG_FLAG_DRDY: Data Ready flag.
- * @arg RNG_FLAG_CECS: Clock Error Current flag.
- * @arg RNG_FLAG_SECS: Seed Error Current flag.
- * @retval The new state of RNG_FLAG (SET or RESET).
- */
-FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_RNG_GET_FLAG(RNG_FLAG));
-
- /* Check the status of the specified RNG flag */
- if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET)
- {
- /* RNG_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* RNG_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the RNG_FLAG status */
- return bitstatus;
-}
-
-
-/**
- * @brief Clears the RNG flags.
- * @param RNG_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg RNG_FLAG_CECS: Clock Error Current flag.
- * @arg RNG_FLAG_SECS: Seed Error Current flag.
- * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function.
- * This flag is cleared only by reading the Random number data (using
- * RNG_GetRandomNumber() function).
- * @retval None
- */
-void RNG_ClearFlag(uint8_t RNG_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG));
- /* Clear the selected RNG flags */
- RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4);
-}
-
-/**
- * @brief Checks whether the specified RNG interrupt has occurred or not.
- * @param RNG_IT: specifies the RNG interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RNG_IT_CEI: Clock Error Interrupt.
- * @arg RNG_IT_SEI: Seed Error Interrupt.
- * @retval The new state of RNG_IT (SET or RESET).
- */
-ITStatus RNG_GetITStatus(uint8_t RNG_IT)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_RNG_GET_IT(RNG_IT));
-
- /* Check the status of the specified RNG interrupt */
- if ((RNG->SR & RNG_IT) != (uint8_t)RESET)
- {
- /* RNG_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* RNG_IT is reset */
- bitstatus = RESET;
- }
- /* Return the RNG_IT status */
- return bitstatus;
-}
-
-
-/**
- * @brief Clears the RNG interrupt pending bit(s).
- * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear.
- * This parameter can be any combination of the following values:
- * @arg RNG_IT_CEI: Clock Error Interrupt.
- * @arg RNG_IT_SEI: Seed Error Interrupt.
- * @retval None
- */
-void RNG_ClearITPendingBit(uint8_t RNG_IT)
-{
- /* Check the parameters */
- assert_param(IS_RNG_IT(RNG_IT));
-
- /* Clear the selected RNG interrupt pending bit */
- RNG->SR = (uint8_t)~RNG_IT;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
deleted file mode 100644
index d4b22d29..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
+++ /dev/null
@@ -1,2761 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_rtc.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Real-Time Clock (RTC) peripheral:
- * + Initialization
- * + Calendar (Time and Date) configuration
- * + Alarms (Alarm A and Alarm B) configuration
- * + WakeUp Timer configuration
- * + Daylight Saving configuration
- * + Output pin Configuration
- * + Coarse digital Calibration configuration
- * + Smooth digital Calibration configuration
- * + TimeStamp configuration
- * + Tampers configuration
- * + Backup Data Registers configuration
- * + Shift control synchronisation
- * + RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
- * + Interrupts and flags management
- *
-@verbatim
-
- ===================================================================
- ##### Backup Domain Operating Condition #####
- ===================================================================
- [..] The real-time clock (RTC), the RTC backup registers, and the backup
- SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
- VDD supply is powered off.
- To retain the content of the RTC backup registers, backup SRAM, and supply
- the RTC when VDD is turned off, VBAT pin can be connected to an optional
- standby voltage supplied by a battery or by another source.
-
- [..] To allow the RTC to operate even when the main digital supply (VDD) is turned
- off, the VBAT pin powers the following blocks:
- (#) The RTC
- (#) The LSE oscillator
- (#) The backup SRAM when the low power backup regulator is enabled
- (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
-
- [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
- the following functions are available:
- (#) PC14 and PC15 can be used as either GPIO or LSE pins
- (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
- (#) PI8 can be used as a GPIO or as the RTC_AF2 pin
-
- [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
- because VDD is not present), the following functions are available:
- (#) PC14 and PC15 can be used as LSE pins only
- (#) PC13 can be used as the RTC_AF1 pin
- (#) PI8 can be used as the RTC_AF2 pin
-
-
- ##### Backup Domain Reset #####
- ===================================================================
- [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
- to their reset values. The BKPSRAM is not affected by this reset. The only
- way of resetting the BKPSRAM is through the Flash interface by requesting
- a protection level change from 1 to 0.
- [..] A backup domain reset is generated when one of the following events occurs:
- (#) Software reset, triggered by setting the BDRST bit in the
- RCC Backup domain control register (RCC_BDCR). You can use the
- RCC_BackupResetCmd().
- (#) VDD or VBAT power on, if both supplies have previously been powered off.
-
-
- ##### Backup Domain Access #####
- ===================================================================
- [..] After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted write
- accesses.
- [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
- (+) Enable the Power Controller (PWR) APB1 interface clock using the
- RCC_APB1PeriphClockCmd() function.
- (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function.
- (+) Select the RTC clock source using the RCC_RTCCLKConfig() function.
- (+) Enable RTC Clock using the RCC_RTCCLKCmd() function.
-
-
- ##### How to use RTC Driver #####
- ===================================================================
- [..]
- (+) Enable the RTC domain access (see description in the section above)
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
- format using the RTC_Init() function.
-
- *** Time and Date configuration ***
- ===================================
- [..]
- (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
- and RTC_SetDate() functions.
- (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() functions.
- (+) Use the RTC_DayLightSavingConfig() function to add or sub one
- hour to the RTC Calendar.
-
- *** Alarm configuration ***
- ===========================
- [..]
- (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
- (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function
- (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
- (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
-
- *** RTC Wakeup configuration ***
- ================================
- [..]
- (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
- function.
- (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() function
- (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function
- (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter()
- function.
-
- *** Outputs configuration ***
- =============================
- [..] The RTC has 2 different outputs:
- (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
- and WaKeUp signals. To output the selected RTC signal on RTC_AF1 pin, use the
- RTC_OutputConfig() function.
- (+) AFO_CALIB: this output is 512Hz signal or 1Hz. To output the RTC Clock on
- RTC_AF1 pin, use the RTC_CalibOutputCmd() function.
-
- *** Smooth digital Calibration configuration ***
- ================================================
- [..]
- (+) Configure the RTC Original Digital Calibration Value and the corresponding
- calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
- function.
-
- *** Coarse digital Calibration configuration ***
- ================================================
- [..]
- (+) Configure the RTC Coarse Calibration Value and the corresponding
- sign using the RTC_CoarseCalibConfig() function.
- (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() function
-
- *** TimeStamp configuration ***
- ===============================
- [..]
- (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp using the RTC
- _TimeStampCmd() function.
- (+) To read the RTC TimeStamp Time and Date register, use the RTC_GetTimeStamp()
- function.
- (+) To read the RTC TimeStamp SubSecond register, use the
- RTC_GetTimeStampSubSecond() function.
- (+) The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13)
- or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in
- RTC_TAFCR register. You can use the RTC_TamperPinSelection() function to
- select the corresponding pin.
-
- *** Tamper configuration ***
- ============================
- [..]
- (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
- (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
- function.
- (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper
- filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig()
- function.
- (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
- function.
- (+) Configure the Tamper precharge or discharge duration using
- RTC_TamperPinsPrechargeDuration() function.
- (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
- (+) Enable the Time stamp on Tamper detection event using
- TC_TSOnTamperDetecCmd() function.
- (+) The TIMESTAMP alternate function can be mapped to either RTC_AF1
- or RTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR
- register. You can use the RTC_TimeStampPinSelection() function to select
- the corresponding pin.
-
- *** Backup Data Registers configuration ***
- ===========================================
- [..]
- (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
- function.
- (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
- function.
-
-
- ##### RTC and low power modes #####
- ===================================================================
- [..] The MCU can be woken up from a low power mode by an RTC alternate
- function.
- [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
- RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
- These RTC alternate functions can wake up the system from the Stop and
- Standby lowpower modes.
- [..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm
- or the RTC wakeup events.
- [..] The RTC provides a programmable time base for waking up from the
- Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC clock source
- is LSE or LSI.
-
-
- ##### Selection of RTC_AF1 alternate functions #####
- ===================================================================
- [..] The RTC_AF1 pin (PC13) can be used for the following purposes:
- (+) AFO_ALARM output
- (+) AFO_CALIB output
- (+) AFI_TAMPER
- (+) AFI_TIMESTAMP
-
- [..]
- +-------------------------------------------------------------------------------------------------------------+
- | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |
- | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |
- | and function | | | | | selection | selection |Configuration |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | Alarm out | | | | | Don't | Don't | |
- | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | Alarm out | | | | | Don't | Don't | |
- | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | Calibration out | | | | | Don't | Don't | |
- | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | TAMPER input | | | | | | Don't | |
- | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | TIMESTAMP and | | | | | | | |
- | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care |
- | floating | | | | | | | |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | TIMESTAMP input | | | | | Don't | | |
- | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care |
- |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
- | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care |
- +-------------------------------------------------------------------------------------------------------------+
-
-
- ##### Selection of RTC_AF2 alternate functions #####
- ===================================================================
- [..] The RTC_AF2 pin (PI8) can be used for the following purposes:
- (+) AFI_TAMPER
- (+) AFI_TIMESTAMP
- [..]
- +---------------------------------------------------------------------------------------+
- | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |
- | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |
- | and function | | | selection | selection |Configuration |
- |-----------------|-----------|--------------|------------|--------------|--------------|
- | TAMPER input | | | | Don't | |
- | floating | 1 | 0 | 1 | care | Don't care |
- |-----------------|-----------|--------------|------------|--------------|--------------|
- | TIMESTAMP and | | | | | |
- | TAMPER input | 1 | 1 | 1 | 1 | Don't care |
- | floating | | | | | |
- |-----------------|-----------|--------------|------------|--------------|--------------|
- | TIMESTAMP input | | | Don't | | |
- | floating | 0 | 1 | care | 1 | Don't care |
- |-----------------|-----------|--------------|------------|--------------|--------------|
- | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care |
- +---------------------------------------------------------------------------------------+
-
-
-@endverbatim
-
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_sdio.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SDIO
- * @brief SDIO driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ------------ SDIO registers bit address in the alias region ----------- */
-#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
-
-/* --- CLKCR Register ---*/
-/* Alias word address of CLKEN bit */
-#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
-#define CLKEN_BitNumber 0x08
-#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
-
-/* --- CMD Register ---*/
-/* Alias word address of SDIOSUSPEND bit */
-#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
-#define SDIOSUSPEND_BitNumber 0x0B
-#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
-
-/* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BitNumber 0x0C
-#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
-
-/* Alias word address of NIEN bit */
-#define NIEN_BitNumber 0x0D
-#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
-
-/* Alias word address of ATACMD bit */
-#define ATACMD_BitNumber 0x0E
-#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
-
-/* --- DCTRL Register ---*/
-/* Alias word address of DMAEN bit */
-#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
-#define DMAEN_BitNumber 0x03
-#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
-
-/* Alias word address of RWSTART bit */
-#define RWSTART_BitNumber 0x08
-#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
-
-/* Alias word address of RWSTOP bit */
-#define RWSTOP_BitNumber 0x09
-#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
-
-/* Alias word address of RWMOD bit */
-#define RWMOD_BitNumber 0x0A
-#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
-
-/* Alias word address of SDIOEN bit */
-#define SDIOEN_BitNumber 0x0B
-#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
-
-/* ---------------------- SDIO registers bit mask ------------------------ */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */
-#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
-
-/* --- PWRCTRL Register ---*/
-/* SDIO PWRCTRL Mask */
-#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
-
-/* --- DCTRL Register ---*/
-/* SDIO DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
-
-/* SDIO RESP Registers Address */
-#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SDIO_Private_Functions
- * @{
- */
-
-/** @defgroup SDIO_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the SDIO peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void SDIO_DeInit(void)
-{
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE);
-}
-
-/**
- * @brief Initializes the SDIO peripheral according to the specified
- * parameters in the SDIO_InitStruct.
- * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
- * that contains the configuration information for the SDIO peripheral.
- * @retval None
- */
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
- assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
- assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
- assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
- assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
-
-/*---------------------------- SDIO CLKCR Configuration ------------------------*/
- /* Get the SDIO CLKCR value */
- tmpreg = SDIO->CLKCR;
-
- /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
- tmpreg &= CLKCR_CLEAR_MASK;
-
- /* Set CLKDIV bits according to SDIO_ClockDiv value */
- /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
- /* Set BYPASS bit according to SDIO_ClockBypass value */
- /* Set WIDBUS bits according to SDIO_BusWide value */
- /* Set NEGEDGE bits according to SDIO_ClockEdge value */
- /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
- tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
- SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
- SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
-
- /* Write to SDIO CLKCR */
- SDIO->CLKCR = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_InitStruct member with its default value.
- * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
-{
- /* SDIO_InitStruct members default value */
- SDIO_InitStruct->SDIO_ClockDiv = 0x00;
- SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
- SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
- SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
- SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
- SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
-}
-
-/**
- * @brief Enables or disables the SDIO Clock.
- * @param NewState: new state of the SDIO Clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_ClockCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Sets the power status of the controller.
- * @param SDIO_PowerState: new state of the Power state.
- * This parameter can be one of the following values:
- * @arg SDIO_PowerState_OFF: SDIO Power OFF
- * @arg SDIO_PowerState_ON: SDIO Power ON
- * @retval None
- */
-void SDIO_SetPowerState(uint32_t SDIO_PowerState)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
-
- SDIO->POWER = SDIO_PowerState;
-}
-
-/**
- * @brief Gets the power status of the controller.
- * @param None
- * @retval Power status of the controller. The returned value can be one of the
- * following values:
- * - 0x00: Power OFF
- * - 0x02: Power UP
- * - 0x03: Power ON
- */
-uint32_t SDIO_GetPowerState(void)
-{
- return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions
- * @brief Command path state machine (CPSM) management functions
- *
-@verbatim
- ===============================================================================
- ##### Command path state machine (CPSM) management functions #####
- ===============================================================================
-
- This section provide functions allowing to program and read the Command path
- state machine (CPSM).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SDIO Command according to the specified
- * parameters in the SDIO_CmdInitStruct and send the command.
- * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
- * structure that contains the configuration information for the SDIO
- * command.
- * @retval None
- */
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
- assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
- assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
- assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
-
-/*---------------------------- SDIO ARG Configuration ------------------------*/
- /* Set the SDIO Argument value */
- SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
-
-/*---------------------------- SDIO CMD Configuration ------------------------*/
- /* Get the SDIO CMD value */
- tmpreg = SDIO->CMD;
- /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
- tmpreg &= CMD_CLEAR_MASK;
- /* Set CMDINDEX bits according to SDIO_CmdIndex value */
- /* Set WAITRESP bits according to SDIO_Response value */
- /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
- /* Set CPSMEN bits according to SDIO_CPSM value */
- tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
- | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
-
- /* Write to SDIO CMD */
- SDIO->CMD = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_CmdInitStruct member with its default value.
- * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
-{
- /* SDIO_CmdInitStruct members default value */
- SDIO_CmdInitStruct->SDIO_Argument = 0x00;
- SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
- SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
- SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
- SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
-}
-
-/**
- * @brief Returns command index of last command for which response received.
- * @param None
- * @retval Returns the command index of the last command response received.
- */
-uint8_t SDIO_GetCommandResponse(void)
-{
- return (uint8_t)(SDIO->RESPCMD);
-}
-
-/**
- * @brief Returns response received from the card for the last command.
- * @param SDIO_RESP: Specifies the SDIO response register.
- * This parameter can be one of the following values:
- * @arg SDIO_RESP1: Response Register 1
- * @arg SDIO_RESP2: Response Register 2
- * @arg SDIO_RESP3: Response Register 3
- * @arg SDIO_RESP4: Response Register 4
- * @retval The Corresponding response register value.
- */
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_RESP(SDIO_RESP));
-
- tmp = SDIO_RESP_ADDR + SDIO_RESP;
-
- return (*(__IO uint32_t *) tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions
- * @brief Data path state machine (DPSM) management functions
- *
-@verbatim
- ===============================================================================
- ##### Data path state machine (DPSM) management functions #####
- ===============================================================================
-
- This section provide functions allowing to program and read the Data path
- state machine (DPSM).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SDIO data path according to the specified
- * parameters in the SDIO_DataInitStruct.
- * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure
- * that contains the configuration information for the SDIO command.
- * @retval None
- */
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
- assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
- assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
- assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
- assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
-
-/*---------------------------- SDIO DTIMER Configuration ---------------------*/
- /* Set the SDIO Data TimeOut value */
- SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
-
-/*---------------------------- SDIO DLEN Configuration -----------------------*/
- /* Set the SDIO DataLength value */
- SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
-
-/*---------------------------- SDIO DCTRL Configuration ----------------------*/
- /* Get the SDIO DCTRL value */
- tmpreg = SDIO->DCTRL;
- /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
- tmpreg &= DCTRL_CLEAR_MASK;
- /* Set DEN bit according to SDIO_DPSM value */
- /* Set DTMODE bit according to SDIO_TransferMode value */
- /* Set DTDIR bit according to SDIO_TransferDir value */
- /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
- tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
- | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
-
- /* Write to SDIO DCTRL */
- SDIO->DCTRL = tmpreg;
-}
-
-/**
- * @brief Fills each SDIO_DataInitStruct member with its default value.
- * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
- /* SDIO_DataInitStruct members default value */
- SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
- SDIO_DataInitStruct->SDIO_DataLength = 0x00;
- SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
- SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
- SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
- SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
-}
-
-/**
- * @brief Returns number of remaining data bytes to be transferred.
- * @param None
- * @retval Number of remaining data bytes to be transferred
- */
-uint32_t SDIO_GetDataCounter(void)
-{
- return SDIO->DCOUNT;
-}
-
-/**
- * @brief Read one data word from Rx FIFO.
- * @param None
- * @retval Data received
- */
-uint32_t SDIO_ReadData(void)
-{
- return SDIO->FIFO;
-}
-
-/**
- * @brief Write one data word to Tx FIFO.
- * @param Data: 32-bit data word to write.
- * @retval None
- */
-void SDIO_WriteData(uint32_t Data)
-{
- SDIO->FIFO = Data;
-}
-
-/**
- * @brief Returns the number of words left to be written to or read from FIFO.
- * @param None
- * @retval Remaining number of words.
- */
-uint32_t SDIO_GetFIFOCount(void)
-{
- return SDIO->FIFOCNT;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions
- * @brief SDIO IO Cards mode management functions
- *
-@verbatim
- ===============================================================================
- ##### SDIO IO Cards mode management functions #####
- ===============================================================================
-
- This section provide functions allowing to program and read the SDIO IO Cards.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the SD I/O Read Wait operation.
- * @param NewState: new state of the Start SDIO Read Wait operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_StartSDIOReadWait(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
-}
-
-/**
- * @brief Stops the SD I/O Read Wait operation.
- * @param NewState: new state of the Stop SDIO Read Wait operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_StopSDIOReadWait(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
-}
-
-/**
- * @brief Sets one of the two options of inserting read wait interval.
- * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
- * This parameter can be:
- * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
- * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
- * @retval None
- */
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
-
- *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
-}
-
-/**
- * @brief Enables or disables the SD I/O Mode Operation.
- * @param NewState: new state of SDIO specific operation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SetSDIOOperation(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the SD I/O Mode suspend command sending.
- * @param NewState: new state of the SD I/O Mode suspend command.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group5 CE-ATA mode management functions
- * @brief CE-ATA mode management functions
- *
-@verbatim
- ===============================================================================
- ##### CE-ATA mode management functions #####
- ===============================================================================
-
- This section provide functions allowing to program and read the CE-ATA card.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the command completion signal.
- * @param NewState: new state of command completion signal.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_CommandCompletionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the CE-ATA interrupt.
- * @param NewState: new state of CE-ATA interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_CEATAITCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
-}
-
-/**
- * @brief Sends CE-ATA command (CMD61).
- * @param NewState: new state of CE-ATA command.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SendCEATACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group6 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
-
- This section provide functions allowing to program SDIO DMA transfer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SDIO DMA request.
- * @param NewState: new state of the selected SDIO DMA request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_DMACmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SDIO interrupts.
- * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
- * @param NewState: new state of the specified SDIO interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_IT(SDIO_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the SDIO interrupts */
- SDIO->MASK |= SDIO_IT;
- }
- else
- {
- /* Disable the SDIO interrupts */
- SDIO->MASK &= ~SDIO_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified SDIO flag is set or not.
- * @param SDIO_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress
- * @arg SDIO_FLAG_TXACT: Data transmit in progress
- * @arg SDIO_FLAG_RXACT: Data receive in progress
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval The new state of SDIO_FLAG (SET or RESET).
- */
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SDIO_FLAG(SDIO_FLAG));
-
- if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the SDIO's pending flags.
- * @param SDIO_FLAG: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval None
- */
-void SDIO_ClearFlag(uint32_t SDIO_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
-
- SDIO->ICR = SDIO_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SDIO interrupt has occurred or not.
- * @param SDIO_IT: specifies the SDIO interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
- * @retval The new state of SDIO_IT (SET or RESET).
- */
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_SDIO_GET_IT(SDIO_IT));
- if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the SDIO's interrupt pending bits.
- * @param SDIO_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
- * @retval None
- */
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
-
- SDIO->ICR = SDIO_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
deleted file mode 100644
index f0526c47..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
+++ /dev/null
@@ -1,1312 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_spi.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Serial peripheral interface (SPI):
- * + Initialization and Configuration
- * + Data transfers functions
- * + Hardware CRC Calculation
- * + DMA transfers management
- * + Interrupts and flags management
- *
-@verbatim
-
- ===================================================================
- ##### How to use this driver #####
- ===================================================================
- [..]
- (#) Enable peripheral clock using the following functions
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI4
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI5
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI6.
-
- (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd()
- function. In I2S mode, if an external clock source is used then the I2S
- CKIN pin GPIO clock should also be enabled.
-
- (#) Peripherals alternate function:
- (++) Connect the pin to the desired peripherals' Alternate Function (AF)
- using GPIO_PinAFConfig() function
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd,
- GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function In I2S mode, if an external clock source is
- used then the I2S CKIN pin should be also configured in Alternate
- function Push-pull pull-up mode.
-
- (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
- Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function.
- In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio
- frequency and Polarity using I2S_Init() function. For I2S mode, make sure
- that either:
- (++) I2S PLL is configured using the functions
- RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), RCC_PLLI2SCmd(ENABLE) and
- RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY); or
- (++) External clock source is configured using the function
- RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly
- the define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file.
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- SPI_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function
- (++) Active the needed channel Request using SPI_I2S_DMACmd() function
-
- (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
- I2S_Cmd().
-
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.
-
- (#) Optionally, you can enable/configure the following parameters without
- re-initialization (i.e there is no need to call again SPI_Init() function):
- (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
- is programmed as Data direction parameter using the SPI_Init() function
- it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
- using the SPI_BiDirectionalLineConfig() function.
- (++) When SPI_NSS_Soft is selected as Slave Select Management parameter
- using the SPI_Init() function it can be possible to manage the
- NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
- (++) Reconfigure the data size using the SPI_DataSizeConfig() function
- (++) Enable or disable the SS output using the SPI_SSOutputCmd() function
-
- (#) To use the CRC Hardware calculation feature refer to the Peripheral
- CRC hardware Calculation subsection.
-
-
- [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI
- peripheral is able to manage sending and receiving data simultaneously
- using two data lines. Each SPI peripheral has an extended block called I2Sxext
- (ie. I2S2ext for SPI2 and I2S3ext for SPI3).
- The extension block is not a full SPI IP, it is used only as I2S slave to
- implement full duplex mode. The extension block uses the same clock sources
- as its master.
- To configure I2S full duplex you have to:
-
- (#) Configure SPIx in I2S mode (I2S_Init() function) as described above.
-
- (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to
- I2S_Init() function.
-
- (#) Call I2S_Cmd() for SPIx then for its extended block.
-
- (#) To configure interrupts or DMA requests and to get/clear flag status,
- use I2Sxext instance for the extension block.
-
- [..] Functions that can be called with I2Sxext instances are: I2S_Cmd(),
- I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(),
- SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(),
- SPI_I2S_ClearFlag(), SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().
-
- Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
-
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
- I2S_StructInit(&I2SInitStruct);
- I2SInitStruct.Mode = I2S_Mode_MasterTx;
- I2S_Init(SPI3, &I2SInitStruct);
- I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)
- I2S_Cmd(SPI3, ENABLE);
- I2S_Cmd(SPI3ext, ENABLE);
- ...
- while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
- {}
- SPI_I2S_SendData(SPI3, txdata[i]);
- ...
- while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)
- {}
- rxdata[i] = SPI_I2S_ReceiveData(I2S3ext);
- ...
-
- [..]
- (@) In I2S mode: if an external clock is used as source clock for the I2S,
- then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should
- be enabled and set to the value of the source clock frequency (in Hz).
-
- (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd()
- just after calling the function SPI_Init().
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_spi.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SPI
- * @brief SPI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* SPI registers Masks */
-#define CR1_CLEAR_MASK ((uint16_t)0x3040)
-#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040)
-
-/* RCC PLLs masks */
-#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000)
-#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0)
-
-#define SPI_CR2_FRF ((uint16_t)0x0010)
-#define SPI_SR_TIFRFE ((uint16_t)0x0100)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SPI_Private_Functions
- * @{
- */
-
-/** @defgroup SPI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to initialize the SPI
- Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS
- Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
-
- [..] The SPI_Init() function follows the SPI configuration procedures for Master
- mode and Slave mode (details for these procedures are available in reference
- manual (RM0090)).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initialize the SPIx peripheral registers to their default reset values.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode.
- *
- * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are de-initialized
- * when the relative I2S peripheral is de-initialized (the extended block's clock
- * is managed by the I2S peripheral clock).
- *
- * @retval None
- */
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- if (SPIx == SPI1)
- {
- /* Enable SPI1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
- /* Release SPI1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
- }
- else if (SPIx == SPI2)
- {
- /* Enable SPI2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
- /* Release SPI2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
- }
- else if (SPIx == SPI3)
- {
- /* Enable SPI3 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
- /* Release SPI3 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
- }
- else if (SPIx == SPI4)
- {
- /* Enable SPI4 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE);
- /* Release SPI4 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, DISABLE);
- }
- else if (SPIx == SPI5)
- {
- /* Enable SPI5 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, ENABLE);
- /* Release SPI5 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, DISABLE);
- }
- else
- {
- if (SPIx == SPI6)
- {
- /* Enable SPI6 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, ENABLE);
- /* Release SPI6 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the SPI_InitStruct.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral.
- * @retval None
- */
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
- uint16_t tmpreg = 0;
-
- /* check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Check the SPI parameters */
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
- assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
-/*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
- master/salve mode, CPOL and CPHA */
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
- /* Set LSBFirst bit according to SPI_FirstBit value */
- /* Set BR bits according to SPI_BaudRatePrescaler value */
- /* Set CPOL bit according to SPI_CPOL value */
- /* Set CPHA bit according to SPI_CPHA value */
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
- SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
- SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
- SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
-
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
- /* Write to SPIx CRCPOLY */
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the I2S_InitStruct.
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode).
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral
- * configured in I2S mode.
- *
- * @note The function calculates the optimal prescaler needed to obtain the most
- * accurate audio frequency (depending on the I2S clock source, the PLL values
- * and the product configuration). But in case the prescaler value is greater
- * than 511, the default value (0x02) will be configured instead.
- *
- * @note if an external clock is used as source clock for the I2S, then the define
- * I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set
- * to the value of the the source clock frequency (in Hz).
- *
- * @retval None
- */
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
- uint32_t tmp = 0, i2sclk = 0;
-#ifndef I2S_EXTERNAL_CLOCK_VAL
- uint32_t pllm = 0, plln = 0, pllr = 0;
-#endif /* I2S_EXTERNAL_CLOCK_VAL */
-
- /* Check the I2S parameters */
- assert_param(IS_SPI_23_PERIPH(SPIx));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK;
- SPIx->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = SPIx->I2SCFGR;
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
- {
- i2sodd = (uint16_t)0;
- i2sdiv = (uint16_t)2;
- }
- /* If the requested audio frequency is not the default, compute the prescaler */
- else
- {
- /* Check the frame length (For the Prescaler computing) *******************/
- if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
- {
- /* Packet length is 16 bits */
- packetlength = 1;
- }
- else
- {
- /* Packet length is 32 bits */
- packetlength = 2;
- }
-
- /* Get I2S source Clock frequency ****************************************/
-
- /* If an external I2S clock has to be used, this define should be set
- in the project configuration or in the stm32f4xx_conf.h file */
- #ifdef I2S_EXTERNAL_CLOCK_VAL
- /* Set external clock as I2S clock source */
- if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
- {
- RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Set the I2S clock to the external clock value */
- i2sclk = I2S_EXTERNAL_CLOCK_VAL;
-
- #else /* There is no define for External I2S clock source */
- /* Set PLLI2S as I2S clock source */
- if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
- {
- RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
- }
-
- /* Get the PLLI2SN value */
- plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \
- (RCC_PLLI2SCFGR_PLLI2SN >> 6));
-
- /* Get the PLLI2SR value */
- pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \
- (RCC_PLLI2SCFGR_PLLI2SR >> 28));
-
- /* Get the PLLM value */
- pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
-
- /* Get the I2S source clock value */
- i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);
- #endif /* I2S_EXTERNAL_CLOCK_VAL */
-
- /* Compute the Real divider depending on the MCLK output state, with a floating point */
- if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
-
- /* Remove the flatting point */
- tmp = tmp / 10;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t) (i2sodd << 8);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2) || (i2sdiv > 0xFF))
- {
- /* Set the default values */
- i2sdiv = 2;
- i2sodd = 0;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
- (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
- /* Write to SPIx I2SCFGR */
- SPIx->I2SCFGR = tmpreg;
-}
-
-/**
- * @brief Fills each SPI_InitStruct member with its default value.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
- /* Initialize the SPI_Direction member */
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- /* initialize the SPI_Mode member */
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
- /* initialize the SPI_DataSize member */
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
- /* Initialize the SPI_CPOL member */
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
- /* Initialize the SPI_CPHA member */
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
- /* Initialize the SPI_NSS member */
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
- /* Initialize the SPI_BaudRatePrescaler member */
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
- /* Initialize the SPI_FirstBit member */
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
- /* Initialize the SPI_CRCPolynomial member */
- SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-/**
- * @brief Fills each I2S_InitStruct member with its default value.
- * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
-{
-/*--------------- Reset I2S init structure parameters values -----------------*/
- /* Initialize the I2S_Mode member */
- I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
-
- /* Initialize the I2S_Standard member */
- I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
-
- /* Initialize the I2S_DataFormat member */
- I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
-
- /* Initialize the I2S_MCLKOutput member */
- I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-
- /* Initialize the I2S_AudioFreq member */
- I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
-
- /* Initialize the I2S_CPOL member */
- I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral */
- SPIx->CR1 |= SPI_CR1_SPE;
- }
- else
- {
- /* Disable the selected SPI peripheral */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
- }
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral (in I2S mode).
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext
- * for full duplex mode).
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_23_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral (in I2S mode) */
- SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
- }
- else
- {
- /* Disable the selected SPI peripheral in I2S mode */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
- }
-}
-
-/**
- * @brief Configures the data size for the selected SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_DataSize: specifies the SPI data size.
- * This parameter can be one of the following values:
- * @arg SPI_DataSize_16b: Set data frame format to 16bit
- * @arg SPI_DataSize_8b: Set data frame format to 8bit
- * @retval None
- */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DATASIZE(SPI_DataSize));
- /* Clear DFF bit */
- SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
- /* Set new DFF bit value */
- SPIx->CR1 |= SPI_DataSize;
-}
-
-/**
- * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
- * This parameter can be one of the following values:
- * @arg SPI_Direction_Tx: Selects Tx transmission direction
- * @arg SPI_Direction_Rx: Selects Rx receive direction
- * @retval None
- */
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DIRECTION(SPI_Direction));
- if (SPI_Direction == SPI_Direction_Tx)
- {
- /* Set the Tx only mode */
- SPIx->CR1 |= SPI_Direction_Tx;
- }
- else
- {
- /* Set the Rx only mode */
- SPIx->CR1 &= SPI_Direction_Rx;
- }
-}
-
-/**
- * @brief Configures internally by software the NSS pin for the selected SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
- * This parameter can be one of the following values:
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
- * @retval None
- */
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
- {
- /* Set NSS pin internally by software */
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;
- }
- else
- {
- /* Reset NSS pin internally by software */
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the SS output for the selected SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param NewState: new state of the SPIx SS output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI SS output */
- SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
- }
- else
- {
- /* Disable the selected SPI SS output */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
- }
-}
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- *
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
- * are not taken into consideration and are configured by hardware
- * respectively to the TI mode requirements.
- *
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6
- * @param NewState: new state of the selected SPI TI communication mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TI mode for the selected SPI peripheral */
- SPIx->CR2 |= SPI_CR2_FRF;
- }
- else
- {
- /* Disable the TI mode for the selected SPI peripheral */
- SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF;
- }
-}
-
-/**
- * @brief Configures the full duplex mode for the I2Sx peripheral using its
- * extension I2Sxext according to the specified parameters in the
- * I2S_InitStruct.
- * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block.
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified I2S peripheral
- * extension.
- *
- * @note The structure pointed by I2S_InitStruct parameter should be the same
- * used for the master I2S peripheral. In this case, if the master is
- * configured as transmitter, the slave will be receiver and vice versa.
- * Or you can force a different mode by modifying the field I2S_Mode to the
- * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration.
- *
- * @note The I2S full duplex extension can be configured in slave mode only.
- *
- * @retval None
- */
-void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, tmp = 0;
-
- /* Check the I2S parameters */
- assert_param(IS_I2S_EXT_PERIPH(I2Sxext));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK;
- I2Sxext->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = I2Sxext->I2SCFGR;
-
- /* Get the mode to be configured for the extended I2S */
- if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
- {
- tmp = I2S_Mode_SlaveRx;
- }
- else
- {
- if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
- {
- tmp = I2S_Mode_SlaveTx;
- }
- }
-
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
- (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
- /* Write to SPIx I2SCFGR */
- I2Sxext->I2SCFGR = tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
-
- [..] This section provides a set of functions allowing to manage the SPI data
- transfers. In reception, data are received and then stored into an internal
- Rx buffer while. In transmission, data are first stored into an internal Tx
- buffer before being transmitted.
-
- [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
- function and returns the Rx buffered value. Whereas a write access to the SPI_DR
- can be done using SPI_I2S_SendData() function and stores the written data into
- Tx buffer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @retval The value of the received data.
- */
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
-
- /* Return the data in the DR register */
- return SPIx->DR;
-}
-
-/**
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
-
- /* Write in the DR register the data to be sent */
- SPIx->DR = Data;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group3 Hardware CRC Calculation functions
- * @brief Hardware CRC Calculation functions
- *
-@verbatim
- ===============================================================================
- ##### Hardware CRC Calculation functions #####
- ===============================================================================
-
- [..] This section provides a set of functions allowing to manage the SPI CRC hardware
- calculation
-
- [..] SPI communication using CRC is possible through the following procedure:
- (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
- Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function.
- (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
- (#) Enable the SPI using the SPI_Cmd() function
- (#) Before writing the last data to the TX buffer, set the CRCNext bit using the
- SPI_TransmitCRC() function to indicate that after transmission of the last
- data, the CRC should be transmitted.
- (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
- bit is reset. The CRC is also received and compared against the SPI_RXCRCR
- value.
- If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
- can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
-
- [..]
- (@) It is advised not to read the calculated CRC values during the communication.
-
- (@) When the SPI is in slave mode, be careful to enable CRC calculation only
- when the clock is stable, that is, when the clock is in the steady state.
- If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
- to the SCK slave input clock as soon as CRCEN is set, and this, whatever
- the value of the SPE bit.
-
- (@) With high bitrate frequencies, be careful when transmitting the CRC.
- As the number of used CPU cycles has to be as low as possible in the CRC
- transfer phase, it is forbidden to call software functions in the CRC
- transmission sequence to avoid errors in the last data and CRC reception.
- In fact, CRCNEXT bit has to be written before the end of the transmission/reception
- of the last data.
-
- (@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
- degradation of the SPI speed performance due to CPU accesses impacting the
- SPI bandwidth.
-
- (@) When the STM32F4xx is configured as slave and the NSS hardware mode is
- used, the NSS pin needs to be kept low between the data phase and the CRC
- phase.
-
- (@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
- calculation takes place even if a high level is applied on the NSS pin.
- This may happen for example in case of a multi-slave environment where the
- communication master addresses slaves alternately.
-
- (@) Between a slave de-selection (high level on NSS) and a new slave selection
- (low level on NSS), the CRC value should be cleared on both master and slave
- sides in order to resynchronize the master and slave for their respective
- CRC calculation.
-
- (@) To clear the CRC, follow the procedure below:
- (#@) Disable SPI using the SPI_Cmd() function
- (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
- (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
- (#@) Enable SPI using the SPI_Cmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the CRC value calculation of the transferred bytes.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param NewState: new state of the SPIx CRC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI CRC calculation */
- SPIx->CR1 |= SPI_CR1_CRCEN;
- }
- else
- {
- /* Disable the selected SPI CRC calculation */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
- }
-}
-
-/**
- * @brief Transmit the SPIx CRC value.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @retval None
- */
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Enable the selected SPI CRC transmission */
- SPIx->CR1 |= SPI_CR1_CRCNEXT;
-}
-
-/**
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param SPI_CRC: specifies the CRC register to be read.
- * This parameter can be one of the following values:
- * @arg SPI_CRC_Tx: Selects Tx CRC register
- * @arg SPI_CRC_Rx: Selects Rx CRC register
- * @retval The selected CRC register value..
- */
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
-{
- uint16_t crcreg = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC(SPI_CRC));
- if (SPI_CRC != SPI_CRC_Rx)
- {
- /* Get the Tx CRC register */
- crcreg = SPIx->TXCRCR;
- }
- else
- {
- /* Get the Rx CRC register */
- crcreg = SPIx->RXCRCR;
- }
- /* Return the selected CRC register */
- return crcreg;
-}
-
-/**
- * @brief Returns the CRC Polynomial register value for the specified SPI.
- * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @retval The CRC Polynomial register value.
- */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the CRC polynomial register */
- return SPIx->CRCPR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group4 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
- * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
- * @param NewState: new state of the selected SPI DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI DMA requests */
- SPIx->CR2 |= SPI_I2S_DMAReq;
- }
- else
- {
- /* Disable the selected SPI DMA requests */
- SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides a set of functions allowing to configure the SPI Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- *** Polling Mode ***
- ====================
-[..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
- (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
- (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
- (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
- (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur
- (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur
- (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
- (#) I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs.
- (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
- (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
-
- (@) Do not use the BSY flag to handle each data transmission or reception. It is
- better to use the TXE and RXNE flags instead.
-
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
- (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources
- and 7 pending bits:
- (+) Pending Bits:
- (##) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
- (##) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
- (##) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only)
- (##) SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only)
- (##) SPI_I2S_IT_OVR : to indicate if an Overrun error occur
- (##) I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only).
- (##) I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only).
-
- (+) Interrupt Source:
- (##) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
- interrupt.
- (##) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
- empty interrupt.
- (##) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
-
- [..] In this Mode it is advised to use the following functions:
- (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
- (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
- (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
- *** DMA Mode ***
- ================
- [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
- (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request
- (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request
-
- [..] In this Mode it is advised to use the following function:
- (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState
- NewState);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified SPI/I2S interrupts.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
- * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
- * @arg SPI_I2S_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified SPI interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
-{
- uint16_t itpos = 0, itmask = 0 ;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
-
- /* Get the SPI IT index */
- itpos = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = (uint16_t)1 << (uint16_t)itpos;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI interrupt */
- SPIx->CR2 |= itmask;
- }
- else
- {
- /* Disable the selected SPI interrupt */
- SPIx->CR2 &= (uint16_t)~itmask;
- }
-}
-
-/**
- * @brief Checks whether the specified SPIx/I2Sx flag is set or not.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_FLAG: specifies the SPI flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
- * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
- * @arg SPI_I2S_FLAG_BSY: Busy flag.
- * @arg SPI_I2S_FLAG_OVR: Overrun flag.
- * @arg SPI_FLAG_MODF: Mode Fault flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- * @arg SPI_I2S_FLAG_TIFRFE: Format Error.
- * @arg I2S_FLAG_UDR: Underrun Error flag.
- * @arg I2S_FLAG_CHSIDE: Channel Side flag.
- * @retval The new state of SPI_I2S_FLAG (SET or RESET).
- */
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
-
- /* Check the status of the specified SPI flag */
- if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
- {
- /* SPI_I2S_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) flag.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
- * This function clears only CRCERR flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- *
- * @note OVR (OverRun error) flag is cleared by software sequence: a read
- * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
- * @note UDR (UnderRun error) flag is cleared by a read operation to
- * SPI_SR register (SPI_I2S_GetFlagStatus()).
- * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
- * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
- *
- * @retval None
- */
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
-
- /* Clear the selected SPI CRC Error (CRCERR) flag */
- SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
- * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
- * @arg SPI_I2S_IT_OVR: Overrun interrupt.
- * @arg SPI_IT_MODF: Mode Fault interrupt.
- * @arg SPI_IT_CRCERR: CRC Error interrupt.
- * @arg I2S_IT_UDR: Underrun interrupt.
- * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt.
- * @retval The new state of SPI_I2S_IT (SET or RESET).
- */
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
-
- /* Get the SPI_I2S_IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Get the SPI_I2S_IT IT mask */
- itmask = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = 0x01 << itmask;
-
- /* Get the SPI_I2S_IT enable bit status */
- enablestatus = (SPIx->CR2 & itmask) ;
-
- /* Check the status of the specified SPI interrupt */
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
- {
- /* SPI_I2S_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_IT is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
- * This function clears only CRCERR interrupt pending bit.
- * @arg SPI_IT_CRCERR: CRC Error interrupt.
- *
- * @note OVR (OverRun Error) interrupt pending bit is cleared by software
- * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
- * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
- * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read
- * operation to SPI_SR register (SPI_I2S_GetITStatus()).
- * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
- * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
- * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
- * the SPI).
- * @retval None
- */
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- uint16_t itpos = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
-
- /* Get the SPI_I2S IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
- SPIx->SR = (uint16_t)~itpos;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
deleted file mode 100644
index 160181c5..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_syscfg.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the SYSCFG peripheral.
- *
- @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..] This driver provides functions for:
-
- (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
-
- (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
-
- (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
-
- -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
- using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_syscfg.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SYSCFG
- * @brief SYSCFG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
-
-/* --- PMC Register ---*/
-/* Alias word address of MII_RMII_SEL bit */
-#define PMC_OFFSET (SYSCFG_OFFSET + 0x04)
-#define MII_RMII_SEL_BitNumber ((uint8_t)0x17)
-#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
-
-/* --- CMPCR Register ---*/
-/* Alias word address of CMP_PD bit */
-#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20)
-#define CMP_PD_BitNumber ((uint8_t)0x00)
-#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SYSCFG_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the Alternate Functions (remap and EXTI configuration)
- * registers to their default reset values.
- * @param None
- * @retval None
- */
-void SYSCFG_DeInit(void)
-{
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
-}
-
-/**
- * @brief Changes the mapping of the specified pin.
- * @param SYSCFG_Memory: selects the memory remapping.
- * This parameter can be one of the following values:
- * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
- * @retval None
- */
-void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
-
- SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
-}
-
-/**
- * @brief Selects the GPIO pin used as EXTI Line.
- * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
- * EXTI lines where x can be (A..I) for STM32F40xx/STM32F41xx
- * and STM32F427x/STM32F437x devices.
- *
- * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
- * This parameter can be EXTI_PinSourcex where x can be (0..15, except
- * for EXTI_PortSourceGPIOI x can be (0..11) for STM32F40xx/STM32F41xx
- * and STM32F427x/STM32F437x devices.
- *
- * @retval None
- */
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
-{
- uint32_t tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
- assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
-
- tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
-}
-
-/**
- * @brief Selects the ETHERNET media interface
- * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode.
- * This parameter can be one of the following values:
- * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected
- * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected
- * @retval None
- */
-void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface)
-{
- assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface));
- /* Configure MII_RMII selection bit */
- *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface;
-}
-
-/**
- * @brief Enables or disables the I/O Compensation Cell.
- * @note The I/O compensation cell can be used only when the device supply
- * voltage ranges from 2.4 to 3.6 V.
- * @param NewState: new state of the I/O Compensation Cell.
- * This parameter can be one of the following values:
- * @arg ENABLE: I/O compensation cell enabled
- * @arg DISABLE: I/O compensation cell power-down mode
- * @retval None
- */
-void SYSCFG_CompensationCellCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Checks whether the I/O Compensation Cell ready flag is set or not.
- * @param None
- * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
- */
-FlagStatus SYSCFG_GetCompensationCellStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
deleted file mode 100644
index 1616a625..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
+++ /dev/null
@@ -1,3365 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_tim.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the TIM peripheral:
- * + TimeBase management
- * + Output Compare management
- * + Input Capture management
- * + Advanced-control timers (TIM1 and TIM8) specific features
- * + Interrupts, DMA and flags management
- * + Clocks management
- * + Synchronization management
- * + Specific interface management
- * + Specific remapping management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- This driver provides functions to configure and program the TIM
- of all STM32F4xx devices.
- These functions are split in 9 groups:
-
- (#) TIM TimeBase management: this group includes all needed functions
- to configure the TM Timebase unit:
- (++) Set/Get Prescaler
- (++) Set/Get Autoreload
- (++) Counter modes configuration
- (++) Set Clock division
- (++) Select the One Pulse mode
- (++) Update Request Configuration
- (++) Update Disable Configuration
- (++) Auto-Preload Configuration
- (++) Enable/Disable the counter
-
- (#) TIM Output Compare management: this group includes all needed
- functions to configure the Capture/Compare unit used in Output
- compare mode:
- (++) Configure each channel, independently, in Output Compare mode
- (++) Select the output compare modes
- (++) Select the Polarities of each channel
- (++) Set/Get the Capture/Compare register values
- (++) Select the Output Compare Fast mode
- (++) Select the Output Compare Forced mode
- (++) Output Compare-Preload Configuration
- (++) Clear Output Compare Reference
- (++) Select the OCREF Clear signal
- (++) Enable/Disable the Capture/Compare Channels
-
- (#) TIM Input Capture management: this group includes all needed
- functions to configure the Capture/Compare unit used in
- Input Capture mode:
- (++) Configure each channel in input capture mode
- (++) Configure Channel1/2 in PWM Input mode
- (++) Set the Input Capture Prescaler
- (++) Get the Capture/Compare values
-
- (#) Advanced-control timers (TIM1 and TIM8) specific features
- (++) Configures the Break input, dead time, Lock level, the OSSI,
- the OSSR State and the AOE(automatic output enable)
- (++) Enable/Disable the TIM peripheral Main Outputs
- (++) Select the Commutation event
- (++) Set/Reset the Capture Compare Preload Control bit
-
- (#) TIM interrupts, DMA and flags management
- (++) Enable/Disable interrupt sources
- (++) Get flags status
- (++) Clear flags/ Pending bits
- (++) Enable/Disable DMA requests
- (++) Configure DMA burst mode
- (++) Select CaptureCompare DMA request
-
- (#) TIM clocks management: this group includes all needed functions
- to configure the clock controller unit:
- (++) Select internal/External clock
- (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
-
- (#) TIM synchronization management: this group includes all needed
- functions to configure the Synchronization unit:
- (++) Select Input Trigger
- (++) Select Output Trigger
- (++) Select Master Slave Mode
- (++) ETR Configuration when used as external trigger
-
- (#) TIM specific interface management, this group includes all
- needed functions to use the specific TIM interface:
- (++) Encoder Interface Configuration
- (++) Select Hall Sensor
-
- (#) TIM specific remapping management includes the Remapping
- configuration of specific timers
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_tim.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup TIM
- * @brief TIM driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define SMCR_ETR_MASK ((uint16_t)0x00FF)
-#define CCMR_OFFSET ((uint16_t)0x0018)
-#define CCER_CCE_SET ((uint16_t)0x0001)
-#define CCER_CCNE_SET ((uint16_t)0x0004)
-#define CCMR_OC13M_MASK ((uint16_t)0xFF8F)
-#define CCMR_OC24M_MASK ((uint16_t)0x8FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIM_Private_Functions
- * @{
- */
-
-/** @defgroup TIM_Group1 TimeBase management functions
- * @brief TimeBase management functions
- *
-@verbatim
- ===============================================================================
- ##### TimeBase management functions #####
- ===============================================================================
-
-
- ##### TIM Driver: how to use it in Timing(Time base) Mode #####
- ===============================================================================
- [..]
- To use the Timer in Timing(Time base) mode, the following steps are mandatory:
-
- (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
-
- (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
-
- (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit
- with the corresponding configuration
-
- (#) Enable the NVIC if you need to generate the update interrupt.
-
- (#) Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update)
-
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-
- -@- All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @retval None
-
- */
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- if (TIMx == TIM1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
- }
- else if (TIMx == TIM2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
- }
- else if (TIMx == TIM3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
- }
- else if (TIMx == TIM4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
- }
- else if (TIMx == TIM5)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
- }
- else if (TIMx == TIM6)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
- }
- else if (TIMx == TIM7)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
- }
- else if (TIMx == TIM8)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
- }
- else if (TIMx == TIM9)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
- }
- else if (TIMx == TIM10)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
- }
- else if (TIMx == TIM11)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
- }
- else if (TIMx == TIM12)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
- }
- else if (TIMx == TIM13)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
- }
- else
- {
- if (TIMx == TIM14)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the TIMx Time Base Unit peripheral according to
- * the specified parameters in the TIM_TimeBaseInitStruct.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
- tmpcr1 = TIMx->CR1;
-
- if((TIMx == TIM1) || (TIMx == TIM8)||
- (TIMx == TIM2) || (TIMx == TIM3)||
- (TIMx == TIM4) || (TIMx == TIM5))
- {
- /* Select the Counter Mode */
- tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
- }
-
- if((TIMx != TIM6) && (TIMx != TIM7))
- {
- /* Set the clock division */
- tmpcr1 &= (uint16_t)(~TIM_CR1_CKD);
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
- }
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-
- if ((TIMx == TIM1) || (TIMx == TIM8))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediatly */
- TIMx->EGR = TIM_PSCReloadMode_Immediate;
-}
-
-/**
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
- * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- /* Set the default configuration */
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
-}
-
-/**
- * @brief Configures the TIMx Prescaler.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param Prescaler: specifies the Prescaler Register value
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
- * This parameter can be one of the following values:
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
- * @retval None
- */
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
- /* Set the Prescaler value */
- TIMx->PSC = Prescaler;
- /* Set or reset the UG Bit */
- TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/**
- * @brief Specifies the TIMx Counter Mode to be used.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_CounterMode: specifies the Counter Mode to be used
- * This parameter can be one of the following values:
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
- * @retval None
- */
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
-
- tmpcr1 = TIMx->CR1;
-
- /* Reset the CMS and DIR Bits */
- tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
-
- /* Set the Counter Mode */
- tmpcr1 |= TIM_CounterMode;
-
- /* Write to TIMx CR1 register */
- TIMx->CR1 = tmpcr1;
-}
-
-/**
- * @brief Sets the TIMx Counter Register value
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param Counter: specifies the Counter register new value.
- * @retval None
- */
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Counter Register value */
- TIMx->CNT = Counter;
-}
-
-/**
- * @brief Sets the TIMx Autoreload Register value
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param Autoreload: specifies the Autoreload register new value.
- * @retval None
- */
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Autoreload Register value */
- TIMx->ARR = Autoreload;
-}
-
-/**
- * @brief Gets the TIMx Counter value.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @retval Counter Register value
- */
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Counter Register value */
- return TIMx->CNT;
-}
-
-/**
- * @brief Gets the TIMx Prescaler value.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @retval Prescaler Register value.
- */
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Prescaler Register value */
- return TIMx->PSC;
-}
-
-/**
- * @brief Enables or Disables the TIMx Update event.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param NewState: new state of the TIMx UDIS bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the Update Disable Bit */
- TIMx->CR1 |= TIM_CR1_UDIS;
- }
- else
- {
- /* Reset the Update Disable Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
- }
-}
-
-/**
- * @brief Configures the TIMx Update Request Interrupt source.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_UpdateSource: specifies the Update source.
- * This parameter can be one of the following values:
- * @arg TIM_UpdateSource_Global: Source of update is the counter
- * overflow/underflow or the setting of UG bit, or an update
- * generation through the slave mode controller.
- * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.
- * @retval None
- */
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
-
- if (TIM_UpdateSource != TIM_UpdateSource_Global)
- {
- /* Set the URS Bit */
- TIMx->CR1 |= TIM_CR1_URS;
- }
- else
- {
- /* Reset the URS Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
- }
-}
-
-/**
- * @brief Enables or disables TIMx peripheral Preload register on ARR.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param NewState: new state of the TIMx peripheral Preload register
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ARR Preload Bit */
- TIMx->CR1 |= TIM_CR1_ARPE;
- }
- else
- {
- /* Reset the ARR Preload Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
- }
-}
-
-/**
- * @brief Selects the TIMx's One Pulse Mode.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_OPMode: specifies the OPM Mode to be used.
- * This parameter can be one of the following values:
- * @arg TIM_OPMode_Single
- * @arg TIM_OPMode_Repetitive
- * @retval None
- */
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
-
- /* Reset the OPM Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
-
- /* Configure the OPM Mode */
- TIMx->CR1 |= TIM_OPMode;
-}
-
-/**
- * @brief Sets the TIMx Clock Division value.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_CKD: specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
- * @retval None
- */
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));
-
- /* Reset the CKD Bits */
- TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
-
- /* Set the CKD value */
- TIMx->CR1 |= TIM_CKD;
-}
-
-/**
- * @brief Enables or disables the specified TIM peripheral.
- * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
- * @param NewState: new state of the TIMx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Counter */
- TIMx->CR1 |= TIM_CR1_CEN;
- }
- else
- {
- /* Disable the TIM Counter */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group2 Output Compare management functions
- * @brief Output Compare management functions
- *
-@verbatim
- ===============================================================================
- ##### Output Compare management functions #####
- ===============================================================================
-
-
- ##### TIM Driver: how to use it in Output Compare Mode #####
- ===============================================================================
- [..]
- To use the Timer in Output Compare mode, the following steps are mandatory:
-
- (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
- function
-
- (#) Configure the TIM pins by configuring the corresponding GPIO pins
-
- (#) Configure the Time base unit as described in the first part of this driver,
- (++) if needed, else the Timer will run with the default configuration:
- Autoreload value = 0xFFFF
- (++) Prescaler value = 0x0000
- (++) Counter mode = Up counting
- (++) Clock Division = TIM_CKD_DIV1
-
- (#) Fill the TIM_OCInitStruct with the desired parameters including:
- (++) The TIM Output Compare mode: TIM_OCMode
- (++) TIM Output State: TIM_OutputState
- (++) TIM Pulse value: TIM_Pulse
- (++) TIM Output Compare Polarity : TIM_OCPolarity
-
- (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired
- channel with the corresponding configuration
-
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-
- -@- All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
- -@- In case of PWM mode, this function is mandatory:
- TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE);
-
- -@- If the corresponding interrupt or DMA request are needed, the user should:
- (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
- (+@) Enable the corresponding interrupt (or DMA request) using the function
- TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIMx Channel1 according to the specified parameters in
- * the TIM_OCInitStruct.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M;
- tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S;
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC1P;
- /* Set the Output Compare Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-
- /* Set the Output State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
- /* Set the Output N Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
- /* Reset the Output N State */
- tmpccer &= (uint16_t)~TIM_CCER_CC1NE;
-
- /* Set the Output N State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS1;
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N;
- /* Set the Output Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel2 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M;
- tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC2P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
- /* Reset the Output N State */
- tmpccer &= (uint16_t)~TIM_CCER_CC2NE;
-
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS2;
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N;
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel3 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M;
- tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S;
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC3P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
- /* Reset the Output N State */
- tmpccer &= (uint16_t)~TIM_CCER_CC3NE;
-
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS3;
- tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N;
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel4 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M;
- tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)~TIM_CCER_CC4P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
- /* Reset the Output Compare IDLE State */
- tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4;
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Fills each TIM_OCInitStruct member with its default value.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- /* Set the default configuration */
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
- TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
- TIM_OCInitStruct->TIM_Pulse = 0x00000000;
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
- TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-/**
- * @brief Selects the TIM Output Compare Mode.
- * @note This function disables the selected channel before changing the Output
- * Compare Mode. If needed, user has to enable this channel using
- * TIM_CCxCmd() and TIM_CCxNCmd() functions.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.
- * This parameter can be one of the following values:
- * @arg TIM_OCMode_Timing
- * @arg TIM_OCMode_Active
- * @arg TIM_OCMode_Toggle
- * @arg TIM_OCMode_PWM1
- * @arg TIM_OCMode_PWM2
- * @arg TIM_ForcedAction_Active
- * @arg TIM_ForcedAction_InActive
- * @retval None
- */
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
-{
- uint32_t tmp = 0;
- uint16_t tmp1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_OCM(TIM_OCMode));
-
- tmp = (uint32_t) TIMx;
- tmp += CCMR_OFFSET;
-
- tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
-
- /* Disable the Channel: Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t) ~tmp1;
-
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
- {
- tmp += (TIM_Channel>>1);
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= TIM_OCMode;
- }
- else
- {
- tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
- }
-}
-
-/**
- * @brief Sets the TIMx Capture Compare1 Register value
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param Compare1: specifies the Capture Compare1 register new value.
- * @retval None
- */
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-
- /* Set the Capture Compare1 Register value */
- TIMx->CCR1 = Compare1;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare2 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param Compare2: specifies the Capture Compare2 register new value.
- * @retval None
- */
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Set the Capture Compare2 Register value */
- TIMx->CCR2 = Compare2;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare3 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare3: specifies the Capture Compare3 register new value.
- * @retval None
- */
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare3 Register value */
- TIMx->CCR3 = Compare3;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare4 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare4: specifies the Capture Compare4 register new value.
- * @retval None
- */
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare4 Register value */
- TIMx->CCR4 = Compare4;
-}
-
-/**
- * @brief Forces the TIMx output 1 waveform to active or inactive level.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
- * @retval None
- */
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1M Bits */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M;
-
- /* Configure The Forced output Mode */
- tmpccmr1 |= TIM_ForcedAction;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 2 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
- * @retval None
- */
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2M Bits */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M;
-
- /* Configure The Forced output Mode */
- tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 3 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
- * @retval None
- */
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC1M Bits */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M;
-
- /* Configure The Forced output Mode */
- tmpccmr2 |= TIM_ForcedAction;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Forces the TIMx output 4 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
- * @retval None
- */
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC2M Bits */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M;
-
- /* Configure The Forced output Mode */
- tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1PE Bit */
- tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= TIM_OCPreload;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2PE Bit */
- tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3PE Bit */
- tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= TIM_OCPreload;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4PE Bit */
- tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 1 Fast feature.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1FE Bit */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= TIM_OCFast;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 2 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2FE Bit */
- tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 3 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3FE Bit */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= TIM_OCFast;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 4 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4FE Bit */
- tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF1 signal on an external event
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1CE Bit */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= TIM_OCClear;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF2 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2CE Bit */
- tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF3 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3CE Bit */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= TIM_OCClear;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF4 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4CE Bit */
- tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx channel 1 polarity.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC1 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC1P Bit */
- tmpccer &= (uint16_t)(~TIM_CCER_CC1P);
- tmpccer |= TIM_OCPolarity;
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 1N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC1N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC1NP Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
- tmpccer |= TIM_OCNPolarity;
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 2 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_OCPolarity: specifies the OC2 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC2P Bit */
- tmpccer &= (uint16_t)(~TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 2N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC2N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC2NP Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 3 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC3 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC3P Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC3P;
- tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 3N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC3N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC3NP Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 4 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC4 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC4P Bit */
- tmpccer &= (uint16_t)~TIM_CCER_CC4P;
- tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCX(TIM_CCx));
-
- tmp = CCER_CCE_SET << TIM_Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t)~ tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
- * @retval None
- */
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCXN(TIM_CCxN));
-
- tmp = CCER_CCNE_SET << TIM_Channel;
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= (uint16_t) ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group3 Input Capture management functions
- * @brief Input Capture management functions
- *
-@verbatim
- ===============================================================================
- ##### Input Capture management functions #####
- ===============================================================================
-
- ##### TIM Driver: how to use it in Input Capture Mode #####
- ===============================================================================
- [..]
- To use the Timer in Input Capture mode, the following steps are mandatory:
-
- (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
- function
-
- (#) Configure the TIM pins by configuring the corresponding GPIO pins
-
- (#) Configure the Time base unit as described in the first part of this driver,
- if needed, else the Timer will run with the default configuration:
- (++) Autoreload value = 0xFFFF
- (++) Prescaler value = 0x0000
- (++) Counter mode = Up counting
- (++) Clock Division = TIM_CKD_DIV1
-
- (#) Fill the TIM_ICInitStruct with the desired parameters including:
- (++) TIM Channel: TIM_Channel
- (++) TIM Input Capture polarity: TIM_ICPolarity
- (++) TIM Input Capture selection: TIM_ICSelection
- (++) TIM Input Capture Prescaler: TIM_ICPrescaler
- (++) TIM Input CApture filter value: TIM_ICFilter
-
- (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel
- with the corresponding configuration and to measure only frequency
- or duty cycle of the input signal, or, Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct)
- to configure the desired channels with the corresponding configuration
- and to measure the frequency and the duty cycle of the input signal
-
- (#) Enable the NVIC or the DMA to read the measured frequency.
-
- (#) Enable the corresponding interrupt (or DMA request) to read the Captured
- value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx)
- (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
-
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-
- (#) Use TIM_GetCapturex(TIMx); to read the captured value.
-
- -@- All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIM peripheral according to the specified parameters
- * in the TIM_ICInitStruct.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
-
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
- {
- /* TI2 Configuration */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
- {
- /* TI3 Configuration */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI4 Configuration */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Fills each TIM_ICInitStruct member with its default value.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
- TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/**
- * @brief Configures the TIM peripheral according to the specified parameters
- * in the TIM_ICInitStruct to measure an external PWM signal.
- * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Select the Opposite Input Polarity */
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
- {
- icoppositepolarity = TIM_ICPolarity_Falling;
- }
- else
- {
- icoppositepolarity = TIM_ICPolarity_Rising;
- }
- /* Select the Opposite Input */
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
- {
- icoppositeselection = TIM_ICSelection_IndirectTI;
- }
- else
- {
- icoppositeselection = TIM_ICSelection_DirectTI;
- }
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI2 Configuration */
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI1 Configuration */
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Gets the TIMx Input Capture 1 value.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @retval Capture Compare 1 Register value.
- */
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-
- /* Get the Capture 1 Register value */
- return TIMx->CCR1;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 2 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @retval Capture Compare 2 Register value.
- */
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Get the Capture 2 Register value */
- return TIMx->CCR2;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 3 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @retval Capture Compare 3 Register value.
- */
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 3 Register value */
- return TIMx->CCR3;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 4 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @retval Capture Compare 4 Register value.
- */
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 4 Register value */
- return TIMx->CCR4;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 1 prescaler.
- * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC1PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC;
-
- /* Set the IC1PSC value */
- TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 2 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC2PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC;
-
- /* Set the IC2PSC value */
- TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @brief Sets the TIMx Input Capture 3 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC3PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
-
- /* Set the IC3PSC value */
- TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 4 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC4PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
-
- /* Set the IC4PSC value */
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
- * @brief Advanced-control timers (TIM1 and TIM8) specific features
- *
-@verbatim
- ===============================================================================
- ##### Advanced-control timers (TIM1 and TIM8) specific features #####
- ===============================================================================
-
- ##### TIM Driver: how to use the Break feature #####
- ===============================================================================
- [..]
- After configuring the Timer channel(s) in the appropriate Output Compare mode:
-
- (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
- Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
- AOE(automatic output enable).
-
- (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
-
- (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
-
- (#) Once the break even occurs, the Timer's output signals are put in reset
- state or in a known state (according to the configuration made in
- TIM_BDTRConfig() function).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param TIMx: where x can be 1 or 8 to select the TIM
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @retval None
- */
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
- assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
- assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
- assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
- assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
- TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
- TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
- TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
- TIM_BDTRInitStruct->TIM_AutomaticOutput;
-}
-
-/**
- * @brief Fills each TIM_BDTRInitStruct member with its default value.
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
- TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
- TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
- TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
- TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
- TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
- TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-/**
- * @brief Enables or disables the TIM peripheral Main Outputs.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
- * @param NewState: new state of the TIM peripheral Main Outputs.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Main Output */
- TIMx->BDTR |= TIM_BDTR_MOE;
- }
- else
- {
- /* Disable the TIM Main Output */
- TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
- }
-}
-
-/**
- * @brief Selects the TIM peripheral Commutation event.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
- * @param NewState: new state of the Commutation event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the COM Bit */
- TIMx->CR2 |= TIM_CR2_CCUS;
- }
- else
- {
- /* Reset the COM Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
- }
-}
-
-/**
- * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
- * @param NewState: new state of the Capture Compare Preload Control bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the CCPC Bit */
- TIMx->CR2 |= TIM_CR2_CCPC;
- }
- else
- {
- /* Reset the CCPC Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
- * @brief Interrupts, DMA and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts, DMA and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified TIM interrupts.
- * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
- * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
- * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
- * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
- * be used: TIM_IT_Update or TIM_IT_CC1
- * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8
- *
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- TIMx->DIER |= TIM_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- TIMx->DIER &= (uint16_t)~TIM_IT;
- }
-}
-
-/**
- * @brief Configures the TIMx event to be generate by software.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_EventSource: specifies the event source.
- * This parameter can be one or more of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_COM: Timer COM event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @arg TIM_EventSource_Break: Timer Break event source
- *
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
-
- /* Set the event sources */
- TIMx->EGR = TIM_EventSource;
-}
-
-/**
- * @brief Checks whether the specified TIM flag is set or not.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
- *
- * @retval The new state of TIM_FLAG (SET or RESET).
- */
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
-
-
- if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's pending flags.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Clear the flags */
- TIMx->SR = (uint16_t)~TIM_FLAG;
-}
-
-/**
- * @brief Checks whether the TIM interrupt has occurred or not.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_IT: specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
- *
- * @retval The new state of the TIM_IT(SET or RESET).
- */
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itstatus = 0x0, itenable = 0x0;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_IT(TIM_IT));
-
- itstatus = TIMx->SR & TIM_IT;
-
- itenable = TIMx->DIER & TIM_IT;
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's interrupt pending bits.
- * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
- * @param TIM_IT: specifies the pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM1 update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Clear the IT pending Bit */
- TIMx->SR = (uint16_t)~TIM_IT;
-}
-
-/**
- * @brief Configures the TIMx's DMA interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_DMABase: DMA Base address.
- * This parameter can be one of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM1_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_RCR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_BDTR
- * @arg TIM_DMABase_DCR
- * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
- * @retval None
- */
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
-
- /* Set the DMA Base and the DMA Burst Length */
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/**
- * @brief Enables or disables the TIMx's DMA Requests.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
- * @param TIM_DMASource: specifies the DMA Request sources.
- * This parameter can be any combination of the following values:
- * @arg TIM_DMA_Update: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA sources */
- TIMx->DIER |= TIM_DMASource;
- }
- else
- {
- /* Disable the DMA sources */
- TIMx->DIER &= (uint16_t)~TIM_DMASource;
- }
-}
-
-/**
- * @brief Selects the TIMx peripheral Capture Compare DMA source.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param NewState: new state of the Capture Compare DMA source
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the CCDS Bit */
- TIMx->CR2 |= TIM_CR2_CCDS;
- }
- else
- {
- /* Reset the CCDS Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group6 Clocks management functions
- * @brief Clocks management functions
- *
-@verbatim
- ===============================================================================
- ##### Clocks management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx internal Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @retval None
- */
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
-}
-
-/**
- * @brief Configures the TIMx Internal Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_InputTriggerSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @retval None
- */
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Select the Internal Trigger */
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
-
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the TIMx Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
- * to select the TIM peripheral.
- * @param TIM_TIxExternalCLKSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
- * @param TIM_ICPolarity: specifies the TIx Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param ICFilter: specifies the filter value.
- * This parameter must be a value between 0x0 and 0xF.
- * @retval None
- */
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
- assert_param(IS_TIM_IC_FILTER(ICFilter));
-
- /* Configure the Timer Input Clock Source */
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
- {
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- else
- {
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- /* Select the Trigger source */
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the External clock Mode1
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the SMS Bits */
- tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
-
- /* Select the External clock mode1 */
- tmpsmcr |= TIM_SlaveMode_External1;
-
- /* Select the Trigger selection : ETRF */
- tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
- tmpsmcr |= TIM_TS_ETRF;
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the External clock Mode2
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Enable the External clock mode2 */
- TIMx->SMCR |= TIM_SMCR_ECE;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group7 Synchronization management functions
- * @brief Synchronization management functions
- *
-@verbatim
- ===============================================================================
- ##### Synchronization management functions #####
- ===============================================================================
-
- ##### TIM Driver: how to use it in synchronization Mode #####
- ===============================================================================
- [..]
-
- *** Case of two/several Timers ***
- ==================================
- [..]
- (#) Configure the Master Timers using the following functions:
- (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
- (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
- (#) Configure the Slave Timers using the following functions:
- (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
- (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-
- *** Case of Timers and external trigger(ETR pin) ***
- ====================================================
- [..]
- (#) Configure the External trigger using this function:
- (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
- (#) Configure the Slave Timers using the following functions:
- (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
- (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
- * to select the TIM peripheral.
- * @param TIM_InputTriggerSource: The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the TS Bits */
- tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
-
- /* Set the Input Trigger source */
- tmpsmcr |= TIM_InputTriggerSource;
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Selects the TIMx Trigger Output Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
- *
- * @param TIM_TRGOSource: specifies the Trigger Output source.
- * This parameter can be one of the following values:
- *
- * - For all TIMx
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
- *
- * - For all TIMx except TIM6 and TIM7
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
- * is to be set, as soon as a capture or compare match occurs(TRGO)
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
- *
- * @retval None
- */
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
-
- /* Reset the MMS Bits */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
- /* Select the TRGO source */
- TIMx->CR2 |= TIM_TRGOSource;
-}
-
-/**
- * @brief Selects the TIMx Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize
- * the counter and triggers an update of the registers
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
- * @retval None
- */
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
-
- /* Reset the SMS Bits */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
-
- /* Select the Slave Mode */
- TIMx->SMCR |= TIM_SlaveMode;
-}
-
-/**
- * @brief Sets or Resets the TIMx Master/Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
- * and its slaves (through TRGO)
- * @arg TIM_MasterSlaveMode_Disable: No action
- * @retval None
- */
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
-
- /* Reset the MSM Bit */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
-
- /* Set or Reset the MSM Bit */
- TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the ETR Bits */
- tmpsmcr &= SMCR_ETR_MASK;
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group8 Specific interface management functions
- * @brief Specific interface management functions
- *
-@verbatim
- ===============================================================================
- ##### Specific interface management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx Encoder Interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
- * This parameter can be one of the following values:
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
- * on the level of the other input.
- * @param TIM_IC1Polarity: specifies the IC1 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @param TIM_IC2Polarity: specifies the IC2 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @retval None
- */
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
-{
- uint16_t tmpsmcr = 0;
- uint16_t tmpccmr1 = 0;
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
- tmpsmcr |= TIM_EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIMx's Hall sensor interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param NewState: new state of the TIMx Hall sensor interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the TI1S Bit */
- TIMx->CR2 |= TIM_CR2_TI1S;
- }
- else
- {
- /* Reset the TI1S Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group9 Specific remapping management function
- * @brief Specific remapping management function
- *
-@verbatim
- ===============================================================================
- ##### Specific remapping management function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
- * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral.
- * @param TIM_Remap: specifies the TIM input remapping source.
- * This parameter can be one of the following values:
- * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
- * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output.
- * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
- * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
- * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
- * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
- * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
- * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
- * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
- * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
- * (HSE divided by a programmable prescaler)
- * @retval None
- */
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_REMAP(TIM_Remap));
-
- /* Set the Timer remapping configuration */
- TIMx->OR = TIM_Remap;
-}
-/**
- * @}
- */
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
- * to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input and set the filter */
- tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
- tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 4);
-
- /* Select the Input and set the filter */
- tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
- tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
- tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 8);
-
- /* Select the Input and set the filter */
- tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 12);
-
- /* Select the Input and set the filter */
- tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
-
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer ;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
deleted file mode 100644
index 40f2391e..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
+++ /dev/null
@@ -1,1486 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_usart.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Universal synchronous asynchronous receiver
- * transmitter (USART):
- * + Initialization and Configuration
- * + Data transfers
- * + Multi-Processor Communication
- * + LIN mode
- * + Half-duplex mode
- * + Smartcard mode
- * + IrDA mode
- * + DMA transfers management
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable peripheral clock using the following functions
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3,
- UART4 or UART5.
-
- (#) According to the USART mode, enable the GPIO clocks using
- RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS,
- or/and SCLK).
-
- (#) Peripheral's alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function
-
- (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) using the USART_Init()
- function.
-
- (#) For synchronous mode, enable the clock and program the polarity,
- phase and last bit using the USART_ClockInit() function.
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- USART_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function
- (++) Active the needed channel Request using USART_DMACmd() function
-
- (#) Enable the USART using the USART_Cmd() function.
-
- (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
-
- -@- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
- for more details
-
- [..]
- In order to reach higher communication baudrates, it is possible to
- enable the oversampling by 8 mode using the function USART_OverSampling8Cmd().
- This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd())
- and before calling the function USART_Init().
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_usart.h"
-#include "stm32f4xx_rcc.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup USART
- * @brief USART driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */
-#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \
- USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE))
-
-/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */
-#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
- USART_CR2_CPHA | USART_CR2_LBCL))
-
-/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */
-#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-
-/*!< USART Interrupts mask */
-#define IT_MASK ((uint16_t)0x001F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup USART_Private_Functions
- * @{
- */
-
-/** @defgroup USART_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible USART frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
- (++) Hardware flow control
- (++) Receiver/transmitter modes
-
- [..]
- The USART_Init() function follows the USART asynchronous configuration
- procedure (details for the procedure are available in reference manual (RM0090)).
-
- (+) For the synchronous mode in addition to the asynchronous mode parameters these
- parameters should be also configured:
- (++) USART Clock Enabled
- (++) USART polarity
- (++) USART phase
- (++) USART LastBit
-
- [..]
- These parameters can be configured using the USART_ClockInit() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @retval None
- */
-void USART_DeInit(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- if (USARTx == USART1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
- }
- else if (USARTx == USART2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
- }
- else if (USARTx == USART3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
- }
- else if (USARTx == UART4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
- }
- else if (USARTx == UART5)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
- }
- else if (USARTx == USART6)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
- }
- else if (USARTx == UART7)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE);
- }
- else
- {
- if (USARTx == UART8)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the USARTx peripheral according to the specified
- * parameters in the USART_InitStruct .
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains
- * the configuration information for the specified USART peripheral.
- * @retval None
- */
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
- uint32_t tmpreg = 0x00, apbclock = 0x00;
- uint32_t integerdivider = 0x00;
- uint32_t fractionaldivider = 0x00;
- RCC_ClocksTypeDef RCC_ClocksStatus;
-
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
-
- /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
- if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
-
- /* Clear STOP[13:12] bits */
- tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit :
- Set STOP[13:12] bits according to USART_StopBits value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
-
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = USARTx->CR1;
-
- /* Clear M, PCE, PS, TE and RE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
-
- /* Configure the USART Word Length, Parity and mode:
- Set the M bits according to USART_WordLength value
- Set PCE and PS bits according to USART_Parity value
- Set TE and RE bits according to USART_Mode value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
- USART_InitStruct->USART_Mode;
-
- /* Write to USART CR1 */
- USARTx->CR1 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR3 Configuration -----------------------*/
- tmpreg = USARTx->CR3;
-
- /* Clear CTSE and RTSE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
-
- /* Configure the USART HFC :
- Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
-
- /* Write to USART CR3 */
- USARTx->CR3 = (uint16_t)tmpreg;
-
-/*---------------------------- USART BRR Configuration -----------------------*/
- /* Configure the USART Baud Rate */
- RCC_GetClocksFreq(&RCC_ClocksStatus);
-
- if ((USARTx == USART1) || (USARTx == USART6))
- {
- apbclock = RCC_ClocksStatus.PCLK2_Frequency;
- }
- else
- {
- apbclock = RCC_ClocksStatus.PCLK1_Frequency;
- }
-
- /* Determine the integer part */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- /* Integer part computing in case Oversampling mode is 8 Samples */
- integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
- }
- else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
- {
- /* Integer part computing in case Oversampling mode is 16 Samples */
- integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
- }
- tmpreg = (integerdivider / 100) << 4;
-
- /* Determine the fractional part */
- fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
-
- /* Implement the fractional part in the register */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
- }
- else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
- {
- tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
- }
-
- /* Write to USART BRR register */
- USARTx->BRR = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_InitStruct member with its default value.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
- /* USART_InitStruct members default value */
- USART_InitStruct->USART_BaudRate = 9600;
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;
- USART_InitStruct->USART_StopBits = USART_StopBits_1;
- USART_InitStruct->USART_Parity = USART_Parity_No ;
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-}
-
-/**
- * @brief Initializes the USARTx peripheral Clock according to the
- * specified parameters in the USART_ClockInitStruct .
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that
- * contains the configuration information for the specified USART peripheral.
- * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
- * @retval None
- */
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- uint32_t tmpreg = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear CLKEN, CPOL, CPHA and LBCL bits */
- tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
- /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
- /* Set CLKEN bit according to USART_Clock value */
- /* Set CPOL bit according to USART_CPOL value */
- /* Set CPHA bit according to USART_CPHA value */
- /* Set LBCL bit according to USART_LastBit value */
- tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_ClockInitStruct member with its default value.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- /* USART_ClockInitStruct members default value */
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/**
- * @brief Enables or disables the specified USART peripheral.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USARTx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART by setting the UE bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_UE;
- }
- else
- {
- /* Disable the selected USART by clearing the UE bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);
- }
-}
-
-/**
- * @brief Sets the system clock prescaler.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_Prescaler: specifies the prescaler clock.
- * @note The function is used for IrDA mode with UART4 and UART5.
- * @retval None
- */
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Clear the USART prescaler */
- USARTx->GTPR &= USART_GTPR_GT;
- /* Set the USART prescaler */
- USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
- * @brief Enables or disables the USART's 8x oversampling mode.
- * @note This function has to be called before calling USART_Init() function
- * in order to have correct baudrate Divider value.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART 8x oversampling mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_OVER8;
- }
- else
- {
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);
- }
-}
-
-/**
- * @brief Enables or disables the USART's one bit sampling method.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART one bit sampling method.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_ONEBIT;
- }
- else
- {
- /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART data
- transfers.
- [..]
- During an USART reception, data shifts in least significant bit first through
- the RX pin. In this mode, the USART_DR register consists of a buffer (RDR)
- between the internal bus and the received shift register.
- [..]
- When a transmission is taking place, a write instruction to the USART_DR register
- stores the data in the TDR register and which is copied in the shift register
- at the end of the current transmission.
- [..]
- The read access of the USART_DR register can be done using the USART_ReceiveData()
- function and returns the RDR buffered value. Whereas a write access to the USART_DR
- can be done using USART_SendData() function and stores the written data into
- TDR buffer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits single data through the USARTx peripheral.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param Data: the data to transmit.
- * @retval None
- */
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DATA(Data));
-
- /* Transmit Data */
- USARTx->DR = (Data & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Returns the most recent received data by the USARTx peripheral.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @retval The received data.
- */
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Receive Data */
- return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group3 MultiProcessor Communication functions
- * @brief Multi-Processor Communication functions
- *
-@verbatim
- ===============================================================================
- ##### Multi-Processor Communication functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART
- multiprocessor communication.
- [..]
- For instance one of the USARTs can be the master, its TX output is connected
- to the RX input of the other USART. The others are slaves, their respective
- TX outputs are logically ANDed together and connected to the RX input of the
- master.
- [..]
- USART multiprocessor communication is possible through the following procedure:
- (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode
- transmitter or Mode receiver and hardware flow control values using
- the USART_Init() function.
- (#) Configures the USART address using the USART_SetAddress() function.
- (#) Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)
- using USART_WakeUpConfig() function only for the slaves.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.
- [..]
- The USART Slave exit from mute mode when receive the wake up condition.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the address of the USART node.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_Address: Indicates the address of the USART node.
- * @retval None
- */
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_ADDRESS(USART_Address));
-
- /* Clear the USART address */
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);
- /* Set the USART address node */
- USARTx->CR2 |= USART_Address;
-}
-
-/**
- * @brief Determines if the USART is in mute mode or not.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART mute mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_RWU;
- }
- else
- {
- /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);
- }
-}
-/**
- * @brief Selects the USART WakeUp method.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_WakeUp: specifies the USART wakeup method.
- * This parameter can be one of the following values:
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
- * @retval None
- */
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_WAKEUP(USART_WakeUp));
-
- USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);
- USARTx->CR1 |= USART_WakeUp;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group4 LIN mode functions
- * @brief LIN mode functions
- *
-@verbatim
- ===============================================================================
- ##### LIN mode functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART LIN
- Mode communication.
- [..]
- In LIN mode, 8-bit data format with 1 stop bit is required in accordance with
- the LIN standard.
- [..]
- Only this LIN Feature is supported by the USART IP:
- (+) LIN Master Synchronous Break send capability and LIN slave break detection
- capability : 13-bit break generation and 10/11 bit break detection
-
- [..]
- USART LIN Master transmitter communication is possible through the following
- procedure:
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values using
- the USART_Init() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enable the LIN mode using the USART_LINCmd() function.
- (#) Send the break character using USART_SendBreak() function.
- [..]
- USART LIN Master receiver communication is possible through the following procedure:
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values using
- the USART_Init() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Configures the break detection length using the USART_LINBreakDetectLengthConfig()
- function.
- (#) Enable the LIN mode using the USART_LINCmd() function.
-
- -@- In LIN mode, the following bits must be kept cleared:
- (+@) CLKEN in the USART_CR2 register,
- (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the USART LIN Break detection length.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
- * @retval None
- */
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);
- USARTx->CR2 |= USART_LINBreakDetectLength;
-}
-
-/**
- * @brief Enables or disables the USART's LIN mode.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART LIN mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_LINEN;
- }
- else
- {
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
- USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);
- }
-}
-
-/**
- * @brief Transmits break characters.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @retval None
- */
-void USART_SendBreak(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Send break characters */
- USARTx->CR1 |= USART_CR1_SBK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group5 Halfduplex mode function
- * @brief Half-duplex mode function
- *
-@verbatim
- ===============================================================================
- ##### Half-duplex mode function #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART
- Half-duplex communication.
- [..]
- The USART can be configured to follow a single-wire half-duplex protocol where
- the TX and RX lines are internally connected.
- [..]
- USART Half duplex communication is possible through the following procedure:
- (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter
- or Mode receiver and hardware flow control values using the USART_Init()
- function.
- (#) Configures the USART address using the USART_SetAddress() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
-
-
- -@- The RX pin is no longer used
- -@- In Half-duplex mode the following bits must be kept cleared:
- (+@) LINEN and CLKEN bits in the USART_CR2 register.
- (+@) SCEN and IREN bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's Half Duplex communication.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the USART Communication.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_HDSEL;
- }
- else
- {
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);
- }
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group6 Smartcard mode functions
- * @brief Smartcard mode functions
- *
-@verbatim
- ===============================================================================
- ##### Smartcard mode functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART
- Smartcard communication.
- [..]
- The Smartcard interface is designed to support asynchronous protocol Smartcards as
- defined in the ISO 7816-3 standard.
- [..]
- The USART can provide a clock to the smartcard through the SCLK output.
- In smartcard mode, SCLK is not associated to the communication but is simply derived
- from the internal peripheral input clock through a 5-bit prescaler.
- [..]
- Smartcard communication is possible through the following procedure:
- (#) Configures the Smartcard Prescaler using the USART_SetPrescaler() function.
- (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() function.
- (#) Program the USART clock using the USART_ClockInit() function as following:
- (++) USART Clock enabled
- (++) USART CPOL Low
- (++) USART CPHA on first edge
- (++) USART Last Bit Clock Enabled
- (#) Program the Smartcard interface using the USART_Init() function as following:
- (++) Word Length = 9 Bits
- (++) 1.5 Stop Bit
- (++) Even parity
- (++) BaudRate = 12096 baud
- (++) Hardware flow control disabled (RTS and CTS signals)
- (++) Tx and Rx enabled
- (#) POptionally you can enable the parity error interrupt using the USART_ITConfig()
- function
- (#) PEnable the USART using the USART_Cmd() function.
- (#) PEnable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
- (#) PEnable the Smartcard interface using the USART_SmartCardCmd() function.
-
- Please refer to the ISO 7816-3 specification for more details.
-
- -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended
- to use 1.5 stop bits for both transmitting and receiving to avoid switching
- between the two configurations.
- -@- In smartcard mode, the following bits must be kept cleared:
- (+@) LINEN bit in the USART_CR2 register.
- (+@) HDSEL and IREN bits in the USART_CR3 register.
- -@- Smartcard mode is available on USART peripherals only (not available on UART4
- and UART5 peripherals).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the specified USART guard time.
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
- * UART peripheral.
- * @param USART_GuardTime: specifies the guard time.
- * @retval None
- */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
-
- /* Clear the USART Guard time */
- USARTx->GTPR &= USART_GTPR_PSC;
- /* Set the USART guard time */
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
- * @brief Enables or disables the USART's Smart Card mode.
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the Smart Card mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_SCEN;
- }
- else
- {
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);
- }
-}
-
-/**
- * @brief Enables or disables NACK transmission.
- * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the NACK transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_1236_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_NACK;
- }
- else
- {
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group7 IrDA mode functions
- * @brief IrDA mode functions
- *
-@verbatim
- ===============================================================================
- ##### IrDA mode functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART
- IrDA communication.
- [..]
- IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
- on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
- is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
- While receiving data, transmission should be avoided as the data to be transmitted
- could be corrupted.
- [..]
- IrDA communication is possible through the following procedure:
- (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver
- modes and hardware flow control values using the USART_Init() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Configures the IrDA pulse width by configuring the prescaler using
- the USART_SetPrescaler() function.
- (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode
- using the USART_IrDAConfig() function.
- (#) Enable the IrDA using the USART_IrDACmd() function.
-
- -@- A pulse of width less than two and greater than one PSC period(s) may or may
- not be rejected.
- -@- The receiver set up time should be managed by software. The IrDA physical layer
- specification specifies a minimum of 10 ms delay between transmission and
- reception (IrDA is a half duplex protocol).
- -@- In IrDA mode, the following bits must be kept cleared:
- (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
- (+@) SCEN and HDSEL bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the USART's IrDA interface.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_IrDAMode: specifies the IrDA mode.
- * This parameter can be one of the following values:
- * @arg USART_IrDAMode_LowPower
- * @arg USART_IrDAMode_Normal
- * @retval None
- */
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);
- USARTx->CR3 |= USART_IrDAMode;
-}
-
-/**
- * @brief Enables or disables the USART's IrDA interface.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param NewState: new state of the IrDA mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_IREN;
- }
- else
- {
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
- USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group8 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's DMA interface.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_DMAReq: specifies the DMA request.
- * This parameter can be any combination of the following values:
- * @arg USART_DMAReq_Tx: USART DMA transmit request
- * @arg USART_DMAReq_Rx: USART DMA receive request
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DMAREQ(USART_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 |= USART_DMAReq;
- }
- else
- {
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 &= (uint16_t)~USART_DMAReq;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group9 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to configure the USART
- Interrupts sources, DMA channels requests and check or clear the flags or
- pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- *** Polling Mode ***
- ====================
- [..]
- In Polling Mode, the SPI communication can be managed by 10 flags:
- (#) USART_FLAG_TXE : to indicate the status of the transmit buffer register
- (#) USART_FLAG_RXNE : to indicate the status of the receive buffer register
- (#) USART_FLAG_TC : to indicate the status of the transmit operation
- (#) USART_FLAG_IDLE : to indicate the status of the Idle Line
- (#) USART_FLAG_CTS : to indicate the status of the nCTS input
- (#) USART_FLAG_LBD : to indicate the status of the LIN break detection
- (#) USART_FLAG_NE : to indicate if a noise error occur
- (#) USART_FLAG_FE : to indicate if a frame error occur
- (#) USART_FLAG_PE : to indicate if a parity error occur
- (#) USART_FLAG_ORE : to indicate if an Overrun error occur
- [..]
- In this Mode it is advised to use the following functions:
- (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
- (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..]
- In Interrupt Mode, the USART communication can be managed by 8 interrupt sources
- and 10 pending bits:
-
- (#) Pending Bits:
-
- (##) USART_IT_TXE : to indicate the status of the transmit buffer register
- (##) USART_IT_RXNE : to indicate the status of the receive buffer register
- (##) USART_IT_TC : to indicate the status of the transmit operation
- (##) USART_IT_IDLE : to indicate the status of the Idle Line
- (##) USART_IT_CTS : to indicate the status of the nCTS input
- (##) USART_IT_LBD : to indicate the status of the LIN break detection
- (##) USART_IT_NE : to indicate if a noise error occur
- (##) USART_IT_FE : to indicate if a frame error occur
- (##) USART_IT_PE : to indicate if a parity error occur
- (##) USART_IT_ORE : to indicate if an Overrun error occur
-
- (#) Interrupt Source:
-
- (##) USART_IT_TXE : specifies the interrupt source for the Tx buffer empty
- interrupt.
- (##) USART_IT_RXNE : specifies the interrupt source for the Rx buffer not
- empty interrupt.
- (##) USART_IT_TC : specifies the interrupt source for the Transmit complete
- interrupt.
- (##) USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt.
- (##) USART_IT_CTS : specifies the interrupt source for the CTS interrupt.
- (##) USART_IT_LBD : specifies the interrupt source for the LIN break detection
- interrupt.
- (##) USART_IT_PE : specifies the interrupt source for the parity error interrupt.
- (##) USART_IT_ERR : specifies the interrupt source for the errors interrupt.
-
- -@@- Some parameters are coded in order to use them as interrupt source
- or as pending bits.
- [..]
- In this Mode it is advised to use the following functions:
- (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
- (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
- (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
-
- *** DMA Mode ***
- ================
- [..]
- In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:
- (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request
- (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request
- [..]
- In this Mode it is advised to use the following function:
- (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified USART interrupts.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified USARTx interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
-{
- uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
- uint32_t usartxbase = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CONFIG_IT(USART_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- usartxbase = (uint32_t)USARTx;
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
-
- /* Get the interrupt position */
- itpos = USART_IT & IT_MASK;
- itmask = (((uint32_t)0x01) << itpos);
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- usartxbase += 0x0C;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- usartxbase += 0x10;
- }
- else /* The IT is in CR3 register */
- {
- usartxbase += 0x14;
- }
- if (NewState != DISABLE)
- {
- *(__IO uint32_t*)usartxbase |= itmask;
- }
- else
- {
- *(__IO uint32_t*)usartxbase &= ~itmask;
- }
-}
-
-/**
- * @brief Checks whether the specified USART flag is set or not.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
- * @arg USART_FLAG_LBD: LIN Break detection flag
- * @arg USART_FLAG_TXE: Transmit data register empty flag
- * @arg USART_FLAG_TC: Transmission Complete flag
- * @arg USART_FLAG_RXNE: Receive data register not empty flag
- * @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
- * @arg USART_FLAG_NE: Noise Error flag
- * @arg USART_FLAG_FE: Framing Error flag
- * @arg USART_FLAG_PE: Parity Error flag
- * @retval The new state of USART_FLAG (SET or RESET).
- */
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_FLAG(USART_FLAG));
-
- /* The CTS flag is not available for UART4 and UART5 */
- if (USART_FLAG == USART_FLAG_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's pending flags.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
- * @arg USART_FLAG_LBD: LIN Break detection flag.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) flags are cleared by software
- * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
- * followed by a read operation to USART_DR register (USART_ReceiveData()).
- * @note RXNE flag can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * @note TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register (USART_GetFlagStatus()) followed by a write operation
- * to USART_DR register (USART_SendData()).
- * @note TXE flag is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- *
- * @retval None
- */
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
-
- /* The CTS flag is not available for UART4 and UART5 */
- if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- USARTx->SR = (uint16_t)~USART_FLAG;
-}
-
-/**
- * @brief Checks whether the specified USART interrupt has occurred or not.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_IT: specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set
- * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set
- * @arg USART_IT_NE: Noise Error interrupt
- * @arg USART_IT_FE: Framing Error interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @retval The new state of USART_IT (SET or RESET).
- */
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_GET_IT(USART_IT));
-
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
- /* Get the interrupt position */
- itmask = USART_IT & IT_MASK;
- itmask = (uint32_t)0x01 << itmask;
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- itmask &= USARTx->CR1;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- itmask &= USARTx->CR2;
- }
- else /* The IT is in CR3 register */
- {
- itmask &= USARTx->CR3;
- }
-
- bitpos = USART_IT >> 0x08;
- bitpos = (uint32_t)0x01 << bitpos;
- bitpos &= USARTx->SR;
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's interrupt pending bits.
- * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param USART_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) pending bits are cleared by
- * software sequence: a read operation to USART_SR register
- * (USART_GetITStatus()) followed by a read operation to USART_DR register
- * (USART_ReceiveData()).
- * @note RXNE pending bit can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * @note TC pending bit can be also cleared by software sequence: a read
- * operation to USART_SR register (USART_GetITStatus()) followed by a write
- * operation to USART_DR register (USART_SendData()).
- * @note TXE pending bit is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- *
- * @retval None
- */
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint16_t bitpos = 0x00, itmask = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_IT(USART_IT));
-
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_1236_PERIPH(USARTx));
- }
-
- bitpos = USART_IT >> 0x08;
- itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
- USARTx->SR = (uint16_t)~itmask;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
deleted file mode 100644
index d3e651b3..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_wwdg.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Window watchdog (WWDG) peripheral:
- * + Prescaler, Refresh window and Counter configuration
- * + WWDG activation
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### WWDG features #####
- ===============================================================================
- [..]
- Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the counter (downcounter)
- before to reach 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3F).
- An MCU reset is also generated if the counter value is refreshed
- before the counter has reached the refresh window value. This
- implies that the counter must be refreshed in a limited window.
-
- Once enabled the WWDG cannot be disabled except by a system reset.
-
- WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
- reset occurs.
-
- The WWDG counter input clock is derived from the APB clock divided
- by a programmable prescaler.
-
- WWDG counter clock = PCLK1 / Prescaler
- WWDG timeout = (WWDG counter clock) * (counter value)
-
- Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
-
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function
-
- (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function
-
- (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function
-
- (#) Set the WWDG counter value and start it using WWDG_Enable() function.
- When the WWDG is enabled the counter value should be configured to
- a value greater than 0x40 to prevent generating an immediate reset.
-
- (#) Optionally you can enable the Early wakeup interrupt which is
- generated when the counter reach 0x40.
- Once enabled this interrupt cannot be disabled except by a system reset.
-
- (#) Then the application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
- WWDG_SetCounter() function. This operation must occur only when
- the counter value is lower than the refresh window value,
- programmed using WWDG_SetWindowValue().
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CONF_H
-#define __STM32F4xx_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment the line below to enable peripheral header file inclusion */
-#include "stm32f4xx_adc.h"
-#include "stm32f4xx_can.h"
-#include "stm32f4xx_crc.h"
-#include "stm32f4xx_cryp.h"
-#include "stm32f4xx_dac.h"
-#include "stm32f4xx_dbgmcu.h"
-#include "stm32f4xx_dcmi.h"
-#include "stm32f4xx_dma.h"
-#include "stm32f4xx_exti.h"
-#include "stm32f4xx_flash.h"
-#include "stm32f4xx_fsmc.h"
-#include "stm32f4xx_hash.h"
-#include "stm32f4xx_gpio.h"
-#include "stm32f4xx_i2c.h"
-#include "stm32f4xx_iwdg.h"
-#include "stm32f4xx_pwr.h"
-#include "stm32f4xx_rcc.h"
-#include "stm32f4xx_rng.h"
-#include "stm32f4xx_rtc.h"
-#include "stm32f4xx_sdio.h"
-#include "stm32f4xx_spi.h"
-#include "stm32f4xx_syscfg.h"
-#include "stm32f4xx_tim.h"
-#include "stm32f4xx_usart.h"
-#include "stm32f4xx_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* If an external clock source is used, then the value of the following define
- should be set to the value of the external clock source, else, if no external
- clock is used, keep this define commented */
-/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
-
-
-/* Uncomment the line below to expanse the "assert_param" macro in the
- Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT 1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F4xx_CONF_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/clock-arch.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/clock-arch.c
deleted file mode 100644
index d8225115..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/clock-arch.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (c) 2006, Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Institute nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * This file is part of the uIP TCP/IP stack
- *
- * $Id: clock-arch.c,v 1.2 2006/06/12 08:00:31 adam Exp $
- */
-
-/**
- * \file
- * Implementation of architecture-specific clock functionality
- * \author
- * Adam Dunkels
- */
-
-#include "clock-arch.h"
-#include "header.h"
-
-/*---------------------------------------------------------------------------*/
-clock_time_t
-clock_time(void)
-{
- return (clock_time_t)TimerGet();
-}
-/*---------------------------------------------------------------------------*/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/clock-arch.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/clock-arch.h
deleted file mode 100644
index aa97f0e7..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/clock-arch.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2006, Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Institute nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * This file is part of the uIP TCP/IP stack
- *
- * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $
- */
-
-#ifndef __CLOCK_ARCH_H__
-#define __CLOCK_ARCH_H__
-
-typedef int clock_time_t;
-#define CLOCK_CONF_SECOND 1000
-
-#endif /* __CLOCK_ARCH_H__ */
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/netdev.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/netdev.c
deleted file mode 100644
index 3ce42bdf..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/netdev.c
+++ /dev/null
@@ -1,442 +0,0 @@
-/*
- * Copyright (c) 2001, Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the Institute nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * Author: Adam Dunkels
- *
- * $Id: netdev.c,v 1.8 2006/06/07 08:39:58 adam Exp $
- */
-
-
-/*---------------------------------------------------------------------------*/
-#include "uip.h"
-#include "uip_arp.h"
-#include "header.h"
-#include "stm32_eth.h" /* STM32 ethernet library */
-#include /* for memcpy */
-
-
-/*---------------------------------------------------------------------------*/
-#define NETDEV_DEFAULT_MACADDR0 (0x08)
-#define NETDEV_DEFAULT_MACADDR1 (0x00)
-#define NETDEV_DEFAULT_MACADDR2 (0x27)
-#define NETDEV_DEFAULT_MACADDR3 (0x69)
-#define NETDEV_DEFAULT_MACADDR4 (0x5B)
-#define NETDEV_DEFAULT_MACADDR5 (0x45)
-
-
-/*---------------------------------------------------------------------------*/
-static void netdev_TxDscrInit(void);
-static void netdev_RxDscrInit(void);
-
-/*---------------------------------------------------------------------------*/
-typedef union _TranDesc0_t
-{
- uint32_t Data;
- struct {
- uint32_t DB : 1;
- uint32_t UF : 1;
- uint32_t ED : 1;
- uint32_t CC : 4;
- uint32_t VF : 1;
- uint32_t EC : 1;
- uint32_t LC : 1;
- uint32_t NC : 1;
- uint32_t LSC : 1;
- uint32_t IPE : 1;
- uint32_t FF : 1;
- uint32_t JT : 1;
- uint32_t ES : 1;
- uint32_t IHE : 1;
- uint32_t : 3;
- uint32_t TCH : 1;
- uint32_t TER : 1;
- uint32_t CIC : 2;
- uint32_t : 2;
- uint32_t DP : 1;
- uint32_t DC : 1;
- uint32_t FS : 1;
- uint32_t LSEG : 1;
- uint32_t IC : 1;
- uint32_t OWN : 1;
- };
-} TranDesc0_t, * pTranDesc0_t;
-
-typedef union _TranDesc1_t
-{
- uint32_t Data;
- struct {
- uint32_t TBS1 :13;
- uint32_t : 3;
- uint32_t TBS2 :12;
- uint32_t : 3;
- };
-} TranDesc1_t, * pTranDesc1_t;
-
-typedef union _RecDesc0_t
-{
- uint32_t Data;
- struct {
- uint32_t RMAM_PCE : 1;
- uint32_t CE : 1;
- uint32_t DE : 1;
- uint32_t RE : 1;
- uint32_t RWT : 1;
- uint32_t FT : 1;
- uint32_t LC : 1;
- uint32_t IPHCE : 1;
- uint32_t LS : 1;
- uint32_t FS : 1;
- uint32_t VLAN : 1;
- uint32_t OE : 1;
- uint32_t LE : 1;
- uint32_t SAF : 1;
- uint32_t DERR : 1;
- uint32_t ES : 1;
- uint32_t FL :14;
- uint32_t AFM : 1;
- uint32_t OWN : 1;
- };
-} RecDesc0_t, * pRecDesc0_t;
-
-typedef union _recDesc1_t
-{
- uint32_t Data;
- struct {
- uint32_t RBS1 :13;
- uint32_t : 1;
- uint32_t RCH : 1;
- uint32_t RER : 1;
- uint32_t RBS2 :14;
- uint32_t DIC : 1;
- };
-} RecDesc1_t, * pRecDesc1_t;
-
-typedef union _EnetDmaDesc_t
-{
- uint32_t Data[4];
- // Rx DMA descriptor
- struct
- {
- RecDesc0_t RxDesc0;
- RecDesc1_t RxDesc1;
- uint32_t * pBuffer;
- union
- {
- uint32_t * pBuffer2;
- union _EnetDmaDesc_t * pEnetDmaNextDesc;
- };
- } Rx;
- // Tx DMA descriptor
- struct
- {
- TranDesc0_t TxDesc0;
- TranDesc1_t TxDesc1;
- uint32_t * pBuffer1;
- union
- {
- uint32_t * pBuffer2;
- union _EnetDmaDesc_t * pEnetDmaNextDesc;
- };
- } Tx;
-} EnetDmaDesc_t, * pEnetDmaDesc_t;
-
-
-/*---------------------------------------------------------------------------*/
-uint8_t RxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4)));
-uint8_t TxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4)));
-
-EnetDmaDesc_t EnetDmaRx __attribute__((aligned (128)));
-EnetDmaDesc_t EnetDmaTx __attribute__ ((aligned (128)));
-
-
-/*---------------------------------------------------------------------------*/
-void netdev_init(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
- ETH_InitTypeDef ETH_InitStructure;
-
- /* Enable ETHERNET clocks */
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |
- RCC_AHB1Periph_ETH_MAC_Rx | RCC_AHB1Periph_ETH_MAC_PTP, ENABLE);
-
-
- /* Enable GPIOs clocks */
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB |
- RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG, ENABLE);
-
- /* Enable SYSCFG clock */
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- /*Select RMII Interface*/
- SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
-
- /* ETHERNET pins configuration */
- /* PA
- ETH_RMII_REF_CLK: PA1
- ETH_RMII_MDIO: PA2
- ETH_RMII_MDINT: PA3
- ETH_RMII_CRS_DV: PA7
- */
-
- /* Configure PA1, PA2, PA3 and PA7*/
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_7;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
- /* Connect PA1, PA2, PA3 and PA7 to ethernet module*/
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_ETH);
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
-
- /* PB
- ETH_RMII_TX_EN: PG11
- */
-
- /* Configure PG11*/
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOG, &GPIO_InitStructure);
-
- /* Connect PG11 to ethernet module*/
- GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH);
-
- /* PC
- ETH_RMII_MDC: PC1
- ETH_RMII_RXD0: PC4
- ETH_RMII_RXD1: PC5
- */
-
- /* Configure PC1, PC4 and PC5*/
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOC, &GPIO_InitStructure);
-
- /* Connect PC1, PC4 and PC5 to ethernet module*/
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
- GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
-
- /* PG
- ETH_RMII_TXD0: PG13
- ETH_RMII_TXD1: PG14
- */
-
- /* Configure PG13 and PG14*/
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14;
- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOG, &GPIO_InitStructure);
-
- /* Connect PG13 and PG14 to ethernet module*/
- GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH);
- GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH);
-
- /* Reset ETHERNET on AHB Bus */
- ETH_DeInit();
-
- /* Software reset */
- ETH_SoftwareReset();
-
- /* Wait for software reset */
- while(ETH_GetSoftwareResetStatus()==SET);
-
- /* ETHERNET Configuration ------------------------------------------------------*/
- /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
- ETH_StructInit(Ð_InitStructure);
-
- /* Fill ETH_InitStructure parametrs */
- /*------------------------ MAC -----------------------------------*/
- ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable ;
- ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
- ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
- ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
- ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable;
- ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
- ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
- ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
- ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
- ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;
- ETH_InitStructure.ETH_Speed = ETH_Speed_100M;
-
- unsigned int PhyAddr;
- union {
- uint32_t HI_LO;
- struct
- {
- uint16_t LO;
- uint16_t HI;
- };
- } PHYID;
- for(PhyAddr = 0; 32 > PhyAddr; PhyAddr++)
- {
- // datasheet for the ks8721bl ethernet controller (http://www.micrel.com/_PDF/Ethernet/datasheets/ks8721bl-sl.pdf)
- // page 20 --> PHY Identifier 1 and 2
- PHYID.HI = ETH_ReadPHYRegister(PhyAddr,2); // 0x0022
- PHYID.LO = ETH_ReadPHYRegister(PhyAddr,3); // 0x1619
- if ((0x00221619 == PHYID.HI_LO) || (0x0007C0F1 == PHYID.HI_LO))
- break;
- }
- /* Configure Ethernet */
- ETH_Init(Ð_InitStructure, PhyAddr);
-
- netdev_TxDscrInit();
- netdev_RxDscrInit();
- ETH_Start();
-}
-
-
-/*---------------------------------------------------------------------------*/
-void netdev_init_mac(void)
-{
- struct uip_eth_addr macAddress;
-
- /* set the default MAC address */
- macAddress.addr[0] = NETDEV_DEFAULT_MACADDR0;
- macAddress.addr[1] = NETDEV_DEFAULT_MACADDR1;
- macAddress.addr[2] = NETDEV_DEFAULT_MACADDR2;
- macAddress.addr[3] = NETDEV_DEFAULT_MACADDR3;
- macAddress.addr[4] = NETDEV_DEFAULT_MACADDR4;
- macAddress.addr[5] = NETDEV_DEFAULT_MACADDR5;
- uip_setethaddr(macAddress);
-}
-
-
-/*---------------------------------------------------------------------------*/
-unsigned int netdev_read(void)
-{
- uint32_t size;
- /*check for validity*/
- if(0 == EnetDmaRx.Rx.RxDesc0.OWN)
- {
- /*Get the size of the packet*/
- size = EnetDmaRx.Rx.RxDesc0.FL; // CRC
- memcpy(uip_buf, RxBuff, size); //string.h library*/
- }
- else
- {
- return 0;
- }
- /* Give the buffer back to ENET */
- EnetDmaRx.Rx.RxDesc0.OWN = 1;
- /* Start the receive operation */
- ETH->DMARPDR = 1;
- /* Return no error */
- return size;
-}
-
-
-/*---------------------------------------------------------------------------*/
-void netdev_send(void)
-{
- while(EnetDmaTx.Tx.TxDesc0.OWN);
-
- /* Copy the application buffer to the driver buffer
- Using this MEMCOPY_L2L_BY4 makes the copy routine faster
- than memcpy */
- memcpy(TxBuff, uip_buf, uip_len);
-
- /* Assign ENET address to Temp Tx Array */
- EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff;
-
- /* Setting the Frame Length*/
- EnetDmaTx.Tx.TxDesc0.Data = 0;
- EnetDmaTx.Tx.TxDesc0.TCH = 1;
- EnetDmaTx.Tx.TxDesc0.LSEG = 1;
- EnetDmaTx.Tx.TxDesc0.FS = 1;
- EnetDmaTx.Tx.TxDesc0.DC = 0;
- EnetDmaTx.Tx.TxDesc0.DP = 0;
-
- EnetDmaTx.Tx.TxDesc1.Data = 0;
- EnetDmaTx.Tx.TxDesc1.TBS1 = (uip_len&0xFFF);
-
- /* Start the ENET by setting the VALID bit in dmaPackStatus of current descr*/
- EnetDmaTx.Tx.TxDesc0.OWN = 1;
-
- /* Start the transmit operation */
- ETH->DMATPDR = 1;
-}
-
-
-/*---------------------------------------------------------------------------*/
-static void netdev_RxDscrInit(void)
-{
- /* Initialization */
- /* Assign temp Rx array to the ENET buffer */
- EnetDmaRx.Rx.pBuffer = (uint32_t *)RxBuff;
-
- /* Initialize RX ENET Status and control */
- EnetDmaRx.Rx.RxDesc0.Data = 0;
-
- /* Initialize the next descriptor- In our case its single descriptor */
- EnetDmaRx.Rx.pEnetDmaNextDesc = &EnetDmaRx;
-
- EnetDmaRx.Rx.RxDesc1.Data = 0;
- EnetDmaRx.Rx.RxDesc1.RER = 0; // end of ring
- EnetDmaRx.Rx.RxDesc1.RCH = 1; // end of ring
-
- /* Set the max packet size */
- EnetDmaRx.Rx.RxDesc1.RBS1 = UIP_CONF_BUFFER_SIZE;
-
- /* Setting the VALID bit */
- EnetDmaRx.Rx.RxDesc0.OWN = 1;
- /* Setting the RX NEXT Descriptor Register inside the ENET */
- ETH->DMARDLAR = (uint32_t)&EnetDmaRx;
-}
-
-
-/*---------------------------------------------------------------------------*/
-static void netdev_TxDscrInit(void)
-{
- /* ENET Start Address */
- EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff;
-
- /* Next Descriptor Address */
- EnetDmaTx.Tx.pEnetDmaNextDesc = &EnetDmaTx;
-
- /* Initialize ENET status and control */
- EnetDmaTx.Tx.TxDesc0.TCH = 1;
- EnetDmaTx.Tx.TxDesc0.Data = 0;
- EnetDmaTx.Tx.TxDesc1.Data = 0;
- /* Tx next set to Tx descriptor base */
- ETH->DMATDLAR = (uint32_t)&EnetDmaTx;
-
-}
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/netdev.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/netdev.h
deleted file mode 100644
index 4ea59ce5..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/netdev.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2001, Adam Dunkels.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Adam Dunkels.
- * 4. The name of the author may not be used to endorse or promote
- * products derived from this software without specific prior
- * written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * This file is part of the uIP TCP/IP stack.
- *
- * $Id: netdev.h,v 1.1 2002/01/10 06:22:56 adam Exp $
- *
- */
-
-#ifndef __NETDEV_H__
-#define __NETDEV_H__
-
-void netdev_init(void);
-void netdev_init_mac(void);
-unsigned int netdev_read(void);
-void netdev_send(void);
-
-#endif /* __NETDEV_H__ */
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/uip-conf.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/uip-conf.h
deleted file mode 100644
index fd9ba0dd..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/lib/uip/uip-conf.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/**
- * \addtogroup uipopt
- * @{
- */
-
-/**
- * \name Project-specific configuration options
- * @{
- *
- * uIP has a number of configuration options that can be overridden
- * for each project. These are kept in a project-specific uip-conf.h
- * file and all configuration names have the prefix UIP_CONF.
- */
-
-/*
- * Copyright (c) 2006, Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Institute nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * This file is part of the uIP TCP/IP stack
- *
- * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $
- */
-
-/**
- * \file
- * An example uIP configuration file
- * \author
- * Adam Dunkels
- */
-
-#ifndef __UIP_CONF_H__
-#define __UIP_CONF_H__
-
-
-/**
- * 8 bit datatype
- *
- * This typedef defines the 8-bit type used throughout uIP.
- *
- * \hideinitializer
- */
-typedef unsigned char u8_t;
-
-/**
- * 16 bit datatype
- *
- * This typedef defines the 16-bit type used throughout uIP.
- *
- * \hideinitializer
- */
-typedef unsigned short u16_t;
-
-/**
- * Statistics datatype
- *
- * This typedef defines the dataype used for keeping statistics in
- * uIP.
- *
- * \hideinitializer
- */
-typedef unsigned short uip_stats_t;
-
-/**
- * Maximum number of TCP connections.
- *
- * \hideinitializer
- */
-#define UIP_CONF_MAX_CONNECTIONS 1
-
-/**
- * Maximum number of listening TCP ports.
- *
- * \hideinitializer
- */
-#define UIP_CONF_MAX_LISTENPORTS 1
-
-/**
- * uIP buffer size.
- *
- * \hideinitializer
- */
-#define UIP_CONF_BUFFER_SIZE 1600
-
-/**
- * CPU byte order.
- *
- * \hideinitializer
- */
-#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN
-
-/**
- * Logging on or off
- *
- * \hideinitializer
- */
-#define UIP_CONF_LOGGING 0
-
-/**
- * UDP support on or off
- *
- * \hideinitializer
- */
-#define UIP_CONF_UDP 0
-
-/**
- * UDP checksums on or off
- *
- * \hideinitializer
- */
-#define UIP_CONF_UDP_CHECKSUMS 1
-
-/**
- * uIP statistics on or off
- *
- * \hideinitializer
- */
-#define UIP_CONF_STATISTICS 0
-
-/* Here we include the header file for the application(s) we use in
- our project. */
-#include "boot.h"
-#include "net.h"
-
-#endif /* __UIP_CONF_H__ */
-
-/** @} */
-/** @} */
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/main.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/main.c
deleted file mode 100644
index a60b62c2..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/main.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARMCM4_STM32F4_Olimex_STM32E407_Crossworks\Prog\main.c
-* \brief Demo program application source file.
-* \ingroup Prog_ARMCM4_STM32F4_Olimex_STM32E407_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-static void Init(void);
-
-
-/************************************************************************************//**
-** \brief This is the entry point for the bootloader application and is called
-** by the reset interrupt vector after the C-startup routines executed.
-** \return none.
-**
-****************************************************************************************/
-void main(void)
-{
- /* initialize the microcontroller */
- Init();
- /* initialize the network application */
- NetInit();
- /* initialize the bootloader interface */
- BootComInit();
-
- /* start the infinite program loop */
- while (1)
- {
- /* toggle LED with a fixed frequency */
- LedToggle();
- /* run the network task */
- NetTask();
- /* check for bootloader activation request */
- BootComCheckActivationRequest();
- }
-} /*** end of main ***/
-
-
-/************************************************************************************//**
-** \brief Initializes the microcontroller.
-** \return none.
-**
-****************************************************************************************/
-static void Init(void)
-{
- /* initialize the system and its clocks */
- SystemInit();
- /* init the led driver */
- LedInit();
- /* init the timer driver */
- TimerInit();
-} /*** end of Init ***/
-
-
-/*********************************** end of main.c *************************************/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/memory.x b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/memory.x
deleted file mode 100644
index 63d40407..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/memory.x
+++ /dev/null
@@ -1,332 +0,0 @@
-MEMORY
-{
- UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0
- FLASH (rx) : ORIGIN = 0x0800C000, LENGTH = 0x00100000-0xC000
- DATA_SRAM (wx) : ORIGIN = 0x10000000, LENGTH = 0x00010000
- SYSTEM (wx) : ORIGIN = 0x1fff0000, LENGTH = 0x00007a10
- OPTION (wx) : ORIGIN = 0x1fffc000, LENGTH = 0x00000008
- RAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
- SRAM1 (wx) : ORIGIN = 0x20000000, LENGTH = 0x0001c000
- SRAM2 (wx) : ORIGIN = 0x2001c000, LENGTH = 0x00004000
- APB1 (wx) : ORIGIN = 0x40000000, LENGTH = 0x00008000
- APB2 (wx) : ORIGIN = 0x40010000, LENGTH = 0x00004c00
- AHB1 (wx) : ORIGIN = 0x40020000, LENGTH = 0x00060000
- AHB2 (wx) : ORIGIN = 0x50000000, LENGTH = 0x00060c00
- AHB3 (wx) : ORIGIN = 0xa0000000, LENGTH = 0x00001000
- PPB (wx) : ORIGIN = 0xe0000000, LENGTH = 0x00100000
- BKPSRAM (wx) : ORIGIN = 0x40024000, LENGTH = 0x00001000
- PCCARD (wx) : ORIGIN = 0x90000000, LENGTH = 0x00000000
- NAND2 (wx) : ORIGIN = 0x80000000, LENGTH = 0x00000000
- NAND1 (wx) : ORIGIN = 0x70000000, LENGTH = 0x00000000
- NOR_PSRAM4 (wx) : ORIGIN = 0x6c000000, LENGTH = 0x00000000
- NOR_PSRAM3 (wx) : ORIGIN = 0x68000000, LENGTH = 0x00000000
- NOR_PSRAM2 (wx) : ORIGIN = 0x64000000, LENGTH = 0x00000000
- NOR_PSRAM1 (wx) : ORIGIN = 0x60000000, LENGTH = 0x00000000
- CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000
-}
-
-
-SECTIONS
-{
- __FLASH_segment_start__ = 0x0800C000;
- __FLASH_segment_end__ = 0x08100000;
- __DATA_SRAM_segment_start__ = 0x10000000;
- __DATA_SRAM_segment_end__ = 0x10010000;
- __SYSTEM_segment_start__ = 0x1fff0000;
- __SYSTEM_segment_end__ = 0x1fff7a10;
- __OPTION_segment_start__ = 0x1fffc000;
- __OPTION_segment_end__ = 0x1fffc008;
- __RAM_segment_start__ = 0x20000000;
- __RAM_segment_end__ = 0x20020000;
- __SRAM1_segment_start__ = 0x20000000;
- __SRAM1_segment_end__ = 0x2001c000;
- __SRAM2_segment_start__ = 0x2001c000;
- __SRAM2_segment_end__ = 0x20020000;
- __APB1_segment_start__ = 0x40000000;
- __APB1_segment_end__ = 0x40008000;
- __APB2_segment_start__ = 0x40010000;
- __APB2_segment_end__ = 0x40014c00;
- __AHB1_segment_start__ = 0x40020000;
- __AHB1_segment_end__ = 0x40080000;
- __AHB2_segment_start__ = 0x50000000;
- __AHB2_segment_end__ = 0x50060c00;
- __AHB3_segment_start__ = 0xa0000000;
- __AHB3_segment_end__ = 0xa0001000;
- __PPB_segment_start__ = 0xe0000000;
- __PPB_segment_end__ = 0xe0100000;
- __BKPSRAM_segment_start__ = 0x40024000;
- __BKPSRAM_segment_end__ = 0x40025000;
- __PCCARD_segment_start__ = 0x90000000;
- __PCCARD_segment_end__ = 0x90000000;
- __NAND2_segment_start__ = 0x80000000;
- __NAND2_segment_end__ = 0x80000000;
- __NAND1_segment_start__ = 0x70000000;
- __NAND1_segment_end__ = 0x70000000;
- __NOR_PSRAM4_segment_start__ = 0x6c000000;
- __NOR_PSRAM4_segment_end__ = 0x6c000000;
- __NOR_PSRAM3_segment_start__ = 0x68000000;
- __NOR_PSRAM3_segment_end__ = 0x68000000;
- __NOR_PSRAM2_segment_start__ = 0x64000000;
- __NOR_PSRAM2_segment_end__ = 0x64000000;
- __NOR_PSRAM1_segment_start__ = 0x60000000;
- __NOR_PSRAM1_segment_end__ = 0x60000000;
- __CM3_System_Control_Space_segment_start__ = 0xe000e000;
- __CM3_System_Control_Space_segment_end__ = 0xe000f000;
-
- __STACKSIZE__ = 2048;
- __STACKSIZE_PROCESS__ = 0;
- __STACKSIZE_IRQ__ = 0;
- __STACKSIZE_FIQ__ = 0;
- __STACKSIZE_SVC__ = 0;
- __STACKSIZE_ABT__ = 0;
- __STACKSIZE_UND__ = 0;
- __HEAPSIZE__ = 2048;
-
- __vectors_ram_load_start__ = ALIGN(__RAM_segment_start__ , 256);
- .vectors_ram ALIGN(__RAM_segment_start__ , 256) (NOLOAD) : AT(ALIGN(__RAM_segment_start__ , 256))
- {
- __vectors_ram_start__ = .;
- *(.vectors_ram .vectors_ram.*)
- }
- __vectors_ram_end__ = __vectors_ram_start__ + SIZEOF(.vectors_ram);
-
- __vectors_ram_load_end__ = __vectors_ram_end__;
-
- . = ASSERT(__vectors_ram_end__ >= __RAM_segment_start__ && __vectors_ram_end__ <= __RAM_segment_end__ , "error: .vectors_ram is too large to fit in RAM memory segment");
-
- __vectors_load_start__ = ALIGN(__FLASH_segment_start__ , 256);
- .vectors ALIGN(__FLASH_segment_start__ , 256) : AT(ALIGN(__FLASH_segment_start__ , 256))
- {
- __vectors_start__ = .;
- *(.vectors .vectors.*)
- }
- __vectors_end__ = __vectors_start__ + SIZEOF(.vectors);
-
- __vectors_load_end__ = __vectors_end__;
-
- . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= __FLASH_segment_end__ , "error: .vectors is too large to fit in FLASH memory segment");
-
- __init_load_start__ = ALIGN(__vectors_end__ , 4);
- .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4))
- {
- __init_start__ = .;
- *(.init .init.*)
- }
- __init_end__ = __init_start__ + SIZEOF(.init);
-
- __init_load_end__ = __init_end__;
-
- . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= __FLASH_segment_end__ , "error: .init is too large to fit in FLASH memory segment");
-
- __text_load_start__ = ALIGN(__init_end__ , 4);
- .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4))
- {
- __text_start__ = .;
- *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table .ARM.extab* .gnu.linkonce.armextab.*)
- }
- __text_end__ = __text_start__ + SIZEOF(.text);
-
- __text_load_end__ = __text_end__;
-
- . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= __FLASH_segment_end__ , "error: .text is too large to fit in FLASH memory segment");
-
- __dtors_load_start__ = ALIGN(__text_end__ , 4);
- .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4))
- {
- __dtors_start__ = .;
- KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) KEEP (*(.fini_array .fini_array.*))
- }
- __dtors_end__ = __dtors_start__ + SIZEOF(.dtors);
-
- __dtors_load_end__ = __dtors_end__;
-
- . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= __FLASH_segment_end__ , "error: .dtors is too large to fit in FLASH memory segment");
-
- __ctors_load_start__ = ALIGN(__dtors_end__ , 4);
- .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
- {
- __ctors_start__ = .;
- KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) KEEP (*(.init_array .init_array.*))
- }
- __ctors_end__ = __ctors_start__ + SIZEOF(.ctors);
-
- __ctors_load_end__ = __ctors_end__;
-
- . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= __FLASH_segment_end__ , "error: .ctors is too large to fit in FLASH memory segment");
-
- __rodata_load_start__ = ALIGN(__ctors_end__ , 4);
- .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
- {
- __rodata_start__ = .;
- *(.rodata .rodata.* .gnu.linkonce.r.*)
- }
- __rodata_end__ = __rodata_start__ + SIZEOF(.rodata);
-
- __rodata_load_end__ = __rodata_end__;
-
- . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= __FLASH_segment_end__ , "error: .rodata is too large to fit in FLASH memory segment");
-
- __ARM.exidx_load_start__ = ALIGN(__rodata_end__ , 4);
- .ARM.exidx ALIGN(__rodata_end__ , 4) : AT(ALIGN(__rodata_end__ , 4))
- {
- __ARM.exidx_start__ = .;
- __exidx_start = __ARM.exidx_start__;
- *(.ARM.exidx .ARM.exidx.*)
- }
- __ARM.exidx_end__ = __ARM.exidx_start__ + SIZEOF(.ARM.exidx);
-
- __exidx_end = __ARM.exidx_end__;
- __ARM.exidx_load_end__ = __ARM.exidx_end__;
-
- . = ASSERT(__ARM.exidx_end__ >= __FLASH_segment_start__ && __ARM.exidx_end__ <= __FLASH_segment_end__ , "error: .ARM.exidx is too large to fit in FLASH memory segment");
-
- __fast_load_start__ = ALIGN(__ARM.exidx_end__ , 4);
- .fast ALIGN(__vectors_ram_end__ , 4) : AT(ALIGN(__ARM.exidx_end__ , 4))
- {
- __fast_start__ = .;
- *(.fast .fast.*)
- }
- __fast_end__ = __fast_start__ + SIZEOF(.fast);
-
- __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
-
- . = ASSERT(__fast_load_end__ >= __FLASH_segment_start__ && __fast_load_end__ <= __FLASH_segment_end__ , "error: .fast is too large to fit in FLASH memory segment");
-
- .fast_run ALIGN(__vectors_ram_end__ , 4) (NOLOAD) :
- {
- __fast_run_start__ = .;
- . = MAX(__fast_run_start__ + SIZEOF(.fast), .);
- }
- __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run);
-
- __fast_run_load_end__ = __fast_run_end__;
-
- . = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= __RAM_segment_end__ , "error: .fast_run is too large to fit in RAM memory segment");
-
- __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4);
- .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4))
- {
- __data_start__ = .;
- *(.data .data.* .gnu.linkonce.d.*)
- }
- __data_end__ = __data_start__ + SIZEOF(.data);
-
- __data_load_end__ = __data_load_start__ + SIZEOF(.data);
-
- . = ASSERT(__data_load_end__ >= __FLASH_segment_start__ && __data_load_end__ <= __FLASH_segment_end__ , "error: .data is too large to fit in FLASH memory segment");
-
- .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) :
- {
- __data_run_start__ = .;
- . = MAX(__data_run_start__ + SIZEOF(.data), .);
- }
- __data_run_end__ = __data_run_start__ + SIZEOF(.data_run);
-
- __data_run_load_end__ = __data_run_end__;
-
- . = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= __RAM_segment_end__ , "error: .data_run is too large to fit in RAM memory segment");
-
- __bss_load_start__ = ALIGN(__data_run_end__ , 4);
- .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
- {
- __bss_start__ = .;
- *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
- }
- __bss_end__ = __bss_start__ + SIZEOF(.bss);
-
- __bss_load_end__ = __bss_end__;
-
- . = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= __RAM_segment_end__ , "error: .bss is too large to fit in RAM memory segment");
-
- __non_init_load_start__ = ALIGN(__bss_end__ , 4);
- .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
- {
- __non_init_start__ = .;
- *(.non_init .non_init.*)
- }
- __non_init_end__ = __non_init_start__ + SIZEOF(.non_init);
-
- __non_init_load_end__ = __non_init_end__;
-
- . = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= __RAM_segment_end__ , "error: .non_init is too large to fit in RAM memory segment");
-
- __heap_load_start__ = ALIGN(__non_init_end__ , 4);
- .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
- {
- __heap_start__ = .;
- *(.heap .heap.*)
- . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4);
- }
- __heap_end__ = __heap_start__ + SIZEOF(.heap);
-
- __heap_load_end__ = __heap_end__;
-
- . = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= __RAM_segment_end__ , "error: .heap is too large to fit in RAM memory segment");
-
- __stack_load_start__ = ALIGN(__heap_end__ , 4);
- .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4))
- {
- __stack_start__ = .;
- *(.stack .stack.*)
- . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4);
- }
- __stack_end__ = __stack_start__ + SIZEOF(.stack);
-
- __stack_load_end__ = __stack_end__;
-
- . = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= __RAM_segment_end__ , "error: .stack is too large to fit in RAM memory segment");
-
- __stack_process_load_start__ = ALIGN(__stack_end__ , 4);
- .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4))
- {
- __stack_process_start__ = .;
- *(.stack_process .stack_process.*)
- . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4);
- }
- __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process);
-
- __stack_process_load_end__ = __stack_process_end__;
-
- . = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= __RAM_segment_end__ , "error: .stack_process is too large to fit in RAM memory segment");
-
- __tbss_load_start__ = ALIGN(__stack_process_end__ , 4);
- .tbss ALIGN(__stack_process_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_process_end__ , 4))
- {
- __tbss_start__ = .;
- *(.tbss .tbss.*)
- }
- __tbss_end__ = __tbss_start__ + SIZEOF(.tbss);
-
- __tbss_load_end__ = __tbss_end__;
-
- . = ASSERT(__tbss_end__ >= __RAM_segment_start__ && __tbss_end__ <= __RAM_segment_end__ , "error: .tbss is too large to fit in RAM memory segment");
-
- __tdata_load_start__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4);
- .tdata ALIGN(__tbss_end__ , 4) : AT(ALIGN(__data_load_start__ + SIZEOF(.data) , 4))
- {
- __tdata_start__ = .;
- *(.tdata .tdata.*)
- }
- __tdata_end__ = __tdata_start__ + SIZEOF(.tdata);
-
- __tdata_load_end__ = __tdata_load_start__ + SIZEOF(.tdata);
-
- __FLASH_segment_used_end__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4) + SIZEOF(.tdata);
-
- . = ASSERT(__tdata_load_end__ >= __FLASH_segment_start__ && __tdata_load_end__ <= __FLASH_segment_end__ , "error: .tdata is too large to fit in FLASH memory segment");
-
- .tdata_run ALIGN(__tbss_end__ , 4) (NOLOAD) :
- {
- __tdata_run_start__ = .;
- . = MAX(__tdata_run_start__ + SIZEOF(.tdata), .);
- }
- __tdata_run_end__ = __tdata_run_start__ + SIZEOF(.tdata_run);
-
- __tdata_run_load_end__ = __tdata_run_end__;
-
- __RAM_segment_used_end__ = ALIGN(__tbss_end__ , 4) + SIZEOF(.tdata_run);
-
- . = ASSERT(__tdata_run_end__ >= __RAM_segment_start__ && __tdata_run_end__ <= __RAM_segment_end__ , "error: .tdata_run is too large to fit in RAM memory segment");
-
-}
-
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/net.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/net.c
deleted file mode 100644
index 6c8f8940..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/net.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARMCM4_STM32F4_Olimex_STM32E407_Crossworks\Prog\net.c
-* \brief Network application for the uIP TCP/IP stack.
-* \ingroup Prog_ARMCM4_STM32F4_Olimex_STM32E407_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2014 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-#include "netdev.h"
-#include "uip.h"
-#include "uip_arp.h"
-
-
-/****************************************************************************************
-* Macro definitions
-****************************************************************************************/
-/** \brief Delta time for the uIP periodic timer. */
-#define NET_UIP_PERIODIC_TIMER_MS (500)
-/** \brief Delta time for the uIP ARP timer. */
-#define NET_UIP_ARP_TIMER_MS (10000)
-/** \brief Macro for accessing the Ethernet header information in the buffer */
-#define NET_UIP_HEADER_BUF ((struct uip_eth_hdr *)&uip_buf[0])
-
-
-/****************************************************************************************
-* Local data declarations
-****************************************************************************************/
-/** \brief Holds the time out value of the uIP periodic timer. */
-static unsigned long periodicTimerTimeOut;
-/** \brief Holds the time out value of the uIP ARP timer. */
-static unsigned long ARPTimerTimeOut;
-
-
-/************************************************************************************//**
-** \brief Initializes the TCP/IP network communication interface.
-** \return none.
-**
-****************************************************************************************/
-void NetInit(void)
-{
- uip_ipaddr_t ipaddr;
-
- /* initialize the network device */
- netdev_init();
- /* initialize the timer variables */
- periodicTimerTimeOut = TimerGet() + NET_UIP_PERIODIC_TIMER_MS;
- ARPTimerTimeOut = TimerGet() + NET_UIP_ARP_TIMER_MS;
- /* initialize the uIP TCP/IP stack. */
- uip_init();
- /* set the IP address */
- uip_ipaddr(ipaddr, BOOT_COM_NET_IPADDR0, BOOT_COM_NET_IPADDR1, BOOT_COM_NET_IPADDR2,
- BOOT_COM_NET_IPADDR3);
- uip_sethostaddr(ipaddr);
- /* set the network mask */
- uip_ipaddr(ipaddr, BOOT_COM_NET_NETMASK0, BOOT_COM_NET_NETMASK1, BOOT_COM_NET_NETMASK2,
- BOOT_COM_NET_NETMASK3);
- uip_setnetmask(ipaddr);
- /* set the gateway address */
- uip_ipaddr(ipaddr, BOOT_COM_NET_GATEWAY0, BOOT_COM_NET_GATEWAY1, BOOT_COM_NET_GATEWAY2,
- BOOT_COM_NET_GATEWAY3);
- uip_setdraddr(ipaddr);
- /* start listening on the configured port for XCP transfers on TCP/IP */
- uip_listen(HTONS(BOOT_COM_NET_PORT));
- /* initialize the MAC and set the MAC address */
- netdev_init_mac();
-} /*** end of NetInit ***/
-
-
-/************************************************************************************//**
-** \brief The uIP network application that detects the XCP connect command on the
-** port used by the bootloader. This indicates that the bootloader should
-** be activated.
-** \return none.
-**
-****************************************************************************************/
-void NetApp(void)
-{
- unsigned char *newDataPtr;
-
- if (uip_connected())
- {
- return;
- }
-
- if (uip_newdata())
- {
- /* a new XCP command was received. check if this is the connect command and in this
- * case activate the bootloader. with XCP on TCP/IP the first 4 bytes contain a
- * counter value in which we are not really interested.
- */
- newDataPtr = uip_appdata;
- newDataPtr += 4;
- /* check if this was an XCP CONNECT command */
- if ((newDataPtr[0] == 0xff) && (newDataPtr[1] == 0x00))
- {
- /* connection request received so start the bootloader */
- BootActivate();
- }
- }
-} /*** end of NetApp ***/
-
-
-/************************************************************************************//**
-** \brief Runs the TCP/IP server task.
-** \return none.
-**
-****************************************************************************************/
-void NetTask(void)
-{
- unsigned long connection;
- unsigned long packetLen;
-
- /* check for an RX packet and read it. */
- packetLen = netdev_read();
- if(packetLen > 0)
- {
- /* set uip_len for uIP stack usage */
- uip_len = (unsigned short)packetLen;
-
- /* process incoming IP packets here. */
- if(NET_UIP_HEADER_BUF->type == htons(UIP_ETHTYPE_IP))
- {
- uip_arp_ipin();
- uip_input();
- /* if the above function invocation resulted in data that
- * should be sent out on the network, the global variable
- * uip_len is set to a value > 0.
- */
- if(uip_len > 0)
- {
- uip_arp_out();
- netdev_send();
- uip_len = 0;
- }
- }
- /* process incoming ARP packets here. */
- else if(NET_UIP_HEADER_BUF->type == htons(UIP_ETHTYPE_ARP))
- {
- uip_arp_arpin();
-
- /* if the above function invocation resulted in data that
- * should be sent out on the network, the global variable
- * uip_len is set to a value > 0.
- */
- if(uip_len > 0)
- {
- netdev_send();
- uip_len = 0;
- }
- }
- }
-
- /* process TCP/IP Periodic Timer here. */
- if (TimerGet() >= periodicTimerTimeOut)
- {
- periodicTimerTimeOut += NET_UIP_PERIODIC_TIMER_MS;
- for (connection = 0; connection < UIP_CONNS; connection++)
- {
- uip_periodic(connection);
- /* If the above function invocation resulted in data that
- * should be sent out on the network, the global variable
- * uip_len is set to a value > 0.
- */
- if(uip_len > 0)
- {
- uip_arp_out();
- netdev_send();
- uip_len = 0;
- }
- }
- }
-
- /* process ARP Timer here. */
- if (TimerGet() >= ARPTimerTimeOut)
- {
- ARPTimerTimeOut += NET_UIP_ARP_TIMER_MS;
- uip_arp_timer();
- }
-} /*** end of NetServerTask ***/
-
-
-/*********************************** end of net.c **************************************/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/net.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/net.h
deleted file mode 100644
index 5b9c3464..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/net.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARMCM4_STM32F4_Olimex_STM32E407_Crossworks\Prog\net.h
-* \brief Network application for the uIP TCP/IP stack.
-* \ingroup Prog_ARMCM4_STM32F4_Olimex_STM32E407_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2014 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-#ifndef NET_H
-#define NET_H
-
-/****************************************************************************************
-* Macro definitions
-****************************************************************************************/
-#ifndef UIP_APPCALL
-#define UIP_APPCALL NetApp
-#endif /* UIP_APPCALL */
-
-
-/****************************************************************************************
-* Type definitions
-****************************************************************************************/
-/** \brief Define the uip_tcp_appstate_t datatype. This is the state of our tcp/ip
- * application, and the memory required for this state is allocated together
- * with each TCP connection. One application state for each TCP connection.
- */
-typedef struct net_state
-{
- unsigned char unused;
-} uip_tcp_appstate_t;
-
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-void NetInit(void);
-void NetApp(void);
-void NetTask(void);
-
-
-#endif /* NET_H */
-/*********************************** end of net.h **************************************/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/prog.dox b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/prog.dox
deleted file mode 100644
index 90274be6..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/prog.dox
+++ /dev/null
@@ -1,7 +0,0 @@
-/**
-\defgroup Prog_ARMCM4_STM32F4_Olimex_STM32E407_Crossworks User Program
-\brief User Program.
-\ingroup ARMCM4_STM32F4_Olimex_STM32E407_Crossworks
-*/
-
-
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/timer.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/timer.c
deleted file mode 100644
index 5d81a232..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/timer.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARMCM4_STM32F4_Olimex_STM32E407_Crossworks\Prog\timer.c
-* \brief Timer driver source file.
-* \ingroup Prog_ARMCM4_STM32F4_Olimex_STM32E407_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* Local data declarations
-****************************************************************************************/
-/** \brief Local variable for storing the number of milliseconds that have elapsed since
- * startup.
- */
-static unsigned long millisecond_counter;
-
-
-/************************************************************************************//**
-** \brief Initializes the timer.
-** \return none.
-**
-****************************************************************************************/
-void TimerInit(void)
-{
- /* configure the SysTick timer for 1 ms period */
- SysTick_Config(SystemCoreClock / 1000);
- /* reset the millisecond counter */
- TimerSet(0);
-} /*** end of TimerInit ***/
-
-
-/************************************************************************************//**
-** \brief Stops and disables the timer.
-** \return none.
-**
-****************************************************************************************/
-void TimerDeinit(void)
-{
- SysTick->CTRL = 0;
-} /*** end of TimerDeinit ***/
-
-
-/************************************************************************************//**
-** \brief Sets the initial counter value of the millisecond timer.
-** \param timer_value initialize value of the millisecond timer.
-** \return none.
-**
-****************************************************************************************/
-void TimerSet(unsigned long timer_value)
-{
- /* set the millisecond counter */
- millisecond_counter = timer_value;
-} /*** end of TimerSet ***/
-
-
-/************************************************************************************//**
-** \brief Obtains the counter value of the millisecond timer.
-** \return Current value of the millisecond timer.
-**
-****************************************************************************************/
-unsigned long TimerGet(void)
-{
- /* read and return the millisecond counter value */
- return millisecond_counter;
-} /*** end of TimerGet ***/
-
-
-/************************************************************************************//**
-** \brief Interrupt service routine of the timer.
-** \return none.
-**
-****************************************************************************************/
-void TimerISRHandler(void)
-{
- /* increment the millisecond counter */
- millisecond_counter++;
-} /*** end of TimerISRHandler ***/
-
-
-/*********************************** end of timer.c ************************************/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/timer.h b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/timer.h
deleted file mode 100644
index 9a5bad92..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/timer.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARMCM4_STM32F4_Olimex_STM32E407_Crossworks\Prog\timer.h
-* \brief Timer driver header file.
-* \ingroup Prog_ARMCM4_STM32F4_Olimex_STM32E407_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-#ifndef TIMER_H
-#define TIMER_H
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-void TimerInit(void);
-void TimerDeinit(void);
-void TimerSet(unsigned long timer_value);
-unsigned long TimerGet(void);
-void TimerISRHandler(void);
-
-#endif /* TIMER_H */
-/*********************************** end of timer.h ************************************/
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/vectors.c b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/vectors.c
deleted file mode 100644
index a80209a5..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/Prog/vectors.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/************************************************************************************//**
-* \file Demo\ARMCM4_STM32F4_Olimex_STM32E407_Crossworks\Prog\vectors.c
-* \brief Demo program interrupt vectors source file.
-* \ingroup Prog_ARMCM4_STM32F4_Olimex_STM32E407_Crossworks
-* \internal
-*----------------------------------------------------------------------------------------
-* C O P Y R I G H T
-*----------------------------------------------------------------------------------------
-* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
-*
-*----------------------------------------------------------------------------------------
-* L I C E N S E
-*----------------------------------------------------------------------------------------
-* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as published by the Free
-* Software Foundation, either version 3 of the License, or (at your option) any later
-* version.
-*
-* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-* PURPOSE. See the GNU General Public License for more details.
-*
-* You have received a copy of the GNU General Public License along with OpenBLT. It
-* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
-*
-* \endinternal
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* External functions
-****************************************************************************************/
-extern void reset_handler(void); /* implemented in cstart.s */
-
-
-/****************************************************************************************
-* External data declarations
-****************************************************************************************/
-/** \brief Stack end address (memory.x) */
-extern unsigned long __stack_end__;
-
-
-/************************************************************************************//**
-** \brief Catch-all for unused interrrupt service routines.
-** \return none.
-**
-****************************************************************************************/
-void UnusedISR(void)
-{
- /* unexpected interrupt occured, so halt the system */
- while (1) { ; }
-} /*** end of UnusedISR ***/
-
-
-/****************************************************************************************
-* I N T E R R U P T V E C T O R T A B L E
-****************************************************************************************/
-/** \brief Structure type for vector table entries. */
-typedef union
-{
- void (*func)(void); /**< for ISR function pointers */
- unsigned long ptr; /**< for stack pointer entry */
-}tIsrFunc;
-
-/** \brief Interrupt vector table. */
-__attribute__ ((section(".vectors")))
-const tIsrFunc _vectors[] =
-{
- { .ptr = (unsigned long)&__stack_end__ }, /* the initial stack pointer */
- { reset_handler }, /* the reset handler */
- { UnusedISR }, /* NMI Handler */
- { UnusedISR }, /* Hard Fault Handler */
- { UnusedISR }, /* MPU Fault Handler */
- { UnusedISR }, /* Bus Fault Handler */
- { UnusedISR }, /* Usage Fault Handler */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* SVCall Handler */
- { UnusedISR }, /* Debug Monitor Handler */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* PendSV Handler */
- { TimerISRHandler }, /* SysTick Handler */
- { UnusedISR }, /* Window Watchdog */
- { UnusedISR }, /* PVD through EXTI Line detect */
- { UnusedISR }, /* Tamper */
- { UnusedISR }, /* RTC */
- { UnusedISR }, /* Flash */
- { UnusedISR }, /* RCC */
- { UnusedISR }, /* EXTI Line 0 */
- { UnusedISR }, /* EXTI Line 1 */
- { UnusedISR }, /* EXTI Line 2 */
- { UnusedISR }, /* EXTI Line 3 */
- { UnusedISR }, /* EXTI Line 4 */
- { UnusedISR }, /* DMA1 Channel 0 */
- { UnusedISR }, /* DMA1 Channel 1 */
- { UnusedISR }, /* DMA1 Channel 2 */
- { UnusedISR }, /* DMA1 Channel 3 */
- { UnusedISR }, /* DMA1 Channel 4 */
- { UnusedISR }, /* DMA1 Channel 5 */
- { UnusedISR }, /* DMA1 Channel 6 */
- { UnusedISR }, /* ADC1 and ADC2, ADC3s */
- { UnusedISR }, /* CAN1 TX */
- { UnusedISR }, /* CAN1 RX0 */
- { UnusedISR }, /* CAN1 RX1 */
- { UnusedISR }, /* CAN1 SCE */
- { UnusedISR }, /* EXTI Line 9..5 */
- { UnusedISR }, /* TIM1 Break and TIM9 */
- { UnusedISR }, /* TIM1 Update and TIM10 */
- { UnusedISR }, /* TIM1 Trigger/Comm. and TIM11 */
- { UnusedISR }, /* TIM1 Capture Compare */
- { UnusedISR }, /* TIM2 */
- { UnusedISR }, /* TIM3 */
- { UnusedISR }, /* TIM4 */
- { UnusedISR }, /* I2C1 Event */
- { UnusedISR }, /* I2C1 Error */
- { UnusedISR }, /* I2C2 Event */
- { UnusedISR }, /* I2C1 Error */
- { UnusedISR }, /* SPI1 */
- { UnusedISR }, /* SPI2 */
- { UnusedISR }, /* USART1 */
- { UnusedISR }, /* USART2 */
- { UnusedISR }, /* USART3 */
- { UnusedISR }, /* EXTI Line 15..10 */
- { UnusedISR }, /* RTC alarm through EXTI line */
- { UnusedISR }, /* USB OTG FS Wakeup */
- { UnusedISR }, /* TIM8 Break and TIM12 */
- { UnusedISR }, /* TIM8 Update and TIM13 */
- { UnusedISR }, /* TIM8 Trigger/Comm. and TIM14 */
- { UnusedISR }, /* TIM8 Capture Compare */
- { UnusedISR }, /* DMA1 Stream7 */
- { UnusedISR }, /* FSMC */
- { UnusedISR }, /* SDIO */
- { UnusedISR }, /* TIM5 */
- { UnusedISR }, /* SPI3 */
- { UnusedISR }, /* UART4 */
- { UnusedISR }, /* UART5 */
- { UnusedISR }, /* TIM6 and DAC1&2 underrun err. */
- { UnusedISR }, /* TIM7 */
- { UnusedISR }, /* DMA2 Stream 0 */
- { UnusedISR }, /* DMA2 Stream 1 */
- { UnusedISR }, /* DMA2 Stream 2 */
- { UnusedISR }, /* DMA2 Stream 3 */
- { UnusedISR }, /* DMA2 Stream 4 */
- { UnusedISR }, /* Ethernet */
- { UnusedISR }, /* Ethernet Wakeup */
- { UnusedISR }, /* CAN2 TX */
- { UnusedISR }, /* CAN2 RX0 */
- { UnusedISR }, /* CAN2 RX1 */
- { UnusedISR }, /* CAN2 SCE */
- { UnusedISR }, /* USB OTG FS */
- { UnusedISR }, /* DMA2 Stream 5 */
- { UnusedISR }, /* DMA2 Stream 6 */
- { UnusedISR }, /* DMA2 Stream 7 */
- { UnusedISR }, /* USART6 */
- { UnusedISR }, /* I2C3 event */
- { UnusedISR }, /* I2C3 error */
- { UnusedISR }, /* USB OTG HS End Point 1 Out */
- { UnusedISR }, /* USB OTG HS End Point 1 In */
- { UnusedISR }, /* USB OTG HS Wakeup through EXTI*/
- { UnusedISR }, /* USB OTG HS */
- { UnusedISR }, /* DCMI */
- { UnusedISR }, /* CRYP crypto */
- { UnusedISR }, /* Hash and Rng */
- { UnusedISR }, /* FPU */
- { (void*)0x55AA11EE }, /* Reserved for OpenBLT checksum */
-};
-
-
-/************************************ end of vectors.c *********************************/
-
-
diff --git a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/demo.dox b/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/demo.dox
deleted file mode 100644
index 0d17c065..00000000
--- a/Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_Crossworks/demo.dox
+++ /dev/null
@@ -1,8 +0,0 @@
-/**
-\defgroup ARMCM4_STM32F4_Olimex_STM32E407_Crossworks Demo for Olimex STM32-E407/Crossworks
-\brief Preconfigured programs for the Olimex STM32-E407 and the Crossworks IDE.
-\details Refer to http://feaser.com/openblt/doku.php?id=manual:demos
- for detailed getting started instructions.
-*/
-
-