-
- All
-STM32 devices definitions are commented by default. User has to select the
-appropriate device before starting else an error will be signaled on compile
-time.
-
Add new IRQs definitons inside the IRQn_Type enumeration for STM23 High-density Value line devices.
-
"bool" type removed.
-
-
STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:system_stm32f10x.h and system_stm32f10x.c
-
-
-
"system_stm32f10x.c" moved to to "STM32F10x_StdPeriph_Template" directory. This file is also moved to each example directory under "STM32F10x_StdPeriph_Examples".
-
-
SystemInit_ExtMemCtl() function: update to support High-density Value line devices.
-
Add "VECT_TAB_SRAM" inside "system_stm32f10x.c"
-to select if the user want to place the Vector Table in internal SRAM.
-An additional define is also to specify the Vector Table offset "VECT_TAB_OFFSET".
-
Update
-the stm32f10x.h file to support new Value line devices features: CEC
-peripheral, new General purpose timers TIM15, TIM16 and TIM17.
-
Peripherals Bits definitions updated to be in line with Value line devices available features.
-
-
HSE_Value,
-HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE,
-HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy
-purposes.
-
-
-
STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:system_stm32f10x.h and system_stm32f10x.c
-
-
-
SystemFrequency variable name changed to SystemCoreClock
-
-
Default
- SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.
-
-
All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.
-
-
Additional function void SystemCoreClockUpdate (void) is provided.
-
Add new
-startup files for STM32 Low-density Value line devices:
- startup_stm32f10x_ld_vl.s
-
Add new startup
-files for STM32 Medium-density Value line devices:
- startup_stm32f10x_md_vl.s
-
SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.
-To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file
-
-
GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.
-
-
-
-
-
-
-
-
License
-
The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.
-
THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS.
-
-
-
-
For
-complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers
-visit www.st.com/STM32
-
-
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Boot/lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Boot/lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h
deleted file mode 100644
index af0c7c9a..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Boot/lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h
+++ /dev/null
@@ -1,8336 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x.h
- * @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
- * This file contains all the peripheral register's definitions, bits
- * definitions and memory mapping for STM32F10x Connectivity line,
- * High density, High density value line, Medium density,
- * Medium density Value line, Low density, Low density Value line
- * and XL-density devices.
- *
- * The file is the unique include file that the application programmer
- * is using in the C source code, usually in main.c. This file contains:
- * - Configuration section that allows to select:
- * - The device used in the target application
- * - To use or not the peripheral’s drivers in application code(i.e.
- * code will be based on direct access to peripheral’s registers
- * rather than drivers API), this option is controlled by
- * "#define USE_STDPERIPH_DRIVER"
- * - To change few application-specific parameters such as the HSE
- * crystal frequency
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral’s registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- *
- The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
- the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
- 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
- communication channels are used by CMSIS to output the following information:
-
-
-
ITM Channel 0: used for printf-style output via the debug interface.
-
ITM Channel 31: is reserved for RTOS kernel awareness debugging.
-
-
-
Debug IN / OUT functions
-
CMSIS provides following debug functions:
-
-
ITM_SendChar (uses ITM channel 0)
-
ITM_ReceiveChar (uses global variable)
-
ITM_CheckChar (uses global variable)
-
-
-
ITM_SendChar
-
- ITM_SendChar is used to transmit a character over ITM channel 0 from
- the microcontroller system to the debug system.
- Only a 8 bit value is transmitted.
-
- ITM communication channel is only capable for OUT direction. For IN direction
- a globel variable is used. A simple mechansim detects if a character is received.
- The project to test need to be build with debug information.
-
-
-
- The globale variable ITM_RxBuffer is used to transmit a 8 bit value from debug system
- to microcontroller system. ITM_RxBuffer is 32 bit wide to enshure a proper handshake.
-
-
-extern volatile int ITM_RxBuffer; /* variable to receive characters */
-
-
- A dedicated bit pattern is used to determin if ITM_RxBuffer is empty
- or contains a valid value.
-
-
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
-
-
- ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking.
- It returns the received character or '-1' if no character was available.
-
-
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-
ITM_CheckChar
-
- ITM_CheckChar is used to check if a character is received.
-
-
-static __INLINE int ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-
-
ITM Debug Support in uVision
-
- uVision uses in a debug session the Debug (printf) Viewer window to
- display the debug data.
-
-
Direction microcontroller system -> uVision:
-
-
- Characters received via ITM communication channel 0 are written in a printf style
- to Debug (printf) Viewer window.
-
-
-
-
Direction uVision -> microcontroller system:
-
-
Check if ITM_RxBuffer variable is available (only performed once).
-
Read character from Debug (printf) Viewer window.
-
If ITM_RxBuffer empty write character to ITM_RxBuffer.
-
-
-
Note
-
-
Current solution does not use a buffer machanism for trasmitting the characters.
-
-
-
-
RTX Kernel awareness in uVision
-
- uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
- No format overhead is necessary.
- uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
- to ITM communication channel 31.
-
-
-
Following RTX events are traced:
-
-
Task Create / Delete event
-
-
32 bit access. Task start address is transmitted
-
16 bit access. Task ID and Create/Delete flag are transmitted
- High byte holds Create/Delete flag, Low byte holds TASK ID.
-
-
-
-
Task switch event
-
-
8 bit access. Task ID of current task is transmitted
-
-
-
-
-
Note
-
-
Other RTOS information could be retrieved via memory read access in a polling mode manner.
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Boot/lib/CMSIS/CMSIS_changes.htm b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Boot/lib/CMSIS/CMSIS_changes.htm
deleted file mode 100644
index 162ffcc9..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Boot/lib/CMSIS/CMSIS_changes.htm
+++ /dev/null
@@ -1,320 +0,0 @@
-
-
-
-CMSIS Changes
-
-
-
-
-
-
-
-
-
Changes to CMSIS version V1.20
-
-
-
-
1. Removed CMSIS Middelware packages
-
- CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
-
-
-
2. SystemFrequency renamed to SystemCoreClock
-
- The variable name SystemCoreClock is more precise than SystemFrequency
- because the variable holds the clock value at which the core is running.
-
-
-
3. Changed startup concept
-
- The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
- from main) has the weakness that it does not work for controllers which need a already
- configuerd clock system to configure the external memory controller.
-
-
-
Changed startup concept
-
-
- SystemInit() is called from startup file before premain.
-
-
- SystemInit() configures the clock system and also configures
- an existing external memory controller.
-
-
- SystemInit() must not use global variables.
-
-
- SystemCoreClock is initialized with a correct predefined value.
-
-
- Additional function void SystemCoreClockUpdate (void) is provided.
- SystemCoreClockUpdate() updates the variable SystemCoreClock
- and must be called whenever the core clock is changed.
- SystemCoreClockUpdate() evaluates the clock register settings and calculates
- the current core clock.
-
-
-
-
-
4. Advanced Debug Functions
-
- ITM communication channel is only capable for OUT direction. To allow also communication for
- IN direction a simple concept is provided.
-
-
-
- Global variable volatile int ITM_RxBuffer used for IN data.
-
-
- Function int ITM_CheckChar (void) checks if a new character is available.
-
-
- Function int ITM_ReceiveChar (void) retrieves the new character.
-
-
-
-
- For detailed explanation see file CMSIS debug support.htm.
-
-
-
-
5. Core Register Bit Definitions
-
- Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
- defines correspond with the Cortex-M Technical Reference Manual.
-
- The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges
- that are faced when software components are deployed to physical microcontroller devices based on a
- Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M
- processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation
- with various silicon and software vendors and provides a common approach to interface to peripherals,
- real-time operating systems, and middleware components.
-
-
-
ARM provides as part of the CMSIS the following software layers that are
-available for various compiler implementations:
-
-
Core Peripheral Access Layer: contains name definitions,
- address definitions and helper functions to
- access core registers and peripherals. It defines also a device
- independent interface for RTOS Kernels that includes debug channel
- definitions.
-
-
-
These software layers are expanded by Silicon partners with:
-
-
Device Peripheral Access Layer: provides definitions
- for all device peripherals
-
Access Functions for Peripherals (optional): provides
- additional helper functions for peripherals
-
-
-
CMSIS defines for a Cortex-M Microcontroller System:
-
-
A common way to access peripheral registers
- and a common way to define exception vectors.
-
The register names of the Core
- Peripherals andthe names of the Core
- Exception Vectors.
-
An device independent interface for RTOS Kernels including a debug
- channel.
-
-
-
- By using CMSIS compliant software components, the user can easier re-use template code.
- CMSIS is intended to enable the combination of software components from multiple middleware vendors.
-
-
-
Coding Rules and Conventions
-
-
- The following section describes the coding rules and conventions used in the CMSIS
- implementation. It contains also information about data types and version number information.
-
-
-
Essentials
-
-
The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations,
- there are disable and enable sequences for PC-LINT inserted.
-
ANSI standard data types defined in the ANSI C header file
- <stdint.h> are used.
-
#define constants that include expressions must be enclosed by
- parenthesis.
-
Variables and parameters have a complete data type.
-
All functions in the Core Peripheral Access Layer are
- re-entrant.
-
The Core Peripheral Access Layer has no blocking code
- (which means that wait/query loops are done at other software layers).
-
For each exception/interrupt there is definition for:
-
-
an exception/interrupt handler with the postfix _Handler
- (for exceptions) or _IRQHandler (for interrupts).
-
a default exception/interrupt handler (weak definition) that contains an endless loop.
-
a #define of the interrupt number with the postfix _IRQn.
-
-
-
-
Recommendations
-
-
The CMSIS recommends the following conventions for identifiers.
-
-
CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
-
CamelCase names to identify peripherals access functions and interrupts.
-
PERIPHERAL_ prefix to identify functions that belong to specify peripherals.
-
Doxygen comments for all functions are included as described under Function Comments below.
-
-
-Comments
-
-
-
Comments use the ANSI C90 style (/* comment */) or C++ style
- (// comment). It is assumed that the programming tools support today
- consistently the C++ comment style.
-
Function Comments provide for each function the following information:
-
-
one-line brief function overview.
-
detailed parameter explanation.
-
detailed information about return values.
-
detailed description of the actual function.
-
-
Doxygen Example:
-
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- * @param IRQn interrupt number that specifies the interrupt
- * @return none.
- * Enable the specified interrupt in the NVIC Interrupt Controller.
- * Other settings of the interrupt such as priority are not affected.
- */
-
-
-
-
Data Types and IO Type Qualifiers
-
-
- The Cortex-M HAL uses the standard types from the standard ANSI C header file
- <stdint.h>. IO Type Qualifiers are used to specify the access
- to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of
- debug information of peripheral registers.
-
-
-
-
-
-
IO Type Qualifier
-
#define
-
Description
-
-
-
__I
-
volatile const
-
Read access only
-
-
-
__O
-
volatile
-
Write access only
-
-
-
__IO
-
volatile
-
Read and write access
-
-
-
-
-
CMSIS Version Number
-
- File core_cm3.h contains the version number of the CMSIS with the following define:
-
-
-
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */
-#define __CM3_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)
-
-
- File core_cm0.h contains the version number of the CMSIS with the following define:
-
-
-
-#define __CM0_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */
-#define __CM0_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)
-
-
-
CMSIS Cortex Core
-
- File core_cm3.h contains the type of the CMSIS Cortex-M with the following define:
-
-
-
-#define __CORTEX_M (0x03)
-
-
- File core_cm0.h contains the type of the CMSIS Cortex-M with the following define:
-
-
-
-#define __CORTEX_M (0x00)
-
-
-
CMSIS Files
-
- This section describes the Files provided in context with the CMSIS to access the Cortex-M
- hardware and peripherals.
-
-
-
-
-
-
File
-
Provider
-
Description
-
-
-
device.h
-
Device specific (provided by silicon partner)
-
Defines the peripherals for the actual device. The file may use
- several other include files to define the peripherals of the actual device.
-
-
-
core_cm0.h
-
ARM (for RealView ARMCC, IAR, and GNU GCC)
-
Defines the core peripherals for the Cortex-M0 CPU and core peripherals.
-
-
-
core_cm3.h
-
ARM (for RealView ARMCC, IAR, and GNU GCC)
-
Defines the core peripherals for the Cortex-M3 CPU and core peripherals.
-
-
-
core_cm0.c
-
ARM (for RealView ARMCC, IAR, and GNU GCC)
-
Provides helper functions that access core registers.
-
-
-
core_cm3.c
-
ARM (for RealView ARMCC, IAR, and GNU GCC)
-
Provides helper functions that access core registers.
-
-
-
startup_device
-
ARM (adapted by compiler partner / silicon partner)
-
Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table
-
-
-
system_device
-
ARM (adapted by silicon partner)
-
Provides a device specific configuration file for the device. It configures the device initializes
- typically the oscillator (PLL) that is part of the microcontroller device
-
-
-
-
-
device.h
-
-
- The file device.h is provided by the silicon vendor and is the
- central include file that the application programmer is using in
- the C source code. This file contains:
-
-
-
-
Interrupt Number Definition: provides interrupt numbers
- (IRQn) for all core and device specific exceptions and interrupts.
-
-
-
Configuration for core_cm0.h / core_cm3.h: reflects the
- actual configuration of the Cortex-M processor that is part of the actual
- device. As such the file core_cm0.h / core_cm3.h is included that
- implements access to processor registers and core peripherals.
-
-
-
Device Peripheral Access Layer: provides definitions
- for all device peripherals. It contains all data structures and the address
- mapping for the device specific peripherals.
-
-
Access Functions for Peripherals (optional): provides
- additional helper functions for peripherals that are useful for programming
- of these peripherals. Access Functions may be provided as inline functions
- or can be extern references to a device specific library provided by the
- silicon vendor.
-
-
-
-
Interrupt Number Definition
-
-
To access the device specific interrupts the device.h file defines IRQn
-numbers for the complete device using a enum typedef as shown below:
- The Cortex-M core configuration options which are defined for each device implementation. Some
- configuration options are reflected in the CMSIS layer using the #define settings described below.
-
-
- To access core peripherals file device.h includes file core_cm0.h / core_cm3.h.
- Several features in core_cm0.h / core_cm3.h are configured by the following defines that must be
- defined before #include <core_cm0.h> / #include <core_cm3.h>
- preprocessor command.
-
-
-
-
-
-
#define
-
File
-
Value
-
Description
-
-
-
__NVIC_PRIO_BITS
-
core_cm0.h
-
(2)
-
Number of priority bits implemented in the NVIC (device specific)
-
-
-
__NVIC_PRIO_BITS
-
core_cm3.h
-
(2 ... 8)
-
Number of priority bits implemented in the NVIC (device specific)
-
-
-
__MPU_PRESENT
-
core_cm0.h, core_cm3.h
-
(0, 1)
-
Defines if an MPU is present or not
-
-
-
__Vendor_SysTickConfig
-
core_cm0.h, core_cm3.h
-
(1)
-
When this define is setup to 1, the SysTickConfig function
- in core_cm3.h is excluded. In this case the device.h
- file must contain a vendor specific implementation of this function.
-
-
-
-
-
-
Device Peripheral Access Layer
-
- Each peripheral uses a prefix which consists of <device abbreviation>_
- and <peripheral name>_ to identify peripheral registers that access this
- specific peripheral. The intention of this is to avoid name collisions caused
- due to short names. If more than one peripheral of the same type exists,
- identifiers have a postfix (digit or letter). For example:
-
-
-
<device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device.
-
<device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART.
- For example UART1->DR is the data register of UART1.
-
- To access the peripheral registers and related function in a device the files device.h
- and core_cm0.h / core_cm3.h defines as a minimum:
-
-
-
The Register Layout Typedef for each peripheral that defines all register names.
- Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
- the peripheral registers. For example:
-
-typedef struct {
- __IO uint32_t CTRL; /* SysTick Control and Status Register */
- __IO uint32_t LOAD; /* SysTick Reload Value Register */
- __IO uint32_t VAL; /* SysTick Current Value Register */
- __I uint32_t CALIB; /* SysTick Calibration Register */
- } SysTick_Type;
-
-
-
- Base Address for each peripheral (in case of multiple peripherals
- that use the same register layout typedef multiple base addresses are defined). For example:
-
-#define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */
-
-
-
- Access Definition for each peripheral (in case of multiple peripherals that use
- the same register layout typedef multiple access definitions exist, i.e. LPC_UART0,
- LPC_UART2). For Example:
-
- These definitions allow to access the peripheral registers from user code with simple assignments like:
-
-
SysTick->CTRL = 0;
-
-
Optional Features
-
In addition the device.h file may define:
-
-
- #define constants that simplify access to the peripheral registers.
- These constant define bit-positions or other specific patterns are that required for the
- programming of the peripheral registers. The identifiers used start with
- <device abbreviation>_ and <peripheral name>_.
- It is recommended to use CAPITAL letters for such #define constants.
-
-
- Functions that perform more complex functions with the peripheral (i.e. status query before
- a sending register is accessed). Again these function start with
- <device abbreviation>_ and <peripheral name>_.
-
-
-
-
core_cm0.h and core_cm0.c
-
- File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does
- the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers
- and core peripherals with efficient functions (defined as static inline).
-
-
- File core_cm0.c defines several helper functions that access processor registers.
-
- File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does
- the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers
- and core peripherals with efficient functions (defined as static inline).
-
-
- File core_cm3.c defines several helper functions that access processor registers.
-
- A template file for startup_device is provided by ARM for each supported
- compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific
- interrupt handlers. Each interrupt handler is defined as weak function
- to an dummy handler. Therefore the interrupt handler can be directly used in application software
- without any requirements to adapt the startup_device file.
-
-
- The following exception names are fixed and define the start of the vector table for a Cortex-M0:
-
- The user application may simply define an interrupt handler function by using the handler name
- as shown below.
-
-
-void WWDG_IRQHandler(void)
-{
- :
- :
-}
-
-
-
system_device.c
-
- A template file for system_device.c is provided by ARM but adapted by
- the silicon vendor to match their actual device. As a minimum requirement
- this file must provide a device specific system configuration function and a global variable
- that contains the system frequency. It configures the device and initializes typically the
- oscillator (PLL) that is part of the microcontroller device.
-
-
- The file system_device.c must provide
- as a minimum requirement the SystemInit function as shown below.
-
-
-
-
-
-
Function Definition
-
Description
-
-
-
void SystemInit (void)
-
Setup the microcontroller system. Typically this function configures the
- oscillator (PLL) that is part of the microcontroller device. For systems
- with variable clock speed it also updates the variable SystemCoreClock.
- SystemInit is called from startup_device file.
-
-
-
void SystemCoreClockUpdate (void)
-
Updates the variable SystemCoreClock and must be called whenever the
- core clock is changed during program execution. SystemCoreClockUpdate()
- evaluates the clock register settings and calculates the current core clock.
-
-
-
-
-
-
- Also part of the file system_device.c
- is the variable SystemCoreClock which contains the current CPU clock speed shown below.
-
-
-
-
-
-
Variable Definition
-
Description
-
-
-
uint32_t SystemCoreClock
-
Contains the system core clock (which is the system clock frequency supplied
- to the SysTick timer and the processor core clock). This variable can be
- used by the user application to setup the SysTick timer or configure other
- parameters. It may also be used by debugger to query the frequency of the
- debug timer or configure the trace clock speed.
- SystemCoreClock is initialized with a correct predefined value.
- The compiler must be configured to avoid the removal of this variable in
- case that the application program is not using it. It is important for
- debug systems that the variable is physically present in memory so that
- it can be examined to configure the debugger.
-
-
-
-
-
Note
-
-
The above definitions are the minimum requirements for the file
- system_device.c. This
- file may export more functions or variables that provide a more flexible
- configuration of the microcontroller system.
-
-
-
-
-
Core Peripheral Access Layer
-
-
Cortex-M Core Register Access
-
- The following functions are defined in core_cm0.h / core_cm3.h
- and provide access to Cortex-M core registers.
-
-
-
-
-
-
Function Definition
-
Core
-
Core Register
-
Description
-
-
-
void __enable_irq (void)
-
M0, M3
-
PRIMASK = 0
-
Global Interrupt enable (using the instruction CPSIE
- i)
-
-
-
void __disable_irq (void)
-
M0, M3
-
PRIMASK = 1
-
Global Interrupt disable (using the instruction
- CPSID i)
-
-
-
void __set_PRIMASK (uint32_t value)
-
M0, M3
-
PRIMASK = value
-
Assign value to Priority Mask Register (using the instruction
- MSR)
-
-
-
uint32_t __get_PRIMASK (void)
-
M0, M3
-
return PRIMASK
-
Return Priority Mask Register (using the instruction
- MRS)
-
-
-
void __enable_fault_irq (void)
-
M3
-
FAULTMASK = 0
-
Global Fault exception and Interrupt enable (using the
- instruction CPSIE
- f)
-
-
-
void __disable_fault_irq (void)
-
M3
-
FAULTMASK = 1
-
Global Fault exception and Interrupt disable (using the
- instruction CPSID f)
-
-
-
void __set_FAULTMASK (uint32_t value)
-
M3
-
FAULTMASK = value
-
Assign value to Fault Mask Register (using the instruction
- MSR)
-
-
-
uint32_t __get_FAULTMASK (void)
-
M3
-
return FAULTMASK
-
Return Fault Mask Register (using the instruction MRS)
-
-
-
void __set_BASEPRI (uint32_t value)
-
M3
-
BASEPRI = value
-
Set Base Priority (using the instruction MSR)
-
-
-
uiuint32_t __get_BASEPRI (void)
-
M3
-
return BASEPRI
-
Return Base Priority (using the instruction MRS)
-
-
-
void __set_CONTROL (uint32_t value)
-
M0, M3
-
CONTROL = value
-
Set CONTROL register value (using the instruction MSR)
-
-
-
uint32_t __get_CONTROL (void)
-
M0, M3
-
return CONTROL
-
Return Control Register Value (using the instruction
- MRS)
-
-
-
void __set_PSP (uint32_t TopOfProcStack)
-
M0, M3
-
PSP = TopOfProcStack
-
Set Process Stack Pointer value (using the instruction
- MSR)
-
-
-
uint32_t __get_PSP (void)
-
M0, M3
-
return PSP
-
Return Process Stack Pointer (using the instruction MRS)
-
-
-
void __set_MSP (uint32_t TopOfMainStack)
-
M0, M3
-
MSP = TopOfMainStack
-
Set Main Stack Pointer (using the instruction MSR)
-
-
-
uint32_t __get_MSP (void)
-
M0, M3
-
return MSP
-
Return Main Stack Pointer (using the instruction MRS)
-
-
-
-
-
Cortex-M Instruction Access
-
- The following functions are defined in core_cm0.h / core_cm3.hand
- generate specific Cortex-M instructions. The functions are implemented in the file
- core_cm0.c / core_cm3.c.
-
-
-
-
-
-
Name
-
Core
-
Generated CPU Instruction
-
Description
-
-
-
void __NOP (void)
-
M0, M3
-
NOP
-
No Operation
-
-
-
void __WFI (void)
-
M0, M3
-
WFI
-
Wait for Interrupt
-
-
-
void __WFE (void)
-
M0, M3
-
WFE
-
Wait for Event
-
-
-
void __SEV (void)
-
M0, M3
-
SEV
-
Set Event
-
-
-
void __ISB (void)
-
M0, M3
-
ISB
-
Instruction Synchronization Barrier
-
-
-
void __DSB (void)
-
M0, M3
-
DSB
-
Data Synchronization Barrier
-
-
-
void __DMB (void)
-
M0, M3
-
DMB
-
Data Memory Barrier
-
-
-
uint32_t __REV (uint32_t value)
-
M0, M3
-
REV
-
Reverse byte order in integer value.
-
-
-
uint32_t __REV16 (uint16_t value)
-
M0, M3
-
REV16
-
Reverse byte order in unsigned short value.
-
-
-
sint32_t __REVSH (sint16_t value)
-
M0, M3
-
REVSH
-
Reverse byte order in signed short value with sign extension to integer.
Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW
-
-
-
-
-
-
NVIC Access Functions
-
- The CMSIS provides access to the NVIC via the register interface structure and several helper
- functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to
- identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative
- IRQn values are used for processor core exceptions.
-
-
- For the IRQn values of core exceptions the file device.h provides
- the following enum names.
-
-
-
-
-
-
Core Exception enum Value
-
Core
-
IRQn
-
Description
-
-
-
NonMaskableInt_IRQn
-
M0, M3
-
-14
-
Cortex-M Non Maskable Interrupt
-
-
-
HardFault_IRQn
-
M0, M3
-
-13
-
Cortex-M Hard Fault Interrupt
-
-
-
MemoryManagement_IRQn
-
M3
-
-12
-
Cortex-M Memory Management Interrupt
-
-
-
BusFault_IRQn
-
M3
-
-11
-
Cortex-M Bus Fault Interrupt
-
-
-
UsageFault_IRQn
-
M3
-
-10
-
Cortex-M Usage Fault Interrupt
-
-
-
SVCall_IRQn
-
M0, M3
-
-5
-
Cortex-M SV Call Interrupt
-
-
-
DebugMonitor_IRQn
-
M3
-
-4
-
Cortex-M Debug Monitor Interrupt
-
-
-
PendSV_IRQn
-
M0, M3
-
-2
-
Cortex-M Pend SV Interrupt
-
-
-
SysTick_IRQn
-
M0, M3
-
-1
-
Cortex-M System Tick Interrupt
-
-
-
-
-
The following functions simplify the setup of the NVIC.
-The functions are defined as static inline.
IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub Priority
-
Deccode given priority to group, preemptive and sub priority
-
-
-
void NVIC_SystemReset (void)
-
M0, M3
-
(void)
-
Resets the System
-
-
-
-
Note
-
-
The processor exceptions have negative enum values. Device specific interrupts
- have positive enum values and start with 0. The values are defined in
- device.h file.
-
-
-
The values for PreemptPriority and SubPriority
- used in functions NVIC_EncodePriority and NVIC_DecodePriority
- depend on the available __NVIC_PRIO_BITS implemented in the NVIC.
-
-
-
-
-
-
SysTick Configuration Function
-
-
The following function is used to configure the SysTick timer and start the
-SysTick interrupt.
-
-
-
-
-
Name
-
Parameter
-
Description
-
-
-
uint32_t SysTickConfig
- (uint32_t ticks)
-
ticks is SysTick counter reload value
-
Setup the SysTick timer and enable the SysTick interrupt. After this
- call the SysTick timer creates interrupts with the specified time
- interval.
-
- Return: 0 when successful, 1 on failure.
-
-
-
-
-
-
-
Cortex-M3 ITM Debug Access
-
-
The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that
-provides together with the Serial Viewer Output trace capabilities for the
-microcontroller system. The ITM has 32 communication channels; two ITM
-communication channels are used by CMSIS to output the following information:
-
-
ITM Channel 0: implements the ITM_SendChar function
- which can be used for printf-style output via the debug interface.
-
ITM Channel 31: is reserved for the RTOS kernel and can be used for
- kernel awareness debugging.
-
-
Note
-
-
The ITM channel 31 is selected for the RTOS kernel since some kernels
- may use the Privileged level for program execution. ITM
- channels have 4 groups with 8 channels each, whereby each group can be
- configured for access rights in the Unprivileged level. The ITM channel 0
- may be therefore enabled for the user task whereas ITM channel 31 may be
- accessible only in Privileged level from the RTOS kernel itself.
-
-
-
-
The prototype of the ITM_SendChar routine is shown in the
-table below.
-
-
-
-
-
Name
-
Parameter
-
Description
-
-
-
void uint32_t ITM_SendChar(uint32_t chr)
-
character to output
-
The function outputs a character via the ITM channel 0. The
- function returns when no debugger is connected that has booked the
- output. It is blocking when a debugger is connected, but the
- previous character send is not transmitted.
- Return: the input character 'chr'.
-
-
-
-
-
- Example for the usage of the ITM Channel 31 for RTOS Kernels:
-
-
- // check if debugger connected and ITM channel enabled for tracing
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
- (ITM->TCR & ITM_TCR_ITMENA) &&
- (ITM->TER & (1UL << 31))) {
- // transmit trace data
- while (ITM->PORT31_U32 == 0);
- ITM->PORT[31].u8 = task_id; // id of next task
- while (ITM->PORT[31].u32 == 0);
- ITM->PORT[31].u32 = task_status; // status information
- }
-
-
-
Cortex-M3 additional Debug Access
-
-
CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access.
-Data can be transmitted via a certain global buffer variable towards the target system.
-
-
The buffer variable and the prototypes of the additional functions are shown in the
-table below.
-
-
-
-
-
Name
-
Parameter
-
Description
-
-
-
extern volatile int ITM_RxBuffer
-
-
Buffer to transmit data towards debug system.
- Value 0x5AA55AA5 indicates that buffer is empty.
-
-
-
int ITM_ReceiveChar (void)
-
none
-
The nonblocking functions returns the character stored in
- ITM_RxBuffer.
- Return: -1 indicates that no character was received.
-
-
-
int ITM_CheckChar (void)
-
none
-
The function checks if a character is available in ITM_RxBuffer.
- Return: 1 indicates that a character is available, 0 indicates that
- no character is available.
-
-
-
-
-
-
CMSIS Example
-
- The following section shows a typical example for using the CMSIS layer in user applications.
- The example is based on a STM32F10x Device.
-
-
-#include "stm32f10x.h"
-
-volatile uint32_t msTicks; /* timeTicks counter */
-
-void SysTick_Handler(void) {
- msTicks++; /* increment timeTicks counter */
-}
-
-__INLINE static void Delay (uint32_t dlyTicks) {
- uint32_t curTicks = msTicks;
-
- while ((msTicks - curTicks) < dlyTicks);
-}
-
-__INLINE static void LED_Config(void) {
- ; /* Configure the LEDs */
-}
-
-__INLINE static void LED_On (uint32_t led) {
- ; /* Turn On LED */
-}
-
-__INLINE static void LED_Off (uint32_t led) {
- ; /* Turn Off LED */
-}
-
-int main (void) {
- if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
- ; /* Handle Error */
- while (1);
- }
-
- LED_Config(); /* configure the LEDs */
-
- while(1) {
- LED_On (0x100); /* Turn on the LED */
- Delay (100); /* delay 100 Msec */
- LED_Off (0x100); /* Turn off the LED */
- Delay (100); /* delay 100 Msec */
- }
-}
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Boot/lib/CMSIS/License.doc b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Boot/lib/CMSIS/License.doc
deleted file mode 100644
index b6b8acec..00000000
Binary files a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Boot/lib/CMSIS/License.doc and /dev/null differ
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Boot/main.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Boot/main.c
deleted file mode 100644
index ef5af572..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Boot/main.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/****************************************************************************************
-| Description: bootloader application source file
-| File Name: main.c
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "boot.h" /* bootloader generic header */
-#include "stm32f10x.h" /* microcontroller registers */
-
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-static void Init(void);
-
-
-/****************************************************************************************
-** NAME: main
-** PARAMETER: none
-** RETURN VALUE: program return code
-** DESCRIPTION: This is the entry point for the bootloader application and is called
-** by the reset interrupt vector after the C-startup routines executed.
-**
-****************************************************************************************/
-int main(void)
-{
- /* initialize the microcontroller */
- Init();
- /* initialize the bootloader */
- BootInit();
-
- /* start the infinite program loop */
- while (1)
- {
- /* run the bootloader task */
- BootTask();
- }
-
- /* program should never get here */
- return 0;
-} /*** end of main ***/
-
-
-/****************************************************************************************
-** NAME: Init
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Initializes the microcontroller. The interrupts are disabled, the
-** clocks are configured and the flash wait states are configured.
-**
-****************************************************************************************/
-static void Init(void)
-{
- volatile blt_int32u StartUpCounter = 0, HSEStatus = 0;
- blt_int32u pll_multiplier;
-
- /* reset the RCC clock configuration to the default reset state (for debug purpose) */
- /* set HSION bit */
- RCC->CR |= (blt_int32u)0x00000001;
- /* reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
- RCC->CFGR &= (blt_int32u)0xF8FF0000;
- /* reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (blt_int32u)0xFEF6FFFF;
- /* reset HSEBYP bit */
- RCC->CR &= (blt_int32u)0xFFFBFFFF;
- /* reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
- RCC->CFGR &= (blt_int32u)0xFF80FFFF;
- /* disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
- /* enable HSE */
- RCC->CR |= ((blt_int32u)RCC_CR_HSEON);
- /* wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != 1500));
- /* check if time out was reached */
- if ((RCC->CR & RCC_CR_HSERDY) == RESET)
- {
- /* cannot continue when HSE is not ready */
- ASSERT_RT(BLT_FALSE);
- }
- /* enable flash prefetch buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
- /* reset flash wait state configuration to default 0 wait states */
- FLASH->ACR &= (blt_int32u)((blt_int32u)~FLASH_ACR_LATENCY);
-#if (BOOT_CPU_SYSTEM_SPEED_KHZ > 48000)
- /* configure 2 flash wait states */
- FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_2;
-#elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000)
- /* configure 1 flash wait states */
- FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_1;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFGR |= (blt_int32u)RCC_CFGR_HPRE_DIV1;
- /* PCLK2 = HCLK/2 */
- RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE2_DIV2;
- /* PCLK1 = HCLK/2 */
- RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE1_DIV2;
- /* reset PLL configuration */
- RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | \
- RCC_CFGR_PLLMULL));
- /* assert that the pll_multiplier is between 2 and 16 */
- ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) >= 2);
- ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) <= 16);
- /* calculate multiplier value */
- pll_multiplier = BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ;
- /* convert to register value */
- pll_multiplier = (blt_int32u)((pll_multiplier - 2) << 18);
- /* set the PLL multiplier and clock source */
- RCC->CFGR |= (blt_int32u)(RCC_CFGR_PLLSRC_HSE | pll_multiplier);
- /* enable PLL */
- RCC->CR |= RCC_CR_PLLON;
- /* wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
- /* select PLL as system clock source */
- RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_SW));
- RCC->CFGR |= (blt_int32u)RCC_CFGR_SW_PLL;
- /* wait till PLL is used as system clock source */
- while ((RCC->CFGR & (blt_int32u)RCC_CFGR_SWS) != (blt_int32u)0x08)
- {
- }
-#if (BOOT_COM_UART_ENABLE > 0)
- /* enable clock for USART2 peripheral */
- RCC->APB1ENR |= (blt_int32u)0x00020000;
- /* enable clocks for USART2 transmitter and receiver pins (GPIOA and AFIO) */
- RCC->APB2ENR |= (blt_int32u)(0x00000004 | 0x00000001);
- /* configure USART2 Tx (GPIOA2) as alternate function push-pull */
- /* first reset the configuration */
- GPIOA->CRL &= ~(blt_int32u)((blt_int32u)0xf << 8);
- /* CNF2[1:0] = %10 and MODE2[1:0] = %11 */
- GPIOA->CRL |= (blt_int32u)((blt_int32u)0xb << 8);
- /* configure USART2 Rx (GPIOA3) as alternate function input floating */
- /* first reset the configuration */
- GPIOA->CRL &= ~(blt_int32u)((blt_int32u)0xf << 12);
- /* CNF2[1:0] = %01 and MODE2[1:0] = %00 */
- GPIOA->CRL |= (blt_int32u)((blt_int32u)0x4 << 12);
-#endif
-#if (BOOT_COM_CAN_ENABLE > 0)
- /* enable clocks for CAN transmitter and receiver pins (GPIOB and AFIO) */
- RCC->APB2ENR |= (blt_int32u)(0x00000008 | 0x00000001);
- /* configure CAN Rx (GPIOB8) as alternate function input pull-up */
- /* first reset the configuration */
- GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 0);
- /* CNF8[1:0] = %10 and MODE8[1:0] = %00 */
- GPIOB->CRH |= (blt_int32u)((blt_int32u)0x8 << 0);
- /* configure CAN Tx (GPIOB9) as alternate function push-pull */
- /* first reset the configuration */
- GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 4);
- /* CNF9[1:0] = %10 and MODE9[1:0] = %11 */
- GPIOB->CRH |= (blt_int32u)((blt_int32u)0xb << 4);
- /* remap CAN1 pins to PortB */
- AFIO->MAPR &= ~(blt_int32u)((blt_int32u)0x3 << 13);
- AFIO->MAPR |= (blt_int32u)((blt_int32u)0x2 << 13);
- /* enable clocks for CAN controller peripheral */
- RCC->APB1ENR |= (blt_int32u)0x02000000;
-#endif
-} /*** end of Init ***/
-
-
-/*********************************** end of main.c *************************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/.cproject b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/.cproject
deleted file mode 100644
index 0b8696c1..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/.cproject
+++ /dev/null
@@ -1,93 +0,0 @@
-
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-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/.project b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/.project
deleted file mode 100644
index 9b8da01b..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/.project
+++ /dev/null
@@ -1,82 +0,0 @@
-
-
- Prog
-
-
-
-
-
- org.eclipse.cdt.managedbuilder.core.genmakebuilder
- clean,full,incremental,
-
-
- ?name?
-
-
-
- org.eclipse.cdt.make.core.append_environment
- true
-
-
- org.eclipse.cdt.make.core.autoBuildTarget
- all
-
-
- org.eclipse.cdt.make.core.buildArguments
-
-
-
- org.eclipse.cdt.make.core.buildCommand
- cs-make
-
-
- org.eclipse.cdt.make.core.buildLocation
- ${workspace_loc:/Prog/Debug}
-
-
- org.eclipse.cdt.make.core.cleanBuildTarget
- clean
-
-
- org.eclipse.cdt.make.core.contents
- org.eclipse.cdt.make.core.activeConfigSettings
-
-
- org.eclipse.cdt.make.core.enableAutoBuild
- false
-
-
- org.eclipse.cdt.make.core.enableCleanBuild
- true
-
-
- org.eclipse.cdt.make.core.enableFullBuild
- true
-
-
- org.eclipse.cdt.make.core.fullBuildTarget
- all
-
-
- org.eclipse.cdt.make.core.stopOnError
- true
-
-
- org.eclipse.cdt.make.core.useDefaultBuildCmd
- true
-
-
-
-
- org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
- full,incremental,
-
-
-
-
-
- org.eclipse.cdt.core.cnature
- org.eclipse.cdt.managedbuilder.core.managedBuildNature
- org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
-
-
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/.settings/org.eclipse.cdt.core.prefs b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/.settings/org.eclipse.cdt.core.prefs
deleted file mode 100644
index ccaafbe3..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/.settings/org.eclipse.cdt.core.prefs
+++ /dev/null
@@ -1,163 +0,0 @@
-#Fri Dec 02 15:00:26 CET 2011
-eclipse.preferences.version=1
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-org.eclipse.cdt.core.formatter.brace_position_for_block_in_case=next_line
-org.eclipse.cdt.core.formatter.brace_position_for_method_declaration=next_line
-org.eclipse.cdt.core.formatter.brace_position_for_namespace_declaration=next_line
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diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/.settings/org.eclipse.cdt.ui.prefs b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/.settings/org.eclipse.cdt.ui.prefs
deleted file mode 100644
index 379e5255..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/.settings/org.eclipse.cdt.ui.prefs
+++ /dev/null
@@ -1,4 +0,0 @@
-#Fri Dec 02 15:00:26 CET 2011
-eclipse.preferences.version=1
-formatter_profile=_Feaser
-formatter_settings_version=1
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/bin/demoprog_olimex_stm32p103.map b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/bin/demoprog_olimex_stm32p103.map
deleted file mode 100644
index cebe2b54..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/bin/demoprog_olimex_stm32p103.map
+++ /dev/null
@@ -1,2009 +0,0 @@
-Archive member included because of file (symbol)
-
-c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-ctype_.o)
- ./lib/stdio_mini.o (__ctype_ptr__)
-c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-strtol.o)
- ./lib/stdio_mini.o (strtol)
-c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-strtoul.o)
- ./lib/stdio_mini.o (strtoul)
-c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-impure.o)
- c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-strtol.o) (_impure_ptr)
-c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/thumb2\libgcc.a(_udivsi3.o)
- c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-strtol.o) (__aeabi_uidiv)
-c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/thumb2\libgcc.a(_dvmd_tls.o)
- c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/thumb2\libgcc.a(_udivsi3.o) (__aeabi_idiv0)
-
-Discarded input sections
-
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- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.o
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- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.o
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- 0x00000000 0x84 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.o
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- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.o
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- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.o
- .text.SysTick_CLKSourceConfig
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_DeInit
- 0x00000000 0x80 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_Init
- 0x00000000 0x50 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_StructInit
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_Cmd 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_DMACmd
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_ITConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_ResetCalibration
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_GetResetCalibrationStatus
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_StartCalibration
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_GetCalibrationStatus
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_SoftwareStartConvCmd
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_GetSoftwareStartConvStatus
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_DiscModeChannelCountConfig
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_DiscModeCmd
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_RegularChannelConfig
- 0x00000000 0xb4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_ExternalTrigConvCmd
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_GetConversionValue
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_GetDualModeConversionValue
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_AutoInjectedConvCmd
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_InjectedDiscModeCmd
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_ExternalTrigInjectedConvConfig
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_ExternalTrigInjectedConvCmd
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_SoftwareStartInjectedConvCmd
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_GetSoftwareStartInjectedConvCmdStatus
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_InjectedChannelConfig
- 0x00000000 0x70 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_InjectedSequencerLengthConfig
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_SetInjectedOffset
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_GetInjectedConversionValue
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_AnalogWatchdogCmd
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_AnalogWatchdogThresholdsConfig
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_AnalogWatchdogSingleChannelConfig
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_TempSensorVrefintCmd
- 0x00000000 0x28 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_GetFlagStatus
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_ClearFlag
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_GetITStatus
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text.ADC_ClearITPendingBit
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .text.BKP_DeInit
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .text.BKP_TamperPinLevelConfig
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .text.BKP_TamperPinCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .text.BKP_ITConfig
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .text.BKP_RTCOutputConfig
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .text.BKP_SetRTCCalibrationValue
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .text.BKP_WriteBackupRegister
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .text.BKP_ReadBackupRegister
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .text.BKP_GetFlagStatus
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .text.BKP_ClearFlag
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .text.BKP_GetITStatus
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .text.BKP_ClearITPendingBit
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CheckITStatus
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_DeInit
- 0x00000000 0x4c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_Init
- 0x00000000 0xf4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_FilterInit
- 0x00000000 0x140 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_StructInit
- 0x00000000 0x28 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_SlaveStartBank
- 0x00000000 0x40 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_DBGFreeze
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_TTComModeCmd
- 0x00000000 0x60 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_Transmit
- 0x00000000 0xe0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_TransmitStatus
- 0x00000000 0x94 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_CancelTransmit
- 0x00000000 0x2c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_Receive
- 0x00000000 0xbc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_FIFORelease
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_MessagePending
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_OperatingModeRequest
- 0x00000000 0xb0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_Sleep
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_WakeUp
- 0x00000000 0x30 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_GetLastErrorCode
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_GetReceiveErrorCounter
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_GetLSBTransmitErrorCounter
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_ITConfig
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_GetFlagStatus
- 0x00000000 0x7c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_ClearFlag
- 0x00000000 0x3c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_GetITStatus
- 0x00000000 0x174 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text.CAN_ClearITPendingBit
- 0x00000000 0xbc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_DeInit
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_Init
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_Cmd 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_ITConfig
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_OwnAddressConfig
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_SetPrescaler
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_SendDataByte
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_ReceiveDataByte
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_StartOfMessage
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_EndOfMessageCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_GetFlagStatus
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_ClearFlag
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_GetITStatus
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text.CEC_ClearITPendingBit
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.o
- .text.CRC_ResetDR
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.o
- .text.CRC_CalcCRC
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.o
- .text.CRC_CalcBlockCRC
- 0x00000000 0x30 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.o
- .text.CRC_GetCRC
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.o
- .text.CRC_SetIDRegister
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.o
- .text.CRC_GetIDRegister
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .text.DAC_DeInit
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .text.DAC_Init
- 0x00000000 0x38 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .text.DAC_StructInit
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .text.DAC_Cmd 0x00000000 0x34 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .text.DAC_DMACmd
- 0x00000000 0x34 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .text.DAC_SoftwareTriggerCmd
- 0x00000000 0x3c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .text.DAC_DualSoftwareTriggerCmd
- 0x00000000 0x28 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .text.DAC_WaveGenerationCmd
- 0x00000000 0x2c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .text.DAC_SetChannel1Data
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .text.DAC_SetChannel2Data
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .text.DAC_SetDualChannelData
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .text.DAC_GetDataOutputValue
- 0x00000000 0x28 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.o
- .text.DBGMCU_GetREVID
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.o
- .text.DBGMCU_GetDEVID
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.o
- .text.DBGMCU_Config
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .text.DMA_DeInit
- 0x00000000 0x184 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .text.DMA_Init
- 0x00000000 0x40 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .text.DMA_StructInit
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .text.DMA_Cmd 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .text.DMA_ITConfig
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .text.DMA_SetCurrDataCounter
- 0x00000000 0x4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .text.DMA_GetCurrDataCounter
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .text.DMA_GetFlagStatus
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .text.DMA_ClearFlag
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .text.DMA_GetITStatus
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .text.DMA_ClearITPendingBit
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.o
- .text.EXTI_DeInit
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.o
- .text.EXTI_Init
- 0x00000000 0x9c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.o
- .text.EXTI_StructInit
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.o
- .text.EXTI_GenerateSWInterrupt
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.o
- .text.EXTI_GetFlagStatus
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.o
- .text.EXTI_ClearFlag
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.o
- .text.EXTI_GetITStatus
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.o
- .text.EXTI_ClearITPendingBit
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_SetLatency
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_HalfCycleAccessCmd
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_PrefetchBufferCmd
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_Unlock
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_UnlockBank1
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_Lock
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_LockBank1
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_GetUserOptionByte
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_GetWriteProtectionOptionByte
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_GetReadOutProtectionStatus
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_GetPrefetchBufferStatus
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_ITConfig
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_GetFlagStatus
- 0x00000000 0x28 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_ClearFlag
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_GetStatus
- 0x00000000 0x44 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_GetBank1Status
- 0x00000000 0x44 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_WaitForLastOperation
- 0x00000000 0x38 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_UserOptionByteConfig
- 0x00000000 0x80 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_ReadOutProtection
- 0x00000000 0xd4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_EnableWriteProtection
- 0x00000000 0x108 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_ProgramOptionByteData
- 0x00000000 0x68 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_ProgramHalfWord
- 0x00000000 0x48 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_ProgramWord
- 0x00000000 0x90 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_EraseOptionBytes
- 0x00000000 0xcc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_EraseAllPages
- 0x00000000 0x48 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_ErasePage
- 0x00000000 0x4c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_WaitForLastBank1Operation
- 0x00000000 0x38 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text.FLASH_EraseAllBank1Pages
- 0x00000000 0x48 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_NORSRAMDeInit
- 0x00000000 0x3c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_NANDDeInit
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_PCCARDDeInit
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_NORSRAMInit
- 0x00000000 0xdc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_NANDInit
- 0x00000000 0x68 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_PCCARDInit
- 0x00000000 0x70 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_NORSRAMStructInit
- 0x00000000 0x70 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_NANDStructInit
- 0x00000000 0x3c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_PCCARDStructInit
- 0x00000000 0x40 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_NORSRAMCmd
- 0x00000000 0x30 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_NANDCmd
- 0x00000000 0x38 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_PCCARDCmd
- 0x00000000 0x30 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_NANDECCCmd
- 0x00000000 0x38 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_GetECC
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_ITConfig
- 0x00000000 0x5c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_GetFlagStatus
- 0x00000000 0x2c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_ClearFlag
- 0x00000000 0x30 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_GetITStatus
- 0x00000000 0x38 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text.FSMC_ClearITPendingBit
- 0x00000000 0x30 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_DeInit
- 0x00000000 0x128 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_AFIODeInit
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_StructInit
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_ReadInputDataBit
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_ReadInputData
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_ReadOutputDataBit
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_ReadOutputData
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_WriteBit
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_Write
- 0x00000000 0x4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_PinLockConfig
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_EventOutputConfig
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_EventOutputCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_PinRemapConfig
- 0x00000000 0x7c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_EXTILineConfig
- 0x00000000 0x44 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text.GPIO_ETH_MediaInterfaceConfig
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_DeInit
- 0x00000000 0x4c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_Init
- 0x00000000 0x10c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_StructInit
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_Cmd 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_DMACmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_DMALastTransferCmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_GenerateSTART
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_GenerateSTOP
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_AcknowledgeConfig
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_OwnAddress2Config
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_DualAddressCmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_GeneralCallCmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_ITConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_SendData
- 0x00000000 0x4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_ReceiveData
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_Send7bitAddress
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_ReadRegister
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_SoftwareResetCmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_NACKPositionConfig
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_SMBusAlertConfig
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_TransmitPEC
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_PECPositionConfig
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_CalculatePEC
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_GetPEC
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_ARPCmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_StretchClockCmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_FastModeDutyCycleConfig
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_CheckEvent
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_GetLastEvent
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_GetFlagStatus
- 0x00000000 0x40 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_ClearFlag
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_GetITStatus
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text.I2C_ClearITPendingBit
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.o
- .text.IWDG_WriteAccessCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.o
- .text.IWDG_SetPrescaler
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.o
- .text.IWDG_SetReload
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.o
- .text.IWDG_ReloadCounter
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.o
- .text.IWDG_Enable
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.o
- .text.IWDG_GetFlagStatus
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.o
- .text.PWR_DeInit
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.o
- .text.PWR_BackupAccessCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.o
- .text.PWR_PVDCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.o
- .text.PWR_PVDLevelConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.o
- .text.PWR_WakeUpPinCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.o
- .text.PWR_EnterSTOPMode
- 0x00000000 0x40 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.o
- .text.PWR_EnterSTANDBYMode
- 0x00000000 0x2c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.o
- .text.PWR_GetFlagStatus
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.o
- .text.PWR_ClearFlag
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_DeInit
- 0x00000000 0x44 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_HSEConfig
- 0x00000000 0x4c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_AdjustHSICalibrationValue
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_HSICmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_PLLConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_PLLCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_SYSCLKConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_GetSYSCLKSource
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_HCLKConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_PCLK1Config
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_PCLK2Config
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_ITConfig
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_USBCLKConfig
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_ADCCLKConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_LSEConfig
- 0x00000000 0x3c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_LSICmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_RTCCLKConfig
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_RTCCLKCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_AHBPeriphClockCmd
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_APB2PeriphResetCmd
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_APB1PeriphResetCmd
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_BackupResetCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_ClockSecuritySystemCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_MCOConfig
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_GetFlagStatus
- 0x00000000 0x34 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_WaitForHSEStartUp
- 0x00000000 0x48 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_ClearFlag
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_GetITStatus
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text.RCC_ClearITPendingBit
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_ITConfig
- 0x00000000 0x28 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_EnterConfigMode
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_ExitConfigMode
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_GetCounter
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_SetCounter
- 0x00000000 0x2c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_SetPrescaler
- 0x00000000 0x2c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_SetAlarm
- 0x00000000 0x2c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_GetDivider
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_WaitForLastTask
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_WaitForSynchro
- 0x00000000 0x2c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_GetFlagStatus
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_ClearFlag
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_GetITStatus
- 0x00000000 0x28 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text.RTC_ClearITPendingBit
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_DeInit
- 0x00000000 0x28 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_Init
- 0x00000000 0x34 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_StructInit
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_ClockCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_SetPowerState
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_GetPowerState
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_ITConfig
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_DMACmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_SendCommand
- 0x00000000 0x30 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_CmdStructInit
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_GetCommandResponse
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_GetResponse
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_DataConfig
- 0x00000000 0x30 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_DataStructInit
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_GetDataCounter
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_ReadData
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_WriteData
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_GetFIFOCount
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_StartSDIOReadWait
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_StopSDIOReadWait
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_SetSDIOReadWaitMode
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_SetSDIOOperation
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_SendSDIOSuspendCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_CommandCompletionCmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_CEATAITCmd
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_SendCEATACmd
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_GetFlagStatus
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_ClearFlag
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_GetITStatus
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text.SDIO_ClearITPendingBit
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_I2S_DeInit
- 0x00000000 0x80 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_Init
- 0x00000000 0x48 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.I2S_Init
- 0x00000000 0xd8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_StructInit
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.I2S_StructInit
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_Cmd 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.I2S_Cmd 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_I2S_ITConfig
- 0x00000000 0x28 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_I2S_DMACmd
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_I2S_SendData
- 0x00000000 0x4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_I2S_ReceiveData
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_NSSInternalSoftwareConfig
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_SSOutputCmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_DataSizeConfig
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_TransmitCRC
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_CalculateCRC
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_GetCRC
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_GetCRCPolynomial
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_BiDirectionalLineConfig
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_I2S_GetFlagStatus
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_I2S_ClearFlag
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_I2S_GetITStatus
- 0x00000000 0x34 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text.SPI_I2S_ClearITPendingBit
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TI1_Config
- 0x00000000 0xb4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TI2_Config
- 0x00000000 0xb8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_DeInit
- 0x00000000 0x2c4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_TimeBaseInit
- 0x00000000 0xf0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC1Init
- 0x00000000 0xd4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC2Init
- 0x00000000 0xb0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC3Init
- 0x00000000 0xac ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC4Init
- 0x00000000 0x8c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_BDTRConfig
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_TimeBaseStructInit
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OCStructInit
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ICStructInit
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_BDTRStructInit
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_Cmd 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_CtrlPWMOutputs
- 0x00000000 0x28 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ITConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_GenerateEvent
- 0x00000000 0x4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_DMAConfig
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_DMACmd
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_InternalClockConfig
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ETRConfig
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ETRClockMode2Config
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ETRClockMode1Config
- 0x00000000 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_PrescalerConfig
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_CounterModeConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SelectInputTrigger
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_TIxExternalClockConfig
- 0x00000000 0x3c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ITRxExternalClockConfig
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_EncoderInterfaceConfig
- 0x00000000 0x50 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ForcedOC1Config
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ForcedOC2Config
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ForcedOC3Config
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ForcedOC4Config
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ARRPreloadConfig
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SelectCOM
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SelectCCDMA
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_CCPreloadControl
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC1PreloadConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC2PreloadConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC3PreloadConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC4PreloadConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC1FastConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC2FastConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC3FastConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC4FastConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ClearOC1Ref
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ClearOC2Ref
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ClearOC3Ref
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ClearOC4Ref
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC1PolarityConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC1NPolarityConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC2PolarityConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC2NPolarityConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC3PolarityConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC3NPolarityConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_OC4PolarityConfig
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_CCxCmd
- 0x00000000 0x28 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_CCxNCmd
- 0x00000000 0x28 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SelectOCxM
- 0x00000000 0x64 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_UpdateDisableConfig
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_UpdateRequestConfig
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SelectHallSensor
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SelectOnePulseMode
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SelectOutputTrigger
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SelectSlaveMode
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SelectMasterSlaveMode
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SetCounter
- 0x00000000 0x4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SetAutoreload
- 0x00000000 0x4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SetCompare1
- 0x00000000 0x4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SetCompare2
- 0x00000000 0x4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SetCompare3
- 0x00000000 0x4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SetCompare4
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SetIC1Prescaler
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SetIC2Prescaler
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_PWMIConfig
- 0x00000000 0xa0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SetIC3Prescaler
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SetIC4Prescaler
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ICInit
- 0x00000000 0x1e4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_SetClockDivision
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_GetCapture1
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_GetCapture2
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_GetCapture3
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_GetCapture4
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_GetCounter
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_GetPrescaler
- 0x00000000 0x8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_GetFlagStatus
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ClearFlag
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_GetITStatus
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text.TIM_ClearITPendingBit
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_DeInit
- 0x00000000 0xd4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_StructInit
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_ClockInit
- 0x00000000 0x2c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_ClockStructInit
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_ITConfig
- 0x00000000 0x3c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_DMACmd
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_SetAddress
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_WakeUpConfig
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_ReceiverWakeUpCmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_LINBreakDetectLengthConfig
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_LINCmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_SendBreak
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_SetGuardTime
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_SetPrescaler
- 0x00000000 0x14 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_SmartCardCmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_SmartCardNACKCmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_HalfDuplexCmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_OverSampling8Cmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_OneBitMethodCmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_IrDAConfig
- 0x00000000 0x1c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_IrDACmd
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_ClearFlag
- 0x00000000 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_GetITStatus
- 0x00000000 0x54 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text.USART_ClearITPendingBit
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.o
- .text.WWDG_DeInit
- 0x00000000 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.o
- .text.WWDG_SetPrescaler
- 0x00000000 0x18 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.o
- .text.WWDG_SetWindowValue
- 0x00000000 0x2c ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.o
- .text.WWDG_EnableIT
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.o
- .text.WWDG_SetCounter
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.o
- .text.WWDG_Enable
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.o
- .text.WWDG_GetFlagStatus
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.o
- .text.WWDG_ClearFlag
- 0x00000000 0x10 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.o
- .text.SystemInit
- 0x00000000 0x130 ./lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.o
- .text.SystemCoreClockUpdate
- 0x00000000 0xe0 ./lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.o
- .data.AHBPrescTable
- 0x00000000 0x10 ./lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.o
- .data.SystemCoreClock
- 0x00000000 0x4 ./lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.o
- .text 0x00000000 0x0 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .data 0x00000000 0x0 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .bss 0x00000000 0x0 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__get_PSP
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__set_PSP
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__get_MSP
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__set_MSP
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__get_BASEPRI
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__set_BASEPRI
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__get_PRIMASK
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__set_PRIMASK
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__get_FAULTMASK
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__set_FAULTMASK
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__get_CONTROL
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__set_CONTROL
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__REV 0x00000000 0x4 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__REV16 0x00000000 0x4 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__REVSH 0x00000000 0x4 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__RBIT 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__LDREXB
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__LDREXH
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__LDREXW
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__STREXB
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__STREXH
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text.__STREXW
- 0x00000000 0x8 ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
- .text 0x00000000 0x0 ./lib/stdio_mini.o
- .data 0x00000000 0x0 ./lib/stdio_mini.o
- .bss 0x00000000 0x0 ./lib/stdio_mini.o
- .text.puts 0x00000000 0x34 ./lib/stdio_mini.o
- .text.scanf 0x00000000 0x258 ./lib/stdio_mini.o
- .text 0x00000000 0x0 ./boot.o
- .data 0x00000000 0x0 ./boot.o
- .bss 0x00000000 0x0 ./boot.o
- .text 0x00000000 0x0 ./cstart.o
- .data 0x00000000 0x0 ./cstart.o
- .bss 0x00000000 0x0 ./cstart.o
- .text 0x00000000 0x0 ./irq.o
- .data 0x00000000 0x0 ./irq.o
- .bss 0x00000000 0x0 ./irq.o
- .text.IrqInterruptDisable
- 0x00000000 0x20 ./irq.o
- .text.IrqInterruptRestore
- 0x00000000 0x18 ./irq.o
- .bss.interruptNesting
- 0x00000000 0x1 ./irq.o
- .text 0x00000000 0x0 ./led.o
- .data 0x00000000 0x0 ./led.o
- .bss 0x00000000 0x0 ./led.o
- .text 0x00000000 0x0 ./main.o
- .data 0x00000000 0x0 ./main.o
- .bss 0x00000000 0x0 ./main.o
- .text 0x00000000 0x0 ./timer.o
- .data 0x00000000 0x0 ./timer.o
- .bss 0x00000000 0x0 ./timer.o
- .text 0x00000000 0x0 ./uart.o
- .data 0x00000000 0x0 ./uart.o
- .bss 0x00000000 0x0 ./uart.o
- .text 0x00000000 0x0 ./vectors.o
- .data 0x00000000 0x0 ./vectors.o
- .bss 0x00000000 0x0 ./vectors.o
- .text 0x00000000 0x0 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-ctype_.o)
- .bss 0x00000000 0x0 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-ctype_.o)
- .text 0x00000000 0x17c c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-strtol.o)
- .data 0x00000000 0x0 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-strtol.o)
- .bss 0x00000000 0x0 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-strtol.o)
- .text 0x00000000 0x17c c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-strtoul.o)
- .data 0x00000000 0x0 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-strtoul.o)
- .bss 0x00000000 0x0 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-strtoul.o)
- .text 0x00000000 0x0 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-impure.o)
- .data 0x00000000 0xf4 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-impure.o)
- .bss 0x00000000 0x0 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-impure.o)
- .rodata 0x00000000 0x4 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-impure.o)
- .rodata.str1.4
- 0x00000000 0x4 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a(lib_a-impure.o)
- .text 0x00000000 0x278 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/thumb2\libgcc.a(_udivsi3.o)
- .data 0x00000000 0x0 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/thumb2\libgcc.a(_udivsi3.o)
- .bss 0x00000000 0x0 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/thumb2\libgcc.a(_udivsi3.o)
- .text 0x00000000 0x4 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/thumb2\libgcc.a(_dvmd_tls.o)
- .data 0x00000000 0x0 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/thumb2\libgcc.a(_dvmd_tls.o)
- .bss 0x00000000 0x0 c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/thumb2\libgcc.a(_dvmd_tls.o)
-
-Memory Configuration
-
-Name Origin Length Attributes
-FLASH 0x08002000 0x0001e000 xr
-SRAM 0x20000000 0x00005000 xrw
-*default* 0x00000000 0xffffffff
-
-Linker script and memory map
-
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
-LOAD ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.o
-LOAD ./lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.o
-LOAD ./lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.o
-LOAD ./lib/stdio_mini.o
-LOAD ./boot.o
-LOAD ./cstart.o
-LOAD ./irq.o
-LOAD ./led.o
-LOAD ./main.o
-LOAD ./timer.o
-LOAD ./uart.o
-LOAD ./vectors.o
-START GROUP
-LOAD c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/thumb2\libgcc.a
-LOAD c:/program files (x86)/codesourcery/sourcery g++ lite/bin/../lib/gcc/arm-none-eabi/4.5.1/../../../../arm-none-eabi/lib/thumb2\libc.a
-END GROUP
- 0x00000400 __STACKSIZE__ = 0x400
-
-.text 0x08002000 0x1158
- *(.isr_vector)
- .isr_vector 0x08002000 0x154 ./vectors.o
- 0x08002000 _vectab
- *(.text*)
- .text.GPIO_Init
- 0x08002154 0xc4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- 0x08002154 GPIO_Init
- .text.GPIO_SetBits
- 0x08002218 0x4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- 0x08002218 GPIO_SetBits
- .text.GPIO_ResetBits
- 0x0800221c 0x4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.o
- 0x0800221c GPIO_ResetBits
- .text.RCC_GetClocksFreq
- 0x08002220 0xe4 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- 0x08002220 RCC_GetClocksFreq
- .text.RCC_APB2PeriphClockCmd
- 0x08002304 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- 0x08002304 RCC_APB2PeriphClockCmd
- .text.RCC_APB1PeriphClockCmd
- 0x08002328 0x24 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.o
- 0x08002328 RCC_APB1PeriphClockCmd
- .text.USART_Init
- 0x0800234c 0xf8 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- 0x0800234c USART_Init
- .text.USART_Cmd
- 0x08002444 0x20 ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- 0x08002444 USART_Cmd
- .text.USART_SendData
- 0x08002464 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- 0x08002464 USART_SendData
- .text.USART_ReceiveData
- 0x08002470 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- 0x08002470 USART_ReceiveData
- .text.USART_GetFlagStatus
- 0x0800247c 0xc ./lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.o
- 0x0800247c USART_GetFlagStatus
- .text.output_dup
- 0x08002488 0x2c ./lib/stdio_mini.o
- .text.format_integer
- 0x080024b4 0x1e8 ./lib/stdio_mini.o
- .text.printf 0x0800269c 0x330 ./lib/stdio_mini.o
- 0x0800269c printf
- .text.BootComInit
- 0x080029cc 0x14 ./boot.o
- 0x080029cc BootComInit
- .text.BootComCheckActivationRequest
- 0x080029e0 0xc0 ./boot.o
- 0x080029e0 BootComCheckActivationRequest
- .text.reset_handler
- 0x08002aa0 0x68 ./cstart.o
- 0x08002aa0 reset_handler
- .text.IrqInterruptEnable
- 0x08002b08 0x4 ./irq.o
- 0x08002b08 IrqInterruptEnable
- .text.LedInit 0x08002b0c 0x48 ./led.o
- 0x08002b0c LedInit
- .text.LedToggle
- 0x08002b54 0x84 ./led.o
- 0x08002b54 LedToggle
- .text.main 0x08002bd8 0x218 ./main.o
- 0x08002bd8 main
- .text.TimerDeinit
- 0x08002df0 0x10 ./timer.o
- 0x08002df0 TimerDeinit
- .text.TimerSet
- 0x08002e00 0xc ./timer.o
- 0x08002e00 TimerSet
- .text.TimerInit
- 0x08002e0c 0x3c ./timer.o
- 0x08002e0c TimerInit
- .text.TimerGet
- 0x08002e48 0xc ./timer.o
- 0x08002e48 TimerGet
- .text.TimerISRHandler
- 0x08002e54 0x14 ./timer.o
- 0x08002e54 TimerISRHandler
- .text.UartInit
- 0x08002e68 0xb4 ./uart.o
- 0x08002e68 UartInit
- .text.UartTxChar
- 0x08002f1c 0x3c ./uart.o
- 0x08002f1c UartTxChar
- .text.UartRxChar
- 0x08002f58 0x58 ./uart.o
- 0x08002f58 UartRxChar
- .text.UnusedISR
- 0x08002fb0 0x4 ./vectors.o
- 0x08002fb0 UnusedISR
- *(.rodata*)
- .rodata.str1.4
- 0x08002fb4 0x3d ./lib/stdio_mini.o
- 0x40 (size before relaxing)
- *fill* 0x08002ff1 0x3 00
- .rodata.base_X
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-.glue_7 0x08003158 0x0
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diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/bin/demoprog_olimex_stm32p103.srec b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/bin/demoprog_olimex_stm32p103.srec
deleted file mode 100644
index 88418ce9..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/bin/demoprog_olimex_stm32p103.srec
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diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/boot.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/boot.c
deleted file mode 100644
index 0c8de75e..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/boot.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/****************************************************************************************
-| Description: demo program bootloader interface source file
-| File Name: boot.c
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-** NAME: BootActivate
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Bootloader activation function.
-**
-****************************************************************************************/
-static void BootActivate(void)
-{
- void (*pEntryFromProgFnc)(void);
-
- /* stop the timer interrupt */
- TimerDeinit();
- /* set pointer to the address of function EntryFromProg in the bootloader. note that
- * 1 is added to this address to enable a switch from Thumb2 to Thumb mode
- */
- pEntryFromProgFnc = (void*)0x08000150 + 1;
- /* call EntryFromProg to activate the bootloader. */
- pEntryFromProgFnc();
-} /*** end of BootActivate ***/
-
-
-#if (BOOT_COM_UART_ENABLE > 0)
-/****************************************************************************************
-* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E
-****************************************************************************************/
-
-/****************************************************************************************
-** NAME: BootComInit
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Initializes the UART communication interface
-**
-****************************************************************************************/
-void BootComInit(void)
-{
- UartInit(BOOT_COM_UART_BAUDRATE);
-} /*** end of BootComInit ***/
-
-
-/****************************************************************************************
-** NAME: BootComCheckActivationRequest
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Receives the CONNECT request from the host, which indicates that the
-** bootloader should be activated and, if so, activates it.
-**
-****************************************************************************************/
-void BootComCheckActivationRequest(void)
-{
- static unsigned char xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1];
- static unsigned char xcpCtoRxLength;
- static unsigned char xcpCtoRxInProgress = 0;
- int ch;
-
- /* start of cto packet received? */
- if (xcpCtoRxInProgress == 0)
- {
- /* store the message length when received */
- ch = UartRxChar(0);
- if (ch != -1)
- {
- xcpCtoReqPacket[0] = (unsigned char)ch;
- /* indicate that a cto packet is being received */
- xcpCtoRxInProgress = 1;
-
- /* reset packet data count */
- xcpCtoRxLength = 0;
- }
- }
- else
- {
- /* store the next packet byte */
- ch = UartRxChar(0);
- if (ch != -1)
- {
- xcpCtoReqPacket[xcpCtoRxLength+1] = (unsigned char)ch;
- /* increment the packet data count */
- xcpCtoRxLength++;
-
- /* check to see if the entire packet was received */
- if (xcpCtoRxLength == xcpCtoReqPacket[0])
- {
- /* done with cto packet reception */
- xcpCtoRxInProgress = 0;
-
- /* check if this was an XCP CONNECT command */
- if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00))
- {
- /* connection request received so start the bootloader */
- BootActivate();
- }
- }
- }
- }
-} /*** end of BootComCheckActivationRequest ***/
-#endif /* BOOT_COM_UART_ENABLE > 0 */
-
-
-#if (BOOT_COM_CAN_ENABLE > 0)
-/****************************************************************************************
-* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E
-****************************************************************************************/
-
-/****************************************************************************************
-* Macro definitions
-****************************************************************************************/
-
-
-/****************************************************************************************
-* Type definitions
-****************************************************************************************/
-typedef struct t_can_bus_timing
-{
- unsigned char tseg1; /* CAN time segment 1 */
- unsigned char tseg2; /* CAN time segment 2 */
-} tCanBusTiming; /* bus timing structure type */
-
-
-/****************************************************************************************
-* Local constant declarations
-****************************************************************************************/
-/* According to the CAN protocol 1 bit-time can be made up of between 8..25 time quanta
- * (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC always being 1.
- * The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) * 100%. This array contains
- * possible and valid time quanta configurations with a sample point between 68..78%.
- */
-static const tCanBusTiming canTiming[] =
-{ /* TQ | TSEG1 | TSEG2 | SP */
- /* ------------------------- */
- { 5, 2 }, /* 8 | 5 | 2 | 75% */
- { 6, 2 }, /* 9 | 6 | 2 | 78% */
- { 6, 3 }, /* 10 | 6 | 3 | 70% */
- { 7, 3 }, /* 11 | 7 | 3 | 73% */
- { 8, 3 }, /* 12 | 8 | 3 | 75% */
- { 9, 3 }, /* 13 | 9 | 3 | 77% */
- { 9, 4 }, /* 14 | 9 | 4 | 71% */
- { 10, 4 }, /* 15 | 10 | 4 | 73% */
- { 11, 4 }, /* 16 | 11 | 4 | 75% */
- { 12, 4 }, /* 17 | 12 | 4 | 76% */
- { 12, 5 }, /* 18 | 12 | 5 | 72% */
- { 13, 5 }, /* 19 | 13 | 5 | 74% */
- { 14, 5 }, /* 20 | 14 | 5 | 75% */
- { 15, 5 }, /* 21 | 15 | 5 | 76% */
- { 15, 6 }, /* 22 | 15 | 6 | 73% */
- { 16, 6 }, /* 23 | 16 | 6 | 74% */
- { 16, 7 }, /* 24 | 16 | 7 | 71% */
- { 16, 8 } /* 25 | 16 | 8 | 68% */
-};
-
-
-/****************************************************************************************
-** NAME: CanGetSpeedConfig
-** PARAMETER: baud The desired baudrate in kbps. Valid values are 10..1000.
-** prescaler Pointer to where the value for the prescaler will be stored.
-** tseg1 Pointer to where the value for TSEG2 will be stored.
-** tseg2 Pointer to where the value for TSEG2 will be stored.
-** RETURN VALUE: 1 if the CAN bustiming register values were found, 0 otherwise.
-** DESCRIPTION: Search algorithm to match the desired baudrate to a possible bus
-** timing configuration.
-**
-****************************************************************************************/
-static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned short *prescaler,
- unsigned char *tseg1, unsigned char *tseg2)
-{
- unsigned char cnt;
-
- /* loop through all possible time quanta configurations to find a match */
- for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
- {
- if (((BOOT_CPU_SYSTEM_SPEED_KHZ/2) % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
- {
- /* compute the prescaler that goes with this TQ configuration */
- *prescaler = (BOOT_CPU_SYSTEM_SPEED_KHZ/2)/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
-
- /* make sure the prescaler is valid */
- if ( (*prescaler > 0) && (*prescaler <= 1024) )
- {
- /* store the bustiming configuration */
- *tseg1 = canTiming[cnt].tseg1;
- *tseg2 = canTiming[cnt].tseg2;
- /* found a good bus timing configuration */
- return 1;
- }
- }
- }
- /* could not find a good bus timing configuration */
- return 0;
-} /*** end of CanGetSpeedConfig ***/
-
-
-/****************************************************************************************
-** NAME: BootComInit
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Initializes the CAN communication interface
-**
-****************************************************************************************/
-void BootComInit(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure;
- CAN_InitTypeDef CAN_InitStructure;
- CAN_FilterInitTypeDef CAN_FilterInitStructure;
- unsigned short prescaler;
- unsigned char tseg1, tseg2;
-
- /* GPIO clock enable */
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
- /* Configure CAN pin: RX */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
- GPIO_Init(GPIOB, &GPIO_InitStructure);
- /* Configure CAN pin: TX */
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOB, &GPIO_InitStructure);
- /* Remap CAN1 pins to PortB */
- GPIO_PinRemapConfig(GPIO_Remap1_CAN1 , ENABLE);
- /* CAN1 Periph clock enable */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
- /* CAN register init */
- CAN_DeInit(CAN1);
- CAN_StructInit(&CAN_InitStructure);
- /* obtain the bittiming configuration for this baudrate */
- CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &tseg1, &tseg2);
- /* CAN controller init */
- CAN_InitStructure.CAN_TTCM = DISABLE;
- CAN_InitStructure.CAN_ABOM = DISABLE;
- CAN_InitStructure.CAN_AWUM = DISABLE;
- CAN_InitStructure.CAN_NART = DISABLE;
- CAN_InitStructure.CAN_RFLM = DISABLE;
- CAN_InitStructure.CAN_TXFP = DISABLE;
- CAN_InitStructure.CAN_Mode = CAN_Mode_Normal;
- /* CAN Baudrate init */
- CAN_InitStructure.CAN_SJW = CAN_SJW_1tq;
- CAN_InitStructure.CAN_BS1 = tseg1 - 1;
- CAN_InitStructure.CAN_BS2 = tseg2 - 1;
- CAN_InitStructure.CAN_Prescaler = prescaler;
- CAN_Init(CAN1, &CAN_InitStructure);
- /* CAN filter init - receive all messages */
- CAN_FilterInitStructure.CAN_FilterNumber = 0;
- CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask;
- CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit;
- CAN_FilterInitStructure.CAN_FilterIdHigh = 0x0000;
- CAN_FilterInitStructure.CAN_FilterIdLow = 0x0000;
- CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0x0000;
- CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0x0000;
- CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 0;
- CAN_FilterInitStructure.CAN_FilterActivation = ENABLE;
- CAN_FilterInit(&CAN_FilterInitStructure);
-} /*** end of BootComInit ***/
-
-
-/****************************************************************************************
-** NAME: BootComCheckActivationRequest
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Receives the CONNECT request from the host, which indicates that the
-** bootloader should be activated and, if so, activates it.
-**
-****************************************************************************************/
-void BootComCheckActivationRequest(void)
-{
- CanRxMsg RxMessage;
-
- /* check if a new message was received */
- if (CAN_MessagePending(CAN1, CAN_FIFO0) > 0)
- {
- /* receive the message */
- CAN_Receive(CAN1, CAN_FIFO0, &RxMessage);
- if (RxMessage.StdId == BOOT_COM_CAN_RX_MSG_ID)
- {
- /* check if this was an XCP CONNECT command */
- if ((RxMessage.Data[0] == 0xff) && (RxMessage.Data[1] == 0x00))
- {
- /* connection request received so start the bootloader */
- BootActivate();
- }
- }
- }
-} /*** end of BootComCheckActivationRequest ***/
-#endif /* BOOT_COM_CAN_ENABLE > 0 */
-
-
-/*********************************** end of boot.c *************************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/boot.h b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/boot.h
deleted file mode 100644
index 92789052..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/boot.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/****************************************************************************************
-| Description: demo program bootloader interface header file
-| File Name: boot.h
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-#ifndef BOOT_H
-#define BOOT_H
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-void BootComInit(void);
-void BootComCheckActivationRequest(void);
-
-
-#endif /* BOOT_H */
-/*********************************** end of boot.h *************************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/cstart.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/cstart.c
deleted file mode 100644
index b22b30be..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/cstart.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/****************************************************************************************
-| Description: Demo program C startup source file
-| File Name: cstart.c
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* External function protoypes
-****************************************************************************************/
-extern int main(void);
-
-
-/****************************************************************************************
-* External data declarations
-****************************************************************************************/
-/* these externals are declared by the linker */
-extern unsigned long _etext;
-extern unsigned long _data;
-extern unsigned long _edata;
-
-
-/****************************************************************************************
-** NAME: reset_handler
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Reset interrupt service routine. Configures the stack, initializes
-** RAM and jumps to function main.
-**
-****************************************************************************************/
-void reset_handler(void)
-{
- unsigned long *pSrc, *pDest;
-
- /* initialize stack pointer */
- __asm(" ldr r1, =_estack\n"
- " mov sp, r1");
- /* copy the data segment initializers from flash to SRAM */
- pSrc = &_etext;
- for(pDest = &_data; pDest < &_edata; )
- {
- *pDest++ = *pSrc++;
- }
- /* zero fill the bss segment. this is done with inline assembly since this will
- * clear the value of pDest if it is not kept in a register.
- */
- __asm(" ldr r0, =_bss\n"
- " ldr r1, =_ebss\n"
- " mov r2, #0\n"
- " .thumb_func\n"
- "zero_loop:\n"
- " cmp r0, r1\n"
- " it lt\n"
- " strlt r2, [r0], #4\n"
- " blt zero_loop");
- /* start the software application by calling its entry point */
- main();
-} /*** end of reset_handler ***/
-
-
-/************************************ end of cstart.c **********************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/header.h b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/header.h
deleted file mode 100644
index cc2e9522..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/header.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/****************************************************************************************
-| Description: generic header file
-| File Name: header.h
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-#ifndef HEADER_H
-#define HEADER_H
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "../Boot/config.h" /* bootloader configuration */
-#include "stm32f10x.h" /* STM32 register definitions */
-#include "stm32f10x_conf.h" /* STM32 peripheral drivers */
-#include "boot.h" /* bootloader interface driver */
-#include "irq.h" /* IRQ driver */
-#include "led.h" /* LED driver */
-#include "uart.h" /* UART driver */
-#include "timer.h" /* Timer driver */
-
-
-#endif /* HEADER_H */
-/*********************************** end of header.h ***********************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/ide/readme.txt b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/ide/readme.txt
deleted file mode 100644
index 9441d3f0..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/ide/readme.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Integrated Development Environment
-----------------------------------
-Eclipse IDE for C/C++ Developers (version 3.7) was used as the editor during the development of this software. It can be downloaded
-from http://www.eclipse.org.
-
-Plugins
--------
-The following plugins are required. Refer to the plugin's website for installation instructions:
-- GNU ARM Eclipse Plug-in (http://sourceforge.net/projects/gnuarmeclipse/)
-
-The following plugins are optional in case you can to use the terminal in Eclipse. The URL's are direct links to the update site for
-Eclipse's "Help->Install New Software..." menu item.
-- Target Management Terminal (http://download.eclipse.org/releases/indigo)
-- RXTX Ebd-Usr Runtime (http://rxtx.qbang.org/eclipse/)
-
-
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/irq.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/irq.c
deleted file mode 100644
index a5cd3cd8..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/irq.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/****************************************************************************************
-| Description: IRQ driver source file
-| File Name: irq.c
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* Local data definitions
-****************************************************************************************/
-static unsigned char interruptNesting = 0; /* used for global interrupt en/disable */
-
-
-/****************************************************************************************
-** NAME: IrqInterruptEnable
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Enables the generation IRQ interrupts. Typically called once during
-** software startup after completion of the initialization.
-**
-****************************************************************************************/
-void IrqInterruptEnable(void)
-{
- __enable_irq();
-} /*** end of IrqInterruptEnable ***/
-
-
-/****************************************************************************************
-** NAME: HwInterruptDisable
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Disables the generation IRQ interrupts and stores information on
-** whether or not the interrupts were already disabled before explicitly
-** disabling them with this function. Normally used as a pair together
-** with IrqInterruptRestore during a critical section.
-**
-****************************************************************************************/
-void IrqInterruptDisable(void)
-{
- if (interruptNesting == 0)
- {
- __disable_irq();
- }
- interruptNesting++;
-} /*** end of IrqInterruptDisable ***/
-
-
-/****************************************************************************************
-** NAME: IrqInterruptRestore
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Restore the generation IRQ interrupts to the setting it had prior to
-** calling IrqInterruptDisable. Normally used as a pair together with
-** IrqInterruptDisable during a critical section.
-**
-****************************************************************************************/
-void IrqInterruptRestore(void)
-{
- interruptNesting--;
- if (interruptNesting == 0)
- {
- __enable_irq();
- }
-} /*** end of IrqInterruptRestore ***/
-
-
-/*********************************** end of irq.c **************************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/irq.h b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/irq.h
deleted file mode 100644
index 9f12faf4..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/irq.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/****************************************************************************************
-| Description: IRQ driver header file
-| File Name: irq.h
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-#ifndef IRQ_H
-#define IRQ_H
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-void IrqInterruptEnable(void);
-void IrqInterruptDisable(void);
-void IrqInterruptRestore(void);
-
-
-#endif /* IRQ_H */
-/*********************************** end of irq.h **************************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/led.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/led.c
deleted file mode 100644
index 74c43174..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/led.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/****************************************************************************************
-| Description: LED driver source file
-| File Name: led.c
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* Macro definitions
-****************************************************************************************/
-#define LED_TOGGLE_MS (500) /* toggle interval time in milliseconds */
-
-
-/****************************************************************************************
-** NAME: LedInit
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Initializes the LED.
-**
-****************************************************************************************/
-void LedInit(void)
-{
- GPIO_InitTypeDef gpio_init;
-
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
- gpio_init.GPIO_Pin = GPIO_Pin_12;
- gpio_init.GPIO_Speed = GPIO_Speed_50MHz;
- gpio_init.GPIO_Mode = GPIO_Mode_Out_PP;
- GPIO_Init(GPIOC, &gpio_init);
-} /*** end of LedInit ***/
-
-
-/****************************************************************************************
-** NAME: LedToggle
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Toggles the LED at a fixed time interval.
-**
-****************************************************************************************/
-void LedToggle(void)
-{
- static unsigned char led_toggle_state = 0;
- static unsigned long timer_counter_last = 0;
- unsigned long timer_counter_now;
-
- /* check if toggle interval time passed */
- timer_counter_now = TimerGet();
- if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
- {
- /* not yet time to toggle */
- return;
- }
-
- /* determine toggle action */
- if (led_toggle_state == 0)
- {
- led_toggle_state = 1;
- /* turn the LED on */
- GPIO_ResetBits(GPIOC, GPIO_Pin_12);
- }
- else
- {
- led_toggle_state = 0;
- /* turn the LED off */
- GPIO_SetBits(GPIOC, GPIO_Pin_12);
- }
-
- /* store toggle time to determine next toggle interval */
- timer_counter_last = timer_counter_now;
-} /*** end of LedToggle ***/
-
-
-/*********************************** end of led.c **************************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/led.h b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/led.h
deleted file mode 100644
index f69b6a44..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/led.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/****************************************************************************************
-| Description: LED driver header file
-| File Name: led.h
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-#ifndef LED_H
-#define LED_H
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-void LedInit(void);
-void LedToggle(void);
-
-
-#endif /* LED_H */
-/*********************************** end of led.h **************************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdio_mini.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdio_mini.c
deleted file mode 100644
index 97ba4565..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdio_mini.c
+++ /dev/null
@@ -1,668 +0,0 @@
-/****************************************************************************************
-| Description: Standard I/O integer optimized library source file
-| The following functions are implemented:
-|
-| - int printf (const char *format, ...)
-| - int scanf(const char *fmt, ...)
-| File Name: stdio_mini.c
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include
-#include
-#include
-#include
-#include "../uart.h"
-
-
-/****************************************************************************************
-* Structure definitions
-****************************************************************************************/
-struct printf_conversion /* A printf() conversion. */
-{
- /* Flags. */
- enum
- {
- MINUS = 1 << 0, /* '-' */
- PLUS = 1 << 1, /* '+' */
- SPACE = 1 << 2, /* ' ' */
- POUND = 1 << 3, /* '#' */
- ZERO = 1 << 4, /* '0' */
- GROUP = 1 << 5 /* '\'' */
- }
- flags;
-
- /* Minimum field width. */
- int width;
-
- /* Numeric precision. -1 indicates no precision was specified. */
- int precision;
-
- /* Type of argument to format. */
- enum
- {
- CHAR = 1, /* hh */
- SHORT = 2, /* h */
- INT = 3, /* (none) */
- LONG = 5, /* l */
- }
- type;
-};
-
-
-struct integer_base
-{
- int base; /* Base. */
- const char *digits; /* Collection of digits. */
- int x; /* `x' character to use, for base 16 only. */
- int group; /* Number of digits to group with ' flag. */
-};
-
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-static void output_dup(char ch, size_t cnt);
-static void format_integer(unsigned long value, char is_signed, char negative,
- const struct integer_base *b,
- const struct printf_conversion *c);
-static const char *parse_conversion(const char *format, struct printf_conversion *c,
- va_list *args);
-static int libvprintf(const char *format, va_list args);
-
-
-/****************************************************************************************
-* Local constant declarations
-****************************************************************************************/
-static const struct integer_base base_d = {10, "0123456789", 0, 3};
-static const struct integer_base base_o = {8, "01234567", 0, 3};
-static const struct integer_base base_x = {16, "0123456789abcdef", 'x', 4};
-static const struct integer_base base_X = {16, "0123456789ABCDEF", 'X', 4};
-
-
-/****************************************************************************************
-* Local data declarations
-****************************************************************************************/
-static volatile unsigned int txcharcnt;
-
-
-/****************************************************************************************
-** NAME: puts
-** PARAMETER: character to write
-** RETURN VALUE: the character written.
-** DESCRIPTION: writes the string s and a newline to the terminal and returns a non-
-** negative value.
-**
-****************************************************************************************/
-int puts(const char *s)
-{
- while(*s != '\0')
- {
- UartTxChar(*s);
- s++;
- }
- UartTxChar('\n');
- UartTxChar('\r');
-
- return 0;
-} /*** end of puts ***/
-
-
-/****************************************************************************************
-** NAME: printf
-** PARAMETER: format string and specifiers
-** RETURN VALUE: number of printed characters.
-** DESCRIPTION: This is a minimal implementation of the STDIO ANSI-C library function
-** with support for the d,i,o,u,x,X format string specifiers. If this
-** library is linked before the standard ANSI-C library iwth STDIO, the
-** standard library functions are automatically overridden.
-**
-****************************************************************************************/
-int printf (const char *format, ...)
-{
- va_list args;
- int retval;
-
- va_start (args, format);
- retval = libvprintf (format, args);
- va_end (args);
-
- return retval;
-}
-
-
-/****************************************************************************************
-** NAME: scanf
-** PARAMETER: format string and specifiers
-** RETURN VALUE: number of conversions.
-** DESCRIPTION: This is a minimal implementation of the STDIO ANSI-C library function
-** with support for the d,u,o,x format string specifiers. If this
-** library is linked before the standard ANSI-C library iwth STDIO, the
-** standard library functions are automatically overridden.
-**
-****************************************************************************************/
-int scanf(const char *fmt, ...)
-{
- char *s0, c;
- char buf[64];
- char *s = &buf[0];
- va_list ap;
- long L, *Lp;
- int i, *ip, rc = 0;
-
- do
- {
- c = UartRxChar(1); /* read byte */
- UartTxChar(c);
- *s++ = c; /* store in buf */
- }
- while((c != '\r') && (c != '\n')); /* read bytes until enter is pressed */
- *s = '\0'; /* add string termination */
- s = &buf[0]; /* set pointer to start of buf for further processing */
-
- va_start(ap, fmt);
-
- for( ; ; )
- {
- for(;;)
- {
- switch(i = *(unsigned char *)fmt++)
- {
- case 0:
- goto done;
- case '%':
- break;
- default:
- if (i <= ' ')
- {
- while(*s <= ' ')
- if (!*s++)
- goto done;
- }
- else if (*s++ != i)
- goto done;
- continue;
- }
- break;
- }
-
- switch(*fmt++)
- {
- case 'l':
- if (*fmt == 'd')
- {
- fmt++;
- Lp = va_arg(ap, long*);
- L = strtol(s0 = s, &s, 10);
- if (s > s0)
- {
- rc++;
- *Lp = L;
- continue;
- }
- }
- else if (*fmt == 'u')
- {
- fmt++;
- Lp = (long*)va_arg(ap, unsigned long*);
- L = strtol(s0 = s, &s, 10);
- if (s > s0)
- {
- rc++;
- *Lp = L;
- continue;
- }
- }
- else if (*fmt == 'x')
- {
- fmt++;
- Lp = (long*)va_arg(ap, unsigned long*);
- L = strtol(s0 = s, &s, 16);
- if (s > s0)
- {
- rc++;
- *Lp = L;
- continue;
- }
- }
- else if (*fmt == 'o')
- {
- fmt++;
- Lp = (long*)va_arg(ap, unsigned long*);
- L = strtol(s0 = s, &s, 8);
- if (s > s0)
- {
- rc++;
- *Lp = L;
- continue;
- }
- }
- else
- goto error;
- goto done;
- case 'd':
- ip = va_arg(ap, int*);
- L = strtol(s0 = s, &s, 10);
- if (s > s0)
- {
- rc++;
- *ip = (int)L;
- continue;
- }
- goto done;
- case 'u':
- ip = (int*)va_arg(ap, unsigned int*);
- L = strtoul(s0 = s, &s, 10);
- if (s > s0)
- {
- rc++;
- *ip = (int)L;
- continue;
- }
- goto done;
- case 'x':
- ip = va_arg(ap, int*);
- L = strtol(s0 = s, &s, 16);
- if (s > s0)
- {
- rc++;
- *ip = (int)L;
- continue;
- }
- goto done;
- case 'o':
- ip = va_arg(ap, int*);
- L = strtol(s0 = s, &s, 8);
- if (s > s0)
- {
- rc++;
- *ip = (int)L;
- continue;
- }
- goto done;
- default:
- goto error; /* wrong format */
- }
- }
-
- done:
- va_end(ap);
- return rc;
-
- error:
- va_end(ap);
- return 0;
-
-} /*** end of scanf ***/
-
-
-/****************************************************************************************
-** NAME: output_dup
-** PARAMETER: character to output and how many times.
-** RETURN VALUE: none
-** DESCRIPTION: writes ch to output cnt times.
-**
-****************************************************************************************/
-static void output_dup(char ch, size_t cnt)
-{
- while (cnt-- > 0)
- {
- UartTxChar(ch);
- txcharcnt++;
- }
-} /*** end of output_dup ***/
-
-
-/****************************************************************************************
-** NAME: format_integer
-** PARAMETER: all necessary conversion information.
-** RETURN VALUE: none
-** DESCRIPTION: Formats an integer to a string and transmits each character through
-** the terminal communication interface.
-**
-****************************************************************************************/
-static void format_integer(unsigned long value, char is_signed, char negative,
- const struct integer_base *b,
- const struct printf_conversion *c)
-{
- char buf[64], *cp; /* Buffer and current position. */
- int x; /* `x' character to use or 0 if none. */
- int sign; /* Sign character or 0 if none. */
- int precision; /* Rendered precision. */
- int pad_cnt; /* # of pad characters to fill field width. */
- int digit_cnt; /* # of digits output so far. */
-
- /* Determine sign character, if any.
- An unsigned conversion will never have a sign character,
- even if one of the flags requests one. */
- sign = 0;
- if (is_signed)
- {
- if (c->flags & PLUS)
- sign = negative ? '-' : '+';
- else if (c->flags & SPACE)
- sign = negative ? '-' : ' ';
- else if (negative)
- sign = '-';
- }
-
- /* Determine whether to include `0x' or `0X'.
- It will only be included with a hexadecimal conversion of a
- nonzero value with the # flag. */
- x = (c->flags & POUND) && value ? b->x : 0;
-
- /* Accumulate digits into buffer.
- This algorithm produces digits in reverse order, so later we
- will output the buffer's content in reverse. */
- cp = buf;
- digit_cnt = 0;
- while (value > 0)
- {
- if ((c->flags & GROUP) && digit_cnt > 0 && digit_cnt % b->group == 0)
- *cp++ = ',';
- *cp++ = b->digits[value % b->base];
- value /= b->base;
- digit_cnt++;
- }
-
- /* Append enough zeros to match precision.
- If requested precision is 0, then a value of zero is
- rendered as a null string, otherwise as "0".
- If the # flag is used with base 8, the result must always
- begin with a zero. */
- precision = c->precision < 0 ? 1 : c->precision;
- while (cp - buf < precision && cp < buf + sizeof buf - 1)
- *cp++ = '0';
- if ((c->flags & POUND) && b->base == 8 && (cp == buf || cp[-1] != '0'))
- *cp++ = '0';
-
- /* Calculate number of pad characters to fill field width. */
- pad_cnt = c->width - (cp - buf) - (x ? 2 : 0) - (sign != 0);
- if (pad_cnt < 0)
- pad_cnt = 0;
-
- /* Do output. */
- if ((c->flags & (MINUS | ZERO)) == 0)
- output_dup (' ', pad_cnt);
- if (sign)
- {
- UartTxChar(sign);
- txcharcnt++;
- }
- if (x)
- {
- UartTxChar ('0');
- txcharcnt++;
- UartTxChar(x);
- txcharcnt++;
- }
- if (c->flags & ZERO)
- output_dup ('0', pad_cnt);
- while (cp > buf)
- {
- UartTxChar (*--cp);
- txcharcnt++;
- }
- if (c->flags & MINUS)
- output_dup (' ', pad_cnt);
-} /*** end of format_integer ***/
-
-
-/****************************************************************************************
-** NAME: parse_conversion
-** PARAMETER: all necessary parsing information and the format string.
-** RETURN VALUE: pointer to the unchanged format string.
-** DESCRIPTION: Parses the actual printf format string for all arguments.
-**
-****************************************************************************************/
-static const char *parse_conversion(const char *format, struct printf_conversion *c,
- va_list *args)
-{
- /* Parse flag characters. */
- c->flags = 0;
- for (;;)
- {
- switch (*format++)
- {
- case '-':
- c->flags |= MINUS;
- break;
- case '+':
- c->flags |= PLUS;
- break;
- case ' ':
- c->flags |= SPACE;
- break;
- case '#':
- c->flags |= POUND;
- break;
- case '0':
- c->flags |= ZERO;
- break;
- case '\'':
- c->flags |= GROUP;
- break;
- default:
- format--;
- goto not_a_flag;
- }
- }
- not_a_flag:
- if (c->flags & MINUS)
- c->flags &= ~ZERO;
- if (c->flags & PLUS)
- c->flags &= ~SPACE;
-
- /* Parse field width. */
- c->width = 0;
- if (*format == '*')
- {
- format++;
- c->width = va_arg (*args, int);
- }
- else
- {
- for (; isdigit ((int)*format); format++)
- c->width = c->width * 10 + *format - '0';
- }
- if (c->width < 0)
- {
- c->width = -c->width;
- c->flags |= MINUS;
- }
-
- /* Parse precision. */
- c->precision = -1;
- if (*format == '.')
- {
- format++;
- if (*format == '*')
- {
- format++;
- c->precision = va_arg (*args, int);
- }
- else
- {
- c->precision = 0;
- for (; isdigit ((int)*format); format++)
- c->precision = c->precision * 10 + *format - '0';
- }
- if (c->precision < 0)
- c->precision = -1;
- }
- if (c->precision >= 0)
- c->flags &= ~ZERO;
-
- /* Parse type. */
- c->type = INT;
- switch (*format++)
- {
- case 'h':
- if (*format == 'h')
- {
- format++;
- c->type = CHAR;
- }
- else
- c->type = SHORT;
- break;
-
- case 'l':
- c->type = LONG;
- break;
-
- default:
- format--;
- break;
- }
-
- return format;
-} /*** end of parse_conversion ***/
-
-
-/****************************************************************************************
-** NAME: libvprintf
-** PARAMETER: format string and argument list.
-** RETURN VALUE: number of printed characters.
-** DESCRIPTION: low level virtual library printf function.
-**
-****************************************************************************************/
-static int libvprintf(const char *format, va_list args)
-{
- for (; *format != '\0'; format++)
- {
- struct printf_conversion c;
-
- /* Literally copy non-conversions to output. */
- if (*format != '%')
- {
- UartTxChar (*format);
- txcharcnt++;
- continue;
- }
- format++;
-
- /* %% => %. */
- if (*format == '%')
- {
- UartTxChar (*format);
- txcharcnt++;
- continue;
- }
-
- /* Parse conversion specifiers. */
- format = parse_conversion (format, &c, &args);
-
- /* Do conversion. */
- switch (*format)
- {
- case 'd':
- case 'i':
- {
- /* Signed integer conversions. */
- signed long value;
-
- switch (c.type)
- {
- case CHAR:
- value = (signed char) va_arg (args, int);
- break;
- case SHORT:
- value = (short) va_arg (args, int);
- break;
- case INT:
- value = va_arg (args, int);
- break;
- case LONG:
- value = va_arg (args, long);
- break;
- default:
- value = 0;
- break;
- }
-
- format_integer (value < 0 ? -value : value,
- 1, value < 0, &base_d, &c);
- }
- break;
-
- case 'o':
- case 'u':
- case 'x':
- case 'X':
- {
- /* Unsigned integer conversions. */
- unsigned long value;
- const struct integer_base *b;
-
- switch (c.type)
- {
- case CHAR:
- value = (unsigned char) va_arg (args, unsigned);
- break;
- case SHORT:
- value = (unsigned short) va_arg (args, unsigned);
- break;
- case INT:
- value = va_arg (args, unsigned);
- break;
- case LONG:
- value = va_arg (args, unsigned long);
- break;
- default:
- value = 0;
- break;
- }
-
- switch (*format)
- {
- case 'o': b = &base_o; break;
- case 'u': b = &base_d; break;
- case 'x': b = &base_x; break;
- case 'X': b = &base_X; break;
- default: b = &base_d; break;
- }
-
- format_integer (value, 0, 0, b, &c);
- }
- break;
-
- default:
- break;
- }
- }
- return txcharcnt;
-} /*** end of libvprintf ***/
-
-
-/************************************ end of stdio.c ***********************************/
-
-
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c
deleted file mode 100644
index 56fddc52..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c
+++ /dev/null
@@ -1,784 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.c
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
- mrs r0, psp
- bx lr
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
- msr psp, r0
- bx lr
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
- mrs r0, msp
- bx lr
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
- msr msp, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
- clrex
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t __get_BASEPRI(void)
-{
- mrs r0, basepri
- bx lr
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
- msr basepri, r0
- bx lr
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
- mrs r0, primask
- bx lr
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
- msr primask, r0
- bx lr
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t __get_FAULTMASK(void)
-{
- mrs r0, faultmask
- bx lr
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
- msr faultmask, r0
- bx lr
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
- mrs r0, control
- bx lr
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
- msr control, r0
- bx lr
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- __ASM("mrs r0, psp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM("msr psp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- __ASM("mrs r0, msp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM("msr msp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- __ASM("rev16 r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- __ASM("rbit r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- __ASM("ldrexb r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- __ASM("ldrexh r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- __ASM("ldrex r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- __ASM("strexb r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- __ASM("strexh r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- __ASM("strex r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, psp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, msp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- uint8_t result=0;
-
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- uint16_t result=0;
-
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h
deleted file mode 100644
index 2b6b51a7..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h
+++ /dev/null
@@ -1,1818 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CM3_CORE_H__
-#define __CM3_CORE_H__
-
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
- *
- * List of Lint messages which will be suppressed and not shown:
- * - Error 10: \n
- * register uint32_t __regBasePri __asm("basepri"); \n
- * Error 10: Expecting ';'
- * .
- * - Error 530: \n
- * return(__regBasePri); \n
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized
- * .
- * - Error 550: \n
- * __regBasePri = (basePri & 0x1ff); \n
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed
- * .
- * - Error 754: \n
- * uint32_t RESERVED0[24]; \n
- * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced
- * .
- * - Error 750: \n
- * #define __CM3_CORE_H__ \n
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
- * .
- * - Error 528: \n
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
- * .
- * - Error 751: \n
- * } InterruptType_Type; \n
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
- * .
- * Note: To re-enable a Message, insert a space before 'lint' *
- *
- */
-
-/*lint -save */
-/*lint -e10 */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core registers and bitfields
- - Cortex-M core peripheral base address
- @{
- */
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex core */
-
-#include /* Include standard types */
-
-#if defined (__ICCARM__)
- #include /* IAR Intrinsics */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
-#endif
-
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
-#else
- #define __I volatile const /*!< defines 'read only' permissions */
-#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- ******************************************************************************/
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
- @{
-*/
-
-
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
- @{
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
-} NVIC_Type;
-/*@}*/ /* end of group CMSIS_CM3_NVIC */
-
-
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
- memory mapped structure for System Control Block (SCB)
- @{
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-/*@}*/ /* end of group CMSIS_CM3_SCB */
-
-
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
- memory mapped structure for SysTick
- @{
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */
-
-
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
- memory mapped structure for Instrumentation Trace Macrocell (ITM)
- @{
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-/*@}*/ /* end of group CMSIS_CM3_ITM */
-
-
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
- memory mapped structure for Interrupt Type
- @{
- */
-typedef struct
-{
- uint32_t RESERVED0;
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
-#else
- uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
-
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
-
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
- memory mapped structure for Memory Protection Unit (MPU)
- @{
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@}*/ /* end of group CMSIS_CM3_MPU */
-#endif
-
-
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
- memory mapped structure for Core Debug Register
- @{
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
-
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
-
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_register */
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq __enable_fiq
-#define __disable_fault_irq __disable_fiq
-
-#define __NOP __nop
-#define __WFI __wfi
-#define __WFE __wfe
-#define __SEV __sev
-#define __ISB() __isb(0)
-#define __DSB() __dsb(0)
-#define __DMB() __dmb(0)
-#define __REV __rev
-#define __RBIT __rbit
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
-#define __STREXB(value, ptr) __strex(value, ptr)
-#define __STREXH(value, ptr) __strex(value, ptr)
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-extern void __CLREX(void);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else /* (__ARMCC_VERSION >= 400000) */
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#define __CLREX __clrex
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-static __INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & 1);
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
-
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
-static __INLINE void __WFI() { __ASM ("wfi"); }
-static __INLINE void __WFE() { __ASM ("wfe"); }
-static __INLINE void __SEV() { __ASM ("sev"); }
-static __INLINE void __CLREX() { __ASM ("clrex"); }
-
-/* intrinsic void __ISB(void) */
-/* intrinsic void __DSB(void) */
-/* intrinsic void __DMB(void) */
-/* intrinsic void __set_PRIMASK(); */
-/* intrinsic void __get_PRIMASK(); */
-/* intrinsic void __set_FAULTMASK(); */
-/* intrinsic void __get_FAULTMASK(); */
-/* intrinsic uint32_t __REV(uint32_t value); */
-/* intrinsic uint32_t __REVSH(uint32_t value); */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
-/* intrinsic unsigned long __LDREX(unsigned long *); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __NOP() { __ASM volatile ("nop"); }
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }
-static __INLINE void __SEV() { __ASM volatile ("sev"); }
-static __INLINE void __ISB() { __ASM volatile ("isb"); }
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
- Core Function Interface containing:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Reset Functions
-*/
-/*@{*/
-
-/* ########################## NVIC functions #################################### */
-
-/**
- * @brief Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param PriorityGroup is priority grouping field
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-/**
- * @brief Get the Priority Grouping from NVIC Interrupt Controller
- *
- * @return priority grouping field
- *
- * Get the priority grouping from NVIC Interrupt Controller.
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-}
-
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- *
- * @param IRQn The positive number of the external interrupt to enable
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-/**
- * @brief Disable the interrupt line for external interrupt specified
- *
- * @param IRQn The positive number of the external interrupt to disable
- *
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-/**
- * @brief Read the interrupt pending bit for a device specific interrupt source
- *
- * @param IRQn The number of the device specifc interrupt
- * @return 1 = interrupt pending, 0 = interrupt not pending
- *
- * Read the pending register in NVIC and return 1 if its status is pending,
- * otherwise it returns 0
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-/**
- * @brief Set the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for set pending
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-/**
- * @brief Clear the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for clear pending
- *
- * Clear the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-/**
- * @brief Read the active bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for read active bit
- * @return 1 = interrupt active, 0 = interrupt not active
- *
- * Read the active register in NVIC and returns 1 if its status is active,
- * otherwise it returns 0.
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-/**
- * @brief Set the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for set priority
- * @param priority The priority to set
- *
- * Set the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
-}
-
-/**
- * @brief Read the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for get priority
- * @return The priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/**
- * @brief Encode the priority for an interrupt
- *
- * @param PriorityGroup The used priority group
- * @param PreemptPriority The preemptive priority value (starting from 0)
- * @param SubPriority The sub priority value (starting from 0)
- * @return The encoded priority for the interrupt
- *
- * Encode the priority for an interrupt with the given priority group,
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The returned priority value can be used for NVIC_SetPriority(...) function
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
- );
-}
-
-
-/**
- * @brief Decode the priority of an interrupt
- *
- * @param Priority The priority for the interrupt
- * @param PriorityGroup The used priority group
- * @param pPreemptPriority The preemptive priority value (starting from 0)
- * @param pSubPriority The sub priority value (starting from 0)
- *
- * Decode an interrupt priority value with the given priority group to
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The priority value can be retrieved with NVIC_GetPriority(...) function
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
-}
-
-
-
-/* ################################## SysTick function ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/**
- * @brief Initialize and start the SysTick counter and its interrupt.
- *
- * @param ticks number of ticks between two interrupts
- * @return 1 = failed, 0 = successful
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate
- * periodical interrupts.
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-
-
-
-/* ################################## Reset function ############################################ */
-
-/**
- * @brief Initiate a system reset request.
- *
- * Initiate a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
- Core Debug Interface containing:
- - Core Debug Receive / Transmit Functions
- - Core Debug Defines
- - Core Debug Variables
-*/
-/*@{*/
-
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/**
- * @brief Outputs a character via the ITM channel 0
- *
- * @param ch character to output
- * @return character to output
- *
- * The function outputs a character via the ITM channel 0.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-
-/**
- * @brief Inputs a character via variable ITM_RxBuffer
- *
- * @return received character, -1 = no character received
- *
- * The function inputs a character via variable ITM_RxBuffer.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
- */
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- * @brief Check if a character via variable ITM_RxBuffer is available
- *
- * @return 1 = character available, 0 = no character available
- *
- * The function checks variable ITM_RxBuffer whether a character is available or not.
- * The function returns '1' if a character is available and '0' if no character is available.
- */
-static __INLINE int ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */
-
-#endif /* __CM3_CORE_H__ */
-
-/*lint -restore */
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html
deleted file mode 100644
index b80f38df..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html
+++ /dev/null
@@ -1,284 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-Release Notes for STM32F10x CMSIS
-
-
-
-
-
-
-
- All
-STM32 devices definitions are commented by default. User has to select the
-appropriate device before starting else an error will be signaled on compile
-time.
-
Add new IRQs definitons inside the IRQn_Type enumeration for STM23 High-density Value line devices.
-
"bool" type removed.
-
-
STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:system_stm32f10x.h and system_stm32f10x.c
-
-
-
"system_stm32f10x.c" moved to to "STM32F10x_StdPeriph_Template" directory. This file is also moved to each example directory under "STM32F10x_StdPeriph_Examples".
-
-
SystemInit_ExtMemCtl() function: update to support High-density Value line devices.
-
Add "VECT_TAB_SRAM" inside "system_stm32f10x.c"
-to select if the user want to place the Vector Table in internal SRAM.
-An additional define is also to specify the Vector Table offset "VECT_TAB_OFFSET".
-
Update
-the stm32f10x.h file to support new Value line devices features: CEC
-peripheral, new General purpose timers TIM15, TIM16 and TIM17.
-
Peripherals Bits definitions updated to be in line with Value line devices available features.
-
-
HSE_Value,
-HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE,
-HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy
-purposes.
-
-
-
STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:system_stm32f10x.h and system_stm32f10x.c
-
-
-
SystemFrequency variable name changed to SystemCoreClock
-
-
Default
- SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.
-
-
All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.
-
-
Additional function void SystemCoreClockUpdate (void) is provided.
-
Add new
-startup files for STM32 Low-density Value line devices:
- startup_stm32f10x_ld_vl.s
-
Add new startup
-files for STM32 Medium-density Value line devices:
- startup_stm32f10x_md_vl.s
-
SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.
-To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file
-
-
GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.
-
-
-
-
-
-
-
-
License
-
The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.
-
THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS.
-
-
-
-
For
-complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers
-visit www.st.com/STM32
-
-
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h
deleted file mode 100644
index af0c7c9a..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h
+++ /dev/null
@@ -1,8336 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x.h
- * @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
- * This file contains all the peripheral register's definitions, bits
- * definitions and memory mapping for STM32F10x Connectivity line,
- * High density, High density value line, Medium density,
- * Medium density Value line, Low density, Low density Value line
- * and XL-density devices.
- *
- * The file is the unique include file that the application programmer
- * is using in the C source code, usually in main.c. This file contains:
- * - Configuration section that allows to select:
- * - The device used in the target application
- * - To use or not the peripheral’s drivers in application code(i.e.
- * code will be based on direct access to peripheral’s registers
- * rather than drivers API), this option is controlled by
- * "#define USE_STDPERIPH_DRIVER"
- * - To change few application-specific parameters such as the HSE
- * crystal frequency
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral’s registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- *
- The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
- the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
- 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
- communication channels are used by CMSIS to output the following information:
-
-
-
ITM Channel 0: used for printf-style output via the debug interface.
-
ITM Channel 31: is reserved for RTOS kernel awareness debugging.
-
-
-
Debug IN / OUT functions
-
CMSIS provides following debug functions:
-
-
ITM_SendChar (uses ITM channel 0)
-
ITM_ReceiveChar (uses global variable)
-
ITM_CheckChar (uses global variable)
-
-
-
ITM_SendChar
-
- ITM_SendChar is used to transmit a character over ITM channel 0 from
- the microcontroller system to the debug system.
- Only a 8 bit value is transmitted.
-
- ITM communication channel is only capable for OUT direction. For IN direction
- a globel variable is used. A simple mechansim detects if a character is received.
- The project to test need to be build with debug information.
-
-
-
- The globale variable ITM_RxBuffer is used to transmit a 8 bit value from debug system
- to microcontroller system. ITM_RxBuffer is 32 bit wide to enshure a proper handshake.
-
-
-extern volatile int ITM_RxBuffer; /* variable to receive characters */
-
-
- A dedicated bit pattern is used to determin if ITM_RxBuffer is empty
- or contains a valid value.
-
-
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
-
-
- ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking.
- It returns the received character or '-1' if no character was available.
-
-
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-
ITM_CheckChar
-
- ITM_CheckChar is used to check if a character is received.
-
-
-static __INLINE int ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-
-
ITM Debug Support in uVision
-
- uVision uses in a debug session the Debug (printf) Viewer window to
- display the debug data.
-
-
Direction microcontroller system -> uVision:
-
-
- Characters received via ITM communication channel 0 are written in a printf style
- to Debug (printf) Viewer window.
-
-
-
-
Direction uVision -> microcontroller system:
-
-
Check if ITM_RxBuffer variable is available (only performed once).
-
Read character from Debug (printf) Viewer window.
-
If ITM_RxBuffer empty write character to ITM_RxBuffer.
-
-
-
Note
-
-
Current solution does not use a buffer machanism for trasmitting the characters.
-
-
-
-
RTX Kernel awareness in uVision
-
- uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
- No format overhead is necessary.
- uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
- to ITM communication channel 31.
-
-
-
Following RTX events are traced:
-
-
Task Create / Delete event
-
-
32 bit access. Task start address is transmitted
-
16 bit access. Task ID and Create/Delete flag are transmitted
- High byte holds Create/Delete flag, Low byte holds TASK ID.
-
-
-
-
Task switch event
-
-
8 bit access. Task ID of current task is transmitted
-
-
-
-
-
Note
-
-
Other RTOS information could be retrieved via memory read access in a polling mode manner.
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CMSIS_changes.htm b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CMSIS_changes.htm
deleted file mode 100644
index 162ffcc9..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/CMSIS_changes.htm
+++ /dev/null
@@ -1,320 +0,0 @@
-
-
-
-CMSIS Changes
-
-
-
-
-
-
-
-
-
Changes to CMSIS version V1.20
-
-
-
-
1. Removed CMSIS Middelware packages
-
- CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
-
-
-
2. SystemFrequency renamed to SystemCoreClock
-
- The variable name SystemCoreClock is more precise than SystemFrequency
- because the variable holds the clock value at which the core is running.
-
-
-
3. Changed startup concept
-
- The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
- from main) has the weakness that it does not work for controllers which need a already
- configuerd clock system to configure the external memory controller.
-
-
-
Changed startup concept
-
-
- SystemInit() is called from startup file before premain.
-
-
- SystemInit() configures the clock system and also configures
- an existing external memory controller.
-
-
- SystemInit() must not use global variables.
-
-
- SystemCoreClock is initialized with a correct predefined value.
-
-
- Additional function void SystemCoreClockUpdate (void) is provided.
- SystemCoreClockUpdate() updates the variable SystemCoreClock
- and must be called whenever the core clock is changed.
- SystemCoreClockUpdate() evaluates the clock register settings and calculates
- the current core clock.
-
-
-
-
-
4. Advanced Debug Functions
-
- ITM communication channel is only capable for OUT direction. To allow also communication for
- IN direction a simple concept is provided.
-
-
-
- Global variable volatile int ITM_RxBuffer used for IN data.
-
-
- Function int ITM_CheckChar (void) checks if a new character is available.
-
-
- Function int ITM_ReceiveChar (void) retrieves the new character.
-
-
-
-
- For detailed explanation see file CMSIS debug support.htm.
-
-
-
-
5. Core Register Bit Definitions
-
- Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
- defines correspond with the Cortex-M Technical Reference Manual.
-
- The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges
- that are faced when software components are deployed to physical microcontroller devices based on a
- Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M
- processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation
- with various silicon and software vendors and provides a common approach to interface to peripherals,
- real-time operating systems, and middleware components.
-
-
-
ARM provides as part of the CMSIS the following software layers that are
-available for various compiler implementations:
-
-
Core Peripheral Access Layer: contains name definitions,
- address definitions and helper functions to
- access core registers and peripherals. It defines also a device
- independent interface for RTOS Kernels that includes debug channel
- definitions.
-
-
-
These software layers are expanded by Silicon partners with:
-
-
Device Peripheral Access Layer: provides definitions
- for all device peripherals
-
Access Functions for Peripherals (optional): provides
- additional helper functions for peripherals
-
-
-
CMSIS defines for a Cortex-M Microcontroller System:
-
-
A common way to access peripheral registers
- and a common way to define exception vectors.
-
The register names of the Core
- Peripherals andthe names of the Core
- Exception Vectors.
-
An device independent interface for RTOS Kernels including a debug
- channel.
-
-
-
- By using CMSIS compliant software components, the user can easier re-use template code.
- CMSIS is intended to enable the combination of software components from multiple middleware vendors.
-
-
-
Coding Rules and Conventions
-
-
- The following section describes the coding rules and conventions used in the CMSIS
- implementation. It contains also information about data types and version number information.
-
-
-
Essentials
-
-
The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations,
- there are disable and enable sequences for PC-LINT inserted.
-
ANSI standard data types defined in the ANSI C header file
- <stdint.h> are used.
-
#define constants that include expressions must be enclosed by
- parenthesis.
-
Variables and parameters have a complete data type.
-
All functions in the Core Peripheral Access Layer are
- re-entrant.
-
The Core Peripheral Access Layer has no blocking code
- (which means that wait/query loops are done at other software layers).
-
For each exception/interrupt there is definition for:
-
-
an exception/interrupt handler with the postfix _Handler
- (for exceptions) or _IRQHandler (for interrupts).
-
a default exception/interrupt handler (weak definition) that contains an endless loop.
-
a #define of the interrupt number with the postfix _IRQn.
-
-
-
-
Recommendations
-
-
The CMSIS recommends the following conventions for identifiers.
-
-
CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
-
CamelCase names to identify peripherals access functions and interrupts.
-
PERIPHERAL_ prefix to identify functions that belong to specify peripherals.
-
Doxygen comments for all functions are included as described under Function Comments below.
-
-
-Comments
-
-
-
Comments use the ANSI C90 style (/* comment */) or C++ style
- (// comment). It is assumed that the programming tools support today
- consistently the C++ comment style.
-
Function Comments provide for each function the following information:
-
-
one-line brief function overview.
-
detailed parameter explanation.
-
detailed information about return values.
-
detailed description of the actual function.
-
-
Doxygen Example:
-
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- * @param IRQn interrupt number that specifies the interrupt
- * @return none.
- * Enable the specified interrupt in the NVIC Interrupt Controller.
- * Other settings of the interrupt such as priority are not affected.
- */
-
-
-
-
Data Types and IO Type Qualifiers
-
-
- The Cortex-M HAL uses the standard types from the standard ANSI C header file
- <stdint.h>. IO Type Qualifiers are used to specify the access
- to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of
- debug information of peripheral registers.
-
-
-
-
-
-
IO Type Qualifier
-
#define
-
Description
-
-
-
__I
-
volatile const
-
Read access only
-
-
-
__O
-
volatile
-
Write access only
-
-
-
__IO
-
volatile
-
Read and write access
-
-
-
-
-
CMSIS Version Number
-
- File core_cm3.h contains the version number of the CMSIS with the following define:
-
-
-
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */
-#define __CM3_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)
-
-
- File core_cm0.h contains the version number of the CMSIS with the following define:
-
-
-
-#define __CM0_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */
-#define __CM0_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)
-
-
-
CMSIS Cortex Core
-
- File core_cm3.h contains the type of the CMSIS Cortex-M with the following define:
-
-
-
-#define __CORTEX_M (0x03)
-
-
- File core_cm0.h contains the type of the CMSIS Cortex-M with the following define:
-
-
-
-#define __CORTEX_M (0x00)
-
-
-
CMSIS Files
-
- This section describes the Files provided in context with the CMSIS to access the Cortex-M
- hardware and peripherals.
-
-
-
-
-
-
File
-
Provider
-
Description
-
-
-
device.h
-
Device specific (provided by silicon partner)
-
Defines the peripherals for the actual device. The file may use
- several other include files to define the peripherals of the actual device.
-
-
-
core_cm0.h
-
ARM (for RealView ARMCC, IAR, and GNU GCC)
-
Defines the core peripherals for the Cortex-M0 CPU and core peripherals.
-
-
-
core_cm3.h
-
ARM (for RealView ARMCC, IAR, and GNU GCC)
-
Defines the core peripherals for the Cortex-M3 CPU and core peripherals.
-
-
-
core_cm0.c
-
ARM (for RealView ARMCC, IAR, and GNU GCC)
-
Provides helper functions that access core registers.
-
-
-
core_cm3.c
-
ARM (for RealView ARMCC, IAR, and GNU GCC)
-
Provides helper functions that access core registers.
-
-
-
startup_device
-
ARM (adapted by compiler partner / silicon partner)
-
Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table
-
-
-
system_device
-
ARM (adapted by silicon partner)
-
Provides a device specific configuration file for the device. It configures the device initializes
- typically the oscillator (PLL) that is part of the microcontroller device
-
-
-
-
-
device.h
-
-
- The file device.h is provided by the silicon vendor and is the
- central include file that the application programmer is using in
- the C source code. This file contains:
-
-
-
-
Interrupt Number Definition: provides interrupt numbers
- (IRQn) for all core and device specific exceptions and interrupts.
-
-
-
Configuration for core_cm0.h / core_cm3.h: reflects the
- actual configuration of the Cortex-M processor that is part of the actual
- device. As such the file core_cm0.h / core_cm3.h is included that
- implements access to processor registers and core peripherals.
-
-
-
Device Peripheral Access Layer: provides definitions
- for all device peripherals. It contains all data structures and the address
- mapping for the device specific peripherals.
-
-
Access Functions for Peripherals (optional): provides
- additional helper functions for peripherals that are useful for programming
- of these peripherals. Access Functions may be provided as inline functions
- or can be extern references to a device specific library provided by the
- silicon vendor.
-
-
-
-
Interrupt Number Definition
-
-
To access the device specific interrupts the device.h file defines IRQn
-numbers for the complete device using a enum typedef as shown below:
- The Cortex-M core configuration options which are defined for each device implementation. Some
- configuration options are reflected in the CMSIS layer using the #define settings described below.
-
-
- To access core peripherals file device.h includes file core_cm0.h / core_cm3.h.
- Several features in core_cm0.h / core_cm3.h are configured by the following defines that must be
- defined before #include <core_cm0.h> / #include <core_cm3.h>
- preprocessor command.
-
-
-
-
-
-
#define
-
File
-
Value
-
Description
-
-
-
__NVIC_PRIO_BITS
-
core_cm0.h
-
(2)
-
Number of priority bits implemented in the NVIC (device specific)
-
-
-
__NVIC_PRIO_BITS
-
core_cm3.h
-
(2 ... 8)
-
Number of priority bits implemented in the NVIC (device specific)
-
-
-
__MPU_PRESENT
-
core_cm0.h, core_cm3.h
-
(0, 1)
-
Defines if an MPU is present or not
-
-
-
__Vendor_SysTickConfig
-
core_cm0.h, core_cm3.h
-
(1)
-
When this define is setup to 1, the SysTickConfig function
- in core_cm3.h is excluded. In this case the device.h
- file must contain a vendor specific implementation of this function.
-
-
-
-
-
-
Device Peripheral Access Layer
-
- Each peripheral uses a prefix which consists of <device abbreviation>_
- and <peripheral name>_ to identify peripheral registers that access this
- specific peripheral. The intention of this is to avoid name collisions caused
- due to short names. If more than one peripheral of the same type exists,
- identifiers have a postfix (digit or letter). For example:
-
-
-
<device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device.
-
<device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART.
- For example UART1->DR is the data register of UART1.
-
- To access the peripheral registers and related function in a device the files device.h
- and core_cm0.h / core_cm3.h defines as a minimum:
-
-
-
The Register Layout Typedef for each peripheral that defines all register names.
- Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
- the peripheral registers. For example:
-
-typedef struct {
- __IO uint32_t CTRL; /* SysTick Control and Status Register */
- __IO uint32_t LOAD; /* SysTick Reload Value Register */
- __IO uint32_t VAL; /* SysTick Current Value Register */
- __I uint32_t CALIB; /* SysTick Calibration Register */
- } SysTick_Type;
-
-
-
- Base Address for each peripheral (in case of multiple peripherals
- that use the same register layout typedef multiple base addresses are defined). For example:
-
-#define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */
-
-
-
- Access Definition for each peripheral (in case of multiple peripherals that use
- the same register layout typedef multiple access definitions exist, i.e. LPC_UART0,
- LPC_UART2). For Example:
-
- These definitions allow to access the peripheral registers from user code with simple assignments like:
-
-
SysTick->CTRL = 0;
-
-
Optional Features
-
In addition the device.h file may define:
-
-
- #define constants that simplify access to the peripheral registers.
- These constant define bit-positions or other specific patterns are that required for the
- programming of the peripheral registers. The identifiers used start with
- <device abbreviation>_ and <peripheral name>_.
- It is recommended to use CAPITAL letters for such #define constants.
-
-
- Functions that perform more complex functions with the peripheral (i.e. status query before
- a sending register is accessed). Again these function start with
- <device abbreviation>_ and <peripheral name>_.
-
-
-
-
core_cm0.h and core_cm0.c
-
- File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does
- the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers
- and core peripherals with efficient functions (defined as static inline).
-
-
- File core_cm0.c defines several helper functions that access processor registers.
-
- File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does
- the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers
- and core peripherals with efficient functions (defined as static inline).
-
-
- File core_cm3.c defines several helper functions that access processor registers.
-
- A template file for startup_device is provided by ARM for each supported
- compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific
- interrupt handlers. Each interrupt handler is defined as weak function
- to an dummy handler. Therefore the interrupt handler can be directly used in application software
- without any requirements to adapt the startup_device file.
-
-
- The following exception names are fixed and define the start of the vector table for a Cortex-M0:
-
- The user application may simply define an interrupt handler function by using the handler name
- as shown below.
-
-
-void WWDG_IRQHandler(void)
-{
- :
- :
-}
-
-
-
system_device.c
-
- A template file for system_device.c is provided by ARM but adapted by
- the silicon vendor to match their actual device. As a minimum requirement
- this file must provide a device specific system configuration function and a global variable
- that contains the system frequency. It configures the device and initializes typically the
- oscillator (PLL) that is part of the microcontroller device.
-
-
- The file system_device.c must provide
- as a minimum requirement the SystemInit function as shown below.
-
-
-
-
-
-
Function Definition
-
Description
-
-
-
void SystemInit (void)
-
Setup the microcontroller system. Typically this function configures the
- oscillator (PLL) that is part of the microcontroller device. For systems
- with variable clock speed it also updates the variable SystemCoreClock.
- SystemInit is called from startup_device file.
-
-
-
void SystemCoreClockUpdate (void)
-
Updates the variable SystemCoreClock and must be called whenever the
- core clock is changed during program execution. SystemCoreClockUpdate()
- evaluates the clock register settings and calculates the current core clock.
-
-
-
-
-
-
- Also part of the file system_device.c
- is the variable SystemCoreClock which contains the current CPU clock speed shown below.
-
-
-
-
-
-
Variable Definition
-
Description
-
-
-
uint32_t SystemCoreClock
-
Contains the system core clock (which is the system clock frequency supplied
- to the SysTick timer and the processor core clock). This variable can be
- used by the user application to setup the SysTick timer or configure other
- parameters. It may also be used by debugger to query the frequency of the
- debug timer or configure the trace clock speed.
- SystemCoreClock is initialized with a correct predefined value.
- The compiler must be configured to avoid the removal of this variable in
- case that the application program is not using it. It is important for
- debug systems that the variable is physically present in memory so that
- it can be examined to configure the debugger.
-
-
-
-
-
Note
-
-
The above definitions are the minimum requirements for the file
- system_device.c. This
- file may export more functions or variables that provide a more flexible
- configuration of the microcontroller system.
-
-
-
-
-
Core Peripheral Access Layer
-
-
Cortex-M Core Register Access
-
- The following functions are defined in core_cm0.h / core_cm3.h
- and provide access to Cortex-M core registers.
-
-
-
-
-
-
Function Definition
-
Core
-
Core Register
-
Description
-
-
-
void __enable_irq (void)
-
M0, M3
-
PRIMASK = 0
-
Global Interrupt enable (using the instruction CPSIE
- i)
-
-
-
void __disable_irq (void)
-
M0, M3
-
PRIMASK = 1
-
Global Interrupt disable (using the instruction
- CPSID i)
-
-
-
void __set_PRIMASK (uint32_t value)
-
M0, M3
-
PRIMASK = value
-
Assign value to Priority Mask Register (using the instruction
- MSR)
-
-
-
uint32_t __get_PRIMASK (void)
-
M0, M3
-
return PRIMASK
-
Return Priority Mask Register (using the instruction
- MRS)
-
-
-
void __enable_fault_irq (void)
-
M3
-
FAULTMASK = 0
-
Global Fault exception and Interrupt enable (using the
- instruction CPSIE
- f)
-
-
-
void __disable_fault_irq (void)
-
M3
-
FAULTMASK = 1
-
Global Fault exception and Interrupt disable (using the
- instruction CPSID f)
-
-
-
void __set_FAULTMASK (uint32_t value)
-
M3
-
FAULTMASK = value
-
Assign value to Fault Mask Register (using the instruction
- MSR)
-
-
-
uint32_t __get_FAULTMASK (void)
-
M3
-
return FAULTMASK
-
Return Fault Mask Register (using the instruction MRS)
-
-
-
void __set_BASEPRI (uint32_t value)
-
M3
-
BASEPRI = value
-
Set Base Priority (using the instruction MSR)
-
-
-
uiuint32_t __get_BASEPRI (void)
-
M3
-
return BASEPRI
-
Return Base Priority (using the instruction MRS)
-
-
-
void __set_CONTROL (uint32_t value)
-
M0, M3
-
CONTROL = value
-
Set CONTROL register value (using the instruction MSR)
-
-
-
uint32_t __get_CONTROL (void)
-
M0, M3
-
return CONTROL
-
Return Control Register Value (using the instruction
- MRS)
-
-
-
void __set_PSP (uint32_t TopOfProcStack)
-
M0, M3
-
PSP = TopOfProcStack
-
Set Process Stack Pointer value (using the instruction
- MSR)
-
-
-
uint32_t __get_PSP (void)
-
M0, M3
-
return PSP
-
Return Process Stack Pointer (using the instruction MRS)
-
-
-
void __set_MSP (uint32_t TopOfMainStack)
-
M0, M3
-
MSP = TopOfMainStack
-
Set Main Stack Pointer (using the instruction MSR)
-
-
-
uint32_t __get_MSP (void)
-
M0, M3
-
return MSP
-
Return Main Stack Pointer (using the instruction MRS)
-
-
-
-
-
Cortex-M Instruction Access
-
- The following functions are defined in core_cm0.h / core_cm3.hand
- generate specific Cortex-M instructions. The functions are implemented in the file
- core_cm0.c / core_cm3.c.
-
-
-
-
-
-
Name
-
Core
-
Generated CPU Instruction
-
Description
-
-
-
void __NOP (void)
-
M0, M3
-
NOP
-
No Operation
-
-
-
void __WFI (void)
-
M0, M3
-
WFI
-
Wait for Interrupt
-
-
-
void __WFE (void)
-
M0, M3
-
WFE
-
Wait for Event
-
-
-
void __SEV (void)
-
M0, M3
-
SEV
-
Set Event
-
-
-
void __ISB (void)
-
M0, M3
-
ISB
-
Instruction Synchronization Barrier
-
-
-
void __DSB (void)
-
M0, M3
-
DSB
-
Data Synchronization Barrier
-
-
-
void __DMB (void)
-
M0, M3
-
DMB
-
Data Memory Barrier
-
-
-
uint32_t __REV (uint32_t value)
-
M0, M3
-
REV
-
Reverse byte order in integer value.
-
-
-
uint32_t __REV16 (uint16_t value)
-
M0, M3
-
REV16
-
Reverse byte order in unsigned short value.
-
-
-
sint32_t __REVSH (sint16_t value)
-
M0, M3
-
REVSH
-
Reverse byte order in signed short value with sign extension to integer.
Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW
-
-
-
-
-
-
NVIC Access Functions
-
- The CMSIS provides access to the NVIC via the register interface structure and several helper
- functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to
- identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative
- IRQn values are used for processor core exceptions.
-
-
- For the IRQn values of core exceptions the file device.h provides
- the following enum names.
-
-
-
-
-
-
Core Exception enum Value
-
Core
-
IRQn
-
Description
-
-
-
NonMaskableInt_IRQn
-
M0, M3
-
-14
-
Cortex-M Non Maskable Interrupt
-
-
-
HardFault_IRQn
-
M0, M3
-
-13
-
Cortex-M Hard Fault Interrupt
-
-
-
MemoryManagement_IRQn
-
M3
-
-12
-
Cortex-M Memory Management Interrupt
-
-
-
BusFault_IRQn
-
M3
-
-11
-
Cortex-M Bus Fault Interrupt
-
-
-
UsageFault_IRQn
-
M3
-
-10
-
Cortex-M Usage Fault Interrupt
-
-
-
SVCall_IRQn
-
M0, M3
-
-5
-
Cortex-M SV Call Interrupt
-
-
-
DebugMonitor_IRQn
-
M3
-
-4
-
Cortex-M Debug Monitor Interrupt
-
-
-
PendSV_IRQn
-
M0, M3
-
-2
-
Cortex-M Pend SV Interrupt
-
-
-
SysTick_IRQn
-
M0, M3
-
-1
-
Cortex-M System Tick Interrupt
-
-
-
-
-
The following functions simplify the setup of the NVIC.
-The functions are defined as static inline.
IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub Priority
-
Deccode given priority to group, preemptive and sub priority
-
-
-
void NVIC_SystemReset (void)
-
M0, M3
-
(void)
-
Resets the System
-
-
-
-
Note
-
-
The processor exceptions have negative enum values. Device specific interrupts
- have positive enum values and start with 0. The values are defined in
- device.h file.
-
-
-
The values for PreemptPriority and SubPriority
- used in functions NVIC_EncodePriority and NVIC_DecodePriority
- depend on the available __NVIC_PRIO_BITS implemented in the NVIC.
-
-
-
-
-
-
SysTick Configuration Function
-
-
The following function is used to configure the SysTick timer and start the
-SysTick interrupt.
-
-
-
-
-
Name
-
Parameter
-
Description
-
-
-
uint32_t SysTickConfig
- (uint32_t ticks)
-
ticks is SysTick counter reload value
-
Setup the SysTick timer and enable the SysTick interrupt. After this
- call the SysTick timer creates interrupts with the specified time
- interval.
-
- Return: 0 when successful, 1 on failure.
-
-
-
-
-
-
-
Cortex-M3 ITM Debug Access
-
-
The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that
-provides together with the Serial Viewer Output trace capabilities for the
-microcontroller system. The ITM has 32 communication channels; two ITM
-communication channels are used by CMSIS to output the following information:
-
-
ITM Channel 0: implements the ITM_SendChar function
- which can be used for printf-style output via the debug interface.
-
ITM Channel 31: is reserved for the RTOS kernel and can be used for
- kernel awareness debugging.
-
-
Note
-
-
The ITM channel 31 is selected for the RTOS kernel since some kernels
- may use the Privileged level for program execution. ITM
- channels have 4 groups with 8 channels each, whereby each group can be
- configured for access rights in the Unprivileged level. The ITM channel 0
- may be therefore enabled for the user task whereas ITM channel 31 may be
- accessible only in Privileged level from the RTOS kernel itself.
-
-
-
-
The prototype of the ITM_SendChar routine is shown in the
-table below.
-
-
-
-
-
Name
-
Parameter
-
Description
-
-
-
void uint32_t ITM_SendChar(uint32_t chr)
-
character to output
-
The function outputs a character via the ITM channel 0. The
- function returns when no debugger is connected that has booked the
- output. It is blocking when a debugger is connected, but the
- previous character send is not transmitted.
- Return: the input character 'chr'.
-
-
-
-
-
- Example for the usage of the ITM Channel 31 for RTOS Kernels:
-
-
- // check if debugger connected and ITM channel enabled for tracing
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
- (ITM->TCR & ITM_TCR_ITMENA) &&
- (ITM->TER & (1UL << 31))) {
- // transmit trace data
- while (ITM->PORT31_U32 == 0);
- ITM->PORT[31].u8 = task_id; // id of next task
- while (ITM->PORT[31].u32 == 0);
- ITM->PORT[31].u32 = task_status; // status information
- }
-
-
-
Cortex-M3 additional Debug Access
-
-
CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access.
-Data can be transmitted via a certain global buffer variable towards the target system.
-
-
The buffer variable and the prototypes of the additional functions are shown in the
-table below.
-
-
-
-
-
Name
-
Parameter
-
Description
-
-
-
extern volatile int ITM_RxBuffer
-
-
Buffer to transmit data towards debug system.
- Value 0x5AA55AA5 indicates that buffer is empty.
-
-
-
int ITM_ReceiveChar (void)
-
none
-
The nonblocking functions returns the character stored in
- ITM_RxBuffer.
- Return: -1 indicates that no character was received.
-
-
-
int ITM_CheckChar (void)
-
none
-
The function checks if a character is available in ITM_RxBuffer.
- Return: 1 indicates that a character is available, 0 indicates that
- no character is available.
-
-
-
-
-
-
CMSIS Example
-
- The following section shows a typical example for using the CMSIS layer in user applications.
- The example is based on a STM32F10x Device.
-
-
-#include "stm32f10x.h"
-
-volatile uint32_t msTicks; /* timeTicks counter */
-
-void SysTick_Handler(void) {
- msTicks++; /* increment timeTicks counter */
-}
-
-__INLINE static void Delay (uint32_t dlyTicks) {
- uint32_t curTicks = msTicks;
-
- while ((msTicks - curTicks) < dlyTicks);
-}
-
-__INLINE static void LED_Config(void) {
- ; /* Configure the LEDs */
-}
-
-__INLINE static void LED_On (uint32_t led) {
- ; /* Turn On LED */
-}
-
-__INLINE static void LED_Off (uint32_t led) {
- ; /* Turn Off LED */
-}
-
-int main (void) {
- if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
- ; /* Handle Error */
- while (1);
- }
-
- LED_Config(); /* configure the LEDs */
-
- while(1) {
- LED_On (0x100); /* Turn on the LED */
- Delay (100); /* delay 100 Msec */
- LED_Off (0x100); /* Turn off the LED */
- Delay (100); /* delay 100 Msec */
- }
-}
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/License.doc b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/License.doc
deleted file mode 100644
index b6b8acec..00000000
Binary files a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/CMSIS/License.doc and /dev/null differ
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/Release_Notes.html b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/Release_Notes.html
deleted file mode 100644
index 633e42e3..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/Release_Notes.html
+++ /dev/null
@@ -1,342 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-Release Notes for STM32F10x Standard Peripherals Library Drivers
-
-
-
-
-
-
STM32F10x Standard
-Peripherals Library Drivers update History
-
V3.5.0 / 11-March-2011
-
Main
-Changes
-
-
-
stm32f10x_can.h/.c files:
-
-
Add 5 new functions
-
-
3
-new functions controlling the counter errors: CAN_GetLastErrorCode(),
-CAN_GetReceiveErrorCounter() and CAN_GetLSBTransmitErrorCounter().
-
-
-
1 new function to select the CAN operating mode: CAN_OperatingModeRequest().
-
-
-
1 new function to support CAN TT mode: CAN_TTComModeCmd().
-
-
-
CAN_TransmitStatus() function updated to support all CAN transmit intermediate states
-
-
-
stm32f10x_i2c.h/.c files:
-
-
Add 1 new function:
-
-
I2C_NACKPositionConfig():
-This function configures the same bit (POS) as I2C_PECPositionConfig()
-but is intended to be used in I2C mode while I2C_PECPositionConfig() is
-intended to used in SMBUS mode.
-
-
-
stm32f10x_tim.h/.c files:
-
-
Change the TIM_DMABurstLength_xBytes definitions to TIM_DMABurstLength_xTansfers
-
-
-
-
-
-
-
3.4.0
-- 10/15/2010
-
-
-
General
-
-
-
-
Add support for STM32F10x High-density value line devices.
-
-
-
-
STM32F10x_StdPeriph_Driver
-
-
-
-
-
-
stm32f10x_bkp.h/.c
-
-
Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file.
-
-
stm32f10x_can.h/.c
-
-
Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.
-
-
Update the wording of some defines and Asserts macro.
-
-
CAN_GetFlagStatus()
-and CAN_ClearFlag() functions: updated to support new flags (were not
-supported in previous version). These flags are: CAN_FLAG_RQCP0,
-CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1,
-CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0, CAN_FLAG_FOV0,
-CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC.
-
-
CAN_GetITStatus()
-function: add a check of the interrupt enable bit before getting the
-status of corresponding interrupt pending bit.
-
-
CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit.
-
-
-
stm32f10x_crc.h/.c
-
-
Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.
-
-
stm32f10x_dac.h/.c
-
-
Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file.
-
-
stm32f10x_dbgmcu.h/.c
-
-
Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file.
-
-
stm32f10x_dma.h/.c
-
-
Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.
-
Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"
-
-
-
stm32f10x_flash.h/.c
-
-
FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.
-
-
stm32f10x_fsmc.h/.c
-
-
Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.
-
-
stm32f10x_gpio.h/.c
-
-
GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.
-
-
stm32f10x_pwr.h/.c
-
-
Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.
-
-
stm32f10x_rtc.h/.c
-
-
Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.
-
-
stm32f10x_spi.h/.c
-
-
Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".
-
-
stm32f10x_tim.h/.c
-
Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".
-
-
-
-
3.3.0
-- 04/16/2010
-
-
General
-
Add support for STM32F10x XL-density devices.
I2C driver: events description and management enhancement.
-
STM32F10x_StdPeriph_Driver
-
stm32f10x_dbgmcu.h/.c
DBGMCU_Config() function: add new values DBGMCU_TIMx_STOP (x: 9..14) for DBGMCU_Periph parameter.
stm32f10x_flash.h/.c:
-updated to support Bank2 of XL-density devices (up to 1MByte of Flash
-memory). For more details, refer to the description provided within
-stm32f10x_flash.c file.
stm32f10x_gpio.h/.c
GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for FSMC_NADV pin and TIM9..11,13,14.
stm32f10x_i2c.h/.c: I2C events description and management enhancement.
I2C_CheckEvent()
-function: updated to check whether the last event contains the
-I2C_EVENT (instead of check whether the last event is equal to
-I2C_EVENT)
Add
-detailed description of I2C events and how to manage them using the
-functions provided by this driver. For more information, refer to
-stm32f10x_i2c.h and stm32f10x_i2c.c files.
stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration
stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.
Add support
-for STM32 Low-density Value line (STM32F100x4/6) and
-Medium-density Value line (STM32F100x8/B) devices.
-
Almost
-peripherals drivers were updated to support Value
-line devices features
-
Drivers limitations fix and enhancements.
-
-
-
-
STM32F10x_StdPeriph_Driver
-
-
-
Add new
-firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c
-
Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.
-
RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.
-
GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: GPIO_Remap_TIM1_DMA, GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.
-
USART
-driver: add support for Oversampling by 8 mode and onebit method. 2
-functions has been added: USART_OverSampling8Cmd() and
-USART_OneBitMethodCmd().
-
-
DAC
-driver: add new functions handling the DAC under run feature:
-DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus()
-and DAC_ClearITPendingBit().
-
DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.
-
-
FLASH
-driver: the FLASH_EraseOptionBytes() function updated. This is now just
-erasing the option bytes without modifying the RDP status either
-enabled or disabled.
-
PWR
-driver: the PWR_EnterSTOPMode() function updated. When woken up from
-STOP mode, this function resets again the SLEEPDEEP bit in the
-Cortex-M3 System Control register to allow Sleep mode entering.
-
-
-
-
License
-
The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.
-
THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS.
-
-
-
-
For
-complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers
-visit www.st.com/STM32
-
-
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/misc.h b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/misc.h
deleted file mode 100644
index 7d401ca9..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/misc.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/**
- ******************************************************************************
- * @file misc.h
- * @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
- * @brief This file contains all the functions prototypes for the miscellaneous
- * firmware library functions (add-on to CMSIS functions).
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_FSMC_H
-#define __STM32F10x_FSMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FSMC
- * @{
- */
-
-/** @defgroup FSMC_Exported_Types
- * @{
- */
-
-/**
- * @brief Timing parameters For NOR/SRAM Banks
- */
-
-typedef struct
-{
- uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
- This parameter can be a value between 0 and 0xF.
- @note: It is not used with synchronous NOR Flash memories. */
-
- uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address hold time.
- This parameter can be a value between 0 and 0xF.
- @note: It is not used with synchronous NOR Flash memories.*/
-
- uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the data setup time.
- This parameter can be a value between 0 and 0xFF.
- @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
-
- uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
- the duration of the bus turnaround.
- This parameter can be a value between 0 and 0xF.
- @note: It is only used for multiplexed NOR Flash memories. */
-
- uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
- This parameter can be a value between 1 and 0xF.
- @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
-
- uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
- to the memory before getting the first data.
- The value of this parameter depends on the memory type as shown below:
- - It must be set to 0 in case of a CRAM
- - It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between 0 and 0xF in NOR Flash memories
- with synchronous burst mode enable */
-
- uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FSMC_Access_Mode */
-}FSMC_NORSRAMTimingInitTypeDef;
-
-/**
- * @brief FSMC NOR/SRAM Init structure definition
- */
-
-typedef struct
-{
- uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */
-
- uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the databus or not.
- This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
- uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
- the corresponding memory bank.
- This parameter can be a value of @ref FSMC_Memory_Type */
-
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FSMC_Data_Width */
-
- uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
- valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FSMC_Burst_Access_Mode */
-
- uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
- valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FSMC_AsynchronousWait */
-
- uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
- the Flash memory in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
-
- uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
- memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FSMC_Wrap_Mode */
-
- uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
- clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Timing */
-
- uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
- This parameter can be a value of @ref FSMC_Write_Operation */
-
- uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
- signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal */
-
- uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FSMC_Extended_Mode */
-
- uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FSMC_Write_Burst */
-
- FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
-
- FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
-}FSMC_NORSRAMInitTypeDef;
-
-/**
- * @brief Timing parameters For FSMC NAND and PCCARD Banks
- */
-
-typedef struct
-{
- uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
- the command assertion for NAND-Flash read or write access
- to common/Attribute or I/O memory space (depending on
- the memory space timing to be configured).
- This parameter can be a value between 0 and 0xFF.*/
-
- uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
- command for NAND-Flash read or write access to
- common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-
- uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
- (and data for write access) after the command deassertion
- for NAND-Flash read or write access to common/Attribute
- or I/O memory space (depending on the memory space timing
- to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-
- uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
- databus is kept in HiZ after the start of a NAND-Flash
- write access to common/Attribute or I/O memory space (depending
- on the memory space timing to be configured).
- This parameter can be a number between 0x00 and 0xFF */
-}FSMC_NAND_PCCARDTimingInitTypeDef;
-
-/**
- * @brief FSMC NAND Init structure definition
- */
-
-typedef struct
-{
- uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
- This parameter can be a value of @ref FSMC_NAND_Bank */
-
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FSMC_Data_Width */
-
- uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FSMC_ECC */
-
- uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FSMC_ECC_Page_Size */
-
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 0xFF. */
-
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0x0 and 0xFF */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-}FSMC_NANDInitTypeDef;
-
-/**
- * @brief FSMC PCCARD Init structure definition
- */
-
-typedef struct
-{
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 0xFF. */
-
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0x0 and 0xFF */
-
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
-}FSMC_PCCARDInitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Exported_Constants
- * @{
- */
-
-/** @defgroup FSMC_NORSRAM_Bank
- * @{
- */
-#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
-#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
-#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
-#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_Bank
- * @{
- */
-#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
-#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCCARD_Bank
- * @{
- */
-#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
-/**
- * @}
- */
-
-#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
- ((BANK) == FSMC_Bank1_NORSRAM2) || \
- ((BANK) == FSMC_Bank1_NORSRAM3) || \
- ((BANK) == FSMC_Bank1_NORSRAM4))
-
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND))
-
-#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND) || \
- ((BANK) == FSMC_Bank4_PCCARD))
-
-#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
- ((BANK) == FSMC_Bank3_NAND) || \
- ((BANK) == FSMC_Bank4_PCCARD))
-
-/** @defgroup NOR_SRAM_Controller
- * @{
- */
-
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing
- * @{
- */
-
-#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
-#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
-#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
- ((MUX) == FSMC_DataAddressMux_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Memory_Type
- * @{
- */
-
-#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
-#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
-#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
-#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
- ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
- ((MEMORY) == FSMC_MemoryType_NOR))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Width
- * @{
- */
-
-#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
-#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
-#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
- ((WIDTH) == FSMC_MemoryDataWidth_16b))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Burst_Access_Mode
- * @{
- */
-
-#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
-#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
-#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
- ((STATE) == FSMC_BurstAccessMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_AsynchronousWait
- * @{
- */
-#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
-#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
-#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
- ((STATE) == FSMC_AsynchronousWait_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal_Polarity
- * @{
- */
-
-#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
-#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
-#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
- ((POLARITY) == FSMC_WaitSignalPolarity_High))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wrap_Mode
- * @{
- */
-
-#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
-#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
-#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
- ((MODE) == FSMC_WrapMode_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Timing
- * @{
- */
-
-#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
-#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
- ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Operation
- * @{
- */
-
-#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
-#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
-#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
- ((OPERATION) == FSMC_WriteOperation_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal
- * @{
- */
-
-#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
-#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
-#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
- ((SIGNAL) == FSMC_WaitSignal_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Extended_Mode
- * @{
- */
-
-#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
-#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
-
-#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
- ((MODE) == FSMC_ExtendedMode_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Burst
- * @{
- */
-
-#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
-#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
-#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
- ((BURST) == FSMC_WriteBurst_Enable))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Setup_Time
- * @{
- */
-
-#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Hold_Time
- * @{
- */
-
-#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Setup_Time
- * @{
- */
-
-#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Bus_Turn_around_Duration
- * @{
- */
-
-#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_CLK_Division
- * @{
- */
-
-#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Latency
- * @{
- */
-
-#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Access_Mode
- * @{
- */
-
-#define FSMC_AccessMode_A ((uint32_t)0x00000000)
-#define FSMC_AccessMode_B ((uint32_t)0x10000000)
-#define FSMC_AccessMode_C ((uint32_t)0x20000000)
-#define FSMC_AccessMode_D ((uint32_t)0x30000000)
-#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
- ((MODE) == FSMC_AccessMode_B) || \
- ((MODE) == FSMC_AccessMode_C) || \
- ((MODE) == FSMC_AccessMode_D))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup NAND_PCCARD_Controller
- * @{
- */
-
-/** @defgroup FSMC_Wait_feature
- * @{
- */
-
-#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
-#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
- ((FEATURE) == FSMC_Waitfeature_Enable))
-
-/**
- * @}
- */
-
-
-/** @defgroup FSMC_ECC
- * @{
- */
-
-#define FSMC_ECC_Disable ((uint32_t)0x00000000)
-#define FSMC_ECC_Enable ((uint32_t)0x00000040)
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
- ((STATE) == FSMC_ECC_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_ECC_Page_Size
- * @{
- */
-
-#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
-#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
-#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
-#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
-#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
-#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
- ((SIZE) == FSMC_ECCPageSize_8192Bytes))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_TCLR_Setup_Time
- * @{
- */
-
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_TAR_Setup_Time
- * @{
- */
-
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Setup_Time
- * @{
- */
-
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Setup_Time
- * @{
- */
-
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Hold_Setup_Time
- * @{
- */
-
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_HiZ_Setup_Time
- * @{
- */
-
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Interrupt_sources
- * @{
- */
-
-#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
-#define FSMC_IT_Level ((uint32_t)0x00000010)
-#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
-#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
- ((IT) == FSMC_IT_Level) || \
- ((IT) == FSMC_IT_FallingEdge))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Flags
- * @{
- */
-
-#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
-#define FSMC_FLAG_Level ((uint32_t)0x00000002)
-#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
-#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
-#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
- ((FLAG) == FSMC_FLAG_Level) || \
- ((FLAG) == FSMC_FLAG_FallingEdge) || \
- ((FLAG) == FSMC_FLAG_FEMPT))
-
-#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Exported_Functions
- * @{
- */
-
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
-void FSMC_NANDDeInit(uint32_t FSMC_Bank);
-void FSMC_PCCARDDeInit(void);
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-void FSMC_PCCARDCmd(FunctionalState NewState);
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F10x_FSMC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h
deleted file mode 100644
index b8aa49a2..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h
+++ /dev/null
@@ -1,385 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_gpio.h
- * @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
- * @brief This file contains all the functions prototypes for the GPIO
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_I2C_H
-#define __STM32F10x_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/** @defgroup I2C_Exported_Types
- * @{
- */
-
-/**
- * @brief I2C Init structure definition
- */
-
-typedef struct
-{
- uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
- This parameter must be set to a value lower than 400kHz */
-
- uint16_t I2C_Mode; /*!< Specifies the I2C mode.
- This parameter can be a value of @ref I2C_mode */
-
- uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
- This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
- uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
- This parameter can be a value of @ref I2C_acknowledgement */
-
- uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
- This parameter can be a value of @ref I2C_acknowledged_address */
-}I2C_InitTypeDef;
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Exported_Constants
- * @{
- */
-
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
- ((PERIPH) == I2C2))
-/** @defgroup I2C_mode
- * @{
- */
-
-#define I2C_Mode_I2C ((uint16_t)0x0000)
-#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
-#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
- ((MODE) == I2C_Mode_SMBusDevice) || \
- ((MODE) == I2C_Mode_SMBusHost))
-/**
- * @}
- */
-
-/** @defgroup I2C_duty_cycle_in_fast_mode
- * @{
- */
-
-#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
-#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
- ((CYCLE) == I2C_DutyCycle_2))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledgement
- * @{
- */
-
-#define I2C_Ack_Enable ((uint16_t)0x0400)
-#define I2C_Ack_Disable ((uint16_t)0x0000)
-#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
- ((STATE) == I2C_Ack_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2C_transfer_direction
- * @{
- */
-
-#define I2C_Direction_Transmitter ((uint8_t)0x00)
-#define I2C_Direction_Receiver ((uint8_t)0x01)
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
- ((DIRECTION) == I2C_Direction_Receiver))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledged_address
- * @{
- */
-
-#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
-#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
-/**
- * @}
- */
-
-/** @defgroup I2C_registers
- * @{
- */
-
-#define I2C_Register_CR1 ((uint8_t)0x00)
-#define I2C_Register_CR2 ((uint8_t)0x04)
-#define I2C_Register_OAR1 ((uint8_t)0x08)
-#define I2C_Register_OAR2 ((uint8_t)0x0C)
-#define I2C_Register_DR ((uint8_t)0x10)
-#define I2C_Register_SR1 ((uint8_t)0x14)
-#define I2C_Register_SR2 ((uint8_t)0x18)
-#define I2C_Register_CCR ((uint8_t)0x1C)
-#define I2C_Register_TRISE ((uint8_t)0x20)
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
- ((REGISTER) == I2C_Register_CR2) || \
- ((REGISTER) == I2C_Register_OAR1) || \
- ((REGISTER) == I2C_Register_OAR2) || \
- ((REGISTER) == I2C_Register_DR) || \
- ((REGISTER) == I2C_Register_SR1) || \
- ((REGISTER) == I2C_Register_SR2) || \
- ((REGISTER) == I2C_Register_CCR) || \
- ((REGISTER) == I2C_Register_TRISE))
-/**
- * @}
- */
-
-/** @defgroup I2C_SMBus_alert_pin_level
- * @{
- */
-
-#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
-#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
-#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
- ((ALERT) == I2C_SMBusAlert_High))
-/**
- * @}
- */
-
-/** @defgroup I2C_PEC_position
- * @{
- */
-
-#define I2C_PECPosition_Next ((uint16_t)0x0800)
-#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
-#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
- ((POSITION) == I2C_PECPosition_Current))
-/**
- * @}
- */
-
-/** @defgroup I2C_NCAK_position
- * @{
- */
-
-#define I2C_NACKPosition_Next ((uint16_t)0x0800)
-#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
-#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
- ((POSITION) == I2C_NACKPosition_Current))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_BUF ((uint16_t)0x0400)
-#define I2C_IT_EVT ((uint16_t)0x0200)
-#define I2C_IT_ERR ((uint16_t)0x0100)
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
-#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
-#define I2C_IT_PECERR ((uint32_t)0x01001000)
-#define I2C_IT_OVR ((uint32_t)0x01000800)
-#define I2C_IT_AF ((uint32_t)0x01000400)
-#define I2C_IT_ARLO ((uint32_t)0x01000200)
-#define I2C_IT_BERR ((uint32_t)0x01000100)
-#define I2C_IT_TXE ((uint32_t)0x06000080)
-#define I2C_IT_RXNE ((uint32_t)0x06000040)
-#define I2C_IT_STOPF ((uint32_t)0x02000010)
-#define I2C_IT_ADD10 ((uint32_t)0x02000008)
-#define I2C_IT_BTF ((uint32_t)0x02000004)
-#define I2C_IT_ADDR ((uint32_t)0x02000002)
-#define I2C_IT_SB ((uint32_t)0x02000001)
-
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
-
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
- ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
- ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
- ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
- ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_flags_definition
- * @{
- */
-
-/**
- * @brief SR2 register flags
- */
-
-#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
-#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
-#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
-#define I2C_FLAG_TRA ((uint32_t)0x00040000)
-#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
-#define I2C_FLAG_MSL ((uint32_t)0x00010000)
-
-/**
- * @brief SR1 register flags
- */
-
-#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
-#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
-#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
-#define I2C_FLAG_OVR ((uint32_t)0x10000800)
-#define I2C_FLAG_AF ((uint32_t)0x10000400)
-#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
-#define I2C_FLAG_BERR ((uint32_t)0x10000100)
-#define I2C_FLAG_TXE ((uint32_t)0x10000080)
-#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
-#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
-#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
-#define I2C_FLAG_BTF ((uint32_t)0x10000004)
-#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
-#define I2C_FLAG_SB ((uint32_t)0x10000001)
-
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
-
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
- ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
- ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
- ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
- ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
- ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
- ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
- ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
- ((FLAG) == I2C_FLAG_SB))
-/**
- * @}
- */
-
-/** @defgroup I2C_Events
- * @{
- */
-
-/*========================================
-
- I2C Master Events (Events grouped in order of communication)
- ==========================================*/
-/**
- * @brief Communication start
- *
- * After sending the START condition (I2C_GenerateSTART() function) the master
- * has to wait for this event. It means that the Start condition has been correctly
- * released on the I2C bus (the bus is free, no other devices is communicating).
- *
- */
-/* --EV5 */
-#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
-
-/**
- * @brief Address Acknowledge
- *
- * After checking on EV5 (start condition correctly released on the bus), the
- * master sends the address of the slave(s) with which it will communicate
- * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
- * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
- * his address. If an acknowledge is sent on the bus, one of the following events will
- * be set:
- *
- * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
- * event is set.
- *
- * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
- * is set
- *
- * 3) In case of 10-Bit addressing mode, the master (just after generating the START
- * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
- * function). Then master should wait on EV9. It means that the 10-bit addressing
- * header has been correctly sent on the bus. Then master should send the second part of
- * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
- * should wait for event EV6.
- *
- */
-
-/* --EV6 */
-#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
-#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
-/* --EV9 */
-#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
-
-/**
- * @brief Communication events
- *
- * If a communication is established (START condition generated and slave address
- * acknowledged) then the master has to check on one of the following events for
- * communication procedures:
- *
- * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
- * the data received from the slave (I2C_ReceiveData() function).
- *
- * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
- * function) then to wait on event EV8 or EV8_2.
- * These two events are similar:
- * - EV8 means that the data has been written in the data register and is
- * being shifted out.
- * - EV8_2 means that the data has been physically shifted out and output
- * on the bus.
- * In most cases, using EV8 is sufficient for the application.
- * Using EV8_2 leads to a slower communication but ensure more reliable test.
- * EV8_2 is also more suitable than EV8 for testing on the last data transmission
- * (before Stop condition generation).
- *
- * @note In case the user software does not guarantee that this event EV7 is
- * managed before the current byte end of transfer, then user may check on EV7
- * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Master RECEIVER mode -----------------------------*/
-/* --EV7 */
-#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
-
-/* Master TRANSMITTER mode --------------------------*/
-/* --EV8 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
-/* --EV8_2 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
-
-
-/*========================================
-
- I2C Slave Events (Events grouped in order of communication)
- ==========================================*/
-
-/**
- * @brief Communication start events
- *
- * Wait on one of these events at the start of the communication. It means that
- * the I2C peripheral detected a Start condition on the bus (generated by master
- * device) followed by the peripheral address. The peripheral generates an ACK
- * condition on the bus (if the acknowledge feature is enabled through function
- * I2C_AcknowledgeConfig()) and the events listed above are set :
- *
- * 1) In normal case (only one address managed by the slave), when the address
- * sent by the master matches the own address of the peripheral (configured by
- * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
- * (where XXX could be TRANSMITTER or RECEIVER).
- *
- * 2) In case the address sent by the master matches the second address of the
- * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
- * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
- * (where XXX could be TRANSMITTER or RECEIVER) are set.
- *
- * 3) In case the address sent by the master is General Call (address 0x00) and
- * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
- * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
- *
- */
-
-/* --EV1 (all the events below are variants of EV1) */
-/* 1) Case of One Single Address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
-
-/* 2) Case of Dual address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
-
-/* 3) Case of General Call enabled for the slave */
-#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
-
-/**
- * @brief Communication events
- *
- * Wait on one of these events when EV1 has already been checked and:
- *
- * - Slave RECEIVER mode:
- * - EV2: When the application is expecting a data byte to be received.
- * - EV4: When the application is expecting the end of the communication: master
- * sends a stop condition and data transmission is stopped.
- *
- * - Slave Transmitter mode:
- * - EV3: When a byte has been transmitted by the slave and the application is expecting
- * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
- * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
- * used when the user software doesn't guarantee the EV3 is managed before the
- * current byte end of transfer.
- * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
- * shall end (before sending the STOP condition). In this case slave has to stop sending
- * data bytes and expect a Stop condition on the bus.
- *
- * @note In case the user software does not guarantee that the event EV2 is
- * managed before the current byte end of transfer, then user may check on EV2
- * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
- * In this case the communication may be slower.
- *
- */
-
-/* Slave RECEIVER mode --------------------------*/
-/* --EV2 */
-#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
-/* --EV4 */
-#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
-
-/* Slave TRANSMITTER mode -----------------------*/
-/* --EV3 */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
-/* --EV3_2 */
-#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
-
-/*=========================== End of Events Description ==========================================*/
-
-#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
- ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
- ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
- ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
- ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
-/**
- * @}
- */
-
-/** @defgroup I2C_own_address1
- * @{
- */
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
-/**
- * @}
- */
-
-/** @defgroup I2C_clock_speed
- * @{
- */
-
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Functions
- * @{
- */
-
-void I2C_DeInit(I2C_TypeDef* I2Cx);
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
-
-/**
- * @brief
- ****************************************************************************************
- *
- * I2C State Monitoring Functions
- *
- ****************************************************************************************
- * This I2C driver provides three different ways for I2C state monitoring
- * depending on the application requirements and constraints:
- *
- *
- * 1) Basic state monitoring:
- * Using I2C_CheckEvent() function:
- * It compares the status registers (SR1 and SR2) content to a given event
- * (can be the combination of one or more flags).
- * It returns SUCCESS if the current status includes the given flags
- * and returns ERROR if one or more flags are missing in the current status.
- * - When to use:
- * - This function is suitable for most applications as well as for startup
- * activity since the events are fully described in the product reference manual
- * (RM0008).
- * - It is also suitable for users who need to define their own events.
- * - Limitations:
- * - If an error occurs (ie. error flags are set besides to the monitored flags),
- * the I2C_CheckEvent() function may return SUCCESS despite the communication
- * hold or corrupted real state.
- * In this case, it is advised to use error interrupts to monitor the error
- * events and handle them in the interrupt IRQ handler.
- *
- * @note
- * For error management, it is advised to use the following functions:
- * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
- * Where x is the peripheral instance (I2C1, I2C2 ...)
- * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
- * in order to determine which error occurred.
- * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- * and/or I2C_GenerateStop() in order to clear the error flag and source,
- * and return to correct communication status.
- *
- *
- * 2) Advanced state monitoring:
- * Using the function I2C_GetLastEvent() which returns the image of both status
- * registers in a single word (uint32_t) (Status Register 2 value is shifted left
- * by 16 bits and concatenated to Status Register 1).
- * - When to use:
- * - This function is suitable for the same applications above but it allows to
- * overcome the limitations of I2C_GetFlagStatus() function (see below).
- * The returned value could be compared to events already defined in the
- * library (stm32f10x_i2c.h) or to custom values defined by user.
- * - This function is suitable when multiple flags are monitored at the same time.
- * - At the opposite of I2C_CheckEvent() function, this function allows user to
- * choose when an event is accepted (when all events flags are set and no
- * other flags are set or just when the needed flags are set like
- * I2C_CheckEvent() function).
- * - Limitations:
- * - User may need to define his own events.
- * - Same remark concerning the error management is applicable for this
- * function if user decides to check only regular communication flags (and
- * ignores error flags).
- *
- *
- * 3) Flag-based state monitoring:
- * Using the function I2C_GetFlagStatus() which simply returns the status of
- * one single flag (ie. I2C_FLAG_RXNE ...).
- * - When to use:
- * - This function could be used for specific applications or in debug phase.
- * - It is suitable when only one flag checking is needed (most I2C events
- * are monitored through multiple flags).
- * - Limitations:
- * - When calling this function, the Status register is accessed. Some flags are
- * cleared when the status register is accessed. So checking the status
- * of one Flag, may clear other ones.
- * - Function may need to be called twice or more in order to monitor one
- * single event.
- *
- */
-
-/**
- *
- * 1) Basic state monitoring
- *******************************************************************************
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
-/**
- *
- * 2) Advanced state monitoring
- *******************************************************************************
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
-/**
- *
- * 3) Flag-based state monitoring
- *******************************************************************************
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-/**
- *
- *******************************************************************************
- */
-
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F10x_I2C_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h
deleted file mode 100644
index 7f5ab764..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_iwdg.h
- * @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
- * @brief This file contains all the functions prototypes for the IWDG
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_flash.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FLASH
- * @brief FLASH driver modules
- * @{
- */
-
-/** @defgroup FLASH_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Private_Defines
- * @{
- */
-
-/* Flash Access Control Register bits */
-#define ACR_LATENCY_Mask ((uint32_t)0x00000038)
-#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
-#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
-
-/* Flash Access Control Register bits */
-#define ACR_PRFTBS_Mask ((uint32_t)0x00000020)
-
-/* Flash Control Register bits */
-#define CR_PG_Set ((uint32_t)0x00000001)
-#define CR_PG_Reset ((uint32_t)0x00001FFE)
-#define CR_PER_Set ((uint32_t)0x00000002)
-#define CR_PER_Reset ((uint32_t)0x00001FFD)
-#define CR_MER_Set ((uint32_t)0x00000004)
-#define CR_MER_Reset ((uint32_t)0x00001FFB)
-#define CR_OPTPG_Set ((uint32_t)0x00000010)
-#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)
-#define CR_OPTER_Set ((uint32_t)0x00000020)
-#define CR_OPTER_Reset ((uint32_t)0x00001FDF)
-#define CR_STRT_Set ((uint32_t)0x00000040)
-#define CR_LOCK_Set ((uint32_t)0x00000080)
-
-/* FLASH Mask */
-#define RDPRT_Mask ((uint32_t)0x00000002)
-#define WRP0_Mask ((uint32_t)0x000000FF)
-#define WRP1_Mask ((uint32_t)0x0000FF00)
-#define WRP2_Mask ((uint32_t)0x00FF0000)
-#define WRP3_Mask ((uint32_t)0xFF000000)
-#define OB_USER_BFB2 ((uint16_t)0x0008)
-
-/* FLASH Keys */
-#define RDP_Key ((uint16_t)0x00A5)
-#define FLASH_KEY1 ((uint32_t)0x45670123)
-#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
-
-/* FLASH BANK address */
-#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
-
-/* Delay definition */
-#define EraseTimeout ((uint32_t)0x000B0000)
-#define ProgramTimeout ((uint32_t)0x00002000)
-/**
- * @}
- */
-
-/** @defgroup FLASH_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Private_Functions
- * @{
- */
-
-/**
-@code
-
- This driver provides functions to configure and program the Flash memory of all STM32F10x devices,
- including the latest STM32F10x_XL density devices.
-
- STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:
- - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)
- - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)
- While other STM32F10x devices features only one bank with memory up to 512 Kbytes.
-
- In version V3.3.0, some functions were updated and new ones were added to support
- STM32F10x_XL devices. Thus some functions manages all devices, while other are
- dedicated for XL devices only.
-
- The table below presents the list of available functions depending on the used STM32F10x devices.
-
- ***************************************************
- * Legacy functions used for all STM32F10x devices *
- ***************************************************
- +----------------------------------------------------------------------------------------------------------------------------------+
- | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
- | | devices | devices | |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_SetLatency | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_HalfCycleAccessCmd | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_PrefetchBufferCmd | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. |
- | | | | - For other devices: unlock Bank1 and it is equivalent |
- | | | | to FLASH_UnlockBank1 function. |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. |
- | | | | - For other devices: lock Bank1 and it is equivalent |
- | | | | to FLASH_LockBank1 function. |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 |
- | | | | - For other devices: erase a page in Bank1 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |
- | | | | - For other devices: erase all pages in Bank1 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_EraseOptionBytes | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ProgramOptionByteData | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_EnableWriteProtection | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ReadOutProtection | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_UserOptionByteConfig | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_GetUserOptionByte | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|
- | | | | - For other devices: enable Bank1's interrupts |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|
- | | | | - For other devices: return Bank1's flag status |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag |
- | | | | - For other devices: clear Bank1's flag |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) |
- | | | | equivalent to FLASH_GetBank1Status function |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) |
- | | | | equivalent to: FLASH_WaitForLastBank1Operation function |
- +----------------------------------------------------------------------------------------------------------------------------------+
-
- ************************************************************************************************************************
- * New functions used for all STM32F10x devices to manage Bank1: *
- * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *
- * - For other devices, these functions are optional (covered by functions listed above) *
- ************************************************************************************************************************
- +----------------------------------------------------------------------------------------------------------------------------------+
- | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
- | | devices | devices | |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation |
- +----------------------------------------------------------------------------------------------------------------------------------+
-
- *****************************************************************************
- * New Functions used only with STM32F10x_XL density devices to manage Bank2 *
- *****************************************************************************
- +----------------------------------------------------------------------------------------------------------------------------------+
- | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
- | | devices | devices | |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- |FLASH_LockBank2 | Yes | No | - Lock Bank2 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation |
- |----------------------------------------------------------------------------------------------------------------------------------|
- | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 |
- +----------------------------------------------------------------------------------------------------------------------------------+
-@endcode
-*/
-
-
-/**
- * @brief Sets the code latency value.
- * @note This function can be used for all STM32F10x devices.
- * @param FLASH_Latency: specifies the FLASH Latency value.
- * This parameter can be one of the following values:
- * @arg FLASH_Latency_0: FLASH Zero Latency cycle
- * @arg FLASH_Latency_1: FLASH One Latency cycle
- * @arg FLASH_Latency_2: FLASH Two Latency cycles
- * @retval None
- */
-void FLASH_SetLatency(uint32_t FLASH_Latency)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));
-
- /* Read the ACR register */
- tmpreg = FLASH->ACR;
-
- /* Sets the Latency value */
- tmpreg &= ACR_LATENCY_Mask;
- tmpreg |= FLASH_Latency;
-
- /* Write the ACR register */
- FLASH->ACR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Half cycle flash access.
- * @note This function can be used for all STM32F10x devices.
- * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
- * This parameter can be one of the following values:
- * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
- * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
- * @retval None
- */
-void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
-
- /* Enable or disable the Half cycle access */
- FLASH->ACR &= ACR_HLFCYA_Mask;
- FLASH->ACR |= FLASH_HalfCycleAccess;
-}
-
-/**
- * @brief Enables or disables the Prefetch Buffer.
- * @note This function can be used for all STM32F10x devices.
- * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
- * This parameter can be one of the following values:
- * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
- * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
- * @retval None
- */
-void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
-
- /* Enable or disable the Prefetch Buffer */
- FLASH->ACR &= ACR_PRFTBE_Mask;
- FLASH->ACR |= FLASH_PrefetchBuffer;
-}
-
-/**
- * @brief Unlocks the FLASH Program Erase Controller.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.
- * - For all other devices it unlocks Bank1 and it is equivalent
- * to FLASH_UnlockBank1 function..
- * @param None
- * @retval None
- */
-void FLASH_Unlock(void)
-{
- /* Authorize the FPEC of Bank1 Access */
- FLASH->KEYR = FLASH_KEY1;
- FLASH->KEYR = FLASH_KEY2;
-
-#ifdef STM32F10X_XL
- /* Authorize the FPEC of Bank2 Access */
- FLASH->KEYR2 = FLASH_KEY1;
- FLASH->KEYR2 = FLASH_KEY2;
-#endif /* STM32F10X_XL */
-}
-/**
- * @brief Unlocks the FLASH Bank1 Program Erase Controller.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices this function unlocks Bank1.
- * - For all other devices it unlocks Bank1 and it is
- * equivalent to FLASH_Unlock function.
- * @param None
- * @retval None
- */
-void FLASH_UnlockBank1(void)
-{
- /* Authorize the FPEC of Bank1 Access */
- FLASH->KEYR = FLASH_KEY1;
- FLASH->KEYR = FLASH_KEY2;
-}
-
-#ifdef STM32F10X_XL
-/**
- * @brief Unlocks the FLASH Bank2 Program Erase Controller.
- * @note This function can be used only for STM32F10X_XL density devices.
- * @param None
- * @retval None
- */
-void FLASH_UnlockBank2(void)
-{
- /* Authorize the FPEC of Bank2 Access */
- FLASH->KEYR2 = FLASH_KEY1;
- FLASH->KEYR2 = FLASH_KEY2;
-
-}
-#endif /* STM32F10X_XL */
-
-/**
- * @brief Locks the FLASH Program Erase Controller.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices this function Locks Bank1 and Bank2.
- * - For all other devices it Locks Bank1 and it is equivalent
- * to FLASH_LockBank1 function.
- * @param None
- * @retval None
- */
-void FLASH_Lock(void)
-{
- /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
- FLASH->CR |= CR_LOCK_Set;
-
-#ifdef STM32F10X_XL
- /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
- FLASH->CR2 |= CR_LOCK_Set;
-#endif /* STM32F10X_XL */
-}
-
-/**
- * @brief Locks the FLASH Bank1 Program Erase Controller.
- * @note this function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices this function Locks Bank1.
- * - For all other devices it Locks Bank1 and it is equivalent
- * to FLASH_Lock function.
- * @param None
- * @retval None
- */
-void FLASH_LockBank1(void)
-{
- /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
- FLASH->CR |= CR_LOCK_Set;
-}
-
-#ifdef STM32F10X_XL
-/**
- * @brief Locks the FLASH Bank2 Program Erase Controller.
- * @note This function can be used only for STM32F10X_XL density devices.
- * @param None
- * @retval None
- */
-void FLASH_LockBank2(void)
-{
- /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
- FLASH->CR2 |= CR_LOCK_Set;
-}
-#endif /* STM32F10X_XL */
-
-/**
- * @brief Erases a specified FLASH page.
- * @note This function can be used for all STM32F10x devices.
- * @param Page_Address: The page address to be erased.
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Page_Address));
-
-#ifdef STM32F10X_XL
- if(Page_Address < FLASH_BANK1_END_ADDRESS)
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase the page */
- FLASH->CR|= CR_PER_Set;
- FLASH->AR = Page_Address;
- FLASH->CR|= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-
- /* Disable the PER Bit */
- FLASH->CR &= CR_PER_Reset;
- }
- }
- else
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase the page */
- FLASH->CR2|= CR_PER_Set;
- FLASH->AR2 = Page_Address;
- FLASH->CR2|= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-
- /* Disable the PER Bit */
- FLASH->CR2 &= CR_PER_Reset;
- }
- }
-#else
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase the page */
- FLASH->CR|= CR_PER_Set;
- FLASH->AR = Page_Address;
- FLASH->CR|= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- /* Disable the PER Bit */
- FLASH->CR &= CR_PER_Reset;
- }
-#endif /* STM32F10X_XL */
-
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Erases all FLASH pages.
- * @note This function can be used for all STM32F10x devices.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_EraseAllPages(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
-#ifdef STM32F10X_XL
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR |= CR_MER_Set;
- FLASH->CR |= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-
- /* Disable the MER Bit */
- FLASH->CR &= CR_MER_Reset;
- }
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR2 |= CR_MER_Set;
- FLASH->CR2 |= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-
- /* Disable the MER Bit */
- FLASH->CR2 &= CR_MER_Reset;
- }
-#else
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR |= CR_MER_Set;
- FLASH->CR |= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- /* Disable the MER Bit */
- FLASH->CR &= CR_MER_Reset;
- }
-#endif /* STM32F10X_XL */
-
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Erases all Bank1 FLASH pages.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices this function erases all Bank1 pages.
- * - For all other devices it erases all Bank1 pages and it is equivalent
- * to FLASH_EraseAllPages function.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_EraseAllBank1Pages(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR |= CR_MER_Set;
- FLASH->CR |= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-
- /* Disable the MER Bit */
- FLASH->CR &= CR_MER_Reset;
- }
- /* Return the Erase Status */
- return status;
-}
-
-#ifdef STM32F10X_XL
-/**
- * @brief Erases all Bank2 FLASH pages.
- * @note This function can be used only for STM32F10x_XL density devices.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_EraseAllBank2Pages(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR2 |= CR_MER_Set;
- FLASH->CR2 |= CR_STRT_Set;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-
- /* Disable the MER Bit */
- FLASH->CR2 &= CR_MER_Reset;
- }
- /* Return the Erase Status */
- return status;
-}
-#endif /* STM32F10X_XL */
-
-/**
- * @brief Erases the FLASH option bytes.
- * @note This functions erases all option bytes except the Read protection (RDP).
- * @note This function can be used for all STM32F10x devices.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_EraseOptionBytes(void)
-{
- uint16_t rdptmp = RDP_Key;
-
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Get the actual read protection Option Byte value */
- if(FLASH_GetReadOutProtectionStatus() != RESET)
- {
- rdptmp = 0x00;
- }
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- /* if the previous operation is completed, proceed to erase the option bytes */
- FLASH->CR |= CR_OPTER_Set;
- FLASH->CR |= CR_STRT_Set;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the erase operation is completed, disable the OPTER Bit */
- FLASH->CR &= CR_OPTER_Reset;
-
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
- /* Restore the last read protection Option Byte value */
- OB->RDP = (uint16_t)rdptmp;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- else
- {
- if (status != FLASH_TIMEOUT)
- {
- /* Disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- }
- /* Return the erase status */
- return status;
-}
-
-/**
- * @brief Programs a word at a specified address.
- * @note This function can be used for all STM32F10x devices.
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
-#ifdef STM32F10X_XL
- if(Address < FLASH_BANK1_END_ADDRESS - 2)
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new first
- half word */
- FLASH->CR |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = (uint16_t)Data;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new second
- half word */
- tmp = Address + 2;
-
- *(__IO uint16_t*) tmp = Data >> 16;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- else
- {
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- }
- }
- else if(Address == (FLASH_BANK1_END_ADDRESS - 1))
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new first
- half word */
- FLASH->CR |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = (uint16_t)Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- else
- {
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new second
- half word */
- FLASH->CR2 |= CR_PG_Set;
- tmp = Address + 2;
-
- *(__IO uint16_t*) tmp = Data >> 16;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR2 &= CR_PG_Reset;
- }
- else
- {
- /* Disable the PG Bit */
- FLASH->CR2 &= CR_PG_Reset;
- }
- }
- else
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new first
- half word */
- FLASH->CR2 |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = (uint16_t)Data;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new second
- half word */
- tmp = Address + 2;
-
- *(__IO uint16_t*) tmp = Data >> 16;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR2 &= CR_PG_Reset;
- }
- else
- {
- /* Disable the PG Bit */
- FLASH->CR2 &= CR_PG_Reset;
- }
- }
- }
-#else
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new first
- half word */
- FLASH->CR |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = (uint16_t)Data;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new second
- half word */
- tmp = Address + 2;
-
- *(__IO uint16_t*) tmp = Data >> 16;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- else
- {
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- }
-#endif /* STM32F10X_XL */
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a half word at a specified address.
- * @note This function can be used for all STM32F10x devices.
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Check the parameters */
- assert_param(IS_FLASH_ADDRESS(Address));
-
-#ifdef STM32F10X_XL
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(Address < FLASH_BANK1_END_ADDRESS)
- {
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = Data;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
- }
- else
- {
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR2 |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = Data;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR2 &= CR_PG_Reset;
- }
- }
-#else
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to program the new data */
- FLASH->CR |= CR_PG_Set;
-
- *(__IO uint16_t*)Address = Data;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- /* Disable the PG Bit */
- FLASH->CR &= CR_PG_Reset;
- }
-#endif /* STM32F10X_XL */
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a half word at a specified Option Byte Data address.
- * @note This function can be used for all STM32F10x devices.
- * @param Address: specifies the address to be programmed.
- * This parameter can be 0x1FFFF804 or 0x1FFFF806.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Check the parameters */
- assert_param(IS_OB_DATA_ADDRESS(Address));
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
- /* Enables the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- /* Return the Option Byte Data Program Status */
- return status;
-}
-
-/**
- * @brief Write protects the desired pages
- * @note This function can be used for all STM32F10x devices.
- * @param FLASH_Pages: specifies the address of the pages to be write protected.
- * This parameter can be:
- * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31
- * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3
- * and FLASH_WRProt_Pages124to127
- * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and
- * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
- * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and
- * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127
- * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and
- * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511
- * @arg FLASH_WRProt_AllPages
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
-{
- uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
-
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
-
- FLASH_Pages = (uint32_t)(~FLASH_Pages);
- WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
- WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
- WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
- WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* Authorizes the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
- FLASH->CR |= CR_OPTPG_Set;
- if(WRP0_Data != 0xFF)
- {
- OB->WRP0 = WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- }
- if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
- {
- OB->WRP1 = WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- }
- if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
- {
- OB->WRP2 = WRP2_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- }
-
- if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
- {
- OB->WRP3 = WRP3_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- }
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- /* Return the write protection operation Status */
- return status;
-}
-
-/**
- * @brief Enables or disables the read out protection.
- * @note If the user has already programmed the other option bytes before calling
- * this function, he must re-program them since this function erases all option bytes.
- * @note This function can be used for all STM32F10x devices.
- * @param Newstate: new state of the ReadOut Protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- status = FLASH_WaitForLastOperation(EraseTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* Authorizes the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
- FLASH->CR |= CR_OPTER_Set;
- FLASH->CR |= CR_STRT_Set;
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
- if(status == FLASH_COMPLETE)
- {
- /* if the erase operation is completed, disable the OPTER Bit */
- FLASH->CR &= CR_OPTER_Reset;
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
- if(NewState != DISABLE)
- {
- OB->RDP = 0x00;
- }
- else
- {
- OB->RDP = RDP_Key;
- }
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(EraseTimeout);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- else
- {
- if(status != FLASH_TIMEOUT)
- {
- /* Disable the OPTER Bit */
- FLASH->CR &= CR_OPTER_Reset;
- }
- }
- }
- /* Return the protection operation Status */
- return status;
-}
-
-/**
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
- * @note This function can be used for all STM32F10x devices.
- * @param OB_IWDG: Selects the IWDG mode
- * This parameter can be one of the following values:
- * @arg OB_IWDG_SW: Software IWDG selected
- * @arg OB_IWDG_HW: Hardware IWDG selected
- * @param OB_STOP: Reset event when entering STOP mode.
- * This parameter can be one of the following values:
- * @arg OB_STOP_NoRST: No reset generated when entering in STOP
- * @arg OB_STOP_RST: Reset generated when entering in STOP
- * @param OB_STDBY: Reset event when entering Standby mode.
- * This parameter can be one of the following values:
- * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
-
- OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-#ifdef STM32F10X_XL
-/**
- * @brief Configures to boot from Bank1 or Bank2.
- * @note This function can be used only for STM32F10x_XL density devices.
- * @param FLASH_BOOT: select the FLASH Bank to boot from.
- * This parameter can be one of the following values:
- * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash
- * position and this parameter is selected the device will boot from Bank1(Default).
- * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash
- * position and this parameter is selected the device will boot from Bank2 or Bank1,
- * depending on the activation of the bank. The active banks are checked in
- * the following order: Bank2, followed by Bank1.
- * The active bank is recognized by the value programmed at the base address
- * of the respective bank (corresponding to the initial stack pointer value
- * in the interrupt vector table).
- * For more information, please refer to AN2606 from www.st.com.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)
-{
- FLASH_Status status = FLASH_COMPLETE;
- assert_param(IS_FLASH_BOOT(FLASH_BOOT));
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= CR_OPTPG_Set;
-
- if(FLASH_BOOT == FLASH_BOOT_Bank1)
- {
- OB->USER |= OB_USER_BFB2;
- }
- else
- {
- OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));
- }
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(ProgramTimeout);
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= CR_OPTPG_Reset;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-#endif /* STM32F10X_XL */
-
-/**
- * @brief Returns the FLASH User Option Bytes values.
- * @note This function can be used for all STM32F10x devices.
- * @param None
- * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
- * and RST_STDBY(Bit2).
- */
-uint32_t FLASH_GetUserOptionByte(void)
-{
- /* Return the User Option Byte */
- return (uint32_t)(FLASH->OBR >> 2);
-}
-
-/**
- * @brief Returns the FLASH Write Protection Option Bytes Register value.
- * @note This function can be used for all STM32F10x devices.
- * @param None
- * @retval The FLASH Write Protection Option Bytes Register value
- */
-uint32_t FLASH_GetWriteProtectionOptionByte(void)
-{
- /* Return the Flash write protection Register value */
- return (uint32_t)(FLASH->WRPR);
-}
-
-/**
- * @brief Checks whether the FLASH Read Out Protection Status is set or not.
- * @note This function can be used for all STM32F10x devices.
- * @param None
- * @retval FLASH ReadOut Protection Status(SET or RESET)
- */
-FlagStatus FLASH_GetReadOutProtectionStatus(void)
-{
- FlagStatus readoutstatus = RESET;
- if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
- {
- readoutstatus = SET;
- }
- else
- {
- readoutstatus = RESET;
- }
- return readoutstatus;
-}
-
-/**
- * @brief Checks whether the FLASH Prefetch Buffer status is set or not.
- * @note This function can be used for all STM32F10x devices.
- * @param None
- * @retval FLASH Prefetch Buffer Status (SET or RESET).
- */
-FlagStatus FLASH_GetPrefetchBufferStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
- return bitstatus;
-}
-
-/**
- * @brief Enables or disables the specified FLASH interrupts.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts
- for Bank1 and Bank2.
- * - For other devices it enables or disables the specified FLASH interrupts for Bank1.
- * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_ERROR: FLASH Error Interrupt
- * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
- * @param NewState: new state of the specified Flash interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
-{
-#ifdef STM32F10X_XL
- /* Check the parameters */
- assert_param(IS_FLASH_IT(FLASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if((FLASH_IT & 0x80000000) != 0x0)
- {
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);
- }
- }
- else
- {
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR |= FLASH_IT;
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR &= ~(uint32_t)FLASH_IT;
- }
- }
-#else
- /* Check the parameters */
- assert_param(IS_FLASH_IT(FLASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR |= FLASH_IT;
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR &= ~(uint32_t)FLASH_IT;
- }
-#endif /* STM32F10X_XL */
-}
-
-/**
- * @brief Checks whether the specified FLASH flag is set or not.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices, this function checks whether the specified
- * Bank1 or Bank2 flag is set or not.
- * - For other devices, it checks whether the specified Bank1 flag is
- * set or not.
- * @param FLASH_FLAG: specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg FLASH_FLAG_BSY: FLASH Busy flag
- * @arg FLASH_FLAG_PGERR: FLASH Program error flag
- * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag
- * @retval The new state of FLASH_FLAG (SET or RESET).
- */
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
-#ifdef STM32F10X_XL
- /* Check the parameters */
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
- if(FLASH_FLAG == FLASH_FLAG_OPTERR)
- {
- if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- else
- {
- if((FLASH_FLAG & 0x80000000) != 0x0)
- {
- if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- }
-#else
- /* Check the parameters */
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
- if(FLASH_FLAG == FLASH_FLAG_OPTERR)
- {
- if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
-#endif /* STM32F10X_XL */
-
- /* Return the new state of FLASH_FLAG (SET or RESET) */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FLASH's pending flags.
- * @note This function can be used for all STM32F10x devices.
- * - For STM32F10X_XL devices, this function clears Bank1 or Bank2’s pending flags
- * - For other devices, it clears Bank1’s pending flags.
- * @param FLASH_FLAG: specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_PGERR: FLASH Program error flag
- * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @retval None
- */
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)
-{
-#ifdef STM32F10X_XL
- /* Check the parameters */
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
-
- if((FLASH_FLAG & 0x80000000) != 0x0)
- {
- /* Clear the flags */
- FLASH->SR2 = FLASH_FLAG;
- }
- else
- {
- /* Clear the flags */
- FLASH->SR = FLASH_FLAG;
- }
-
-#else
- /* Check the parameters */
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
-
- /* Clear the flags */
- FLASH->SR = FLASH_FLAG;
-#endif /* STM32F10X_XL */
-}
-
-/**
- * @brief Returns the FLASH Status.
- * @note This function can be used for all STM32F10x devices, it is equivalent
- * to FLASH_GetBank1Status function.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
- * FLASH_ERROR_WRP or FLASH_COMPLETE
- */
-FLASH_Status FLASH_GetStatus(void)
-{
- FLASH_Status flashstatus = FLASH_COMPLETE;
-
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
- {
- flashstatus = FLASH_BUSY;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_PGERR) != 0)
- {
- flashstatus = FLASH_ERROR_PG;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )
- {
- flashstatus = FLASH_ERROR_WRP;
- }
- else
- {
- flashstatus = FLASH_COMPLETE;
- }
- }
- }
- /* Return the Flash Status */
- return flashstatus;
-}
-
-/**
- * @brief Returns the FLASH Bank1 Status.
- * @note This function can be used for all STM32F10x devices, it is equivalent
- * to FLASH_GetStatus function.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
- * FLASH_ERROR_WRP or FLASH_COMPLETE
- */
-FLASH_Status FLASH_GetBank1Status(void)
-{
- FLASH_Status flashstatus = FLASH_COMPLETE;
-
- if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
- {
- flashstatus = FLASH_BUSY;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)
- {
- flashstatus = FLASH_ERROR_PG;
- }
- else
- {
- if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )
- {
- flashstatus = FLASH_ERROR_WRP;
- }
- else
- {
- flashstatus = FLASH_COMPLETE;
- }
- }
- }
- /* Return the Flash Status */
- return flashstatus;
-}
-
-#ifdef STM32F10X_XL
-/**
- * @brief Returns the FLASH Bank2 Status.
- * @note This function can be used for STM32F10x_XL density devices.
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
- * FLASH_ERROR_WRP or FLASH_COMPLETE
- */
-FLASH_Status FLASH_GetBank2Status(void)
-{
- FLASH_Status flashstatus = FLASH_COMPLETE;
-
- if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF))
- {
- flashstatus = FLASH_BUSY;
- }
- else
- {
- if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)
- {
- flashstatus = FLASH_ERROR_PG;
- }
- else
- {
- if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )
- {
- flashstatus = FLASH_ERROR_WRP;
- }
- else
- {
- flashstatus = FLASH_COMPLETE;
- }
- }
- }
- /* Return the Flash Status */
- return flashstatus;
-}
-#endif /* STM32F10X_XL */
-/**
- * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
- * @note This function can be used for all STM32F10x devices,
- * it is equivalent to FLASH_WaitForLastBank1Operation.
- * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation
- * to complete or a TIMEOUT to occur.
- * - For all other devices it waits for a Flash operation to complete
- * or a TIMEOUT to occur.
- * @param Timeout: FLASH programming Timeout
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the Flash Status */
- status = FLASH_GetBank1Status();
- /* Wait for a Flash operation to complete or a TIMEOUT to occur */
- while((status == FLASH_BUSY) && (Timeout != 0x00))
- {
- status = FLASH_GetBank1Status();
- Timeout--;
- }
- if(Timeout == 0x00 )
- {
- status = FLASH_TIMEOUT;
- }
- /* Return the operation status */
- return status;
-}
-
-/**
- * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
- * @note This function can be used for all STM32F10x devices,
- * it is equivalent to FLASH_WaitForLastOperation.
- * @param Timeout: FLASH programming Timeout
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the Flash Status */
- status = FLASH_GetBank1Status();
- /* Wait for a Flash operation to complete or a TIMEOUT to occur */
- while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
- {
- status = FLASH_GetBank1Status();
- Timeout--;
- }
- if(Timeout == 0x00 )
- {
- status = FLASH_TIMEOUT;
- }
- /* Return the operation status */
- return status;
-}
-
-#ifdef STM32F10X_XL
-/**
- * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.
- * @note This function can be used only for STM32F10x_XL density devices.
- * @param Timeout: FLASH programming Timeout
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the Flash Status */
- status = FLASH_GetBank2Status();
- /* Wait for a Flash operation to complete or a TIMEOUT to occur */
- while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))
- {
- status = FLASH_GetBank2Status();
- Timeout--;
- }
- if(Timeout == 0x00 )
- {
- status = FLASH_TIMEOUT;
- }
- /* Return the operation status */
- return status;
-}
-#endif /* STM32F10X_XL */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c
deleted file mode 100644
index c75137ca..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c
+++ /dev/null
@@ -1,866 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_fsmc.c
- * @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
- * @brief This file provides all the FSMC firmware functions.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_rcc.h"
-
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup I2C
- * @brief I2C driver modules
- * @{
- */
-
-/** @defgroup I2C_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Private_Defines
- * @{
- */
-
-/* I2C SPE mask */
-#define CR1_PE_Set ((uint16_t)0x0001)
-#define CR1_PE_Reset ((uint16_t)0xFFFE)
-
-/* I2C START mask */
-#define CR1_START_Set ((uint16_t)0x0100)
-#define CR1_START_Reset ((uint16_t)0xFEFF)
-
-/* I2C STOP mask */
-#define CR1_STOP_Set ((uint16_t)0x0200)
-#define CR1_STOP_Reset ((uint16_t)0xFDFF)
-
-/* I2C ACK mask */
-#define CR1_ACK_Set ((uint16_t)0x0400)
-#define CR1_ACK_Reset ((uint16_t)0xFBFF)
-
-/* I2C ENGC mask */
-#define CR1_ENGC_Set ((uint16_t)0x0040)
-#define CR1_ENGC_Reset ((uint16_t)0xFFBF)
-
-/* I2C SWRST mask */
-#define CR1_SWRST_Set ((uint16_t)0x8000)
-#define CR1_SWRST_Reset ((uint16_t)0x7FFF)
-
-/* I2C PEC mask */
-#define CR1_PEC_Set ((uint16_t)0x1000)
-#define CR1_PEC_Reset ((uint16_t)0xEFFF)
-
-/* I2C ENPEC mask */
-#define CR1_ENPEC_Set ((uint16_t)0x0020)
-#define CR1_ENPEC_Reset ((uint16_t)0xFFDF)
-
-/* I2C ENARP mask */
-#define CR1_ENARP_Set ((uint16_t)0x0010)
-#define CR1_ENARP_Reset ((uint16_t)0xFFEF)
-
-/* I2C NOSTRETCH mask */
-#define CR1_NOSTRETCH_Set ((uint16_t)0x0080)
-#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
-
-/* I2C registers Masks */
-#define CR1_CLEAR_Mask ((uint16_t)0xFBF5)
-
-/* I2C DMAEN mask */
-#define CR2_DMAEN_Set ((uint16_t)0x0800)
-#define CR2_DMAEN_Reset ((uint16_t)0xF7FF)
-
-/* I2C LAST mask */
-#define CR2_LAST_Set ((uint16_t)0x1000)
-#define CR2_LAST_Reset ((uint16_t)0xEFFF)
-
-/* I2C FREQ mask */
-#define CR2_FREQ_Reset ((uint16_t)0xFFC0)
-
-/* I2C ADD0 mask */
-#define OAR1_ADD0_Set ((uint16_t)0x0001)
-#define OAR1_ADD0_Reset ((uint16_t)0xFFFE)
-
-/* I2C ENDUAL mask */
-#define OAR2_ENDUAL_Set ((uint16_t)0x0001)
-#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)
-
-/* I2C ADD2 mask */
-#define OAR2_ADD2_Reset ((uint16_t)0xFF01)
-
-/* I2C F/S mask */
-#define CCR_FS_Set ((uint16_t)0x8000)
-
-/* I2C CCR mask */
-#define CCR_CCR_Set ((uint16_t)0x0FFF)
-
-/* I2C FLAG mask */
-#define FLAG_Mask ((uint32_t)0x00FFFFFF)
-
-/* I2C Interrupt Enable mask */
-#define ITEN_Mask ((uint32_t)0x07000000)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval None
- */
-void I2C_DeInit(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- if (I2Cx == I2C1)
- {
- /* Enable I2C1 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
- /* Release I2C1 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
- }
- else
- {
- /* Enable I2C2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
- /* Release I2C2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
- }
-}
-
-/**
- * @brief Initializes the I2Cx peripheral according to the specified
- * parameters in the I2C_InitStruct.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
- * contains the configuration information for the specified I2C peripheral.
- * @retval None
- */
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
-{
- uint16_t tmpreg = 0, freqrange = 0;
- uint16_t result = 0x04;
- uint32_t pclk1 = 8000000;
- RCC_ClocksTypeDef rcc_clocks;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
- assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
-
-/*---------------------------- I2Cx CR2 Configuration ------------------------*/
- /* Get the I2Cx CR2 value */
- tmpreg = I2Cx->CR2;
- /* Clear frequency FREQ[5:0] bits */
- tmpreg &= CR2_FREQ_Reset;
- /* Get pclk1 frequency value */
- RCC_GetClocksFreq(&rcc_clocks);
- pclk1 = rcc_clocks.PCLK1_Frequency;
- /* Set frequency bits depending on pclk1 value */
- freqrange = (uint16_t)(pclk1 / 1000000);
- tmpreg |= freqrange;
- /* Write to I2Cx CR2 */
- I2Cx->CR2 = tmpreg;
-
-/*---------------------------- I2Cx CCR Configuration ------------------------*/
- /* Disable the selected I2C peripheral to configure TRISE */
- I2Cx->CR1 &= CR1_PE_Reset;
- /* Reset tmpreg value */
- /* Clear F/S, DUTY and CCR[11:0] bits */
- tmpreg = 0;
-
- /* Configure speed in standard mode */
- if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
- {
- /* Standard mode speed calculate */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
- /* Test if CCR value is under 0x4*/
- if (result < 0x04)
- {
- /* Set minimum allowed value */
- result = 0x04;
- }
- /* Set speed value for standard mode */
- tmpreg |= result;
- /* Set Maximum Rise Time for standard mode */
- I2Cx->TRISE = freqrange + 1;
- }
- /* Configure speed in fast mode */
- else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
- {
- if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
- {
- /* Fast mode speed calculate: Tlow/Thigh = 2 */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
- }
- else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
- {
- /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
- /* Set DUTY bit */
- result |= I2C_DutyCycle_16_9;
- }
-
- /* Test if CCR value is under 0x1*/
- if ((result & CCR_CCR_Set) == 0)
- {
- /* Set minimum allowed value */
- result |= (uint16_t)0x0001;
- }
- /* Set speed value and set F/S bit for fast mode */
- tmpreg |= (uint16_t)(result | CCR_FS_Set);
- /* Set Maximum Rise Time for fast mode */
- I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
- }
-
- /* Write to I2Cx CCR */
- I2Cx->CCR = tmpreg;
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= CR1_PE_Set;
-
-/*---------------------------- I2Cx CR1 Configuration ------------------------*/
- /* Get the I2Cx CR1 value */
- tmpreg = I2Cx->CR1;
- /* Clear ACK, SMBTYPE and SMBUS bits */
- tmpreg &= CR1_CLEAR_Mask;
- /* Configure I2Cx: mode and acknowledgement */
- /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
- /* Set ACK bit according to I2C_Ack value */
- tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
- /* Write to I2Cx CR1 */
- I2Cx->CR1 = tmpreg;
-
-/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
- /* Set I2Cx Own Address1 and acknowledged address */
- I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
-}
-
-/**
- * @brief Fills each I2C_InitStruct member with its default value.
- * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
-{
-/*---------------- Reset I2C init structure parameters values ----------------*/
- /* initialize the I2C_ClockSpeed member */
- I2C_InitStruct->I2C_ClockSpeed = 5000;
- /* Initialize the I2C_Mode member */
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
- /* Initialize the I2C_DutyCycle member */
- I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
- /* Initialize the I2C_OwnAddress1 member */
- I2C_InitStruct->I2C_OwnAddress1 = 0;
- /* Initialize the I2C_Ack member */
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
- /* Initialize the I2C_AcknowledgedAddress member */
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-}
-
-/**
- * @brief Enables or disables the specified I2C peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= CR1_PE_Set;
- }
- else
- {
- /* Disable the selected I2C peripheral */
- I2Cx->CR1 &= CR1_PE_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C DMA requests.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C DMA requests */
- I2Cx->CR2 |= CR2_DMAEN_Set;
- }
- else
- {
- /* Disable the selected I2C DMA requests */
- I2Cx->CR2 &= CR2_DMAEN_Reset;
- }
-}
-
-/**
- * @brief Specifies if the next DMA transfer will be the last one.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C DMA last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Next DMA transfer is the last transfer */
- I2Cx->CR2 |= CR2_LAST_Set;
- }
- else
- {
- /* Next DMA transfer is not the last transfer */
- I2Cx->CR2 &= CR2_LAST_Reset;
- }
-}
-
-/**
- * @brief Generates I2Cx communication START condition.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C START condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Generate a START condition */
- I2Cx->CR1 |= CR1_START_Set;
- }
- else
- {
- /* Disable the START condition generation */
- I2Cx->CR1 &= CR1_START_Reset;
- }
-}
-
-/**
- * @brief Generates I2Cx communication STOP condition.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C STOP condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Generate a STOP condition */
- I2Cx->CR1 |= CR1_STOP_Set;
- }
- else
- {
- /* Disable the STOP condition generation */
- I2Cx->CR1 &= CR1_STOP_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C acknowledge feature.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C Acknowledgement.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the acknowledgement */
- I2Cx->CR1 |= CR1_ACK_Set;
- }
- else
- {
- /* Disable the acknowledgement */
- I2Cx->CR1 &= CR1_ACK_Reset;
- }
-}
-
-/**
- * @brief Configures the specified I2C own address2.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Address: specifies the 7bit I2C own address2.
- * @retval None.
- */
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
-{
- uint16_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Get the old register value */
- tmpreg = I2Cx->OAR2;
-
- /* Reset I2Cx Own address2 bit [7:1] */
- tmpreg &= OAR2_ADD2_Reset;
-
- /* Set I2Cx Own address2 */
- tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
-
- /* Store the new register value */
- I2Cx->OAR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the specified I2C dual addressing mode.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C dual addressing mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable dual addressing mode */
- I2Cx->OAR2 |= OAR2_ENDUAL_Set;
- }
- else
- {
- /* Disable dual addressing mode */
- I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C general call feature.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C General call.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable generall call */
- I2Cx->CR1 |= CR1_ENGC_Set;
- }
- else
- {
- /* Disable generall call */
- I2Cx->CR1 &= CR1_ENGC_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C interrupts.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_BUF: Buffer interrupt mask
- * @arg I2C_IT_EVT: Event interrupt mask
- * @arg I2C_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified I2C interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C interrupts */
- I2Cx->CR2 |= I2C_IT;
- }
- else
- {
- /* Disable the selected I2C interrupts */
- I2Cx->CR2 &= (uint16_t)~I2C_IT;
- }
-}
-
-/**
- * @brief Sends a data byte through the I2Cx peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Data: Byte to be transmitted..
- * @retval None
- */
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Write in the DR register the data to be sent */
- I2Cx->DR = Data;
-}
-
-/**
- * @brief Returns the most recent received data by the I2Cx peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The value of the received data.
- */
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Return the data in the DR register */
- return (uint8_t)I2Cx->DR;
-}
-
-/**
- * @brief Transmits the address byte to select the slave device.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Address: specifies the slave address which will be transmitted
- * @param I2C_Direction: specifies whether the I2C device will be a
- * Transmitter or a Receiver. This parameter can be one of the following values
- * @arg I2C_Direction_Transmitter: Transmitter mode
- * @arg I2C_Direction_Receiver: Receiver mode
- * @retval None.
- */
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DIRECTION(I2C_Direction));
- /* Test on the direction to set/reset the read/write bit */
- if (I2C_Direction != I2C_Direction_Transmitter)
- {
- /* Set the address bit0 for read */
- Address |= OAR1_ADD0_Set;
- }
- else
- {
- /* Reset the address bit0 for write */
- Address &= OAR1_ADD0_Reset;
- }
- /* Send the address */
- I2Cx->DR = Address;
-}
-
-/**
- * @brief Reads the specified I2C register and returns its value.
- * @param I2C_Register: specifies the register to read.
- * This parameter can be one of the following values:
- * @arg I2C_Register_CR1: CR1 register.
- * @arg I2C_Register_CR2: CR2 register.
- * @arg I2C_Register_OAR1: OAR1 register.
- * @arg I2C_Register_OAR2: OAR2 register.
- * @arg I2C_Register_DR: DR register.
- * @arg I2C_Register_SR1: SR1 register.
- * @arg I2C_Register_SR2: SR2 register.
- * @arg I2C_Register_CCR: CCR register.
- * @arg I2C_Register_TRISE: TRISE register.
- * @retval The value of the read register.
- */
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_REGISTER(I2C_Register));
-
- tmp = (uint32_t) I2Cx;
- tmp += I2C_Register;
-
- /* Return the selected register value */
- return (*(__IO uint16_t *) tmp);
-}
-
-/**
- * @brief Enables or disables the specified I2C software reset.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C software reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Peripheral under reset */
- I2Cx->CR1 |= CR1_SWRST_Set;
- }
- else
- {
- /* Peripheral not under reset */
- I2Cx->CR1 &= CR1_SWRST_Reset;
- }
-}
-
-/**
- * @brief Selects the specified I2C NACK position in master receiver mode.
- * This function is useful in I2C Master Receiver mode when the number
- * of data to be received is equal to 2. In this case, this function
- * should be called (with parameter I2C_NACKPosition_Next) before data
- * reception starts,as described in the 2-byte reception procedure
- * recommended in Reference Manual in Section: Master receiver.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_NACKPosition: specifies the NACK position.
- * This parameter can be one of the following values:
- * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
- * received byte.
- * @arg I2C_NACKPosition_Current: indicates that current byte is the last
- * received byte.
- *
- * @note This function configures the same bit (POS) as I2C_PECPositionConfig()
- * but is intended to be used in I2C mode while I2C_PECPositionConfig()
- * is intended to used in SMBUS mode.
- *
- * @retval None
- */
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
-
- /* Check the input parameter */
- if (I2C_NACKPosition == I2C_NACKPosition_Next)
- {
- /* Next byte in shift register is the last received byte */
- I2Cx->CR1 |= I2C_NACKPosition_Next;
- }
- else
- {
- /* Current byte in shift register is the last received byte */
- I2Cx->CR1 &= I2C_NACKPosition_Current;
- }
-}
-
-/**
- * @brief Drives the SMBusAlert pin high or low for the specified I2C.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_SMBusAlert: specifies SMBAlert pin level.
- * This parameter can be one of the following values:
- * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
- * @arg I2C_SMBusAlert_High: SMBAlert pin driven high
- * @retval None
- */
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
- if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
- {
- /* Drive the SMBusAlert pin Low */
- I2Cx->CR1 |= I2C_SMBusAlert_Low;
- }
- else
- {
- /* Drive the SMBusAlert pin High */
- I2Cx->CR1 &= I2C_SMBusAlert_High;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C PEC transfer.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C PEC transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC transmission */
- I2Cx->CR1 |= CR1_PEC_Set;
- }
- else
- {
- /* Disable the selected I2C PEC transmission */
- I2Cx->CR1 &= CR1_PEC_Reset;
- }
-}
-
-/**
- * @brief Selects the specified I2C PEC position.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_PECPosition: specifies the PEC position.
- * This parameter can be one of the following values:
- * @arg I2C_PECPosition_Next: indicates that the next byte is PEC
- * @arg I2C_PECPosition_Current: indicates that current byte is PEC
- *
- * @note This function configures the same bit (POS) as I2C_NACKPositionConfig()
- * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig()
- * is intended to used in I2C mode.
- *
- * @retval None
- */
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
- if (I2C_PECPosition == I2C_PECPosition_Next)
- {
- /* Next byte in shift register is PEC */
- I2Cx->CR1 |= I2C_PECPosition_Next;
- }
- else
- {
- /* Current byte in shift register is PEC */
- I2Cx->CR1 &= I2C_PECPosition_Current;
- }
-}
-
-/**
- * @brief Enables or disables the PEC value calculation of the transferred bytes.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx PEC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C PEC calculation */
- I2Cx->CR1 |= CR1_ENPEC_Set;
- }
- else
- {
- /* Disable the selected I2C PEC calculation */
- I2Cx->CR1 &= CR1_ENPEC_Reset;
- }
-}
-
-/**
- * @brief Returns the PEC value for the specified I2C.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The PEC value.
- */
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- /* Return the selected I2C PEC value */
- return ((I2Cx->SR2) >> 8);
-}
-
-/**
- * @brief Enables or disables the specified I2C ARP.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx ARP.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C ARP */
- I2Cx->CR1 |= CR1_ENARP_Set;
- }
- else
- {
- /* Disable the selected I2C ARP */
- I2Cx->CR1 &= CR1_ENARP_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C Clock stretching.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Clock stretching.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState == DISABLE)
- {
- /* Enable the selected I2C Clock stretching */
- I2Cx->CR1 |= CR1_NOSTRETCH_Set;
- }
- else
- {
- /* Disable the selected I2C Clock stretching */
- I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
- }
-}
-
-/**
- * @brief Selects the specified I2C fast mode duty cycle.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_DutyCycle: specifies the fast mode duty cycle.
- * This parameter can be one of the following values:
- * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
- * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
- * @retval None
- */
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
- if (I2C_DutyCycle != I2C_DutyCycle_16_9)
- {
- /* I2C fast mode Tlow/Thigh=2 */
- I2Cx->CCR &= I2C_DutyCycle_2;
- }
- else
- {
- /* I2C fast mode Tlow/Thigh=16/9 */
- I2Cx->CCR |= I2C_DutyCycle_16_9;
- }
-}
-
-
-
-/**
- * @brief
- ****************************************************************************************
- *
- * I2C State Monitoring Functions
- *
- ****************************************************************************************
- * This I2C driver provides three different ways for I2C state monitoring
- * depending on the application requirements and constraints:
- *
- *
- * 1) Basic state monitoring:
- * Using I2C_CheckEvent() function:
- * It compares the status registers (SR1 and SR2) content to a given event
- * (can be the combination of one or more flags).
- * It returns SUCCESS if the current status includes the given flags
- * and returns ERROR if one or more flags are missing in the current status.
- * - When to use:
- * - This function is suitable for most applications as well as for startup
- * activity since the events are fully described in the product reference manual
- * (RM0008).
- * - It is also suitable for users who need to define their own events.
- * - Limitations:
- * - If an error occurs (ie. error flags are set besides to the monitored flags),
- * the I2C_CheckEvent() function may return SUCCESS despite the communication
- * hold or corrupted real state.
- * In this case, it is advised to use error interrupts to monitor the error
- * events and handle them in the interrupt IRQ handler.
- *
- * @note
- * For error management, it is advised to use the following functions:
- * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
- * Where x is the peripheral instance (I2C1, I2C2 ...)
- * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
- * in order to determine which error occured.
- * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- * and/or I2C_GenerateStop() in order to clear the error flag and source,
- * and return to correct communication status.
- *
- *
- * 2) Advanced state monitoring:
- * Using the function I2C_GetLastEvent() which returns the image of both status
- * registers in a single word (uint32_t) (Status Register 2 value is shifted left
- * by 16 bits and concatenated to Status Register 1).
- * - When to use:
- * - This function is suitable for the same applications above but it allows to
- * overcome the mentioned limitation of I2C_GetFlagStatus() function.
- * The returned value could be compared to events already defined in the
- * library (stm32f10x_i2c.h) or to custom values defined by user.
- * - This function is suitable when multiple flags are monitored at the same time.
- * - At the opposite of I2C_CheckEvent() function, this function allows user to
- * choose when an event is accepted (when all events flags are set and no
- * other flags are set or just when the needed flags are set like
- * I2C_CheckEvent() function).
- * - Limitations:
- * - User may need to define his own events.
- * - Same remark concerning the error management is applicable for this
- * function if user decides to check only regular communication flags (and
- * ignores error flags).
- *
- *
- * 3) Flag-based state monitoring:
- * Using the function I2C_GetFlagStatus() which simply returns the status of
- * one single flag (ie. I2C_FLAG_RXNE ...).
- * - When to use:
- * - This function could be used for specific applications or in debug phase.
- * - It is suitable when only one flag checking is needed (most I2C events
- * are monitored through multiple flags).
- * - Limitations:
- * - When calling this function, the Status register is accessed. Some flags are
- * cleared when the status register is accessed. So checking the status
- * of one Flag, may clear other ones.
- * - Function may need to be called twice or more in order to monitor one
- * single event.
- *
- * For detailed description of Events, please refer to section I2C_Events in
- * stm32f10x_i2c.h file.
- *
- */
-
-/**
- *
- * 1) Basic state monitoring
- *******************************************************************************
- */
-
-/**
- * @brief Checks whether the last I2Cx Event is equal to the one passed
- * as parameter.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_EVENT: specifies the event to be checked.
- * This parameter can be one of the following values:
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1
- * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1
- * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1
- * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1
- * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2
- * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
- * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2
- * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4
- * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5
- * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6
- * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6
- * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2
- * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
- *
- * @note: For detailed description of Events, please refer to section
- * I2C_Events in stm32f10x_i2c.h file.
- *
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Last event is equal to the I2C_EVENT
- * - ERROR: Last event is different from the I2C_EVENT
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
-{
- uint32_t lastevent = 0;
- uint32_t flag1 = 0, flag2 = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_EVENT(I2C_EVENT));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
- flag2 = I2Cx->SR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_Mask;
-
- /* Check whether the last event contains the I2C_EVENT */
- if ((lastevent & I2C_EVENT) == I2C_EVENT)
- {
- /* SUCCESS: last event is equal to I2C_EVENT */
- status = SUCCESS;
- }
- else
- {
- /* ERROR: last event is different from I2C_EVENT */
- status = ERROR;
- }
- /* Return status */
- return status;
-}
-
-/**
- *
- * 2) Advanced state monitoring
- *******************************************************************************
- */
-
-/**
- * @brief Returns the last I2Cx Event.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- *
- * @note: For detailed description of Events, please refer to section
- * I2C_Events in stm32f10x_i2c.h file.
- *
- * @retval The last event
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
-{
- uint32_t lastevent = 0;
- uint32_t flag1 = 0, flag2 = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->SR1;
- flag2 = I2Cx->SR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- lastevent = (flag1 | flag2) & FLAG_Mask;
-
- /* Return status */
- return lastevent;
-}
-
-/**
- *
- * 3) Flag-based state monitoring
- *******************************************************************************
- */
-
-/**
- * @brief Checks whether the specified I2C flag is set or not.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
- * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
- * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
- * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
- * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
- * @arg I2C_FLAG_BUSY: Bus busy flag
- * @arg I2C_FLAG_MSL: Master/Slave flag
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
- * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
- * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
- * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
- * @arg I2C_FLAG_BTF: Byte transfer finished flag
- * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
- * Address matched flag (Slave mode)"ENDA"
- * @arg I2C_FLAG_SB: Start bit flag (Master mode)
- * @retval The new state of I2C_FLAG (SET or RESET).
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- FlagStatus bitstatus = RESET;
- __IO uint32_t i2creg = 0, i2cxbase = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
-
- /* Get the I2Cx peripheral base address */
- i2cxbase = (uint32_t)I2Cx;
-
- /* Read flag register index */
- i2creg = I2C_FLAG >> 28;
-
- /* Get bit[23:0] of the flag */
- I2C_FLAG &= FLAG_Mask;
-
- if(i2creg != 0)
- {
- /* Get the I2Cx SR1 register address */
- i2cxbase += 0x14;
- }
- else
- {
- /* Flag in I2Cx SR2 Register */
- I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
- /* Get the I2Cx SR2 register address */
- i2cxbase += 0x18;
- }
-
- if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
- {
- /* I2C_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the I2C_FLAG status */
- return bitstatus;
-}
-
-
-
-/**
- * @brief Clears the I2Cx's pending flags.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- *
- * @note
- * - STOPF (STOP detection) is cleared by software sequence: a read operation
- * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
- * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
- * - ADD10 (10-bit header sent) is cleared by software sequence: a read
- * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
- * second byte of the address in DR register.
- * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
- * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
- * read/write to I2C_DR register (I2C_SendData()).
- * - ADDR (Address sent) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
- * I2C_SR2 register ((void)(I2Cx->SR2)).
- * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
- * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
- * register (I2C_SendData()).
- * @retval None
- */
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- uint32_t flagpos = 0;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
- /* Get the I2C flag position */
- flagpos = I2C_FLAG & FLAG_Mask;
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @brief Checks whether the specified I2C interrupt has occurred or not.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2C_IT_SMBALERT: SMBus Alert flag
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_IT_PECERR: PEC error in reception flag
- * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_IT_AF: Acknowledge failure flag
- * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_IT_BERR: Bus error flag
- * @arg I2C_IT_TXE: Data register empty flag (Transmitter)
- * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
- * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
- * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
- * @arg I2C_IT_BTF: Byte transfer finished flag
- * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
- * Address matched flag (Slave mode)"ENDAD"
- * @arg I2C_IT_SB: Start bit flag (Master mode)
- * @retval The new state of I2C_IT (SET or RESET).
- */
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_IT(I2C_IT));
-
- /* Check if the interrupt source is enabled or not */
- enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
-
- /* Get bit[23:0] of the flag */
- I2C_IT &= FLAG_Mask;
-
- /* Check the status of the specified I2C flag */
- if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
- {
- /* I2C_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_IT is reset */
- bitstatus = RESET;
- }
- /* Return the I2C_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx’s interrupt pending bits.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_SMBALERT: SMBus Alert interrupt
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
- * @arg I2C_IT_PECERR: PEC error in reception interrupt
- * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
- * @arg I2C_IT_AF: Acknowledge failure interrupt
- * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
- * @arg I2C_IT_BERR: Bus error interrupt
- *
- * @note
- * - STOPF (STOP detection) is cleared by software sequence: a read operation
- * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
- * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
- * - ADD10 (10-bit header sent) is cleared by software sequence: a read
- * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
- * byte of the address in I2C_DR register.
- * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
- * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
- * read/write to I2C_DR register (I2C_SendData()).
- * - ADDR (Address sent) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
- * I2C_SR2 register ((void)(I2Cx->SR2)).
- * - SB (Start Bit) is cleared by software sequence: a read operation to
- * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
- * I2C_DR register (I2C_SendData()).
- * @retval None
- */
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- uint32_t flagpos = 0;
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));
- /* Get the I2C flag position */
- flagpos = I2C_IT & FLAG_Mask;
- /* Clear the selected I2C flag */
- I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
deleted file mode 100644
index 9d3b0e85..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_iwdg.c
- * @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
- * @brief This file provides all the IWDG firmware functions.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_tim.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup TIM
- * @brief TIM driver modules
- * @{
- */
-
-/** @defgroup TIM_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Defines
- * @{
- */
-
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define SMCR_ETR_Mask ((uint16_t)0x00FF)
-#define CCMR_Offset ((uint16_t)0x0018)
-#define CCER_CCE_Set ((uint16_t)0x0001)
-#define CCER_CCNE_Set ((uint16_t)0x0004)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_FunctionPrototypes
- * @{
- */
-
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @retval None
- */
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- if (TIMx == TIM1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
- }
- else if (TIMx == TIM2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
- }
- else if (TIMx == TIM3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
- }
- else if (TIMx == TIM4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
- }
- else if (TIMx == TIM5)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
- }
- else if (TIMx == TIM6)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
- }
- else if (TIMx == TIM7)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
- }
- else if (TIMx == TIM8)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
- }
- else if (TIMx == TIM9)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
- }
- else if (TIMx == TIM10)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
- }
- else if (TIMx == TIM11)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
- }
- else if (TIMx == TIM12)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
- }
- else if (TIMx == TIM13)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
- }
- else if (TIMx == TIM14)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
- }
- else if (TIMx == TIM15)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
- }
- else if (TIMx == TIM16)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
- }
- else
- {
- if (TIMx == TIM17)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the TIMx Time Base Unit peripheral according to
- * the specified parameters in the TIM_TimeBaseInitStruct.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
- * structure that contains the configuration information for the
- * specified TIM peripheral.
- * @retval None
- */
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
- tmpcr1 = TIMx->CR1;
-
- if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
- (TIMx == TIM4) || (TIMx == TIM5))
- {
- /* Select the Counter Mode */
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
- }
-
- if((TIMx != TIM6) && (TIMx != TIM7))
- {
- /* Set the clock division */
- tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
- }
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-
- if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler and the Repetition counter
- values immediately */
- TIMx->EGR = TIM_PSCReloadMode_Immediate;
-}
-
-/**
- * @brief Initializes the TIMx Channel1 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
- /* Set the Output Compare Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-
- /* Set the Output State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-
- if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
- (TIMx == TIM16)|| (TIMx == TIM17))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
- /* Set the Output N Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
-
- /* Reset the Output N State */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
- /* Set the Output N State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
-
- /* Set the Output Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel2 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
- * the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
-
- /* Reset the Output N State */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
-
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel3 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
- /* Reset the Output N State */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
-
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel4 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 2: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIM peripheral according to the specified
- * parameters in the TIM_ICInitStruct.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
-
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
- (TIMx == TIM4) ||(TIMx == TIM5))
- {
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
- }
- else
- {
- assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
- }
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
- {
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
- {
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* TI3 Configuration */
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* TI4 Configuration */
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Configures the TIM peripheral according to the specified
- * parameters in the TIM_ICInitStruct to measure an external PWM signal.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* Select the Opposite Input Polarity */
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
- {
- icoppositepolarity = TIM_ICPolarity_Falling;
- }
- else
- {
- icoppositepolarity = TIM_ICPolarity_Rising;
- }
- /* Select the Opposite Input */
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
- {
- icoppositeselection = TIM_ICSelection_IndirectTI;
- }
- else
- {
- icoppositeselection = TIM_ICSelection_DirectTI;
- }
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI2 Configuration */
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI1 Configuration */
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
- * the OSSR State and the AOE(automatic output enable).
- * @param TIMx: where x can be 1 or 8 to select the TIM
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @retval None
- */
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
- assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
- assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
- assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
- assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
- /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
- TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
- TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
- TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
- TIM_BDTRInitStruct->TIM_AutomaticOutput;
-}
-
-/**
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
- * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- /* Set the default configuration */
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
-}
-
-/**
- * @brief Fills each TIM_OCInitStruct member with its default value.
- * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- /* Set the default configuration */
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
- TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
- TIM_OCInitStruct->TIM_Pulse = 0x0000;
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
- TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-/**
- * @brief Fills each TIM_ICInitStruct member with its default value.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
- TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/**
- * @brief Fills each TIM_BDTRInitStruct member with its default value.
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
- TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
- TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
- TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
- TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
- TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
- TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-/**
- * @brief Enables or disables the specified TIM peripheral.
- * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
- * @param NewState: new state of the TIMx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Counter */
- TIMx->CR1 |= TIM_CR1_CEN;
- }
- else
- {
- /* Disable the TIM Counter */
- TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
- }
-}
-
-/**
- * @brief Enables or disables the TIM peripheral Main Outputs.
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
- * @param NewState: new state of the TIM peripheral Main Outputs.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the TIM Main Output */
- TIMx->BDTR |= TIM_BDTR_MOE;
- }
- else
- {
- /* Disable the TIM Main Output */
- TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
- }
-}
-
-/**
- * @brief Enables or disables the specified TIM interrupts.
- * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- * @note
- * - TIM6 and TIM7 can only generate an update interrupt.
- * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
- * TIM_IT_CC2 or TIM_IT_Trigger.
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
- * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
- * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- TIMx->DIER |= TIM_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- TIMx->DIER &= (uint16_t)~TIM_IT;
- }
-}
-
-/**
- * @brief Configures the TIMx event to be generate by software.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_EventSource: specifies the event source.
- * This parameter can be one or more of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_COM: Timer COM event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @arg TIM_EventSource_Break: Timer Break event source
- * @note
- * - TIM6 and TIM7 can only generate an update event.
- * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
- * @retval None
- */
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
-
- /* Set the event sources */
- TIMx->EGR = TIM_EventSource;
-}
-
-/**
- * @brief Configures the TIMx's DMA interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
- * the TIM peripheral.
- * @param TIM_DMABase: DMA Base address.
- * This parameter can be one of the following values:
- * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
- * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
- * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
- * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
- * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
- * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
- * TIM_DMABase_DCR.
- * @param TIM_DMABurstLength: DMA Burst length.
- * This parameter can be one value between:
- * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
- * @retval None
- */
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
- /* Set the DMA Base and the DMA Burst Length */
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/**
- * @brief Enables or disables the TIMx's DMA Requests.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17
- * to select the TIM peripheral.
- * @param TIM_DMASource: specifies the DMA Request sources.
- * This parameter can be any combination of the following values:
- * @arg TIM_DMA_Update: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST9_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA sources */
- TIMx->DIER |= TIM_DMASource;
- }
- else
- {
- /* Disable the DMA sources */
- TIMx->DIER &= (uint16_t)~TIM_DMASource;
- }
-}
-
-/**
- * @brief Configures the TIMx internal Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15
- * to select the TIM peripheral.
- * @retval None
- */
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-}
-
-/**
- * @brief Configures the TIMx Internal Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_ITRSource: Trigger source.
- * This parameter can be one of the following values:
- * @param TIM_TS_ITR0: Internal Trigger 0
- * @param TIM_TS_ITR1: Internal Trigger 1
- * @param TIM_TS_ITR2: Internal Trigger 2
- * @param TIM_TS_ITR3: Internal Trigger 3
- * @retval None
- */
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
- /* Select the Internal Trigger */
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the TIMx Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_TIxExternalCLKSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
- * @param TIM_ICPolarity: specifies the TIx Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param ICFilter : specifies the filter value.
- * This parameter must be a value between 0x0 and 0xF.
- * @retval None
- */
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
- assert_param(IS_TIM_IC_FILTER(ICFilter));
- /* Configure the Timer Input Clock Source */
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
- {
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- else
- {
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- /* Select the Trigger source */
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the External clock Mode1
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the SMS Bits */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
- /* Select the External clock mode1 */
- tmpsmcr |= TIM_SlaveMode_External1;
- /* Select the Trigger selection : ETRF */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
- tmpsmcr |= TIM_TS_ETRF;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the External clock Mode2
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
- /* Enable the External clock mode2 */
- TIMx->SMCR |= TIM_SMCR_ECE;
-}
-
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
- tmpsmcr = TIMx->SMCR;
- /* Reset the ETR Bits */
- tmpsmcr &= SMCR_ETR_Mask;
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the TIMx Prescaler.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param Prescaler: specifies the Prescaler Register value
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
- * This parameter can be one of the following values:
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
- * @retval None
- */
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
- /* Set the Prescaler value */
- TIMx->PSC = Prescaler;
- /* Set or reset the UG Bit */
- TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/**
- * @brief Specifies the TIMx Counter Mode to be used.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_CounterMode: specifies the Counter Mode to be used
- * This parameter can be one of the following values:
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
- * @retval None
- */
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
-{
- uint16_t tmpcr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
- tmpcr1 = TIMx->CR1;
- /* Reset the CMS and DIR Bits */
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
- /* Set the Counter Mode */
- tmpcr1 |= TIM_CounterMode;
- /* Write to TIMx CR1 register */
- TIMx->CR1 = tmpcr1;
-}
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_InputTriggerSource: The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- uint16_t tmpsmcr = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
- /* Set the Input Trigger source */
- tmpsmcr |= TIM_InputTriggerSource;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the TIMx Encoder Interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
- * This parameter can be one of the following values:
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
- * on the level of the other input.
- * @param TIM_IC1Polarity: specifies the IC1 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @param TIM_IC2Polarity: specifies the IC2 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @retval None
- */
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
-{
- uint16_t tmpsmcr = 0;
- uint16_t tmpccmr1 = 0;
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
- tmpsmcr |= TIM_EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Forces the TIMx output 1 waveform to active or inactive level.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
- * @retval None
- */
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1M Bits */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
- /* Configure The Forced output Mode */
- tmpccmr1 |= TIM_ForcedAction;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 2 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
- * @retval None
- */
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2M Bits */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
- /* Configure The Forced output Mode */
- tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 3 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
- * @retval None
- */
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC1M Bits */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
- /* Configure The Forced output Mode */
- tmpccmr2 |= TIM_ForcedAction;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Forces the TIMx output 4 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
- * @retval None
- */
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC2M Bits */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
- /* Configure The Forced output Mode */
- tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables TIMx peripheral Preload register on ARR.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param NewState: new state of the TIMx peripheral Preload register
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the ARR Preload Bit */
- TIMx->CR1 |= TIM_CR1_ARPE;
- }
- else
- {
- /* Reset the ARR Preload Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
- }
-}
-
-/**
- * @brief Selects the TIM peripheral Commutation event.
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
- * @param NewState: new state of the Commutation event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the COM Bit */
- TIMx->CR2 |= TIM_CR2_CCUS;
- }
- else
- {
- /* Reset the COM Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
- }
-}
-
-/**
- * @brief Selects the TIMx peripheral Capture Compare DMA source.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
- * the TIM peripheral.
- * @param NewState: new state of the Capture Compare DMA source
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the CCDS Bit */
- TIMx->CR2 |= TIM_CR2_CCDS;
- }
- else
- {
- /* Reset the CCDS Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
- }
-}
-
-/**
- * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15
- * to select the TIMx peripheral
- * @param NewState: new state of the Capture Compare Preload Control bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the CCPC Bit */
- TIMx->CR2 |= TIM_CR2_CCPC;
- }
- else
- {
- /* Reset the CCPC Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
- }
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1PE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= TIM_OCPreload;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
- * the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2PE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3PE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= TIM_OCPreload;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4PE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 1 Fast feature.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1FE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= TIM_OCFast;
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 2 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
- * the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2FE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 3 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3FE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= TIM_OCFast;
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 4 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4FE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF1 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1CE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= TIM_OCClear;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF2 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2CE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF3 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3CE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= TIM_OCClear;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF4 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4CE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx channel 1 polarity.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC1 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC1P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
- tmpccer |= TIM_OCPolarity;
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 1N polarity.
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC1N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC1NP Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
- tmpccer |= TIM_OCNPolarity;
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 2 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC2 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC2P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 2N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC2N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC2NP Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 3 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC3 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC3P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 3N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC3N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC3NP Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 4 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC4 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC4P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCX(TIM_CCx));
-
- tmp = CCER_CCE_Set << TIM_Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t)~ tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
- * @retval None
- */
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCXN(TIM_CCxN));
-
- tmp = CCER_CCNE_Set << TIM_Channel;
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= (uint16_t) ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
-}
-
-/**
- * @brief Selects the TIM Output Compare Mode.
- * @note This function disables the selected channel before changing the Output
- * Compare Mode.
- * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.
- * This parameter can be one of the following values:
- * @arg TIM_OCMode_Timing
- * @arg TIM_OCMode_Active
- * @arg TIM_OCMode_Toggle
- * @arg TIM_OCMode_PWM1
- * @arg TIM_OCMode_PWM2
- * @arg TIM_ForcedAction_Active
- * @arg TIM_ForcedAction_InActive
- * @retval None
- */
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
-{
- uint32_t tmp = 0;
- uint16_t tmp1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_OCM(TIM_OCMode));
-
- tmp = (uint32_t) TIMx;
- tmp += CCMR_Offset;
-
- tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
-
- /* Disable the Channel: Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t) ~tmp1;
-
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
- {
- tmp += (TIM_Channel>>1);
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= TIM_OCMode;
- }
- else
- {
- tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
- }
-}
-
-/**
- * @brief Enables or Disables the TIMx Update event.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param NewState: new state of the TIMx UDIS bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the Update Disable Bit */
- TIMx->CR1 |= TIM_CR1_UDIS;
- }
- else
- {
- /* Reset the Update Disable Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
- }
-}
-
-/**
- * @brief Configures the TIMx Update Request Interrupt source.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_UpdateSource: specifies the Update source.
- * This parameter can be one of the following values:
- * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
- or the setting of UG bit, or an update generation
- through the slave mode controller.
- * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
- * @retval None
- */
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
- if (TIM_UpdateSource != TIM_UpdateSource_Global)
- {
- /* Set the URS Bit */
- TIMx->CR1 |= TIM_CR1_URS;
- }
- else
- {
- /* Reset the URS Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
- }
-}
-
-/**
- * @brief Enables or disables the TIMx's Hall sensor interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param NewState: new state of the TIMx Hall sensor interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the TI1S Bit */
- TIMx->CR2 |= TIM_CR2_TI1S;
- }
- else
- {
- /* Reset the TI1S Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
- }
-}
-
-/**
- * @brief Selects the TIMx's One Pulse Mode.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_OPMode: specifies the OPM Mode to be used.
- * This parameter can be one of the following values:
- * @arg TIM_OPMode_Single
- * @arg TIM_OPMode_Repetitive
- * @retval None
- */
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
- /* Reset the OPM Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
- /* Configure the OPM Mode */
- TIMx->CR1 |= TIM_OPMode;
-}
-
-/**
- * @brief Selects the TIMx Trigger Output Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_TRGOSource: specifies the Trigger Output source.
- * This paramter can be one of the following values:
- *
- * - For all TIMx
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
- *
- * - For all TIMx except TIM6 and TIM7
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
- * is to be set, as soon as a capture or compare match occurs (TRGO).
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
- *
- * @retval None
- */
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST7_PERIPH(TIMx));
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
- /* Reset the MMS Bits */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
- /* Select the TRGO source */
- TIMx->CR2 |= TIM_TRGOSource;
-}
-
-/**
- * @brief Selects the TIMx Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
- * the counter and triggers an update of the registers.
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
- * @retval None
- */
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
- /* Reset the SMS Bits */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
- /* Select the Slave Mode */
- TIMx->SMCR |= TIM_SlaveMode;
-}
-
-/**
- * @brief Sets or Resets the TIMx Master/Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
- * and its slaves (through TRGO).
- * @arg TIM_MasterSlaveMode_Disable: No action
- * @retval None
- */
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
- /* Reset the MSM Bit */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
-
- /* Set or Reset the MSM Bit */
- TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/**
- * @brief Sets the TIMx Counter Register value
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param Counter: specifies the Counter register new value.
- * @retval None
- */
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- /* Set the Counter Register value */
- TIMx->CNT = Counter;
-}
-
-/**
- * @brief Sets the TIMx Autoreload Register value
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param Autoreload: specifies the Autoreload register new value.
- * @retval None
- */
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- /* Set the Autoreload Register value */
- TIMx->ARR = Autoreload;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare1 Register value
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param Compare1: specifies the Capture Compare1 register new value.
- * @retval None
- */
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- /* Set the Capture Compare1 Register value */
- TIMx->CCR1 = Compare1;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare2 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param Compare2: specifies the Capture Compare2 register new value.
- * @retval None
- */
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* Set the Capture Compare2 Register value */
- TIMx->CCR2 = Compare2;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare3 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare3: specifies the Capture Compare3 register new value.
- * @retval None
- */
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* Set the Capture Compare3 Register value */
- TIMx->CCR3 = Compare3;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare4 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare4: specifies the Capture Compare4 register new value.
- * @retval None
- */
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* Set the Capture Compare4 Register value */
- TIMx->CCR4 = Compare4;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 1 prescaler.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
- /* Reset the IC1PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
- /* Set the IC1PSC value */
- TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 2 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
- /* Reset the IC2PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
- /* Set the IC2PSC value */
- TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @brief Sets the TIMx Input Capture 3 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
- /* Reset the IC3PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
- /* Set the IC3PSC value */
- TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 4 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
- /* Reset the IC4PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
- /* Set the IC4PSC value */
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @brief Sets the TIMx Clock Division value.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select
- * the TIM peripheral.
- * @param TIM_CKD: specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
- * @retval None
- */
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));
- /* Reset the CKD Bits */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
- /* Set the CKD value */
- TIMx->CR1 |= TIM_CKD;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 1 value.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @retval Capture Compare 1 Register value.
- */
-uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- /* Get the Capture 1 Register value */
- return TIMx->CCR1;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 2 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @retval Capture Compare 2 Register value.
- */
-uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* Get the Capture 2 Register value */
- return TIMx->CCR2;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 3 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @retval Capture Compare 3 Register value.
- */
-uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* Get the Capture 3 Register value */
- return TIMx->CCR3;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 4 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @retval Capture Compare 4 Register value.
- */
-uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* Get the Capture 4 Register value */
- return TIMx->CCR4;
-}
-
-/**
- * @brief Gets the TIMx Counter value.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @retval Counter Register value.
- */
-uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- /* Get the Counter Register value */
- return TIMx->CNT;
-}
-
-/**
- * @brief Gets the TIMx Prescaler value.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @retval Prescaler Register value.
- */
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- /* Get the Prescaler Register value */
- return TIMx->PSC;
-}
-
-/**
- * @brief Checks whether the specified TIM flag is set or not.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
- * @note
- * - TIM6 and TIM7 can have only one update flag.
- * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
- * TIM_FLAG_CC2 or TIM_FLAG_Trigger.
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
- * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
- * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
- * @retval The new state of TIM_FLAG (SET or RESET).
- */
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
-
- if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's pending flags.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
- * @note
- * - TIM6 and TIM7 can have only one update flag.
- * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
- * TIM_FLAG_CC2 or TIM_FLAG_Trigger.
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
- * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
- * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
- * @retval None
- */
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
-
- /* Clear the flags */
- TIMx->SR = (uint16_t)~TIM_FLAG;
-}
-
-/**
- * @brief Checks whether the TIM interrupt has occurred or not.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_IT: specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- * @note
- * - TIM6 and TIM7 can generate only an update interrupt.
- * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
- * TIM_IT_CC2 or TIM_IT_Trigger.
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
- * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
- * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
- * @retval The new state of the TIM_IT(SET or RESET).
- */
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itstatus = 0x0, itenable = 0x0;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_IT(TIM_IT));
-
- itstatus = TIMx->SR & TIM_IT;
-
- itenable = TIMx->DIER & TIM_IT;
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's interrupt pending bits.
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
- * @param TIM_IT: specifies the pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM1 update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- * @note
- * - TIM6 and TIM7 can generate only an update interrupt.
- * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
- * TIM_IT_CC2 or TIM_IT_Trigger.
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
- * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
- * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
- * @retval None
- */
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
- /* Clear the IT pending Bit */
- TIMx->SR = (uint16_t)~TIM_IT;
-}
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0;
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- /* Select the Input and set the filter */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
- tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
- (TIMx == TIM4) ||(TIMx == TIM5))
- {
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
- }
- else
- {
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
- }
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 4);
- /* Select the Input and set the filter */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
- tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
- tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
-
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
- (TIMx == TIM4) ||(TIMx == TIM5))
- {
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
- }
- else
- {
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
- }
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 8);
- /* Select the Input and set the filter */
- tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
- (TIMx == TIM4) ||(TIMx == TIM5))
- {
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
- }
- else
- {
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
- }
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 12);
- /* Select the Input and set the filter */
- tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
-
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
- (TIMx == TIM4) ||(TIMx == TIM5))
- {
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
- }
- else
- {
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
- }
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
deleted file mode 100644
index a3f16f15..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
+++ /dev/null
@@ -1,1058 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_usart.c
- * @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
- * @brief This file provides all the USART firmware functions.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_usart.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup USART
- * @brief USART driver modules
- * @{
- */
-
-/** @defgroup USART_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Defines
- * @{
- */
-
-#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */
-#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */
-
-#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */
-
-#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */
-#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */
-#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */
-#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */
-#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */
-
-#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */
-#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */
-
-#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */
-#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */
-#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */
-
-#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */
-#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */
-
-#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */
-#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */
-
-#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */
-#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */
-
-#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */
-#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */
-
-#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */
-#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */
-#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */
-#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */
-#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */
-
-/* USART OverSampling-8 Mask */
-#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */
-#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */
-
-/* USART One Bit Sampling Mask */
-#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */
-#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @retval None
- */
-void USART_DeInit(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- if (USARTx == USART1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
- }
- else if (USARTx == USART2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
- }
- else if (USARTx == USART3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
- }
- else if (USARTx == UART4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
- }
- else
- {
- if (USARTx == UART5)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the USARTx peripheral according to the specified
- * parameters in the USART_InitStruct .
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
- * that contains the configuration information for the specified USART
- * peripheral.
- * @retval None
- */
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
- uint32_t tmpreg = 0x00, apbclock = 0x00;
- uint32_t integerdivider = 0x00;
- uint32_t fractionaldivider = 0x00;
- uint32_t usartxbase = 0;
- RCC_ClocksTypeDef RCC_ClocksStatus;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
- /* The hardware flow control is available only for USART1, USART2 and USART3 */
- if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
- {
- assert_param(IS_USART_123_PERIPH(USARTx));
- }
-
- usartxbase = (uint32_t)USARTx;
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear STOP[13:12] bits */
- tmpreg &= CR2_STOP_CLEAR_Mask;
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
- /* Set STOP[13:12] bits according to USART_StopBits value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
-
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = USARTx->CR1;
- /* Clear M, PCE, PS, TE and RE bits */
- tmpreg &= CR1_CLEAR_Mask;
- /* Configure the USART Word Length, Parity and mode ----------------------- */
- /* Set the M bits according to USART_WordLength value */
- /* Set PCE and PS bits according to USART_Parity value */
- /* Set TE and RE bits according to USART_Mode value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
- USART_InitStruct->USART_Mode;
- /* Write to USART CR1 */
- USARTx->CR1 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR3 Configuration -----------------------*/
- tmpreg = USARTx->CR3;
- /* Clear CTSE and RTSE bits */
- tmpreg &= CR3_CLEAR_Mask;
- /* Configure the USART HFC -------------------------------------------------*/
- /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
- /* Write to USART CR3 */
- USARTx->CR3 = (uint16_t)tmpreg;
-
-/*---------------------------- USART BRR Configuration -----------------------*/
- /* Configure the USART Baud Rate -------------------------------------------*/
- RCC_GetClocksFreq(&RCC_ClocksStatus);
- if (usartxbase == USART1_BASE)
- {
- apbclock = RCC_ClocksStatus.PCLK2_Frequency;
- }
- else
- {
- apbclock = RCC_ClocksStatus.PCLK1_Frequency;
- }
-
- /* Determine the integer part */
- if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
- {
- /* Integer part computing in case Oversampling mode is 8 Samples */
- integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
- }
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
- {
- /* Integer part computing in case Oversampling mode is 16 Samples */
- integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
- }
- tmpreg = (integerdivider / 100) << 4;
-
- /* Determine the fractional part */
- fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
-
- /* Implement the fractional part in the register */
- if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
- {
- tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
- }
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
- {
- tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
- }
-
- /* Write to USART BRR */
- USARTx->BRR = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_InitStruct member with its default value.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
- /* USART_InitStruct members default value */
- USART_InitStruct->USART_BaudRate = 9600;
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;
- USART_InitStruct->USART_StopBits = USART_StopBits_1;
- USART_InitStruct->USART_Parity = USART_Parity_No ;
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-}
-
-/**
- * @brief Initializes the USARTx peripheral Clock according to the
- * specified parameters in the USART_ClockInitStruct .
- * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure that contains the configuration information for the specified
- * USART peripheral.
- * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
- * @retval None
- */
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- uint32_t tmpreg = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear CLKEN, CPOL, CPHA and LBCL bits */
- tmpreg &= CR2_CLOCK_CLEAR_Mask;
- /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
- /* Set CLKEN bit according to USART_Clock value */
- /* Set CPOL bit according to USART_CPOL value */
- /* Set CPHA bit according to USART_CPHA value */
- /* Set LBCL bit according to USART_LastBit value */
- tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
- /* Write to USART CR2 */
- USARTx->CR2 = (uint16_t)tmpreg;
-}
-
-/**
- * @brief Fills each USART_ClockInitStruct member with its default value.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- /* USART_ClockInitStruct members default value */
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/**
- * @brief Enables or disables the specified USART peripheral.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USARTx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART by setting the UE bit in the CR1 register */
- USARTx->CR1 |= CR1_UE_Set;
- }
- else
- {
- /* Disable the selected USART by clearing the UE bit in the CR1 register */
- USARTx->CR1 &= CR1_UE_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the specified USART interrupts.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified USARTx interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
-{
- uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
- uint32_t usartxbase = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CONFIG_IT(USART_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_123_PERIPH(USARTx));
- }
-
- usartxbase = (uint32_t)USARTx;
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
-
- /* Get the interrupt position */
- itpos = USART_IT & IT_Mask;
- itmask = (((uint32_t)0x01) << itpos);
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- usartxbase += 0x0C;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- usartxbase += 0x10;
- }
- else /* The IT is in CR3 register */
- {
- usartxbase += 0x14;
- }
- if (NewState != DISABLE)
- {
- *(__IO uint32_t*)usartxbase |= itmask;
- }
- else
- {
- *(__IO uint32_t*)usartxbase &= ~itmask;
- }
-}
-
-/**
- * @brief Enables or disables the USART’s DMA interface.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_DMAReq: specifies the DMA request.
- * This parameter can be any combination of the following values:
- * @arg USART_DMAReq_Tx: USART DMA transmit request
- * @arg USART_DMAReq_Rx: USART DMA receive request
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @note The DMA mode is not available for UART5 except in the STM32
- * High density value line devices(STM32F10X_HD_VL).
- * @retval None
- */
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DMAREQ(USART_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 |= USART_DMAReq;
- }
- else
- {
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 &= (uint16_t)~USART_DMAReq;
- }
-}
-
-/**
- * @brief Sets the address of the USART node.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_Address: Indicates the address of the USART node.
- * @retval None
- */
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_ADDRESS(USART_Address));
-
- /* Clear the USART address */
- USARTx->CR2 &= CR2_Address_Mask;
- /* Set the USART address node */
- USARTx->CR2 |= USART_Address;
-}
-
-/**
- * @brief Selects the USART WakeUp method.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_WakeUp: specifies the USART wakeup method.
- * This parameter can be one of the following values:
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
- * @retval None
- */
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_WAKEUP(USART_WakeUp));
-
- USARTx->CR1 &= CR1_WAKE_Mask;
- USARTx->CR1 |= USART_WakeUp;
-}
-
-/**
- * @brief Determines if the USART is in mute mode or not.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USART mute mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
- USARTx->CR1 |= CR1_RWU_Set;
- }
- else
- {
- /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
- USARTx->CR1 &= CR1_RWU_Reset;
- }
-}
-
-/**
- * @brief Sets the USART LIN Break detection length.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
- * @retval None
- */
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-
- USARTx->CR2 &= CR2_LBDL_Mask;
- USARTx->CR2 |= USART_LINBreakDetectLength;
-}
-
-/**
- * @brief Enables or disables the USART’s LIN mode.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USART LIN mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- USARTx->CR2 |= CR2_LINEN_Set;
- }
- else
- {
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
- USARTx->CR2 &= CR2_LINEN_Reset;
- }
-}
-
-/**
- * @brief Transmits single data through the USARTx peripheral.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param Data: the data to transmit.
- * @retval None
- */
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DATA(Data));
-
- /* Transmit Data */
- USARTx->DR = (Data & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Returns the most recent received data by the USARTx peripheral.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @retval The received data.
- */
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Receive Data */
- return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Transmits break characters.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @retval None
- */
-void USART_SendBreak(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Send break characters */
- USARTx->CR1 |= CR1_SBK_Set;
-}
-
-/**
- * @brief Sets the specified USART guard time.
- * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
- * @param USART_GuardTime: specifies the guard time.
- * @note The guard time bits are not available for UART4 and UART5.
- * @retval None
- */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
-
- /* Clear the USART Guard time */
- USARTx->GTPR &= GTPR_LSB_Mask;
- /* Set the USART guard time */
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
- * @brief Sets the system clock prescaler.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_Prescaler: specifies the prescaler clock.
- * @note The function is used for IrDA mode with UART4 and UART5.
- * @retval None
- */
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Clear the USART prescaler */
- USARTx->GTPR &= GTPR_MSB_Mask;
- /* Set the USART prescaler */
- USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
- * @brief Enables or disables the USART’s Smart Card mode.
- * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
- * @param NewState: new state of the Smart Card mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note The Smart Card mode is not available for UART4 and UART5.
- * @retval None
- */
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */
- USARTx->CR3 |= CR3_SCEN_Set;
- }
- else
- {
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
- USARTx->CR3 &= CR3_SCEN_Reset;
- }
-}
-
-/**
- * @brief Enables or disables NACK transmission.
- * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
- * @param NewState: new state of the NACK transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @note The Smart Card mode is not available for UART4 and UART5.
- * @retval None
- */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
- USARTx->CR3 |= CR3_NACK_Set;
- }
- else
- {
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
- USARTx->CR3 &= CR3_NACK_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the USART’s Half Duplex communication.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USART Communication.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- USARTx->CR3 |= CR3_HDSEL_Set;
- }
- else
- {
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
- USARTx->CR3 &= CR3_HDSEL_Reset;
- }
-}
-
-
-/**
- * @brief Enables or disables the USART's 8x oversampling mode.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USART one bit sampling method.
- * This parameter can be: ENABLE or DISABLE.
- * @note
- * This function has to be called before calling USART_Init()
- * function in order to have correct baudrate Divider value.
- * @retval None
- */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
- USARTx->CR1 |= CR1_OVER8_Set;
- }
- else
- {
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
- USARTx->CR1 &= CR1_OVER8_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the USART's one bit sampling method.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the USART one bit sampling method.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
- USARTx->CR3 |= CR3_ONEBITE_Set;
- }
- else
- {
- /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */
- USARTx->CR3 &= CR3_ONEBITE_Reset;
- }
-}
-
-/**
- * @brief Configures the USART's IrDA interface.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_IrDAMode: specifies the IrDA mode.
- * This parameter can be one of the following values:
- * @arg USART_IrDAMode_LowPower
- * @arg USART_IrDAMode_Normal
- * @retval None
- */
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-
- USARTx->CR3 &= CR3_IRLP_Mask;
- USARTx->CR3 |= USART_IrDAMode;
-}
-
-/**
- * @brief Enables or disables the USART's IrDA interface.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param NewState: new state of the IrDA mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
- USARTx->CR3 |= CR3_IREN_Set;
- }
- else
- {
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
- USARTx->CR3 &= CR3_IREN_Reset;
- }
-}
-
-/**
- * @brief Checks whether the specified USART flag is set or not.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
- * @arg USART_FLAG_LBD: LIN Break detection flag
- * @arg USART_FLAG_TXE: Transmit data register empty flag
- * @arg USART_FLAG_TC: Transmission Complete flag
- * @arg USART_FLAG_RXNE: Receive data register not empty flag
- * @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
- * @arg USART_FLAG_NE: Noise Error flag
- * @arg USART_FLAG_FE: Framing Error flag
- * @arg USART_FLAG_PE: Parity Error flag
- * @retval The new state of USART_FLAG (SET or RESET).
- */
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_FLAG(USART_FLAG));
- /* The CTS flag is not available for UART4 and UART5 */
- if (USART_FLAG == USART_FLAG_CTS)
- {
- assert_param(IS_USART_123_PERIPH(USARTx));
- }
-
- if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's pending flags.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
- * @arg USART_FLAG_LBD: LIN Break detection flag.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) flags are cleared by software
- * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
- * followed by a read operation to USART_DR register (USART_ReceiveData()).
- * - RXNE flag can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * - TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register (USART_GetFlagStatus()) followed by a write operation
- * to USART_DR register (USART_SendData()).
- * - TXE flag is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- * @retval None
- */
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
- /* The CTS flag is not available for UART4 and UART5 */
- if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
- {
- assert_param(IS_USART_123_PERIPH(USARTx));
- }
-
- USARTx->SR = (uint16_t)~USART_FLAG;
-}
-
-/**
- * @brief Checks whether the specified USART interrupt has occurred or not.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_IT: specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ORE: OverRun Error interrupt
- * @arg USART_IT_NE: Noise Error interrupt
- * @arg USART_IT_FE: Framing Error interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @retval The new state of USART_IT (SET or RESET).
- */
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_GET_IT(USART_IT));
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_123_PERIPH(USARTx));
- }
-
- /* Get the USART register index */
- usartreg = (((uint8_t)USART_IT) >> 0x05);
- /* Get the interrupt position */
- itmask = USART_IT & IT_Mask;
- itmask = (uint32_t)0x01 << itmask;
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- itmask &= USARTx->CR1;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- itmask &= USARTx->CR2;
- }
- else /* The IT is in CR3 register */
- {
- itmask &= USARTx->CR3;
- }
-
- bitpos = USART_IT >> 0x08;
- bitpos = (uint32_t)0x01 << bitpos;
- bitpos &= USARTx->SR;
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's interrupt pending bits.
- * @param USARTx: Select the USART or the UART peripheral.
- * This parameter can be one of the following values:
- * USART1, USART2, USART3, UART4 or UART5.
- * @param USART_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg USART_IT_LBD: LIN Break detection interrupt
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
- *
- * @note
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) pending bits are cleared by
- * software sequence: a read operation to USART_SR register
- * (USART_GetITStatus()) followed by a read operation to USART_DR register
- * (USART_ReceiveData()).
- * - RXNE pending bit can be also cleared by a read to the USART_DR register
- * (USART_ReceiveData()).
- * - TC pending bit can be also cleared by software sequence: a read
- * operation to USART_SR register (USART_GetITStatus()) followed by a write
- * operation to USART_DR register (USART_SendData()).
- * - TXE pending bit is cleared only by a write to the USART_DR register
- * (USART_SendData()).
- * @retval None
- */
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
- uint16_t bitpos = 0x00, itmask = 0x00;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_IT(USART_IT));
- /* The CTS interrupt is not available for UART4 and UART5 */
- if (USART_IT == USART_IT_CTS)
- {
- assert_param(IS_USART_123_PERIPH(USARTx));
- }
-
- bitpos = USART_IT >> 0x08;
- itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
- USARTx->SR = (uint16_t)~itmask;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
deleted file mode 100644
index 77a7ce51..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f10x_wwdg.c
- * @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
- * @brief This file provides all the WWDG firmware functions.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the
- Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT 1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function which reports
- * the name of the source file and the source line number of the call
- * that failed. If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/main.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/main.c
deleted file mode 100644
index 5d39655d..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/main.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/****************************************************************************************
-| Description: demo program application source file
-| File Name: main.c
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-#include /* standard IO library */
-
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-static void DisplayUptime(void);
-static void Init(void);
-
-
-/****************************************************************************************
-** NAME: main
-** PARAMETER: none
-** RETURN VALUE: program return code
-** DESCRIPTION: This is the entry point for the bootloader application and is called
-** by the reset interrupt vector after the C-startup routines executed.
-**
-****************************************************************************************/
-int main(void)
-{
- /* initialize the microcontroller */
- Init();
- /* initialize the bootloader interface */
- BootComInit();
-
- /* start the infinite program loop */
- while (1)
- {
- /* toggle LED with a fixed frequency */
- LedToggle();
- /* Output uptime on terminal */
- DisplayUptime();
- /* check for bootloader activation request */
- BootComCheckActivationRequest();
- }
-
- /* program should never get here */
- return 0;
-} /*** end of main ***/
-
-
-/****************************************************************************************
-** NAME: DisplayUptime
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Outputs the program's runtime on the terminal every second.
-**
-****************************************************************************************/
-static void DisplayUptime(void)
-{
- static unsigned long uptime_ms_last = 0;
- unsigned long uptime_ms_now;
- static unsigned char hr=0, min=0, sec=0;
-
- uptime_ms_now = TimerGet();
-
- /* output info on terminal just once a second */
- if ( (uptime_ms_now - uptime_ms_last) < 1000)
- {
- /* not yet time to toggle */
- return;
- }
- /* calculate uptime */
- if (++sec >= 60)
- {
- sec = 0;
- if (++min >= 60)
- {
- min = 0;
- if (++hr >= 24)
- {
- hr = 0;
- }
- }
- }
-
- /* output time on terminal */
- printf("Program uptime: %02d:%02d:%02d\r", hr, min, sec);
-
- /* store for next comparison */
- uptime_ms_last = uptime_ms_now;
-} /*** end of DisplayUptime ***/
-
-
-/****************************************************************************************
-** NAME: Init
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Initializes the microcontroller.
-**
-****************************************************************************************/
-static void Init(void)
-{
- volatile unsigned long StartUpCounter = 0, HSEStatus = 0;
- unsigned long pll_multiplier;
-
- /* reset the RCC clock configuration to the default reset state (for debug purpose) */
- /* set HSION bit */
- RCC->CR |= (unsigned long)0x00000001;
- /* reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
- RCC->CFGR &= (unsigned long)0xF8FF0000;
- /* reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (unsigned long)0xFEF6FFFF;
- /* reset HSEBYP bit */
- RCC->CR &= (unsigned long)0xFFFBFFFF;
- /* reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
- RCC->CFGR &= (unsigned long)0xFF80FFFF;
- /* disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
- /* enable HSE */
- RCC->CR |= ((unsigned long)RCC_CR_HSEON);
- /* wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != 1500));
- /* check if time out was reached */
- if ((RCC->CR & RCC_CR_HSERDY) == RESET)
- {
- /* cannot continue when HSE is not ready */
- while (1) { ; }
- }
- /* enable flash prefetch buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
- /* reset flash wait state configuration to default 0 wait states */
- FLASH->ACR &= (unsigned long)((unsigned long)~FLASH_ACR_LATENCY);
-#if (BOOT_CPU_SYSTEM_SPEED_KHZ > 48000)
- /* configure 2 flash wait states */
- FLASH->ACR |= (unsigned long)FLASH_ACR_LATENCY_2;
-#elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000)
- /* configure 1 flash wait states */
- FLASH->ACR |= (unsigned long)FLASH_ACR_LATENCY_1;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFGR |= (unsigned long)RCC_CFGR_HPRE_DIV1;
- /* PCLK2 = HCLK/2 */
- RCC->CFGR |= (unsigned long)RCC_CFGR_PPRE2_DIV2;
- /* PCLK1 = HCLK/2 */
- RCC->CFGR |= (unsigned long)RCC_CFGR_PPRE1_DIV2;
- /* reset PLL configuration */
- RCC->CFGR &= (unsigned long)((unsigned long)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | \
- RCC_CFGR_PLLMULL));
- /* calculate multiplier value */
- pll_multiplier = BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ;
- /* convert to register value */
- pll_multiplier = (unsigned long)((pll_multiplier - 2) << 18);
- /* set the PLL multiplier and clock source */
- RCC->CFGR |= (unsigned long)(RCC_CFGR_PLLSRC_HSE | pll_multiplier);
- /* enable PLL */
- RCC->CR |= RCC_CR_PLLON;
- /* wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
- /* select PLL as system clock source */
- RCC->CFGR &= (unsigned long)((unsigned long)~(RCC_CFGR_SW));
- RCC->CFGR |= (unsigned long)RCC_CFGR_SW_PLL;
- /* wait till PLL is used as system clock source */
- while ((RCC->CFGR & (unsigned long)RCC_CFGR_SWS) != (unsigned long)0x08)
- {
- }
-#if (BOOT_COM_UART_ENABLE == 0)
- /* initialize the UART interface if this is not the interface used to
- * reactivate OpenBLT, because stdio_mini needs it for printf/scanf.
- */
- UartInit(BOOT_COM_UART_BAUDRATE);
-#endif
- /* init the led driver */
- LedInit();
- /* init the timer driver */
- TimerInit();
- /* enable IRQ's, because they were initially disabled by the bootloader */
- IrqInterruptEnable();
-} /*** end of Init ***/
-
-
-/*********************************** end of main.c *************************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/memory.x b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/memory.x
deleted file mode 100644
index 32ba23df..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/memory.x
+++ /dev/null
@@ -1,38 +0,0 @@
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x08002000, LENGTH = 120K
- SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
-}
-
-SECTIONS
-{
- __STACKSIZE__ = 1024;
-
- .text :
- {
- KEEP(*(.isr_vector))
- *(.text*)
- *(.rodata*)
- _etext = .;
- } > FLASH
-
-
- .data : AT (ADDR(.text) + SIZEOF(.text))
- {
- _data = .;
- *(vtable)
- *(.data*)
- _edata = .;
- } > SRAM
-
- .bss :
- {
- _bss = .;
- *(.bss*)
- *(COMMON)
- _ebss = .;
- _stack = .;
- . = ALIGN(MAX(_stack + __STACKSIZE__ , .), 4);
- _estack = .;
- } > SRAM
-}
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/timer.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/timer.c
deleted file mode 100644
index 282215a8..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/timer.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/****************************************************************************************
-| Description: Timer driver source file
-| File Name: timer.c
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* Local data declarations
-****************************************************************************************/
-static unsigned long millisecond_counter;
-
-
-/****************************************************************************************
-** NAME: TimerInit
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Initializes the timer.
-**
-****************************************************************************************/
-void TimerInit(void)
-{
- /* configure the SysTick timer for 1 ms period */
- SysTick_Config(BOOT_CPU_SYSTEM_SPEED_KHZ);
- /* reset the millisecond counter */
- TimerSet(0);
-} /*** end of TimerInit ***/
-
-
-/****************************************************************************************
-** NAME: TimerDeinit
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Stops the timer.
-**
-****************************************************************************************/
-void TimerDeinit(void)
-{
- SysTick->CTRL = 0;
-} /*** end of TimerDeinit ***/
-
-
-/****************************************************************************************
-** NAME: TimerSet
-** PARAMETER: timer_value initialize value of the millisecond timer.
-** RETURN VALUE: none
-** DESCRIPTION: Sets the initial counter value of the millisecond timer.
-**
-****************************************************************************************/
-void TimerSet(unsigned long timer_value)
-{
- /* set the millisecond counter */
- millisecond_counter = timer_value;
-} /*** end of TimerSet ***/
-
-
-/****************************************************************************************
-** NAME: TimerGet
-** PARAMETER: none
-** RETURN VALUE: current value of the millisecond timer
-** DESCRIPTION: Obtains the counter value of the millisecond timer.
-**
-****************************************************************************************/
-unsigned long TimerGet(void)
-{
- /* read and return the millisecond counter value */
- return millisecond_counter;
-} /*** end of TimerGet ***/
-
-
-/****************************************************************************************
-** NAME: TimerISRHandler
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Interrupt service routine of the timer.
-**
-****************************************************************************************/
-void TimerISRHandler(void)
-{
- /* increment the millisecond counter */
- millisecond_counter++;
-} /*** end of TimerISRHandler ***/
-
-
-/*********************************** end of timer.c ************************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/timer.h b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/timer.h
deleted file mode 100644
index b3da70d4..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/timer.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/****************************************************************************************
-| Description: Timer driver header file
-| File Name: timer.h
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-#ifndef TIMER_H
-#define TIMER_H
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-void TimerInit(void);
-void TimerDeinit(void);
-void TimerSet(unsigned long timer_value);
-unsigned long TimerGet(void);
-void TimerISRHandler(void);
-
-#endif /* TIMER_H */
-/*********************************** end of timer.h ************************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/uart.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/uart.c
deleted file mode 100644
index 69d5f1f3..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/uart.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/****************************************************************************************
-| Description: UART driver source file
-| File Name: uart.c
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-** NAME: UartInit
-** PARAMETER: baudrate communication speed in bits/sec
-** RETURN VALUE: none
-** DESCRIPTION: Initializes the UART interface for the selected communication speed.
-**
-****************************************************************************************/
-void UartInit(unsigned long baudrate)
-{
- GPIO_InitTypeDef GPIO_InitStruct;
- USART_InitTypeDef USART_InitStruct;
-
- /* enable UART peripheral clock */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
- /* enable GPIO peripheral clock for transmitter and receiver pins */
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE);
- /* configure USART Tx as alternate function push-pull */
- GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2;
- GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStruct);
- /* Configure USART Rx as alternate function input floating */
- GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
- GPIO_InitStruct.GPIO_Pin = GPIO_Pin_3;
- GPIO_Init(GPIOA, &GPIO_InitStruct);
- /* configure UART communcation parameters */
- USART_InitStruct.USART_BaudRate = baudrate;
- USART_InitStruct.USART_WordLength = USART_WordLength_8b;
- USART_InitStruct.USART_StopBits = USART_StopBits_1;
- USART_InitStruct.USART_Parity = USART_Parity_No;
- USART_InitStruct.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
- USART_InitStruct.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- USART_Init(USART2, &USART_InitStruct);
- /* enable UART */
- USART_Cmd(USART2, ENABLE);
-} /*** end of UartInit ***/
-
-
-/****************************************************************************************
-** NAME: UartTxChar
-** PARAMETER: ch character to transmit
-** RETURN VALUE: the transmitted character.
-** DESCRIPTION: Transmits a character through the UART interface.
-**
-****************************************************************************************/
-int UartTxChar(int ch)
-{
- /* wait for transmit completion of the previous character, if any */
- while (USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET) { ; }
- /* transmit the character */
- USART_SendData(USART2, (unsigned char)ch);
- /* for stdio compatibility */
- return ch;
-} /*** end of UartTxChar ***/
-
-
-/****************************************************************************************
-** NAME: UartRxChar
-** PARAMETER: blocking 1 to block until a character was received, 0 otherwise.
-** RETURN VALUE: the value of the received character or -1.
-** DESCRIPTION: Receives a character from the UART interface.
-**
-****************************************************************************************/
-int UartRxChar(unsigned char blocking)
-{
- if (!blocking)
- {
- /* check flag to see if a byte was received */
- if (USART_GetFlagStatus(USART2, USART_FLAG_RXNE) == RESET)
- {
- return -1;
- }
- }
- else
- {
- /* wait for reception of byte */
- while (USART_GetFlagStatus(USART2, USART_FLAG_RXNE) == RESET) { ; }
- }
- /* retrieve and return the newly received byte */
- return USART_ReceiveData(USART2);
-} /*** end of UartRxChar ***/
-
-
-/*********************************** end of uart.c *************************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/uart.h b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/uart.h
deleted file mode 100644
index d92e6906..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/uart.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/****************************************************************************************
-| Description: UART driver header file
-| File Name: uart.h
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-#ifndef UART_H
-#define UART_H
-
-/****************************************************************************************
-* Function prototypes
-****************************************************************************************/
-void UartInit(unsigned long baudrate);
-int UartTxChar(int ch);
-int UartRxChar(unsigned char blocking);
-
-
-#endif /* UART_H */
-/*********************************** end of uart.h *************************************/
diff --git a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/vectors.c b/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/vectors.c
deleted file mode 100644
index 9f671c56..00000000
--- a/Target/Demo/ARMCM3_STM32_Olimex_STM32P103_GCC_Eclipse/Prog/vectors.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/****************************************************************************************
-| Description: bootloader interrupt vector table source file
-| File Name: vectors.c
-|
-|----------------------------------------------------------------------------------------
-| C O P Y R I G H T
-|----------------------------------------------------------------------------------------
-| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
-|
-|----------------------------------------------------------------------------------------
-| L I C E N S E
-|----------------------------------------------------------------------------------------
-| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
-| modify it under the terms of the GNU General Public License as published by the Free
-| Software Foundation, either version 3 of the License, or (at your option) any later
-| version.
-|
-| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-| PURPOSE. See the GNU General Public License for more details.
-|
-| You should have received a copy of the GNU General Public License along with OpenBLT.
-| If not, see .
-|
-| A special exception to the GPL is included to allow you to distribute a combined work
-| that includes OpenBLT without being obliged to provide the source code for any
-| proprietary components. The exception text is included at the bottom of the license
-| file .
-|
-****************************************************************************************/
-
-/****************************************************************************************
-* Include files
-****************************************************************************************/
-#include "header.h" /* generic header */
-
-
-/****************************************************************************************
-* External functions
-****************************************************************************************/
-extern void reset_handler(void); /* implemented in cstart.c */
-
-
-/****************************************************************************************
-* External data declarations
-****************************************************************************************/
-extern unsigned long _estack; /* stack end address (memory.x) */
-
-
-/****************************************************************************************
-** NAME: UnusedISR
-** PARAMETER: none
-** RETURN VALUE: none
-** DESCRIPTION: Catch-all for unused interrrupt service routines.
-**
-****************************************************************************************/
-void UnusedISR(void)
-{
- /* unexpected interrupt occured, so halt the system */
- while (1) { ; }
-} /*** end of UnusedISR ***/
-
-
-/****************************************************************************************
-* I N T E R R U P T V E C T O R T A B L E
-****************************************************************************************/
-typedef union
-{
- void (*func)(void); /* for ISR function pointers */
- unsigned long ptr; /* for stack pointer entry */
-}tIsrFunc; /* type for vector table entries */
-
-__attribute__ ((section(".isr_vector")))
-const tIsrFunc _vectab[] =
-{
- { .ptr = (unsigned long)&_estack }, /* the initial stack pointer */
- { reset_handler }, /* the reset handler */
- { UnusedISR }, /* NMI Handler */
- { UnusedISR }, /* Hard Fault Handler */
- { UnusedISR }, /* MPU Fault Handler */
- { UnusedISR }, /* Bus Fault Handler */
- { UnusedISR }, /* Usage Fault Handler */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* SVCall Handler */
- { UnusedISR }, /* Debug Monitor Handler */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* PendSV Handler */
- { TimerISRHandler }, /* SysTick Handler */
- { UnusedISR }, /* Window Watchdog */
- { UnusedISR }, /* PVD through EXTI Line detect */
- { UnusedISR }, /* Tamper */
- { UnusedISR }, /* RTC */
- { UnusedISR }, /* Flash */
- { UnusedISR }, /* RCC */
- { UnusedISR }, /* EXTI Line 0 */
- { UnusedISR }, /* EXTI Line 1 */
- { UnusedISR }, /* EXTI Line 2 */
- { UnusedISR }, /* EXTI Line 3 */
- { UnusedISR }, /* EXTI Line 4 */
- { UnusedISR }, /* DMA1 Channel 1 */
- { UnusedISR }, /* DMA1 Channel 2 */
- { UnusedISR }, /* DMA1 Channel 3 */
- { UnusedISR }, /* DMA1 Channel 4 */
- { UnusedISR }, /* DMA1 Channel 5 */
- { UnusedISR }, /* DMA1 Channel 6 */
- { UnusedISR }, /* DMA1 Channel 7 */
- { UnusedISR }, /* ADC1 and ADC2 */
- { UnusedISR }, /* CAN1 TX */
- { UnusedISR }, /* CAN1 RX0 */
- { UnusedISR }, /* CAN1 RX1 */
- { UnusedISR }, /* CAN1 SCE */
- { UnusedISR }, /* EXTI Line 9..5 */
- { UnusedISR }, /* TIM1 Break */
- { UnusedISR }, /* TIM1 Update */
- { UnusedISR }, /* TIM1 Trigger and Commutation */
- { UnusedISR }, /* TIM1 Capture Compare */
- { UnusedISR }, /* TIM2 */
- { UnusedISR }, /* TIM3 */
- { UnusedISR }, /* TIM4 */
- { UnusedISR }, /* I2C1 Event */
- { UnusedISR }, /* I2C1 Error */
- { UnusedISR }, /* I2C2 Event */
- { UnusedISR }, /* I2C1 Error */
- { UnusedISR }, /* SPI1 */
- { UnusedISR }, /* SPI2 */
- { UnusedISR }, /* USART1 */
- { UnusedISR }, /* USART2 */
- { UnusedISR }, /* USART3 */
- { UnusedISR }, /* EXTI Line 15..10 */
- { UnusedISR }, /* RTC alarm through EXTI line */
- { UnusedISR }, /* USB OTG FS Wakeup */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* Reserved */
- { UnusedISR }, /* TIM5 */
- { UnusedISR }, /* SPI3 */
- { UnusedISR }, /* UART4 */
- { UnusedISR }, /* UART5 */
- { UnusedISR }, /* TIM6 */
- { UnusedISR }, /* TIM7 */
- { UnusedISR }, /* DMA2 Channel1 */
- { UnusedISR }, /* DMA2 Channel2 */
- { UnusedISR }, /* DMA2 Channel3 */
- { UnusedISR }, /* DMA2 Channel4 */
- { UnusedISR }, /* DMA2 Channel5 */
- { UnusedISR }, /* Ethernet */
- { UnusedISR }, /* Ethernet Wakeup */
- { UnusedISR }, /* CAN2 TX */
- { UnusedISR }, /* CAN2 RX0 */
- { UnusedISR }, /* CAN2 RX1 */
- { UnusedISR }, /* CAN2 SCE */
- { UnusedISR }, /* USB OTG FS */
- { (void*)0x55AA11EE }, /* Reserved for OpenBLT checksum */
-};
-
-
-/************************************ end of hw.c **************************************/
-
-
