From 673474c79d843a22e9a21219daf5339b01f07177 Mon Sep 17 00:00:00 2001 From: Frank Voorburg Date: Wed, 12 Aug 2015 15:46:49 +0000 Subject: [PATCH] - removed Nuclue STM32 demo due to incomplete patch. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@118 5dc33758-31d5-4daf-9ae8-b24bf3d40d73 --- .../Boot/.project | 39 - .../openblt_demoprog_nucleo_stm32f103rb.srec | 247 - .../Boot/blt_conf.h | 216 - .../Boot/boot.dox | 7 - .../Boot/cmd/build.bat | 3 - .../Boot/cmd/clean.bat | 3 - .../Boot/cmd/debug.bat | 2 - .../Boot/cmd/debug.cfg | 11 - .../Boot/cmd/env.bat | 5 - .../Boot/cmd/flash.bat | 2 - .../Boot/cmd/flash.cfg | 13 - .../Boot/hooks.c | 453 - .../Boot/ide/DemoBoot.project | 193 - .../Boot/ide/DemoBoot.workspace | 12 - .../Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.c | 784 - .../Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.h | 1818 -- .../ST/STM32F10x/Release_Notes.html | 284 - .../DeviceSupport/ST/STM32F10x/stm32f10x.h | 8336 --------- .../Release_Notes.html | 342 - .../inc/stm32f10x_gpio.h | 385 - .../inc/stm32f10x_rcc.h | 727 - .../inc/stm32f10x_spi.h | 487 - .../inc/stm32f10x_usart.h | 412 - .../src/stm32f10x_gpio.c | 650 - .../src/stm32f10x_rcc.c | 1470 -- .../src/stm32f10x_spi.c | 908 - .../src/stm32f10x_usart.c | 1058 -- .../stm32f10x_conf.h | 77 - .../Boot/lib/fatfs/ffconf.h | 192 - .../Boot/main.c | 221 - .../Boot/makefile | 196 - .../Boot/obj/assert.lst | 150 - .../Boot/obj/backdoor.lst | 310 - .../Boot/obj/boot.lst | 192 - .../Boot/obj/can.lst | 22 - .../Boot/obj/com.lst | 595 - .../Boot/obj/cop.lst | 127 - .../Boot/obj/core_cm3.lst | 1351 -- .../Boot/obj/cstart.lst | 196 - .../Boot/obj/ff.lst | 13916 ---------------- .../Boot/obj/file.lst | 22 - .../Boot/obj/flash.lst | 2133 --- .../Boot/obj/hooks.lst | 22 - .../Boot/obj/main.lst | 431 - .../Boot/obj/mmc.lst | 2694 --- .../Boot/obj/nvm.lst | 375 - .../Boot/obj/stm32f10x_gpio.lst | 1517 -- .../Boot/obj/stm32f10x_rcc.lst | 2796 ---- .../Boot/obj/stm32f10x_spi.lst | 1862 --- .../Boot/obj/stm32f10x_usart.lst | 2276 --- .../Prog/bin/demoprog_nucleo_stm32f103rb.map | 110 - .../Prog/bin/demoprog_nucleo_stm32f103rb.srec | 125 - .../Prog/boot.c | 397 - .../Prog/boot.h | 45 - .../Prog/cmd/clean.bat | 3 - .../Prog/cmd/env.bat | 5 - .../Prog/cstart.c | 94 - .../Prog/header.h | 49 - .../Prog/ide/DemoProg.project | 170 - .../Prog/ide/DemoProg.workspace | 12 - .../Prog/ide/readme.txt | 4 - .../Prog/irq.c | 94 - .../Prog/led.h | 44 - .../CMSIS/CM3/CoreSupport/core_cm3.c | 784 - .../CMSIS/CM3/CoreSupport/core_cm3.h | 1818 -- .../DeviceSupport/ST/STM32F10x/stm32f10x.h | 8336 --------- .../Release_Notes.html | 342 - .../STM32F10x_StdPeriph_Driver/inc/misc.h | 220 - .../inc/stm32f10x_adc.h | 483 - .../inc/stm32f10x_bkp.h | 195 - .../inc/stm32f10x_can.h | 697 - .../inc/stm32f10x_cec.h | 210 - .../inc/stm32f10x_crc.h | 94 - .../inc/stm32f10x_dac.h | 317 - .../inc/stm32f10x_dbgmcu.h | 119 - .../inc/stm32f10x_exti.h | 184 - .../inc/stm32f10x_flash.h | 426 - .../inc/stm32f10x_fsmc.h | 733 - .../inc/stm32f10x_gpio.h | 385 - .../inc/stm32f10x_i2c.h | 684 - .../inc/stm32f10x_pwr.h | 156 - .../inc/stm32f10x_rcc.h | 727 - .../inc/stm32f10x_rtc.h | 135 - .../inc/stm32f10x_sdio.h | 531 - .../inc/stm32f10x_spi.h | 487 - .../inc/stm32f10x_usart.h | 412 - .../STM32F10x_StdPeriph_Driver/src/misc.c | 225 - .../src/stm32f10x_adc.c | 1307 -- .../src/stm32f10x_bkp.c | 308 - .../src/stm32f10x_can.c | 1415 -- .../src/stm32f10x_cec.c | 433 - .../src/stm32f10x_dac.c | 571 - .../src/stm32f10x_dbgmcu.c | 162 - .../src/stm32f10x_dma.c | 714 - .../src/stm32f10x_exti.c | 269 - .../src/stm32f10x_flash.c | 1684 -- .../src/stm32f10x_fsmc.c | 866 - .../src/stm32f10x_i2c.c | 1331 -- .../src/stm32f10x_iwdg.c | 190 - .../src/stm32f10x_pwr.c | 307 - .../src/stm32f10x_rcc.c | 1470 -- .../src/stm32f10x_rtc.c | 339 - .../src/stm32f10x_sdio.c | 799 - .../src/stm32f10x_tim.c | 2890 ---- .../demo.dox | 8 - 105 files changed, 85455 deletions(-) delete mode 100644 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a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/.project b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/.project deleted file mode 100644 index 1cc0c99d..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/.project +++ /dev/null @@ -1,39 +0,0 @@ - - - openblt_boot_ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - openblt_source - 2 - OPENBLT/Source - - - - - OPENBLT - file:/C:/workdir/io6/openblt-code-org/Target - - - diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/bin/openblt_demoprog_nucleo_stm32f103rb.srec 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\file Demo\ARMCM3_STM32_Olimex_STM32P103_GCC\Boot\blt_conf.h -* \brief Bootloader configuration header file. -* \ingroup Boot_ARMCM3_STM32_Olimex_STM32P103_GCC -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or -* modify it under the terms of the GNU General Public License as published by the Free -* Software Foundation, either version 3 of the License, or (at your option) any later -* version. -* -* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; -* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -* PURPOSE. See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along with OpenBLT. -* If not, see . -* -* A special exception to the GPL is included to allow you to distribute a combined work -* that includes OpenBLT without being obliged to provide the source code for any -* proprietary components. The exception text is included at the bottom of the license -* file . -* -* \endinternal -****************************************************************************************/ -#ifndef BLT_CONF_H -#define BLT_CONF_H - -/**************************************************************************************** -* C P U D R I V E R C O N F I G U R A T I O N -****************************************************************************************/ -/* To properly initialize the baudrate clocks of the communication interface, typically - * the speed of the crystal oscillator and/or the speed at which the system runs is - * needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and - * BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is - * not dependent on the targets architecture, the byte ordering needs to be known. - * Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects little endian mode and 0 selects - * big endian mode. - * - * Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be - * called the moment the user program is about to be started. This could be used to - * de-initialize application specific parts, for example to stop blinking an LED, etc. - */ -/** \brief Frequency of the external crystal oscillator. */ -#define BOOT_CPU_XTAL_SPEED_KHZ (8000) -/** \brief Desired system speed. */ -#define BOOT_CPU_SYSTEM_SPEED_KHZ (72000) -/** \brief Motorola or Intel style byte ordering. */ -#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0) -/** \brief Enable/disable hook function call right before user program start. */ -#define BOOT_CPU_USER_PROGRAM_START_HOOK (0) - - -/**************************************************************************************** -* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N -****************************************************************************************/ -/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE - * configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed - * in bits/second. Two CAN messages are reserved for communication with the host. The - * message identifier for sending data from the target to the host is configured with - * BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with - * BOOT_COM_CAN_RXMSG_ID. The maximum amount of data bytes in a message for data - * transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and - * BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more - * than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the - * CAN controller channel. - * - */ -/** \brief Enable/disable CAN transport layer. */ -#define BOOT_COM_CAN_ENABLE (0) -/** \brief Configure the desired CAN baudrate. */ -#define BOOT_COM_CAN_BAUDRATE (500000) -/** \brief Configure CAN message ID target->host. */ -#define BOOT_COM_CAN_TX_MSG_ID (0x7E1) -/** \brief Configure number of bytes in the target->host CAN message. */ -#define BOOT_COM_CAN_TX_MAX_DATA (8) -/** \brief Configure CAN message ID host->target. */ -#define BOOT_COM_CAN_RX_MSG_ID (0x667) -/** \brief Configure number of bytes in the host->target CAN message. */ -#define BOOT_COM_CAN_RX_MAX_DATA (8) -/** \brief Select the desired CAN peripheral as a zero based index. */ -#define BOOT_COM_CAN_CHANNEL_INDEX (0) - -/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE - * configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed - * in bits/second. The maximum amount of data bytes in a message for data transmission - * and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA, - * respectively. It is common for a microcontroller to have more than 1 UART interface - * on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface. - * - */ -/** \brief Enable/disable UART transport layer. */ -#define BOOT_COM_UART_ENABLE (1) -/** \brief Configure the desired communication speed. */ -#define BOOT_COM_UART_BAUDRATE (57600) -/** \brief Configure number of bytes in the target->host data packet. */ -#define BOOT_COM_UART_TX_MAX_DATA (64) -/** \brief Configure number of bytes in the host->target data packet. */ -#define BOOT_COM_UART_RX_MAX_DATA (64) -/** \brief Select the desired UART peripheral as a zero based index. */ -#define BOOT_COM_UART_CHANNEL_INDEX (1) - - -/**************************************************************************************** -* F I L E S Y S T E M I N T E R F A C E C O N F I G U R A T I O N -****************************************************************************************/ -/* The file system interface is selected by setting the BOOT_FILE_SYS_ENABLE configurable - * to 1. This enables support for firmware updates from a file stored on a locally - * attached file system such as an SD-card. Note that this interface can be enabled - * together with one of the remote communication interfaces such as UART, CAN or USB. - * - * Set BOOT_FILE_LOGGING_ENABLE to 1 if you would like log messages to be created during - * a firmware update. The hook function FileFirmwareUpdateLogHook() will be called each - * time a new string formatted log entry is available. This could be used during testing - * by outputting the string on UART or to create a log file on the file system itself. - * - * Set BOOT_FILE_ERROR_HOOK_ENABLE to 1 if you would like to be informed in case an error - * occurs during the firmware update. This could for example be used to turn on an error - * LED to inform the user that something went wrong. Inspecting the log messages provides - * additional information on the error cause. - * - * Set BOOT_FILE_STARTED_HOOK_ENABLE to 1 if you would like to be informed when a new - * firmware update is started by the bootloader. - * - * Set BOOT_FILE_COMPLETED_HOOK_ENABLE to 1 if you would like to be informed when a - * firmware update is completed by the bootloader. - */ -/** \brief Enable/disable support for firmware updates from a locally attached storage.*/ -#define BOOT_FILE_SYS_ENABLE (0) -/** \brief Enable/disable logging messages during firmware updates. */ -#define BOOT_FILE_LOGGING_ENABLE (0) -/** \brief Enable/disable a hook function that is called upon detection of an error. */ -#define BOOT_FILE_ERROR_HOOK_ENABLE (0) -/** \brief Enable/disable a hook function that is called at the start of the update. */ -#define BOOT_FILE_STARTED_HOOK_ENABLE (0) -/** \brief Enable/disable a hook function that is called at the end of the update. */ -#define BOOT_FILE_COMPLETED_HOOK_ENABLE (0) - - -/**************************************************************************************** -* B A C K D O O R E N T R Y C O N F I G U R A T I O N -****************************************************************************************/ -/* It is possible to implement an application specific method to force the bootloader to - * stay active after a reset. Such a backdoor entry into the bootloader is desired in - * situations where the user program does not run properly and therefore cannot - * reactivate the bootloader. By enabling these hook functions, the application can - * implement the backdoor, which overrides the default backdoor entry that is programmed - * into the bootloader. When desired for security purposes, these hook functions can - * also be implemented in a way that disables the backdoor entry altogether. - */ -/** \brief Enable/disable the backdoor override hook functions. */ -#define BOOT_BACKDOOR_HOOKS_ENABLE (0) - - -/**************************************************************************************** -* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N -****************************************************************************************/ -/* The NVM driver typically supports erase and program operations of the internal memory - * present on the microcontroller. Through these hook functions the NVM driver can be - * extended to support additional memory types such as external flash memory and serial - * eeproms. The size of the internal memory in kilobytes is specified with configurable - * BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can - * be overridden with a application specific method by enabling configuration switch - * BOOT_NVM_CHECKSUM_HOOKS_ENABLE. - */ -/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */ -#define BOOT_NVM_HOOKS_ENABLE (0) -/** \brief Configure the size of the default memory device (typically flash EEPROM). */ -#define BOOT_NVM_SIZE_KB (128) -/** \brief Enable/disable hooks functions to override the user program checksum handling. */ -#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0) - - -/**************************************************************************************** -* W A T C H D O G D R I V E R C O N F I G U R A T I O N -****************************************************************************************/ -/* The COP driver cannot be configured internally in the bootloader, because its use - * and configuration is application specific. The bootloader does need to service the - * watchdog in case it is used. When the application requires the use of a watchdog, - * set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through - * hook functions. - */ -/** \brief Enable/disable the hook functions for controlling the watchdog. */ -#define BOOT_COP_HOOKS_ENABLE (0) - - -/**************************************************************************************** -* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N -****************************************************************************************/ -/* A security mechanism can be enabled in the bootloader's XCP module by setting configu- - * rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming - * operations can be performed, access to this resource need to be unlocked. - * In the Microboot settings on tab "XCP Protection" you need to specify a DLL that - * implements the unlocking algorithm. The demo programs are configured for the (simple) - * algorithm in "FeaserKey.dll". The source code for this DLL is available so it can be - * customized to your needs. - * During the unlock sequence, Microboot requests a seed from the bootloader, which is in - * the format of a byte array. Using this seed the unlock algorithm in the DLL computes - * a key, which is also a byte array, and sends this back to the bootloader. The - * bootloader then verifies this key to determine if programming and erase operations are - * permitted. - * After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook() - * are called by the bootloader to obtain the seed and to verify the key, respectively. - */ -#define BOOT_XCP_SEED_KEY_ENABLE (0) - - -#endif /* BLT_CONF_H */ -/*********************************** end of blt_conf.h *********************************/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/boot.dox b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/boot.dox deleted file mode 100644 index f3d7df8b..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/boot.dox +++ /dev/null @@ -1,7 +0,0 @@ -/** -\defgroup Boot_ARMCM3_STM32_Olimex_STM32P103_GCC Bootloader -\brief Bootloader. -\ingroup ARMCM3_STM32_Olimex_STM32P103_GCC -*/ - - diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/build.bat b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/build.bat deleted file mode 100644 index 716230da..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/build.bat +++ /dev/null @@ -1,3 +0,0 @@ -@echo off -call env.bat -make --directory=../ all diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/clean.bat b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/clean.bat deleted file mode 100644 index da685acd..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/clean.bat +++ /dev/null @@ -1,3 +0,0 @@ -@echo off -call env.bat -make --directory=../ clean diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/debug.bat b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/debug.bat deleted file mode 100644 index b74ee771..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/debug.bat +++ /dev/null @@ -1,2 +0,0 @@ -call env.bat -openocd.exe -f interface/stlink-v2-1.cfg -f target/stm32f1x_stlink.cfg -f debug.cfg \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/debug.cfg b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/debug.cfg deleted file mode 100644 index fa5752f8..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/debug.cfg +++ /dev/null @@ -1,11 +0,0 @@ -### -# Description: starts the OpenOCD GDB server (localhost:3333) -# once started use arm-elf-insight .elf to start the debug session -### - -init -reset init -halt - - - diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/env.bat b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/env.bat deleted file mode 100644 index 8d9a84ef..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/env.bat +++ /dev/null @@ -1,5 +0,0 @@ -@echo off -set PATH=c:\Program Files\GNU ARM Eclipse\OpenOCD\0.9.0-201505190955\bin;%PATH% -set PATH=c:\Program Files (x86)\GNU ARM Eclipse\Build Tools\2.4-201503242026\bin;%PATH% -set PATH=c:\Program Files (x86)\GNU Tools ARM Embedded\4.9 2015q1\bin;%PATH% -set PATH=c:\Program Files (x86)\GNU Tools ARM Embedded\4.9 2015q1\arm-none-eabi\bin;%PATH% \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/flash.bat b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/flash.bat deleted file mode 100644 index 4f1858d6..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/flash.bat +++ /dev/null @@ -1,2 +0,0 @@ -call env.bat -openocd.exe -f interface/stlink-v2-1.cfg -f target/stm32f1x_stlink.cfg -f flash.cfg \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/flash.cfg b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/flash.cfg deleted file mode 100644 index 1217715f..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/cmd/flash.cfg +++ /dev/null @@ -1,13 +0,0 @@ -### -# Description: mass erases and flashes the binary with OpenOCD -### - -init -reset init -halt -stm32f1x mass_erase 0 -flash write_image ..\\bin\\openblt_demoprog_nucleo_stm32f103rb.elf -#flash write_image erase ..\\bin\\openblt_demoprog_nucleo_stm32f103rb.elf -shutdown - - diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/hooks.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/hooks.c deleted file mode 100644 index 10f131ef..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/hooks.c +++ /dev/null @@ -1,453 +0,0 @@ -/************************************************************************************//** -* \file Demo\ARMCM3_STM32_Olimex_STM32P103_GCC\Boot\hooks.c -* \brief Bootloader callback source file. -* \ingroup Boot_ARMCM3_STM32_Olimex_STM32P103_GCC -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or -* modify it under the terms of the GNU General Public License as published by the Free -* Software Foundation, either version 3 of the License, or (at your option) any later -* version. -* -* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; -* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -* PURPOSE. See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along with OpenBLT. -* If not, see . -* -* A special exception to the GPL is included to allow you to distribute a combined work -* that includes OpenBLT without being obliged to provide the source code for any -* proprietary components. The exception text is included at the bottom of the license -* file . -* -* \endinternal -****************************************************************************************/ - -/**************************************************************************************** -* Include files -****************************************************************************************/ -#include "boot.h" /* bootloader generic header */ -#if (BOOT_FILE_LOGGING_ENABLE > 0) -#include "stm32f10x.h" /* STM32 registers */ -#include "stm32f10x_conf.h" /* STM32 peripheral drivers */ -#endif - - -/**************************************************************************************** -* B A C K D O O R E N T R Y H O O K F U N C T I O N S -****************************************************************************************/ - -#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0) -/************************************************************************************//** -** \brief Initializes the backdoor entry option. -** \return none. -** -****************************************************************************************/ -void BackDoorInitHook(void) -{ -} /*** end of BackDoorInitHook ***/ - - -/************************************************************************************//** -** \brief Checks if a backdoor entry is requested. -** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise. -** -****************************************************************************************/ -blt_bool BackDoorEntryHook(void) -{ - /* default implementation always activates the bootloader after a reset */ - return BLT_TRUE; -} /*** end of BackDoorEntryHook ***/ -#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */ - - -/**************************************************************************************** -* C P U D R I V E R H O O K F U N C T I O N S -****************************************************************************************/ - -#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0) -/************************************************************************************//** -** \brief Callback that gets called when the bootloader is about to exit and -** hand over control to the user program. This is the last moment that -** some final checking can be performed and if necessary prevent the -** bootloader from activiting the user program. -** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep -** keep the bootloader active. -** -****************************************************************************************/ -blt_bool CpuUserProgramStartHook(void) -{ - /* okay to start the user program */ - return BLT_TRUE; -} /*** end of CpuUserProgramStartHook ***/ -#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */ - - -/**************************************************************************************** -* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S -****************************************************************************************/ - -#if (BOOT_NVM_HOOKS_ENABLE > 0) -/************************************************************************************//** -** \brief Callback that gets called at the start of the internal NVM driver -** initialization routine. -** \return none. -** -****************************************************************************************/ -void NvmInitHook(void) -{ -} /*** end of NvmInitHook ***/ - - -/************************************************************************************//** -** \brief Callback that gets called at the start of the NVM driver write -** routine. It allows additional memory to be operated on. If the address -** is not within the range of the additional memory, then -** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't -** been written yet. -** \param addr Start address. -** \param len Length in bytes. -** \param data Pointer to the data buffer. -** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is -** not within the supported memory range, or BLT_NVM_ERROR is the write -** operation failed. -** -****************************************************************************************/ -blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data) -{ - return BLT_NVM_NOT_IN_RANGE; -} /*** end of NvmWriteHook ***/ - - -/************************************************************************************//** -** \brief Callback that gets called at the start of the NVM driver erase -** routine. It allows additional memory to be operated on. If the address -** is not within the range of the additional memory, then -** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory -** hasn't been erased yet. -** \param addr Start address. -** \param len Length in bytes. -** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is -** not within the supported memory range, or BLT_NVM_ERROR is the erase -** operation failed. -** -****************************************************************************************/ -blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len) -{ - return BLT_NVM_NOT_IN_RANGE; -} /*** end of NvmEraseHook ***/ - - -/************************************************************************************//** -** \brief Callback that gets called at the end of the NVM programming session. -** \return BLT_TRUE is successful, BLT_FALSE otherwise. -** -****************************************************************************************/ -blt_bool NvmDoneHook(void) -{ - return BLT_TRUE; -} /*** end of NvmDoneHook ***/ -#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */ - - -#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) -/************************************************************************************//** -** \brief Verifies the checksum, which indicates that a valid user program is -** present and can be started. -** \return BLT_TRUE if successful, BLT_FALSE otherwise. -** -****************************************************************************************/ -blt_bool NvmVerifyChecksumHook(void) -{ - return BLT_TRUE; -} /*** end of NvmVerifyChecksum ***/ - - -/************************************************************************************//** -** \brief Writes a checksum of the user program to non-volatile memory. This is -** performed once the entire user program has been programmed. Through -** the checksum, the bootloader can check if a valid user programming is -** present and can be started. -** \return BLT_TRUE if successful, BLT_FALSE otherwise. -** -****************************************************************************************/ -blt_bool NvmWriteChecksumHook(void) -{ - return BLT_TRUE; -} -#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */ - - -/**************************************************************************************** -* W A T C H D O G D R I V E R H O O K F U N C T I O N S -****************************************************************************************/ - -#if (BOOT_COP_HOOKS_ENABLE > 0) -/************************************************************************************//** -** \brief Callback that gets called at the end of the internal COP driver -** initialization routine. It can be used to configure and enable the -** watchdog. -** \return none. -** -****************************************************************************************/ -void CopInitHook(void) -{ -} /*** end of CopInitHook ***/ - - -/************************************************************************************//** -** \brief Callback that gets called at the end of the internal COP driver -** service routine. This gets called upon initialization and during -** potential long lasting loops and routine. It can be used to service -** the watchdog to prevent a watchdog reset. -** \return none. -** -****************************************************************************************/ -void CopServiceHook(void) -{ -} /*** end of CopServiceHook ***/ -#endif /* BOOT_COP_HOOKS_ENABLE > 0 */ - - -/**************************************************************************************** -* F I L E S Y S T E M I N T E R F A C E H O O K F U N C T I O N S -****************************************************************************************/ - -#if (BOOT_FILE_SYS_ENABLE > 0) - -/**************************************************************************************** -* Constant data declarations -****************************************************************************************/ -/** \brief Firmware filename. */ -static const blt_char firmwareFilename[] = "/demoprog_olimex_stm32p103.srec"; - - -/**************************************************************************************** -* Local data declarations -****************************************************************************************/ -#if (BOOT_FILE_LOGGING_ENABLE > 0) -/** \brief Data structure for grouping log-file related information. */ -static struct -{ - FIL handle; /**< FatFS handle to the log-file. */ - blt_bool canUse; /**< Flag to indicate if the log-file can be used. */ -} logfile; -#endif - - -/************************************************************************************//** -** \brief Callback that gets called to check whether a firmware update from -** local file storage should be started. This could for example be when -** a switch is pressed, when a certain file is found on the local file -** storage, etc. -** \return BLT_TRUE if a firmware update is requested, BLT_FALSE otherwise. -** -****************************************************************************************/ -blt_bool FileIsFirmwareUpdateRequestedHook(void) -{ - FILINFO fileInfoObject = { 0 }; /* needs to be zeroed according to f_stat docs */; - - /* Current example implementation looks for a predetermined firmware file on the - * SD-card. If the SD-card is accessible and the firmware file was found the firmware - * update is started. When successfully completed, the firmware file is deleted. - * During the firmware update, progress information is written to a file called - * bootlog.txt and additionally outputted on UART @57600 bps for debugging purposes. - */ - /* check if firmware file is present and SD-card is accessible */ - if (f_stat(firmwareFilename, &fileInfoObject) == FR_OK) - { - /* check if the filesize is valid and that it is not a directory */ - if ( (fileInfoObject.fsize > 0) && (!(fileInfoObject.fattrib & AM_DIR)) ) - { - /* all conditions are met to start a firmware update from local file storage */ - return BLT_TRUE; - } - } - /* still here so no firmware update request is pending */ - return BLT_FALSE; -} /*** end of FileIsFirmwareUpdateRequestedHook ***/ - - -/************************************************************************************//** -** \brief Callback to obtain the filename of the firmware file that should be -** used during the firmware update from the local file storage. This -** hook function is called at the beginning of the firmware update from -** local storage sequence. -** \return valid firmware filename with full path or BLT_NULL. -** -****************************************************************************************/ -const blt_char *FileGetFirmwareFilenameHook(void) -{ - return firmwareFilename; -} /*** end of FileGetFirmwareFilenameHook ***/ - - -#if (BOOT_FILE_STARTED_HOOK_ENABLE > 0) -/************************************************************************************//** -** \brief Callback that gets called to inform the application that a firmware -** update from local storage just started. -** \return none. -** -****************************************************************************************/ -void FileFirmwareUpdateStartedHook(void) -{ - #if (BOOT_FILE_LOGGING_ENABLE > 0) - /* create/overwrite the logfile */ - logfile.canUse = BLT_FALSE; - if (f_open(&logfile.handle, "/bootlog.txt", FA_CREATE_ALWAYS | FA_WRITE) == FR_OK) - { - logfile.canUse = BLT_TRUE; - } - #endif -} /*** end of FileFirmwareUpdateStartedHook ***/ -#endif /* BOOT_FILE_STARTED_HOOK_ENABLE > 0 */ - - -#if (BOOT_FILE_COMPLETED_HOOK_ENABLE > 0) -/************************************************************************************//** -** \brief Callback that gets called to inform the application that a firmware -** update was successfully completed. -** \return none. -** -****************************************************************************************/ -void FileFirmwareUpdateCompletedHook(void) -{ - #if (BOOT_FILE_LOGGING_ENABLE > 0) - /* close the log file */ - if (logfile.canUse == BLT_TRUE) - { - f_close(&logfile.handle); - } - /* wait for all logging related transmission to complete */ - while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); - #endif - /* now delete the firmware file from the disk since the update was successful */ - f_unlink(firmwareFilename); -} /*** end of FileFirmwareUpdateCompletedHook ***/ -#endif /* BOOT_FILE_COMPLETED_HOOK_ENABLE > 0 */ - - -#if (BOOT_FILE_ERROR_HOOK_ENABLE > 0) -/************************************************************************************//** -** \brief Callback that gets called in case an error occurred during a firmware -** update. Refer to for a list of available error codes. -** \return none. -** -****************************************************************************************/ -void FileFirmwareUpdateErrorHook(blt_int8u error_code) -{ - #if (BOOT_FILE_LOGGING_ENABLE > 0) - /* error detected which stops the firmware update, so close the log file */ - if (logfile.canUse == BLT_TRUE) - { - f_close(&logfile.handle); - } - #endif -} /*** end of FileFirmwareUpdateErrorHook ***/ -#endif /* BOOT_FILE_ERROR_HOOK_ENABLE > 0 */ - - -#if (BOOT_FILE_LOGGING_ENABLE > 0) -/************************************************************************************//** -** \brief Callback that gets called each time new log information becomes -** available during a firmware update. -** \param info_string Pointer to a character array with the log entry info. -** \return none. -** -****************************************************************************************/ -void FileFirmwareUpdateLogHook(blt_char *info_string) -{ - /* write the string to the log file */ - if (logfile.canUse == BLT_TRUE) - { - if (f_puts(info_string, &logfile.handle) < 0) - { - logfile.canUse = BLT_FALSE; - f_close(&logfile.handle); - } - } - /* echo all characters in the string on UART */ - while(*info_string != '\0') - { - /* write character to transmit holding register */ - USART_SendData(USART2, *info_string); - /* wait for tx holding register to be empty */ - while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); - /* point to the next character in the string */ - info_string++; - } -} /*** end of FileFirmwareUpdateLogHook ***/ -#endif /* BOOT_FILE_LOGGING_ENABLE > 0 */ - - -#endif /* BOOT_FILE_SYS_ENABLE > 0 */ - - -/**************************************************************************************** -* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S -****************************************************************************************/ - -#if (BOOT_XCP_SEED_KEY_ENABLE > 0) -/************************************************************************************//** -** \brief Provides a seed to the XCP master that will be used for the key -** generation when the master attempts to unlock the specified resource. -** Called by the GET_SEED command. -** \param resource Resource that the seed if requested for (XCP_RES_XXX). -** \param seed Pointer to byte buffer wher the seed will be stored. -** \return Length of the seed in bytes. -** -****************************************************************************************/ -blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed) -{ - /* request seed for unlocking ProGraMming resource */ - if ((resource & XCP_RES_PGM) != 0) - { - seed[0] = 0x55; - } - - /* return seed length */ - return 1; -} /*** end of XcpGetSeedHook ***/ - - -/************************************************************************************//** -** \brief Called by the UNLOCK command and checks if the key to unlock the -** specified resource was correct. If so, then the resource protection -** will be removed. -** \param resource resource to unlock (XCP_RES_XXX). -** \param key pointer to the byte buffer holding the key. -** \param len length of the key in bytes. -** \return 1 if the key was correct, 0 otherwise. -** -****************************************************************************************/ -blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len) -{ - /* suppress compiler warning for unused parameter */ - len = len; - - /* the example key algorithm in "FeaserKey.dll" works as follows: - * - PGM will be unlocked if key = seed - 1 - */ - - /* check key for unlocking ProGraMming resource */ - if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1))) - { - /* correct key received for unlocking PGM resource */ - return 1; - } - - /* still here so key incorrect */ - return 0; -} /*** end of XcpVerifyKeyHook ***/ -#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */ - - -/*********************************** end of hooks.c ************************************/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/ide/DemoBoot.project b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/ide/DemoBoot.project deleted file mode 100644 index c0a3e983..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/ide/DemoBoot.project +++ /dev/null @@ -1,193 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - break main -continue - - - - - - - mingw32-make clean - mingw32-make - - - - None - $(WorkspacePath)/.. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - make clean - make - - - - None - $(WorkspacePath) - - - - - - - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/ide/DemoBoot.workspace b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/ide/DemoBoot.workspace deleted file mode 100644 index 7957a1d7..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/ide/DemoBoot.workspace +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.c deleted file mode 100644 index 0e8c3c43..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.c +++ /dev/null @@ -1,784 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) __attribute__( ( naked ) ); -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n\t" - "BX lr \n\t" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) __attribute__( ( naked ) ); -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n\t" - "BX lr \n\t" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.h deleted file mode 100644 index 2b6b51a7..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/CMSIS/CM3/CoreSupport/core_cm3.h +++ /dev/null @@ -1,1818 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CM3_CORE_H__ -#define __CM3_CORE_H__ - -/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - Error 10: \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' - * . - * - Error 530: \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized - * . - * - Error 550: \n - * __regBasePri = (basePri & 0x1ff); \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed - * . - * - Error 754: \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced - * . - * - Error 750: \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced - * . - * - Error 528: \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced - * . - * - Error 751: \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register - @{ -*/ - - -/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM3_NVIC */ - - -/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM3_SCB */ - - -/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM3_SysTick */ - - -/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM - memory mapped structure for Instrumentation Trace Macrocell (ITM) - @{ - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_CM3_ITM */ - - -/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type - memory mapped structure for Interrupt Type - @{ - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ -/*@}*/ /* end of group CMSIS_CM3_InterruptType */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU - memory mapped structure for Memory Protection Unit (MPU) - @{ - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@}*/ /* end of group CMSIS_CM3_MPU */ -#endif - - -/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - -/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ -/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ -static __INLINE void __WFI() { __ASM ("wfi"); } -static __INLINE void __WFE() { __ASM ("wfe"); } -static __INLINE void __SEV() { __ASM ("sev"); } -static __INLINE void __CLREX() { __ASM ("clrex"); } - -/* intrinsic void __ISB(void) */ -/* intrinsic void __DSB(void) */ -/* intrinsic void __DMB(void) */ -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } - -static __INLINE void __NOP() { __ASM volatile ("nop"); } -static __INLINE void __WFI() { __ASM volatile ("wfi"); } -static __INLINE void __WFE() { __ASM volatile ("wfe"); } -static __INLINE void __SEV() { __ASM volatile ("sev"); } -static __INLINE void __ISB() { __ASM volatile ("isb"); } -static __INLINE void __DSB() { __ASM volatile ("dsb"); } -static __INLINE void __DMB() { __ASM volatile ("dmb"); } -static __INLINE void __CLREX() { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - -/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param PriorityGroup is priority grouping field - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @return priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn The number of the interrupt for read active bit - * @return 1 = interrupt active, 0 = interrupt not active - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param PriorityGroup The used priority group - * @param PreemptPriority The preemptive priority value (starting from 0) - * @param SubPriority The sub priority value (starting from 0) - * @return The encoded priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param Priority The priority for the interrupt - * @param PriorityGroup The used priority group - * @param pPreemptPriority The preemptive priority value (starting from 0) - * @param pSubPriority The sub priority value (starting from 0) - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ - - - -/* ##################################### Debug In/Output function ########################################### */ - -/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface - Core Debug Interface containing: - - Core Debug Receive / Transmit Functions - - Core Debug Defines - - Core Debug Variables -*/ -/*@{*/ - -extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** - * @brief Outputs a character via the ITM channel 0 - * - * @param ch character to output - * @return character to output - * - * The function outputs a character via the ITM channel 0. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** - * @brief Inputs a character via variable ITM_RxBuffer - * - * @return received character, -1 = no character received - * - * The function inputs a character via variable ITM_RxBuffer. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE int ITM_ReceiveChar (void) { - int ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - * @brief Check if a character via variable ITM_RxBuffer is available - * - * @return 1 = character available, 0 = no character available - * - * The function checks variable ITM_RxBuffer whether a character is available or not. - * The function returns '1' if a character is available and '0' if no character is available. - */ -static __INLINE int ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_definitions */ - -#endif /* __CM3_CORE_H__ */ - -/*lint -restore */ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html deleted file mode 100644 index b80f38df..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html +++ /dev/null @@ -1,284 +0,0 @@ - - - - - - - - - - - - -Release Notes for STM32F10x CMSIS - - - - - -
-


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Back to Release page
-

Release -Notes for STM32F10x CMSIS

-

Copyright 2011 STMicroelectronics

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-

Contents

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    -
  1. STM32F10x CMSIS -update History
    2. -
  2. License
    3. -
- -

STM32F10x CMSIS -update History


-

V3.5.0 / 11-March-2011

-

Main -Changes

- -
    -
  • stm32f10x.h -and startup_stm32f10x_hd_vl.s files: remove the FSMC interrupt -definition for STM32F10x High-density Value line devices.
    -
    • -
  • system_stm32f10x.c file provided within the CMSIS folder.
    -
    • - -
- -

3.4.0 -- 10/15/2010

- -
    -
  1. General
    2. -
- -
    -
  • Add support -for STM32F10x High-density Value line devices.
    • -
-
    -
  1. STM32F10x CMSIS Device Peripheral Access Layer
    2. -
- - - -
    -
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    -
    • Update to support High-density Value line devices
      • Add new define STM32F10X_HD_VL
        • -
      • RCC, AFIO, FSMC bits definition updated
        • -
      -
    • - - All -STM32 devices definitions are commented by default. User has to select the -appropriate device before starting else an error will be signaled on compile -time.
      • -
    • Add new IRQs definitons inside the IRQn_Type enumeration for STM23 High-density Value line devices.
      • -
    • "bool" type removed.
      -
      • -
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    -
    • -
      -
    • "system_stm32f10x.c" moved to to "STM32F10x_StdPeriph_Template" directory. This file is also moved to each example directory under "STM32F10x_StdPeriph_Examples".
      -
      • -
    • SystemInit_ExtMemCtl() function: update to support High-density Value line devices.
      • -
    • Add "VECT_TAB_SRAM" inside "system_stm32f10x.c" -to select if the user want to place the Vector Table in internal SRAM. -An additional define is also to specify the Vector Table offset "VECT_TAB_OFFSET".
      -
      • - -
    -
  • STM32F10x CMSIS startup files:startup_stm32f10x_xx.s
    • Add three -startup files for STM32 High-density Value line devices: - startup_stm32f10x_hd_vl.s
    -
-

3.3.0 -- 04/16/2010

- -
  1. General
-
  • Add support -for STM32F10x XL-density devices.
  • Add startup files for TrueSTUDIO toolchain
  1. STM32F10x CMSIS Device Peripheral Access Layer
- -
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    -
    • Update to support XL-density devices
      • Add new define STM32F10X_XL
      • Add new IRQs for TIM9..14
      • Update FLASH_TypeDef structure
      • Add new IP instances TIM9..14
      • RCC, AFIO, DBGMCU bits definition updated
    • Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma "," at the end of enum list)
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    -
    • SystemInit_ExtMemCtl() function: update to support XL-density devices
    • SystemInit() function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions. 
      -
  • STM32F10x CMSIS startup files:
    • add three -startup files for STM32 XL-density devices: - startup_stm32f10x_xl.s
    • startup_stm32f10x_md_vl.s for RIDE7: add USART3 IRQ Handler (was missing in previous version)
    • Add startup files for TrueSTUDIO toolchain
-

3.2.0 -- 03/01/2010

-
    -
  1. General
    2. -
-
    - -
  • STM32F10x CMSIS files updated to CMSIS V1.30 release
    • -
  • Directory structure updated to be aligned with CMSIS V1.30
    -
    • -
  • Add support -for STM32 Low-density Value line (STM32F100x4/6) and -Medium-density Value line (STM32F100x8/B) devices. 
    • - -
-
    -
  1. CMSIS Core Peripheral Access Layer
- -
    -
  1. STM32F10x CMSIS Device Peripheral Access Layer
    2. - -
- -
    - -
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    -
    • -
      -
    • Update -the stm32f10x.h file to support new Value line devices features: CEC -peripheral, new General purpose timers TIM15, TIM16 and TIM17.
      • -
    • Peripherals Bits definitions updated to be in line with Value line devices available features.
      -
      • -
    • HSE_Value, -HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE, -HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy -purposes.
      -
      • -
    -
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    -
    • -
      -
    • SystemFrequency variable name changed to SystemCoreClock
      -
      • -
    • Default - SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.
      -
      • -
    • All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.
      -
      • -
    • Additional function void SystemCoreClockUpdate (void) is provided.
      -
      • -
    -
  • STM32F10x CMSIS Startup files: startup_stm32f10x_xx.s
    • -
      -
    • Add new -startup files for STM32 Low-density Value line devices: - startup_stm32f10x_ld_vl.s
      • -
    • Add new startup -files for STM32 Medium-density Value line devices: - startup_stm32f10x_md_vl.s
      • -
    • SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.
      -To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file
      -
      • -
    • GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.
      -
      • -
    - -
- -
    -
-

License

-

The -enclosed firmware and all the related documentation are not covered by -a License Agreement, if you need such License you can contact your -local STMicroelectronics office.

-

THE -PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO -SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR -ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY -CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY -CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH -THEIR PRODUCTS.

-

 

-
-
-

For -complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers -visit www.st.com/STM32

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h deleted file mode 100644 index af0c7c9a..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h +++ /dev/null @@ -1,8336 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F10x Connectivity line, - * High density, High density value line, Medium density, - * Medium density Value line, Low density, Low density Value line - * and XL-density devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x - * @{ - */ - -#ifndef __STM32F10x_H -#define __STM32F10x_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) - /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ - /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ - /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ - /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ - /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ - /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ - /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ - /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ -#endif -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - - - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 16 and 32 Kbytes. - - Low-density value line devices are STM32F100xx microcontrollers where the Flash - memory density ranges between 16 and 32 Kbytes. - - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 64 and 128 Kbytes. - - Medium-density value line devices are STM32F100xx microcontrollers where the - Flash memory density ranges between 64 and 128 Kbytes. - - High-density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 256 and 512 Kbytes. - - High-density value line devices are STM32F100xx microcontrollers where the - Flash memory density ranges between 256 and 512 Kbytes. - - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 512 and 1024 Kbytes. - - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. - */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) - #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" -#endif - -#if !defined USE_STDPERIPH_DRIVER -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined HSE_VALUE - #ifdef STM32F10X_CL - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - #else - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ - #endif /* STM32F10X_CL */ -#endif /* HSE_VALUE */ - - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ - -#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ - -/** - * @brief STM32F10x Standard Peripheral Library version number - */ -#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F10X_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#ifdef STM32F10X_XL - #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ -#else - #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ -#endif /* STM32F10X_XL */ -#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @brief STM32F10x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - -#ifdef STM32F10X_LD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_LD */ - -#ifdef STM32F10X_LD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_LD_VL */ - -#ifdef STM32F10X_MD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_MD */ - -#ifdef STM32F10X_MD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_MD_VL */ - -#ifdef STM32F10X_HD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ - TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_HD */ - -#ifdef STM32F10X_HD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ - TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ - TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ - DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is - mapped at position 60 only if the MISC_REMAP bit in - the AFIO_MAPR2 register is set) */ -#endif /* STM32F10X_HD_VL */ - -#ifdef STM32F10X_XL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_XL */ - -#ifdef STM32F10X_CL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ -#endif /* STM32F10X_CL */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32f10x.h" -#include - -/** @addtogroup Exported_types - * @{ - */ - -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT -#define HSE_Value HSE_VALUE -#define HSI_Value HSI_VALUE -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; -} ADC_TypeDef; - -/** - * @brief Backup Registers - */ - -typedef struct -{ - uint32_t RESERVED0; - __IO uint16_t DR1; - uint16_t RESERVED1; - __IO uint16_t DR2; - uint16_t RESERVED2; - __IO uint16_t DR3; - uint16_t RESERVED3; - __IO uint16_t DR4; - uint16_t RESERVED4; - __IO uint16_t DR5; - uint16_t RESERVED5; - __IO uint16_t DR6; - uint16_t RESERVED6; - __IO uint16_t DR7; - uint16_t RESERVED7; - __IO uint16_t DR8; - uint16_t RESERVED8; - __IO uint16_t DR9; - uint16_t RESERVED9; - __IO uint16_t DR10; - uint16_t RESERVED10; - __IO uint16_t RTCCR; - uint16_t RESERVED11; - __IO uint16_t CR; - uint16_t RESERVED12; - __IO uint16_t CSR; - uint16_t RESERVED13[5]; - __IO uint16_t DR11; - uint16_t RESERVED14; - __IO uint16_t DR12; - uint16_t RESERVED15; - __IO uint16_t DR13; - uint16_t RESERVED16; - __IO uint16_t DR14; - uint16_t RESERVED17; - __IO uint16_t DR15; - uint16_t RESERVED18; - __IO uint16_t DR16; - uint16_t RESERVED19; - __IO uint16_t DR17; - uint16_t RESERVED20; - __IO uint16_t DR18; - uint16_t RESERVED21; - __IO uint16_t DR19; - uint16_t RESERVED22; - __IO uint16_t DR20; - uint16_t RESERVED23; - __IO uint16_t DR21; - uint16_t RESERVED24; - __IO uint16_t DR22; - uint16_t RESERVED25; - __IO uint16_t DR23; - uint16_t RESERVED26; - __IO uint16_t DR24; - uint16_t RESERVED27; - __IO uint16_t DR25; - uint16_t RESERVED28; - __IO uint16_t DR26; - uint16_t RESERVED29; - __IO uint16_t DR27; - uint16_t RESERVED30; - __IO uint16_t DR28; - uint16_t RESERVED31; - __IO uint16_t DR29; - uint16_t RESERVED32; - __IO uint16_t DR30; - uint16_t RESERVED33; - __IO uint16_t DR31; - uint16_t RESERVED34; - __IO uint16_t DR32; - uint16_t RESERVED35; - __IO uint16_t DR33; - uint16_t RESERVED36; - __IO uint16_t DR34; - uint16_t RESERVED37; - __IO uint16_t DR35; - uint16_t RESERVED38; - __IO uint16_t DR36; - uint16_t RESERVED39; - __IO uint16_t DR37; - uint16_t RESERVED40; - __IO uint16_t DR38; - uint16_t RESERVED41; - __IO uint16_t DR39; - uint16_t RESERVED42; - __IO uint16_t DR40; - uint16_t RESERVED43; - __IO uint16_t DR41; - uint16_t RESERVED44; - __IO uint16_t DR42; - uint16_t RESERVED45; -} BKP_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; - __IO uint32_t TDTR; - __IO uint32_t TDLR; - __IO uint32_t TDHR; -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; - __IO uint32_t RDTR; - __IO uint32_t RDLR; - __IO uint32_t RDHR; -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; - __IO uint32_t MSR; - __IO uint32_t TSR; - __IO uint32_t RF0R; - __IO uint32_t RF1R; - __IO uint32_t IER; - __IO uint32_t ESR; - __IO uint32_t BTR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FMR; - __IO uint32_t FM1R; - uint32_t RESERVED2; - __IO uint32_t FS1R; - uint32_t RESERVED3; - __IO uint32_t FFA1R; - uint32_t RESERVED4; - __IO uint32_t FA1R; - uint32_t RESERVED5[8]; -#ifndef STM32F10X_CL - CAN_FilterRegister_TypeDef sFilterRegister[14]; -#else - CAN_FilterRegister_TypeDef sFilterRegister[28]; -#endif /* STM32F10X_CL */ -} CAN_TypeDef; - -/** - * @brief Consumer Electronics Control (CEC) - */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t OAR; - __IO uint32_t PRES; - __IO uint32_t ESR; - __IO uint32_t CSR; - __IO uint32_t TXD; - __IO uint32_t RXD; -} CEC_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; - __IO uint8_t IDR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CR; -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t SWTRIGR; - __IO uint32_t DHR12R1; - __IO uint32_t DHR12L1; - __IO uint32_t DHR8R1; - __IO uint32_t DHR12R2; - __IO uint32_t DHR12L2; - __IO uint32_t DHR8R2; - __IO uint32_t DHR12RD; - __IO uint32_t DHR12LD; - __IO uint32_t DHR8RD; - __IO uint32_t DOR1; - __IO uint32_t DOR2; -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - __IO uint32_t SR; -#endif -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; - __IO uint32_t CR; -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; - __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t IFCR; -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - uint32_t RESERVED8[567]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - uint32_t RESERVED9[9]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; - __IO uint32_t EMR; - __IO uint32_t RTSR; - __IO uint32_t FTSR; - __IO uint32_t SWIER; - __IO uint32_t PR; -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; - __IO uint32_t KEYR; - __IO uint32_t OPTKEYR; - __IO uint32_t SR; - __IO uint32_t CR; - __IO uint32_t AR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WRPR; -#ifdef STM32F10X_XL - uint32_t RESERVED1[8]; - __IO uint32_t KEYR2; - uint32_t RESERVED2; - __IO uint32_t SR2; - __IO uint32_t CR2; - __IO uint32_t AR2; -#endif /* STM32F10X_XL */ -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ - -typedef struct -{ - __IO uint16_t RDP; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRP0; - __IO uint16_t WRP1; - __IO uint16_t WRP2; - __IO uint16_t WRP3; -} OB_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; - __IO uint32_t SR2; - __IO uint32_t PMEM2; - __IO uint32_t PATT2; - uint32_t RESERVED0; - __IO uint32_t ECCR2; -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; - __IO uint32_t SR3; - __IO uint32_t PMEM3; - __IO uint32_t PATT3; - uint32_t RESERVED0; - __IO uint32_t ECCR3; -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; - __IO uint32_t SR4; - __IO uint32_t PMEM4; - __IO uint32_t PATT4; - __IO uint32_t PIO4; -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t CRL; - __IO uint32_t CRH; - __IO uint32_t IDR; - __IO uint32_t ODR; - __IO uint32_t BSRR; - __IO uint32_t BRR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/** - * @brief Alternate Function I/O - */ - -typedef struct -{ - __IO uint32_t EVCR; - __IO uint32_t MAPR; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t MAPR2; -} AFIO_TypeDef; -/** - * @brief Inter Integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t OAR1; - uint16_t RESERVED2; - __IO uint16_t OAR2; - uint16_t RESERVED3; - __IO uint16_t DR; - uint16_t RESERVED4; - __IO uint16_t SR1; - uint16_t RESERVED5; - __IO uint16_t SR2; - uint16_t RESERVED6; - __IO uint16_t CCR; - uint16_t RESERVED7; - __IO uint16_t TRISE; - uint16_t RESERVED8; -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; - __IO uint32_t PR; - __IO uint32_t RLR; - __IO uint32_t SR; -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFGR; - __IO uint32_t CIR; - __IO uint32_t APB2RSTR; - __IO uint32_t APB1RSTR; - __IO uint32_t AHBENR; - __IO uint32_t APB2ENR; - __IO uint32_t APB1ENR; - __IO uint32_t BDCR; - __IO uint32_t CSR; - -#ifdef STM32F10X_CL - __IO uint32_t AHBRSTR; - __IO uint32_t CFGR2; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - uint32_t RESERVED0; - __IO uint32_t CFGR2; -#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint16_t CRH; - uint16_t RESERVED0; - __IO uint16_t CRL; - uint16_t RESERVED1; - __IO uint16_t PRLH; - uint16_t RESERVED2; - __IO uint16_t PRLL; - uint16_t RESERVED3; - __IO uint16_t DIVH; - uint16_t RESERVED4; - __IO uint16_t DIVL; - uint16_t RESERVED5; - __IO uint16_t CNTH; - uint16_t RESERVED6; - __IO uint16_t CNTL; - uint16_t RESERVED7; - __IO uint16_t ALRH; - uint16_t RESERVED8; - __IO uint16_t ALRL; - uint16_t RESERVED9; -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLKCR; - __IO uint32_t ARG; - __IO uint32_t CMD; - __I uint32_t RESPCMD; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __I uint32_t RESP4; - __IO uint32_t DTIMER; - __IO uint32_t DLEN; - __IO uint32_t DCTRL; - __I uint32_t DCOUNT; - __I uint32_t STA; - __IO uint32_t ICR; - __IO uint32_t MASK; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SR; - uint16_t RESERVED2; - __IO uint16_t DR; - uint16_t RESERVED3; - __IO uint16_t CRCPR; - uint16_t RESERVED4; - __IO uint16_t RXCRCR; - uint16_t RESERVED5; - __IO uint16_t TXCRCR; - uint16_t RESERVED6; - __IO uint16_t I2SCFGR; - uint16_t RESERVED7; - __IO uint16_t I2SPR; - uint16_t RESERVED8; -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SMCR; - uint16_t RESERVED2; - __IO uint16_t DIER; - uint16_t RESERVED3; - __IO uint16_t SR; - uint16_t RESERVED4; - __IO uint16_t EGR; - uint16_t RESERVED5; - __IO uint16_t CCMR1; - uint16_t RESERVED6; - __IO uint16_t CCMR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ARR; - uint16_t RESERVED11; - __IO uint16_t RCR; - uint16_t RESERVED12; - __IO uint16_t CCR1; - uint16_t RESERVED13; - __IO uint16_t CCR2; - uint16_t RESERVED14; - __IO uint16_t CCR3; - uint16_t RESERVED15; - __IO uint16_t CCR4; - uint16_t RESERVED16; - __IO uint16_t BDTR; - uint16_t RESERVED17; - __IO uint16_t DCR; - uint16_t RESERVED18; - __IO uint16_t DMAR; - uint16_t RESERVED19; -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; - uint16_t RESERVED0; - __IO uint16_t DR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CR1; - uint16_t RESERVED3; - __IO uint16_t CR2; - uint16_t RESERVED4; - __IO uint16_t CR3; - uint16_t RESERVED5; - __IO uint16_t GTPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFR; - __IO uint32_t SR; -} WWDG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define CEC_BASE (APB1PERIPH_BASE + 0x7800) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) -#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) -#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) - -#define SDIO_BASE (PERIPH_BASE + 0x18000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ - -#define ETH_BASE (AHBPERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define BKP ((BKP_TypeDef *) BKP_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define CEC ((CEC_TypeDef *) CEC_BASE) -#define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* CRC calculation unit */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ - - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ - -/*!< PVD level configuration */ -#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ -#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ -#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ -#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ -#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ -#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ -#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ -#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ - -#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ - - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ - -/******************************************************************************/ -/* */ -/* Backup registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR11 register *******************/ -#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR12 register *******************/ -#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR13 register *******************/ -#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR14 register *******************/ -#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR15 register *******************/ -#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR16 register *******************/ -#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR17 register *******************/ -#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_DR18 register ********************/ -#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR19 register *******************/ -#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR20 register *******************/ -#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR21 register *******************/ -#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR22 register *******************/ -#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR23 register *******************/ -#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR24 register *******************/ -#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR25 register *******************/ -#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR26 register *******************/ -#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR27 register *******************/ -#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR28 register *******************/ -#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR29 register *******************/ -#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR30 register *******************/ -#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR31 register *******************/ -#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR32 register *******************/ -#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR33 register *******************/ -#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR34 register *******************/ -#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR35 register *******************/ -#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR36 register *******************/ -#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR37 register *******************/ -#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR38 register *******************/ -#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR39 register *******************/ -#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR40 register *******************/ -#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR41 register *******************/ -#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR42 register *******************/ -#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ -#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ -#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ -#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ - -/******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ -#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ -#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ -#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ -#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ -#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ - -#ifdef STM32F10X_CL - #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ - #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ - #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ - #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ -#endif /* STM32F10X_CL */ - -/******************* Bit definition for RCC_CFGR register *******************/ -/*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ - -/*!< ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ - -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ - -#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ - -/*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ - -#ifdef STM32F10X_CL - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ - #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ - - #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ - #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ - #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ - #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#else - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#endif /* STM32F10X_CL */ - -/*!<****************** Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ - -#ifdef STM32F10X_CL - #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ - #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ - #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ - #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ - #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ - #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ -#endif /* STM32F10X_CL */ - -/***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ -#endif - -#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ -#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ -#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ - #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ - #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ - #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ - #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ -#endif /* STM32F10X_XL */ - -/***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ -#endif - -#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ - #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ - #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ - #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ - #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ - #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ - #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ - #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ - #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ - #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ - #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ - #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ - #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ -#endif - -#ifdef STM32F10X_CL - #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ - #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ - #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ -#endif /* STM32F10X_XL */ - -/****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ -#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) - #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ - #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ -#endif - -#ifdef STM32F10X_CL - #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ - #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ - #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ - #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ -#endif /* STM32F10X_CL */ - -/****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ -#endif - -#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ -#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ -#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ - #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ - #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ - #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ - #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ -#endif - -/***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ -#endif - -#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ - #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ - #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ - #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) - #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) - #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ - #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ - #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ - #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ -#endif - -#ifdef STM32F10X_HD_VL - #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ - #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ - #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ - #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ - #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ - #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ - #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ -#endif /* STM32F10X_HD_VL */ - -#ifdef STM32F10X_CL - #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ - #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ - #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ -#endif /* STM32F10X_XL */ - -/******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ - -#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ -#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ - -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ - -#ifdef STM32F10X_CL -/******************* Bit definition for RCC_AHBRSTR register ****************/ - #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ - #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ - -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ - -/*!< PREDIV2 configuration */ - #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ - #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ - #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ - -/*!< PLL2MUL configuration */ - #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ - #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ - #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ - #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ - #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ - #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ - #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ - #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ - #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ - #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ - #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ - -/*!< PLL3MUL configuration */ - #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ - #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ - #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ - #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ - #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ - #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ - #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ - #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ - #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ - #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ - #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ - - #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ - #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ -#endif - -/******************************************************************************/ -/* */ -/* General Purpose and Alternate Function I/O */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/*!<****************** Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ -#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ -#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ -#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ -#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ -#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ -#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ -#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ -#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ -#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ -#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ -#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ -#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ -#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ -#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ -#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ - -/******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ -#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ -#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ -#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ -#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ -#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ -#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ -#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ -#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ -#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ -#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ -#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ -#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ -#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ -#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ -#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ -#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ -#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ -#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ -#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ -#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ -#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ -#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ -#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ -#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ -#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ -#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ -#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ -#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ -#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ -#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ - -#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ -#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ -#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ -#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ -#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ -#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ -#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ -#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ -#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ -#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ -#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ -#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ -#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ -#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ -#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ -#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ -#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ -#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ -#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ -#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ -#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ -#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ -#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ -#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ -#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ -#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ -#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ -#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ -#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ -#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ -#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ -#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ - -/*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ - -#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ -#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ -#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ -#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ - -/*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ -#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ -#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ -#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ -#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ - -#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ - -/****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ - -#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -/* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -/*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -/*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ - -/*!< CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ - -/*!< SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ - -#ifdef STM32F10X_CL -/*!< ETH_REMAP configuration */ - #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ - -/*!< CAN2_REMAP configuration */ - #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ - -/*!< MII_RMII_SEL configuration */ - #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ - -/*!< SPI3_REMAP configuration */ - #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ - -/*!< TIM2ITR1_IREMAP configuration */ - #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ - -/*!< PTP_PPS_REMAP configuration */ - #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ -#endif - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ - -/*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ - -/*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ - -/*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ - -/*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ - -/*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ - -/* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ - -/*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ - -/*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ - -/*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ - -/*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ - -/*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ - -/*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ - -/* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ - -/* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ - -/*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ - -/*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ -#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ -#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ -#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ -#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ -#endif - -#ifdef STM32F10X_HD_VL -#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ -#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ -#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ -#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ -#endif - -#ifdef STM32F10X_XL -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ -#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ -#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ -#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ -#endif - -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ -#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ -#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ - -/******************************************************************************/ -/* */ -/* DMA Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CCR1 register *******************/ -#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ -#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ -#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR2 register *******************/ -#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR3 register *******************/ -#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/*!<****************** Bit definition for DMA_CCR4 register *******************/ -#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/****************** Bit definition for DMA_CCR5 register *******************/ -#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ - -/******************* Bit definition for DMA_CCR6 register *******************/ -#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR7 register *******************/ -#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ - -/****************** Bit definition for DMA_CNDTR1 register ******************/ -#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR2 register ******************/ -#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR3 register ******************/ -#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR4 register ******************/ -#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR5 register ******************/ -#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR6 register ******************/ -#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR7 register ******************/ -#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CPAR1 register *******************/ -#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR2 register *******************/ -#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR3 register *******************/ -#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR4 register *******************/ -#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR5 register *******************/ -#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR6 register *******************/ -#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR7 register *******************/ -#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CMAR1 register *******************/ -#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR2 register *******************/ -#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR3 register *******************/ -#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - - -/****************** Bit definition for DMA_CMAR4 register *******************/ -#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR5 register *******************/ -#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR6 register *******************/ -#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR7 register *******************/ -#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ -#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ -#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ -#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ -#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ - -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ -#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ - - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ -#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ -#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ -#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ -#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ - -#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ - -#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ -#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ -#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ -#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ - -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ - -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ - -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ -#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ - -#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ -#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ -#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ -#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ - -#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ -#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ -#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ - -#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ - -/***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12R2 register ******************/ -#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L2 register ******************/ -#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R2 register ******************/ -#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12RD register ******************/ -#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ -#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12LD register ******************/ -#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ -#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8RD register ******************/ -#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ -#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ - -/******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ - -/******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ - -/******************** Bit definition for DAC_SR register ********************/ -#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ - -/******************************************************************************/ -/* */ -/* CEC */ -/* */ -/******************************************************************************/ -/******************** Bit definition for CEC_CFGR register ******************/ -#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ -#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ -#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ -#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ - -/******************** Bit definition for CEC_OAR register ******************/ -#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ -#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ - -/******************** Bit definition for CEC_PRES register ******************/ -#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ - -/******************** Bit definition for CEC_ESR register ******************/ -#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ -#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ -#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ -#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ -#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ -#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ -#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ - -/******************** Bit definition for CEC_CSR register ******************/ -#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ -#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ -#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ -#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ -#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ -#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ -#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ -#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ - -/******************** Bit definition for CEC_TXD register ******************/ -#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ - -/******************** Bit definition for CEC_RXD register ******************/ -#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ - -/******************************************************************************/ -/* */ -/* TIM */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ -#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ -#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ -#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ -#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ - -#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ - -#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ - -#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ -#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -/******************* Bit definition for TIM_CR2 register ********************/ -#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ -#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ -#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ - -#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ -#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ -#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ -#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ -#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ -#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIM_SMCR register *******************/ -#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ - -#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ -#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ - -#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ -#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ -#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ -#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ - -#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ -#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ - -/******************* Bit definition for TIM_DIER register *******************/ -#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ -#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ -#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ -#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ -#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ -#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ -#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ -#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ -#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ -#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ -#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ -#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ - -/******************** Bit definition for TIM_SR register ********************/ -#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ -#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ -#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ -#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ -#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ -#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ -#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ -#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ -#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ -#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ -#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ -#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIM_EGR register ********************/ -#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ -#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ -#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ -#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ -#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ -#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ -#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ -#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ - -/****************** Bit definition for TIM_CCMR1 register *******************/ -#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ - -#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ -#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ - -#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ - -#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ -#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ - -#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ - -#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ -#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ - -#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ -#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ - -/****************** Bit definition for TIM_CCMR2 register *******************/ -#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ - -#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ -#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ - -#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ - -#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ -#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ - -#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ - -#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ -#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ - -#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ -#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ -#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ -#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ -#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ -#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ -#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ -#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ -#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ -#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ -#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ -#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ -#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ -#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ -#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ -#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ - -/******************* Bit definition for TIM_ARR register ********************/ -#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ - -/******************* Bit definition for TIM_RCR register ********************/ -#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ - -/******************* Bit definition for TIM_CCR1 register *******************/ -#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ - -/******************* Bit definition for TIM_CCR2 register *******************/ -#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ - -/******************* Bit definition for TIM_CCR3 register *******************/ -#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ - -/******************* Bit definition for TIM_CCR4 register *******************/ -#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ - -#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ -#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ -#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ -#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ -#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ -#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ -#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ - -/******************* Bit definition for TIM_DCR register ********************/ -#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ -#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ - -#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ -#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ -#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ -#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ - -/******************* Bit definition for TIM_DMAR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ - -/******************************************************************************/ -/* */ -/* Real-Time Clock */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for RTC_CRH register ********************/ -#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ -#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ -#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ - -/******************* Bit definition for RTC_CRL register ********************/ -#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ -#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ -#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ -#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ -#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ -#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ - -/******************* Bit definition for RTC_PRLH register *******************/ -#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ - -/******************* Bit definition for RTC_PRLL register *******************/ -#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ - -/******************* Bit definition for RTC_DIVH register *******************/ -#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ - -/******************* Bit definition for RTC_DIVL register *******************/ -#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ - -/******************* Bit definition for RTC_CNTH register *******************/ -#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ - -/******************* Bit definition for RTC_CNTL register *******************/ -#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ - -/******************* Bit definition for RTC_ALRH register *******************/ -#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ - -/******************* Bit definition for RTC_ALRL register *******************/ -#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ - -/******************************************************************************/ -/* */ -/* Independent WATCHDOG */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ - -/******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ - -/******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ - -/******************************************************************************/ -/* */ -/* Window WATCHDOG */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CR register ********************/ -#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ -#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ -#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ -#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ -#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ -#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ -#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ - -#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ - -/******************* Bit definition for WWDG_CFR register *******************/ -#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ -#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ - -#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ -#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ - -#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_SR register ********************/ -#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Flexible Static Memory Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for FSMC_BCR1 register *******************/ -#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR2 register *******************/ -#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR3 register *******************/ -#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ -#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR4 register *******************/ -#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BTR1 register ******************/ -#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BTR2 register *******************/ -#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/******************* Bit definition for FSMC_BTR3 register *******************/ -#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BTR4 register *******************/ -#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR1 register ******************/ -#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR2 register ******************/ -#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ -#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR3 register ******************/ -#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR4 register ******************/ -#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_PCR2 register *******************/ -#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ -#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/****************** Bit definition for FSMC_PCR3 register *******************/ -#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/****************** Bit definition for FSMC_PCR4 register *******************/ -#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/******************* Bit definition for FSMC_SR2 register *******************/ -#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/******************* Bit definition for FSMC_SR3 register *******************/ -#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/******************* Bit definition for FSMC_SR4 register *******************/ -#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/****************** Bit definition for FSMC_PMEM2 register ******************/ -#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ -#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ -#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ -#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ -#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PMEM3 register ******************/ -#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ -#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ -#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ -#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ -#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PMEM4 register ******************/ -#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ -#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ -#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ -#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ -#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT2 register ******************/ -#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ -#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ -#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ -#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ -#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT3 register ******************/ -#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ -#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ -#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ -#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ -#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT4 register ******************/ -#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ -#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ -#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ -#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ -#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PIO4 register *******************/ -#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ -#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ -#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ -#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ -#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_ECCR2 register ******************/ -#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ - -/****************** Bit definition for FSMC_ECCR3 register ******************/ -#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ - -/******************************************************************************/ -/* */ -/* SD host Interface */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for SDIO_POWER register ******************/ -#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ -#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ - -/****************** Bit definition for SDIO_CLKCR register ******************/ -#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ -#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ -#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ -#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ - -#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ -#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ -#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ - -#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ - -/******************* Bit definition for SDIO_ARG register *******************/ -#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ - -/******************* Bit definition for SDIO_CMD register *******************/ -#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ - -#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ -#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ -#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ - -#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ -#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ -#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ -#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ -#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ -#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ -#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ - -/***************** Bit definition for SDIO_RESPCMD register *****************/ -#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ - -/****************** Bit definition for SDIO_RESP0 register ******************/ -#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP1 register ******************/ -#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP2 register ******************/ -#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP3 register ******************/ -#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP4 register ******************/ -#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_DTIMER register *****************/ -#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ - -/****************** Bit definition for SDIO_DLEN register *******************/ -#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ - -/****************** Bit definition for SDIO_DCTRL register ******************/ -#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ -#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ -#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ -#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ - -#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ -#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ -#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ -#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ -#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ - -/****************** Bit definition for SDIO_DCOUNT register *****************/ -#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ - -/****************** Bit definition for SDIO_STA register ********************/ -#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ -#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ -#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ -#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ -#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ -#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ -#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ -#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ -#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ -#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ -#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ -#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ -#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ -#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ -#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ -#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ -#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ -#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ -#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ -#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ -#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ -#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ -#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ -#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ - -/******************* Bit definition for SDIO_ICR register *******************/ -#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ -#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ -#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ -#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ -#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ -#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ -#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ -#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ -#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ -#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ -#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ - -/****************** Bit definition for SDIO_MASK register *******************/ -#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ -#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ -#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ -#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ -#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ -#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ -#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ -#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ -#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ -#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ -#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ -#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ -#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ -#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ -#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ -#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ -#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ -#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ -#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ -#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ -#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ -#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ - -/***************** Bit definition for SDIO_FIFOCNT register *****************/ -#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ - -/****************** Bit definition for SDIO_FIFO register *******************/ -#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ - -/******************************************************************************/ -/* */ -/* USB Device FS */ -/* */ -/******************************************************************************/ - -/*!< Endpoint-specific registers */ -/******************* Bit definition for USB_EP0R register *******************/ -#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP1R register *******************/ -#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP2R register *******************/ -#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP3R register *******************/ -#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP4R register *******************/ -#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP5R register *******************/ -#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP6R register *******************/ -#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP7R register *******************/ -#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/*!< Common registers */ -/******************* Bit definition for USB_CNTR register *******************/ -#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ -#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ -#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ -#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ -#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ -#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ -#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ -#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ -#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ -#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ -#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ -#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ -#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ - -/******************* Bit definition for USB_ISTR register *******************/ -#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ -#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ -#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ -#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ -#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ -#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ -#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ -#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ -#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ -#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ - -/******************* Bit definition for USB_FNR register ********************/ -#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ -#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ -#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ -#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ -#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ - -/****************** Bit definition for USB_DADDR register *******************/ -#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ -#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ -#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ -#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ -#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ -#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ -#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ -#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ - -#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ - -/****************** Bit definition for USB_BTABLE register ******************/ -#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ - -/*!< Buffer descriptor table */ -/***************** Bit definition for USB_ADDR0_TX register *****************/ -#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ - -/***************** Bit definition for USB_ADDR1_TX register *****************/ -#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ - -/***************** Bit definition for USB_ADDR2_TX register *****************/ -#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ - -/***************** Bit definition for USB_ADDR3_TX register *****************/ -#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ - -/***************** Bit definition for USB_ADDR4_TX register *****************/ -#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ - -/***************** Bit definition for USB_ADDR5_TX register *****************/ -#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ - -/***************** Bit definition for USB_ADDR6_TX register *****************/ -#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ - -/***************** Bit definition for USB_ADDR7_TX register *****************/ -#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_COUNT0_TX register ****************/ -#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ - -/***************** Bit definition for USB_COUNT1_TX register ****************/ -#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ - -/***************** Bit definition for USB_COUNT2_TX register ****************/ -#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ - -/***************** Bit definition for USB_COUNT3_TX register ****************/ -#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ - -/***************** Bit definition for USB_COUNT4_TX register ****************/ -#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ - -/***************** Bit definition for USB_COUNT5_TX register ****************/ -#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ - -/***************** Bit definition for USB_COUNT6_TX register ****************/ -#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ - -/***************** Bit definition for USB_COUNT7_TX register ****************/ -#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ - -/*----------------------------------------------------------------------------*/ - -/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ -#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ - -/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ -#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ - -/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ -#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ - -/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ -#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ - -/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ -#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ - -/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ -#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ - -/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ -#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ - -/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ -#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ - -/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ -#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ - -/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ -#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ - -/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ -#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ - -/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ -#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ - -/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ -#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ - -/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ -#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ - -/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ -#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ - -/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ -#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_ADDR0_RX register *****************/ -#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ - -/***************** Bit definition for USB_ADDR1_RX register *****************/ -#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ - -/***************** Bit definition for USB_ADDR2_RX register *****************/ -#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ - -/***************** Bit definition for USB_ADDR3_RX register *****************/ -#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ - -/***************** Bit definition for USB_ADDR4_RX register *****************/ -#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ - -/***************** Bit definition for USB_ADDR5_RX register *****************/ -#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ - -/***************** Bit definition for USB_ADDR6_RX register *****************/ -#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ - -/***************** Bit definition for USB_ADDR7_RX register *****************/ -#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_COUNT0_RX register ****************/ -#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT1_RX register ****************/ -#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT2_RX register ****************/ -#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT3_RX register ****************/ -#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT4_RX register ****************/ -#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT5_RX register ****************/ -#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT6_RX register ****************/ -#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT7_RX register ****************/ -#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/*----------------------------------------------------------------------------*/ - -/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ -#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ -#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ -#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ -#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ -#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ -#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ -#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ -#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ -#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ -#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ -#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ -#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ -#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ -#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ -#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ -#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/******************************************************************************/ -/* */ -/* Controller Area Network */ -/* */ -/******************************************************************************/ - -/*!< CAN control and status registers */ -/******************* Bit definition for CAN_MCR register ********************/ -#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ -#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ -#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ -#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ -#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ -#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ -#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ -#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ -#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ - -/******************* Bit definition for CAN_MSR register ********************/ -#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ -#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ -#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ -#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ -#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ -#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ -#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ -#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ -#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ - -/******************* Bit definition for CAN_TSR register ********************/ -#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ -#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ -#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ -#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ -#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ -#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ -#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ -#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ -#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ -#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ -#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ -#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ -#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ -#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ -#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ -#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ - -#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ -#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ -#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ -#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ - -#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ -#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ - -/******************* Bit definition for CAN_RF0R register *******************/ -#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ -#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ -#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ -#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ - -/******************* Bit definition for CAN_RF1R register *******************/ -#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ -#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ -#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ -#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ - -/******************** Bit definition for CAN_IER register *******************/ -#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ -#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ -#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ -#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ -#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ -#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ -#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ -#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ -#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ -#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ - -/******************** Bit definition for CAN_ESR register *******************/ -#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ -#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ -#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ - -#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ -#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - -#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ -#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ - -/******************* Bit definition for CAN_BTR register ********************/ -#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ -#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ -#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ -#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ -#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ -#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ - -/*!< Mailbox registers */ -/****************** Bit definition for CAN_TI0R register ********************/ -#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/****************** Bit definition for CAN_TDT0R register *******************/ -#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/****************** Bit definition for CAN_TDL0R register *******************/ -#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/****************** Bit definition for CAN_TDH0R register *******************/ -#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_TI1R register *******************/ -#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT1R register ******************/ -#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_TDL1R register ******************/ -#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_TDH1R register ******************/ -#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_TI2R register *******************/ -#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ -#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT2R register ******************/ -#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_TDL2R register ******************/ -#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_TDH2R register ******************/ -#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_RI0R register *******************/ -#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT0R register ******************/ -#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ -#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_RDL0R register ******************/ -#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_RDH0R register ******************/ -#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_RI1R register *******************/ -#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ -#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT1R register ******************/ -#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ -#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_RDL1R register ******************/ -#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_RDH1R register ******************/ -#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/*!< CAN filter registers */ -/******************* Bit definition for CAN_FMR register ********************/ -#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ - -/******************* Bit definition for CAN_FM1R register *******************/ -#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ -#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ -#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ -#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ -#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ -#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ -#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ -#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ -#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ -#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ -#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ -#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ -#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ -#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ -#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ - -/******************* Bit definition for CAN_FS1R register *******************/ -#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ -#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ -#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ -#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ -#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ -#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ -#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ -#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ -#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ -#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ -#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ -#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ -#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ -#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ -#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ - -/****************** Bit definition for CAN_FFA1R register *******************/ -#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ -#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ -#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ -#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ -#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ -#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ -#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ -#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ -#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ -#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ -#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ -#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ -#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ -#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ -#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ - -/******************* Bit definition for CAN_FA1R register *******************/ -#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ -#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ -#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ -#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ -#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ -#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ -#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ -#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ -#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ -#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ -#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ -#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ -#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ -#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ -#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ - -/******************* Bit definition for CAN_F0R1 register *******************/ -#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F1R1 register *******************/ -#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F2R1 register *******************/ -#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F3R1 register *******************/ -#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F4R1 register *******************/ -#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F5R1 register *******************/ -#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F6R1 register *******************/ -#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F7R1 register *******************/ -#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F8R1 register *******************/ -#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F9R1 register *******************/ -#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F10R1 register ******************/ -#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F11R1 register ******************/ -#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F12R1 register ******************/ -#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F13R1 register ******************/ -#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F0R2 register *******************/ -#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F1R2 register *******************/ -#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F2R2 register *******************/ -#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F3R2 register *******************/ -#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F4R2 register *******************/ -#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F5R2 register *******************/ -#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F6R2 register *******************/ -#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F7R2 register *******************/ -#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F8R2 register *******************/ -#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F9R2 register *******************/ -#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F10R2 register ******************/ -#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F11R2 register ******************/ -#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F12R2 register ******************/ -#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F13R2 register ******************/ -#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************************************************************************/ -/* */ -/* Serial Peripheral Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ -#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ -#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ - -#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ -#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ -#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ - -#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ -#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ -#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ -#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ -#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ -#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ -#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ -#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ -#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ -#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ -#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ -#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ -#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ -#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ -#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ -#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ - -/******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ - -/******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ - -/****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ - -/****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ - -/****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ - -#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ -#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ - -/****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ -#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ - -/******************************************************************************/ -/* */ -/* Inter-integrated Circuit Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CR1 register ********************/ -#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ -#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ -#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ -#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ -#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ -#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ -#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ -#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ -#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ -#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ -#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ -#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ -#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ -#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ - -/******************* Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ - -#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ -#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ -#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ -#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ -#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ - -/******************* Bit definition for I2C_OAR1 register *******************/ -#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ -#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ - -#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ -#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ -#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ - -#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OAR2 register *******************/ -#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ -#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ - -/******************** Bit definition for I2C_DR register ********************/ -#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ - -/******************* Bit definition for I2C_SR1 register ********************/ -#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ -#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ -#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ -#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ -#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ -#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ -#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ -#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ -#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ -#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ -#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ -#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ -#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ -#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ - -/******************* Bit definition for I2C_SR2 register ********************/ -#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ -#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ -#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ -#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ -#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ -#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ -#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ -#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ - -/******************* Bit definition for I2C_CCR register ********************/ -#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ -#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ - -/****************** Bit definition for I2C_TRISE register *******************/ -#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ - -/******************************************************************************/ -/* */ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for USART_SR register *******************/ -#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ -#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ -#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ -#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ -#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ -#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ -#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ -#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ -#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ -#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ - -/******************* Bit definition for USART_DR register *******************/ -#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ - -/****************** Bit definition for USART_CR1 register *******************/ -#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ -#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ -#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ -#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ -#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ -#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ -#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ -#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ -#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ -#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ -#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ -#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ -#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ - -/****************** Bit definition for USART_CR2 register *******************/ -#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ -#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ -#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ -#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ -#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ -#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ - -#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ -#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ - -/****************** Bit definition for USART_CR3 register *******************/ -#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ -#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ -#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ -#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ -#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ -#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ -#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ -#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ -#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ -#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ -#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ -#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ - -/****************** Bit definition for USART_GTPR register ******************/ -#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ -#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ - -#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ - -/******************************************************************************/ -/* */ -/* Debug MCU */ -/* */ -/******************************************************************************/ - -/**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ - -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ -#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ -#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ -#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ -#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ -#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ -#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ -#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ -#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ -#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ - -/****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ -#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ - -#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ -#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ -#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ - -/******************************************************************************/ -/* */ -/* FLASH and Option Bytes Registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ -#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ -#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ -#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ - -#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ -#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ - -/***************** Bit definition for FLASH_OPTKEYR register ****************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ - -/****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ -#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ -#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ -#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ - -/******************* Bit definition for FLASH_CR register *******************/ -#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ -#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ -#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ -#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ -#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ -#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ -#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ -#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ -#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ -#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ - -/******************* Bit definition for FLASH_AR register *******************/ -#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ - -#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ -#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ -#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ - -/****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for FLASH_RDP register *******************/ -#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ -#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ - -/****************** Bit definition for FLASH_WRP0 register ******************/ -#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP1 register ******************/ -#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP2 register ******************/ -#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP3 register ******************/ -#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -#ifdef STM32F10X_CL -/******************************************************************************/ -/* Ethernet MAC Registers bits definitions */ -/******************************************************************************/ -/* Bit definition for Ethernet MAC Control Register register */ -#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ -#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ -#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ - #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ - #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ - #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ - #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ - #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ - #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ - #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ - #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ -#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ -#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ -#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ -#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ -#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ -#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ -#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ -#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ -#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling - a transmission attempt during retries after a collision: 0 =< r <2^k */ - #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ - #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ - #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ - #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ -#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ -#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ -#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ - -/* Bit definition for Ethernet MAC Frame Filter Register */ -#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ -#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ -#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ -#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ -#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ - #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ - #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ - #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ -#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ -#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ -#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ -#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ -#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ -#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ - -/* Bit definition for Ethernet MAC Hash Table High Register */ -#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ - -/* Bit definition for Ethernet MAC Hash Table Low Register */ -#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ - -/* Bit definition for Ethernet MAC MII Address Register */ -#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ -#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ -#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ - #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ - #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ - #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ -#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ -#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ - -/* Bit definition for Ethernet MAC MII Data Register */ -#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ - -/* Bit definition for Ethernet MAC Flow Control Register */ -#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ -#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ -#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ - #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ - #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ - #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ - #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ -#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ -#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ -#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ -#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ - -/* Bit definition for Ethernet MAC VLAN Tag Register */ -#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ -#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ - -/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ -#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ -/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. - Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ -/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask - Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask - Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask - Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask - Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - - RSVD - Filter1 Command - RSVD - Filter0 Command - Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset - Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 - Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ - -/* Bit definition for Ethernet MAC PMT Control and Status Register */ -#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ -#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ -#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ -#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ -#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ -#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ - -/* Bit definition for Ethernet MAC Status Register */ -#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ -#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ -#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ -#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ -#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ - -/* Bit definition for Ethernet MAC Interrupt Mask Register */ -#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ -#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ - -/* Bit definition for Ethernet MAC Address0 High Register */ -#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ - -/* Bit definition for Ethernet MAC Address0 Low Register */ -#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ - -/* Bit definition for Ethernet MAC Address1 High Register */ -#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ - #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ -#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address1 Low Register */ -#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ - -/* Bit definition for Ethernet MAC Address2 High Register */ -#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ - #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address2 Low Register */ -#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ - -/* Bit definition for Ethernet MAC Address3 High Register */ -#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ - #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ - -/* Bit definition for Ethernet MAC Address3 Low Register */ -#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ - -/******************************************************************************/ -/* Ethernet MMC Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet MMC Contol Register */ -#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ -#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ -#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ -#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ - -/* Bit definition for Ethernet MMC Receive Interrupt Register */ -#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Register */ -#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ -#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ -#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ -#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ -#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ -#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ - -/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ -#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ - -/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ -#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ - -/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ -#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ - -/******************************************************************************/ -/* Ethernet PTP Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet PTP Time Stamp Contol Register */ -#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ -#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ -#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ -#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ -#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ -#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ - -/* Bit definition for Ethernet PTP Sub-Second Increment Register */ -#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ - -/* Bit definition for Ethernet PTP Time Stamp High Register */ -#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ - -/* Bit definition for Ethernet PTP Time Stamp Low Register */ -#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ -#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp High Update Register */ -#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ -#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ -#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Addend Register */ -#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ - -/* Bit definition for Ethernet PTP Target Time High Register */ -#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ - -/* Bit definition for Ethernet PTP Target Time Low Register */ -#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ - -/******************************************************************************/ -/* Ethernet DMA Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet DMA Bus Mode Register */ -#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ -#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ -#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ -#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ - #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ - #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ - #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ - #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ -#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ -#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ -#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ - #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ - #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ - #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ - #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ -#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ -#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ -#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ - -/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ -#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ - -/* Bit definition for Ethernet DMA Receive Poll Demand Register */ -#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ - -/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ -#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ - -/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ -#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ - -/* Bit definition for Ethernet DMA Status Register */ -#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ -#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ -#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ -#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ - /* combination with EBS[2:0] for GetFlagStatus function */ - #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ - #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ - #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ - #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ - #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ - #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ - #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ - #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ - #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ -#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ - #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ - #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ - #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ - #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ - #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ - #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ -#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ -#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ -#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ -#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ -#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ -#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ -#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ -#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ -#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ -#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ -#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ -#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ -#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ -#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ -#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ - -/* Bit definition for Ethernet DMA Operation Mode Register */ -#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ -#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ -#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ -#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ -#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ -#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ - #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ - #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ - #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ - #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ - #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ - #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ - #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ - #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ -#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ -#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ -#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ -#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ - #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ - #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ - #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ - #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ -#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ -#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ - -/* Bit definition for Ethernet DMA Interrupt Enable Register */ -#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ -#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ -#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ -#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ -#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ -#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ -#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ -#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ -#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ -#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ -#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ -#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ -#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ -#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ -#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ - -/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ -#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ -#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ -#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ -#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ - -/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ -#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ -#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ -#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ -#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ -#endif /* STM32F10X_CL */ - -/** - * @} - */ - - /** - * @} - */ - -#ifdef USE_STDPERIPH_DRIVER - #include "stm32f10x_conf.h" -#endif - -/** @addtogroup Exported_macro - * @{ - */ - -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_H */ - -/** - * @} - */ - - /** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/Release_Notes.html b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/Release_Notes.html deleted file mode 100644 index 633e42e3..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/Release_Notes.html +++ /dev/null @@ -1,342 +0,0 @@ - - - - - - - - - - - - -Release Notes for STM32F10x Standard Peripherals Library Drivers - - - - - -
-


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Back to Release page
-

Release -Notes for STM32F10x Standard Peripherals Library Drivers -(StdPeriph_Driver)

-

Copyright 2011 STMicroelectronics

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-

 

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-

Contents

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    -
  1. STM32F10x Standard Peripherals Library -Drivers update History
    2. -
  2. License
    3. -
- - -

STM32F10x Standard -Peripherals Library Drivers  update History


-

V3.5.0 / 11-March-2011

-

Main -Changes

- -
    -
  • stm32f10x_can.h/.c files:
    • -
      -
    • Add 5 new functions
      • -
        -
      • 3 -new functions controlling the counter errors: CAN_GetLastErrorCode(), -CAN_GetReceiveErrorCounter() and CAN_GetLSBTransmitErrorCounter().
        • -
      -
        -
      • 1 new function to select the CAN operating mode: CAN_OperatingModeRequest().
        • -
      -
        -
      • 1 new function to support CAN TT mode: CAN_TTComModeCmd().
        -
        • -
      -
    • CAN_TransmitStatus() function updated to support all CAN transmit intermediate states
      -
      • -
    -
  • stm32f10x_i2c.h/.c files:
    • -
      -
    • Add 1 new function:
      • -
        -
      • I2C_NACKPositionConfig(): -This function configures the same bit (POS) as I2C_PECPositionConfig() -but is intended to be used in I2C mode while I2C_PECPositionConfig() is -intended to used in SMBUS mode.
        • -
      -
    -
  • stm32f10x_tim.h/.c files:
    • -
      -
    • Change the TIM_DMABurstLength_xBytes definitions to TIM_DMABurstLength_xTansfers
      -
      • -
    - - -
- -

3.4.0 -- 10/15/2010

- -
    -
  1. General
    2. -
- -
    -
  • Add support for STM32F10x High-density value line devices.
    • -
- -
    -
  1. STM32F10x_StdPeriph_Driver
    2. -
- - -
    - -
  • stm32f10x_bkp.h/.c
    • -
      -
    • Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file.
      • -
    -
  • stm32f10x_can.h/.c
    • -
      -
    • Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.
      -
      • -
    • Update the wording of some defines and Asserts macro.
      -
      • -
    • CAN_GetFlagStatus() -and CAN_ClearFlag() functions: updated to support new flags (were not -supported in previous version). These flags are:  CAN_FLAG_RQCP0, -CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1, -CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0,   CAN_FLAG_FOV0, -CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC.
      -
      • -
    • CAN_GetITStatus() -function: add a check of the interrupt enable bit before getting the -status of corresponding interrupt pending bit.
      -
      • -
    • CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit.
      -
      • -
    -
  • stm32f10x_crc.h/.c
    • -
      -
    • Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.
      • -
    -
  • stm32f10x_dac.h/.c
    • -
      -
    • Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file.
      • -
    -
  • stm32f10x_dbgmcu.h/.c
    • -
      -
    • Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file.
      • -
    -
  • stm32f10x_dma.h/.c
    • -
      -
    • Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.
      • -
    • Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"
      -
      • -
    -
  • stm32f10x_flash.h/.c
    • -
      -
    • FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.
      • -
    -
  • stm32f10x_fsmc.h/.c
    • -
      -
    • Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.
      • -
    -
  • stm32f10x_gpio.h/.c
    • -
      -
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.
      • -
    -
  • stm32f10x_pwr.h/.c
    • -
      -
    • Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.
      • -
    -
  • stm32f10x_rtc.h/.c
    • -
      -
    • Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.
      • -
    -
  • stm32f10x_spi.h/.c
    • -
      -
    • Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".
      • -
    -
  • stm32f10x_tim.h/.c
    • -
    • Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".
    - -
- -

3.3.0 -- 04/16/2010

- -
  1. General
-
  • Add support for STM32F10x XL-density devices.
  • I2C driver: events description and management enhancement.
-
  1. STM32F10x_StdPeriph_Driver
-
  • stm32f10x_dbgmcu.h/.c
    • DBGMCU_Config() function: add new values DBGMCU_TIMx_STOP (x: 9..14) for DBGMCU_Periph parameter.
  • stm32f10x_flash.h/.c: -updated to support Bank2 of XL-density devices (up to 1MByte of Flash -memory). For more details, refer to the description provided within -stm32f10x_flash.c file.
  • stm32f10x_gpio.h/.c
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for FSMC_NADV pin and TIM9..11,13,14.
  • stm32f10x_i2c.h/.c: I2C events description and management enhancement.
    • I2C_CheckEvent() -function: updated to check whether the last event contains the -I2C_EVENT  (instead of check whether the last event is equal to -I2C_EVENT)
    • Add -detailed description of I2C events and how to manage them using the -functions provided by this driver. For more information, refer to -stm32f10x_i2c.h and stm32f10x_i2c.c files.
  • stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration
  • stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.
  • stm32f10x_sdio.h: 
    • SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter
      change
        -#define -SDIO_ReadWaitMode_CLK               -  ((uint32_t)0x00000000)
        #define -SDIO_ReadWaitMode_DATA2             -((uint32_t)0x00000001)
      by
        #define -SDIO_ReadWaitMode_CLK               -  ((uint32_t)0x00000001)
        #define -SDIO_ReadWaitMode_DATA2             -((uint32_t)0x00000000)
-

3.2.0 -- 03/01/2010

-
    -
  1. General
    2. -
-
    - -
  • Add support -for STM32 Low-density Value line (STM32F100x4/6) and -Medium-density Value line (STM32F100x8/B) devices.
    • -
  • Almost -peripherals drivers were updated to support Value -line devices features
    • -
  • Drivers limitations fix and enhancements.
    • - -
-
    -
  1. STM32F10x_StdPeriph_Driver
    2. -
-
    -
  • Add new -firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c
    • -
  • Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.
    • -
  • RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.
    • -
  • GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: GPIO_Remap_TIM1_DMA, GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.
    • -
  • USART -driver: add support for Oversampling by 8 mode and onebit method. 2 -functions has been added: USART_OverSampling8Cmd() and -USART_OneBitMethodCmd().
    -
    • -
  • DAC -driver: add new functions handling the DAC under run feature: -DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus() -and DAC_ClearITPendingBit().
    • -
  • DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.
    -
    • -
  • FLASH -driver: the FLASH_EraseOptionBytes() function updated. This is now just -erasing the option bytes without modifying the RDP status either -enabled or disabled.
    • -
  • PWR -driver: the PWR_EnterSTOPMode() function updated. When woken up from -STOP mode, this function resets again the SLEEPDEEP bit in the -Cortex-M3 System Control register to allow Sleep mode entering.
    • - - -
-

License

-

The -enclosed firmware and all the related documentation are not covered by -a License Agreement, if you need such License you can contact your -local STMicroelectronics office.

-

THE -PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO -SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR -ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY -CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY -CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH -THEIR PRODUCTS.

-

 

-
-
-

For -complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers -visit www.st.com/STM32

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h deleted file mode 100644 index b8aa49a2..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h +++ /dev/null @@ -1,385 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_gpio.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the GPIO - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_GPIO_H -#define __STM32F10x_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/** @defgroup GPIO_Exported_Types - * @{ - */ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF) || \ - ((PERIPH) == GPIOG)) - -/** - * @brief Output Maximum frequency selection - */ - -typedef enum -{ - GPIO_Speed_10MHz = 1, - GPIO_Speed_2MHz, - GPIO_Speed_50MHz -}GPIOSpeed_TypeDef; -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ - ((SPEED) == GPIO_Speed_50MHz)) - -/** - * @brief Configuration Mode enumeration - */ - -typedef enum -{ GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 -}GPIOMode_TypeDef; - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ - ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ - ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ - ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) - -/** - * @brief GPIO Init structure definition - */ - -typedef struct -{ - uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -}GPIO_InitTypeDef; - - -/** - * @brief Bit_SET and Bit_RESET enumeration - */ - -typedef enum -{ Bit_RESET = 0, - Bit_SET -}BitAction; - -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ - -#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ - -#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) - -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) - -/** - * @} - */ - -/** @defgroup GPIO_Remap_define - * @{ - */ - -#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ -#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ -#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ -#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ -#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ -#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ -#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ -#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ -#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ -#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ -#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ -#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ -#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ -#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ -#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ -#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected - to TIM2 Internal Trigger 1 for calibration - (only for Connectivity line devices) */ -#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ - -#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ - -#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ -#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ -#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ - -#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ -#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ -#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, - only for High density Value line devices) */ - -#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ - ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ - ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ - ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ - ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ - ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ - ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ - ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ - ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ - ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ - ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ - ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ - ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ - ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ - ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ - ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ - ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ - ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ - ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ - ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ - ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \ - ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) - -/** - * @} - */ - -/** @defgroup GPIO_Port_Sources - * @{ - */ - -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOB ((uint8_t)0x01) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) -#define GPIO_PortSourceGPIOD ((uint8_t)0x03) -#define GPIO_PortSourceGPIOE ((uint8_t)0x04) -#define GPIO_PortSourceGPIOF ((uint8_t)0x05) -#define GPIO_PortSourceGPIOG ((uint8_t)0x06) -#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOE)) - -#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOG)) - -/** - * @} - */ - -/** @defgroup GPIO_Pin_sources - * @{ - */ - -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) - -/** - * @} - */ - -/** @defgroup Ethernet_Media_Interface - * @{ - */ -#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) -#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) - -#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ - ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) - -/** - * @} - */ -/** - * @} - */ - -/** @defgroup GPIO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions - * @{ - */ - -void GPIO_DeInit(GPIO_TypeDef* GPIOx); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_EventOutputCmd(FunctionalState NewState); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_GPIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h deleted file mode 100644 index b3b7d821..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h +++ /dev/null @@ -1,727 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rcc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the RCC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_RCC_H -#define __STM32F10x_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/** @defgroup RCC_Exported_Types - * @{ - */ - -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ - uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/** - * @} - */ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup HSE_configuration - * @{ - */ - -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00010000) -#define RCC_HSE_Bypass ((uint32_t)0x00040000) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) - -/** - * @} - */ - -/** @defgroup PLL_entry_clock_source - * @{ - */ - -#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) - #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) - #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) - #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div2)) -#else - #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) - #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_PREDIV1)) -#endif /* STM32F10X_CL */ - -/** - * @} - */ - -/** @defgroup PLL_multiplication_factor - * @{ - */ -#ifndef STM32F10X_CL - #define RCC_PLLMul_2 ((uint32_t)0x00000000) - #define RCC_PLLMul_3 ((uint32_t)0x00040000) - #define RCC_PLLMul_4 ((uint32_t)0x00080000) - #define RCC_PLLMul_5 ((uint32_t)0x000C0000) - #define RCC_PLLMul_6 ((uint32_t)0x00100000) - #define RCC_PLLMul_7 ((uint32_t)0x00140000) - #define RCC_PLLMul_8 ((uint32_t)0x00180000) - #define RCC_PLLMul_9 ((uint32_t)0x001C0000) - #define RCC_PLLMul_10 ((uint32_t)0x00200000) - #define RCC_PLLMul_11 ((uint32_t)0x00240000) - #define RCC_PLLMul_12 ((uint32_t)0x00280000) - #define RCC_PLLMul_13 ((uint32_t)0x002C0000) - #define RCC_PLLMul_14 ((uint32_t)0x00300000) - #define RCC_PLLMul_15 ((uint32_t)0x00340000) - #define RCC_PLLMul_16 ((uint32_t)0x00380000) - #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ - ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ - ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ - ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ - ((MUL) == RCC_PLLMul_16)) - -#else - #define RCC_PLLMul_4 ((uint32_t)0x00080000) - #define RCC_PLLMul_5 ((uint32_t)0x000C0000) - #define RCC_PLLMul_6 ((uint32_t)0x00100000) - #define RCC_PLLMul_7 ((uint32_t)0x00140000) - #define RCC_PLLMul_8 ((uint32_t)0x00180000) - #define RCC_PLLMul_9 ((uint32_t)0x001C0000) - #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) - - #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_6_5)) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup PREDIV1_division_factor - * @{ - */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) - #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) - #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) - #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) - #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) - #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) - #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) - #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) - #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) - #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) - #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) - #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) - #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) - #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) - #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) - #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) - #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) - - #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ - ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ - ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ - ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ - ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ - ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ - ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ - ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) -#endif -/** - * @} - */ - - -/** @defgroup PREDIV1_clock_source - * @{ - */ -#ifdef STM32F10X_CL -/* PREDIV1 clock source (for STM32 connectivity line devices) */ - #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) - #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) - - #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ - ((SOURCE) == RCC_PREDIV1_Source_PLL2)) -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/* PREDIV1 clock source (for STM32 Value line devices) */ - #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) - - #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) -#endif -/** - * @} - */ - -#ifdef STM32F10X_CL -/** @defgroup PREDIV2_division_factor - * @{ - */ - - #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) - #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) - #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) - #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) - #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) - #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) - #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) - #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) - #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) - #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) - #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) - #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) - #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) - #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) - #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) - #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) - - #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ - ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ - ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ - ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ - ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ - ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ - ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ - ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) -/** - * @} - */ - - -/** @defgroup PLL2_multiplication_factor - * @{ - */ - - #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) - #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) - #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) - #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) - #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) - #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) - #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) - #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) - #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) - - #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ - ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ - ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ - ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ - ((MUL) == RCC_PLL2Mul_20)) -/** - * @} - */ - - -/** @defgroup PLL3_multiplication_factor - * @{ - */ - - #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) - #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) - #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) - #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) - #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) - #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) - #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) - #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) - #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) - - #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ - ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ - ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ - ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ - ((MUL) == RCC_PLL3Mul_20)) -/** - * @} - */ - -#endif /* STM32F10X_CL */ - - -/** @defgroup System_clock_source - * @{ - */ - -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup AHB_clock_source - * @{ - */ - -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup APB1_APB2_clock_source - * @{ - */ - -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00000400) -#define RCC_HCLK_Div4 ((uint32_t)0x00000500) -#define RCC_HCLK_Div8 ((uint32_t)0x00000600) -#define RCC_HCLK_Div16 ((uint32_t)0x00000700) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt_source - * @{ - */ - -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) - -#ifndef STM32F10X_CL - #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) - #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) - #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) -#else - #define RCC_IT_PLL2RDY ((uint8_t)0x20) - #define RCC_IT_PLL3RDY ((uint8_t)0x40) - #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) - #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) - #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) -#endif /* STM32F10X_CL */ - - -/** - * @} - */ - -#ifndef STM32F10X_CL -/** @defgroup USB_Device_clock_source - * @{ - */ - - #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) - #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) - - #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ - ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) -/** - * @} - */ -#else -/** @defgroup USB_OTG_FS_clock_source - * @{ - */ - #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) - #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) - - #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ - ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) -/** - * @} - */ -#endif /* STM32F10X_CL */ - - -#ifdef STM32F10X_CL -/** @defgroup I2S2_clock_source - * @{ - */ - #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) - #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) - - #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ - ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) -/** - * @} - */ - -/** @defgroup I2S3_clock_source - * @{ - */ - #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) - #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) - - #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ - ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) -/** - * @} - */ -#endif /* STM32F10X_CL */ - - -/** @defgroup ADC_clock_source - * @{ - */ - -#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) -#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) -#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) -#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) -#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ - ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) -/** - * @} - */ - -/** @defgroup LSE_configuration - * @{ - */ - -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RTC_clock_source - * @{ - */ - -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) -/** - * @} - */ - -/** @defgroup AHB_peripheral - * @{ - */ - -#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) -#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) -#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) -#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) - -#ifndef STM32F10X_CL - #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) - #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) - #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) -#else - #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) - #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) - #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) - #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) - - #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) - #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup APB2_peripheral - * @{ - */ - -#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) -#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) -#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) -#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) -#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) -#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) -#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) -#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) -#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup APB1_peripheral - * @{ - */ - -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) -#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) -#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_USB ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) - -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup Clock_source_to_output_on_MCO_pin - * @{ - */ - -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) -#define RCC_MCO_HSE ((uint8_t)0x06) -#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) - -#ifndef STM32F10X_CL - #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ - ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ - ((MCO) == RCC_MCO_PLLCLK_Div2)) -#else - #define RCC_MCO_PLL2CLK ((uint8_t)0x08) - #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) - #define RCC_MCO_XT1 ((uint8_t)0x0A) - #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) - - #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ - ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ - ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ - ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ - ((MCO) == RCC_MCO_PLL3CLK)) -#endif /* STM32F10X_CL */ - -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ - -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -#ifndef STM32F10X_CL - #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ - ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ - ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ - ((FLAG) == RCC_FLAG_LPWRRST)) -#else - #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) - #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) - #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ - ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ - ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ - ((FLAG) == RCC_FLAG_LPWRRST)) -#endif /* STM32F10X_CL */ - -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RCC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions - * @{ - */ - -void RCC_DeInit(void); -void RCC_HSEConfig(uint32_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) - void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); -#endif - -#ifdef STM32F10X_CL - void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); - void RCC_PLL2Config(uint32_t RCC_PLL2Mul); - void RCC_PLL2Cmd(FunctionalState NewState); - void RCC_PLL3Config(uint32_t RCC_PLL3Mul); - void RCC_PLL3Cmd(FunctionalState NewState); -#endif /* STM32F10X_CL */ - -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); - -#ifndef STM32F10X_CL - void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); -#else - void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); -#endif /* STM32F10X_CL */ - -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); - -#ifdef STM32F10X_CL - void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); - void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); -#endif /* STM32F10X_CL */ - -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -#ifdef STM32F10X_CL -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -#endif /* STM32F10X_CL */ - -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCO); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_RCC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h deleted file mode 100644 index 6056c4c6..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h +++ /dev/null @@ -1,487 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_spi.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the SPI firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_SPI_H -#define __STM32F10x_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Exported_Types - * @{ - */ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/** - * @} - */ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx) || \ - ((MODE) == I2S_Mode_MasterRx) ) -/** - * @} - */ - -/** @defgroup I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) -#define I2S_IT_UDR ((uint8_t)0x53) -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ - ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SPI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions - * @{ - */ - -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_SPI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h deleted file mode 100644 index 61ae249a..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h +++ /dev/null @@ -1,412 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_usart.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_USART_H -#define __STM32F10x_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/** @defgroup USART_Exported_Types - * @{ - */ - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - - uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/** - * @} - */ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4) || \ - ((PERIPH) == UART5)) - -#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3)) - -#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4)) -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_0_5) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) -#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @{ - */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) -#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) - -#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) -#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\ - ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ - || ((USART_FLAG) != USART_FLAG_CTS)) -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) -#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup USART_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Exported_Functions - * @{ - */ - -void USART_DeInit(USART_TypeDef* USARTx); -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); -void USART_SendBreak(USART_TypeDef* USARTx); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_USART_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c deleted file mode 100644 index 93dbcd7c..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c +++ /dev/null @@ -1,650 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_gpio.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the GPIO firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_gpio.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/** @defgroup GPIO_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Defines - * @{ - */ - -/* ------------ RCC registers bit address in the alias region ----------------*/ -#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) - -/* --- EVENTCR Register -----*/ - -/* Alias word address of EVOE bit */ -#define EVCR_OFFSET (AFIO_OFFSET + 0x00) -#define EVOE_BitNumber ((uint8_t)0x07) -#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) - - -/* --- MAPR Register ---*/ -/* Alias word address of MII_RMII_SEL bit */ -#define MAPR_OFFSET (AFIO_OFFSET + 0x04) -#define MII_RMII_SEL_BitNumber ((u8)0x17) -#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) - - -#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) -/** - * @} - */ - -/** @defgroup GPIO_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if (GPIOx == GPIOA) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); - } - else if (GPIOx == GPIOB) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); - } - else if (GPIOx == GPIOC) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); - } - else if (GPIOx == GPIOD) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); - } - else if (GPIOx == GPIOE) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); - } - else if (GPIOx == GPIOF) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); - } - else - { - if (GPIOx == GPIOG) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); - } - } -} - -/** - * @brief Deinitializes the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * @param None - * @retval None - */ -void GPIO_AFIODeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified - * parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - -/*---------------------------- GPIO Mode Configuration -----------------------*/ - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - { - /* Check the parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - /* Output mode */ - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } -/*---------------------------- GPIO CRL Configuration ------------------------*/ - /* Configure the eight low port pins */ - if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) - { - tmpreg = GPIOx->CRL; - for (pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - if (currentpin == pos) - { - pos = pinpos << 2; - /* Clear the corresponding low control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tmpreg |= (currentmode << pos); - /* Reset the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BRR = (((uint32_t)0x01) << pinpos); - } - else - { - /* Set the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSRR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CRL = tmpreg; - } -/*---------------------------- GPIO CRH Configuration ------------------------*/ - /* Configure the eight high port pins */ - if (GPIO_InitStruct->GPIO_Pin > 0x00FF) - { - tmpreg = GPIOx->CRH; - for (pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x08)); - /* Get the port pins position */ - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - if (currentpin == pos) - { - pos = pinpos << 2; - /* Clear the corresponding high control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tmpreg |= (currentmode << pos); - /* Reset the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - /* Set the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - } - } - GPIOx->CRH = tmpreg; - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRR = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BRR = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRR = GPIO_Pin; - } - else - { - GPIOx->BRR = GPIO_Pin; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; -} - -/** - * @brief Selects the GPIO pin used as Event output. - * @param GPIO_PortSource: selects the GPIO port to be used as source - * for Event output. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). - * @param GPIO_PinSource: specifies the pin for the Event output. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @retval None - */ -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - - tmpreg = AFIO->EVCR; - /* Clear the PORT[6:4] and PIN[3:0] bits */ - tmpreg &= EVCR_PORTPINCONFIG_MASK; - tmpreg |= (uint32_t)GPIO_PortSource << 0x04; - tmpreg |= GPIO_PinSource; - AFIO->EVCR = tmpreg; -} - -/** - * @brief Enables or disables the Event Output. - * @param NewState: new state of the Event output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_EventOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; -} - -/** - * @brief Changes the mapping of the specified pin. - * @param GPIO_Remap: selects the pin to remap. - * This parameter can be one of the following values: - * @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping - * @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping - * @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping - * @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping - * @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping - * @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping - * @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping - * @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping - * @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping - * @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping - * @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping - * @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping - * @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping - * @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping - * @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping - * @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping - * @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping - * @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration - * @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping - * @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping - * @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping - * @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping - * @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices) - * @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices) - * @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST - * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled - * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP) - * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) - * When the SPI3/I2S3 is remapped using this function, the SWJ is configured - * to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST. - * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected - * to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) - * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to - * Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. - * @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) - * @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices) - * @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices) - * @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices) - * @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices) - * @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices) - * @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices) - * @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices) - * @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices) - * @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) - * @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) - * @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) - * @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) - * @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices) - * @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, - * only for High density Value line devices) - * @param NewState: new state of the port pin remapping. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) -{ - uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_REMAP(GPIO_Remap)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - tmpreg = AFIO->MAPR2; - } - else - { - tmpreg = AFIO->MAPR; - } - - tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - tmp = GPIO_Remap & LSB_MASK; - - if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) - { - tmpreg &= DBGAFR_SWJCFG_MASK; - AFIO->MAPR &= DBGAFR_SWJCFG_MASK; - } - else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - else - { - tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - - if (NewState != DISABLE) - { - tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); - } - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - AFIO->MAPR2 = tmpreg; - } - else - { - AFIO->MAPR = tmpreg; - } -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). - * @param GPIO_PinSource: specifies the EXTI line to be configured. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @retval None - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmp = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - - tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); - AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; - AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); -} - -/** - * @brief Selects the Ethernet media interface. - * @note This function applies only to STM32 Connectivity line devices. - * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. - * This parameter can be one of the following values: - * @arg GPIO_ETH_MediaInterface_MII: MII mode - * @arg GPIO_ETH_MediaInterface_RMII: RMII mode - * @retval None - */ -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) -{ - assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); - - /* Configure MII_RMII selection bit */ - *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c deleted file mode 100644 index 4b2ec1f1..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c +++ /dev/null @@ -1,1470 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rcc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the RCC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/** @defgroup RCC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Defines - * @{ - */ - -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) - -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) - -#ifdef STM32F10X_CL - /* Alias word address of PLL2ON bit */ - #define PLL2ON_BitNumber 0x1A - #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) - - /* Alias word address of PLL3ON bit */ - #define PLL3ON_BitNumber 0x1C - #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) - -/* --- CFGR Register ---*/ - -/* Alias word address of USBPRE bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x04) - -#ifndef STM32F10X_CL - #define USBPRE_BitNumber 0x16 - #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) -#else - #define OTGFSPRE_BitNumber 0x16 - #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* --- BDCR Register ---*/ - -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x20) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) - -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x24) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) - -#ifdef STM32F10X_CL -/* --- CFGR2 Register ---*/ - - /* Alias word address of I2S2SRC bit */ - #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) - #define I2S2SRC_BitNumber 0x11 - #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) - - /* Alias word address of I2S3SRC bit */ - #define I2S3SRC_BitNumber 0x12 - #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* ---------------------- RCC registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CR_HSEBYP_Set ((uint32_t)0x00040000) -#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CR_HSEON_Set ((uint32_t)0x00010000) -#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -/* CFGR register bit mask */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) - #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) -#else - #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) -#endif /* STM32F10X_CL */ - -#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) -#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) -#define CFGR_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) -#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) -#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) -#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) -#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) -#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) - -/* CSR register bit mask */ -#define CSR_RMVF_Set ((uint32_t)0x01000000) - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) -/* CFGR2 register bit mask */ - #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) - #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) -#endif -#ifdef STM32F10X_CL - #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) - #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) - #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) -#endif /* STM32F10X_CL */ - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CFGR register byte 4 (Bits[31:24]) base address */ -#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) - -/* BDCR register base address */ -#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - -/** - * @} - */ - -/** @defgroup RCC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Variables - * @{ - */ - -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; - -/** - * @} - */ - -/** @defgroup RCC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#ifndef STM32F10X_CL - RCC->CFGR &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR &= (uint32_t)0xF0FF0000; -#endif /* STM32F10X_CL */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - -#ifdef STM32F10X_CL - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#endif /* STM32F10X_CL */ - -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note HSE can not be stopped if it is used directly or through the PLL as system clock. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: HSE oscillator OFF - * @arg RCC_HSE_ON: HSE oscillator ON - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - /* Reset HSEON bit */ - RCC->CR &= CR_HSEON_Reset; - /* Reset HSEBYP bit */ - RCC->CR &= CR_HSEBYP_Reset; - /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ - switch(RCC_HSE) - { - case RCC_HSE_ON: - /* Set HSEON bit */ - RCC->CR |= CR_HSEON_Set; - break; - - case RCC_HSE_Bypass: - /* Set HSEBYP and HSEON bits */ - RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; - break; - - default: - break; - } -} - -/** - * @brief Waits for HSE start-up. - * @param None - * @retval An ErrorStatus enumuration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - ErrorStatus status = ERROR; - FlagStatus HSEStatus = RESET; - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @param HSICalibrationValue: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - tmpreg = RCC->CR; - /* Clear HSITRIM[4:0] bits */ - tmpreg &= CR_HSITRIM_Mask; - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note HSI can not be stopped if it is used directly or through the PLL as system clock. - * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLL clock source and multiplication factor. - * @note This function must be used only when the PLL is disabled. - * @param RCC_PLLSource: specifies the PLL entry clock source. - * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, - * this parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry - * @param RCC_PLLMul: specifies the PLL multiplication factor. - * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} - * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); - - tmpreg = RCC->CFGR; - /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - tmpreg &= CFGR_PLL_Mask; - /* Set the PLL configuration bits */ - tmpreg |= RCC_PLLSource | RCC_PLLMul; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Enables or disables the PLL. - * @note The PLL can not be disabled if it is used as system clock. - * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) -/** - * @brief Configures the PREDIV1 division factor. - * @note - * - This function must be used only when the PLL is disabled. - * - This function applies only to STM32 Connectivity line and Value line - * devices. - * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. - * This parameter can be one of the following values: - * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock - * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock - * @note - * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE - * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. - * This parameter can be RCC_PREDIV1_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); - assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ - tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); - /* Set the PREDIV1 clock source and division factor */ - tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} -#endif - -#ifdef STM32F10X_CL -/** - * @brief Configures the PREDIV2 division factor. - * @note - * - This function must be used only when both PLL2 and PLL3 are disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. - * This parameter can be RCC_PREDIV2_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV2[3:0] bits */ - tmpreg &= ~CFGR2_PREDIV2; - /* Set the PREDIV2 division factor */ - tmpreg |= RCC_PREDIV2_Div; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - -/** - * @brief Configures the PLL2 multiplication factor. - * @note - * - This function must be used only when the PLL2 is disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. - * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL2Config(uint32_t RCC_PLL2Mul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); - - tmpreg = RCC->CFGR2; - /* Clear PLL2Mul[3:0] bits */ - tmpreg &= ~CFGR2_PLL2MUL; - /* Set the PLL2 configuration bits */ - tmpreg |= RCC_PLL2Mul; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - - -/** - * @brief Enables or disables the PLL2. - * @note - * - The PLL2 can not be disabled if it is used indirectly as system clock - * (i.e. it is used as PLL clock entry that is used as System clock). - * - This function applies only to STM32 Connectivity line devices. - * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL2Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; -} - - -/** - * @brief Configures the PLL3 multiplication factor. - * @note - * - This function must be used only when the PLL3 is disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. - * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL3Config(uint32_t RCC_PLL3Mul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); - - tmpreg = RCC->CFGR2; - /* Clear PLL3Mul[3:0] bits */ - tmpreg &= ~CFGR2_PLL3MUL; - /* Set the PLL3 configuration bits */ - tmpreg |= RCC_PLL3Mul; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - - -/** - * @brief Enables or disables the PLL3. - * @note This function applies only to STM32 Connectivity line devices. - * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL3Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the system clock (SYSCLK). - * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - tmpreg = RCC->CFGR; - /* Clear SW[1:0] bits */ - tmpreg &= CFGR_SW_Mask; - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can - * be one of the following: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - tmpreg = RCC->CFGR; - /* Clear HPRE[3:0] bits */ - tmpreg &= CFGR_HPRE_Reset_Mask; - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - tmpreg = RCC->CFGR; - /* Clear PPRE1[2:0] bits */ - tmpreg &= CFGR_PPRE1_Reset_Mask; - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - tmpreg = RCC->CFGR; - /* Clear PPRE2[2:0] bits */ - tmpreg &= CFGR_PPRE2_Reset_Mask; - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Enables or disables the specified RCC interrupts. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -#ifndef STM32F10X_CL -/** - * @brief Configures the USB clock (USBCLK). - * @param RCC_USBCLKSource: specifies the USB clock source. This clock is - * derived from the PLL output. - * This parameter can be one of the following values: - * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB - * clock source - * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source - * @retval None - */ -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); - - *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; -} -#else -/** - * @brief Configures the USB OTG FS clock (OTGFSCLK). - * This function applies only to STM32 Connectivity line devices. - * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. - * This clock is derived from the PLL output. - * This parameter can be one of the following values: - * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source - * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source - * @retval None - */ -void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); - - *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the ADC clock (ADCCLK). - * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from - * the APB2 clock (PCLK2). - * This parameter can be one of the following values: - * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 - * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 - * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 - * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 - * @retval None - */ -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); - tmpreg = RCC->CFGR; - /* Clear ADCPRE[1:0] bits */ - tmpreg &= CFGR_ADCPRE_Reset_Mask; - /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ - tmpreg |= RCC_PCLK2; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -#ifdef STM32F10X_CL -/** - * @brief Configures the I2S2 clock source(I2S2CLK). - * @note - * - This function must be called before enabling I2S2 APB clock. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry - * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry - * @retval None - */ -void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); - - *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; -} - -/** - * @brief Configures the I2S3 clock source(I2S2CLK). - * @note - * - This function must be called before enabling I2S3 APB clock. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry - * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry - * @retval None - */ -void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); - - *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: LSE oscillator OFF - * @arg RCC_LSE_ON: LSE oscillator ON - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - /* Reset LSEBYP bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - switch(RCC_LSE) - { - case RCC_LSE_ON: - /* Set LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - break; - - case RCC_LSE_Bypass: - /* Set LSEBYP and LSEON bits */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - - default: - break; - } -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset. - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - /* Select the RTC clock source */ - RCC->BDCR |= RCC_RTCCLKSource; -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Returns the frequencies of different on chip clocks. - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * @note The result of this function could be not correct when using - * fractional value for HSE crystal. - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; - -#ifdef STM32F10X_CL - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - uint32_t prediv1factor = 0; -#endif - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & CFGR_SWS_Mask; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & CFGR_PLLMull_Mask; - pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; - -#ifndef STM32F10X_CL - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; - } - else - { - #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; - #else - /* HSE selected as PLL clock entry */ - if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; - } - else - { - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; - } - #endif - } -#else - pllmull = pllmull >> 18; - - if (pllmull != 0x0D) - { - pllmull += 2; - } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; - } - - if (pllsource == 0x00) - {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; - - if (prediv1source == 0) - { /* HSE oscillator clock selected as PREDIV1 clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; - RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; - } - } -#endif /* STM32F10X_CL */ - break; - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - - /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ - /* Get HCLK prescaler */ - tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; - tmp = tmp >> 11; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - /* Get ADCCLK prescaler */ - tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; - tmp = tmp >> 14; - presc = ADCPrescTable[tmp]; - /* ADCCLK clock frequency */ - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; -} - -/** - * @brief Enables or disables the AHB peripheral clock. - * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values: - * @arg RCC_AHBPeriph_DMA1 - * @arg RCC_AHBPeriph_DMA2 - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_FLITF - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_OTG_FS - * @arg RCC_AHBPeriph_ETH_MAC - * @arg RCC_AHBPeriph_ETH_MAC_Tx - * @arg RCC_AHBPeriph_ETH_MAC_Rx - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values: - * @arg RCC_AHBPeriph_DMA1 - * @arg RCC_AHBPeriph_DMA2 - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_FLITF - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_FSMC - * @arg RCC_AHBPeriph_SDIO - * - * @note SRAM and FLITF clock can be disabled only during sleep mode. - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBENR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, - * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, - * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, - * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, - * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, - * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, - * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, - * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, - * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, - * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, - * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, - * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, - * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -#ifdef STM32F10X_CL -/** - * @brief Forces or releases AHB peripheral reset. - * @note This function applies only to STM32 Connectivity line devices. - * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_OTG_FS - * @arg RCC_AHBPeriph_ETH_MAC - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBRSTR |= RCC_AHBPeriph; - } - else - { - RCC->AHBRSTR &= ~RCC_AHBPeriph; - } -} -#endif /* STM32F10X_CL */ - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, - * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, - * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, - * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, - * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, - * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, - * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, - * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, - * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, - * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, - * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, - * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, - * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases the Backup domain reset. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @param NewState: new state of the Clock Security System.. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO pin. - * @param RCC_MCO: specifies the clock source to output. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_MCO_NoClock: No clock selected - * @arg RCC_MCO_SYSCLK: System clock selected - * @arg RCC_MCO_HSI: HSI oscillator clock selected - * @arg RCC_MCO_HSE: HSE oscillator clock selected - * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected - * @arg RCC_MCO_PLL2CLK: PLL2 clock selected - * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected - * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected - * @arg RCC_MCO_PLL3CLK: PLL3 clock selected - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_MCO_NoClock: No clock selected - * @arg RCC_MCO_SYSCLK: System clock selected - * @arg RCC_MCO_HSI: HSI oscillator clock selected - * @arg RCC_MCO_HSE: HSE oscillator clock selected - * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected - * - * @retval None - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCO)); - - /* Perform Byte access to MCO bits to select the MCO source */ - *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready - * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 2) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_Mask; - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= CSR_RMVF_Set; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c deleted file mode 100644 index 51a9cce7..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c +++ /dev/null @@ -1,908 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_spi.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the SPI firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_spi.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/** @defgroup SPI_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - - -/** @defgroup SPI_Private_Defines - * @{ - */ - -/* SPI SPE mask */ -#define CR1_SPE_Set ((uint16_t)0x0040) -#define CR1_SPE_Reset ((uint16_t)0xFFBF) - -/* I2S I2SE mask */ -#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) -#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) - -/* SPI CRCNext mask */ -#define CR1_CRCNext_Set ((uint16_t)0x1000) - -/* SPI CRCEN mask */ -#define CR1_CRCEN_Set ((uint16_t)0x2000) -#define CR1_CRCEN_Reset ((uint16_t)0xDFFF) - -/* SPI SSOE mask */ -#define CR2_SSOE_Set ((uint16_t)0x0004) -#define CR2_SSOE_Reset ((uint16_t)0xFFFB) - -/* SPI registers Masks */ -#define CR1_CLEAR_Mask ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) - -/* SPI or I2S mode selection masks */ -#define SPI_Mode_Select ((uint16_t)0xF7FF) -#define I2S_Mode_Select ((uint16_t)0x0800) - -/* I2S clock source selection masks */ -#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) -#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) -#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) -#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) - -/** - * @} - */ - -/** @defgroup SPI_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values (Affects also the I2Ss). - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else - { - if (SPIx == SPI3) - { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - } -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= SPI_Mode_Select; - -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral - * (configured in I2S mode). - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * @note - * The function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. * - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0; - RCC_ClocksTypeDef RCC_Clocks; - uint32_t sourceclock = 0; - - /* Check the I2S parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) */ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get the I2S clock source mask depending on the peripheral number */ - if(((uint32_t)SPIx) == SPI2_BASE) - { - /* The mask is relative to I2S2 */ - tmp = I2S2_CLOCK_SRC; - } - else - { - /* The mask is relative to I2S3 */ - tmp = I2S3_CLOCK_SRC; - } - - /* Check the I2S clock source configuration depending on the Device: - Only Connectivity line devices have the PLL3 VCO clock */ -#ifdef STM32F10X_CL - if((RCC->CFGR2 & tmp) != 0) - { - /* Get the configuration bits of RCC PLL3 multiplier */ - tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12); - - /* Get the value of the PLL3 multiplier */ - if((tmp > 5) && (tmp < 15)) - { - /* Multiplier is between 8 and 14 (value 15 is forbidden) */ - tmp += 2; - } - else - { - if (tmp == 15) - { - /* Multiplier is 20 */ - tmp = 20; - } - } - /* Get the PREDIV2 value */ - sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); - - /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */ - sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); - } - else - { - /* I2S Clock source is System clock: Get System Clock frequency */ - RCC_GetClocksFreq(&RCC_Clocks); - - /* Get the source clock value: based on System Clock value */ - sourceclock = RCC_Clocks.SYSCLK_Frequency; - } -#else /* STM32F10X_HD */ - /* I2S Clock source is System clock: Get System Clock frequency */ - RCC_GetClocksFreq(&RCC_Clocks); - - /* Get the source clock value: based on System Clock value */ - sourceclock = RCC_Clocks.SYSCLK_Frequency; -#endif /* STM32F10X_CL */ - - /* Compute the Real divider depending on the MCLK output state with a floating point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the floating point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg; -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= CR1_SPE_Set; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= CR1_SPE_Reset; - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; - } - else - { - /* Disable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; - } -} - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI/I2S interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI/I2S IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI/I2S interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI/I2S interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI/I2S DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - if (NewState != DISABLE) - { - /* Enable the selected SPI/I2S DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI/I2S DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param Data : Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Write in the DR register the data to be sent */ - SPIx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the data in the DR register */ - return SPIx->DR; -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= CR2_SSOE_Set; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= CR2_SSOE_Reset; - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * This parameter can be one of the following values: - * @arg SPI_DataSize_16b: Set data frame format to 16bit - * @arg SPI_DataSize_8b: Set data frame format to 8bit - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - /* Clear DFF bit */ - SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - /* Set new DFF bit value */ - SPIx->CR1 |= SPI_DataSize; -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= CR1_CRCNext_Set; -} - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= CR1_CRCEN_Set; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= CR1_CRCEN_Reset; - } -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Checks whether the specified SPI/I2S flag is set or not. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - /* Check the status of the specified SPI/I2S flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @note - * - OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * - UDR (UnderRun error) flag is cleared by a read operation to - * SPI_SR register (SPI_I2S_GetFlagStatus()). - * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * @arg I2S_IT_UDR: Underrun Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI/I2S IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI/I2S IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI/I2S interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR interrupt pending bit. - * @note - * - OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - * - UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_SR register (SPI_I2S_GetITStatus()). - * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - * the SPI). - * @retval None - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - SPIx->SR = (uint16_t)~itpos; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c deleted file mode 100644 index a3f16f15..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c +++ /dev/null @@ -1,1058 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_usart.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the USART firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_usart.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/** @defgroup USART_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Defines - * @{ - */ - -#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */ -#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */ - -#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ - -#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ -#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ -#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */ -#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */ -#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */ - -#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ -#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ - -#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ -#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */ -#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */ - -#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */ -#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ - -#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ -#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ - -#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ -#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ - -#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ -#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */ - -#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ -#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ -#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ -#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ -#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ - -/* USART OverSampling-8 Mask */ -#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */ -#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */ - -/* USART One Bit Sampling Mask */ -#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */ -#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */ - -/** - * @} - */ - -/** @defgroup USART_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if (USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else - { - if (USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified USART - * peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - uint32_t usartxbase = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - /* The hardware flow control is available only for USART1, USART2 and USART3 */ - if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear STOP[13:12] bits */ - tmpreg &= CR2_STOP_CLEAR_Mask; - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ - /* Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; - -/*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure the USART Word Length, Parity and mode ----------------------- */ - /* Set the M bits according to USART_WordLength value */ - /* Set PCE and PS bits according to USART_Parity value */ - /* Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - /* Write to USART CR1 */ - USARTx->CR1 = (uint16_t)tmpreg; - -/*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - /* Clear CTSE and RTSE bits */ - tmpreg &= CR3_CLEAR_Mask; - /* Configure the USART HFC -------------------------------------------------*/ - /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - /* Write to USART CR3 */ - USARTx->CR3 = (uint16_t)tmpreg; - -/*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate -------------------------------------------*/ - RCC_GetClocksFreq(&RCC_ClocksStatus); - if (usartxbase == USART1_BASE) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & CR1_OVER8_Set) != 0) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - /* Determine the fractional part */ - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - /* Implement the fractional part in the register */ - if ((USARTx->CR1 & CR1_OVER8_Set) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - /* Write to USART BRR */ - USARTx->BRR = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - tmpreg &= CR2_CLOCK_CLEAR_Mask; - /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= CR1_UE_Set; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= CR1_UE_Reset; - } -} - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - - /* Get the interrupt position */ - itpos = USART_IT & IT_Mask; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - usartxbase += 0x0C; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x10; - } - else /* The IT is in CR3 register */ - { - usartxbase += 0x14; - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Enables or disables the USART’s DMA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @note The DMA mode is not available for UART5 except in the STM32 - * High density value line devices(STM32F10X_HD_VL). - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint16_t)~USART_DMAReq; - } -} - -/** - * @brief Sets the address of the USART node. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS(USART_Address)); - - /* Clear the USART address */ - USARTx->CR2 &= CR2_Address_Mask; - /* Set the USART address node */ - USARTx->CR2 |= USART_Address; -} - -/** - * @brief Selects the USART WakeUp method. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= CR1_WAKE_Mask; - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @brief Determines if the USART is in mute mode or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - USARTx->CR1 |= CR1_RWU_Set; - } - else - { - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - USARTx->CR1 &= CR1_RWU_Reset; - } -} - -/** - * @brief Sets the USART LIN Break detection length. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= CR2_LBDL_Mask; - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USART’s LIN mode. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= CR2_LINEN_Set; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= CR2_LINEN_Reset; - } -} - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->DR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); -} - -/** - * @brief Transmits break characters. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @retval None - */ -void USART_SendBreak(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Send break characters */ - USARTx->CR1 |= CR1_SBK_Set; -} - -/** - * @brief Sets the specified USART guard time. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param USART_GuardTime: specifies the guard time. - * @note The guard time bits are not available for UART4 and UART5. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= GTPR_LSB_Mask; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Sets the system clock prescaler. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_Prescaler: specifies the prescaler clock. - * @note The function is used for IrDA mode with UART4 and UART5. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= GTPR_MSB_Mask; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @brief Enables or disables the USART’s Smart Card mode. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @note The Smart Card mode is not available for UART4 and UART5. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= CR3_SCEN_Set; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= CR3_SCEN_Reset; - } -} - -/** - * @brief Enables or disables NACK transmission. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @note The Smart Card mode is not available for UART4 and UART5. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= CR3_NACK_Set; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= CR3_NACK_Reset; - } -} - -/** - * @brief Enables or disables the USART’s Half Duplex communication. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= CR3_HDSEL_Set; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= CR3_HDSEL_Reset; - } -} - - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @note - * This function has to be called before calling USART_Init() - * function in order to have correct baudrate Divider value. - * @retval None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= CR1_OVER8_Set; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= CR1_OVER8_Reset; - } -} - -/** - * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - USARTx->CR3 |= CR3_ONEBITE_Set; - } - else - { - /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ - USARTx->CR3 &= CR3_ONEBITE_Reset; - } -} - -/** - * @brief Configures the USART's IrDA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= CR3_IRLP_Mask; - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USART's IrDA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= CR3_IREN_Set; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= CR3_IREN_Reset; - } -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - /* The CTS flag is not available for UART4 and UART5 */ - if (USART_FLAG == USART_FLAG_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DR register (USART_ReceiveData()). - * - RXNE flag can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * - TC flag can be also cleared by software sequence: a read operation to - * USART_SR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DR register (USART_SendData()). - * - TXE flag is cleared only by a write to the USART_DR register - * (USART_SendData()). - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - /* The CTS flag is not available for UART4 and UART5 */ - if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - USARTx->SR = (uint16_t)~USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE: OverRun Error interrupt - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - /* Get the interrupt position */ - itmask = USART_IT & IT_Mask; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->SR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTx's interrupt pending bits. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_SR register - * (USART_GetITStatus()) followed by a read operation to USART_DR register - * (USART_ReceiveData()). - * - RXNE pending bit can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * - TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by a write - * operation to USART_DR register (USART_SendData()). - * - TXE pending bit is cleared only by a write to the USART_DR register - * (USART_SendData()). - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->SR = (uint16_t)~itmask; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/stm32f10x_conf.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/stm32f10x_conf.h deleted file mode 100644 index d606cd37..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/STM32F10x_StdPeriph_Driver/stm32f10x_conf.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - ****************************************************************************** - * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h - * @author MCD Application Team - * @version V3.5.0 - * @date 08-April-2011 - * @brief Library configuration file. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CONF_H -#define __STM32F10x_CONF_H - -/* Includes ------------------------------------------------------------------*/ -/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ -/*#include "stm32f10x_adc.h"*/ -/*#include "stm32f10x_bkp.h"*/ -/*#include "stm32f10x_can.h"*/ -/*#include "stm32f10x_cec.h"*/ -/*#include "stm32f10x_crc.h"*/ -/*#include "stm32f10x_dac.h"*/ -/*#include "stm32f10x_dbgmcu.h"*/ -/*#include "stm32f10x_dma.h"*/ -/*#include "stm32f10x_exti.h"*/ -/*#include "stm32f10x_flash.h"*/ -/*#include "stm32f10x_fsmc.h"*/ -#include "stm32f10x_gpio.h" /* needed for configuring the SPI and UART pins */ -/*#include "stm32f10x_i2c.h"*/ -/*#include "stm32f10x_iwdg.h"*/ -/*#include "stm32f10x_pwr.h"*/ -#include "stm32f10x_rcc.h" /* needed for enabling the SPI and UART peripherals */ -/*#include "stm32f10x_rtc.h"*/ -/*#include "stm32f10x_sdio.h"*/ -#include "stm32f10x_spi.h" /* needed for low-level interfacing with SD-card */ -/*#include "stm32f10x_tim.h"*/ -#include "stm32f10x_usart.h" /* needed for UART logging during firmware updates from SD-card */ -/*#include "stm32f10x_wwdg.h"*/ -/*#include "misc.h"*/ /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Uncomment the line below to expanse the "assert_param" macro in the - Standard Peripheral Library drivers code */ -/* #define USE_FULL_ASSERT 1 */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT - -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function which reports - * the name of the source file and the source line number of the call - * that failed. If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#endif /* __STM32F10x_CONF_H */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/fatfs/ffconf.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/fatfs/ffconf.h deleted file mode 100644 index 02ad6ca3..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/lib/fatfs/ffconf.h +++ /dev/null @@ -1,192 +0,0 @@ -/*---------------------------------------------------------------------------/ -/ FatFs - FAT file system module configuration file R0.09b (C)ChaN, 2013 -/----------------------------------------------------------------------------/ -/ -/ CAUTION! Do not forget to make clean the project after any changes to -/ the configuration options. -/ -/----------------------------------------------------------------------------*/ -#ifndef _FFCONF -#define _FFCONF 82786 /* Revision ID */ - - -/*---------------------------------------------------------------------------/ -/ Functions and Buffer Configurations -/----------------------------------------------------------------------------*/ - -#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ -/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system -/ object instead of the sector buffer in the individual file object for file -/ data transfer. This reduces memory consumption 512 bytes each file object. */ - - -#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ -/* Setting _FS_READONLY to 1 defines read only configuration. This removes -/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, -/ f_truncate and useless f_getfree. */ - - -#define _FS_MINIMIZE 0 /* 0 to 3 */ -/* The _FS_MINIMIZE option defines minimization level to remove some functions. -/ -/ 0: Full function. -/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename -/ are removed. -/ 2: f_opendir and f_readdir are removed in addition to 1. -/ 3: f_lseek is removed in addition to 2. */ - - -#define _USE_STRFUNC 2 /* 0:Disable or 1-2:Enable */ -/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ - - -#define _USE_MKFS 0 /* 0:Disable or 1:Enable */ -/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ - - -#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ -/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ - - -#define _USE_LABEL 0 /* 0:Disable or 1:Enable */ -/* To enable volume label functions, set _USE_LAVEL to 1 */ - - -#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ -/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ - - -/*---------------------------------------------------------------------------/ -/ Locale and Namespace Configurations -/----------------------------------------------------------------------------*/ - -#define _CODE_PAGE 437 -/* The _CODE_PAGE specifies the OEM code page to be used on the target system. -/ Incorrect setting of the code page can cause a file open failure. -/ -/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) -/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) -/ 949 - Korean (DBCS, OEM, Windows) -/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) -/ 1250 - Central Europe (Windows) -/ 1251 - Cyrillic (Windows) -/ 1252 - Latin 1 (Windows) -/ 1253 - Greek (Windows) -/ 1254 - Turkish (Windows) -/ 1255 - Hebrew (Windows) -/ 1256 - Arabic (Windows) -/ 1257 - Baltic (Windows) -/ 1258 - Vietnam (OEM, Windows) -/ 437 - U.S. (OEM) -/ 720 - Arabic (OEM) -/ 737 - Greek (OEM) -/ 775 - Baltic (OEM) -/ 850 - Multilingual Latin 1 (OEM) -/ 858 - Multilingual Latin 1 + Euro (OEM) -/ 852 - Latin 2 (OEM) -/ 855 - Cyrillic (OEM) -/ 866 - Russian (OEM) -/ 857 - Turkish (OEM) -/ 862 - Hebrew (OEM) -/ 874 - Thai (OEM, Windows) -/ 1 - ASCII only (Valid for non LFN cfg.) -*/ - - -#define _USE_LFN 1 /* 0 to 3 */ -#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ -/* The _USE_LFN option switches the LFN support. -/ -/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. -/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. -/ 2: Enable LFN with dynamic working buffer on the STACK. -/ 3: Enable LFN with dynamic working buffer on the HEAP. -/ -/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, -/ Unicode handling functions ff_convert() and ff_wtoupper() must be added -/ to the project. When enable to use heap, memory control functions -/ ff_memalloc() and ff_memfree() must be added to the project. */ - - -#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ -/* To switch the character code set on FatFs API to Unicode, -/ enable LFN feature and set _LFN_UNICODE to 1. */ - - -#define _FS_RPATH 0 /* 0 to 2 */ -/* The _FS_RPATH option configures relative path feature. -/ -/ 0: Disable relative path feature and remove related functions. -/ 1: Enable relative path. f_chdrive() and f_chdir() are available. -/ 2: f_getcwd() is available in addition to 1. -/ -/ Note that output of the f_readdir fnction is affected by this option. */ - - -/*---------------------------------------------------------------------------/ -/ Physical Drive Configurations -/----------------------------------------------------------------------------*/ - -#define _VOLUMES 1 -/* Number of volumes (logical drives) to be used. */ - - -#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ -/* Maximum sector size to be handled. -/ Always set 512 for memory card and hard disk but a larger value may be -/ required for on-board flash memory, floppy disk and optical disk. -/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size -/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ - - -#define _MULTI_PARTITION 0 /* 0:Single partition, 1:Enable multiple partition */ -/* When set to 0, each volume is bound to the same physical drive number and -/ it can mount only first primaly partition. When it is set to 1, each volume -/ is tied to the partitions listed in VolToPart[]. */ - - -#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ -/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command -/ should be added to the disk_ioctl functio. */ - - - -/*---------------------------------------------------------------------------/ -/ System Configurations -/----------------------------------------------------------------------------*/ - -#define _WORD_ACCESS 0 /* 0 or 1 */ -/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS -/ option defines which access method is used to the word data on the FAT volume. -/ -/ 0: Byte-by-byte access. -/ 1: Word access. Do not choose this unless following condition is met. -/ -/ When the byte order on the memory is big-endian or address miss-aligned word -/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. -/ If it is not the case, the value can also be set to 1 to improve the -/ performance and code size. -*/ - - -/* A header file that defines sync object types on the O/S, such as -/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ - -#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ -#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ -#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ - -/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. -/ -/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. -/ 1: Enable reentrancy. Also user provided synchronization handlers, -/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj -/ function must be added to the project. */ - - -#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */ -/* To enable file lock control feature, set _FS_LOCK to 1 or greater. - The value defines how many files can be opened simultaneously. */ - - -#endif /* _FFCONFIG */ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/main.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/main.c deleted file mode 100644 index aa06a69a..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/main.c +++ /dev/null @@ -1,221 +0,0 @@ -/************************************************************************************//** -* \file Demo\ARMCM3_STM32_Olimex_STM32P103_GCC\Boot\main.c -* \brief Bootloader application source file. -* \ingroup Boot_ARMCM3_STM32_Olimex_STM32P103_GCC -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or -* modify it under the terms of the GNU General Public License as published by the Free -* Software Foundation, either version 3 of the License, or (at your option) any later -* version. -* -* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; -* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -* PURPOSE. See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along with OpenBLT. -* If not, see . -* -* A special exception to the GPL is included to allow you to distribute a combined work -* that includes OpenBLT without being obliged to provide the source code for any -* proprietary components. The exception text is included at the bottom of the license -* file . -* -* \endinternal -****************************************************************************************/ - -/**************************************************************************************** -* Include files -****************************************************************************************/ -#include "boot.h" /* bootloader generic header */ -#include "stm32f10x.h" /* microcontroller registers */ -#if (BOOT_FILE_LOGGING_ENABLE > 0) && (BOOT_COM_UART_ENABLE == 0) -#include "stm32f10x_conf.h" /* STM32 peripheral drivers */ -#endif - - -/**************************************************************************************** -* Function prototypes -****************************************************************************************/ -static void Init(void); - - -/************************************************************************************//** -** \brief This is the entry point for the bootloader application and is called -** by the reset interrupt vector after the C-startup routines executed. -** \return Program return code. -** -****************************************************************************************/ -int main(void) -{ - /* initialize the microcontroller */ - Init(); - /* initialize the bootloader */ - BootInit(); - - /* start the infinite program loop */ - while (1) - { - /* run the bootloader task */ - BootTask(); - } - - /* program should never get here */ - return 0; -} /*** end of main ***/ - - -/************************************************************************************//** -** \brief Initializes the microcontroller. -** \return none. -** -****************************************************************************************/ -static void Init(void) -{ - volatile blt_int32u StartUpCounter = 0, HSEStatus = 0; - blt_int32u pll_multiplier; -#if (BOOT_FILE_LOGGING_ENABLE > 0) && (BOOT_COM_UART_ENABLE == 0) - GPIO_InitTypeDef GPIO_InitStruct; - USART_InitTypeDef USART_InitStruct; -#endif - - /* reset the RCC clock configuration to the default reset state (for debug purpose) */ - /* set HSION bit */ - RCC->CR |= (blt_int32u)0x00000001; - /* reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ - RCC->CFGR &= (blt_int32u)0xF8FF0000; - /* reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (blt_int32u)0xFEF6FFFF; - /* reset HSEBYP bit */ - RCC->CR &= (blt_int32u)0xFFFBFFFF; - /* reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (blt_int32u)0xFF80FFFF; - /* disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; - /* enable HSE */ - RCC->CR |= ((blt_int32u)RCC_CR_HSEON); - /* wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != 1500)); - /* check if time out was reached */ - if ((RCC->CR & RCC_CR_HSERDY) == RESET) - { - /* cannot continue when HSE is not ready */ - ASSERT_RT(BLT_FALSE); - } - /* enable flash prefetch buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - /* reset flash wait state configuration to default 0 wait states */ - FLASH->ACR &= (blt_int32u)((blt_int32u)~FLASH_ACR_LATENCY); -#if (BOOT_CPU_SYSTEM_SPEED_KHZ > 48000) - /* configure 2 flash wait states */ - FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_2; -#elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000) - /* configure 1 flash wait states */ - FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_1; -#endif - /* HCLK = SYSCLK */ - RCC->CFGR |= (blt_int32u)RCC_CFGR_HPRE_DIV1; - /* PCLK2 = HCLK/2 */ - RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE2_DIV2; - /* PCLK1 = HCLK/2 */ - RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE1_DIV2; - /* reset PLL configuration */ - RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | \ - RCC_CFGR_PLLMULL)); - /* assert that the pll_multiplier is between 2 and 16 */ - ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) >= 2); - ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) <= 16); - /* calculate multiplier value */ - pll_multiplier = BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ; - /* convert to register value */ - pll_multiplier = (blt_int32u)((pll_multiplier - 2) << 18); - /* set the PLL multiplier and clock source */ - RCC->CFGR |= (blt_int32u)(RCC_CFGR_PLLSRC_HSE | pll_multiplier); - /* enable PLL */ - RCC->CR |= RCC_CR_PLLON; - /* wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - /* select PLL as system clock source */ - RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_SW)); - RCC->CFGR |= (blt_int32u)RCC_CFGR_SW_PLL; - /* wait till PLL is used as system clock source */ - while ((RCC->CFGR & (blt_int32u)RCC_CFGR_SWS) != (blt_int32u)0x08) - { - } -#if (BOOT_COM_CAN_ENABLE > 0) - /* enable clocks for CAN transmitter and receiver pins (GPIOB and AFIO) */ - RCC->APB2ENR |= (blt_int32u)(0x00000008 | 0x00000001); - /* configure CAN Rx (GPIOB8) as alternate function input pull-up */ - /* first reset the configuration */ - GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 0); - /* CNF8[1:0] = %10 and MODE8[1:0] = %00 */ - GPIOB->CRH |= (blt_int32u)((blt_int32u)0x8 << 0); - /* configure CAN Tx (GPIOB9) as alternate function push-pull */ - /* first reset the configuration */ - GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 4); - /* CNF9[1:0] = %10 and MODE9[1:0] = %11 */ - GPIOB->CRH |= (blt_int32u)((blt_int32u)0xb << 4); - /* remap CAN1 pins to PortB */ - AFIO->MAPR &= ~(blt_int32u)((blt_int32u)0x3 << 13); - AFIO->MAPR |= (blt_int32u)((blt_int32u)0x2 << 13); - /* enable clocks for CAN controller peripheral */ - RCC->APB1ENR |= (blt_int32u)0x02000000; -#endif -#if (BOOT_COM_UART_ENABLE > 0) - /* enable clock for USART2 peripheral */ - RCC->APB1ENR |= (blt_int32u)0x00020000; - /* enable clocks for USART2 transmitter and receiver pins (GPIOA and AFIO) */ - RCC->APB2ENR |= (blt_int32u)(0x00000004 | 0x00000001); - /* configure USART2 Tx (GPIOA2) as alternate function push-pull */ - /* first reset the configuration */ - GPIOA->CRL &= ~(blt_int32u)((blt_int32u)0xf << 8); - /* CNF2[1:0] = %10 and MODE2[1:0] = %11 */ - GPIOA->CRL |= (blt_int32u)((blt_int32u)0xb << 8); - /* configure USART2 Rx (GPIOA3) as alternate function input floating */ - /* first reset the configuration */ - GPIOA->CRL &= ~(blt_int32u)((blt_int32u)0xf << 12); - /* CNF2[1:0] = %01 and MODE2[1:0] = %00 */ - GPIOA->CRL |= (blt_int32u)((blt_int32u)0x4 << 12); -#elif (BOOT_FILE_LOGGING_ENABLE > 0) - /* enable UART peripheral clock */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); - /* enable GPIO peripheral clock for transmitter and receiver pins */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE); - /* configure USART Tx as alternate function push-pull */ - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2; - GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStruct); - /* Configure USART Rx as alternate function input floating */ - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_3; - GPIO_Init(GPIOA, &GPIO_InitStruct); - /* configure UART communcation parameters */ - USART_InitStruct.USART_BaudRate = BOOT_COM_UART_BAUDRATE; - USART_InitStruct.USART_WordLength = USART_WordLength_8b; - USART_InitStruct.USART_StopBits = USART_StopBits_1; - USART_InitStruct.USART_Parity = USART_Parity_No; - USART_InitStruct.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStruct.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(USART2, &USART_InitStruct); - /* enable UART */ - USART_Cmd(USART2, ENABLE); -#endif -} /*** end of Init ***/ - - -/*********************************** end of main.c *************************************/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/makefile b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/makefile deleted file mode 100644 index 582316a9..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/makefile +++ /dev/null @@ -1,196 +0,0 @@ -#**************************************************************************************** -#| Description: Makefile for STM32 using CodeSourcery GNU GCC compiler toolset -#| File Name: makefile -#| -#|--------------------------------------------------------------------------------------- -#| C O P Y R I G H T -#|--------------------------------------------------------------------------------------- -#| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved -#| -#|--------------------------------------------------------------------------------------- -#| L I C E N S E -#|--------------------------------------------------------------------------------------- -#| This file is part of OpenBTL. OpenBTL is free software: you can redistribute it and/or -#| modify it under the terms of the GNU General Public License as published by the Free -#| Software Foundation, either version 3 of the License, or (at your option) any later -#| version. -#| -#| OpenBTL is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; -#| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -#| PURPOSE. See the GNU General Public License for more details. -#| -#| You should have received a copy of the GNU General Public License along with OpenBTL. -#| If not, see . -#| -#**************************************************************************************** -SHELL = sh - -#|---------------------------------------------------------------------------------------| -#| Configure project name | -#|---------------------------------------------------------------------------------------| -PROJ_NAME=openblt_demoprog_nucleo_stm32f103rb - - -#|---------------------------------------------------------------------------------------| -#| Speficy project source files | -#|---------------------------------------------------------------------------------------| -PROJ_FILES= \ -blt_conf.h \ -hooks.c \ -main.c \ -./lib/fatfs/ffconf.h \ -./lib/fatfs/mmc.c \ -./lib/CMSIS/CM3/CoreSupport/core_cm3.c \ -./lib/CMSIS/CM3/CoreSupport/core_cm3.h \ -./lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h \ -./lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c \ -./lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h \ -./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h \ -./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h \ -./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h \ -./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h \ -./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c \ -./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c \ -./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c \ -./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c \ -./lib/STM32F10x_StdPeriph_Driver/stm32f10x_conf.h \ -../../../Source/third_party/fatfs/src/diskio.h \ -../../../Source/third_party/fatfs/src/ff.c \ -../../../Source/third_party/fatfs/src/ff.h \ -../../../Source/third_party/fatfs/src/integer.h \ -../../../Source/third_party/fatfs/src/option/unicode.c \ -../../../Source/boot.c \ -../../../Source/boot.h \ -../../../Source/com.c \ -../../../Source/com.h \ -../../../Source/xcp.c \ -../../../Source/xcp.h \ -../../../Source/backdoor.c \ -../../../Source/backdoor.h \ -../../../Source/cop.c \ -../../../Source/cop.h \ -../../../Source/file.c \ -../../../Source/file.h \ -../../../Source/assert.c \ -../../../Source/assert.h \ -../../../Source/plausibility.h \ -../../../Source/ARMCM3_STM32/types.h \ -../../../Source/ARMCM3_STM32/cpu.c \ -../../../Source/ARMCM3_STM32/cpu.h \ -../../../Source/ARMCM3_STM32/can.c \ -../../../Source/ARMCM3_STM32/can.h \ -../../../Source/ARMCM3_STM32/uart.c \ -../../../Source/ARMCM3_STM32/uart.h \ -../../../Source/ARMCM3_STM32/nvm.c \ -../../../Source/ARMCM3_STM32/nvm.h \ -../../../Source/ARMCM3_STM32/timer.c \ -../../../Source/ARMCM3_STM32/timer.h \ -../../../Source/ARMCM3_STM32/flash.c \ -../../../Source/ARMCM3_STM32/flash.h \ -../../../Source/ARMCM3_STM32/GCC/vectors.c \ -../../../Source/ARMCM3_STM32/GCC/cstart.c - - -#|---------------------------------------------------------------------------------------| -#| Compiler binaries | -#|---------------------------------------------------------------------------------------| -CC = arm-none-eabi-gcc -LN = arm-none-eabi-gcc -OC = arm-none-eabi-objcopy -OD = arm-none-eabi-objdump -AS = arm-none-eabi-as -SZ = arm-none-eabi-size - - -#|---------------------------------------------------------------------------------------| -#| Extract file names | -#|---------------------------------------------------------------------------------------| -PROJ_ASRCS = $(filter %.s,$(foreach file,$(PROJ_FILES),$(notdir $(file)))) -PROJ_CSRCS = $(filter %.c,$(foreach file,$(PROJ_FILES),$(notdir $(file)))) -PROJ_CHDRS = $(filter %.h,$(foreach file,$(PROJ_FILES),$(notdir $(file)))) -PROJ_CCMPL = $(patsubst %.c,%.cpl,$(PROJ_CSRCS)) -PROJ_ACMPL = $(patsubst %.s,%.cpl,$(PROJ_ASRCS)) - - -#|---------------------------------------------------------------------------------------| -#| Set important path variables | -#|---------------------------------------------------------------------------------------| -VPATH = $(foreach path,$(sort $(foreach file,$(PROJ_FILES),$(dir $(file)))) $(subst \,/,$(OBJ_PATH)),$(path) :) -OBJ_PATH = obj -BIN_PATH = bin -INC_PATH = $(patsubst %,-I%,$(sort $(foreach file,$(filter %.h,$(PROJ_FILES)),$(dir $(file))))) -INC_PATH += -I. -LIB_PATH = -L../../../Source/ARMCM3_STM32/GCC/ - - -#|---------------------------------------------------------------------------------------| -#| Options for compiler binaries | -#|---------------------------------------------------------------------------------------| -CFLAGS = -g -D inline= -mthumb -mcpu=cortex-m3 -O1 -T memory.x -CFLAGS += -D PACK_STRUCT_END=__attribute\(\(packed\)\) -Wno-main -CFLAGS += -D ALIGN_STRUCT_END=__attribute\(\(aligned\(4\)\)\) -CFLAGS += -ffunction-sections -fdata-sections $(INC_PATH) -D STM32F10X_MD -D GCC_ARMCM3 -CFLAGS += -D USE_STDPERIPH_DRIVER -D VECT_TAB_FLASH -Wa,-adhlns="$(OBJ_PATH)/$(subst .o,.lst,$@)" -LFLAGS = -nostartfiles -Xlinker -M -Xlinker -Map=$(BIN_PATH)/$(PROJ_NAME).map -LFLAGS += $(LIB_PATH) -Xlinker --gc-sections -OFLAGS = -O srec -ODFLAGS = -x -SZFLAGS = -B -d - - -#|---------------------------------------------------------------------------------------| -#| Specify library files | -#|---------------------------------------------------------------------------------------| -LIBS = - - -#|---------------------------------------------------------------------------------------| -#| Define targets | -#|---------------------------------------------------------------------------------------| -AOBJS = $(patsubst %.s,%.o,$(PROJ_ASRCS)) -COBJS = $(patsubst %.c,%.o,$(PROJ_CSRCS)) - - -#|---------------------------------------------------------------------------------------| -#| Make ALL | -#|---------------------------------------------------------------------------------------| -all : $(BIN_PATH)/$(PROJ_NAME).srec - - -$(BIN_PATH)/$(PROJ_NAME).srec : $(BIN_PATH)/$(PROJ_NAME).elf - @$(OC) $< $(OFLAGS) $@ - @$(OD) $(ODFLAGS) $< > $(BIN_PATH)/$(PROJ_NAME).map - @echo +++ Summary of memory consumption: - @$(SZ) $(SZFLAGS) $< - @echo +++ Build complete [$(notdir $@)] - -$(BIN_PATH)/$(PROJ_NAME).elf : $(AOBJS) $(COBJS) - @echo +++ Linking [$(notdir $@)] - @$(LN) $(CFLAGS) -o $@ $(patsubst %.o,$(OBJ_PATH)/%.o,$(^F)) $(LIBS) $(LFLAGS) - - -#|---------------------------------------------------------------------------------------| -#| Compile and assemble | -#|---------------------------------------------------------------------------------------| -$(AOBJS): %.o: %.s $(PROJ_CHDRS) - @echo +++ Assembling [$(notdir $<)] - @$(AS) $(AFLAGS) $< -o $(OBJ_PATH)/$(@F) - -$(COBJS): %.o: %.c $(PROJ_CHDRS) - @echo +++ Compiling [$(notdir $<)] - @$(CC) $(CFLAGS) -c $< -o $(OBJ_PATH)/$(@F) - - -#|---------------------------------------------------------------------------------------| -#| Make CLEAN | -#|---------------------------------------------------------------------------------------| -clean : - @echo +++ Cleaning build environment - @rm -f $(foreach file,$(AOBJS),$(OBJ_PATH)/$(file)) - @rm -f $(foreach file,$(COBJS),$(OBJ_PATH)/$(file)) - @rm -f $(patsubst %.o,%.lst,$(foreach file,$(COBJS),$(OBJ_PATH)/$(file))) - @rm -f $(BIN_PATH)/$(PROJ_NAME).elf $(BIN_PATH)/$(PROJ_NAME).map - @rm -f $(BIN_PATH)/$(PROJ_NAME).srec - @echo +++ Clean complete - - \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/assert.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/assert.lst deleted file mode 100644 index 8568af42..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/assert.lst +++ /dev/null @@ -1,150 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "assert.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.AssertFailure,"ax",%progbits - 19 .align 2 - 20 .global AssertFailure - 21 .thumb - 22 .thumb_func - 24 AssertFailure: - 25 .LFB0: - 26 .file 1 "../../../Source/assert.c" - 1:../../../Source/assert.c **** /************************************************************************************//** - 2:../../../Source/assert.c **** * \file Source\assert.c - 3:../../../Source/assert.c **** * \brief Bootloader assertion module source file. - 4:../../../Source/assert.c **** * \ingroup Core - 5:../../../Source/assert.c **** * \internal - 6:../../../Source/assert.c **** *---------------------------------------------------------------------------------------- - 7:../../../Source/assert.c **** * C O P Y R I G H T - 8:../../../Source/assert.c **** *---------------------------------------------------------------------------------------- - 9:../../../Source/assert.c **** * Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved - 10:../../../Source/assert.c **** * - 11:../../../Source/assert.c **** *---------------------------------------------------------------------------------------- - 12:../../../Source/assert.c **** * L I C E N S E - 13:../../../Source/assert.c **** *---------------------------------------------------------------------------------------- - 14:../../../Source/assert.c **** * This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or - 15:../../../Source/assert.c **** * modify it under the terms of the GNU General Public License as published by the Free - 16:../../../Source/assert.c **** * Software Foundation, either version 3 of the License, or (at your option) any later - 17:../../../Source/assert.c **** * version. - 18:../../../Source/assert.c **** * - 19:../../../Source/assert.c **** * OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; - 20:../../../Source/assert.c **** * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - 21:../../../Source/assert.c **** * PURPOSE. See the GNU General Public License for more details. - 22:../../../Source/assert.c **** * - 23:../../../Source/assert.c **** * You should have received a copy of the GNU General Public License along with OpenBLT. - 24:../../../Source/assert.c **** * If not, see . - 25:../../../Source/assert.c **** * - 26:../../../Source/assert.c **** * A special exception to the GPL is included to allow you to distribute a combined work - 27:../../../Source/assert.c **** * that includes OpenBLT without being obliged to provide the source code for any - 28:../../../Source/assert.c **** * proprietary components. The exception text is included at the bottom of the license - 29:../../../Source/assert.c **** * file . - 30:../../../Source/assert.c **** * - 31:../../../Source/assert.c **** * \endinternal - 32:../../../Source/assert.c **** ****************************************************************************************/ - 33:../../../Source/assert.c **** - 34:../../../Source/assert.c **** /**************************************************************************************** - 35:../../../Source/assert.c **** * Include files - 36:../../../Source/assert.c **** ****************************************************************************************/ - 37:../../../Source/assert.c **** #include "boot.h" /* bootloader generic header */ - 38:../../../Source/assert.c **** - 39:../../../Source/assert.c **** - 40:../../../Source/assert.c **** #ifndef NDEBUG - 41:../../../Source/assert.c **** /**************************************************************************************** - 42:../../../Source/assert.c **** * Local data declarations - 43:../../../Source/assert.c **** ****************************************************************************************/ - 44:../../../Source/assert.c **** /** \brief Holds the filename in which the assertion occurred. */ - 45:../../../Source/assert.c **** static volatile blt_char *assert_failure_file; - 46:../../../Source/assert.c **** /** \brief Holds the linenumber where the assertion occurred. */ - 47:../../../Source/assert.c **** static volatile blt_int32u assert_failure_line; - 48:../../../Source/assert.c **** - 49:../../../Source/assert.c **** - 50:../../../Source/assert.c **** /************************************************************************************//** - 51:../../../Source/assert.c **** ** \brief Called when a runtime assertion failed. It stores information about where - 52:../../../Source/assert.c **** ** the assertion occurred and halts the software program. - 53:../../../Source/assert.c **** ** \param file Name of the source file where the assertion occurred. - 54:../../../Source/assert.c **** ** \param line Linenumber in the source file where the assertion occurred. - 55:../../../Source/assert.c **** ** \return none - 56:../../../Source/assert.c **** ** - 57:../../../Source/assert.c **** ****************************************************************************************/ - 58:../../../Source/assert.c **** void AssertFailure(blt_char *file, blt_int32u line) - 59:../../../Source/assert.c **** { - 27 .loc 1 59 0 - 28 .cfi_startproc - 29 @ Volatile: function does not return. - 30 @ args = 0, pretend = 0, frame = 0 - 31 @ frame_needed = 0, uses_anonymous_args = 0 - 32 .LVL0: - 33 0000 08B5 push {r3, lr} - 34 .cfi_def_cfa_offset 8 - 35 .cfi_offset 3, -8 - 36 .cfi_offset 14, -4 - 60:../../../Source/assert.c **** /* store the file string and line number so that it can be read on a breakpoint*/ - 61:../../../Source/assert.c **** assert_failure_file = file; - 37 .loc 1 61 0 - 38 0002 034B ldr r3, .L4 - 39 0004 1860 str r0, [r3] - 62:../../../Source/assert.c **** assert_failure_line = line; - 40 .loc 1 62 0 - 41 0006 034B ldr r3, .L4+4 - 42 0008 1960 str r1, [r3] - 43 .LVL1: - 44 .L2: - 63:../../../Source/assert.c **** /* hang the software so that it requires a hard reset */ - 64:../../../Source/assert.c **** for(;;) - 65:../../../Source/assert.c **** { - 66:../../../Source/assert.c **** /* keep servicing the watchdog so that this one does not cause a reset */ - 67:../../../Source/assert.c **** CopService(); - 45 .loc 1 67 0 discriminator 1 - 46 000a FFF7FEFF bl CopService - 47 .LVL2: - 68:../../../Source/assert.c **** } - 48 .loc 1 68 0 discriminator 1 - 49 000e FCE7 b .L2 - 50 .L5: - 51 .align 2 - 52 .L4: - 53 0010 00000000 .word .LANCHOR0 - 54 0014 00000000 .word .LANCHOR1 - 55 .cfi_endproc - 56 .LFE0: - 58 .section .bss.assert_failure_file,"aw",%nobits - 59 .align 2 - 60 .set .LANCHOR0,. + 0 - 63 assert_failure_file: - 64 0000 00000000 .space 4 - 65 .section .bss.assert_failure_line,"aw",%nobits - 66 .align 2 - 67 .set .LANCHOR1,. + 0 - 70 assert_failure_line: - 71 0000 00000000 .space 4 - 72 .text - 73 .Letext0: - 74 .file 2 "../../../Source/ARMCM3_STM32/types.h" - 75 .file 3 "../../../Source/cop.h" -DEFINED SYMBOLS - *ABS*:00000000 assert.c -C:\Users\lwngim1\AppData\Local\Temp\ccr0wxrM.s:19 .text.AssertFailure:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccr0wxrM.s:24 .text.AssertFailure:00000000 AssertFailure -C:\Users\lwngim1\AppData\Local\Temp\ccr0wxrM.s:53 .text.AssertFailure:00000010 $d -C:\Users\lwngim1\AppData\Local\Temp\ccr0wxrM.s:59 .bss.assert_failure_file:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\ccr0wxrM.s:63 .bss.assert_failure_file:00000000 assert_failure_file -C:\Users\lwngim1\AppData\Local\Temp\ccr0wxrM.s:66 .bss.assert_failure_line:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\ccr0wxrM.s:70 .bss.assert_failure_line:00000000 assert_failure_line - .debug_frame:00000010 $d - -UNDEFINED SYMBOLS -CopService diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/backdoor.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/backdoor.lst deleted file mode 100644 index 6465cadd..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/backdoor.lst +++ /dev/null @@ -1,310 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "backdoor.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.BackDoorCheck,"ax",%progbits - 19 .align 2 - 20 .global BackDoorCheck - 21 .thumb - 22 .thumb_func - 24 BackDoorCheck: - 25 .LFB1: - 26 .file 1 "../../../Source/backdoor.c" - 1:../../../Source/backdoor.c **** /************************************************************************************//** - 2:../../../Source/backdoor.c **** * \file Source\backdoor.c - 3:../../../Source/backdoor.c **** * \brief Bootloader backdoor entry source file. - 4:../../../Source/backdoor.c **** * \ingroup Core - 5:../../../Source/backdoor.c **** * \internal - 6:../../../Source/backdoor.c **** *---------------------------------------------------------------------------------------- - 7:../../../Source/backdoor.c **** * C O P Y R I G H T - 8:../../../Source/backdoor.c **** *---------------------------------------------------------------------------------------- - 9:../../../Source/backdoor.c **** * Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved - 10:../../../Source/backdoor.c **** * - 11:../../../Source/backdoor.c **** *---------------------------------------------------------------------------------------- - 12:../../../Source/backdoor.c **** * L I C E N S E - 13:../../../Source/backdoor.c **** *---------------------------------------------------------------------------------------- - 14:../../../Source/backdoor.c **** * This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or - 15:../../../Source/backdoor.c **** * modify it under the terms of the GNU General Public License as published by the Free - 16:../../../Source/backdoor.c **** * Software Foundation, either version 3 of the License, or (at your option) any later - 17:../../../Source/backdoor.c **** * version. - 18:../../../Source/backdoor.c **** * - 19:../../../Source/backdoor.c **** * OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; - 20:../../../Source/backdoor.c **** * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - 21:../../../Source/backdoor.c **** * PURPOSE. See the GNU General Public License for more details. - 22:../../../Source/backdoor.c **** * - 23:../../../Source/backdoor.c **** * You should have received a copy of the GNU General Public License along with OpenBLT. - 24:../../../Source/backdoor.c **** * If not, see . - 25:../../../Source/backdoor.c **** * - 26:../../../Source/backdoor.c **** * A special exception to the GPL is included to allow you to distribute a combined work - 27:../../../Source/backdoor.c **** * that includes OpenBLT without being obliged to provide the source code for any - 28:../../../Source/backdoor.c **** * proprietary components. The exception text is included at the bottom of the license - 29:../../../Source/backdoor.c **** * file . - 30:../../../Source/backdoor.c **** * - 31:../../../Source/backdoor.c **** * \endinternal - 32:../../../Source/backdoor.c **** ****************************************************************************************/ - 33:../../../Source/backdoor.c **** - 34:../../../Source/backdoor.c **** /**************************************************************************************** - 35:../../../Source/backdoor.c **** * Include files - 36:../../../Source/backdoor.c **** ****************************************************************************************/ - 37:../../../Source/backdoor.c **** #include "boot.h" /* bootloader generic header */ - 38:../../../Source/backdoor.c **** - 39:../../../Source/backdoor.c **** - 40:../../../Source/backdoor.c **** /**************************************************************************************** - 41:../../../Source/backdoor.c **** * Macro definitions - 42:../../../Source/backdoor.c **** ****************************************************************************************/ - 43:../../../Source/backdoor.c **** #if (BOOT_BACKDOOR_HOOKS_ENABLE == 0) - 44:../../../Source/backdoor.c **** #ifndef BACKDOOR_ENTRY_TIMEOUT_MS - 45:../../../Source/backdoor.c **** /** \brief Sets the time in milliseconds that the backdoor is open, but allow an - 46:../../../Source/backdoor.c **** * override for this time. note that this time should be at least 2.5 times - 47:../../../Source/backdoor.c **** * as long as the time that is configured in Microboot's XCP settings for the - 48:../../../Source/backdoor.c **** * connect command response. This is the last entry on XCP Timeouts tab. By - 49:../../../Source/backdoor.c **** * default the connect command response is configured as 20ms by Microboot, - 50:../../../Source/backdoor.c **** * except for TCP/IP where it is 300ms due to accomodate for worldwide - 51:../../../Source/backdoor.c **** * network latency. For CAN this was also adjusted to 500ms so that Microboot - 52:../../../Source/backdoor.c **** * can wait for the bootloader to initialize. Otherwise errorframes can be - 53:../../../Source/backdoor.c **** * generated on the CAN bus. - 54:../../../Source/backdoor.c **** */ - 55:../../../Source/backdoor.c **** #if (BOOT_COM_NET_ENABLE == 1) - 56:../../../Source/backdoor.c **** #define BACKDOOR_ENTRY_TIMEOUT_MS (750) - 57:../../../Source/backdoor.c **** #elif (BOOT_COM_CAN_ENABLE == 1) - 58:../../../Source/backdoor.c **** #define BACKDOOR_ENTRY_TIMEOUT_MS (500) - 59:../../../Source/backdoor.c **** #else - 60:../../../Source/backdoor.c **** #define BACKDOOR_ENTRY_TIMEOUT_MS (50) - 61:../../../Source/backdoor.c **** #endif - 62:../../../Source/backdoor.c **** #endif - 63:../../../Source/backdoor.c **** #endif - 64:../../../Source/backdoor.c **** - 65:../../../Source/backdoor.c **** /**************************************************************************************** - 66:../../../Source/backdoor.c **** * Hook functions - 67:../../../Source/backdoor.c **** ****************************************************************************************/ - 68:../../../Source/backdoor.c **** #if (BOOT_BACKDOOR_HOOKS_ENABLE > 0) - 69:../../../Source/backdoor.c **** extern void BackDoorInitHook(void); - 70:../../../Source/backdoor.c **** extern blt_bool BackDoorEntryHook(void); - 71:../../../Source/backdoor.c **** #endif - 72:../../../Source/backdoor.c **** - 73:../../../Source/backdoor.c **** - 74:../../../Source/backdoor.c **** /**************************************************************************************** - 75:../../../Source/backdoor.c **** * Local data declarations - 76:../../../Source/backdoor.c **** ****************************************************************************************/ - 77:../../../Source/backdoor.c **** #if (BOOT_BACKDOOR_HOOKS_ENABLE == 0) - 78:../../../Source/backdoor.c **** /** \brief To determine if the backdoor is open or closed. */ - 79:../../../Source/backdoor.c **** static blt_bool backdoorOpen; - 80:../../../Source/backdoor.c **** /** \brief To determine how long the backdoor has been open in milliseconds. */ - 81:../../../Source/backdoor.c **** static blt_int32u backdoorOpenTime; - 82:../../../Source/backdoor.c **** #endif - 83:../../../Source/backdoor.c **** - 84:../../../Source/backdoor.c **** - 85:../../../Source/backdoor.c **** /************************************************************************************//** - 86:../../../Source/backdoor.c **** ** \brief Initializes the backdoor entry option. - 87:../../../Source/backdoor.c **** ** \return none - 88:../../../Source/backdoor.c **** ** - 89:../../../Source/backdoor.c **** ****************************************************************************************/ - 90:../../../Source/backdoor.c **** void BackDoorInit(void) - 91:../../../Source/backdoor.c **** { - 92:../../../Source/backdoor.c **** #if (BOOT_BACKDOOR_HOOKS_ENABLE > 0) - 93:../../../Source/backdoor.c **** /* initialize application's backdoor functionality */ - 94:../../../Source/backdoor.c **** BackDoorInitHook(); - 95:../../../Source/backdoor.c **** - 96:../../../Source/backdoor.c **** /* attempt to start the user program when no backdoor entry is requested */ - 97:../../../Source/backdoor.c **** if (BackDoorEntryHook() == BLT_FALSE) - 98:../../../Source/backdoor.c **** { - 99:../../../Source/backdoor.c **** /* this function does not return if a valid user program is present */ - 100:../../../Source/backdoor.c **** CpuStartUserProgram(); - 101:../../../Source/backdoor.c **** } - 102:../../../Source/backdoor.c **** #if (BOOT_FILE_SYS_ENABLE > 0) - 103:../../../Source/backdoor.c **** else - 104:../../../Source/backdoor.c **** { - 105:../../../Source/backdoor.c **** /* the backdoor is open so we should check if a update from locally attached storage - 106:../../../Source/backdoor.c **** * is requested and, if so, start it. - 107:../../../Source/backdoor.c **** */ - 108:../../../Source/backdoor.c **** FileHandleFirmwareUpdateRequest(); - 109:../../../Source/backdoor.c **** } - 110:../../../Source/backdoor.c **** #endif - 111:../../../Source/backdoor.c **** #else - 112:../../../Source/backdoor.c **** /* open the backdoor after a reset */ - 113:../../../Source/backdoor.c **** backdoorOpen = BLT_TRUE; - 114:../../../Source/backdoor.c **** backdoorOpenTime = TimerGet(); - 115:../../../Source/backdoor.c **** #endif - 116:../../../Source/backdoor.c **** /* perform the first check that open/closes the backdoor */ - 117:../../../Source/backdoor.c **** BackDoorCheck(); - 118:../../../Source/backdoor.c **** } /*** end of BackDoorInit ***/ - 119:../../../Source/backdoor.c **** - 120:../../../Source/backdoor.c **** - 121:../../../Source/backdoor.c **** /************************************************************************************//** - 122:../../../Source/backdoor.c **** ** \brief The default backdoor entry feature keeps the bootloader active for a - 123:../../../Source/backdoor.c **** ** predetermined time after reset, allowing the host application to - 124:../../../Source/backdoor.c **** ** establish a connection and start a programming sequence. This function - 125:../../../Source/backdoor.c **** ** controls the opening/closing of the backdoor. - 126:../../../Source/backdoor.c **** ** \return none - 127:../../../Source/backdoor.c **** ** - 128:../../../Source/backdoor.c **** ****************************************************************************************/ - 129:../../../Source/backdoor.c **** void BackDoorCheck(void) - 130:../../../Source/backdoor.c **** { - 27 .loc 1 130 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 0000 08B5 push {r3, lr} - 32 .cfi_def_cfa_offset 8 - 33 .cfi_offset 3, -8 - 34 .cfi_offset 14, -4 - 131:../../../Source/backdoor.c **** #if (BOOT_BACKDOOR_HOOKS_ENABLE == 0) - 132:../../../Source/backdoor.c **** #if (BOOT_COM_ENABLE > 0) - 133:../../../Source/backdoor.c **** /* check if a connection with the host was already established. in this case the - 134:../../../Source/backdoor.c **** * backdoor stays open anyway, so no need to check if it needs to be closed. - 135:../../../Source/backdoor.c **** */ - 136:../../../Source/backdoor.c **** if (ComIsConnected() == BLT_TRUE) - 35 .loc 1 136 0 - 36 0002 FFF7FEFF bl ComIsConnected - 37 .LVL0: - 38 0006 0128 cmp r0, #1 - 39 0008 0FD0 beq .L1 - 137:../../../Source/backdoor.c **** { - 138:../../../Source/backdoor.c **** return; - 139:../../../Source/backdoor.c **** } - 140:../../../Source/backdoor.c **** #endif - 141:../../../Source/backdoor.c **** #if (BOOT_FILE_SYS_ENABLE > 0) - 142:../../../Source/backdoor.c **** /* check if the file module is busy, indicating that a firmware update through the - 143:../../../Source/backdoor.c **** * locally attached storage is in progress. in this case the backdoor stays open - 144:../../../Source/backdoor.c **** * anyway, so no need to check if it needs to be closed. - 145:../../../Source/backdoor.c **** */ - 146:../../../Source/backdoor.c **** if (FileIsIdle() == BLT_FALSE) - 147:../../../Source/backdoor.c **** { - 148:../../../Source/backdoor.c **** return; - 149:../../../Source/backdoor.c **** } - 150:../../../Source/backdoor.c **** #endif - 151:../../../Source/backdoor.c **** - 152:../../../Source/backdoor.c **** /* when the backdoor is still open, check if it's time to close it */ - 153:../../../Source/backdoor.c **** if (backdoorOpen == BLT_TRUE) - 40 .loc 1 153 0 - 41 000a 084B ldr r3, .L4 - 42 000c 1B78 ldrb r3, [r3] @ zero_extendqisi2 - 43 000e 012B cmp r3, #1 - 44 0010 0BD1 bne .L1 - 154:../../../Source/backdoor.c **** { - 155:../../../Source/backdoor.c **** /* check if the backdoor entry time window elapsed */ - 156:../../../Source/backdoor.c **** if (TimerGet() >= (BACKDOOR_ENTRY_TIMEOUT_MS + backdoorOpenTime)) - 45 .loc 1 156 0 - 46 0012 FFF7FEFF bl TimerGet - 47 .LVL1: - 48 0016 064B ldr r3, .L4+4 - 49 0018 1B68 ldr r3, [r3] - 50 001a 3233 adds r3, r3, #50 - 51 001c 9842 cmp r0, r3 - 52 001e 04D3 bcc .L1 - 157:../../../Source/backdoor.c **** { - 158:../../../Source/backdoor.c **** /* close the backdoor */ - 159:../../../Source/backdoor.c **** backdoorOpen = BLT_FALSE; - 53 .loc 1 159 0 - 54 0020 0022 movs r2, #0 - 55 0022 024B ldr r3, .L4 - 56 0024 1A70 strb r2, [r3] - 160:../../../Source/backdoor.c **** #if (BOOT_FILE_SYS_ENABLE > 0) - 161:../../../Source/backdoor.c **** /* during the timed backdoor no remote update request was detected. now do one - 162:../../../Source/backdoor.c **** * last check to see if a firmware update from locally attached storage is - 163:../../../Source/backdoor.c **** * pending. - 164:../../../Source/backdoor.c **** */ - 165:../../../Source/backdoor.c **** if (FileHandleFirmwareUpdateRequest() == BLT_FALSE) - 166:../../../Source/backdoor.c **** #endif - 167:../../../Source/backdoor.c **** { - 168:../../../Source/backdoor.c **** /* no firmware update requests detected, so attempt to start the user program. - 169:../../../Source/backdoor.c **** * this function does not return if a valid user program is present. - 170:../../../Source/backdoor.c **** */ - 171:../../../Source/backdoor.c **** CpuStartUserProgram(); - 57 .loc 1 171 0 - 58 0026 FFF7FEFF bl CpuStartUserProgram - 59 .LVL2: - 60 .L1: - 61 002a 08BD pop {r3, pc} - 62 .L5: - 63 .align 2 - 64 .L4: - 65 002c 00000000 .word .LANCHOR0 - 66 0030 00000000 .word .LANCHOR1 - 67 .cfi_endproc - 68 .LFE1: - 70 .section .text.BackDoorInit,"ax",%progbits - 71 .align 2 - 72 .global BackDoorInit - 73 .thumb - 74 .thumb_func - 76 BackDoorInit: - 77 .LFB0: - 91:../../../Source/backdoor.c **** #if (BOOT_BACKDOOR_HOOKS_ENABLE > 0) - 78 .loc 1 91 0 - 79 .cfi_startproc - 80 @ args = 0, pretend = 0, frame = 0 - 81 @ frame_needed = 0, uses_anonymous_args = 0 - 82 0000 08B5 push {r3, lr} - 83 .cfi_def_cfa_offset 8 - 84 .cfi_offset 3, -8 - 85 .cfi_offset 14, -4 - 113:../../../Source/backdoor.c **** backdoorOpenTime = TimerGet(); - 86 .loc 1 113 0 - 87 0002 0122 movs r2, #1 - 88 0004 044B ldr r3, .L8 - 89 0006 1A70 strb r2, [r3] - 114:../../../Source/backdoor.c **** #endif - 90 .loc 1 114 0 - 91 0008 FFF7FEFF bl TimerGet - 92 .LVL3: - 93 000c 034B ldr r3, .L8+4 - 94 000e 1860 str r0, [r3] - 117:../../../Source/backdoor.c **** } /*** end of BackDoorInit ***/ - 95 .loc 1 117 0 - 96 0010 FFF7FEFF bl BackDoorCheck - 97 .LVL4: - 98 0014 08BD pop {r3, pc} - 99 .L9: - 100 0016 00BF .align 2 - 101 .L8: - 102 0018 00000000 .word .LANCHOR0 - 103 001c 00000000 .word .LANCHOR1 - 104 .cfi_endproc - 105 .LFE0: - 107 .section .bss.backdoorOpen,"aw",%nobits - 108 .set .LANCHOR0,. + 0 - 111 backdoorOpen: - 112 0000 00 .space 1 - 113 .section .bss.backdoorOpenTime,"aw",%nobits - 114 .align 2 - 115 .set .LANCHOR1,. + 0 - 118 backdoorOpenTime: - 119 0000 00000000 .space 4 - 120 .text - 121 .Letext0: - 122 .file 2 "../../../Source/ARMCM3_STM32/types.h" - 123 .file 3 "../../../Source/com.h" - 124 .file 4 "../../../Source/ARMCM3_STM32/timer.h" - 125 .file 5 "../../../Source/ARMCM3_STM32/cpu.h" -DEFINED SYMBOLS - *ABS*:00000000 backdoor.c -C:\Users\lwngim1\AppData\Local\Temp\ccV5nJcl.s:19 .text.BackDoorCheck:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccV5nJcl.s:24 .text.BackDoorCheck:00000000 BackDoorCheck -C:\Users\lwngim1\AppData\Local\Temp\ccV5nJcl.s:65 .text.BackDoorCheck:0000002c $d -C:\Users\lwngim1\AppData\Local\Temp\ccV5nJcl.s:71 .text.BackDoorInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccV5nJcl.s:76 .text.BackDoorInit:00000000 BackDoorInit -C:\Users\lwngim1\AppData\Local\Temp\ccV5nJcl.s:102 .text.BackDoorInit:00000018 $d -C:\Users\lwngim1\AppData\Local\Temp\ccV5nJcl.s:111 .bss.backdoorOpen:00000000 backdoorOpen -C:\Users\lwngim1\AppData\Local\Temp\ccV5nJcl.s:112 .bss.backdoorOpen:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\ccV5nJcl.s:114 .bss.backdoorOpenTime:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\ccV5nJcl.s:118 .bss.backdoorOpenTime:00000000 backdoorOpenTime - .debug_frame:00000010 $d - -UNDEFINED SYMBOLS -ComIsConnected -TimerGet -CpuStartUserProgram diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/boot.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/boot.lst deleted file mode 100644 index 7823d4be..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/boot.lst +++ /dev/null @@ -1,192 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "boot.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.BootInit,"ax",%progbits - 19 .align 2 - 20 .global BootInit - 21 .thumb - 22 .thumb_func - 24 BootInit: - 25 .LFB0: - 26 .file 1 "../../../Source/boot.c" - 1:../../../Source/boot.c **** /************************************************************************************//** - 2:../../../Source/boot.c **** * \file Source\boot.c - 3:../../../Source/boot.c **** * \brief Bootloader core module source file. - 4:../../../Source/boot.c **** * \ingroup Core - 5:../../../Source/boot.c **** * \internal - 6:../../../Source/boot.c **** *---------------------------------------------------------------------------------------- - 7:../../../Source/boot.c **** * C O P Y R I G H T - 8:../../../Source/boot.c **** *---------------------------------------------------------------------------------------- - 9:../../../Source/boot.c **** * Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved - 10:../../../Source/boot.c **** * - 11:../../../Source/boot.c **** *---------------------------------------------------------------------------------------- - 12:../../../Source/boot.c **** * L I C E N S E - 13:../../../Source/boot.c **** *---------------------------------------------------------------------------------------- - 14:../../../Source/boot.c **** * This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or - 15:../../../Source/boot.c **** * modify it under the terms of the GNU General Public License as published by the Free - 16:../../../Source/boot.c **** * Software Foundation, either version 3 of the License, or (at your option) any later - 17:../../../Source/boot.c **** * version. - 18:../../../Source/boot.c **** * - 19:../../../Source/boot.c **** * OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; - 20:../../../Source/boot.c **** * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - 21:../../../Source/boot.c **** * PURPOSE. See the GNU General Public License for more details. - 22:../../../Source/boot.c **** * - 23:../../../Source/boot.c **** * You should have received a copy of the GNU General Public License along with OpenBLT. - 24:../../../Source/boot.c **** * If not, see . - 25:../../../Source/boot.c **** * - 26:../../../Source/boot.c **** * A special exception to the GPL is included to allow you to distribute a combined work - 27:../../../Source/boot.c **** * that includes OpenBLT without being obliged to provide the source code for any - 28:../../../Source/boot.c **** * proprietary components. The exception text is included at the bottom of the license - 29:../../../Source/boot.c **** * file . - 30:../../../Source/boot.c **** * - 31:../../../Source/boot.c **** * \endinternal - 32:../../../Source/boot.c **** ****************************************************************************************/ - 33:../../../Source/boot.c **** - 34:../../../Source/boot.c **** /**************************************************************************************** - 35:../../../Source/boot.c **** * Include files - 36:../../../Source/boot.c **** ****************************************************************************************/ - 37:../../../Source/boot.c **** #include "boot.h" /* bootloader generic header */ - 38:../../../Source/boot.c **** - 39:../../../Source/boot.c **** - 40:../../../Source/boot.c **** /************************************************************************************//** - 41:../../../Source/boot.c **** ** \brief Initializes the bootloader core. - 42:../../../Source/boot.c **** ** \return none - 43:../../../Source/boot.c **** ** - 44:../../../Source/boot.c **** ****************************************************************************************/ - 45:../../../Source/boot.c **** void BootInit(void) - 46:../../../Source/boot.c **** { - 27 .loc 1 46 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 0000 08B5 push {r3, lr} - 32 .cfi_def_cfa_offset 8 - 33 .cfi_offset 3, -8 - 34 .cfi_offset 14, -4 - 47:../../../Source/boot.c **** /* initialize the watchdog */ - 48:../../../Source/boot.c **** CopInit(); - 35 .loc 1 48 0 - 36 0002 FFF7FEFF bl CopInit - 37 .LVL0: - 49:../../../Source/boot.c **** /* initialize the millisecond timer */ - 50:../../../Source/boot.c **** TimerInit(); - 38 .loc 1 50 0 - 39 0006 FFF7FEFF bl TimerInit - 40 .LVL1: - 51:../../../Source/boot.c **** /* initialize the non-volatile memory driver */ - 52:../../../Source/boot.c **** NvmInit(); - 41 .loc 1 52 0 - 42 000a FFF7FEFF bl NvmInit - 43 .LVL2: - 53:../../../Source/boot.c **** #if (BOOT_FILE_SYS_ENABLE > 0) - 54:../../../Source/boot.c **** /* initialize the file system module */ - 55:../../../Source/boot.c **** FileInit(); - 56:../../../Source/boot.c **** #endif - 57:../../../Source/boot.c **** #if (BOOT_COM_ENABLE > 0) - 58:../../../Source/boot.c **** /* initialize the communication module */ - 59:../../../Source/boot.c **** ComInit(); - 44 .loc 1 59 0 - 45 000e FFF7FEFF bl ComInit - 46 .LVL3: - 60:../../../Source/boot.c **** #endif - 61:../../../Source/boot.c **** /* initialize the backdoor entry */ - 62:../../../Source/boot.c **** BackDoorInit(); - 47 .loc 1 62 0 - 48 0012 FFF7FEFF bl BackDoorInit - 49 .LVL4: - 50 0016 08BD pop {r3, pc} - 51 .cfi_endproc - 52 .LFE0: - 54 .section .text.BootTask,"ax",%progbits - 55 .align 2 - 56 .global BootTask - 57 .thumb - 58 .thumb_func - 60 BootTask: - 61 .LFB1: - 63:../../../Source/boot.c **** } /*** end of BootInit ***/ - 64:../../../Source/boot.c **** - 65:../../../Source/boot.c **** - 66:../../../Source/boot.c **** /************************************************************************************//** - 67:../../../Source/boot.c **** ** \brief Task function of the bootloader core that drives the program. - 68:../../../Source/boot.c **** ** \return none - 69:../../../Source/boot.c **** ** - 70:../../../Source/boot.c **** ****************************************************************************************/ - 71:../../../Source/boot.c **** void BootTask(void) - 72:../../../Source/boot.c **** { - 62 .loc 1 72 0 - 63 .cfi_startproc - 64 @ args = 0, pretend = 0, frame = 0 - 65 @ frame_needed = 0, uses_anonymous_args = 0 - 66 0000 08B5 push {r3, lr} - 67 .cfi_def_cfa_offset 8 - 68 .cfi_offset 3, -8 - 69 .cfi_offset 14, -4 - 73:../../../Source/boot.c **** /* service the watchdog */ - 74:../../../Source/boot.c **** CopService(); - 70 .loc 1 74 0 - 71 0002 FFF7FEFF bl CopService - 72 .LVL5: - 75:../../../Source/boot.c **** /* update the millisecond timer */ - 76:../../../Source/boot.c **** TimerUpdate(); - 73 .loc 1 76 0 - 74 0006 FFF7FEFF bl TimerUpdate - 75 .LVL6: - 77:../../../Source/boot.c **** #if (BOOT_FILE_SYS_ENABLE > 0) - 78:../../../Source/boot.c **** /* call worker task for updating firmware from locally attached file storage */ - 79:../../../Source/boot.c **** FileTask(); - 80:../../../Source/boot.c **** #endif /* BOOT_FILE_SYS_ENABLE > 0 */ - 81:../../../Source/boot.c **** #if (BOOT_COM_ENABLE > 0) - 82:../../../Source/boot.c **** /* process possibly pending communication data */ - 83:../../../Source/boot.c **** ComTask(); - 76 .loc 1 83 0 - 77 000a FFF7FEFF bl ComTask - 78 .LVL7: - 84:../../../Source/boot.c **** #endif - 85:../../../Source/boot.c **** /* control the backdoor */ - 86:../../../Source/boot.c **** BackDoorCheck(); - 79 .loc 1 86 0 - 80 000e FFF7FEFF bl BackDoorCheck - 81 .LVL8: - 82 0012 08BD pop {r3, pc} - 83 .cfi_endproc - 84 .LFE1: - 86 .text - 87 .Letext0: - 88 .file 2 "../../../Source/cop.h" - 89 .file 3 "../../../Source/ARMCM3_STM32/timer.h" - 90 .file 4 "../../../Source/ARMCM3_STM32/nvm.h" - 91 .file 5 "../../../Source/com.h" - 92 .file 6 "../../../Source/backdoor.h" -DEFINED SYMBOLS - *ABS*:00000000 boot.c -C:\Users\lwngim1\AppData\Local\Temp\ccGYAvWS.s:19 .text.BootInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccGYAvWS.s:24 .text.BootInit:00000000 BootInit -C:\Users\lwngim1\AppData\Local\Temp\ccGYAvWS.s:55 .text.BootTask:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccGYAvWS.s:60 .text.BootTask:00000000 BootTask - .debug_frame:00000010 $d - -UNDEFINED SYMBOLS -CopInit -TimerInit -NvmInit -ComInit -BackDoorInit -CopService -TimerUpdate -ComTask -BackDoorCheck diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/can.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/can.lst deleted file mode 100644 index d38ae116..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/can.lst +++ /dev/null @@ -1,22 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "can.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .Letext0: -DEFINED SYMBOLS - *ABS*:00000000 can.c - -NO UNDEFINED SYMBOLS diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/com.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/com.lst deleted file mode 100644 index 6ff38060..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/com.lst +++ /dev/null @@ -1,595 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "com.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.ComInit,"ax",%progbits - 19 .align 2 - 20 .global ComInit - 21 .thumb - 22 .thumb_func - 24 ComInit: - 25 .LFB0: - 26 .file 1 "../../../Source/com.c" - 1:../../../Source/com.c **** /************************************************************************************//** - 2:../../../Source/com.c **** * \file Source\com.c - 3:../../../Source/com.c **** * \brief Bootloader communication interface source file. - 4:../../../Source/com.c **** * \ingroup Core - 5:../../../Source/com.c **** * \internal - 6:../../../Source/com.c **** *---------------------------------------------------------------------------------------- - 7:../../../Source/com.c **** * C O P Y R I G H T - 8:../../../Source/com.c **** *---------------------------------------------------------------------------------------- - 9:../../../Source/com.c **** * Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved - 10:../../../Source/com.c **** * - 11:../../../Source/com.c **** *---------------------------------------------------------------------------------------- - 12:../../../Source/com.c **** * L I C E N S E - 13:../../../Source/com.c **** *---------------------------------------------------------------------------------------- - 14:../../../Source/com.c **** * This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or - 15:../../../Source/com.c **** * modify it under the terms of the GNU General Public License as published by the Free - 16:../../../Source/com.c **** * Software Foundation, either version 3 of the License, or (at your option) any later - 17:../../../Source/com.c **** * version. - 18:../../../Source/com.c **** * - 19:../../../Source/com.c **** * OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; - 20:../../../Source/com.c **** * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - 21:../../../Source/com.c **** * PURPOSE. See the GNU General Public License for more details. - 22:../../../Source/com.c **** * - 23:../../../Source/com.c **** * You should have received a copy of the GNU General Public License along with OpenBLT. - 24:../../../Source/com.c **** * If not, see . - 25:../../../Source/com.c **** * - 26:../../../Source/com.c **** * A special exception to the GPL is included to allow you to distribute a combined work - 27:../../../Source/com.c **** * that includes OpenBLT without being obliged to provide the source code for any - 28:../../../Source/com.c **** * proprietary components. The exception text is included at the bottom of the license - 29:../../../Source/com.c **** * file . - 30:../../../Source/com.c **** * - 31:../../../Source/com.c **** * \endinternal - 32:../../../Source/com.c **** ****************************************************************************************/ - 33:../../../Source/com.c **** - 34:../../../Source/com.c **** /**************************************************************************************** - 35:../../../Source/com.c **** * Include files - 36:../../../Source/com.c **** ****************************************************************************************/ - 37:../../../Source/com.c **** #include "boot.h" /* bootloader generic header */ - 38:../../../Source/com.c **** #if (BOOT_COM_CAN_ENABLE > 0) - 39:../../../Source/com.c **** #include "can.h" /* can driver module */ - 40:../../../Source/com.c **** #endif - 41:../../../Source/com.c **** #if (BOOT_COM_UART_ENABLE > 0) - 42:../../../Source/com.c **** #include "uart.h" /* uart driver module */ - 43:../../../Source/com.c **** #endif - 44:../../../Source/com.c **** #if (BOOT_COM_USB_ENABLE > 0) - 45:../../../Source/com.c **** #include "usb.h" /* usb driver module */ - 46:../../../Source/com.c **** #endif - 47:../../../Source/com.c **** #if (BOOT_COM_NET_ENABLE > 0) - 48:../../../Source/com.c **** #include "net.h" /* tcp/ip driver module */ - 49:../../../Source/com.c **** #endif - 50:../../../Source/com.c **** - 51:../../../Source/com.c **** - 52:../../../Source/com.c **** #if (BOOT_COM_ENABLE > 0) - 53:../../../Source/com.c **** /**************************************************************************************** - 54:../../../Source/com.c **** * Local data declarations - 55:../../../Source/com.c **** ****************************************************************************************/ - 56:../../../Source/com.c **** /** \brief Holds the communication interface of the currently active interface. */ - 57:../../../Source/com.c **** static tComInterfaceId comActiveInterface = COM_IF_OTHER; - 58:../../../Source/com.c **** - 59:../../../Source/com.c **** - 60:../../../Source/com.c **** /************************************************************************************//** - 61:../../../Source/com.c **** ** \brief Initializes the communication module including the hardware needed for - 62:../../../Source/com.c **** ** the communication. - 63:../../../Source/com.c **** ** \return none - 64:../../../Source/com.c **** ** - 65:../../../Source/com.c **** ****************************************************************************************/ - 66:../../../Source/com.c **** void ComInit(void) - 67:../../../Source/com.c **** { - 27 .loc 1 67 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 0000 08B5 push {r3, lr} - 32 .cfi_def_cfa_offset 8 - 33 .cfi_offset 3, -8 - 34 .cfi_offset 14, -4 - 68:../../../Source/com.c **** /* initialize the XCP communication protocol */ - 69:../../../Source/com.c **** XcpInit(); - 35 .loc 1 69 0 - 36 0002 FFF7FEFF bl XcpInit - 37 .LVL0: - 70:../../../Source/com.c **** #if (BOOT_COM_CAN_ENABLE > 0) - 71:../../../Source/com.c **** /* initialize the CAN controller */ - 72:../../../Source/com.c **** CanInit(); - 73:../../../Source/com.c **** /* set it as active */ - 74:../../../Source/com.c **** comActiveInterface = COM_IF_CAN; - 75:../../../Source/com.c **** #endif - 76:../../../Source/com.c **** #if (BOOT_COM_UART_ENABLE > 0) - 77:../../../Source/com.c **** /* initialize the UART interface */ - 78:../../../Source/com.c **** UartInit(); - 38 .loc 1 78 0 - 39 0006 FFF7FEFF bl UartInit - 40 .LVL1: - 79:../../../Source/com.c **** /* set it as active */ - 80:../../../Source/com.c **** comActiveInterface = COM_IF_UART; - 41 .loc 1 80 0 - 42 000a 0022 movs r2, #0 - 43 000c 014B ldr r3, .L3 - 44 000e 1A70 strb r2, [r3] - 45 0010 08BD pop {r3, pc} - 46 .L4: - 47 0012 00BF .align 2 - 48 .L3: - 49 0014 00000000 .word .LANCHOR0 - 50 .cfi_endproc - 51 .LFE0: - 53 .section .text.ComTask,"ax",%progbits - 54 .align 2 - 55 .global ComTask - 56 .thumb - 57 .thumb_func - 59 ComTask: - 60 .LFB1: - 81:../../../Source/com.c **** #endif - 82:../../../Source/com.c **** #if (BOOT_COM_USB_ENABLE > 0) - 83:../../../Source/com.c **** /* initialize the USB interface */ - 84:../../../Source/com.c **** UsbInit(); - 85:../../../Source/com.c **** /* set it as active */ - 86:../../../Source/com.c **** comActiveInterface = COM_IF_USB; - 87:../../../Source/com.c **** #endif - 88:../../../Source/com.c **** #if (BOOT_COM_NET_ENABLE > 0) - 89:../../../Source/com.c **** /* initialize the TCP/IP interface */ - 90:../../../Source/com.c **** NetInit(); - 91:../../../Source/com.c **** /* set it as active */ - 92:../../../Source/com.c **** comActiveInterface = COM_IF_NET; - 93:../../../Source/com.c **** #endif - 94:../../../Source/com.c **** } /*** end of ComInit ***/ - 95:../../../Source/com.c **** - 96:../../../Source/com.c **** - 97:../../../Source/com.c **** /************************************************************************************//** - 98:../../../Source/com.c **** ** \brief Updates the communication module by checking if new data was received - 99:../../../Source/com.c **** ** and submitting the request to process newly received data. - 100:../../../Source/com.c **** ** \return none - 101:../../../Source/com.c **** ** - 102:../../../Source/com.c **** ****************************************************************************************/ - 103:../../../Source/com.c **** void ComTask(void) - 104:../../../Source/com.c **** { - 61 .loc 1 104 0 - 62 .cfi_startproc - 63 @ args = 0, pretend = 0, frame = 0 - 64 @ frame_needed = 0, uses_anonymous_args = 0 - 65 0000 08B5 push {r3, lr} - 66 .cfi_def_cfa_offset 8 - 67 .cfi_offset 3, -8 - 68 .cfi_offset 14, -4 - 105:../../../Source/com.c **** /* make xcpCtoReqPacket static for runtime efficiency */ - 106:../../../Source/com.c **** static blt_int8u xcpCtoReqPacket[BOOT_COM_RX_MAX_DATA]; - 107:../../../Source/com.c **** - 108:../../../Source/com.c **** #if (BOOT_COM_CAN_ENABLE > 0) - 109:../../../Source/com.c **** if (CanReceivePacket(&xcpCtoReqPacket[0]) == BLT_TRUE) - 110:../../../Source/com.c **** { - 111:../../../Source/com.c **** /* make this the active interface */ - 112:../../../Source/com.c **** comActiveInterface = COM_IF_CAN; - 113:../../../Source/com.c **** /* process packet */ - 114:../../../Source/com.c **** XcpPacketReceived(&xcpCtoReqPacket[0]); - 115:../../../Source/com.c **** } - 116:../../../Source/com.c **** #endif - 117:../../../Source/com.c **** #if (BOOT_COM_UART_ENABLE > 0) - 118:../../../Source/com.c **** if (UartReceivePacket(&xcpCtoReqPacket[0]) == BLT_TRUE) - 69 .loc 1 118 0 - 70 0002 0648 ldr r0, .L8 - 71 0004 FFF7FEFF bl UartReceivePacket - 72 .LVL2: - 73 0008 0128 cmp r0, #1 - 74 000a 05D1 bne .L5 - 119:../../../Source/com.c **** { - 120:../../../Source/com.c **** /* make this the active interface */ - 121:../../../Source/com.c **** comActiveInterface = COM_IF_UART; - 75 .loc 1 121 0 - 76 000c 0022 movs r2, #0 - 77 000e 044B ldr r3, .L8+4 - 78 0010 1A70 strb r2, [r3] - 122:../../../Source/com.c **** /* process packet */ - 123:../../../Source/com.c **** XcpPacketReceived(&xcpCtoReqPacket[0]); - 79 .loc 1 123 0 - 80 0012 0248 ldr r0, .L8 - 81 0014 FFF7FEFF bl XcpPacketReceived - 82 .LVL3: - 83 .L5: - 84 0018 08BD pop {r3, pc} - 85 .L9: - 86 001a 00BF .align 2 - 87 .L8: - 88 001c 00000000 .word .LANCHOR1 - 89 0020 00000000 .word .LANCHOR0 - 90 .cfi_endproc - 91 .LFE1: - 93 .section .text.ComFree,"ax",%progbits - 94 .align 2 - 95 .global ComFree - 96 .thumb - 97 .thumb_func - 99 ComFree: - 100 .LFB2: - 124:../../../Source/com.c **** } - 125:../../../Source/com.c **** #endif - 126:../../../Source/com.c **** #if (BOOT_COM_USB_ENABLE > 0) - 127:../../../Source/com.c **** if (UsbReceivePacket(&xcpCtoReqPacket[0]) == BLT_TRUE) - 128:../../../Source/com.c **** { - 129:../../../Source/com.c **** /* make this the active interface */ - 130:../../../Source/com.c **** comActiveInterface = COM_IF_USB; - 131:../../../Source/com.c **** /* process packet */ - 132:../../../Source/com.c **** XcpPacketReceived(&xcpCtoReqPacket[0]); - 133:../../../Source/com.c **** } - 134:../../../Source/com.c **** #endif - 135:../../../Source/com.c **** #if (BOOT_COM_NET_ENABLE > 0) - 136:../../../Source/com.c **** if (NetReceivePacket(&xcpCtoReqPacket[0]) == BLT_TRUE) - 137:../../../Source/com.c **** { - 138:../../../Source/com.c **** /* make this the active interface */ - 139:../../../Source/com.c **** comActiveInterface = COM_IF_NET; - 140:../../../Source/com.c **** /* process packet */ - 141:../../../Source/com.c **** XcpPacketReceived(&xcpCtoReqPacket[0]); - 142:../../../Source/com.c **** } - 143:../../../Source/com.c **** #endif - 144:../../../Source/com.c **** } /*** end of ComTask ***/ - 145:../../../Source/com.c **** - 146:../../../Source/com.c **** - 147:../../../Source/com.c **** /************************************************************************************//** - 148:../../../Source/com.c **** ** \brief Releases the communication module. - 149:../../../Source/com.c **** ** \return none - 150:../../../Source/com.c **** ** - 151:../../../Source/com.c **** ****************************************************************************************/ - 152:../../../Source/com.c **** void ComFree(void) - 153:../../../Source/com.c **** { - 101 .loc 1 153 0 - 102 .cfi_startproc - 103 @ args = 0, pretend = 0, frame = 0 - 104 @ frame_needed = 0, uses_anonymous_args = 0 - 105 @ link register save eliminated. - 106 0000 7047 bx lr - 107 .cfi_endproc - 108 .LFE2: - 110 0002 00BF .section .text.ComTransmitPacket,"ax",%progbits - 111 .align 2 - 112 .global ComTransmitPacket - 113 .thumb - 114 .thumb_func - 116 ComTransmitPacket: - 117 .LFB3: - 154:../../../Source/com.c **** #if (BOOT_COM_USB_ENABLE > 0) - 155:../../../Source/com.c **** /* disconnect the usb device from the usb host */ - 156:../../../Source/com.c **** UsbFree(); - 157:../../../Source/com.c **** #endif - 158:../../../Source/com.c **** } /*** end of ComFree ***/ - 159:../../../Source/com.c **** - 160:../../../Source/com.c **** - 161:../../../Source/com.c **** /************************************************************************************//** - 162:../../../Source/com.c **** ** \brief Transmits the packet using the xcp transport layer. - 163:../../../Source/com.c **** ** \param data Pointer to the byte buffer with packet data. - 164:../../../Source/com.c **** ** \param len Number of data bytes that need to be transmitted. - 165:../../../Source/com.c **** ** \return none - 166:../../../Source/com.c **** ** - 167:../../../Source/com.c **** ****************************************************************************************/ - 168:../../../Source/com.c **** void ComTransmitPacket(blt_int8u *data, blt_int16u len) - 169:../../../Source/com.c **** { - 118 .loc 1 169 0 - 119 .cfi_startproc - 120 @ args = 0, pretend = 0, frame = 0 - 121 @ frame_needed = 0, uses_anonymous_args = 0 - 122 .LVL4: - 123 .loc 1 169 0 - 124 0000 08B5 push {r3, lr} - 125 .cfi_def_cfa_offset 8 - 126 .cfi_offset 3, -8 - 127 .cfi_offset 14, -4 - 170:../../../Source/com.c **** #if (BOOT_COM_CAN_ENABLE > 0) - 171:../../../Source/com.c **** /* transmit the packet. note that len is limited to 8 in the plausibility check, - 172:../../../Source/com.c **** * so cast is okay. - 173:../../../Source/com.c **** */ - 174:../../../Source/com.c **** if (comActiveInterface == COM_IF_CAN) - 175:../../../Source/com.c **** { - 176:../../../Source/com.c **** CanTransmitPacket(data, (blt_int8u)len); - 177:../../../Source/com.c **** } - 178:../../../Source/com.c **** #endif - 179:../../../Source/com.c **** #if (BOOT_COM_UART_ENABLE > 0) - 180:../../../Source/com.c **** /* transmit the packet. note that len is limited to 255 in the plausibility check, - 181:../../../Source/com.c **** * so cast is okay. - 182:../../../Source/com.c **** */ - 183:../../../Source/com.c **** if (comActiveInterface == COM_IF_UART) - 128 .loc 1 183 0 - 129 0002 044B ldr r3, .L14 - 130 0004 1B78 ldrb r3, [r3] @ zero_extendqisi2 - 131 0006 13B9 cbnz r3, .L12 - 184:../../../Source/com.c **** { - 185:../../../Source/com.c **** UartTransmitPacket(data, (blt_int8u)len); - 132 .loc 1 185 0 - 133 0008 C9B2 uxtb r1, r1 - 134 .LVL5: - 135 000a FFF7FEFF bl UartTransmitPacket - 136 .LVL6: - 137 .L12: - 186:../../../Source/com.c **** } - 187:../../../Source/com.c **** #endif - 188:../../../Source/com.c **** #if (BOOT_COM_USB_ENABLE > 0) - 189:../../../Source/com.c **** /* transmit the packet */ - 190:../../../Source/com.c **** if (comActiveInterface == COM_IF_USB) - 191:../../../Source/com.c **** { - 192:../../../Source/com.c **** UsbTransmitPacket(data, len); - 193:../../../Source/com.c **** } - 194:../../../Source/com.c **** #endif - 195:../../../Source/com.c **** #if (BOOT_COM_NET_ENABLE > 0) - 196:../../../Source/com.c **** if (comActiveInterface == COM_IF_NET) - 197:../../../Source/com.c **** { - 198:../../../Source/com.c **** /* transmit the packet */ - 199:../../../Source/com.c **** NetTransmitPacket(data, len); - 200:../../../Source/com.c **** } - 201:../../../Source/com.c **** #endif - 202:../../../Source/com.c **** - 203:../../../Source/com.c **** /* send signal that the packet was transmitted */ - 204:../../../Source/com.c **** XcpPacketTransmitted(); - 138 .loc 1 204 0 - 139 000e FFF7FEFF bl XcpPacketTransmitted - 140 .LVL7: - 141 0012 08BD pop {r3, pc} - 142 .L15: - 143 .align 2 - 144 .L14: - 145 0014 00000000 .word .LANCHOR0 - 146 .cfi_endproc - 147 .LFE3: - 149 .section .text.ComGetActiveInterfaceMaxRxLen,"ax",%progbits - 150 .align 2 - 151 .global ComGetActiveInterfaceMaxRxLen - 152 .thumb - 153 .thumb_func - 155 ComGetActiveInterfaceMaxRxLen: - 156 .LFB4: - 205:../../../Source/com.c **** } /*** end of ComTransmitPacket ***/ - 206:../../../Source/com.c **** - 207:../../../Source/com.c **** - 208:../../../Source/com.c **** /************************************************************************************//** - 209:../../../Source/com.c **** ** \brief Obtains the maximum number of bytes that can be received on the specified - 210:../../../Source/com.c **** ** communication interface. - 211:../../../Source/com.c **** ** \return Maximum number of bytes that can be received. - 212:../../../Source/com.c **** ** - 213:../../../Source/com.c **** ****************************************************************************************/ - 214:../../../Source/com.c **** blt_int16u ComGetActiveInterfaceMaxRxLen(void) - 215:../../../Source/com.c **** { - 157 .loc 1 215 0 - 158 .cfi_startproc - 159 @ args = 0, pretend = 0, frame = 0 - 160 @ frame_needed = 0, uses_anonymous_args = 0 - 161 @ link register save eliminated. - 216:../../../Source/com.c **** blt_int16u result; - 217:../../../Source/com.c **** - 218:../../../Source/com.c **** /* filter on communication interface identifier */ - 219:../../../Source/com.c **** switch (comActiveInterface) - 162 .loc 1 219 0 - 163 0000 074B ldr r3, .L22 - 164 0002 1B78 ldrb r3, [r3] @ zero_extendqisi2 - 165 0004 022B cmp r3, #2 - 166 0006 06D0 beq .L18 - 167 0008 032B cmp r3, #3 - 168 000a 06D0 beq .L19 - 169 000c 012B cmp r3, #1 - 220:../../../Source/com.c **** { - 221:../../../Source/com.c **** case COM_IF_UART: - 222:../../../Source/com.c **** result = BOOT_COM_UART_RX_MAX_DATA; - 170 .loc 1 222 0 - 171 000e 0CBF ite eq - 172 0010 0820 moveq r0, #8 - 173 0012 4020 movne r0, #64 - 174 0014 7047 bx lr - 175 .L18: - 176 .LVL8: - 223:../../../Source/com.c **** break; - 224:../../../Source/com.c **** - 225:../../../Source/com.c **** case COM_IF_CAN: - 226:../../../Source/com.c **** result = BOOT_COM_CAN_RX_MAX_DATA; - 227:../../../Source/com.c **** break; - 228:../../../Source/com.c **** - 229:../../../Source/com.c **** case COM_IF_USB: - 230:../../../Source/com.c **** result = BOOT_COM_USB_RX_MAX_DATA; - 177 .loc 1 230 0 - 178 0016 0020 movs r0, #0 - 231:../../../Source/com.c **** break; - 179 .loc 1 231 0 - 180 0018 7047 bx lr - 181 .LVL9: - 182 .L19: - 232:../../../Source/com.c **** - 233:../../../Source/com.c **** case COM_IF_NET: - 234:../../../Source/com.c **** result = BOOT_COM_NET_RX_MAX_DATA; - 183 .loc 1 234 0 - 184 001a 0020 movs r0, #0 - 185 .LVL10: - 235:../../../Source/com.c **** break; - 236:../../../Source/com.c **** - 237:../../../Source/com.c **** default: - 238:../../../Source/com.c **** result = BOOT_COM_RX_MAX_DATA; - 239:../../../Source/com.c **** break; - 240:../../../Source/com.c **** } - 241:../../../Source/com.c **** - 242:../../../Source/com.c **** return result; - 243:../../../Source/com.c **** } /*** end of ComGetActiveInterfaceMaxRxLen ***/ - 186 .loc 1 243 0 - 187 001c 7047 bx lr - 188 .L23: - 189 001e 00BF .align 2 - 190 .L22: - 191 0020 00000000 .word .LANCHOR0 - 192 .cfi_endproc - 193 .LFE4: - 195 .section .text.ComGetActiveInterfaceMaxTxLen,"ax",%progbits - 196 .align 2 - 197 .global ComGetActiveInterfaceMaxTxLen - 198 .thumb - 199 .thumb_func - 201 ComGetActiveInterfaceMaxTxLen: - 202 .LFB5: - 244:../../../Source/com.c **** - 245:../../../Source/com.c **** - 246:../../../Source/com.c **** /************************************************************************************//** - 247:../../../Source/com.c **** ** \brief Obtains the maximum number of bytes that can be transmitted on the - 248:../../../Source/com.c **** ** specified communication interface. - 249:../../../Source/com.c **** ** \return Maximum number of bytes that can be received. - 250:../../../Source/com.c **** ** - 251:../../../Source/com.c **** ****************************************************************************************/ - 252:../../../Source/com.c **** blt_int16u ComGetActiveInterfaceMaxTxLen(void) - 253:../../../Source/com.c **** { - 203 .loc 1 253 0 - 204 .cfi_startproc - 205 @ args = 0, pretend = 0, frame = 0 - 206 @ frame_needed = 0, uses_anonymous_args = 0 - 207 @ link register save eliminated. - 254:../../../Source/com.c **** blt_int16u result; - 255:../../../Source/com.c **** - 256:../../../Source/com.c **** /* filter on communication interface identifier */ - 257:../../../Source/com.c **** switch (comActiveInterface) - 208 .loc 1 257 0 - 209 0000 074B ldr r3, .L30 - 210 0002 1B78 ldrb r3, [r3] @ zero_extendqisi2 - 211 0004 022B cmp r3, #2 - 212 0006 06D0 beq .L26 - 213 0008 032B cmp r3, #3 - 214 000a 06D0 beq .L27 - 215 000c 012B cmp r3, #1 - 258:../../../Source/com.c **** { - 259:../../../Source/com.c **** case COM_IF_UART: - 260:../../../Source/com.c **** result = BOOT_COM_UART_TX_MAX_DATA; - 216 .loc 1 260 0 - 217 000e 0CBF ite eq - 218 0010 0820 moveq r0, #8 - 219 0012 4020 movne r0, #64 - 220 0014 7047 bx lr - 221 .L26: - 222 .LVL11: - 261:../../../Source/com.c **** break; - 262:../../../Source/com.c **** - 263:../../../Source/com.c **** case COM_IF_CAN: - 264:../../../Source/com.c **** result = BOOT_COM_CAN_TX_MAX_DATA; - 265:../../../Source/com.c **** break; - 266:../../../Source/com.c **** - 267:../../../Source/com.c **** case COM_IF_USB: - 268:../../../Source/com.c **** result = BOOT_COM_USB_TX_MAX_DATA; - 223 .loc 1 268 0 - 224 0016 0020 movs r0, #0 - 269:../../../Source/com.c **** break; - 225 .loc 1 269 0 - 226 0018 7047 bx lr - 227 .LVL12: - 228 .L27: - 270:../../../Source/com.c **** - 271:../../../Source/com.c **** case COM_IF_NET: - 272:../../../Source/com.c **** result = BOOT_COM_NET_TX_MAX_DATA; - 229 .loc 1 272 0 - 230 001a 0020 movs r0, #0 - 231 .LVL13: - 273:../../../Source/com.c **** break; - 274:../../../Source/com.c **** - 275:../../../Source/com.c **** default: - 276:../../../Source/com.c **** result = BOOT_COM_TX_MAX_DATA; - 277:../../../Source/com.c **** break; - 278:../../../Source/com.c **** } - 279:../../../Source/com.c **** - 280:../../../Source/com.c **** return result; - 281:../../../Source/com.c **** } /*** end of ComGetActiveInterfaceMaxTxLen ***/ - 232 .loc 1 281 0 - 233 001c 7047 bx lr - 234 .L31: - 235 001e 00BF .align 2 - 236 .L30: - 237 0020 00000000 .word .LANCHOR0 - 238 .cfi_endproc - 239 .LFE5: - 241 .section .text.ComIsConnected,"ax",%progbits - 242 .align 2 - 243 .global ComIsConnected - 244 .thumb - 245 .thumb_func - 247 ComIsConnected: - 248 .LFB6: - 282:../../../Source/com.c **** - 283:../../../Source/com.c **** - 284:../../../Source/com.c **** /************************************************************************************//** - 285:../../../Source/com.c **** ** \brief This function obtains the XCP connection state. - 286:../../../Source/com.c **** ** \return BLT_TRUE when an XCP connection is established, BLT_FALSE otherwise. - 287:../../../Source/com.c **** ** - 288:../../../Source/com.c **** ****************************************************************************************/ - 289:../../../Source/com.c **** blt_bool ComIsConnected(void) - 290:../../../Source/com.c **** { - 249 .loc 1 290 0 - 250 .cfi_startproc - 251 @ args = 0, pretend = 0, frame = 0 - 252 @ frame_needed = 0, uses_anonymous_args = 0 - 253 0000 08B5 push {r3, lr} - 254 .cfi_def_cfa_offset 8 - 255 .cfi_offset 3, -8 - 256 .cfi_offset 14, -4 - 291:../../../Source/com.c **** return XcpIsConnected(); - 257 .loc 1 291 0 - 258 0002 FFF7FEFF bl XcpIsConnected - 259 .LVL14: - 292:../../../Source/com.c **** } /*** end of ComIsConnected ***/ - 260 .loc 1 292 0 - 261 0006 08BD pop {r3, pc} - 262 .cfi_endproc - 263 .LFE6: - 265 .section .data.comActiveInterface,"aw",%progbits - 266 .set .LANCHOR0,. + 0 - 269 comActiveInterface: - 270 0000 04 .byte 4 - 271 .section .bss.xcpCtoReqPacket.4189,"aw",%nobits - 272 .align 2 - 273 .set .LANCHOR1,. + 0 - 276 xcpCtoReqPacket.4189: - 277 0000 00000000 .space 64 - 277 00000000 - 277 00000000 - 277 00000000 - 277 00000000 - 278 .text - 279 .Letext0: - 280 .file 2 "../../../Source/ARMCM3_STM32/types.h" - 281 .file 3 "../../../Source/com.h" - 282 .file 4 "../../../Source/xcp.h" - 283 .file 5 "../../../Source/ARMCM3_STM32/uart.h" -DEFINED SYMBOLS - *ABS*:00000000 com.c -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:19 .text.ComInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:24 .text.ComInit:00000000 ComInit -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:49 .text.ComInit:00000014 $d -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:54 .text.ComTask:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:59 .text.ComTask:00000000 ComTask -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:88 .text.ComTask:0000001c $d -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:94 .text.ComFree:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:99 .text.ComFree:00000000 ComFree -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:111 .text.ComTransmitPacket:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:116 .text.ComTransmitPacket:00000000 ComTransmitPacket -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:145 .text.ComTransmitPacket:00000014 $d -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:150 .text.ComGetActiveInterfaceMaxRxLen:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:155 .text.ComGetActiveInterfaceMaxRxLen:00000000 ComGetActiveInterfaceMaxRxLen -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:191 .text.ComGetActiveInterfaceMaxRxLen:00000020 $d -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:196 .text.ComGetActiveInterfaceMaxTxLen:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:201 .text.ComGetActiveInterfaceMaxTxLen:00000000 ComGetActiveInterfaceMaxTxLen -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:237 .text.ComGetActiveInterfaceMaxTxLen:00000020 $d -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:242 .text.ComIsConnected:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:247 .text.ComIsConnected:00000000 ComIsConnected -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:269 .data.comActiveInterface:00000000 comActiveInterface -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:272 .bss.xcpCtoReqPacket.4189:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\ccQn89P2.s:276 .bss.xcpCtoReqPacket.4189:00000000 xcpCtoReqPacket.4189 - .debug_frame:00000010 $d - -UNDEFINED SYMBOLS -XcpInit -UartInit -UartReceivePacket -XcpPacketReceived -UartTransmitPacket -XcpPacketTransmitted -XcpIsConnected diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/cop.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/cop.lst deleted file mode 100644 index 6e0720de..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/cop.lst +++ /dev/null @@ -1,127 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "cop.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.CopInit,"ax",%progbits - 19 .align 2 - 20 .global CopInit - 21 .thumb - 22 .thumb_func - 24 CopInit: - 25 .LFB0: - 26 .file 1 "../../../Source/cop.c" - 1:../../../Source/cop.c **** /************************************************************************************//** - 2:../../../Source/cop.c **** * \file Source\cop.c - 3:../../../Source/cop.c **** * \brief Bootloader watchdog module source file. - 4:../../../Source/cop.c **** * \ingroup Core - 5:../../../Source/cop.c **** * \internal - 6:../../../Source/cop.c **** *---------------------------------------------------------------------------------------- - 7:../../../Source/cop.c **** * C O P Y R I G H T - 8:../../../Source/cop.c **** *---------------------------------------------------------------------------------------- - 9:../../../Source/cop.c **** * Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved - 10:../../../Source/cop.c **** * - 11:../../../Source/cop.c **** *---------------------------------------------------------------------------------------- - 12:../../../Source/cop.c **** * L I C E N S E - 13:../../../Source/cop.c **** *---------------------------------------------------------------------------------------- - 14:../../../Source/cop.c **** * This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or - 15:../../../Source/cop.c **** * modify it under the terms of the GNU General Public License as published by the Free - 16:../../../Source/cop.c **** * Software Foundation, either version 3 of the License, or (at your option) any later - 17:../../../Source/cop.c **** * version. - 18:../../../Source/cop.c **** * - 19:../../../Source/cop.c **** * OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; - 20:../../../Source/cop.c **** * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - 21:../../../Source/cop.c **** * PURPOSE. See the GNU General Public License for more details. - 22:../../../Source/cop.c **** * - 23:../../../Source/cop.c **** * You should have received a copy of the GNU General Public License along with OpenBLT. - 24:../../../Source/cop.c **** * If not, see . - 25:../../../Source/cop.c **** * - 26:../../../Source/cop.c **** * A special exception to the GPL is included to allow you to distribute a combined work - 27:../../../Source/cop.c **** * that includes OpenBLT without being obliged to provide the source code for any - 28:../../../Source/cop.c **** * proprietary components. The exception text is included at the bottom of the license - 29:../../../Source/cop.c **** * file . - 30:../../../Source/cop.c **** * - 31:../../../Source/cop.c **** * \endinternal - 32:../../../Source/cop.c **** ****************************************************************************************/ - 33:../../../Source/cop.c **** - 34:../../../Source/cop.c **** /**************************************************************************************** - 35:../../../Source/cop.c **** * Include files - 36:../../../Source/cop.c **** ****************************************************************************************/ - 37:../../../Source/cop.c **** #include "boot.h" /* bootloader generic header */ - 38:../../../Source/cop.c **** - 39:../../../Source/cop.c **** - 40:../../../Source/cop.c **** /**************************************************************************************** - 41:../../../Source/cop.c **** * Hook functions - 42:../../../Source/cop.c **** ****************************************************************************************/ - 43:../../../Source/cop.c **** #if (BOOT_COP_HOOKS_ENABLE > 0) - 44:../../../Source/cop.c **** extern void CopInitHook(void); - 45:../../../Source/cop.c **** extern void CopServiceHook(void); - 46:../../../Source/cop.c **** #endif - 47:../../../Source/cop.c **** - 48:../../../Source/cop.c **** - 49:../../../Source/cop.c **** /************************************************************************************//** - 50:../../../Source/cop.c **** ** \brief Watchdog initialization function. - 51:../../../Source/cop.c **** ** \return none - 52:../../../Source/cop.c **** ** - 53:../../../Source/cop.c **** ****************************************************************************************/ - 54:../../../Source/cop.c **** void CopInit(void) - 55:../../../Source/cop.c **** { - 27 .loc 1 55 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 @ link register save eliminated. - 32 0000 7047 bx lr - 33 .cfi_endproc - 34 .LFE0: - 36 0002 00BF .section .text.CopService,"ax",%progbits - 37 .align 2 - 38 .global CopService - 39 .thumb - 40 .thumb_func - 42 CopService: - 43 .LFB1: - 56:../../../Source/cop.c **** #if (BOOT_COP_HOOKS_ENABLE > 0) - 57:../../../Source/cop.c **** CopInitHook(); - 58:../../../Source/cop.c **** #endif - 59:../../../Source/cop.c **** } /*** end of CopInit ***/ - 60:../../../Source/cop.c **** - 61:../../../Source/cop.c **** - 62:../../../Source/cop.c **** /************************************************************************************//** - 63:../../../Source/cop.c **** ** \brief Watchdog service function to prevent the watchdog from timing out. - 64:../../../Source/cop.c **** ** \return none - 65:../../../Source/cop.c **** ** - 66:../../../Source/cop.c **** ****************************************************************************************/ - 67:../../../Source/cop.c **** void CopService(void) - 68:../../../Source/cop.c **** { - 44 .loc 1 68 0 - 45 .cfi_startproc - 46 @ args = 0, pretend = 0, frame = 0 - 47 @ frame_needed = 0, uses_anonymous_args = 0 - 48 @ link register save eliminated. - 49 0000 7047 bx lr - 50 .cfi_endproc - 51 .LFE1: - 53 0002 00BF .text - 54 .Letext0: -DEFINED SYMBOLS - *ABS*:00000000 cop.c -C:\Users\lwngim1\AppData\Local\Temp\cc52PIju.s:19 .text.CopInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc52PIju.s:24 .text.CopInit:00000000 CopInit -C:\Users\lwngim1\AppData\Local\Temp\cc52PIju.s:37 .text.CopService:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc52PIju.s:42 .text.CopService:00000000 CopService - .debug_frame:00000010 $d - -NO UNDEFINED SYMBOLS diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/core_cm3.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/core_cm3.lst deleted file mode 100644 index 31f6d80f..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/core_cm3.lst +++ /dev/null @@ -1,1351 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "core_cm3.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.__get_PSP,"ax",%progbits - 19 .align 2 - 20 .global __get_PSP - 21 .thumb - 22 .thumb_func - 24 __get_PSP: - 25 .LFB0: - 26 .file 1 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" - 1:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /**************************************************************************//** - 2:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @file core_cm3.c - 3:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - 4:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @version V1.30 - 5:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @date 30. October 2009 - 6:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 7:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @note - 8:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Copyright (C) 2009 ARM Limited. All rights reserved. - 9:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 10:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @par - 11:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * ARM Limited (ARM) is supplying this software for use with Cortex-M - 12:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * processor based microcontrollers. This file can be freely distributed - 13:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * within development tools that are supporting such ARM based processors. - 14:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 15:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @par - 16:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - 17:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - 18:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - 19:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - 20:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - 21:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 22:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** ******************************************************************************/ - 23:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 24:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #include - 25:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 26:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /* define compiler specific symbols */ - 27:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #if defined ( __CC_ARM ) - 28:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #define __ASM __asm /*!< asm keyword for ARM Comp - 29:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #define __INLINE __inline /*!< inline keyword for ARM C - 30:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 31:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #elif defined ( __ICCARM__ ) - 32:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #define __ASM __asm /*!< asm keyword for IAR Comp - 33:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #define __INLINE inline /*!< inline keyword for IAR C - 34:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 35:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #elif defined ( __GNUC__ ) - 36:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #define __ASM __asm /*!< asm keyword for GNU Comp - 37:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #define __INLINE inline /*!< inline keyword for GNU C - 38:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 39:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #elif defined ( __TASKING__ ) - 40:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #define __ASM __asm /*!< asm keyword for TASKING - 41:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #define __INLINE inline /*!< inline keyword for TASKI - 42:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 43:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #endif - 44:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 45:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 46:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /* ################### Compiler specific Intrinsics ########################### */ - 47:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 48:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ - 49:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /* ARM armcc specific functions */ - 50:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 51:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 52:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Process Stack Pointer - 53:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 54:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return ProcessStackPointer - 55:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 56:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return the actual process stack pointer - 57:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 58:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM uint32_t __get_PSP(void) - 59:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 60:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** mrs r0, psp - 61:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 62:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 63:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 64:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 65:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Process Stack Pointer - 66:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 67:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param topOfProcStack Process Stack Pointer - 68:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 69:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Assign the value ProcessStackPointer to the MSP - 70:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * (process stack pointer) Cortex processor register - 71:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 72:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM void __set_PSP(uint32_t topOfProcStack) - 73:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 74:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** msr psp, r0 - 75:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 76:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 77:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 78:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 79:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Main Stack Pointer - 80:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 81:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return Main Stack Pointer - 82:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 83:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return the current value of the MSP (main stack pointer) - 84:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Cortex processor register - 85:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 86:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM uint32_t __get_MSP(void) - 87:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 88:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** mrs r0, msp - 89:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 90:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 91:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 92:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 93:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Main Stack Pointer - 94:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 95:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param topOfMainStack Main Stack Pointer - 96:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 97:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Assign the value mainStackPointer to the MSP - 98:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * (main stack pointer) Cortex processor register - 99:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 100:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM void __set_MSP(uint32_t mainStackPointer) - 101:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 102:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** msr msp, r0 - 103:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 104:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 105:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 106:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 107:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Reverse byte order in unsigned short value - 108:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 109:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to reverse - 110:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return reversed value - 111:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 112:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Reverse byte order in unsigned short value - 113:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 114:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM uint32_t __REV16(uint16_t value) - 115:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 116:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** rev16 r0, r0 - 117:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 118:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 119:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 120:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 121:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Reverse byte order in signed short value with sign extension to integer - 122:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 123:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to reverse - 124:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return reversed value - 125:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 126:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Reverse byte order in signed short value with sign extension to integer - 127:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 128:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM int32_t __REVSH(int16_t value) - 129:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 130:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** revsh r0, r0 - 131:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 132:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 133:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 134:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 135:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #if (__ARMCC_VERSION < 400000) - 136:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 137:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 138:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Remove the exclusive lock created by ldrex - 139:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 140:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Removes the exclusive lock which is created by ldrex. - 141:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 142:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM void __CLREX(void) - 143:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 144:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** clrex - 145:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 146:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 147:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 148:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Base Priority value - 149:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 150:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return BasePriority - 151:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 152:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return the content of the base priority register - 153:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 154:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM uint32_t __get_BASEPRI(void) - 155:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 156:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** mrs r0, basepri - 157:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 158:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 159:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 160:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 161:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Base Priority value - 162:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 163:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param basePri BasePriority - 164:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 165:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Set the base priority register - 166:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 167:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM void __set_BASEPRI(uint32_t basePri) - 168:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 169:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** msr basepri, r0 - 170:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 171:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 172:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 173:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 174:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Priority Mask value - 175:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 176:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return PriMask - 177:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 178:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return state of the priority mask bit from the priority mask register - 179:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 180:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM uint32_t __get_PRIMASK(void) - 181:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 182:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** mrs r0, primask - 183:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 184:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 185:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 186:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 187:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Priority Mask value - 188:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 189:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param priMask PriMask - 190:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 191:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Set the priority mask bit in the priority mask register - 192:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 193:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM void __set_PRIMASK(uint32_t priMask) - 194:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 195:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** msr primask, r0 - 196:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 197:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 198:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 199:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 200:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Fault Mask value - 201:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 202:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return FaultMask - 203:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 204:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return the content of the fault mask register - 205:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 206:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM uint32_t __get_FAULTMASK(void) - 207:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 208:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** mrs r0, faultmask - 209:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 210:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 211:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 212:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 213:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Fault Mask value - 214:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 215:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param faultMask faultMask value - 216:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 217:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Set the fault mask register - 218:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 219:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM void __set_FAULTMASK(uint32_t faultMask) - 220:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 221:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** msr faultmask, r0 - 222:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 223:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 224:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 225:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 226:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Control Register value - 227:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 228:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return Control value - 229:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 230:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return the content of the control register - 231:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 232:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM uint32_t __get_CONTROL(void) - 233:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 234:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** mrs r0, control - 235:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 236:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 237:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 238:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 239:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Control Register value - 240:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 241:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param control Control value - 242:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 243:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Set the control register - 244:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 245:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM void __set_CONTROL(uint32_t control) - 246:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 247:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** msr control, r0 - 248:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** bx lr - 249:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 250:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 251:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #endif /* __ARMCC_VERSION */ - 252:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 253:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 254:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 255:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ - 256:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /* IAR iccarm specific functions */ - 257:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #pragma diag_suppress=Pe940 - 258:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 259:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 260:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Process Stack Pointer - 261:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 262:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return ProcessStackPointer - 263:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 264:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return the actual process stack pointer - 265:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 266:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __get_PSP(void) - 267:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 268:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("mrs r0, psp"); - 269:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("bx lr"); - 270:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 271:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 272:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 273:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Process Stack Pointer - 274:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 275:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param topOfProcStack Process Stack Pointer - 276:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 277:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Assign the value ProcessStackPointer to the MSP - 278:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * (process stack pointer) Cortex processor register - 279:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 280:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** void __set_PSP(uint32_t topOfProcStack) - 281:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 282:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("msr psp, r0"); - 283:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("bx lr"); - 284:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 285:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 286:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 287:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Main Stack Pointer - 288:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 289:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return Main Stack Pointer - 290:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 291:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return the current value of the MSP (main stack pointer) - 292:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Cortex processor register - 293:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 294:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __get_MSP(void) - 295:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 296:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("mrs r0, msp"); - 297:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("bx lr"); - 298:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 299:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 300:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 301:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Main Stack Pointer - 302:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 303:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param topOfMainStack Main Stack Pointer - 304:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 305:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Assign the value mainStackPointer to the MSP - 306:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * (main stack pointer) Cortex processor register - 307:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 308:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** void __set_MSP(uint32_t topOfMainStack) - 309:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 310:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("msr msp, r0"); - 311:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("bx lr"); - 312:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 313:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 314:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 315:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Reverse byte order in unsigned short value - 316:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 317:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to reverse - 318:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return reversed value - 319:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 320:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Reverse byte order in unsigned short value - 321:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 322:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __REV16(uint16_t value) - 323:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 324:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("rev16 r0, r0"); - 325:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("bx lr"); - 326:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 327:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 328:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 329:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Reverse bit order of value - 330:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 331:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to reverse - 332:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return reversed value - 333:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 334:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Reverse bit order of value - 335:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 336:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __RBIT(uint32_t value) - 337:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 338:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("rbit r0, r0"); - 339:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("bx lr"); - 340:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 341:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 342:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 343:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief LDR Exclusive (8 bit) - 344:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 345:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param *addr address pointer - 346:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return value of (*address) - 347:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 348:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Exclusive LDR command for 8 bit values) - 349:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 350:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint8_t __LDREXB(uint8_t *addr) - 351:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 352:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("ldrexb r0, [r0]"); - 353:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("bx lr"); - 354:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 355:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 356:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 357:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief LDR Exclusive (16 bit) - 358:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 359:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param *addr address pointer - 360:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return value of (*address) - 361:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 362:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Exclusive LDR command for 16 bit values - 363:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 364:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint16_t __LDREXH(uint16_t *addr) - 365:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 366:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("ldrexh r0, [r0]"); - 367:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("bx lr"); - 368:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 369:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 370:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 371:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief LDR Exclusive (32 bit) - 372:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 373:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param *addr address pointer - 374:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return value of (*address) - 375:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 376:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Exclusive LDR command for 32 bit values - 377:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 378:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __LDREXW(uint32_t *addr) - 379:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 380:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("ldrex r0, [r0]"); - 381:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("bx lr"); - 382:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 383:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 384:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 385:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief STR Exclusive (8 bit) - 386:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 387:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to store - 388:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param *addr address pointer - 389:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return successful / failed - 390:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 391:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Exclusive STR command for 8 bit values - 392:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 393:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __STREXB(uint8_t value, uint8_t *addr) - 394:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 395:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("strexb r0, r0, [r1]"); - 396:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("bx lr"); - 397:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 398:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 399:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 400:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief STR Exclusive (16 bit) - 401:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 402:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to store - 403:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param *addr address pointer - 404:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return successful / failed - 405:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 406:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Exclusive STR command for 16 bit values - 407:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 408:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __STREXH(uint16_t value, uint16_t *addr) - 409:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 410:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("strexh r0, r0, [r1]"); - 411:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("bx lr"); - 412:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 413:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 414:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 415:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief STR Exclusive (32 bit) - 416:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 417:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to store - 418:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param *addr address pointer - 419:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return successful / failed - 420:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 421:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Exclusive STR command for 32 bit values - 422:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 423:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __STREXW(uint32_t value, uint32_t *addr) - 424:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 425:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("strex r0, r0, [r1]"); - 426:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM("bx lr"); - 427:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 428:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 429:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #pragma diag_default=Pe940 - 430:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 431:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 432:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ - 433:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /* GNU gcc specific functions */ - 434:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 435:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 436:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Process Stack Pointer - 437:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 438:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return ProcessStackPointer - 439:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 440:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return the actual process stack pointer - 441:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 442:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __get_PSP(void) __attribute__( ( naked ) ); - 443:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __get_PSP(void) - 444:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 27 .loc 1 444 0 - 28 .cfi_startproc - 29 @ Naked Function: prologue and epilogue provided by programmer. - 30 @ args = 0, pretend = 0, frame = 0 - 31 @ frame_needed = 0, uses_anonymous_args = 0 - 32 .LVL0: - 445:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 446:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 447:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("MRS %0, psp\n\t" - 33 .loc 1 447 0 - 34 @ 447 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 35 0000 EFF30980 MRS r0, psp - 36 0004 0046 MOV r0, r0 - 37 0006 7047 BX lr - 38 - 39 @ 0 "" 2 - 40 .LVL1: - 448:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** "MOV r0, %0 \n\t" - 449:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** "BX lr \n\t" : "=r" (result) ); - 450:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 451:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 41 .loc 1 451 0 - 42 .thumb - 43 .cfi_endproc - 44 .LFE0: - 46 .section .text.__set_PSP,"ax",%progbits - 47 .align 2 - 48 .global __set_PSP - 49 .thumb - 50 .thumb_func - 52 __set_PSP: - 53 .LFB1: - 452:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 453:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 454:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Process Stack Pointer - 455:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 456:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param topOfProcStack Process Stack Pointer - 457:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 458:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Assign the value ProcessStackPointer to the MSP - 459:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * (process stack pointer) Cortex processor register - 460:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 461:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); - 462:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** void __set_PSP(uint32_t topOfProcStack) - 463:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 54 .loc 1 463 0 - 55 .cfi_startproc - 56 @ Naked Function: prologue and epilogue provided by programmer. - 57 @ args = 0, pretend = 0, frame = 0 - 58 @ frame_needed = 0, uses_anonymous_args = 0 - 59 .LVL2: - 464:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("MSR psp, %0\n\t" - 60 .loc 1 464 0 - 61 @ 464 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 62 0000 80F30988 MSR psp, r0 - 63 0004 7047 BX lr - 64 - 65 @ 0 "" 2 - 465:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** "BX lr \n\t" : : "r" (topOfProcStack) ); - 466:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 66 .loc 1 466 0 - 67 .thumb - 68 .cfi_endproc - 69 .LFE1: - 71 .section .text.__get_MSP,"ax",%progbits - 72 .align 2 - 73 .global __get_MSP - 74 .thumb - 75 .thumb_func - 77 __get_MSP: - 78 .LFB2: - 467:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 468:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 469:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Main Stack Pointer - 470:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 471:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return Main Stack Pointer - 472:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 473:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return the current value of the MSP (main stack pointer) - 474:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Cortex processor register - 475:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 476:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __get_MSP(void) __attribute__( ( naked ) ); - 477:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __get_MSP(void) - 478:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 79 .loc 1 478 0 - 80 .cfi_startproc - 81 @ Naked Function: prologue and epilogue provided by programmer. - 82 @ args = 0, pretend = 0, frame = 0 - 83 @ frame_needed = 0, uses_anonymous_args = 0 - 84 .LVL3: - 479:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 480:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 481:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("MRS %0, msp\n\t" - 85 .loc 1 481 0 - 86 @ 481 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 87 0000 EFF30880 MRS r0, msp - 88 0004 0046 MOV r0, r0 - 89 0006 7047 BX lr - 90 - 91 @ 0 "" 2 - 92 .LVL4: - 482:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** "MOV r0, %0 \n\t" - 483:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** "BX lr \n\t" : "=r" (result) ); - 484:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 485:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 93 .loc 1 485 0 - 94 .thumb - 95 .cfi_endproc - 96 .LFE2: - 98 .section .text.__set_MSP,"ax",%progbits - 99 .align 2 - 100 .global __set_MSP - 101 .thumb - 102 .thumb_func - 104 __set_MSP: - 105 .LFB3: - 486:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 487:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 488:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Main Stack Pointer - 489:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 490:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param topOfMainStack Main Stack Pointer - 491:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 492:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Assign the value mainStackPointer to the MSP - 493:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * (main stack pointer) Cortex processor register - 494:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 495:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); - 496:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** void __set_MSP(uint32_t topOfMainStack) - 497:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 106 .loc 1 497 0 - 107 .cfi_startproc - 108 @ Naked Function: prologue and epilogue provided by programmer. - 109 @ args = 0, pretend = 0, frame = 0 - 110 @ frame_needed = 0, uses_anonymous_args = 0 - 111 .LVL5: - 498:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("MSR msp, %0\n\t" - 112 .loc 1 498 0 - 113 @ 498 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 114 0000 80F30888 MSR msp, r0 - 115 0004 7047 BX lr - 116 - 117 @ 0 "" 2 - 499:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** "BX lr \n\t" : : "r" (topOfMainStack) ); - 500:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 118 .loc 1 500 0 - 119 .thumb - 120 .cfi_endproc - 121 .LFE3: - 123 .section .text.__get_BASEPRI,"ax",%progbits - 124 .align 2 - 125 .global __get_BASEPRI - 126 .thumb - 127 .thumb_func - 129 __get_BASEPRI: - 130 .LFB4: - 501:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 502:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 503:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Base Priority value - 504:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 505:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return BasePriority - 506:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 507:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return the content of the base priority register - 508:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 509:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __get_BASEPRI(void) - 510:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 131 .loc 1 510 0 - 132 .cfi_startproc - 133 @ args = 0, pretend = 0, frame = 0 - 134 @ frame_needed = 0, uses_anonymous_args = 0 - 135 @ link register save eliminated. - 136 .LVL6: - 511:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 512:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 513:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - 137 .loc 1 513 0 - 138 @ 513 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 139 0000 EFF31280 MRS r0, basepri_max - 140 @ 0 "" 2 - 141 .LVL7: - 514:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 515:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 142 .loc 1 515 0 - 143 .thumb - 144 0004 7047 bx lr - 145 .cfi_endproc - 146 .LFE4: - 148 .section .text.__set_BASEPRI,"ax",%progbits - 149 .align 2 - 150 .global __set_BASEPRI - 151 .thumb - 152 .thumb_func - 154 __set_BASEPRI: - 155 .LFB5: - 516:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 517:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 518:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Base Priority value - 519:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 520:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param basePri BasePriority - 521:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 522:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Set the base priority register - 523:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 524:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** void __set_BASEPRI(uint32_t value) - 525:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 156 .loc 1 525 0 - 157 .cfi_startproc - 158 @ args = 0, pretend = 0, frame = 0 - 159 @ frame_needed = 0, uses_anonymous_args = 0 - 160 @ link register save eliminated. - 161 .LVL8: - 526:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("MSR basepri, %0" : : "r" (value) ); - 162 .loc 1 526 0 - 163 @ 526 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 164 0000 80F31188 MSR basepri, r0 - 165 @ 0 "" 2 - 166 .thumb - 167 0004 7047 bx lr - 168 .cfi_endproc - 169 .LFE5: - 171 0006 00BF .section .text.__get_PRIMASK,"ax",%progbits - 172 .align 2 - 173 .global __get_PRIMASK - 174 .thumb - 175 .thumb_func - 177 __get_PRIMASK: - 178 .LFB6: - 527:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 528:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 529:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 530:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Priority Mask value - 531:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 532:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return PriMask - 533:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 534:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return state of the priority mask bit from the priority mask register - 535:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 536:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __get_PRIMASK(void) - 537:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 179 .loc 1 537 0 - 180 .cfi_startproc - 181 @ args = 0, pretend = 0, frame = 0 - 182 @ frame_needed = 0, uses_anonymous_args = 0 - 183 @ link register save eliminated. - 184 .LVL9: - 538:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 539:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 540:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("MRS %0, primask" : "=r" (result) ); - 185 .loc 1 540 0 - 186 @ 540 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 187 0000 EFF31080 MRS r0, primask - 188 @ 0 "" 2 - 189 .LVL10: - 541:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 542:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 190 .loc 1 542 0 - 191 .thumb - 192 0004 7047 bx lr - 193 .cfi_endproc - 194 .LFE6: - 196 .section .text.__set_PRIMASK,"ax",%progbits - 197 .align 2 - 198 .global __set_PRIMASK - 199 .thumb - 200 .thumb_func - 202 __set_PRIMASK: - 203 .LFB7: - 543:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 544:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 545:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Priority Mask value - 546:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 547:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param priMask PriMask - 548:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 549:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Set the priority mask bit in the priority mask register - 550:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 551:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** void __set_PRIMASK(uint32_t priMask) - 552:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 204 .loc 1 552 0 - 205 .cfi_startproc - 206 @ args = 0, pretend = 0, frame = 0 - 207 @ frame_needed = 0, uses_anonymous_args = 0 - 208 @ link register save eliminated. - 209 .LVL11: - 553:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); - 210 .loc 1 553 0 - 211 @ 553 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 212 0000 80F31088 MSR primask, r0 - 213 @ 0 "" 2 - 214 .thumb - 215 0004 7047 bx lr - 216 .cfi_endproc - 217 .LFE7: - 219 0006 00BF .section .text.__get_FAULTMASK,"ax",%progbits - 220 .align 2 - 221 .global __get_FAULTMASK - 222 .thumb - 223 .thumb_func - 225 __get_FAULTMASK: - 226 .LFB8: - 554:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 555:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 556:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 557:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Fault Mask value - 558:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 559:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return FaultMask - 560:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 561:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return the content of the fault mask register - 562:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 563:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __get_FAULTMASK(void) - 564:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 227 .loc 1 564 0 - 228 .cfi_startproc - 229 @ args = 0, pretend = 0, frame = 0 - 230 @ frame_needed = 0, uses_anonymous_args = 0 - 231 @ link register save eliminated. - 232 .LVL12: - 565:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 566:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 567:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - 233 .loc 1 567 0 - 234 @ 567 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 235 0000 EFF31380 MRS r0, faultmask - 236 @ 0 "" 2 - 237 .LVL13: - 568:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 569:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 238 .loc 1 569 0 - 239 .thumb - 240 0004 7047 bx lr - 241 .cfi_endproc - 242 .LFE8: - 244 .section .text.__set_FAULTMASK,"ax",%progbits - 245 .align 2 - 246 .global __set_FAULTMASK - 247 .thumb - 248 .thumb_func - 250 __set_FAULTMASK: - 251 .LFB9: - 570:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 571:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 572:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Fault Mask value - 573:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 574:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param faultMask faultMask value - 575:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 576:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Set the fault mask register - 577:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 578:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** void __set_FAULTMASK(uint32_t faultMask) - 579:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 252 .loc 1 579 0 - 253 .cfi_startproc - 254 @ args = 0, pretend = 0, frame = 0 - 255 @ frame_needed = 0, uses_anonymous_args = 0 - 256 @ link register save eliminated. - 257 .LVL14: - 580:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); - 258 .loc 1 580 0 - 259 @ 580 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 260 0000 80F31388 MSR faultmask, r0 - 261 @ 0 "" 2 - 262 .thumb - 263 0004 7047 bx lr - 264 .cfi_endproc - 265 .LFE9: - 267 0006 00BF .section .text.__get_CONTROL,"ax",%progbits - 268 .align 2 - 269 .global __get_CONTROL - 270 .thumb - 271 .thumb_func - 273 __get_CONTROL: - 274 .LFB10: - 581:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 582:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 583:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 584:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Return the Control Register value - 585:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 586:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return Control value - 587:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 588:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Return the content of the control register - 589:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 590:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __get_CONTROL(void) - 591:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 275 .loc 1 591 0 - 276 .cfi_startproc - 277 @ args = 0, pretend = 0, frame = 0 - 278 @ frame_needed = 0, uses_anonymous_args = 0 - 279 @ link register save eliminated. - 280 .LVL15: - 592:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 593:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 594:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("MRS %0, control" : "=r" (result) ); - 281 .loc 1 594 0 - 282 @ 594 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 283 0000 EFF31480 MRS r0, control - 284 @ 0 "" 2 - 285 .LVL16: - 595:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 596:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 286 .loc 1 596 0 - 287 .thumb - 288 0004 7047 bx lr - 289 .cfi_endproc - 290 .LFE10: - 292 .section .text.__set_CONTROL,"ax",%progbits - 293 .align 2 - 294 .global __set_CONTROL - 295 .thumb - 296 .thumb_func - 298 __set_CONTROL: - 299 .LFB11: - 597:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 598:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 599:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Set the Control Register value - 600:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 601:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param control Control value - 602:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 603:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Set the control register - 604:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 605:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** void __set_CONTROL(uint32_t control) - 606:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 300 .loc 1 606 0 - 301 .cfi_startproc - 302 @ args = 0, pretend = 0, frame = 0 - 303 @ frame_needed = 0, uses_anonymous_args = 0 - 304 @ link register save eliminated. - 305 .LVL17: - 607:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("MSR control, %0" : : "r" (control) ); - 306 .loc 1 607 0 - 307 @ 607 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 308 0000 80F31488 MSR control, r0 - 309 @ 0 "" 2 - 310 .thumb - 311 0004 7047 bx lr - 312 .cfi_endproc - 313 .LFE11: - 315 0006 00BF .section .text.__REV,"ax",%progbits - 316 .align 2 - 317 .global __REV - 318 .thumb - 319 .thumb_func - 321 __REV: - 322 .LFB12: - 608:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 609:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 610:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 611:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 612:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Reverse byte order in integer value - 613:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 614:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to reverse - 615:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return reversed value - 616:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 617:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Reverse byte order in integer value - 618:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 619:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __REV(uint32_t value) - 620:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 323 .loc 1 620 0 - 324 .cfi_startproc - 325 @ args = 0, pretend = 0, frame = 0 - 326 @ frame_needed = 0, uses_anonymous_args = 0 - 327 @ link register save eliminated. - 328 .LVL18: - 621:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 622:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 623:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - 329 .loc 1 623 0 - 330 @ 623 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 331 0000 00BA rev r0, r0 - 332 @ 0 "" 2 - 333 .LVL19: - 624:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 625:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 334 .loc 1 625 0 - 335 .thumb - 336 0002 7047 bx lr - 337 .cfi_endproc - 338 .LFE12: - 340 .section .text.__REV16,"ax",%progbits - 341 .align 2 - 342 .global __REV16 - 343 .thumb - 344 .thumb_func - 346 __REV16: - 347 .LFB13: - 626:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 627:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 628:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Reverse byte order in unsigned short value - 629:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 630:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to reverse - 631:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return reversed value - 632:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 633:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Reverse byte order in unsigned short value - 634:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 635:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __REV16(uint16_t value) - 636:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 348 .loc 1 636 0 - 349 .cfi_startproc - 350 @ args = 0, pretend = 0, frame = 0 - 351 @ frame_needed = 0, uses_anonymous_args = 0 - 352 @ link register save eliminated. - 353 .LVL20: - 637:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 638:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 639:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - 354 .loc 1 639 0 - 355 @ 639 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 356 0000 40BA rev16 r0, r0 - 357 @ 0 "" 2 - 358 .LVL21: - 640:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 641:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 359 .loc 1 641 0 - 360 .thumb - 361 0002 7047 bx lr - 362 .cfi_endproc - 363 .LFE13: - 365 .section .text.__REVSH,"ax",%progbits - 366 .align 2 - 367 .global __REVSH - 368 .thumb - 369 .thumb_func - 371 __REVSH: - 372 .LFB14: - 642:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 643:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 644:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Reverse byte order in signed short value with sign extension to integer - 645:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 646:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to reverse - 647:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return reversed value - 648:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 649:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Reverse byte order in signed short value with sign extension to integer - 650:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 651:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** int32_t __REVSH(int16_t value) - 652:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 373 .loc 1 652 0 - 374 .cfi_startproc - 375 @ args = 0, pretend = 0, frame = 0 - 376 @ frame_needed = 0, uses_anonymous_args = 0 - 377 @ link register save eliminated. - 378 .LVL22: - 653:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 654:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 655:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - 379 .loc 1 655 0 - 380 @ 655 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 381 0000 C0BA revsh r0, r0 - 382 @ 0 "" 2 - 383 .LVL23: - 656:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 657:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 384 .loc 1 657 0 - 385 .thumb - 386 0002 7047 bx lr - 387 .cfi_endproc - 388 .LFE14: - 390 .section .text.__RBIT,"ax",%progbits - 391 .align 2 - 392 .global __RBIT - 393 .thumb - 394 .thumb_func - 396 __RBIT: - 397 .LFB15: - 658:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 659:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 660:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief Reverse bit order of value - 661:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 662:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to reverse - 663:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return reversed value - 664:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 665:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Reverse bit order of value - 666:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 667:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __RBIT(uint32_t value) - 668:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 398 .loc 1 668 0 - 399 .cfi_startproc - 400 @ args = 0, pretend = 0, frame = 0 - 401 @ frame_needed = 0, uses_anonymous_args = 0 - 402 @ link register save eliminated. - 403 .LVL24: - 669:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 670:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 671:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 404 .loc 1 671 0 - 405 @ 671 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 406 0000 90FAA0F0 rbit r0, r0 - 407 @ 0 "" 2 - 408 .LVL25: - 672:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 673:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 409 .loc 1 673 0 - 410 .thumb - 411 0004 7047 bx lr - 412 .cfi_endproc - 413 .LFE15: - 415 .section .text.__LDREXB,"ax",%progbits - 416 .align 2 - 417 .global __LDREXB - 418 .thumb - 419 .thumb_func - 421 __LDREXB: - 422 .LFB16: - 674:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 675:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 676:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief LDR Exclusive (8 bit) - 677:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 678:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param *addr address pointer - 679:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return value of (*address) - 680:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 681:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Exclusive LDR command for 8 bit value - 682:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 683:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint8_t __LDREXB(uint8_t *addr) - 684:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 423 .loc 1 684 0 - 424 .cfi_startproc - 425 @ args = 0, pretend = 0, frame = 0 - 426 @ frame_needed = 0, uses_anonymous_args = 0 - 427 @ link register save eliminated. - 428 .LVL26: - 685:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint8_t result=0; - 686:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 687:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - 429 .loc 1 687 0 - 430 @ 687 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 431 0000 D0E84F0F ldrexb r0, [r0] - 432 @ 0 "" 2 - 433 .LVL27: - 688:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 689:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 434 .loc 1 689 0 - 435 .thumb - 436 0004 C0B2 uxtb r0, r0 - 437 0006 7047 bx lr - 438 .cfi_endproc - 439 .LFE16: - 441 .section .text.__LDREXH,"ax",%progbits - 442 .align 2 - 443 .global __LDREXH - 444 .thumb - 445 .thumb_func - 447 __LDREXH: - 448 .LFB17: - 690:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 691:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 692:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief LDR Exclusive (16 bit) - 693:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 694:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param *addr address pointer - 695:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return value of (*address) - 696:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 697:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Exclusive LDR command for 16 bit values - 698:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 699:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint16_t __LDREXH(uint16_t *addr) - 700:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 449 .loc 1 700 0 - 450 .cfi_startproc - 451 @ args = 0, pretend = 0, frame = 0 - 452 @ frame_needed = 0, uses_anonymous_args = 0 - 453 @ link register save eliminated. - 454 .LVL28: - 701:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint16_t result=0; - 702:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 703:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - 455 .loc 1 703 0 - 456 @ 703 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 457 0000 D0E85F0F ldrexh r0, [r0] - 458 @ 0 "" 2 - 459 .LVL29: - 704:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 705:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 460 .loc 1 705 0 - 461 .thumb - 462 0004 80B2 uxth r0, r0 - 463 0006 7047 bx lr - 464 .cfi_endproc - 465 .LFE17: - 467 .section .text.__LDREXW,"ax",%progbits - 468 .align 2 - 469 .global __LDREXW - 470 .thumb - 471 .thumb_func - 473 __LDREXW: - 474 .LFB18: - 706:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 707:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 708:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief LDR Exclusive (32 bit) - 709:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 710:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param *addr address pointer - 711:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return value of (*address) - 712:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 713:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Exclusive LDR command for 32 bit values - 714:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 715:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __LDREXW(uint32_t *addr) - 716:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 475 .loc 1 716 0 - 476 .cfi_startproc - 477 @ args = 0, pretend = 0, frame = 0 - 478 @ frame_needed = 0, uses_anonymous_args = 0 - 479 @ link register save eliminated. - 480 .LVL30: - 717:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 718:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 719:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - 481 .loc 1 719 0 - 482 @ 719 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 483 0000 50E8000F ldrex r0, [r0] - 484 @ 0 "" 2 - 485 .LVL31: - 720:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 721:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 486 .loc 1 721 0 - 487 .thumb - 488 0004 7047 bx lr - 489 .cfi_endproc - 490 .LFE18: - 492 .section .text.__STREXB,"ax",%progbits - 493 .align 2 - 494 .global __STREXB - 495 .thumb - 496 .thumb_func - 498 __STREXB: - 499 .LFB19: - 722:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 723:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 724:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief STR Exclusive (8 bit) - 725:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 726:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to store - 727:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param *addr address pointer - 728:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return successful / failed - 729:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 730:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Exclusive STR command for 8 bit values - 731:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 732:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __STREXB(uint8_t value, uint8_t *addr) - 733:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 500 .loc 1 733 0 - 501 .cfi_startproc - 502 @ args = 0, pretend = 0, frame = 0 - 503 @ frame_needed = 0, uses_anonymous_args = 0 - 504 @ link register save eliminated. - 505 .LVL32: - 734:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 735:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 736:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - 506 .loc 1 736 0 - 507 @ 736 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 508 0000 C1E8430F strexb r3, r0, [r1] - 509 @ 0 "" 2 - 510 .LVL33: - 511 .thumb - 512 0004 1846 mov r0, r3 - 513 .LVL34: - 737:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 738:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 514 .loc 1 738 0 - 515 0006 7047 bx lr - 516 .cfi_endproc - 517 .LFE19: - 519 .section .text.__STREXH,"ax",%progbits - 520 .align 2 - 521 .global __STREXH - 522 .thumb - 523 .thumb_func - 525 __STREXH: - 526 .LFB20: - 739:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 740:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 741:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief STR Exclusive (16 bit) - 742:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 743:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to store - 744:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param *addr address pointer - 745:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return successful / failed - 746:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 747:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Exclusive STR command for 16 bit values - 748:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 749:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __STREXH(uint16_t value, uint16_t *addr) - 750:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 527 .loc 1 750 0 - 528 .cfi_startproc - 529 @ args = 0, pretend = 0, frame = 0 - 530 @ frame_needed = 0, uses_anonymous_args = 0 - 531 @ link register save eliminated. - 532 .LVL35: - 751:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 752:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 753:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - 533 .loc 1 753 0 - 534 @ 753 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 535 0000 C1E8530F strexh r3, r0, [r1] - 536 @ 0 "" 2 - 537 .LVL36: - 538 .thumb - 539 0004 1846 mov r0, r3 - 540 .LVL37: - 754:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 755:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 541 .loc 1 755 0 - 542 0006 7047 bx lr - 543 .cfi_endproc - 544 .LFE20: - 546 .section .text.__STREXW,"ax",%progbits - 547 .align 2 - 548 .global __STREXW - 549 .thumb - 550 .thumb_func - 552 __STREXW: - 553 .LFB21: - 756:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 757:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** /** - 758:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @brief STR Exclusive (32 bit) - 759:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 760:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param value value to store - 761:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @param *addr address pointer - 762:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * @return successful / failed - 763:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * - 764:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** * Exclusive STR command for 32 bit values - 765:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** */ - 766:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t __STREXW(uint32_t value, uint32_t *addr) - 767:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** { - 554 .loc 1 767 0 - 555 .cfi_startproc - 556 @ args = 0, pretend = 0, frame = 0 - 557 @ frame_needed = 0, uses_anonymous_args = 0 - 558 @ link register save eliminated. - 559 .LVL38: - 768:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** uint32_t result=0; - 769:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** - 770:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - 560 .loc 1 770 0 - 561 @ 770 "./lib/CMSIS/CM3/CoreSupport/core_cm3.c" 1 - 562 0000 41E80000 strex r0, r0, [r1] - 563 @ 0 "" 2 - 564 .LVL39: - 771:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** return(result); - 772:./lib/CMSIS/CM3/CoreSupport/core_cm3.c **** } - 565 .loc 1 772 0 - 566 .thumb - 567 0004 7047 bx lr - 568 .cfi_endproc - 569 .LFE21: - 571 .text - 572 .Letext0: - 573 .file 2 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\mach - 574 .file 3 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\stdi -DEFINED SYMBOLS - *ABS*:00000000 core_cm3.c -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:19 .text.__get_PSP:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:24 .text.__get_PSP:00000000 __get_PSP -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:47 .text.__set_PSP:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:52 .text.__set_PSP:00000000 __set_PSP -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:72 .text.__get_MSP:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:77 .text.__get_MSP:00000000 __get_MSP -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:99 .text.__set_MSP:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:104 .text.__set_MSP:00000000 __set_MSP -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:124 .text.__get_BASEPRI:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:129 .text.__get_BASEPRI:00000000 __get_BASEPRI -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:149 .text.__set_BASEPRI:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:154 .text.__set_BASEPRI:00000000 __set_BASEPRI -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:172 .text.__get_PRIMASK:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:177 .text.__get_PRIMASK:00000000 __get_PRIMASK -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:197 .text.__set_PRIMASK:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:202 .text.__set_PRIMASK:00000000 __set_PRIMASK -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:220 .text.__get_FAULTMASK:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:225 .text.__get_FAULTMASK:00000000 __get_FAULTMASK -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:245 .text.__set_FAULTMASK:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:250 .text.__set_FAULTMASK:00000000 __set_FAULTMASK -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:268 .text.__get_CONTROL:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:273 .text.__get_CONTROL:00000000 __get_CONTROL -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:293 .text.__set_CONTROL:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:298 .text.__set_CONTROL:00000000 __set_CONTROL -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:316 .text.__REV:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:321 .text.__REV:00000000 __REV -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:341 .text.__REV16:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:346 .text.__REV16:00000000 __REV16 -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:366 .text.__REVSH:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:371 .text.__REVSH:00000000 __REVSH -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:391 .text.__RBIT:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:396 .text.__RBIT:00000000 __RBIT -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:416 .text.__LDREXB:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:421 .text.__LDREXB:00000000 __LDREXB -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:442 .text.__LDREXH:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:447 .text.__LDREXH:00000000 __LDREXH -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:468 .text.__LDREXW:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:473 .text.__LDREXW:00000000 __LDREXW -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:493 .text.__STREXB:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:498 .text.__STREXB:00000000 __STREXB -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:520 .text.__STREXH:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:525 .text.__STREXH:00000000 __STREXH -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:547 .text.__STREXW:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cctHfVNh.s:552 .text.__STREXW:00000000 __STREXW - .debug_frame:00000010 $d - -NO UNDEFINED SYMBOLS diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/cstart.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/cstart.lst deleted file mode 100644 index 35c1d322..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/cstart.lst +++ /dev/null @@ -1,196 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "cstart.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.reset_handler,"ax",%progbits - 19 .align 2 - 20 .global reset_handler - 21 .thumb - 22 .thumb_func - 24 reset_handler: - 25 .LFB0: - 26 .file 1 "../../../Source/ARMCM3_STM32/GCC/cstart.c" - 1:../../../Source/ARMCM3_STM32/GCC/cstart.c **** /************************************************************************************//** - 2:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * \file Source\ARMCM3_STM32\GCC\cstart.c - 3:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * \brief Bootloader C startup source file. - 4:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * \ingroup Target_ARMCM3_STM32 - 5:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * \internal - 6:../../../Source/ARMCM3_STM32/GCC/cstart.c **** *---------------------------------------------------------------------------------------- - 7:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * C O P Y R I G H T - 8:../../../Source/ARMCM3_STM32/GCC/cstart.c **** *---------------------------------------------------------------------------------------- - 9:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved - 10:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * - 11:../../../Source/ARMCM3_STM32/GCC/cstart.c **** *---------------------------------------------------------------------------------------- - 12:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * L I C E N S E - 13:../../../Source/ARMCM3_STM32/GCC/cstart.c **** *---------------------------------------------------------------------------------------- - 14:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or - 15:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * modify it under the terms of the GNU General Public License as published by the Free - 16:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * Software Foundation, either version 3 of the License, or (at your option) any later - 17:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * version. - 18:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * - 19:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; - 20:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - 21:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * PURPOSE. See the GNU General Public License for more details. - 22:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * - 23:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * You should have received a copy of the GNU General Public License along with OpenBLT. - 24:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * If not, see . - 25:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * - 26:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * A special exception to the GPL is included to allow you to distribute a combined work - 27:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * that includes OpenBLT without being obliged to provide the source code for any - 28:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * proprietary components. The exception text is included at the bottom of the license - 29:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * file . - 30:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * - 31:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * \endinternal - 32:../../../Source/ARMCM3_STM32/GCC/cstart.c **** ****************************************************************************************/ - 33:../../../Source/ARMCM3_STM32/GCC/cstart.c **** - 34:../../../Source/ARMCM3_STM32/GCC/cstart.c **** /**************************************************************************************** - 35:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * Include files - 36:../../../Source/ARMCM3_STM32/GCC/cstart.c **** ****************************************************************************************/ - 37:../../../Source/ARMCM3_STM32/GCC/cstart.c **** #include "boot.h" /* bootloader generic header */ - 38:../../../Source/ARMCM3_STM32/GCC/cstart.c **** - 39:../../../Source/ARMCM3_STM32/GCC/cstart.c **** - 40:../../../Source/ARMCM3_STM32/GCC/cstart.c **** /**************************************************************************************** - 41:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * External function protoypes - 42:../../../Source/ARMCM3_STM32/GCC/cstart.c **** ****************************************************************************************/ - 43:../../../Source/ARMCM3_STM32/GCC/cstart.c **** extern int main(void); - 44:../../../Source/ARMCM3_STM32/GCC/cstart.c **** - 45:../../../Source/ARMCM3_STM32/GCC/cstart.c **** - 46:../../../Source/ARMCM3_STM32/GCC/cstart.c **** /**************************************************************************************** - 47:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * External data declarations - 48:../../../Source/ARMCM3_STM32/GCC/cstart.c **** ****************************************************************************************/ - 49:../../../Source/ARMCM3_STM32/GCC/cstart.c **** /* these externals are declared by the linker */ - 50:../../../Source/ARMCM3_STM32/GCC/cstart.c **** extern blt_int32u _etext; - 51:../../../Source/ARMCM3_STM32/GCC/cstart.c **** extern blt_int32u _data; - 52:../../../Source/ARMCM3_STM32/GCC/cstart.c **** extern blt_int32u _edata; - 53:../../../Source/ARMCM3_STM32/GCC/cstart.c **** extern blt_int32u _bss; - 54:../../../Source/ARMCM3_STM32/GCC/cstart.c **** extern blt_int32u _ebss; - 55:../../../Source/ARMCM3_STM32/GCC/cstart.c **** extern blt_int32u _estack; - 56:../../../Source/ARMCM3_STM32/GCC/cstart.c **** - 57:../../../Source/ARMCM3_STM32/GCC/cstart.c **** - 58:../../../Source/ARMCM3_STM32/GCC/cstart.c **** /************************************************************************************//** - 59:../../../Source/ARMCM3_STM32/GCC/cstart.c **** ** \brief Reset interrupt service routine. Configures the stack, initializes - 60:../../../Source/ARMCM3_STM32/GCC/cstart.c **** ** RAM and jumps to function main. - 61:../../../Source/ARMCM3_STM32/GCC/cstart.c **** ** \return none. - 62:../../../Source/ARMCM3_STM32/GCC/cstart.c **** ** - 63:../../../Source/ARMCM3_STM32/GCC/cstart.c **** ****************************************************************************************/ - 64:../../../Source/ARMCM3_STM32/GCC/cstart.c **** void reset_handler(void) - 65:../../../Source/ARMCM3_STM32/GCC/cstart.c **** { - 27 .loc 1 65 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 0000 08B5 push {r3, lr} - 32 .cfi_def_cfa_offset 8 - 33 .cfi_offset 3, -8 - 34 .cfi_offset 14, -4 - 66:../../../Source/ARMCM3_STM32/GCC/cstart.c **** blt_int32u *pSrc, *pDest; - 67:../../../Source/ARMCM3_STM32/GCC/cstart.c **** - 68:../../../Source/ARMCM3_STM32/GCC/cstart.c **** /* disable interrupts first */ - 69:../../../Source/ARMCM3_STM32/GCC/cstart.c **** __asm(" cpsid i"); - 35 .loc 1 69 0 - 36 @ 69 "../../../Source/ARMCM3_STM32/GCC/cstart.c" 1 - 37 0002 72B6 cpsid i - 38 @ 0 "" 2 - 39 .LVL0: - 70:../../../Source/ARMCM3_STM32/GCC/cstart.c **** /* copy the data segment initializers from flash to SRAM */ - 71:../../../Source/ARMCM3_STM32/GCC/cstart.c **** pSrc = &_etext; - 72:../../../Source/ARMCM3_STM32/GCC/cstart.c **** for(pDest = &_data; pDest < &_edata; ) - 40 .loc 1 72 0 - 41 .thumb - 42 0004 0E4B ldr r3, .L6 - 43 0006 0F4A ldr r2, .L6+4 - 44 0008 9A42 cmp r2, r3 - 45 000a 0DD2 bcs .L2 - 46 000c 101D adds r0, r2, #4 - 47 000e 0333 adds r3, r3, #3 - 48 0010 181A subs r0, r3, r0 - 49 0012 20F00300 bic r0, r0, #3 - 50 0016 0430 adds r0, r0, #4 - 51 0018 0B4B ldr r3, .L6+8 - 52 001a 1844 add r0, r0, r3 - 53 .LVL1: - 54 .L3: - 73:../../../Source/ARMCM3_STM32/GCC/cstart.c **** { - 74:../../../Source/ARMCM3_STM32/GCC/cstart.c **** *pDest++ = *pSrc++; - 55 .loc 1 74 0 - 56 001c 53F8041B ldr r1, [r3], #4 - 57 .LVL2: - 58 0020 42F8041B str r1, [r2], #4 - 59 .LVL3: - 72:../../../Source/ARMCM3_STM32/GCC/cstart.c **** { - 60 .loc 1 72 0 - 61 0024 8342 cmp r3, r0 - 62 0026 F9D1 bne .L3 - 63 .LVL4: - 64 .L2: - 75:../../../Source/ARMCM3_STM32/GCC/cstart.c **** } - 76:../../../Source/ARMCM3_STM32/GCC/cstart.c **** /* zero fill the bss segment. this is done with inline assembly since this will - 77:../../../Source/ARMCM3_STM32/GCC/cstart.c **** * clear the value of pDest if it is not kept in a register. - 78:../../../Source/ARMCM3_STM32/GCC/cstart.c **** */ - 79:../../../Source/ARMCM3_STM32/GCC/cstart.c **** __asm(" ldr r0, =_bss\n" - 65 .loc 1 79 0 - 66 @ 79 "../../../Source/ARMCM3_STM32/GCC/cstart.c" 1 - 67 0028 0848 ldr r0, =_bss - 68 002a 0949 ldr r1, =_ebss - 69 002c 4FF00002 mov r2, #0 - 70 .thumb_func - 71 zero_loop: - 72 0030 8842 cmp r0, r1 - 73 0032 B8BF it lt - 74 0034 40F8042B strlt r2, [r0], #4 - 75 0038 FADB blt zero_loop - 76 @ 0 "" 2 - 80:../../../Source/ARMCM3_STM32/GCC/cstart.c **** " ldr r1, =_ebss\n" - 81:../../../Source/ARMCM3_STM32/GCC/cstart.c **** " mov r2, #0\n" - 82:../../../Source/ARMCM3_STM32/GCC/cstart.c **** " .thumb_func\n" - 83:../../../Source/ARMCM3_STM32/GCC/cstart.c **** "zero_loop:\n" - 84:../../../Source/ARMCM3_STM32/GCC/cstart.c **** " cmp r0, r1\n" - 85:../../../Source/ARMCM3_STM32/GCC/cstart.c **** " it lt\n" - 86:../../../Source/ARMCM3_STM32/GCC/cstart.c **** " strlt r2, [r0], #4\n" - 87:../../../Source/ARMCM3_STM32/GCC/cstart.c **** " blt zero_loop"); - 88:../../../Source/ARMCM3_STM32/GCC/cstart.c **** /* start the software application by calling its entry point */ - 89:../../../Source/ARMCM3_STM32/GCC/cstart.c **** main(); - 77 .loc 1 89 0 - 78 .thumb - 79 003a FFF7FEFF bl main - 80 .LVL5: - 81 003e 08BD pop {r3, pc} - 82 .L7: - 83 .align 2 - 84 .L6: - 85 0040 00000000 .word _edata - 86 0044 00000000 .word _data - 87 0048 00000000 .word _etext - 88 .cfi_endproc - 89 .LFE0: - 91 .text - 92 .Letext0: - 93 .file 2 "../../../Source/ARMCM3_STM32/types.h" -DEFINED SYMBOLS - *ABS*:00000000 cstart.c -C:\Users\lwngim1\AppData\Local\Temp\ccu7mGw5.s:19 .text.reset_handler:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccu7mGw5.s:24 .text.reset_handler:00000000 reset_handler -C:\Users\lwngim1\AppData\Local\Temp\ccu7mGw5.s:71 .text.reset_handler:00000030 zero_loop -C:\Users\lwngim1\AppData\Local\Temp\ccu7mGw5.s:85 .text.reset_handler:00000040 $d - .debug_frame:00000010 $d - -UNDEFINED SYMBOLS -_bss -_ebss -main -_edata -_data -_etext diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/ff.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/ff.lst deleted file mode 100644 index 29d6f521..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/ff.lst +++ /dev/null @@ -1,13916 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "ff.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.mem_cpy,"ax",%progbits - 19 .align 2 - 20 .thumb - 21 .thumb_func - 23 mem_cpy: - 24 .LFB0: - 25 .file 1 "../../../Source/third_party/fatfs/src/ff.c" - 1:../../../Source/third_party/fatfs/src/ff.c **** /*----------------------------------------------------------------------------/ - 2:../../../Source/third_party/fatfs/src/ff.c **** / FatFs - FAT file system module R0.09b (C)ChaN, 2013 - 3:../../../Source/third_party/fatfs/src/ff.c **** /-----------------------------------------------------------------------------/ - 4:../../../Source/third_party/fatfs/src/ff.c **** / FatFs module is a generic FAT file system module for small embedded systems. - 5:../../../Source/third_party/fatfs/src/ff.c **** / This is a free software that opened for education, research and commercial - 6:../../../Source/third_party/fatfs/src/ff.c **** / developments under license policy of following terms. - 7:../../../Source/third_party/fatfs/src/ff.c **** / - 8:../../../Source/third_party/fatfs/src/ff.c **** / Copyright (C) 2013, ChaN, all right reserved. - 9:../../../Source/third_party/fatfs/src/ff.c **** / - 10:../../../Source/third_party/fatfs/src/ff.c **** / * The FatFs module is a free software and there is NO WARRANTY. - 11:../../../Source/third_party/fatfs/src/ff.c **** / * No restriction on use. You can use, modify and redistribute it for - 12:../../../Source/third_party/fatfs/src/ff.c **** / personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. - 13:../../../Source/third_party/fatfs/src/ff.c **** / * Redistributions of source code must retain the above copyright notice. - 14:../../../Source/third_party/fatfs/src/ff.c **** / - 15:../../../Source/third_party/fatfs/src/ff.c **** /-----------------------------------------------------------------------------/ - 16:../../../Source/third_party/fatfs/src/ff.c **** / Feb 26,'06 R0.00 Prototype. - 17:../../../Source/third_party/fatfs/src/ff.c **** / - 18:../../../Source/third_party/fatfs/src/ff.c **** / Apr 29,'06 R0.01 First stable version. - 19:../../../Source/third_party/fatfs/src/ff.c **** / - 20:../../../Source/third_party/fatfs/src/ff.c **** / Jun 01,'06 R0.02 Added FAT12 support. - 21:../../../Source/third_party/fatfs/src/ff.c **** / Removed unbuffered mode. - 22:../../../Source/third_party/fatfs/src/ff.c **** / Fixed a problem on small (<32M) partition. - 23:../../../Source/third_party/fatfs/src/ff.c **** / Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). - 24:../../../Source/third_party/fatfs/src/ff.c **** / - 25:../../../Source/third_party/fatfs/src/ff.c **** / Sep 22,'06 R0.03 Added f_rename(). - 26:../../../Source/third_party/fatfs/src/ff.c **** / Changed option _FS_MINIMUM to _FS_MINIMIZE. - 27:../../../Source/third_party/fatfs/src/ff.c **** / Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast. - 28:../../../Source/third_party/fatfs/src/ff.c **** / Fixed f_mkdir() creates incorrect directory on FAT32. - 29:../../../Source/third_party/fatfs/src/ff.c **** / - 30:../../../Source/third_party/fatfs/src/ff.c **** / Feb 04,'07 R0.04 Supported multiple drive system. - 31:../../../Source/third_party/fatfs/src/ff.c **** / Changed some interfaces for multiple drive system. - 32:../../../Source/third_party/fatfs/src/ff.c **** / Changed f_mountdrv() to f_mount(). - 33:../../../Source/third_party/fatfs/src/ff.c **** / Added f_mkfs(). - 34:../../../Source/third_party/fatfs/src/ff.c **** / Apr 01,'07 R0.04a Supported multiple partitions on a physical drive. - 35:../../../Source/third_party/fatfs/src/ff.c **** / Added a capability of extending file size to f_lseek(). - 36:../../../Source/third_party/fatfs/src/ff.c **** / Added minimization level 3. - 37:../../../Source/third_party/fatfs/src/ff.c **** / Fixed an endian sensitive code in f_mkfs(). - 38:../../../Source/third_party/fatfs/src/ff.c **** / May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. - 39:../../../Source/third_party/fatfs/src/ff.c **** / Added FSInfo support. - 40:../../../Source/third_party/fatfs/src/ff.c **** / Fixed DBCS name can result FR_INVALID_NAME. - 41:../../../Source/third_party/fatfs/src/ff.c **** / Fixed short seek (<= csize) collapses the file object. - 42:../../../Source/third_party/fatfs/src/ff.c **** / - 43:../../../Source/third_party/fatfs/src/ff.c **** / Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). - 44:../../../Source/third_party/fatfs/src/ff.c **** / Fixed f_mkfs() on FAT32 creates incorrect FSInfo. - 45:../../../Source/third_party/fatfs/src/ff.c **** / Fixed f_mkdir() on FAT32 creates incorrect directory. - 46:../../../Source/third_party/fatfs/src/ff.c **** / Feb 03,'08 R0.05a Added f_truncate() and f_utime(). - 47:../../../Source/third_party/fatfs/src/ff.c **** / Fixed off by one error at FAT sub-type determination. - 48:../../../Source/third_party/fatfs/src/ff.c **** / Fixed btr in f_read() can be mistruncated. - 49:../../../Source/third_party/fatfs/src/ff.c **** / Fixed cached sector is not flushed when create and close without write. - 50:../../../Source/third_party/fatfs/src/ff.c **** / - 51:../../../Source/third_party/fatfs/src/ff.c **** / Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). - 52:../../../Source/third_party/fatfs/src/ff.c **** / Improved performance of f_lseek() on moving to the same or following cluster. - 53:../../../Source/third_party/fatfs/src/ff.c **** / - 54:../../../Source/third_party/fatfs/src/ff.c **** / Apr 01,'09 R0.07 Merged Tiny-FatFs as a configuration option. (_FS_TINY) - 55:../../../Source/third_party/fatfs/src/ff.c **** / Added long file name feature. - 56:../../../Source/third_party/fatfs/src/ff.c **** / Added multiple code page feature. - 57:../../../Source/third_party/fatfs/src/ff.c **** / Added re-entrancy for multitask operation. - 58:../../../Source/third_party/fatfs/src/ff.c **** / Added auto cluster size selection to f_mkfs(). - 59:../../../Source/third_party/fatfs/src/ff.c **** / Added rewind option to f_readdir(). - 60:../../../Source/third_party/fatfs/src/ff.c **** / Changed result code of critical errors. - 61:../../../Source/third_party/fatfs/src/ff.c **** / Renamed string functions to avoid name collision. - 62:../../../Source/third_party/fatfs/src/ff.c **** / Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg. - 63:../../../Source/third_party/fatfs/src/ff.c **** / Added multiple sector size feature. - 64:../../../Source/third_party/fatfs/src/ff.c **** / Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error. - 65:../../../Source/third_party/fatfs/src/ff.c **** / Fixed wrong cache control in f_lseek(). - 66:../../../Source/third_party/fatfs/src/ff.c **** / Added relative path feature. - 67:../../../Source/third_party/fatfs/src/ff.c **** / Added f_chdir() and f_chdrive(). - 68:../../../Source/third_party/fatfs/src/ff.c **** / Added proper case conversion to extended char. - 69:../../../Source/third_party/fatfs/src/ff.c **** / Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h. - 70:../../../Source/third_party/fatfs/src/ff.c **** / Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. - 71:../../../Source/third_party/fatfs/src/ff.c **** / Fixed name matching error on the 13 char boundary. - 72:../../../Source/third_party/fatfs/src/ff.c **** / Added a configuration option, _LFN_UNICODE. - 73:../../../Source/third_party/fatfs/src/ff.c **** / Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. - 74:../../../Source/third_party/fatfs/src/ff.c **** / - 75:../../../Source/third_party/fatfs/src/ff.c **** / May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3) - 76:../../../Source/third_party/fatfs/src/ff.c **** / Added file lock feature. (_FS_SHARE) - 77:../../../Source/third_party/fatfs/src/ff.c **** / Added fast seek feature. (_USE_FASTSEEK) - 78:../../../Source/third_party/fatfs/src/ff.c **** / Changed some types on the API, XCHAR->TCHAR. - 79:../../../Source/third_party/fatfs/src/ff.c **** / Changed fname member in the FILINFO structure on Unicode cfg. - 80:../../../Source/third_party/fatfs/src/ff.c **** / String functions support UTF-8 encoding files on Unicode cfg. - 81:../../../Source/third_party/fatfs/src/ff.c **** / Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2) - 82:../../../Source/third_party/fatfs/src/ff.c **** / Added sector erase feature. (_USE_ERASE) - 83:../../../Source/third_party/fatfs/src/ff.c **** / Moved file lock semaphore table from fs object to the bss. - 84:../../../Source/third_party/fatfs/src/ff.c **** / Fixed a wrong directory entry is created on non-LFN cfg when the given name con - 85:../../../Source/third_party/fatfs/src/ff.c **** / Fixed f_mkfs() creates wrong FAT32 volume. - 86:../../../Source/third_party/fatfs/src/ff.c **** / Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write(). - 87:../../../Source/third_party/fatfs/src/ff.c **** / f_lseek() reports required table size on creating CLMP. - 88:../../../Source/third_party/fatfs/src/ff.c **** / Extended format syntax of f_printf function. - 89:../../../Source/third_party/fatfs/src/ff.c **** / Ignores duplicated directory separators in given path name. - 90:../../../Source/third_party/fatfs/src/ff.c **** / - 91:../../../Source/third_party/fatfs/src/ff.c **** / Sep 06,'11 R0.09 f_mkfs() supports multiple partition to finish the multiple partition feature. - 92:../../../Source/third_party/fatfs/src/ff.c **** / Added f_fdisk(). (_MULTI_PARTITION = 2) - 93:../../../Source/third_party/fatfs/src/ff.c **** / Aug 27,'12 R0.09a Fixed assertion failure due to OS/2 EA on FAT12/16 volume. - 94:../../../Source/third_party/fatfs/src/ff.c **** / Changed f_open() and f_opendir reject null object pointer to avoid crash. - 95:../../../Source/third_party/fatfs/src/ff.c **** / Changed option name _FS_SHARE to _FS_LOCK. - 96:../../../Source/third_party/fatfs/src/ff.c **** / Jan 24,'13 R0.09b Added f_setlabel() and f_getlabel(). (_USE_LABEL = 1) - 97:../../../Source/third_party/fatfs/src/ff.c **** /---------------------------------------------------------------------------*/ - 98:../../../Source/third_party/fatfs/src/ff.c **** - 99:../../../Source/third_party/fatfs/src/ff.c **** #include "ff.h" /* FatFs configurations and declarations */ - 100:../../../Source/third_party/fatfs/src/ff.c **** #include "diskio.h" /* Declarations of low level disk I/O functions */ - 101:../../../Source/third_party/fatfs/src/ff.c **** - 102:../../../Source/third_party/fatfs/src/ff.c **** - 103:../../../Source/third_party/fatfs/src/ff.c **** /*-------------------------------------------------------------------------- - 104:../../../Source/third_party/fatfs/src/ff.c **** - 105:../../../Source/third_party/fatfs/src/ff.c **** Module Private Definitions - 106:../../../Source/third_party/fatfs/src/ff.c **** - 107:../../../Source/third_party/fatfs/src/ff.c **** ---------------------------------------------------------------------------*/ - 108:../../../Source/third_party/fatfs/src/ff.c **** - 109:../../../Source/third_party/fatfs/src/ff.c **** #if _FATFS != 82786 /* Revision ID */ - 110:../../../Source/third_party/fatfs/src/ff.c **** #error Wrong include file (ff.h). - 111:../../../Source/third_party/fatfs/src/ff.c **** #endif - 112:../../../Source/third_party/fatfs/src/ff.c **** - 113:../../../Source/third_party/fatfs/src/ff.c **** - 114:../../../Source/third_party/fatfs/src/ff.c **** /* Definitions on sector size */ - 115:../../../Source/third_party/fatfs/src/ff.c **** #if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096 - 116:../../../Source/third_party/fatfs/src/ff.c **** #error Wrong sector size. - 117:../../../Source/third_party/fatfs/src/ff.c **** #endif - 118:../../../Source/third_party/fatfs/src/ff.c **** #if _MAX_SS != 512 - 119:../../../Source/third_party/fatfs/src/ff.c **** #define SS(fs) ((fs)->ssize) /* Variable sector size */ - 120:../../../Source/third_party/fatfs/src/ff.c **** #else - 121:../../../Source/third_party/fatfs/src/ff.c **** #define SS(fs) 512U /* Fixed sector size */ - 122:../../../Source/third_party/fatfs/src/ff.c **** #endif - 123:../../../Source/third_party/fatfs/src/ff.c **** - 124:../../../Source/third_party/fatfs/src/ff.c **** - 125:../../../Source/third_party/fatfs/src/ff.c **** /* Reentrancy related */ - 126:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_REENTRANT - 127:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN == 1 - 128:../../../Source/third_party/fatfs/src/ff.c **** #error Static LFN work area must not be used in re-entrant configuration. - 129:../../../Source/third_party/fatfs/src/ff.c **** #endif - 130:../../../Source/third_party/fatfs/src/ff.c **** #define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } - 131:../../../Source/third_party/fatfs/src/ff.c **** #define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } - 132:../../../Source/third_party/fatfs/src/ff.c **** #else - 133:../../../Source/third_party/fatfs/src/ff.c **** #define ENTER_FF(fs) - 134:../../../Source/third_party/fatfs/src/ff.c **** #define LEAVE_FF(fs, res) return res - 135:../../../Source/third_party/fatfs/src/ff.c **** #endif - 136:../../../Source/third_party/fatfs/src/ff.c **** - 137:../../../Source/third_party/fatfs/src/ff.c **** #define ABORT(fs, res) { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); } - 138:../../../Source/third_party/fatfs/src/ff.c **** - 139:../../../Source/third_party/fatfs/src/ff.c **** - 140:../../../Source/third_party/fatfs/src/ff.c **** /* File access control feature */ - 141:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_LOCK - 142:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_READONLY - 143:../../../Source/third_party/fatfs/src/ff.c **** #error _FS_LOCK must be 0 on read-only cfg. - 144:../../../Source/third_party/fatfs/src/ff.c **** #endif - 145:../../../Source/third_party/fatfs/src/ff.c **** typedef struct { - 146:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs; /* File ID 1, volume (NULL:blank entry) */ - 147:../../../Source/third_party/fatfs/src/ff.c **** DWORD clu; /* File ID 2, directory */ - 148:../../../Source/third_party/fatfs/src/ff.c **** WORD idx; /* File ID 3, directory index */ - 149:../../../Source/third_party/fatfs/src/ff.c **** WORD ctr; /* File open counter, 0:none, 0x01..0xFF:read open count, 0x100:write mode */ - 150:../../../Source/third_party/fatfs/src/ff.c **** } FILESEM; - 151:../../../Source/third_party/fatfs/src/ff.c **** #endif - 152:../../../Source/third_party/fatfs/src/ff.c **** - 153:../../../Source/third_party/fatfs/src/ff.c **** - 154:../../../Source/third_party/fatfs/src/ff.c **** - 155:../../../Source/third_party/fatfs/src/ff.c **** /* DBCS code ranges and SBCS extend char conversion table */ - 156:../../../Source/third_party/fatfs/src/ff.c **** - 157:../../../Source/third_party/fatfs/src/ff.c **** #if _CODE_PAGE == 932 /* Japanese Shift-JIS */ - 158:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0x81 /* DBC 1st byte range 1 start */ - 159:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1E 0x9F /* DBC 1st byte range 1 end */ - 160:../../../Source/third_party/fatfs/src/ff.c **** #define _DF2S 0xE0 /* DBC 1st byte range 2 start */ - 161:../../../Source/third_party/fatfs/src/ff.c **** #define _DF2E 0xFC /* DBC 1st byte range 2 end */ - 162:../../../Source/third_party/fatfs/src/ff.c **** #define _DS1S 0x40 /* DBC 2nd byte range 1 start */ - 163:../../../Source/third_party/fatfs/src/ff.c **** #define _DS1E 0x7E /* DBC 2nd byte range 1 end */ - 164:../../../Source/third_party/fatfs/src/ff.c **** #define _DS2S 0x80 /* DBC 2nd byte range 2 start */ - 165:../../../Source/third_party/fatfs/src/ff.c **** #define _DS2E 0xFC /* DBC 2nd byte range 2 end */ - 166:../../../Source/third_party/fatfs/src/ff.c **** - 167:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ - 168:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0x81 - 169:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1E 0xFE - 170:../../../Source/third_party/fatfs/src/ff.c **** #define _DS1S 0x40 - 171:../../../Source/third_party/fatfs/src/ff.c **** #define _DS1E 0x7E - 172:../../../Source/third_party/fatfs/src/ff.c **** #define _DS2S 0x80 - 173:../../../Source/third_party/fatfs/src/ff.c **** #define _DS2E 0xFE - 174:../../../Source/third_party/fatfs/src/ff.c **** - 175:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 949 /* Korean */ - 176:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0x81 - 177:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1E 0xFE - 178:../../../Source/third_party/fatfs/src/ff.c **** #define _DS1S 0x41 - 179:../../../Source/third_party/fatfs/src/ff.c **** #define _DS1E 0x5A - 180:../../../Source/third_party/fatfs/src/ff.c **** #define _DS2S 0x61 - 181:../../../Source/third_party/fatfs/src/ff.c **** #define _DS2E 0x7A - 182:../../../Source/third_party/fatfs/src/ff.c **** #define _DS3S 0x81 - 183:../../../Source/third_party/fatfs/src/ff.c **** #define _DS3E 0xFE - 184:../../../Source/third_party/fatfs/src/ff.c **** - 185:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ - 186:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0x81 - 187:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1E 0xFE - 188:../../../Source/third_party/fatfs/src/ff.c **** #define _DS1S 0x40 - 189:../../../Source/third_party/fatfs/src/ff.c **** #define _DS1E 0x7E - 190:../../../Source/third_party/fatfs/src/ff.c **** #define _DS2S 0xA1 - 191:../../../Source/third_party/fatfs/src/ff.c **** #define _DS2E 0xFE - 192:../../../Source/third_party/fatfs/src/ff.c **** - 193:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 437 /* U.S. (OEM) */ - 194:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 195:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x9 - 196:../../../Source/third_party/fatfs/src/ff.c **** 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2, - 197:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 198:../../../Source/third_party/fatfs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2, - 199:../../../Source/third_party/fatfs/src/ff.c **** - 200:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 720 /* Arabic (OEM) */ - 201:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 202:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x9 - 203:../../../Source/third_party/fatfs/src/ff.c **** 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2, - 204:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 205:../../../Source/third_party/fatfs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2, - 206:../../../Source/third_party/fatfs/src/ff.c **** - 207:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 737 /* Greek (OEM) */ - 208:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 209:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x9 - 210:../../../Source/third_party/fatfs/src/ff.c **** 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2, - 211:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 212:../../../Source/third_party/fatfs/src/ff.c **** 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2, - 213:../../../Source/third_party/fatfs/src/ff.c **** - 214:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 775 /* Baltic (OEM) */ - 215:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 216:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x9 - 217:../../../Source/third_party/fatfs/src/ff.c **** 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2, - 218:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7, - 219:../../../Source/third_party/fatfs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2, - 220:../../../Source/third_party/fatfs/src/ff.c **** - 221:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */ - 222:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 223:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x9 - 224:../../../Source/third_party/fatfs/src/ff.c **** 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2, - 225:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 226:../../../Source/third_party/fatfs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2, - 227:../../../Source/third_party/fatfs/src/ff.c **** - 228:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 852 /* Latin 2 (OEM) */ - 229:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 230:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x9 - 231:../../../Source/third_party/fatfs/src/ff.c **** 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2, - 232:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2, - 233:../../../Source/third_party/fatfs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2, - 234:../../../Source/third_party/fatfs/src/ff.c **** - 235:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 855 /* Cyrillic (OEM) */ - 236:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 237:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x9 - 238:../../../Source/third_party/fatfs/src/ff.c **** 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2, - 239:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3, - 240:../../../Source/third_party/fatfs/src/ff.c **** 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2, - 241:../../../Source/third_party/fatfs/src/ff.c **** - 242:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 857 /* Turkish (OEM) */ - 243:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 244:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x9 - 245:../../../Source/third_party/fatfs/src/ff.c **** 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2, - 246:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 247:../../../Source/third_party/fatfs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2, - 248:../../../Source/third_party/fatfs/src/ff.c **** - 249:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */ - 250:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 251:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x9 - 252:../../../Source/third_party/fatfs/src/ff.c **** 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2, - 253:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2, - 254:../../../Source/third_party/fatfs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2, - 255:../../../Source/third_party/fatfs/src/ff.c **** - 256:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 862 /* Hebrew (OEM) */ - 257:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 258:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x9 - 259:../../../Source/third_party/fatfs/src/ff.c **** 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2, - 260:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 261:../../../Source/third_party/fatfs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2, - 262:../../../Source/third_party/fatfs/src/ff.c **** - 263:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 866 /* Russian (OEM) */ - 264:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 265:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x9 - 266:../../../Source/third_party/fatfs/src/ff.c **** 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2, - 267:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 268:../../../Source/third_party/fatfs/src/ff.c **** 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2, - 269:../../../Source/third_party/fatfs/src/ff.c **** - 270:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */ - 271:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 272:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x9 - 273:../../../Source/third_party/fatfs/src/ff.c **** 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2, - 274:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 275:../../../Source/third_party/fatfs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2, - 276:../../../Source/third_party/fatfs/src/ff.c **** - 277:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 1250 /* Central Europe (Windows) */ - 278:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 279:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x9 - 280:../../../Source/third_party/fatfs/src/ff.c **** 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2, - 281:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 282:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 283:../../../Source/third_party/fatfs/src/ff.c **** - 284:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */ - 285:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 286:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x8 - 287:../../../Source/third_party/fatfs/src/ff.c **** 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2, - 288:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 289:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 290:../../../Source/third_party/fatfs/src/ff.c **** - 291:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */ - 292:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 293:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x9 - 294:../../../Source/third_party/fatfs/src/ff.c **** 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2, - 295:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 296:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 297:../../../Source/third_party/fatfs/src/ff.c **** - 298:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 1253 /* Greek (Windows) */ - 299:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 300:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x9 - 301:../../../Source/third_party/fatfs/src/ff.c **** 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2, - 302:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 303:../../../Source/third_party/fatfs/src/ff.c **** 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2, - 304:../../../Source/third_party/fatfs/src/ff.c **** - 305:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 1254 /* Turkish (Windows) */ - 306:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 307:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x9 - 308:../../../Source/third_party/fatfs/src/ff.c **** 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2, - 309:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 310:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 311:../../../Source/third_party/fatfs/src/ff.c **** - 312:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 1255 /* Hebrew (Windows) */ - 313:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 314:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x9 - 315:../../../Source/third_party/fatfs/src/ff.c **** 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2, - 316:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 317:../../../Source/third_party/fatfs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2, - 318:../../../Source/third_party/fatfs/src/ff.c **** - 319:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 1256 /* Arabic (Windows) */ - 320:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 321:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x9 - 322:../../../Source/third_party/fatfs/src/ff.c **** 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2, - 323:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 324:../../../Source/third_party/fatfs/src/ff.c **** 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2, - 325:../../../Source/third_party/fatfs/src/ff.c **** - 326:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 1257 /* Baltic (Windows) */ - 327:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 328:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x9 - 329:../../../Source/third_party/fatfs/src/ff.c **** 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2, - 330:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 331:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 332:../../../Source/third_party/fatfs/src/ff.c **** - 333:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */ - 334:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 335:../../../Source/third_party/fatfs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x9 - 336:../../../Source/third_party/fatfs/src/ff.c **** 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2, - 337:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2, - 338:../../../Source/third_party/fatfs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2, - 339:../../../Source/third_party/fatfs/src/ff.c **** - 340:../../../Source/third_party/fatfs/src/ff.c **** #elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ - 341:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN - 342:../../../Source/third_party/fatfs/src/ff.c **** #error Cannot use LFN feature without valid code page. - 343:../../../Source/third_party/fatfs/src/ff.c **** #endif - 344:../../../Source/third_party/fatfs/src/ff.c **** #define _DF1S 0 - 345:../../../Source/third_party/fatfs/src/ff.c **** - 346:../../../Source/third_party/fatfs/src/ff.c **** #else - 347:../../../Source/third_party/fatfs/src/ff.c **** #error Unknown code page - 348:../../../Source/third_party/fatfs/src/ff.c **** - 349:../../../Source/third_party/fatfs/src/ff.c **** #endif - 350:../../../Source/third_party/fatfs/src/ff.c **** - 351:../../../Source/third_party/fatfs/src/ff.c **** - 352:../../../Source/third_party/fatfs/src/ff.c **** /* Character code support macros */ - 353:../../../Source/third_party/fatfs/src/ff.c **** #define IsUpper(c) (((c)>='A')&&((c)<='Z')) - 354:../../../Source/third_party/fatfs/src/ff.c **** #define IsLower(c) (((c)>='a')&&((c)<='z')) - 355:../../../Source/third_party/fatfs/src/ff.c **** #define IsDigit(c) (((c)>='0')&&((c)<='9')) - 356:../../../Source/third_party/fatfs/src/ff.c **** - 357:../../../Source/third_party/fatfs/src/ff.c **** #if _DF1S /* Code page is DBCS */ - 358:../../../Source/third_party/fatfs/src/ff.c **** - 359:../../../Source/third_party/fatfs/src/ff.c **** #ifdef _DF2S /* Two 1st byte areas */ - 360:../../../Source/third_party/fatfs/src/ff.c **** #define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) - 361:../../../Source/third_party/fatfs/src/ff.c **** #else /* One 1st byte area */ - 362:../../../Source/third_party/fatfs/src/ff.c **** #define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) - 363:../../../Source/third_party/fatfs/src/ff.c **** #endif - 364:../../../Source/third_party/fatfs/src/ff.c **** - 365:../../../Source/third_party/fatfs/src/ff.c **** #ifdef _DS3S /* Three 2nd byte areas */ - 366:../../../Source/third_party/fatfs/src/ff.c **** #define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) - 367:../../../Source/third_party/fatfs/src/ff.c **** #else /* Two 2nd byte areas */ - 368:../../../Source/third_party/fatfs/src/ff.c **** #define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) - 369:../../../Source/third_party/fatfs/src/ff.c **** #endif - 370:../../../Source/third_party/fatfs/src/ff.c **** - 371:../../../Source/third_party/fatfs/src/ff.c **** #else /* Code page is SBCS */ - 372:../../../Source/third_party/fatfs/src/ff.c **** - 373:../../../Source/third_party/fatfs/src/ff.c **** #define IsDBCS1(c) 0 - 374:../../../Source/third_party/fatfs/src/ff.c **** #define IsDBCS2(c) 0 - 375:../../../Source/third_party/fatfs/src/ff.c **** - 376:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _DF1S */ - 377:../../../Source/third_party/fatfs/src/ff.c **** - 378:../../../Source/third_party/fatfs/src/ff.c **** - 379:../../../Source/third_party/fatfs/src/ff.c **** /* Name status flags */ - 380:../../../Source/third_party/fatfs/src/ff.c **** #define NS 11 /* Index of name status byte in fn[] */ - 381:../../../Source/third_party/fatfs/src/ff.c **** #define NS_LOSS 0x01 /* Out of 8.3 format */ - 382:../../../Source/third_party/fatfs/src/ff.c **** #define NS_LFN 0x02 /* Force to create LFN entry */ - 383:../../../Source/third_party/fatfs/src/ff.c **** #define NS_LAST 0x04 /* Last segment */ - 384:../../../Source/third_party/fatfs/src/ff.c **** #define NS_BODY 0x08 /* Lower case flag (body) */ - 385:../../../Source/third_party/fatfs/src/ff.c **** #define NS_EXT 0x10 /* Lower case flag (ext) */ - 386:../../../Source/third_party/fatfs/src/ff.c **** #define NS_DOT 0x20 /* Dot entry */ - 387:../../../Source/third_party/fatfs/src/ff.c **** - 388:../../../Source/third_party/fatfs/src/ff.c **** - 389:../../../Source/third_party/fatfs/src/ff.c **** /* FAT sub-type boundaries */ - 390:../../../Source/third_party/fatfs/src/ff.c **** /* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */ - 391:../../../Source/third_party/fatfs/src/ff.c **** #define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */ - 392:../../../Source/third_party/fatfs/src/ff.c **** #define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */ - 393:../../../Source/third_party/fatfs/src/ff.c **** - 394:../../../Source/third_party/fatfs/src/ff.c **** - 395:../../../Source/third_party/fatfs/src/ff.c **** /* FatFs refers the members in the FAT structures as byte array instead of - 396:../../../Source/third_party/fatfs/src/ff.c **** / structure member because the structure is not binary compatible between - 397:../../../Source/third_party/fatfs/src/ff.c **** / different platforms */ - 398:../../../Source/third_party/fatfs/src/ff.c **** - 399:../../../Source/third_party/fatfs/src/ff.c **** #define BS_jmpBoot 0 /* Jump instruction (3) */ - 400:../../../Source/third_party/fatfs/src/ff.c **** #define BS_OEMName 3 /* OEM name (8) */ - 401:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_BytsPerSec 11 /* Sector size [byte] (2) */ - 402:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_SecPerClus 13 /* Cluster size [sector] (1) */ - 403:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (2) */ - 404:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_NumFATs 16 /* Number of FAT copies (1) */ - 405:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_RootEntCnt 17 /* Number of root dir entries for FAT12/16 (2) */ - 406:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_TotSec16 19 /* Volume size [sector] (2) */ - 407:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_Media 21 /* Media descriptor (1) */ - 408:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_FATSz16 22 /* FAT size [sector] (2) */ - 409:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_SecPerTrk 24 /* Track size [sector] (2) */ - 410:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_NumHeads 26 /* Number of heads (2) */ - 411:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_HiddSec 28 /* Number of special hidden sectors (4) */ - 412:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_TotSec32 32 /* Volume size [sector] (4) */ - 413:../../../Source/third_party/fatfs/src/ff.c **** #define BS_DrvNum 36 /* Physical drive number (2) */ - 414:../../../Source/third_party/fatfs/src/ff.c **** #define BS_BootSig 38 /* Extended boot signature (1) */ - 415:../../../Source/third_party/fatfs/src/ff.c **** #define BS_VolID 39 /* Volume serial number (4) */ - 416:../../../Source/third_party/fatfs/src/ff.c **** #define BS_VolLab 43 /* Volume label (8) */ - 417:../../../Source/third_party/fatfs/src/ff.c **** #define BS_FilSysType 54 /* File system type (1) */ - 418:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_FATSz32 36 /* FAT size [sector] (4) */ - 419:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_ExtFlags 40 /* Extended flags (2) */ - 420:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_FSVer 42 /* File system version (2) */ - 421:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_RootClus 44 /* Root dir first cluster (4) */ - 422:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_FSInfo 48 /* Offset of FSInfo sector (2) */ - 423:../../../Source/third_party/fatfs/src/ff.c **** #define BPB_BkBootSec 50 /* Offset of backup boot sector (2) */ - 424:../../../Source/third_party/fatfs/src/ff.c **** #define BS_DrvNum32 64 /* Physical drive number (2) */ - 425:../../../Source/third_party/fatfs/src/ff.c **** #define BS_BootSig32 66 /* Extended boot signature (1) */ - 426:../../../Source/third_party/fatfs/src/ff.c **** #define BS_VolID32 67 /* Volume serial number (4) */ - 427:../../../Source/third_party/fatfs/src/ff.c **** #define BS_VolLab32 71 /* Volume label (8) */ - 428:../../../Source/third_party/fatfs/src/ff.c **** #define BS_FilSysType32 82 /* File system type (1) */ - 429:../../../Source/third_party/fatfs/src/ff.c **** #define FSI_LeadSig 0 /* FSI: Leading signature (4) */ - 430:../../../Source/third_party/fatfs/src/ff.c **** #define FSI_StrucSig 484 /* FSI: Structure signature (4) */ - 431:../../../Source/third_party/fatfs/src/ff.c **** #define FSI_Free_Count 488 /* FSI: Number of free clusters (4) */ - 432:../../../Source/third_party/fatfs/src/ff.c **** #define FSI_Nxt_Free 492 /* FSI: Last allocated cluster (4) */ - 433:../../../Source/third_party/fatfs/src/ff.c **** #define MBR_Table 446 /* MBR: Partition table offset (2) */ - 434:../../../Source/third_party/fatfs/src/ff.c **** #define SZ_PTE 16 /* MBR: Size of a partition table entry */ - 435:../../../Source/third_party/fatfs/src/ff.c **** #define BS_55AA 510 /* Boot sector signature (2) */ - 436:../../../Source/third_party/fatfs/src/ff.c **** - 437:../../../Source/third_party/fatfs/src/ff.c **** #define DIR_Name 0 /* Short file name (11) */ - 438:../../../Source/third_party/fatfs/src/ff.c **** #define DIR_Attr 11 /* Attribute (1) */ - 439:../../../Source/third_party/fatfs/src/ff.c **** #define DIR_NTres 12 /* NT flag (1) */ - 440:../../../Source/third_party/fatfs/src/ff.c **** #define DIR_CrtTimeTenth 13 /* Created time sub-second (1) */ - 441:../../../Source/third_party/fatfs/src/ff.c **** #define DIR_CrtTime 14 /* Created time (2) */ - 442:../../../Source/third_party/fatfs/src/ff.c **** #define DIR_CrtDate 16 /* Created date (2) */ - 443:../../../Source/third_party/fatfs/src/ff.c **** #define DIR_LstAccDate 18 /* Last accessed date (2) */ - 444:../../../Source/third_party/fatfs/src/ff.c **** #define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (2) */ - 445:../../../Source/third_party/fatfs/src/ff.c **** #define DIR_WrtTime 22 /* Modified time (2) */ - 446:../../../Source/third_party/fatfs/src/ff.c **** #define DIR_WrtDate 24 /* Modified date (2) */ - 447:../../../Source/third_party/fatfs/src/ff.c **** #define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (2) */ - 448:../../../Source/third_party/fatfs/src/ff.c **** #define DIR_FileSize 28 /* File size (4) */ - 449:../../../Source/third_party/fatfs/src/ff.c **** #define LDIR_Ord 0 /* LFN entry order and LLE flag (1) */ - 450:../../../Source/third_party/fatfs/src/ff.c **** #define LDIR_Attr 11 /* LFN attribute (1) */ - 451:../../../Source/third_party/fatfs/src/ff.c **** #define LDIR_Type 12 /* LFN type (1) */ - 452:../../../Source/third_party/fatfs/src/ff.c **** #define LDIR_Chksum 13 /* Sum of corresponding SFN entry */ - 453:../../../Source/third_party/fatfs/src/ff.c **** #define LDIR_FstClusLO 26 /* Filled by zero (0) */ - 454:../../../Source/third_party/fatfs/src/ff.c **** #define SZ_DIR 32 /* Size of a directory entry */ - 455:../../../Source/third_party/fatfs/src/ff.c **** #define LLE 0x40 /* Last long entry flag in LDIR_Ord */ - 456:../../../Source/third_party/fatfs/src/ff.c **** #define DDE 0xE5 /* Deleted directory entry mark in DIR_Name[0] */ - 457:../../../Source/third_party/fatfs/src/ff.c **** #define NDDE 0x05 /* Replacement of the character collides with DDE */ - 458:../../../Source/third_party/fatfs/src/ff.c **** - 459:../../../Source/third_party/fatfs/src/ff.c **** - 460:../../../Source/third_party/fatfs/src/ff.c **** /*------------------------------------------------------------*/ - 461:../../../Source/third_party/fatfs/src/ff.c **** /* Module private work area */ - 462:../../../Source/third_party/fatfs/src/ff.c **** /*------------------------------------------------------------*/ - 463:../../../Source/third_party/fatfs/src/ff.c **** /* Note that uninitialized variables with static duration are - 464:../../../Source/third_party/fatfs/src/ff.c **** / zeroed/nulled at start-up. If not, the compiler or start-up - 465:../../../Source/third_party/fatfs/src/ff.c **** / routine is out of ANSI-C standard. - 466:../../../Source/third_party/fatfs/src/ff.c **** */ - 467:../../../Source/third_party/fatfs/src/ff.c **** - 468:../../../Source/third_party/fatfs/src/ff.c **** #if _VOLUMES - 469:../../../Source/third_party/fatfs/src/ff.c **** static - 470:../../../Source/third_party/fatfs/src/ff.c **** FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */ - 471:../../../Source/third_party/fatfs/src/ff.c **** #else - 472:../../../Source/third_party/fatfs/src/ff.c **** #error Number of volumes must not be 0. - 473:../../../Source/third_party/fatfs/src/ff.c **** #endif - 474:../../../Source/third_party/fatfs/src/ff.c **** - 475:../../../Source/third_party/fatfs/src/ff.c **** static - 476:../../../Source/third_party/fatfs/src/ff.c **** WORD Fsid; /* File system mount ID */ - 477:../../../Source/third_party/fatfs/src/ff.c **** - 478:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_RPATH - 479:../../../Source/third_party/fatfs/src/ff.c **** static - 480:../../../Source/third_party/fatfs/src/ff.c **** BYTE CurrVol; /* Current drive */ - 481:../../../Source/third_party/fatfs/src/ff.c **** #endif - 482:../../../Source/third_party/fatfs/src/ff.c **** - 483:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_LOCK - 484:../../../Source/third_party/fatfs/src/ff.c **** static - 485:../../../Source/third_party/fatfs/src/ff.c **** FILESEM Files[_FS_LOCK]; /* File lock semaphores */ - 486:../../../Source/third_party/fatfs/src/ff.c **** #endif - 487:../../../Source/third_party/fatfs/src/ff.c **** - 488:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN == 0 /* No LFN feature */ - 489:../../../Source/third_party/fatfs/src/ff.c **** #define DEF_NAMEBUF BYTE sfn[12] - 490:../../../Source/third_party/fatfs/src/ff.c **** #define INIT_BUF(dobj) (dobj).fn = sfn - 491:../../../Source/third_party/fatfs/src/ff.c **** #define FREE_BUF() - 492:../../../Source/third_party/fatfs/src/ff.c **** - 493:../../../Source/third_party/fatfs/src/ff.c **** #elif _USE_LFN == 1 /* LFN feature with static working buffer */ - 494:../../../Source/third_party/fatfs/src/ff.c **** static WCHAR LfnBuf[_MAX_LFN+1]; - 495:../../../Source/third_party/fatfs/src/ff.c **** #define DEF_NAMEBUF BYTE sfn[12] - 496:../../../Source/third_party/fatfs/src/ff.c **** #define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; } - 497:../../../Source/third_party/fatfs/src/ff.c **** #define FREE_BUF() - 498:../../../Source/third_party/fatfs/src/ff.c **** - 499:../../../Source/third_party/fatfs/src/ff.c **** #elif _USE_LFN == 2 /* LFN feature with dynamic working buffer on the stack */ - 500:../../../Source/third_party/fatfs/src/ff.c **** #define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1] - 501:../../../Source/third_party/fatfs/src/ff.c **** #define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; } - 502:../../../Source/third_party/fatfs/src/ff.c **** #define FREE_BUF() - 503:../../../Source/third_party/fatfs/src/ff.c **** - 504:../../../Source/third_party/fatfs/src/ff.c **** #elif _USE_LFN == 3 /* LFN feature with dynamic working buffer on the heap */ - 505:../../../Source/third_party/fatfs/src/ff.c **** #define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn - 506:../../../Source/third_party/fatfs/src/ff.c **** #define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \ - 507:../../../Source/third_party/fatfs/src/ff.c **** if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \ - 508:../../../Source/third_party/fatfs/src/ff.c **** (dobj).lfn = lfn; (dobj).fn = sfn; } - 509:../../../Source/third_party/fatfs/src/ff.c **** #define FREE_BUF() ff_memfree(lfn) - 510:../../../Source/third_party/fatfs/src/ff.c **** - 511:../../../Source/third_party/fatfs/src/ff.c **** #else - 512:../../../Source/third_party/fatfs/src/ff.c **** #error Wrong LFN configuration. - 513:../../../Source/third_party/fatfs/src/ff.c **** #endif - 514:../../../Source/third_party/fatfs/src/ff.c **** - 515:../../../Source/third_party/fatfs/src/ff.c **** - 516:../../../Source/third_party/fatfs/src/ff.c **** #ifdef _EXCVT - 517:../../../Source/third_party/fatfs/src/ff.c **** static - 518:../../../Source/third_party/fatfs/src/ff.c **** const BYTE ExCvt[] = _EXCVT; /* Upper conversion table for extended chars */ - 519:../../../Source/third_party/fatfs/src/ff.c **** #endif - 520:../../../Source/third_party/fatfs/src/ff.c **** - 521:../../../Source/third_party/fatfs/src/ff.c **** - 522:../../../Source/third_party/fatfs/src/ff.c **** - 523:../../../Source/third_party/fatfs/src/ff.c **** - 524:../../../Source/third_party/fatfs/src/ff.c **** - 525:../../../Source/third_party/fatfs/src/ff.c **** - 526:../../../Source/third_party/fatfs/src/ff.c **** /*-------------------------------------------------------------------------- - 527:../../../Source/third_party/fatfs/src/ff.c **** - 528:../../../Source/third_party/fatfs/src/ff.c **** Module Private Functions - 529:../../../Source/third_party/fatfs/src/ff.c **** - 530:../../../Source/third_party/fatfs/src/ff.c **** ---------------------------------------------------------------------------*/ - 531:../../../Source/third_party/fatfs/src/ff.c **** - 532:../../../Source/third_party/fatfs/src/ff.c **** - 533:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 534:../../../Source/third_party/fatfs/src/ff.c **** /* String functions */ - 535:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 536:../../../Source/third_party/fatfs/src/ff.c **** - 537:../../../Source/third_party/fatfs/src/ff.c **** /* Copy memory to memory */ - 538:../../../Source/third_party/fatfs/src/ff.c **** static - 539:../../../Source/third_party/fatfs/src/ff.c **** void mem_cpy (void* dst, const void* src, UINT cnt) { - 26 .loc 1 539 0 - 27 .cfi_startproc - 28 @ args = 0, pretend = 0, frame = 0 - 29 @ frame_needed = 0, uses_anonymous_args = 0 - 30 @ link register save eliminated. - 31 .LVL0: - 540:../../../Source/third_party/fatfs/src/ff.c **** BYTE *d = (BYTE*)dst; - 541:../../../Source/third_party/fatfs/src/ff.c **** const BYTE *s = (const BYTE*)src; - 542:../../../Source/third_party/fatfs/src/ff.c **** - 543:../../../Source/third_party/fatfs/src/ff.c **** #if _WORD_ACCESS == 1 - 544:../../../Source/third_party/fatfs/src/ff.c **** while (cnt >= sizeof (int)) { - 545:../../../Source/third_party/fatfs/src/ff.c **** *(int*)d = *(int*)s; - 546:../../../Source/third_party/fatfs/src/ff.c **** d += sizeof (int); s += sizeof (int); - 547:../../../Source/third_party/fatfs/src/ff.c **** cnt -= sizeof (int); - 548:../../../Source/third_party/fatfs/src/ff.c **** } - 549:../../../Source/third_party/fatfs/src/ff.c **** #endif - 550:../../../Source/third_party/fatfs/src/ff.c **** while (cnt--) - 32 .loc 1 550 0 - 33 0000 3AB1 cbz r2, .L1 - 34 0002 0138 subs r0, r0, #1 - 35 .LVL1: - 36 0004 8A18 adds r2, r1, r2 - 37 .LVL2: - 38 .L3: - 551:../../../Source/third_party/fatfs/src/ff.c **** *d++ = *s++; - 39 .loc 1 551 0 - 40 0006 11F8013B ldrb r3, [r1], #1 @ zero_extendqisi2 - 41 .LVL3: - 42 000a 00F8013F strb r3, [r0, #1]! - 43 .LVL4: - 550:../../../Source/third_party/fatfs/src/ff.c **** *d++ = *s++; - 44 .loc 1 550 0 - 45 000e 9142 cmp r1, r2 - 46 0010 F9D1 bne .L3 - 47 .LVL5: - 48 .L1: - 49 0012 7047 bx lr - 50 .cfi_endproc - 51 .LFE0: - 53 .section .text.ld_clust,"ax",%progbits - 54 .align 2 - 55 .thumb - 56 .thumb_func - 58 ld_clust: - 59 .LFB15: - 552:../../../Source/third_party/fatfs/src/ff.c **** } - 553:../../../Source/third_party/fatfs/src/ff.c **** - 554:../../../Source/third_party/fatfs/src/ff.c **** /* Fill memory */ - 555:../../../Source/third_party/fatfs/src/ff.c **** static - 556:../../../Source/third_party/fatfs/src/ff.c **** void mem_set (void* dst, int val, UINT cnt) { - 557:../../../Source/third_party/fatfs/src/ff.c **** BYTE *d = (BYTE*)dst; - 558:../../../Source/third_party/fatfs/src/ff.c **** - 559:../../../Source/third_party/fatfs/src/ff.c **** while (cnt--) - 560:../../../Source/third_party/fatfs/src/ff.c **** *d++ = (BYTE)val; - 561:../../../Source/third_party/fatfs/src/ff.c **** } - 562:../../../Source/third_party/fatfs/src/ff.c **** - 563:../../../Source/third_party/fatfs/src/ff.c **** /* Compare memory to memory */ - 564:../../../Source/third_party/fatfs/src/ff.c **** static - 565:../../../Source/third_party/fatfs/src/ff.c **** int mem_cmp (const void* dst, const void* src, UINT cnt) { - 566:../../../Source/third_party/fatfs/src/ff.c **** const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; - 567:../../../Source/third_party/fatfs/src/ff.c **** int r = 0; - 568:../../../Source/third_party/fatfs/src/ff.c **** - 569:../../../Source/third_party/fatfs/src/ff.c **** while (cnt-- && (r = *d++ - *s++) == 0) ; - 570:../../../Source/third_party/fatfs/src/ff.c **** return r; - 571:../../../Source/third_party/fatfs/src/ff.c **** } - 572:../../../Source/third_party/fatfs/src/ff.c **** - 573:../../../Source/third_party/fatfs/src/ff.c **** /* Check if chr is contained in the string */ - 574:../../../Source/third_party/fatfs/src/ff.c **** static - 575:../../../Source/third_party/fatfs/src/ff.c **** int chk_chr (const char* str, int chr) { - 576:../../../Source/third_party/fatfs/src/ff.c **** while (*str && *str != chr) str++; - 577:../../../Source/third_party/fatfs/src/ff.c **** return *str; - 578:../../../Source/third_party/fatfs/src/ff.c **** } - 579:../../../Source/third_party/fatfs/src/ff.c **** - 580:../../../Source/third_party/fatfs/src/ff.c **** - 581:../../../Source/third_party/fatfs/src/ff.c **** - 582:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 583:../../../Source/third_party/fatfs/src/ff.c **** /* Request/Release grant to access the volume */ - 584:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 585:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_REENTRANT - 586:../../../Source/third_party/fatfs/src/ff.c **** - 587:../../../Source/third_party/fatfs/src/ff.c **** static - 588:../../../Source/third_party/fatfs/src/ff.c **** int lock_fs ( - 589:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs /* File system object */ - 590:../../../Source/third_party/fatfs/src/ff.c **** ) - 591:../../../Source/third_party/fatfs/src/ff.c **** { - 592:../../../Source/third_party/fatfs/src/ff.c **** return ff_req_grant(fs->sobj); - 593:../../../Source/third_party/fatfs/src/ff.c **** } - 594:../../../Source/third_party/fatfs/src/ff.c **** - 595:../../../Source/third_party/fatfs/src/ff.c **** - 596:../../../Source/third_party/fatfs/src/ff.c **** static - 597:../../../Source/third_party/fatfs/src/ff.c **** void unlock_fs ( - 598:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs, /* File system object */ - 599:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res /* Result code to be returned */ - 600:../../../Source/third_party/fatfs/src/ff.c **** ) - 601:../../../Source/third_party/fatfs/src/ff.c **** { - 602:../../../Source/third_party/fatfs/src/ff.c **** if (fs && - 603:../../../Source/third_party/fatfs/src/ff.c **** res != FR_NOT_ENABLED && - 604:../../../Source/third_party/fatfs/src/ff.c **** res != FR_INVALID_DRIVE && - 605:../../../Source/third_party/fatfs/src/ff.c **** res != FR_INVALID_OBJECT && - 606:../../../Source/third_party/fatfs/src/ff.c **** res != FR_TIMEOUT) { - 607:../../../Source/third_party/fatfs/src/ff.c **** ff_rel_grant(fs->sobj); - 608:../../../Source/third_party/fatfs/src/ff.c **** } - 609:../../../Source/third_party/fatfs/src/ff.c **** } - 610:../../../Source/third_party/fatfs/src/ff.c **** #endif - 611:../../../Source/third_party/fatfs/src/ff.c **** - 612:../../../Source/third_party/fatfs/src/ff.c **** - 613:../../../Source/third_party/fatfs/src/ff.c **** - 614:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 615:../../../Source/third_party/fatfs/src/ff.c **** /* File lock control functions */ - 616:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 617:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_LOCK - 618:../../../Source/third_party/fatfs/src/ff.c **** - 619:../../../Source/third_party/fatfs/src/ff.c **** static - 620:../../../Source/third_party/fatfs/src/ff.c **** FRESULT chk_lock ( /* Check if the file can be accessed */ - 621:../../../Source/third_party/fatfs/src/ff.c **** DIR* dj, /* Directory object pointing the file to be checked */ - 622:../../../Source/third_party/fatfs/src/ff.c **** int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ - 623:../../../Source/third_party/fatfs/src/ff.c **** ) - 624:../../../Source/third_party/fatfs/src/ff.c **** { - 625:../../../Source/third_party/fatfs/src/ff.c **** UINT i, be; - 626:../../../Source/third_party/fatfs/src/ff.c **** - 627:../../../Source/third_party/fatfs/src/ff.c **** /* Search file semaphore table */ - 628:../../../Source/third_party/fatfs/src/ff.c **** for (i = be = 0; i < _FS_LOCK; i++) { - 629:../../../Source/third_party/fatfs/src/ff.c **** if (Files[i].fs) { /* Existing entry */ - 630:../../../Source/third_party/fatfs/src/ff.c **** if (Files[i].fs == dj->fs && /* Check if the file matched with an open file */ - 631:../../../Source/third_party/fatfs/src/ff.c **** Files[i].clu == dj->sclust && - 632:../../../Source/third_party/fatfs/src/ff.c **** Files[i].idx == dj->index) break; - 633:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Blank entry */ - 634:../../../Source/third_party/fatfs/src/ff.c **** be++; - 635:../../../Source/third_party/fatfs/src/ff.c **** } - 636:../../../Source/third_party/fatfs/src/ff.c **** } - 637:../../../Source/third_party/fatfs/src/ff.c **** if (i == _FS_LOCK) /* The file is not opened */ - 638:../../../Source/third_party/fatfs/src/ff.c **** return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new file? - 639:../../../Source/third_party/fatfs/src/ff.c **** - 640:../../../Source/third_party/fatfs/src/ff.c **** /* The file has been opened. Reject any open against writing file and all write mode open */ - 641:../../../Source/third_party/fatfs/src/ff.c **** return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; - 642:../../../Source/third_party/fatfs/src/ff.c **** } - 643:../../../Source/third_party/fatfs/src/ff.c **** - 644:../../../Source/third_party/fatfs/src/ff.c **** - 645:../../../Source/third_party/fatfs/src/ff.c **** static - 646:../../../Source/third_party/fatfs/src/ff.c **** int enq_lock (void) /* Check if an entry is available for a new file */ - 647:../../../Source/third_party/fatfs/src/ff.c **** { - 648:../../../Source/third_party/fatfs/src/ff.c **** UINT i; - 649:../../../Source/third_party/fatfs/src/ff.c **** - 650:../../../Source/third_party/fatfs/src/ff.c **** for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; - 651:../../../Source/third_party/fatfs/src/ff.c **** return (i == _FS_LOCK) ? 0 : 1; - 652:../../../Source/third_party/fatfs/src/ff.c **** } - 653:../../../Source/third_party/fatfs/src/ff.c **** - 654:../../../Source/third_party/fatfs/src/ff.c **** - 655:../../../Source/third_party/fatfs/src/ff.c **** static - 656:../../../Source/third_party/fatfs/src/ff.c **** UINT inc_lock ( /* Increment file open counter and returns its index (0:int error) */ - 657:../../../Source/third_party/fatfs/src/ff.c **** DIR* dj, /* Directory object pointing the file to register or increment */ - 658:../../../Source/third_party/fatfs/src/ff.c **** int acc /* Desired access mode (0:Read, !0:Write) */ - 659:../../../Source/third_party/fatfs/src/ff.c **** ) - 660:../../../Source/third_party/fatfs/src/ff.c **** { - 661:../../../Source/third_party/fatfs/src/ff.c **** UINT i; - 662:../../../Source/third_party/fatfs/src/ff.c **** - 663:../../../Source/third_party/fatfs/src/ff.c **** - 664:../../../Source/third_party/fatfs/src/ff.c **** for (i = 0; i < _FS_LOCK; i++) { /* Find the file */ - 665:../../../Source/third_party/fatfs/src/ff.c **** if (Files[i].fs == dj->fs && - 666:../../../Source/third_party/fatfs/src/ff.c **** Files[i].clu == dj->sclust && - 667:../../../Source/third_party/fatfs/src/ff.c **** Files[i].idx == dj->index) break; - 668:../../../Source/third_party/fatfs/src/ff.c **** } - 669:../../../Source/third_party/fatfs/src/ff.c **** - 670:../../../Source/third_party/fatfs/src/ff.c **** if (i == _FS_LOCK) { /* Not opened. Register it as new. */ - 671:../../../Source/third_party/fatfs/src/ff.c **** for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; - 672:../../../Source/third_party/fatfs/src/ff.c **** if (i == _FS_LOCK) return 0; /* No space to register (int err) */ - 673:../../../Source/third_party/fatfs/src/ff.c **** Files[i].fs = dj->fs; - 674:../../../Source/third_party/fatfs/src/ff.c **** Files[i].clu = dj->sclust; - 675:../../../Source/third_party/fatfs/src/ff.c **** Files[i].idx = dj->index; - 676:../../../Source/third_party/fatfs/src/ff.c **** Files[i].ctr = 0; - 677:../../../Source/third_party/fatfs/src/ff.c **** } - 678:../../../Source/third_party/fatfs/src/ff.c **** - 679:../../../Source/third_party/fatfs/src/ff.c **** if (acc && Files[i].ctr) return 0; /* Access violation (int err) */ - 680:../../../Source/third_party/fatfs/src/ff.c **** - 681:../../../Source/third_party/fatfs/src/ff.c **** Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ - 682:../../../Source/third_party/fatfs/src/ff.c **** - 683:../../../Source/third_party/fatfs/src/ff.c **** return i + 1; - 684:../../../Source/third_party/fatfs/src/ff.c **** } - 685:../../../Source/third_party/fatfs/src/ff.c **** - 686:../../../Source/third_party/fatfs/src/ff.c **** - 687:../../../Source/third_party/fatfs/src/ff.c **** static - 688:../../../Source/third_party/fatfs/src/ff.c **** FRESULT dec_lock ( /* Decrement file open counter */ - 689:../../../Source/third_party/fatfs/src/ff.c **** UINT i /* Semaphore index */ - 690:../../../Source/third_party/fatfs/src/ff.c **** ) - 691:../../../Source/third_party/fatfs/src/ff.c **** { - 692:../../../Source/third_party/fatfs/src/ff.c **** WORD n; - 693:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 694:../../../Source/third_party/fatfs/src/ff.c **** - 695:../../../Source/third_party/fatfs/src/ff.c **** - 696:../../../Source/third_party/fatfs/src/ff.c **** if (--i < _FS_LOCK) { - 697:../../../Source/third_party/fatfs/src/ff.c **** n = Files[i].ctr; - 698:../../../Source/third_party/fatfs/src/ff.c **** if (n == 0x100) n = 0; - 699:../../../Source/third_party/fatfs/src/ff.c **** if (n) n--; - 700:../../../Source/third_party/fatfs/src/ff.c **** Files[i].ctr = n; - 701:../../../Source/third_party/fatfs/src/ff.c **** if (!n) Files[i].fs = 0; - 702:../../../Source/third_party/fatfs/src/ff.c **** res = FR_OK; - 703:../../../Source/third_party/fatfs/src/ff.c **** } else { - 704:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INT_ERR; - 705:../../../Source/third_party/fatfs/src/ff.c **** } - 706:../../../Source/third_party/fatfs/src/ff.c **** return res; - 707:../../../Source/third_party/fatfs/src/ff.c **** } - 708:../../../Source/third_party/fatfs/src/ff.c **** - 709:../../../Source/third_party/fatfs/src/ff.c **** - 710:../../../Source/third_party/fatfs/src/ff.c **** static - 711:../../../Source/third_party/fatfs/src/ff.c **** void clear_lock ( /* Clear lock entries of the volume */ - 712:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs - 713:../../../Source/third_party/fatfs/src/ff.c **** ) - 714:../../../Source/third_party/fatfs/src/ff.c **** { - 715:../../../Source/third_party/fatfs/src/ff.c **** UINT i; - 716:../../../Source/third_party/fatfs/src/ff.c **** - 717:../../../Source/third_party/fatfs/src/ff.c **** for (i = 0; i < _FS_LOCK; i++) { - 718:../../../Source/third_party/fatfs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; - 719:../../../Source/third_party/fatfs/src/ff.c **** } - 720:../../../Source/third_party/fatfs/src/ff.c **** } - 721:../../../Source/third_party/fatfs/src/ff.c **** #endif - 722:../../../Source/third_party/fatfs/src/ff.c **** - 723:../../../Source/third_party/fatfs/src/ff.c **** - 724:../../../Source/third_party/fatfs/src/ff.c **** - 725:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 726:../../../Source/third_party/fatfs/src/ff.c **** /* Move/Flush disk access window */ - 727:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 728:../../../Source/third_party/fatfs/src/ff.c **** - 729:../../../Source/third_party/fatfs/src/ff.c **** - 730:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY - 731:../../../Source/third_party/fatfs/src/ff.c **** static - 732:../../../Source/third_party/fatfs/src/ff.c **** FRESULT sync_window ( - 733:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs /* File system object */ - 734:../../../Source/third_party/fatfs/src/ff.c **** ) - 735:../../../Source/third_party/fatfs/src/ff.c **** { - 736:../../../Source/third_party/fatfs/src/ff.c **** DWORD wsect; - 737:../../../Source/third_party/fatfs/src/ff.c **** UINT nf; - 738:../../../Source/third_party/fatfs/src/ff.c **** - 739:../../../Source/third_party/fatfs/src/ff.c **** - 740:../../../Source/third_party/fatfs/src/ff.c **** if (fs->wflag) { /* Write back the sector if it is dirty */ - 741:../../../Source/third_party/fatfs/src/ff.c **** wsect = fs->winsect; /* Current sector number */ - 742:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) - 743:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; - 744:../../../Source/third_party/fatfs/src/ff.c **** fs->wflag = 0; - 745:../../../Source/third_party/fatfs/src/ff.c **** if (wsect >= fs->fatbase && wsect < (fs->fatbase + fs->fsize)) { /* In FAT area? */ - 746:../../../Source/third_party/fatfs/src/ff.c **** for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ - 747:../../../Source/third_party/fatfs/src/ff.c **** wsect += fs->fsize; - 748:../../../Source/third_party/fatfs/src/ff.c **** disk_write(fs->drv, fs->win, wsect, 1); - 749:../../../Source/third_party/fatfs/src/ff.c **** } - 750:../../../Source/third_party/fatfs/src/ff.c **** } - 751:../../../Source/third_party/fatfs/src/ff.c **** } - 752:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; - 753:../../../Source/third_party/fatfs/src/ff.c **** } - 754:../../../Source/third_party/fatfs/src/ff.c **** #endif - 755:../../../Source/third_party/fatfs/src/ff.c **** - 756:../../../Source/third_party/fatfs/src/ff.c **** - 757:../../../Source/third_party/fatfs/src/ff.c **** static - 758:../../../Source/third_party/fatfs/src/ff.c **** FRESULT move_window ( - 759:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs, /* File system object */ - 760:../../../Source/third_party/fatfs/src/ff.c **** DWORD sector /* Sector number to make appearance in the fs->win[] */ - 761:../../../Source/third_party/fatfs/src/ff.c **** ) - 762:../../../Source/third_party/fatfs/src/ff.c **** { - 763:../../../Source/third_party/fatfs/src/ff.c **** if (sector != fs->winsect) { /* Changed current window */ - 764:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY - 765:../../../Source/third_party/fatfs/src/ff.c **** if (sync_window(fs) != FR_OK) - 766:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; - 767:../../../Source/third_party/fatfs/src/ff.c **** #endif - 768:../../../Source/third_party/fatfs/src/ff.c **** if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) - 769:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; - 770:../../../Source/third_party/fatfs/src/ff.c **** fs->winsect = sector; - 771:../../../Source/third_party/fatfs/src/ff.c **** } - 772:../../../Source/third_party/fatfs/src/ff.c **** - 773:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; - 774:../../../Source/third_party/fatfs/src/ff.c **** } - 775:../../../Source/third_party/fatfs/src/ff.c **** - 776:../../../Source/third_party/fatfs/src/ff.c **** - 777:../../../Source/third_party/fatfs/src/ff.c **** - 778:../../../Source/third_party/fatfs/src/ff.c **** - 779:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 780:../../../Source/third_party/fatfs/src/ff.c **** /* Synchronize file system and strage device */ - 781:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 782:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY - 783:../../../Source/third_party/fatfs/src/ff.c **** static - 784:../../../Source/third_party/fatfs/src/ff.c **** FRESULT sync_fs ( /* FR_OK: successful, FR_DISK_ERR: failed */ - 785:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs /* File system object */ - 786:../../../Source/third_party/fatfs/src/ff.c **** ) - 787:../../../Source/third_party/fatfs/src/ff.c **** { - 788:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 789:../../../Source/third_party/fatfs/src/ff.c **** - 790:../../../Source/third_party/fatfs/src/ff.c **** - 791:../../../Source/third_party/fatfs/src/ff.c **** res = sync_window(fs); - 792:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 793:../../../Source/third_party/fatfs/src/ff.c **** /* Update FSInfo sector if needed */ - 794:../../../Source/third_party/fatfs/src/ff.c **** if (fs->fs_type == FS_FAT32 && fs->fsi_flag) { - 795:../../../Source/third_party/fatfs/src/ff.c **** fs->winsect = 0; - 796:../../../Source/third_party/fatfs/src/ff.c **** /* Create FSInfo structure */ - 797:../../../Source/third_party/fatfs/src/ff.c **** mem_set(fs->win, 0, 512); - 798:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(fs->win+BS_55AA, 0xAA55); - 799:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(fs->win+FSI_LeadSig, 0x41615252); - 800:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(fs->win+FSI_StrucSig, 0x61417272); - 801:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust); - 802:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust); - 803:../../../Source/third_party/fatfs/src/ff.c **** /* Write it into the FSInfo sector */ - 804:../../../Source/third_party/fatfs/src/ff.c **** disk_write(fs->drv, fs->win, fs->fsi_sector, 1); - 805:../../../Source/third_party/fatfs/src/ff.c **** fs->fsi_flag = 0; - 806:../../../Source/third_party/fatfs/src/ff.c **** } - 807:../../../Source/third_party/fatfs/src/ff.c **** /* Make sure that no pending write process in the physical drive */ - 808:../../../Source/third_party/fatfs/src/ff.c **** if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) - 809:../../../Source/third_party/fatfs/src/ff.c **** res = FR_DISK_ERR; - 810:../../../Source/third_party/fatfs/src/ff.c **** } - 811:../../../Source/third_party/fatfs/src/ff.c **** - 812:../../../Source/third_party/fatfs/src/ff.c **** return res; - 813:../../../Source/third_party/fatfs/src/ff.c **** } - 814:../../../Source/third_party/fatfs/src/ff.c **** #endif - 815:../../../Source/third_party/fatfs/src/ff.c **** - 816:../../../Source/third_party/fatfs/src/ff.c **** - 817:../../../Source/third_party/fatfs/src/ff.c **** - 818:../../../Source/third_party/fatfs/src/ff.c **** - 819:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 820:../../../Source/third_party/fatfs/src/ff.c **** /* Get sector# from cluster# */ - 821:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 822:../../../Source/third_party/fatfs/src/ff.c **** - 823:../../../Source/third_party/fatfs/src/ff.c **** - 824:../../../Source/third_party/fatfs/src/ff.c **** DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ - 825:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs, /* File system object */ - 826:../../../Source/third_party/fatfs/src/ff.c **** DWORD clst /* Cluster# to be converted */ - 827:../../../Source/third_party/fatfs/src/ff.c **** ) - 828:../../../Source/third_party/fatfs/src/ff.c **** { - 829:../../../Source/third_party/fatfs/src/ff.c **** clst -= 2; - 830:../../../Source/third_party/fatfs/src/ff.c **** if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */ - 831:../../../Source/third_party/fatfs/src/ff.c **** return clst * fs->csize + fs->database; - 832:../../../Source/third_party/fatfs/src/ff.c **** } - 833:../../../Source/third_party/fatfs/src/ff.c **** - 834:../../../Source/third_party/fatfs/src/ff.c **** - 835:../../../Source/third_party/fatfs/src/ff.c **** - 836:../../../Source/third_party/fatfs/src/ff.c **** - 837:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 838:../../../Source/third_party/fatfs/src/ff.c **** /* FAT access - Read value of a FAT entry */ - 839:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 840:../../../Source/third_party/fatfs/src/ff.c **** - 841:../../../Source/third_party/fatfs/src/ff.c **** - 842:../../../Source/third_party/fatfs/src/ff.c **** DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */ - 843:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs, /* File system object */ - 844:../../../Source/third_party/fatfs/src/ff.c **** DWORD clst /* Cluster# to get the link information */ - 845:../../../Source/third_party/fatfs/src/ff.c **** ) - 846:../../../Source/third_party/fatfs/src/ff.c **** { - 847:../../../Source/third_party/fatfs/src/ff.c **** UINT wc, bc; - 848:../../../Source/third_party/fatfs/src/ff.c **** BYTE *p; - 849:../../../Source/third_party/fatfs/src/ff.c **** - 850:../../../Source/third_party/fatfs/src/ff.c **** - 851:../../../Source/third_party/fatfs/src/ff.c **** if (clst < 2 || clst >= fs->n_fatent) /* Check range */ - 852:../../../Source/third_party/fatfs/src/ff.c **** return 1; - 853:../../../Source/third_party/fatfs/src/ff.c **** - 854:../../../Source/third_party/fatfs/src/ff.c **** switch (fs->fs_type) { - 855:../../../Source/third_party/fatfs/src/ff.c **** case FS_FAT12 : - 856:../../../Source/third_party/fatfs/src/ff.c **** bc = (UINT)clst; bc += bc / 2; - 857:../../../Source/third_party/fatfs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; - 858:../../../Source/third_party/fatfs/src/ff.c **** wc = fs->win[bc % SS(fs)]; bc++; - 859:../../../Source/third_party/fatfs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; - 860:../../../Source/third_party/fatfs/src/ff.c **** wc |= fs->win[bc % SS(fs)] << 8; - 861:../../../Source/third_party/fatfs/src/ff.c **** return (clst & 1) ? (wc >> 4) : (wc & 0xFFF); - 862:../../../Source/third_party/fatfs/src/ff.c **** - 863:../../../Source/third_party/fatfs/src/ff.c **** case FS_FAT16 : - 864:../../../Source/third_party/fatfs/src/ff.c **** if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break; - 865:../../../Source/third_party/fatfs/src/ff.c **** p = &fs->win[clst * 2 % SS(fs)]; - 866:../../../Source/third_party/fatfs/src/ff.c **** return LD_WORD(p); - 867:../../../Source/third_party/fatfs/src/ff.c **** - 868:../../../Source/third_party/fatfs/src/ff.c **** case FS_FAT32 : - 869:../../../Source/third_party/fatfs/src/ff.c **** if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break; - 870:../../../Source/third_party/fatfs/src/ff.c **** p = &fs->win[clst * 4 % SS(fs)]; - 871:../../../Source/third_party/fatfs/src/ff.c **** return LD_DWORD(p) & 0x0FFFFFFF; - 872:../../../Source/third_party/fatfs/src/ff.c **** } - 873:../../../Source/third_party/fatfs/src/ff.c **** - 874:../../../Source/third_party/fatfs/src/ff.c **** return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */ - 875:../../../Source/third_party/fatfs/src/ff.c **** } - 876:../../../Source/third_party/fatfs/src/ff.c **** - 877:../../../Source/third_party/fatfs/src/ff.c **** - 878:../../../Source/third_party/fatfs/src/ff.c **** - 879:../../../Source/third_party/fatfs/src/ff.c **** - 880:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 881:../../../Source/third_party/fatfs/src/ff.c **** /* FAT access - Change value of a FAT entry */ - 882:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 883:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY - 884:../../../Source/third_party/fatfs/src/ff.c **** - 885:../../../Source/third_party/fatfs/src/ff.c **** FRESULT put_fat ( - 886:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs, /* File system object */ - 887:../../../Source/third_party/fatfs/src/ff.c **** DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */ - 888:../../../Source/third_party/fatfs/src/ff.c **** DWORD val /* New value to mark the cluster */ - 889:../../../Source/third_party/fatfs/src/ff.c **** ) - 890:../../../Source/third_party/fatfs/src/ff.c **** { - 891:../../../Source/third_party/fatfs/src/ff.c **** UINT bc; - 892:../../../Source/third_party/fatfs/src/ff.c **** BYTE *p; - 893:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 894:../../../Source/third_party/fatfs/src/ff.c **** - 895:../../../Source/third_party/fatfs/src/ff.c **** - 896:../../../Source/third_party/fatfs/src/ff.c **** if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ - 897:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INT_ERR; - 898:../../../Source/third_party/fatfs/src/ff.c **** - 899:../../../Source/third_party/fatfs/src/ff.c **** } else { - 900:../../../Source/third_party/fatfs/src/ff.c **** switch (fs->fs_type) { - 901:../../../Source/third_party/fatfs/src/ff.c **** case FS_FAT12 : - 902:../../../Source/third_party/fatfs/src/ff.c **** bc = (UINT)clst; bc += bc / 2; - 903:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(fs, fs->fatbase + (bc / SS(fs))); - 904:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 905:../../../Source/third_party/fatfs/src/ff.c **** p = &fs->win[bc % SS(fs)]; - 906:../../../Source/third_party/fatfs/src/ff.c **** *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; - 907:../../../Source/third_party/fatfs/src/ff.c **** bc++; - 908:../../../Source/third_party/fatfs/src/ff.c **** fs->wflag = 1; - 909:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(fs, fs->fatbase + (bc / SS(fs))); - 910:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 911:../../../Source/third_party/fatfs/src/ff.c **** p = &fs->win[bc % SS(fs)]; - 912:../../../Source/third_party/fatfs/src/ff.c **** *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); - 913:../../../Source/third_party/fatfs/src/ff.c **** break; - 914:../../../Source/third_party/fatfs/src/ff.c **** - 915:../../../Source/third_party/fatfs/src/ff.c **** case FS_FAT16 : - 916:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); - 917:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 918:../../../Source/third_party/fatfs/src/ff.c **** p = &fs->win[clst * 2 % SS(fs)]; - 919:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(p, (WORD)val); - 920:../../../Source/third_party/fatfs/src/ff.c **** break; - 921:../../../Source/third_party/fatfs/src/ff.c **** - 922:../../../Source/third_party/fatfs/src/ff.c **** case FS_FAT32 : - 923:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); - 924:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 925:../../../Source/third_party/fatfs/src/ff.c **** p = &fs->win[clst * 4 % SS(fs)]; - 926:../../../Source/third_party/fatfs/src/ff.c **** val |= LD_DWORD(p) & 0xF0000000; - 927:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(p, val); - 928:../../../Source/third_party/fatfs/src/ff.c **** break; - 929:../../../Source/third_party/fatfs/src/ff.c **** - 930:../../../Source/third_party/fatfs/src/ff.c **** default : - 931:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INT_ERR; - 932:../../../Source/third_party/fatfs/src/ff.c **** } - 933:../../../Source/third_party/fatfs/src/ff.c **** fs->wflag = 1; - 934:../../../Source/third_party/fatfs/src/ff.c **** } - 935:../../../Source/third_party/fatfs/src/ff.c **** - 936:../../../Source/third_party/fatfs/src/ff.c **** return res; - 937:../../../Source/third_party/fatfs/src/ff.c **** } - 938:../../../Source/third_party/fatfs/src/ff.c **** #endif /* !_FS_READONLY */ - 939:../../../Source/third_party/fatfs/src/ff.c **** - 940:../../../Source/third_party/fatfs/src/ff.c **** - 941:../../../Source/third_party/fatfs/src/ff.c **** - 942:../../../Source/third_party/fatfs/src/ff.c **** - 943:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 944:../../../Source/third_party/fatfs/src/ff.c **** /* FAT handling - Remove a cluster chain */ - 945:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 946:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY - 947:../../../Source/third_party/fatfs/src/ff.c **** static - 948:../../../Source/third_party/fatfs/src/ff.c **** FRESULT remove_chain ( - 949:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs, /* File system object */ - 950:../../../Source/third_party/fatfs/src/ff.c **** DWORD clst /* Cluster# to remove a chain from */ - 951:../../../Source/third_party/fatfs/src/ff.c **** ) - 952:../../../Source/third_party/fatfs/src/ff.c **** { - 953:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 954:../../../Source/third_party/fatfs/src/ff.c **** DWORD nxt; - 955:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_ERASE - 956:../../../Source/third_party/fatfs/src/ff.c **** DWORD scl = clst, ecl = clst, rt[2]; - 957:../../../Source/third_party/fatfs/src/ff.c **** #endif - 958:../../../Source/third_party/fatfs/src/ff.c **** - 959:../../../Source/third_party/fatfs/src/ff.c **** if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ - 960:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INT_ERR; - 961:../../../Source/third_party/fatfs/src/ff.c **** - 962:../../../Source/third_party/fatfs/src/ff.c **** } else { - 963:../../../Source/third_party/fatfs/src/ff.c **** res = FR_OK; - 964:../../../Source/third_party/fatfs/src/ff.c **** while (clst < fs->n_fatent) { /* Not a last link? */ - 965:../../../Source/third_party/fatfs/src/ff.c **** nxt = get_fat(fs, clst); /* Get cluster status */ - 966:../../../Source/third_party/fatfs/src/ff.c **** if (nxt == 0) break; /* Empty cluster? */ - 967:../../../Source/third_party/fatfs/src/ff.c **** if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */ - 968:../../../Source/third_party/fatfs/src/ff.c **** if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ - 969:../../../Source/third_party/fatfs/src/ff.c **** res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ - 970:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 971:../../../Source/third_party/fatfs/src/ff.c **** if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */ - 972:../../../Source/third_party/fatfs/src/ff.c **** fs->free_clust++; - 973:../../../Source/third_party/fatfs/src/ff.c **** fs->fsi_flag = 1; - 974:../../../Source/third_party/fatfs/src/ff.c **** } - 975:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_ERASE - 976:../../../Source/third_party/fatfs/src/ff.c **** if (ecl + 1 == nxt) { /* Is next cluster contiguous? */ - 977:../../../Source/third_party/fatfs/src/ff.c **** ecl = nxt; - 978:../../../Source/third_party/fatfs/src/ff.c **** } else { /* End of contiguous clusters */ - 979:../../../Source/third_party/fatfs/src/ff.c **** rt[0] = clust2sect(fs, scl); /* Start sector */ - 980:../../../Source/third_party/fatfs/src/ff.c **** rt[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */ - 981:../../../Source/third_party/fatfs/src/ff.c **** disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, rt); /* Erase the block */ - 982:../../../Source/third_party/fatfs/src/ff.c **** scl = ecl = nxt; - 983:../../../Source/third_party/fatfs/src/ff.c **** } - 984:../../../Source/third_party/fatfs/src/ff.c **** #endif - 985:../../../Source/third_party/fatfs/src/ff.c **** clst = nxt; /* Next cluster */ - 986:../../../Source/third_party/fatfs/src/ff.c **** } - 987:../../../Source/third_party/fatfs/src/ff.c **** } - 988:../../../Source/third_party/fatfs/src/ff.c **** - 989:../../../Source/third_party/fatfs/src/ff.c **** return res; - 990:../../../Source/third_party/fatfs/src/ff.c **** } - 991:../../../Source/third_party/fatfs/src/ff.c **** #endif - 992:../../../Source/third_party/fatfs/src/ff.c **** - 993:../../../Source/third_party/fatfs/src/ff.c **** - 994:../../../Source/third_party/fatfs/src/ff.c **** - 995:../../../Source/third_party/fatfs/src/ff.c **** - 996:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 997:../../../Source/third_party/fatfs/src/ff.c **** /* FAT handling - Stretch or Create a cluster chain */ - 998:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ - 999:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -1000:../../../Source/third_party/fatfs/src/ff.c **** static -1001:../../../Source/third_party/fatfs/src/ff.c **** DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster -1002:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs, /* File system object */ -1003:../../../Source/third_party/fatfs/src/ff.c **** DWORD clst /* Cluster# to stretch. 0 means create a new chain. */ -1004:../../../Source/third_party/fatfs/src/ff.c **** ) -1005:../../../Source/third_party/fatfs/src/ff.c **** { -1006:../../../Source/third_party/fatfs/src/ff.c **** DWORD cs, ncl, scl; -1007:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -1008:../../../Source/third_party/fatfs/src/ff.c **** -1009:../../../Source/third_party/fatfs/src/ff.c **** -1010:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0) { /* Create a new chain */ -1011:../../../Source/third_party/fatfs/src/ff.c **** scl = fs->last_clust; /* Get suggested start point */ -1012:../../../Source/third_party/fatfs/src/ff.c **** if (!scl || scl >= fs->n_fatent) scl = 1; -1013:../../../Source/third_party/fatfs/src/ff.c **** } -1014:../../../Source/third_party/fatfs/src/ff.c **** else { /* Stretch the current chain */ -1015:../../../Source/third_party/fatfs/src/ff.c **** cs = get_fat(fs, clst); /* Check the cluster status */ -1016:../../../Source/third_party/fatfs/src/ff.c **** if (cs < 2) return 1; /* It is an invalid cluster */ -1017:../../../Source/third_party/fatfs/src/ff.c **** if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ -1018:../../../Source/third_party/fatfs/src/ff.c **** scl = clst; -1019:../../../Source/third_party/fatfs/src/ff.c **** } -1020:../../../Source/third_party/fatfs/src/ff.c **** -1021:../../../Source/third_party/fatfs/src/ff.c **** ncl = scl; /* Start cluster */ -1022:../../../Source/third_party/fatfs/src/ff.c **** for (;;) { -1023:../../../Source/third_party/fatfs/src/ff.c **** ncl++; /* Next cluster */ -1024:../../../Source/third_party/fatfs/src/ff.c **** if (ncl >= fs->n_fatent) { /* Wrap around */ -1025:../../../Source/third_party/fatfs/src/ff.c **** ncl = 2; -1026:../../../Source/third_party/fatfs/src/ff.c **** if (ncl > scl) return 0; /* No free cluster */ -1027:../../../Source/third_party/fatfs/src/ff.c **** } -1028:../../../Source/third_party/fatfs/src/ff.c **** cs = get_fat(fs, ncl); /* Get the cluster status */ -1029:../../../Source/third_party/fatfs/src/ff.c **** if (cs == 0) break; /* Found a free cluster */ -1030:../../../Source/third_party/fatfs/src/ff.c **** if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */ -1031:../../../Source/third_party/fatfs/src/ff.c **** return cs; -1032:../../../Source/third_party/fatfs/src/ff.c **** if (ncl == scl) return 0; /* No free cluster */ -1033:../../../Source/third_party/fatfs/src/ff.c **** } -1034:../../../Source/third_party/fatfs/src/ff.c **** -1035:../../../Source/third_party/fatfs/src/ff.c **** res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */ -1036:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK && clst != 0) { -1037:../../../Source/third_party/fatfs/src/ff.c **** res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */ -1038:../../../Source/third_party/fatfs/src/ff.c **** } -1039:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -1040:../../../Source/third_party/fatfs/src/ff.c **** fs->last_clust = ncl; /* Update FSINFO */ -1041:../../../Source/third_party/fatfs/src/ff.c **** if (fs->free_clust != 0xFFFFFFFF) { -1042:../../../Source/third_party/fatfs/src/ff.c **** fs->free_clust--; -1043:../../../Source/third_party/fatfs/src/ff.c **** fs->fsi_flag = 1; -1044:../../../Source/third_party/fatfs/src/ff.c **** } -1045:../../../Source/third_party/fatfs/src/ff.c **** } else { -1046:../../../Source/third_party/fatfs/src/ff.c **** ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; -1047:../../../Source/third_party/fatfs/src/ff.c **** } -1048:../../../Source/third_party/fatfs/src/ff.c **** -1049:../../../Source/third_party/fatfs/src/ff.c **** return ncl; /* Return new cluster number or error code */ -1050:../../../Source/third_party/fatfs/src/ff.c **** } -1051:../../../Source/third_party/fatfs/src/ff.c **** #endif /* !_FS_READONLY */ -1052:../../../Source/third_party/fatfs/src/ff.c **** -1053:../../../Source/third_party/fatfs/src/ff.c **** -1054:../../../Source/third_party/fatfs/src/ff.c **** -1055:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1056:../../../Source/third_party/fatfs/src/ff.c **** /* FAT handling - Convert offset into cluster with link map table */ -1057:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1058:../../../Source/third_party/fatfs/src/ff.c **** -1059:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_FASTSEEK -1060:../../../Source/third_party/fatfs/src/ff.c **** static -1061:../../../Source/third_party/fatfs/src/ff.c **** DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ -1062:../../../Source/third_party/fatfs/src/ff.c **** FIL* fp, /* Pointer to the file object */ -1063:../../../Source/third_party/fatfs/src/ff.c **** DWORD ofs /* File offset to be converted to cluster# */ -1064:../../../Source/third_party/fatfs/src/ff.c **** ) -1065:../../../Source/third_party/fatfs/src/ff.c **** { -1066:../../../Source/third_party/fatfs/src/ff.c **** DWORD cl, ncl, *tbl; -1067:../../../Source/third_party/fatfs/src/ff.c **** -1068:../../../Source/third_party/fatfs/src/ff.c **** -1069:../../../Source/third_party/fatfs/src/ff.c **** tbl = fp->cltbl + 1; /* Top of CLMT */ -1070:../../../Source/third_party/fatfs/src/ff.c **** cl = ofs / SS(fp->fs) / fp->fs->csize; /* Cluster order from top of the file */ -1071:../../../Source/third_party/fatfs/src/ff.c **** for (;;) { -1072:../../../Source/third_party/fatfs/src/ff.c **** ncl = *tbl++; /* Number of cluters in the fragment */ -1073:../../../Source/third_party/fatfs/src/ff.c **** if (!ncl) return 0; /* End of table? (error) */ -1074:../../../Source/third_party/fatfs/src/ff.c **** if (cl < ncl) break; /* In this fragment? */ -1075:../../../Source/third_party/fatfs/src/ff.c **** cl -= ncl; tbl++; /* Next fragment */ -1076:../../../Source/third_party/fatfs/src/ff.c **** } -1077:../../../Source/third_party/fatfs/src/ff.c **** return cl + *tbl; /* Return the cluster number */ -1078:../../../Source/third_party/fatfs/src/ff.c **** } -1079:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _USE_FASTSEEK */ -1080:../../../Source/third_party/fatfs/src/ff.c **** -1081:../../../Source/third_party/fatfs/src/ff.c **** -1082:../../../Source/third_party/fatfs/src/ff.c **** -1083:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1084:../../../Source/third_party/fatfs/src/ff.c **** /* Directory handling - Set directory index */ -1085:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1086:../../../Source/third_party/fatfs/src/ff.c **** -1087:../../../Source/third_party/fatfs/src/ff.c **** static -1088:../../../Source/third_party/fatfs/src/ff.c **** FRESULT dir_sdi ( -1089:../../../Source/third_party/fatfs/src/ff.c **** DIR *dj, /* Pointer to directory object */ -1090:../../../Source/third_party/fatfs/src/ff.c **** WORD idx /* Index of directory table */ -1091:../../../Source/third_party/fatfs/src/ff.c **** ) -1092:../../../Source/third_party/fatfs/src/ff.c **** { -1093:../../../Source/third_party/fatfs/src/ff.c **** DWORD clst; -1094:../../../Source/third_party/fatfs/src/ff.c **** WORD ic; -1095:../../../Source/third_party/fatfs/src/ff.c **** -1096:../../../Source/third_party/fatfs/src/ff.c **** -1097:../../../Source/third_party/fatfs/src/ff.c **** dj->index = idx; -1098:../../../Source/third_party/fatfs/src/ff.c **** clst = dj->sclust; -1099:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 1 || clst >= dj->fs->n_fatent) /* Check start cluster range */ -1100:../../../Source/third_party/fatfs/src/ff.c **** return FR_INT_ERR; -1101:../../../Source/third_party/fatfs/src/ff.c **** if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */ -1102:../../../Source/third_party/fatfs/src/ff.c **** clst = dj->fs->dirbase; -1103:../../../Source/third_party/fatfs/src/ff.c **** -1104:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0) { /* Static table (root-dir in FAT12/16) */ -1105:../../../Source/third_party/fatfs/src/ff.c **** dj->clust = clst; -1106:../../../Source/third_party/fatfs/src/ff.c **** if (idx >= dj->fs->n_rootdir) /* Index is out of range */ -1107:../../../Source/third_party/fatfs/src/ff.c **** return FR_INT_ERR; -1108:../../../Source/third_party/fatfs/src/ff.c **** dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */ -1109:../../../Source/third_party/fatfs/src/ff.c **** } -1110:../../../Source/third_party/fatfs/src/ff.c **** else { /* Dynamic table (sub-dirs or root-dir in FAT32) */ -1111:../../../Source/third_party/fatfs/src/ff.c **** ic = SS(dj->fs) / SZ_DIR * dj->fs->csize; /* Entries per cluster */ -1112:../../../Source/third_party/fatfs/src/ff.c **** while (idx >= ic) { /* Follow cluster chain */ -1113:../../../Source/third_party/fatfs/src/ff.c **** clst = get_fat(dj->fs, clst); /* Get next cluster */ -1114:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ -1115:../../../Source/third_party/fatfs/src/ff.c **** if (clst < 2 || clst >= dj->fs->n_fatent) /* Reached to end of table or int error */ -1116:../../../Source/third_party/fatfs/src/ff.c **** return FR_INT_ERR; -1117:../../../Source/third_party/fatfs/src/ff.c **** idx -= ic; -1118:../../../Source/third_party/fatfs/src/ff.c **** } -1119:../../../Source/third_party/fatfs/src/ff.c **** dj->clust = clst; -1120:../../../Source/third_party/fatfs/src/ff.c **** dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */ -1121:../../../Source/third_party/fatfs/src/ff.c **** } -1122:../../../Source/third_party/fatfs/src/ff.c **** -1123:../../../Source/third_party/fatfs/src/ff.c **** dj->dir = dj->fs->win + (idx % (SS(dj->fs) / SZ_DIR)) * SZ_DIR; /* Ptr to the entry in the sector -1124:../../../Source/third_party/fatfs/src/ff.c **** -1125:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; /* Seek succeeded */ -1126:../../../Source/third_party/fatfs/src/ff.c **** } -1127:../../../Source/third_party/fatfs/src/ff.c **** -1128:../../../Source/third_party/fatfs/src/ff.c **** -1129:../../../Source/third_party/fatfs/src/ff.c **** -1130:../../../Source/third_party/fatfs/src/ff.c **** -1131:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1132:../../../Source/third_party/fatfs/src/ff.c **** /* Directory handling - Move directory table index next */ -1133:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1134:../../../Source/third_party/fatfs/src/ff.c **** -1135:../../../Source/third_party/fatfs/src/ff.c **** static -1136:../../../Source/third_party/fatfs/src/ff.c **** FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */ -1137:../../../Source/third_party/fatfs/src/ff.c **** DIR *dj, /* Pointer to the directory object */ -1138:../../../Source/third_party/fatfs/src/ff.c **** int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ -1139:../../../Source/third_party/fatfs/src/ff.c **** ) -1140:../../../Source/third_party/fatfs/src/ff.c **** { -1141:../../../Source/third_party/fatfs/src/ff.c **** DWORD clst; -1142:../../../Source/third_party/fatfs/src/ff.c **** WORD i; -1143:../../../Source/third_party/fatfs/src/ff.c **** -1144:../../../Source/third_party/fatfs/src/ff.c **** -1145:../../../Source/third_party/fatfs/src/ff.c **** stretch = stretch; /* To suppress warning on read-only cfg. */ -1146:../../../Source/third_party/fatfs/src/ff.c **** i = dj->index + 1; -1147:../../../Source/third_party/fatfs/src/ff.c **** if (!i || !dj->sect) /* Report EOT when index has reached 65535 */ -1148:../../../Source/third_party/fatfs/src/ff.c **** return FR_NO_FILE; -1149:../../../Source/third_party/fatfs/src/ff.c **** -1150:../../../Source/third_party/fatfs/src/ff.c **** if (!(i % (SS(dj->fs) / SZ_DIR))) { /* Sector changed? */ -1151:../../../Source/third_party/fatfs/src/ff.c **** dj->sect++; /* Next sector */ -1152:../../../Source/third_party/fatfs/src/ff.c **** -1153:../../../Source/third_party/fatfs/src/ff.c **** if (dj->clust == 0) { /* Static table */ -1154:../../../Source/third_party/fatfs/src/ff.c **** if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */ -1155:../../../Source/third_party/fatfs/src/ff.c **** return FR_NO_FILE; -1156:../../../Source/third_party/fatfs/src/ff.c **** } -1157:../../../Source/third_party/fatfs/src/ff.c **** else { /* Dynamic table */ -1158:../../../Source/third_party/fatfs/src/ff.c **** if (((i / (SS(dj->fs) / SZ_DIR)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */ -1159:../../../Source/third_party/fatfs/src/ff.c **** clst = get_fat(dj->fs, dj->clust); /* Get next cluster */ -1160:../../../Source/third_party/fatfs/src/ff.c **** if (clst <= 1) return FR_INT_ERR; -1161:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; -1162:../../../Source/third_party/fatfs/src/ff.c **** if (clst >= dj->fs->n_fatent) { /* When it reached end of dynamic table */ -1163:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -1164:../../../Source/third_party/fatfs/src/ff.c **** BYTE c; -1165:../../../Source/third_party/fatfs/src/ff.c **** if (!stretch) return FR_NO_FILE; /* When do not stretch, report EOT */ -1166:../../../Source/third_party/fatfs/src/ff.c **** clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */ -1167:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0) return FR_DENIED; /* No free cluster */ -1168:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 1) return FR_INT_ERR; -1169:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; -1170:../../../Source/third_party/fatfs/src/ff.c **** /* Clean-up stretched table */ -1171:../../../Source/third_party/fatfs/src/ff.c **** if (sync_window(dj->fs)) return FR_DISK_ERR; /* Flush active window */ -1172:../../../Source/third_party/fatfs/src/ff.c **** mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */ -1173:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */ -1174:../../../Source/third_party/fatfs/src/ff.c **** for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */ -1175:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->wflag = 1; -1176:../../../Source/third_party/fatfs/src/ff.c **** if (sync_window(dj->fs)) return FR_DISK_ERR; -1177:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->winsect++; -1178:../../../Source/third_party/fatfs/src/ff.c **** } -1179:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->winsect -= c; /* Rewind window address */ -1180:../../../Source/third_party/fatfs/src/ff.c **** #else -1181:../../../Source/third_party/fatfs/src/ff.c **** return FR_NO_FILE; /* Report EOT */ -1182:../../../Source/third_party/fatfs/src/ff.c **** #endif -1183:../../../Source/third_party/fatfs/src/ff.c **** } -1184:../../../Source/third_party/fatfs/src/ff.c **** dj->clust = clst; /* Initialize data for new cluster */ -1185:../../../Source/third_party/fatfs/src/ff.c **** dj->sect = clust2sect(dj->fs, clst); -1186:../../../Source/third_party/fatfs/src/ff.c **** } -1187:../../../Source/third_party/fatfs/src/ff.c **** } -1188:../../../Source/third_party/fatfs/src/ff.c **** } -1189:../../../Source/third_party/fatfs/src/ff.c **** -1190:../../../Source/third_party/fatfs/src/ff.c **** dj->index = i; -1191:../../../Source/third_party/fatfs/src/ff.c **** dj->dir = dj->fs->win + (i % (SS(dj->fs) / SZ_DIR)) * SZ_DIR; -1192:../../../Source/third_party/fatfs/src/ff.c **** -1193:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; -1194:../../../Source/third_party/fatfs/src/ff.c **** } -1195:../../../Source/third_party/fatfs/src/ff.c **** -1196:../../../Source/third_party/fatfs/src/ff.c **** -1197:../../../Source/third_party/fatfs/src/ff.c **** -1198:../../../Source/third_party/fatfs/src/ff.c **** -1199:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1200:../../../Source/third_party/fatfs/src/ff.c **** /* Directory handling - Reserve directory entry */ -1201:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1202:../../../Source/third_party/fatfs/src/ff.c **** -1203:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -1204:../../../Source/third_party/fatfs/src/ff.c **** static -1205:../../../Source/third_party/fatfs/src/ff.c **** FRESULT dir_alloc ( -1206:../../../Source/third_party/fatfs/src/ff.c **** DIR* dj, /* Pointer to the directory object */ -1207:../../../Source/third_party/fatfs/src/ff.c **** UINT nent /* Number of contiguous entries to allocate (1-21) */ -1208:../../../Source/third_party/fatfs/src/ff.c **** ) -1209:../../../Source/third_party/fatfs/src/ff.c **** { -1210:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -1211:../../../Source/third_party/fatfs/src/ff.c **** UINT n; -1212:../../../Source/third_party/fatfs/src/ff.c **** -1213:../../../Source/third_party/fatfs/src/ff.c **** -1214:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(dj, 0); -1215:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -1216:../../../Source/third_party/fatfs/src/ff.c **** n = 0; -1217:../../../Source/third_party/fatfs/src/ff.c **** do { -1218:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(dj->fs, dj->sect); -1219:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -1220:../../../Source/third_party/fatfs/src/ff.c **** if (dj->dir[0] == DDE || dj->dir[0] == 0) { /* Is it a blank entry? */ -1221:../../../Source/third_party/fatfs/src/ff.c **** if (++n == nent) break; /* A block of contiguous entry is found */ -1222:../../../Source/third_party/fatfs/src/ff.c **** } else { -1223:../../../Source/third_party/fatfs/src/ff.c **** n = 0; /* Not a blank entry. Restart to search */ -1224:../../../Source/third_party/fatfs/src/ff.c **** } -1225:../../../Source/third_party/fatfs/src/ff.c **** res = dir_next(dj, 1); /* Next entry with table stretch enabled */ -1226:../../../Source/third_party/fatfs/src/ff.c **** } while (res == FR_OK); -1227:../../../Source/third_party/fatfs/src/ff.c **** } -1228:../../../Source/third_party/fatfs/src/ff.c **** return res; -1229:../../../Source/third_party/fatfs/src/ff.c **** } -1230:../../../Source/third_party/fatfs/src/ff.c **** #endif -1231:../../../Source/third_party/fatfs/src/ff.c **** -1232:../../../Source/third_party/fatfs/src/ff.c **** -1233:../../../Source/third_party/fatfs/src/ff.c **** -1234:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1235:../../../Source/third_party/fatfs/src/ff.c **** /* Directory handling - Load/Store start cluster number */ -1236:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1237:../../../Source/third_party/fatfs/src/ff.c **** -1238:../../../Source/third_party/fatfs/src/ff.c **** static -1239:../../../Source/third_party/fatfs/src/ff.c **** DWORD ld_clust ( -1240:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs, /* Pointer to the fs object */ -1241:../../../Source/third_party/fatfs/src/ff.c **** BYTE *dir /* Pointer to the directory entry */ -1242:../../../Source/third_party/fatfs/src/ff.c **** ) -1243:../../../Source/third_party/fatfs/src/ff.c **** { - 60 .loc 1 1243 0 - 61 .cfi_startproc - 62 @ args = 0, pretend = 0, frame = 0 - 63 @ frame_needed = 0, uses_anonymous_args = 0 - 64 @ link register save eliminated. - 65 .LVL6: -1244:../../../Source/third_party/fatfs/src/ff.c **** DWORD cl; -1245:../../../Source/third_party/fatfs/src/ff.c **** -1246:../../../Source/third_party/fatfs/src/ff.c **** cl = LD_WORD(dir+DIR_FstClusLO); - 66 .loc 1 1246 0 - 67 0000 CA7E ldrb r2, [r1, #27] @ zero_extendqisi2 - 68 0002 8B7E ldrb r3, [r1, #26] @ zero_extendqisi2 - 69 0004 43EA0223 orr r3, r3, r2, lsl #8 - 70 .LVL7: -1247:../../../Source/third_party/fatfs/src/ff.c **** if (fs->fs_type == FS_FAT32) - 71 .loc 1 1247 0 - 72 0008 0278 ldrb r2, [r0] @ zero_extendqisi2 - 73 000a 032A cmp r2, #3 - 74 000c 05D1 bne .L6 -1248:../../../Source/third_party/fatfs/src/ff.c **** cl |= (DWORD)LD_WORD(dir+DIR_FstClusHI) << 16; - 75 .loc 1 1248 0 - 76 000e 487D ldrb r0, [r1, #21] @ zero_extendqisi2 - 77 .LVL8: - 78 0010 0A7D ldrb r2, [r1, #20] @ zero_extendqisi2 - 79 0012 42EA0022 orr r2, r2, r0, lsl #8 - 80 0016 43EA0243 orr r3, r3, r2, lsl #16 - 81 .LVL9: - 82 .L6: -1249:../../../Source/third_party/fatfs/src/ff.c **** -1250:../../../Source/third_party/fatfs/src/ff.c **** return cl; -1251:../../../Source/third_party/fatfs/src/ff.c **** } - 83 .loc 1 1251 0 - 84 001a 1846 mov r0, r3 - 85 001c 7047 bx lr - 86 .cfi_endproc - 87 .LFE15: - 89 001e 00BF .section .text.sum_sfn,"ax",%progbits - 90 .align 2 - 91 .thumb - 92 .thumb_func - 94 sum_sfn: - 95 .LFB21: -1252:../../../Source/third_party/fatfs/src/ff.c **** -1253:../../../Source/third_party/fatfs/src/ff.c **** -1254:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -1255:../../../Source/third_party/fatfs/src/ff.c **** static -1256:../../../Source/third_party/fatfs/src/ff.c **** void st_clust ( -1257:../../../Source/third_party/fatfs/src/ff.c **** BYTE *dir, /* Pointer to the directory entry */ -1258:../../../Source/third_party/fatfs/src/ff.c **** DWORD cl /* Value to be set */ -1259:../../../Source/third_party/fatfs/src/ff.c **** ) -1260:../../../Source/third_party/fatfs/src/ff.c **** { -1261:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+DIR_FstClusLO, cl); -1262:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+DIR_FstClusHI, cl >> 16); -1263:../../../Source/third_party/fatfs/src/ff.c **** } -1264:../../../Source/third_party/fatfs/src/ff.c **** #endif -1265:../../../Source/third_party/fatfs/src/ff.c **** -1266:../../../Source/third_party/fatfs/src/ff.c **** -1267:../../../Source/third_party/fatfs/src/ff.c **** -1268:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1269:../../../Source/third_party/fatfs/src/ff.c **** /* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */ -1270:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1271:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN -1272:../../../Source/third_party/fatfs/src/ff.c **** static -1273:../../../Source/third_party/fatfs/src/ff.c **** const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN chars in the directory -1274:../../../Source/third_party/fatfs/src/ff.c **** -1275:../../../Source/third_party/fatfs/src/ff.c **** -1276:../../../Source/third_party/fatfs/src/ff.c **** static -1277:../../../Source/third_party/fatfs/src/ff.c **** int cmp_lfn ( /* 1:Matched, 0:Not matched */ -1278:../../../Source/third_party/fatfs/src/ff.c **** WCHAR *lfnbuf, /* Pointer to the LFN to be compared */ -1279:../../../Source/third_party/fatfs/src/ff.c **** BYTE *dir /* Pointer to the directory entry containing a part of LFN */ -1280:../../../Source/third_party/fatfs/src/ff.c **** ) -1281:../../../Source/third_party/fatfs/src/ff.c **** { -1282:../../../Source/third_party/fatfs/src/ff.c **** UINT i, s; -1283:../../../Source/third_party/fatfs/src/ff.c **** WCHAR wc, uc; -1284:../../../Source/third_party/fatfs/src/ff.c **** -1285:../../../Source/third_party/fatfs/src/ff.c **** -1286:../../../Source/third_party/fatfs/src/ff.c **** i = ((dir[LDIR_Ord] & ~LLE) - 1) * 13; /* Get offset in the LFN buffer */ -1287:../../../Source/third_party/fatfs/src/ff.c **** s = 0; wc = 1; -1288:../../../Source/third_party/fatfs/src/ff.c **** do { -1289:../../../Source/third_party/fatfs/src/ff.c **** uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ -1290:../../../Source/third_party/fatfs/src/ff.c **** if (wc) { /* Last char has not been processed */ -1291:../../../Source/third_party/fatfs/src/ff.c **** wc = ff_wtoupper(uc); /* Convert it to upper case */ -1292:../../../Source/third_party/fatfs/src/ff.c **** if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */ -1293:../../../Source/third_party/fatfs/src/ff.c **** return 0; /* Not matched */ -1294:../../../Source/third_party/fatfs/src/ff.c **** } else { -1295:../../../Source/third_party/fatfs/src/ff.c **** if (uc != 0xFFFF) return 0; /* Check filler */ -1296:../../../Source/third_party/fatfs/src/ff.c **** } -1297:../../../Source/third_party/fatfs/src/ff.c **** } while (++s < 13); /* Repeat until all chars in the entry are checked */ -1298:../../../Source/third_party/fatfs/src/ff.c **** -1299:../../../Source/third_party/fatfs/src/ff.c **** if ((dir[LDIR_Ord] & LLE) && wc && lfnbuf[i]) /* Last segment matched but different length */ -1300:../../../Source/third_party/fatfs/src/ff.c **** return 0; -1301:../../../Source/third_party/fatfs/src/ff.c **** -1302:../../../Source/third_party/fatfs/src/ff.c **** return 1; /* The part of LFN matched */ -1303:../../../Source/third_party/fatfs/src/ff.c **** } -1304:../../../Source/third_party/fatfs/src/ff.c **** -1305:../../../Source/third_party/fatfs/src/ff.c **** -1306:../../../Source/third_party/fatfs/src/ff.c **** -1307:../../../Source/third_party/fatfs/src/ff.c **** static -1308:../../../Source/third_party/fatfs/src/ff.c **** int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */ -1309:../../../Source/third_party/fatfs/src/ff.c **** WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */ -1310:../../../Source/third_party/fatfs/src/ff.c **** BYTE *dir /* Pointer to the directory entry */ -1311:../../../Source/third_party/fatfs/src/ff.c **** ) -1312:../../../Source/third_party/fatfs/src/ff.c **** { -1313:../../../Source/third_party/fatfs/src/ff.c **** UINT i, s; -1314:../../../Source/third_party/fatfs/src/ff.c **** WCHAR wc, uc; -1315:../../../Source/third_party/fatfs/src/ff.c **** -1316:../../../Source/third_party/fatfs/src/ff.c **** -1317:../../../Source/third_party/fatfs/src/ff.c **** i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ -1318:../../../Source/third_party/fatfs/src/ff.c **** -1319:../../../Source/third_party/fatfs/src/ff.c **** s = 0; wc = 1; -1320:../../../Source/third_party/fatfs/src/ff.c **** do { -1321:../../../Source/third_party/fatfs/src/ff.c **** uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ -1322:../../../Source/third_party/fatfs/src/ff.c **** if (wc) { /* Last char has not been processed */ -1323:../../../Source/third_party/fatfs/src/ff.c **** if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ -1324:../../../Source/third_party/fatfs/src/ff.c **** lfnbuf[i++] = wc = uc; /* Store it */ -1325:../../../Source/third_party/fatfs/src/ff.c **** } else { -1326:../../../Source/third_party/fatfs/src/ff.c **** if (uc != 0xFFFF) return 0; /* Check filler */ -1327:../../../Source/third_party/fatfs/src/ff.c **** } -1328:../../../Source/third_party/fatfs/src/ff.c **** } while (++s < 13); /* Read all character in the entry */ -1329:../../../Source/third_party/fatfs/src/ff.c **** -1330:../../../Source/third_party/fatfs/src/ff.c **** if (dir[LDIR_Ord] & LLE) { /* Put terminator if it is the last LFN part */ -1331:../../../Source/third_party/fatfs/src/ff.c **** if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ -1332:../../../Source/third_party/fatfs/src/ff.c **** lfnbuf[i] = 0; -1333:../../../Source/third_party/fatfs/src/ff.c **** } -1334:../../../Source/third_party/fatfs/src/ff.c **** -1335:../../../Source/third_party/fatfs/src/ff.c **** return 1; -1336:../../../Source/third_party/fatfs/src/ff.c **** } -1337:../../../Source/third_party/fatfs/src/ff.c **** -1338:../../../Source/third_party/fatfs/src/ff.c **** -1339:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -1340:../../../Source/third_party/fatfs/src/ff.c **** static -1341:../../../Source/third_party/fatfs/src/ff.c **** void fit_lfn ( -1342:../../../Source/third_party/fatfs/src/ff.c **** const WCHAR *lfnbuf, /* Pointer to the LFN buffer */ -1343:../../../Source/third_party/fatfs/src/ff.c **** BYTE *dir, /* Pointer to the directory entry */ -1344:../../../Source/third_party/fatfs/src/ff.c **** BYTE ord, /* LFN order (1-20) */ -1345:../../../Source/third_party/fatfs/src/ff.c **** BYTE sum /* SFN sum */ -1346:../../../Source/third_party/fatfs/src/ff.c **** ) -1347:../../../Source/third_party/fatfs/src/ff.c **** { -1348:../../../Source/third_party/fatfs/src/ff.c **** UINT i, s; -1349:../../../Source/third_party/fatfs/src/ff.c **** WCHAR wc; -1350:../../../Source/third_party/fatfs/src/ff.c **** -1351:../../../Source/third_party/fatfs/src/ff.c **** -1352:../../../Source/third_party/fatfs/src/ff.c **** dir[LDIR_Chksum] = sum; /* Set check sum */ -1353:../../../Source/third_party/fatfs/src/ff.c **** dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ -1354:../../../Source/third_party/fatfs/src/ff.c **** dir[LDIR_Type] = 0; -1355:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+LDIR_FstClusLO, 0); -1356:../../../Source/third_party/fatfs/src/ff.c **** -1357:../../../Source/third_party/fatfs/src/ff.c **** i = (ord - 1) * 13; /* Get offset in the LFN buffer */ -1358:../../../Source/third_party/fatfs/src/ff.c **** s = wc = 0; -1359:../../../Source/third_party/fatfs/src/ff.c **** do { -1360:../../../Source/third_party/fatfs/src/ff.c **** if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */ -1361:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+LfnOfs[s], wc); /* Put it */ -1362:../../../Source/third_party/fatfs/src/ff.c **** if (!wc) wc = 0xFFFF; /* Padding chars following last char */ -1363:../../../Source/third_party/fatfs/src/ff.c **** } while (++s < 13); -1364:../../../Source/third_party/fatfs/src/ff.c **** if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLE; /* Bottom LFN part is the start of LFN sequence */ -1365:../../../Source/third_party/fatfs/src/ff.c **** dir[LDIR_Ord] = ord; /* Set the LFN order */ -1366:../../../Source/third_party/fatfs/src/ff.c **** } -1367:../../../Source/third_party/fatfs/src/ff.c **** -1368:../../../Source/third_party/fatfs/src/ff.c **** #endif -1369:../../../Source/third_party/fatfs/src/ff.c **** #endif -1370:../../../Source/third_party/fatfs/src/ff.c **** -1371:../../../Source/third_party/fatfs/src/ff.c **** -1372:../../../Source/third_party/fatfs/src/ff.c **** -1373:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1374:../../../Source/third_party/fatfs/src/ff.c **** /* Create numbered name */ -1375:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1376:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN -1377:../../../Source/third_party/fatfs/src/ff.c **** void gen_numname ( -1378:../../../Source/third_party/fatfs/src/ff.c **** BYTE *dst, /* Pointer to generated SFN */ -1379:../../../Source/third_party/fatfs/src/ff.c **** const BYTE *src, /* Pointer to source SFN to be modified */ -1380:../../../Source/third_party/fatfs/src/ff.c **** const WCHAR *lfn, /* Pointer to LFN */ -1381:../../../Source/third_party/fatfs/src/ff.c **** WORD seq /* Sequence number */ -1382:../../../Source/third_party/fatfs/src/ff.c **** ) -1383:../../../Source/third_party/fatfs/src/ff.c **** { -1384:../../../Source/third_party/fatfs/src/ff.c **** BYTE ns[8], c; -1385:../../../Source/third_party/fatfs/src/ff.c **** UINT i, j; -1386:../../../Source/third_party/fatfs/src/ff.c **** -1387:../../../Source/third_party/fatfs/src/ff.c **** -1388:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(dst, src, 11); -1389:../../../Source/third_party/fatfs/src/ff.c **** -1390:../../../Source/third_party/fatfs/src/ff.c **** if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */ -1391:../../../Source/third_party/fatfs/src/ff.c **** do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn); -1392:../../../Source/third_party/fatfs/src/ff.c **** } -1393:../../../Source/third_party/fatfs/src/ff.c **** -1394:../../../Source/third_party/fatfs/src/ff.c **** /* itoa (hexdecimal) */ -1395:../../../Source/third_party/fatfs/src/ff.c **** i = 7; -1396:../../../Source/third_party/fatfs/src/ff.c **** do { -1397:../../../Source/third_party/fatfs/src/ff.c **** c = (seq % 16) + '0'; -1398:../../../Source/third_party/fatfs/src/ff.c **** if (c > '9') c += 7; -1399:../../../Source/third_party/fatfs/src/ff.c **** ns[i--] = c; -1400:../../../Source/third_party/fatfs/src/ff.c **** seq /= 16; -1401:../../../Source/third_party/fatfs/src/ff.c **** } while (seq); -1402:../../../Source/third_party/fatfs/src/ff.c **** ns[i] = '~'; -1403:../../../Source/third_party/fatfs/src/ff.c **** -1404:../../../Source/third_party/fatfs/src/ff.c **** /* Append the number */ -1405:../../../Source/third_party/fatfs/src/ff.c **** for (j = 0; j < i && dst[j] != ' '; j++) { -1406:../../../Source/third_party/fatfs/src/ff.c **** if (IsDBCS1(dst[j])) { -1407:../../../Source/third_party/fatfs/src/ff.c **** if (j == i - 1) break; -1408:../../../Source/third_party/fatfs/src/ff.c **** j++; -1409:../../../Source/third_party/fatfs/src/ff.c **** } -1410:../../../Source/third_party/fatfs/src/ff.c **** } -1411:../../../Source/third_party/fatfs/src/ff.c **** do { -1412:../../../Source/third_party/fatfs/src/ff.c **** dst[j++] = (i < 8) ? ns[i++] : ' '; -1413:../../../Source/third_party/fatfs/src/ff.c **** } while (j < 8); -1414:../../../Source/third_party/fatfs/src/ff.c **** } -1415:../../../Source/third_party/fatfs/src/ff.c **** #endif -1416:../../../Source/third_party/fatfs/src/ff.c **** -1417:../../../Source/third_party/fatfs/src/ff.c **** -1418:../../../Source/third_party/fatfs/src/ff.c **** -1419:../../../Source/third_party/fatfs/src/ff.c **** -1420:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1421:../../../Source/third_party/fatfs/src/ff.c **** /* Calculate sum of an SFN */ -1422:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1423:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN -1424:../../../Source/third_party/fatfs/src/ff.c **** static -1425:../../../Source/third_party/fatfs/src/ff.c **** BYTE sum_sfn ( -1426:../../../Source/third_party/fatfs/src/ff.c **** const BYTE *dir /* Ptr to directory entry */ -1427:../../../Source/third_party/fatfs/src/ff.c **** ) -1428:../../../Source/third_party/fatfs/src/ff.c **** { - 96 .loc 1 1428 0 - 97 .cfi_startproc - 98 @ args = 0, pretend = 0, frame = 0 - 99 @ frame_needed = 0, uses_anonymous_args = 0 - 100 @ link register save eliminated. - 101 .LVL10: - 102 0000 00F10B01 add r1, r0, #11 -1429:../../../Source/third_party/fatfs/src/ff.c **** BYTE sum = 0; - 103 .loc 1 1429 0 - 104 0004 0023 movs r3, #0 - 105 .LVL11: - 106 .L8: -1430:../../../Source/third_party/fatfs/src/ff.c **** UINT n = 11; -1431:../../../Source/third_party/fatfs/src/ff.c **** -1432:../../../Source/third_party/fatfs/src/ff.c **** do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); - 107 .loc 1 1432 0 discriminator 1 - 108 0006 DA01 lsls r2, r3, #7 - 109 0008 42EA5303 orr r3, r2, r3, lsr #1 - 110 .LVL12: - 111 000c 10F8012B ldrb r2, [r0], #1 @ zero_extendqisi2 - 112 .LVL13: - 113 0010 1344 add r3, r3, r2 - 114 0012 03F0FF03 and r3, r3, #255 - 115 .LVL14: - 116 0016 8842 cmp r0, r1 - 117 0018 F5D1 bne .L8 -1433:../../../Source/third_party/fatfs/src/ff.c **** return sum; -1434:../../../Source/third_party/fatfs/src/ff.c **** } - 118 .loc 1 1434 0 - 119 001a 1846 mov r0, r3 - 120 .LVL15: - 121 001c 7047 bx lr - 122 .cfi_endproc - 123 .LFE21: - 125 001e 00BF .section .text.check_fs,"ax",%progbits - 126 .align 2 - 127 .thumb - 128 .thumb_func - 130 check_fs: - 131 .LFB29: -1435:../../../Source/third_party/fatfs/src/ff.c **** #endif -1436:../../../Source/third_party/fatfs/src/ff.c **** -1437:../../../Source/third_party/fatfs/src/ff.c **** -1438:../../../Source/third_party/fatfs/src/ff.c **** -1439:../../../Source/third_party/fatfs/src/ff.c **** -1440:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1441:../../../Source/third_party/fatfs/src/ff.c **** /* Directory handling - Find an object in the directory */ -1442:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1443:../../../Source/third_party/fatfs/src/ff.c **** -1444:../../../Source/third_party/fatfs/src/ff.c **** static -1445:../../../Source/third_party/fatfs/src/ff.c **** FRESULT dir_find ( -1446:../../../Source/third_party/fatfs/src/ff.c **** DIR *dj /* Pointer to the directory object linked to the file name */ -1447:../../../Source/third_party/fatfs/src/ff.c **** ) -1448:../../../Source/third_party/fatfs/src/ff.c **** { -1449:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -1450:../../../Source/third_party/fatfs/src/ff.c **** BYTE c, *dir; -1451:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN -1452:../../../Source/third_party/fatfs/src/ff.c **** BYTE a, ord, sum; -1453:../../../Source/third_party/fatfs/src/ff.c **** #endif -1454:../../../Source/third_party/fatfs/src/ff.c **** -1455:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(dj, 0); /* Rewind directory object */ -1456:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) return res; -1457:../../../Source/third_party/fatfs/src/ff.c **** -1458:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN -1459:../../../Source/third_party/fatfs/src/ff.c **** ord = sum = 0xFF; -1460:../../../Source/third_party/fatfs/src/ff.c **** #endif -1461:../../../Source/third_party/fatfs/src/ff.c **** do { -1462:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(dj->fs, dj->sect); -1463:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -1464:../../../Source/third_party/fatfs/src/ff.c **** dir = dj->dir; /* Ptr to the directory entry of current index */ -1465:../../../Source/third_party/fatfs/src/ff.c **** c = dir[DIR_Name]; -1466:../../../Source/third_party/fatfs/src/ff.c **** if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ -1467:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN /* LFN configuration */ -1468:../../../Source/third_party/fatfs/src/ff.c **** a = dir[DIR_Attr] & AM_MASK; -1469:../../../Source/third_party/fatfs/src/ff.c **** if (c == DDE || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ -1470:../../../Source/third_party/fatfs/src/ff.c **** ord = 0xFF; -1471:../../../Source/third_party/fatfs/src/ff.c **** } else { -1472:../../../Source/third_party/fatfs/src/ff.c **** if (a == AM_LFN) { /* An LFN entry is found */ -1473:../../../Source/third_party/fatfs/src/ff.c **** if (dj->lfn) { -1474:../../../Source/third_party/fatfs/src/ff.c **** if (c & LLE) { /* Is it start of LFN sequence? */ -1475:../../../Source/third_party/fatfs/src/ff.c **** sum = dir[LDIR_Chksum]; -1476:../../../Source/third_party/fatfs/src/ff.c **** c &= ~LLE; ord = c; /* LFN start order */ -1477:../../../Source/third_party/fatfs/src/ff.c **** dj->lfn_idx = dj->index; -1478:../../../Source/third_party/fatfs/src/ff.c **** } -1479:../../../Source/third_party/fatfs/src/ff.c **** /* Check validity of the LFN entry and compare it with given name */ -1480:../../../Source/third_party/fatfs/src/ff.c **** ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; -1481:../../../Source/third_party/fatfs/src/ff.c **** } -1482:../../../Source/third_party/fatfs/src/ff.c **** } else { /* An SFN entry is found */ -1483:../../../Source/third_party/fatfs/src/ff.c **** if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */ -1484:../../../Source/third_party/fatfs/src/ff.c **** ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */ -1485:../../../Source/third_party/fatfs/src/ff.c **** if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */ -1486:../../../Source/third_party/fatfs/src/ff.c **** } -1487:../../../Source/third_party/fatfs/src/ff.c **** } -1488:../../../Source/third_party/fatfs/src/ff.c **** #else /* Non LFN configuration */ -1489:../../../Source/third_party/fatfs/src/ff.c **** if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */ -1490:../../../Source/third_party/fatfs/src/ff.c **** break; -1491:../../../Source/third_party/fatfs/src/ff.c **** #endif -1492:../../../Source/third_party/fatfs/src/ff.c **** res = dir_next(dj, 0); /* Next entry */ -1493:../../../Source/third_party/fatfs/src/ff.c **** } while (res == FR_OK); -1494:../../../Source/third_party/fatfs/src/ff.c **** -1495:../../../Source/third_party/fatfs/src/ff.c **** return res; -1496:../../../Source/third_party/fatfs/src/ff.c **** } -1497:../../../Source/third_party/fatfs/src/ff.c **** -1498:../../../Source/third_party/fatfs/src/ff.c **** -1499:../../../Source/third_party/fatfs/src/ff.c **** -1500:../../../Source/third_party/fatfs/src/ff.c **** -1501:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1502:../../../Source/third_party/fatfs/src/ff.c **** /* Read an object from the directory */ -1503:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1504:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 -1505:../../../Source/third_party/fatfs/src/ff.c **** static -1506:../../../Source/third_party/fatfs/src/ff.c **** FRESULT dir_read ( -1507:../../../Source/third_party/fatfs/src/ff.c **** DIR *dj, /* Pointer to the directory object */ -1508:../../../Source/third_party/fatfs/src/ff.c **** int vol /* Filtered by 0:file/dir or 1:volume label */ -1509:../../../Source/third_party/fatfs/src/ff.c **** ) -1510:../../../Source/third_party/fatfs/src/ff.c **** { -1511:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -1512:../../../Source/third_party/fatfs/src/ff.c **** BYTE a, c, *dir; -1513:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN -1514:../../../Source/third_party/fatfs/src/ff.c **** BYTE ord = 0xFF, sum = 0xFF; -1515:../../../Source/third_party/fatfs/src/ff.c **** #endif -1516:../../../Source/third_party/fatfs/src/ff.c **** -1517:../../../Source/third_party/fatfs/src/ff.c **** res = FR_NO_FILE; -1518:../../../Source/third_party/fatfs/src/ff.c **** while (dj->sect) { -1519:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(dj->fs, dj->sect); -1520:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -1521:../../../Source/third_party/fatfs/src/ff.c **** dir = dj->dir; /* Ptr to the directory entry of current index */ -1522:../../../Source/third_party/fatfs/src/ff.c **** c = dir[DIR_Name]; -1523:../../../Source/third_party/fatfs/src/ff.c **** if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ -1524:../../../Source/third_party/fatfs/src/ff.c **** a = dir[DIR_Attr] & AM_MASK; -1525:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN /* LFN configuration */ -1526:../../../Source/third_party/fatfs/src/ff.c **** if (c == DDE || (!_FS_RPATH && c == '.') || (a == AM_VOL) != vol) { /* An entry without valid dat -1527:../../../Source/third_party/fatfs/src/ff.c **** ord = 0xFF; -1528:../../../Source/third_party/fatfs/src/ff.c **** } else { -1529:../../../Source/third_party/fatfs/src/ff.c **** if (a == AM_LFN) { /* An LFN entry is found */ -1530:../../../Source/third_party/fatfs/src/ff.c **** if (c & LLE) { /* Is it start of LFN sequence? */ -1531:../../../Source/third_party/fatfs/src/ff.c **** sum = dir[LDIR_Chksum]; -1532:../../../Source/third_party/fatfs/src/ff.c **** c &= ~LLE; ord = c; -1533:../../../Source/third_party/fatfs/src/ff.c **** dj->lfn_idx = dj->index; -1534:../../../Source/third_party/fatfs/src/ff.c **** } -1535:../../../Source/third_party/fatfs/src/ff.c **** /* Check LFN validity and capture it */ -1536:../../../Source/third_party/fatfs/src/ff.c **** ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; -1537:../../../Source/third_party/fatfs/src/ff.c **** } else { /* An SFN entry is found */ -1538:../../../Source/third_party/fatfs/src/ff.c **** if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */ -1539:../../../Source/third_party/fatfs/src/ff.c **** dj->lfn_idx = 0xFFFF; /* It has no LFN. */ -1540:../../../Source/third_party/fatfs/src/ff.c **** break; -1541:../../../Source/third_party/fatfs/src/ff.c **** } -1542:../../../Source/third_party/fatfs/src/ff.c **** } -1543:../../../Source/third_party/fatfs/src/ff.c **** #else /* Non LFN configuration */ -1544:../../../Source/third_party/fatfs/src/ff.c **** if (c != DDE && (_FS_RPATH || c != '.') && a != AM_LFN && (a == AM_VOL) == vol) /* Is it a valid -1545:../../../Source/third_party/fatfs/src/ff.c **** break; -1546:../../../Source/third_party/fatfs/src/ff.c **** #endif -1547:../../../Source/third_party/fatfs/src/ff.c **** res = dir_next(dj, 0); /* Next entry */ -1548:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -1549:../../../Source/third_party/fatfs/src/ff.c **** } -1550:../../../Source/third_party/fatfs/src/ff.c **** -1551:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) dj->sect = 0; -1552:../../../Source/third_party/fatfs/src/ff.c **** -1553:../../../Source/third_party/fatfs/src/ff.c **** return res; -1554:../../../Source/third_party/fatfs/src/ff.c **** } -1555:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */ -1556:../../../Source/third_party/fatfs/src/ff.c **** -1557:../../../Source/third_party/fatfs/src/ff.c **** -1558:../../../Source/third_party/fatfs/src/ff.c **** -1559:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1560:../../../Source/third_party/fatfs/src/ff.c **** /* Register an object to the directory */ -1561:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1562:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -1563:../../../Source/third_party/fatfs/src/ff.c **** static -1564:../../../Source/third_party/fatfs/src/ff.c **** FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_D -1565:../../../Source/third_party/fatfs/src/ff.c **** DIR *dj /* Target directory with object name to be created */ -1566:../../../Source/third_party/fatfs/src/ff.c **** ) -1567:../../../Source/third_party/fatfs/src/ff.c **** { -1568:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -1569:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN /* LFN configuration */ -1570:../../../Source/third_party/fatfs/src/ff.c **** WORD n, ne; -1571:../../../Source/third_party/fatfs/src/ff.c **** BYTE sn[12], *fn, sum; -1572:../../../Source/third_party/fatfs/src/ff.c **** WCHAR *lfn; -1573:../../../Source/third_party/fatfs/src/ff.c **** -1574:../../../Source/third_party/fatfs/src/ff.c **** -1575:../../../Source/third_party/fatfs/src/ff.c **** fn = dj->fn; lfn = dj->lfn; -1576:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(sn, fn, 12); -1577:../../../Source/third_party/fatfs/src/ff.c **** -1578:../../../Source/third_party/fatfs/src/ff.c **** if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */ -1579:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_NAME; -1580:../../../Source/third_party/fatfs/src/ff.c **** -1581:../../../Source/third_party/fatfs/src/ff.c **** if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ -1582:../../../Source/third_party/fatfs/src/ff.c **** fn[NS] = 0; dj->lfn = 0; /* Find only SFN */ -1583:../../../Source/third_party/fatfs/src/ff.c **** for (n = 1; n < 100; n++) { -1584:../../../Source/third_party/fatfs/src/ff.c **** gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ -1585:../../../Source/third_party/fatfs/src/ff.c **** res = dir_find(dj); /* Check if the name collides with existing SFN */ -1586:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -1587:../../../Source/third_party/fatfs/src/ff.c **** } -1588:../../../Source/third_party/fatfs/src/ff.c **** if (n == 100) return FR_DENIED; /* Abort if too many collisions */ -1589:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ -1590:../../../Source/third_party/fatfs/src/ff.c **** fn[NS] = sn[NS]; dj->lfn = lfn; -1591:../../../Source/third_party/fatfs/src/ff.c **** } -1592:../../../Source/third_party/fatfs/src/ff.c **** -1593:../../../Source/third_party/fatfs/src/ff.c **** if (sn[NS] & NS_LFN) { /* When LFN is to be created, allocate entries for an SFN + LFNs. */ -1594:../../../Source/third_party/fatfs/src/ff.c **** for (n = 0; lfn[n]; n++) ; -1595:../../../Source/third_party/fatfs/src/ff.c **** ne = (n + 25) / 13; -1596:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Otherwise allocate an entry for an SFN */ -1597:../../../Source/third_party/fatfs/src/ff.c **** ne = 1; -1598:../../../Source/third_party/fatfs/src/ff.c **** } -1599:../../../Source/third_party/fatfs/src/ff.c **** res = dir_alloc(dj, ne); /* Allocate entries */ -1600:../../../Source/third_party/fatfs/src/ff.c **** -1601:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK && --ne) { /* Set LFN entry if needed */ -1602:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(dj, (WORD)(dj->index - ne)); -1603:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -1604:../../../Source/third_party/fatfs/src/ff.c **** sum = sum_sfn(dj->fn); /* Sum value of the SFN tied to the LFN */ -1605:../../../Source/third_party/fatfs/src/ff.c **** do { /* Store LFN entries in bottom first */ -1606:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(dj->fs, dj->sect); -1607:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -1608:../../../Source/third_party/fatfs/src/ff.c **** fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum); -1609:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->wflag = 1; -1610:../../../Source/third_party/fatfs/src/ff.c **** res = dir_next(dj, 0); /* Next entry */ -1611:../../../Source/third_party/fatfs/src/ff.c **** } while (res == FR_OK && --ne); -1612:../../../Source/third_party/fatfs/src/ff.c **** } -1613:../../../Source/third_party/fatfs/src/ff.c **** } -1614:../../../Source/third_party/fatfs/src/ff.c **** #else /* Non LFN configuration */ -1615:../../../Source/third_party/fatfs/src/ff.c **** res = dir_alloc(dj, 1); /* Allocate an entry for SFN */ -1616:../../../Source/third_party/fatfs/src/ff.c **** #endif -1617:../../../Source/third_party/fatfs/src/ff.c **** -1618:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { /* Set SFN entry */ -1619:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(dj->fs, dj->sect); -1620:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -1621:../../../Source/third_party/fatfs/src/ff.c **** mem_set(dj->dir, 0, SZ_DIR); /* Clean the entry */ -1622:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(dj->dir, dj->fn, 11); /* Put SFN */ -1623:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN -1624:../../../Source/third_party/fatfs/src/ff.c **** dj->dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */ -1625:../../../Source/third_party/fatfs/src/ff.c **** #endif -1626:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->wflag = 1; -1627:../../../Source/third_party/fatfs/src/ff.c **** } -1628:../../../Source/third_party/fatfs/src/ff.c **** } -1629:../../../Source/third_party/fatfs/src/ff.c **** -1630:../../../Source/third_party/fatfs/src/ff.c **** return res; -1631:../../../Source/third_party/fatfs/src/ff.c **** } -1632:../../../Source/third_party/fatfs/src/ff.c **** #endif /* !_FS_READONLY */ -1633:../../../Source/third_party/fatfs/src/ff.c **** -1634:../../../Source/third_party/fatfs/src/ff.c **** -1635:../../../Source/third_party/fatfs/src/ff.c **** -1636:../../../Source/third_party/fatfs/src/ff.c **** -1637:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1638:../../../Source/third_party/fatfs/src/ff.c **** /* Remove an object from the directory */ -1639:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1640:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY && !_FS_MINIMIZE -1641:../../../Source/third_party/fatfs/src/ff.c **** static -1642:../../../Source/third_party/fatfs/src/ff.c **** FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */ -1643:../../../Source/third_party/fatfs/src/ff.c **** DIR *dj /* Directory object pointing the entry to be removed */ -1644:../../../Source/third_party/fatfs/src/ff.c **** ) -1645:../../../Source/third_party/fatfs/src/ff.c **** { -1646:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -1647:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN /* LFN configuration */ -1648:../../../Source/third_party/fatfs/src/ff.c **** WORD i; -1649:../../../Source/third_party/fatfs/src/ff.c **** -1650:../../../Source/third_party/fatfs/src/ff.c **** i = dj->index; /* SFN index */ -1651:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of th -1652:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -1653:../../../Source/third_party/fatfs/src/ff.c **** do { -1654:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(dj->fs, dj->sect); -1655:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -1656:../../../Source/third_party/fatfs/src/ff.c **** *dj->dir = DDE; /* Mark the entry "deleted" */ -1657:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->wflag = 1; -1658:../../../Source/third_party/fatfs/src/ff.c **** if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ -1659:../../../Source/third_party/fatfs/src/ff.c **** res = dir_next(dj, 0); /* Next entry */ -1660:../../../Source/third_party/fatfs/src/ff.c **** } while (res == FR_OK); -1661:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) res = FR_INT_ERR; -1662:../../../Source/third_party/fatfs/src/ff.c **** } -1663:../../../Source/third_party/fatfs/src/ff.c **** -1664:../../../Source/third_party/fatfs/src/ff.c **** #else /* Non LFN configuration */ -1665:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(dj, dj->index); -1666:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -1667:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(dj->fs, dj->sect); -1668:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -1669:../../../Source/third_party/fatfs/src/ff.c **** *dj->dir = DDE; /* Mark the entry "deleted" */ -1670:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->wflag = 1; -1671:../../../Source/third_party/fatfs/src/ff.c **** } -1672:../../../Source/third_party/fatfs/src/ff.c **** } -1673:../../../Source/third_party/fatfs/src/ff.c **** #endif -1674:../../../Source/third_party/fatfs/src/ff.c **** -1675:../../../Source/third_party/fatfs/src/ff.c **** return res; -1676:../../../Source/third_party/fatfs/src/ff.c **** } -1677:../../../Source/third_party/fatfs/src/ff.c **** #endif /* !_FS_READONLY */ -1678:../../../Source/third_party/fatfs/src/ff.c **** -1679:../../../Source/third_party/fatfs/src/ff.c **** -1680:../../../Source/third_party/fatfs/src/ff.c **** -1681:../../../Source/third_party/fatfs/src/ff.c **** -1682:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1683:../../../Source/third_party/fatfs/src/ff.c **** /* Pick a segment and create the object name in directory form */ -1684:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1685:../../../Source/third_party/fatfs/src/ff.c **** -1686:../../../Source/third_party/fatfs/src/ff.c **** static -1687:../../../Source/third_party/fatfs/src/ff.c **** FRESULT create_name ( -1688:../../../Source/third_party/fatfs/src/ff.c **** DIR *dj, /* Pointer to the directory object */ -1689:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR **path /* Pointer to pointer to the segment in the path string */ -1690:../../../Source/third_party/fatfs/src/ff.c **** ) -1691:../../../Source/third_party/fatfs/src/ff.c **** { -1692:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN /* LFN configuration */ -1693:../../../Source/third_party/fatfs/src/ff.c **** BYTE b, cf; -1694:../../../Source/third_party/fatfs/src/ff.c **** WCHAR w, *lfn; -1695:../../../Source/third_party/fatfs/src/ff.c **** UINT i, ni, si, di; -1696:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *p; -1697:../../../Source/third_party/fatfs/src/ff.c **** -1698:../../../Source/third_party/fatfs/src/ff.c **** /* Create LFN in Unicode */ -1699:../../../Source/third_party/fatfs/src/ff.c **** for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ -1700:../../../Source/third_party/fatfs/src/ff.c **** lfn = dj->lfn; -1701:../../../Source/third_party/fatfs/src/ff.c **** si = di = 0; -1702:../../../Source/third_party/fatfs/src/ff.c **** for (;;) { -1703:../../../Source/third_party/fatfs/src/ff.c **** w = p[si++]; /* Get a character */ -1704:../../../Source/third_party/fatfs/src/ff.c **** if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ -1705:../../../Source/third_party/fatfs/src/ff.c **** if (di >= _MAX_LFN) /* Reject too long name */ -1706:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_NAME; -1707:../../../Source/third_party/fatfs/src/ff.c **** #if !_LFN_UNICODE -1708:../../../Source/third_party/fatfs/src/ff.c **** w &= 0xFF; -1709:../../../Source/third_party/fatfs/src/ff.c **** if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ -1710:../../../Source/third_party/fatfs/src/ff.c **** b = (BYTE)p[si++]; /* Get 2nd byte */ -1711:../../../Source/third_party/fatfs/src/ff.c **** if (!IsDBCS2(b)) -1712:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_NAME; /* Reject invalid sequence */ -1713:../../../Source/third_party/fatfs/src/ff.c **** w = (w << 8) + b; /* Create a DBC */ -1714:../../../Source/third_party/fatfs/src/ff.c **** } -1715:../../../Source/third_party/fatfs/src/ff.c **** w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */ -1716:../../../Source/third_party/fatfs/src/ff.c **** if (!w) return FR_INVALID_NAME; /* Reject invalid code */ -1717:../../../Source/third_party/fatfs/src/ff.c **** #endif -1718:../../../Source/third_party/fatfs/src/ff.c **** if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */ -1719:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_NAME; -1720:../../../Source/third_party/fatfs/src/ff.c **** lfn[di++] = w; /* Store the Unicode char */ -1721:../../../Source/third_party/fatfs/src/ff.c **** } -1722:../../../Source/third_party/fatfs/src/ff.c **** *path = &p[si]; /* Return pointer to the next segment */ -1723:../../../Source/third_party/fatfs/src/ff.c **** cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ -1724:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_RPATH -1725:../../../Source/third_party/fatfs/src/ff.c **** if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */ -1726:../../../Source/third_party/fatfs/src/ff.c **** (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) { -1727:../../../Source/third_party/fatfs/src/ff.c **** lfn[di] = 0; -1728:../../../Source/third_party/fatfs/src/ff.c **** for (i = 0; i < 11; i++) -1729:../../../Source/third_party/fatfs/src/ff.c **** dj->fn[i] = (i < di) ? '.' : ' '; -1730:../../../Source/third_party/fatfs/src/ff.c **** dj->fn[i] = cf | NS_DOT; /* This is a dot entry */ -1731:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; -1732:../../../Source/third_party/fatfs/src/ff.c **** } -1733:../../../Source/third_party/fatfs/src/ff.c **** #endif -1734:../../../Source/third_party/fatfs/src/ff.c **** while (di) { /* Strip trailing spaces and dots */ -1735:../../../Source/third_party/fatfs/src/ff.c **** w = lfn[di-1]; -1736:../../../Source/third_party/fatfs/src/ff.c **** if (w != ' ' && w != '.') break; -1737:../../../Source/third_party/fatfs/src/ff.c **** di--; -1738:../../../Source/third_party/fatfs/src/ff.c **** } -1739:../../../Source/third_party/fatfs/src/ff.c **** if (!di) return FR_INVALID_NAME; /* Reject nul string */ -1740:../../../Source/third_party/fatfs/src/ff.c **** -1741:../../../Source/third_party/fatfs/src/ff.c **** lfn[di] = 0; /* LFN is created */ -1742:../../../Source/third_party/fatfs/src/ff.c **** -1743:../../../Source/third_party/fatfs/src/ff.c **** /* Create SFN in directory form */ -1744:../../../Source/third_party/fatfs/src/ff.c **** mem_set(dj->fn, ' ', 11); -1745:../../../Source/third_party/fatfs/src/ff.c **** for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ -1746:../../../Source/third_party/fatfs/src/ff.c **** if (si) cf |= NS_LOSS | NS_LFN; -1747:../../../Source/third_party/fatfs/src/ff.c **** while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ -1748:../../../Source/third_party/fatfs/src/ff.c **** -1749:../../../Source/third_party/fatfs/src/ff.c **** b = i = 0; ni = 8; -1750:../../../Source/third_party/fatfs/src/ff.c **** for (;;) { -1751:../../../Source/third_party/fatfs/src/ff.c **** w = lfn[si++]; /* Get an LFN char */ -1752:../../../Source/third_party/fatfs/src/ff.c **** if (!w) break; /* Break on end of the LFN */ -1753:../../../Source/third_party/fatfs/src/ff.c **** if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ -1754:../../../Source/third_party/fatfs/src/ff.c **** cf |= NS_LOSS | NS_LFN; continue; -1755:../../../Source/third_party/fatfs/src/ff.c **** } -1756:../../../Source/third_party/fatfs/src/ff.c **** -1757:../../../Source/third_party/fatfs/src/ff.c **** if (i >= ni || si == di) { /* Extension or end of SFN */ -1758:../../../Source/third_party/fatfs/src/ff.c **** if (ni == 11) { /* Long extension */ -1759:../../../Source/third_party/fatfs/src/ff.c **** cf |= NS_LOSS | NS_LFN; break; -1760:../../../Source/third_party/fatfs/src/ff.c **** } -1761:../../../Source/third_party/fatfs/src/ff.c **** if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ -1762:../../../Source/third_party/fatfs/src/ff.c **** if (si > di) break; /* No extension */ -1763:../../../Source/third_party/fatfs/src/ff.c **** si = di; i = 8; ni = 11; /* Enter extension section */ -1764:../../../Source/third_party/fatfs/src/ff.c **** b <<= 2; continue; -1765:../../../Source/third_party/fatfs/src/ff.c **** } -1766:../../../Source/third_party/fatfs/src/ff.c **** -1767:../../../Source/third_party/fatfs/src/ff.c **** if (w >= 0x80) { /* Non ASCII char */ -1768:../../../Source/third_party/fatfs/src/ff.c **** #ifdef _EXCVT -1769:../../../Source/third_party/fatfs/src/ff.c **** w = ff_convert(w, 0); /* Unicode -> OEM code */ -1770:../../../Source/third_party/fatfs/src/ff.c **** if (w) w = ExCvt[w - 0x80]; /* Convert extended char to upper (SBCS) */ -1771:../../../Source/third_party/fatfs/src/ff.c **** #else -1772:../../../Source/third_party/fatfs/src/ff.c **** w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ -1773:../../../Source/third_party/fatfs/src/ff.c **** #endif -1774:../../../Source/third_party/fatfs/src/ff.c **** cf |= NS_LFN; /* Force create LFN entry */ -1775:../../../Source/third_party/fatfs/src/ff.c **** } -1776:../../../Source/third_party/fatfs/src/ff.c **** -1777:../../../Source/third_party/fatfs/src/ff.c **** if (_DF1S && w >= 0x100) { /* Double byte char (always false on SBCS cfg) */ -1778:../../../Source/third_party/fatfs/src/ff.c **** if (i >= ni - 1) { -1779:../../../Source/third_party/fatfs/src/ff.c **** cf |= NS_LOSS | NS_LFN; i = ni; continue; -1780:../../../Source/third_party/fatfs/src/ff.c **** } -1781:../../../Source/third_party/fatfs/src/ff.c **** dj->fn[i++] = (BYTE)(w >> 8); -1782:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Single byte char */ -1783:../../../Source/third_party/fatfs/src/ff.c **** if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal chars for SFN */ -1784:../../../Source/third_party/fatfs/src/ff.c **** w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ -1785:../../../Source/third_party/fatfs/src/ff.c **** } else { -1786:../../../Source/third_party/fatfs/src/ff.c **** if (IsUpper(w)) { /* ASCII large capital */ -1787:../../../Source/third_party/fatfs/src/ff.c **** b |= 2; -1788:../../../Source/third_party/fatfs/src/ff.c **** } else { -1789:../../../Source/third_party/fatfs/src/ff.c **** if (IsLower(w)) { /* ASCII small capital */ -1790:../../../Source/third_party/fatfs/src/ff.c **** b |= 1; w -= 0x20; -1791:../../../Source/third_party/fatfs/src/ff.c **** } -1792:../../../Source/third_party/fatfs/src/ff.c **** } -1793:../../../Source/third_party/fatfs/src/ff.c **** } -1794:../../../Source/third_party/fatfs/src/ff.c **** } -1795:../../../Source/third_party/fatfs/src/ff.c **** dj->fn[i++] = (BYTE)w; -1796:../../../Source/third_party/fatfs/src/ff.c **** } -1797:../../../Source/third_party/fatfs/src/ff.c **** -1798:../../../Source/third_party/fatfs/src/ff.c **** if (dj->fn[0] == DDE) dj->fn[0] = NDDE; /* If the first char collides with deleted mark, replace i -1799:../../../Source/third_party/fatfs/src/ff.c **** -1800:../../../Source/third_party/fatfs/src/ff.c **** if (ni == 8) b <<= 2; -1801:../../../Source/third_party/fatfs/src/ff.c **** if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capital -1802:../../../Source/third_party/fatfs/src/ff.c **** cf |= NS_LFN; -1803:../../../Source/third_party/fatfs/src/ff.c **** if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are create -1804:../../../Source/third_party/fatfs/src/ff.c **** if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ -1805:../../../Source/third_party/fatfs/src/ff.c **** if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ -1806:../../../Source/third_party/fatfs/src/ff.c **** } -1807:../../../Source/third_party/fatfs/src/ff.c **** -1808:../../../Source/third_party/fatfs/src/ff.c **** dj->fn[NS] = cf; /* SFN is created */ -1809:../../../Source/third_party/fatfs/src/ff.c **** -1810:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; -1811:../../../Source/third_party/fatfs/src/ff.c **** -1812:../../../Source/third_party/fatfs/src/ff.c **** -1813:../../../Source/third_party/fatfs/src/ff.c **** #else /* Non-LFN configuration */ -1814:../../../Source/third_party/fatfs/src/ff.c **** BYTE b, c, d, *sfn; -1815:../../../Source/third_party/fatfs/src/ff.c **** UINT ni, si, i; -1816:../../../Source/third_party/fatfs/src/ff.c **** const char *p; -1817:../../../Source/third_party/fatfs/src/ff.c **** -1818:../../../Source/third_party/fatfs/src/ff.c **** /* Create file name in directory form */ -1819:../../../Source/third_party/fatfs/src/ff.c **** for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ -1820:../../../Source/third_party/fatfs/src/ff.c **** sfn = dj->fn; -1821:../../../Source/third_party/fatfs/src/ff.c **** mem_set(sfn, ' ', 11); -1822:../../../Source/third_party/fatfs/src/ff.c **** si = i = b = 0; ni = 8; -1823:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_RPATH -1824:../../../Source/third_party/fatfs/src/ff.c **** if (p[si] == '.') { /* Is this a dot entry? */ -1825:../../../Source/third_party/fatfs/src/ff.c **** for (;;) { -1826:../../../Source/third_party/fatfs/src/ff.c **** c = (BYTE)p[si++]; -1827:../../../Source/third_party/fatfs/src/ff.c **** if (c != '.' || si >= 3) break; -1828:../../../Source/third_party/fatfs/src/ff.c **** sfn[i++] = c; -1829:../../../Source/third_party/fatfs/src/ff.c **** } -1830:../../../Source/third_party/fatfs/src/ff.c **** if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; -1831:../../../Source/third_party/fatfs/src/ff.c **** *path = &p[si]; /* Return pointer to the next segment */ -1832:../../../Source/third_party/fatfs/src/ff.c **** sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */ -1833:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; -1834:../../../Source/third_party/fatfs/src/ff.c **** } -1835:../../../Source/third_party/fatfs/src/ff.c **** #endif -1836:../../../Source/third_party/fatfs/src/ff.c **** for (;;) { -1837:../../../Source/third_party/fatfs/src/ff.c **** c = (BYTE)p[si++]; -1838:../../../Source/third_party/fatfs/src/ff.c **** if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */ -1839:../../../Source/third_party/fatfs/src/ff.c **** if (c == '.' || i >= ni) { -1840:../../../Source/third_party/fatfs/src/ff.c **** if (ni != 8 || c != '.') return FR_INVALID_NAME; -1841:../../../Source/third_party/fatfs/src/ff.c **** i = 8; ni = 11; -1842:../../../Source/third_party/fatfs/src/ff.c **** b <<= 2; continue; -1843:../../../Source/third_party/fatfs/src/ff.c **** } -1844:../../../Source/third_party/fatfs/src/ff.c **** if (c >= 0x80) { /* Extended char? */ -1845:../../../Source/third_party/fatfs/src/ff.c **** b |= 3; /* Eliminate NT flag */ -1846:../../../Source/third_party/fatfs/src/ff.c **** #ifdef _EXCVT -1847:../../../Source/third_party/fatfs/src/ff.c **** c = ExCvt[c - 0x80]; /* To upper extended chars (SBCS cfg) */ -1848:../../../Source/third_party/fatfs/src/ff.c **** #else -1849:../../../Source/third_party/fatfs/src/ff.c **** #if !_DF1S -1850:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_NAME; /* Reject extended chars (ASCII cfg) */ -1851:../../../Source/third_party/fatfs/src/ff.c **** #endif -1852:../../../Source/third_party/fatfs/src/ff.c **** #endif -1853:../../../Source/third_party/fatfs/src/ff.c **** } -1854:../../../Source/third_party/fatfs/src/ff.c **** if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ -1855:../../../Source/third_party/fatfs/src/ff.c **** d = (BYTE)p[si++]; /* Get 2nd byte */ -1856:../../../Source/third_party/fatfs/src/ff.c **** if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */ -1857:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_NAME; -1858:../../../Source/third_party/fatfs/src/ff.c **** sfn[i++] = c; -1859:../../../Source/third_party/fatfs/src/ff.c **** sfn[i++] = d; -1860:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Single byte code */ -1861:../../../Source/third_party/fatfs/src/ff.c **** if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */ -1862:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_NAME; -1863:../../../Source/third_party/fatfs/src/ff.c **** if (IsUpper(c)) { /* ASCII large capital? */ -1864:../../../Source/third_party/fatfs/src/ff.c **** b |= 2; -1865:../../../Source/third_party/fatfs/src/ff.c **** } else { -1866:../../../Source/third_party/fatfs/src/ff.c **** if (IsLower(c)) { /* ASCII small capital? */ -1867:../../../Source/third_party/fatfs/src/ff.c **** b |= 1; c -= 0x20; -1868:../../../Source/third_party/fatfs/src/ff.c **** } -1869:../../../Source/third_party/fatfs/src/ff.c **** } -1870:../../../Source/third_party/fatfs/src/ff.c **** sfn[i++] = c; -1871:../../../Source/third_party/fatfs/src/ff.c **** } -1872:../../../Source/third_party/fatfs/src/ff.c **** } -1873:../../../Source/third_party/fatfs/src/ff.c **** *path = &p[si]; /* Return pointer to the next segment */ -1874:../../../Source/third_party/fatfs/src/ff.c **** c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ -1875:../../../Source/third_party/fatfs/src/ff.c **** -1876:../../../Source/third_party/fatfs/src/ff.c **** if (!i) return FR_INVALID_NAME; /* Reject nul string */ -1877:../../../Source/third_party/fatfs/src/ff.c **** if (sfn[0] == DDE) sfn[0] = NDDE; /* When first char collides with DDE, replace it with 0x05 */ -1878:../../../Source/third_party/fatfs/src/ff.c **** -1879:../../../Source/third_party/fatfs/src/ff.c **** if (ni == 8) b <<= 2; -1880:../../../Source/third_party/fatfs/src/ff.c **** if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */ -1881:../../../Source/third_party/fatfs/src/ff.c **** if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */ -1882:../../../Source/third_party/fatfs/src/ff.c **** -1883:../../../Source/third_party/fatfs/src/ff.c **** sfn[NS] = c; /* Store NT flag, File name is created */ -1884:../../../Source/third_party/fatfs/src/ff.c **** -1885:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; -1886:../../../Source/third_party/fatfs/src/ff.c **** #endif -1887:../../../Source/third_party/fatfs/src/ff.c **** } -1888:../../../Source/third_party/fatfs/src/ff.c **** -1889:../../../Source/third_party/fatfs/src/ff.c **** -1890:../../../Source/third_party/fatfs/src/ff.c **** -1891:../../../Source/third_party/fatfs/src/ff.c **** -1892:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1893:../../../Source/third_party/fatfs/src/ff.c **** /* Get file information from directory entry */ -1894:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1895:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 -1896:../../../Source/third_party/fatfs/src/ff.c **** static -1897:../../../Source/third_party/fatfs/src/ff.c **** void get_fileinfo ( /* No return code */ -1898:../../../Source/third_party/fatfs/src/ff.c **** DIR *dj, /* Pointer to the directory object */ -1899:../../../Source/third_party/fatfs/src/ff.c **** FILINFO *fno /* Pointer to the file information to be filled */ -1900:../../../Source/third_party/fatfs/src/ff.c **** ) -1901:../../../Source/third_party/fatfs/src/ff.c **** { -1902:../../../Source/third_party/fatfs/src/ff.c **** UINT i; -1903:../../../Source/third_party/fatfs/src/ff.c **** BYTE nt, *dir; -1904:../../../Source/third_party/fatfs/src/ff.c **** TCHAR *p, c; -1905:../../../Source/third_party/fatfs/src/ff.c **** -1906:../../../Source/third_party/fatfs/src/ff.c **** -1907:../../../Source/third_party/fatfs/src/ff.c **** p = fno->fname; -1908:../../../Source/third_party/fatfs/src/ff.c **** if (dj->sect) { -1909:../../../Source/third_party/fatfs/src/ff.c **** dir = dj->dir; -1910:../../../Source/third_party/fatfs/src/ff.c **** nt = dir[DIR_NTres]; /* NT flag */ -1911:../../../Source/third_party/fatfs/src/ff.c **** for (i = 0; i < 8; i++) { /* Copy name body */ -1912:../../../Source/third_party/fatfs/src/ff.c **** c = dir[i]; -1913:../../../Source/third_party/fatfs/src/ff.c **** if (c == ' ') break; -1914:../../../Source/third_party/fatfs/src/ff.c **** if (c == NDDE) c = (TCHAR)DDE; -1915:../../../Source/third_party/fatfs/src/ff.c **** if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20; -1916:../../../Source/third_party/fatfs/src/ff.c **** #if _LFN_UNICODE -1917:../../../Source/third_party/fatfs/src/ff.c **** if (IsDBCS1(c) && i < 7 && IsDBCS2(dir[i+1])) -1918:../../../Source/third_party/fatfs/src/ff.c **** c = (c << 8) | dir[++i]; -1919:../../../Source/third_party/fatfs/src/ff.c **** c = ff_convert(c, 1); -1920:../../../Source/third_party/fatfs/src/ff.c **** if (!c) c = '?'; -1921:../../../Source/third_party/fatfs/src/ff.c **** #endif -1922:../../../Source/third_party/fatfs/src/ff.c **** *p++ = c; -1923:../../../Source/third_party/fatfs/src/ff.c **** } -1924:../../../Source/third_party/fatfs/src/ff.c **** if (dir[8] != ' ') { /* Copy name extension */ -1925:../../../Source/third_party/fatfs/src/ff.c **** *p++ = '.'; -1926:../../../Source/third_party/fatfs/src/ff.c **** for (i = 8; i < 11; i++) { -1927:../../../Source/third_party/fatfs/src/ff.c **** c = dir[i]; -1928:../../../Source/third_party/fatfs/src/ff.c **** if (c == ' ') break; -1929:../../../Source/third_party/fatfs/src/ff.c **** if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20; -1930:../../../Source/third_party/fatfs/src/ff.c **** #if _LFN_UNICODE -1931:../../../Source/third_party/fatfs/src/ff.c **** if (IsDBCS1(c) && i < 10 && IsDBCS2(dir[i+1])) -1932:../../../Source/third_party/fatfs/src/ff.c **** c = (c << 8) | dir[++i]; -1933:../../../Source/third_party/fatfs/src/ff.c **** c = ff_convert(c, 1); -1934:../../../Source/third_party/fatfs/src/ff.c **** if (!c) c = '?'; -1935:../../../Source/third_party/fatfs/src/ff.c **** #endif -1936:../../../Source/third_party/fatfs/src/ff.c **** *p++ = c; -1937:../../../Source/third_party/fatfs/src/ff.c **** } -1938:../../../Source/third_party/fatfs/src/ff.c **** } -1939:../../../Source/third_party/fatfs/src/ff.c **** fno->fattrib = dir[DIR_Attr]; /* Attribute */ -1940:../../../Source/third_party/fatfs/src/ff.c **** fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */ -1941:../../../Source/third_party/fatfs/src/ff.c **** fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */ -1942:../../../Source/third_party/fatfs/src/ff.c **** fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */ -1943:../../../Source/third_party/fatfs/src/ff.c **** } -1944:../../../Source/third_party/fatfs/src/ff.c **** *p = 0; /* Terminate SFN str by a \0 */ -1945:../../../Source/third_party/fatfs/src/ff.c **** -1946:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN -1947:../../../Source/third_party/fatfs/src/ff.c **** if (fno->lfname && fno->lfsize) { -1948:../../../Source/third_party/fatfs/src/ff.c **** TCHAR *tp = fno->lfname; -1949:../../../Source/third_party/fatfs/src/ff.c **** WCHAR w, *lfn; -1950:../../../Source/third_party/fatfs/src/ff.c **** -1951:../../../Source/third_party/fatfs/src/ff.c **** i = 0; -1952:../../../Source/third_party/fatfs/src/ff.c **** if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */ -1953:../../../Source/third_party/fatfs/src/ff.c **** lfn = dj->lfn; -1954:../../../Source/third_party/fatfs/src/ff.c **** while ((w = *lfn++) != 0) { /* Get an LFN char */ -1955:../../../Source/third_party/fatfs/src/ff.c **** #if !_LFN_UNICODE -1956:../../../Source/third_party/fatfs/src/ff.c **** w = ff_convert(w, 0); /* Unicode -> OEM conversion */ -1957:../../../Source/third_party/fatfs/src/ff.c **** if (!w) { i = 0; break; } /* Could not convert, no LFN */ -1958:../../../Source/third_party/fatfs/src/ff.c **** if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */ -1959:../../../Source/third_party/fatfs/src/ff.c **** tp[i++] = (TCHAR)(w >> 8); -1960:../../../Source/third_party/fatfs/src/ff.c **** #endif -1961:../../../Source/third_party/fatfs/src/ff.c **** if (i >= fno->lfsize - 1) { i = 0; break; } /* Buffer overflow, no LFN */ -1962:../../../Source/third_party/fatfs/src/ff.c **** tp[i++] = (TCHAR)w; -1963:../../../Source/third_party/fatfs/src/ff.c **** } -1964:../../../Source/third_party/fatfs/src/ff.c **** } -1965:../../../Source/third_party/fatfs/src/ff.c **** tp[i] = 0; /* Terminate the LFN str by a \0 */ -1966:../../../Source/third_party/fatfs/src/ff.c **** } -1967:../../../Source/third_party/fatfs/src/ff.c **** #endif -1968:../../../Source/third_party/fatfs/src/ff.c **** } -1969:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2*/ -1970:../../../Source/third_party/fatfs/src/ff.c **** -1971:../../../Source/third_party/fatfs/src/ff.c **** -1972:../../../Source/third_party/fatfs/src/ff.c **** -1973:../../../Source/third_party/fatfs/src/ff.c **** -1974:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1975:../../../Source/third_party/fatfs/src/ff.c **** /* Follow a file path */ -1976:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -1977:../../../Source/third_party/fatfs/src/ff.c **** -1978:../../../Source/third_party/fatfs/src/ff.c **** static -1979:../../../Source/third_party/fatfs/src/ff.c **** FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ -1980:../../../Source/third_party/fatfs/src/ff.c **** DIR *dj, /* Directory object to return last directory and found object */ -1981:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *path /* Full-path string to find a file or directory */ -1982:../../../Source/third_party/fatfs/src/ff.c **** ) -1983:../../../Source/third_party/fatfs/src/ff.c **** { -1984:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -1985:../../../Source/third_party/fatfs/src/ff.c **** BYTE *dir, ns; -1986:../../../Source/third_party/fatfs/src/ff.c **** -1987:../../../Source/third_party/fatfs/src/ff.c **** -1988:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_RPATH -1989:../../../Source/third_party/fatfs/src/ff.c **** if (*path == '/' || *path == '\\') { /* There is a heading separator */ -1990:../../../Source/third_party/fatfs/src/ff.c **** path++; dj->sclust = 0; /* Strip it and start from the root dir */ -1991:../../../Source/third_party/fatfs/src/ff.c **** } else { /* No heading separator */ -1992:../../../Source/third_party/fatfs/src/ff.c **** dj->sclust = dj->fs->cdir; /* Start from the current dir */ -1993:../../../Source/third_party/fatfs/src/ff.c **** } -1994:../../../Source/third_party/fatfs/src/ff.c **** #else -1995:../../../Source/third_party/fatfs/src/ff.c **** if (*path == '/' || *path == '\\') /* Strip heading separator if exist */ -1996:../../../Source/third_party/fatfs/src/ff.c **** path++; -1997:../../../Source/third_party/fatfs/src/ff.c **** dj->sclust = 0; /* Start from the root dir */ -1998:../../../Source/third_party/fatfs/src/ff.c **** #endif -1999:../../../Source/third_party/fatfs/src/ff.c **** -2000:../../../Source/third_party/fatfs/src/ff.c **** if ((UINT)*path < ' ') { /* Nul path means the start directory itself */ -2001:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(dj, 0); -2002:../../../Source/third_party/fatfs/src/ff.c **** dj->dir = 0; -2003:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Follow path */ -2004:../../../Source/third_party/fatfs/src/ff.c **** for (;;) { -2005:../../../Source/third_party/fatfs/src/ff.c **** res = create_name(dj, &path); /* Get a segment */ -2006:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -2007:../../../Source/third_party/fatfs/src/ff.c **** res = dir_find(dj); /* Find it */ -2008:../../../Source/third_party/fatfs/src/ff.c **** ns = *(dj->fn+NS); -2009:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) { /* Failed to find the object */ -2010:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_NO_FILE) break; /* Abort if any hard error occurred */ -2011:../../../Source/third_party/fatfs/src/ff.c **** /* Object not found */ -2012:../../../Source/third_party/fatfs/src/ff.c **** if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exit */ -2013:../../../Source/third_party/fatfs/src/ff.c **** dj->sclust = 0; dj->dir = 0; /* It is the root dir */ -2014:../../../Source/third_party/fatfs/src/ff.c **** res = FR_OK; -2015:../../../Source/third_party/fatfs/src/ff.c **** if (!(ns & NS_LAST)) continue; -2016:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Could not find the object */ -2017:../../../Source/third_party/fatfs/src/ff.c **** if (!(ns & NS_LAST)) res = FR_NO_PATH; -2018:../../../Source/third_party/fatfs/src/ff.c **** } -2019:../../../Source/third_party/fatfs/src/ff.c **** break; -2020:../../../Source/third_party/fatfs/src/ff.c **** } -2021:../../../Source/third_party/fatfs/src/ff.c **** if (ns & NS_LAST) break; /* Last segment match. Function completed. */ -2022:../../../Source/third_party/fatfs/src/ff.c **** dir = dj->dir; /* There is next segment. Follow the sub directory */ -2023:../../../Source/third_party/fatfs/src/ff.c **** if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */ -2024:../../../Source/third_party/fatfs/src/ff.c **** res = FR_NO_PATH; break; -2025:../../../Source/third_party/fatfs/src/ff.c **** } -2026:../../../Source/third_party/fatfs/src/ff.c **** dj->sclust = ld_clust(dj->fs, dir); -2027:../../../Source/third_party/fatfs/src/ff.c **** } -2028:../../../Source/third_party/fatfs/src/ff.c **** } -2029:../../../Source/third_party/fatfs/src/ff.c **** -2030:../../../Source/third_party/fatfs/src/ff.c **** return res; -2031:../../../Source/third_party/fatfs/src/ff.c **** } -2032:../../../Source/third_party/fatfs/src/ff.c **** -2033:../../../Source/third_party/fatfs/src/ff.c **** -2034:../../../Source/third_party/fatfs/src/ff.c **** -2035:../../../Source/third_party/fatfs/src/ff.c **** -2036:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2037:../../../Source/third_party/fatfs/src/ff.c **** /* Load a sector and check if it is an FAT Volume Boot Record */ -2038:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2039:../../../Source/third_party/fatfs/src/ff.c **** -2040:../../../Source/third_party/fatfs/src/ff.c **** static -2041:../../../Source/third_party/fatfs/src/ff.c **** BYTE check_fs ( /* 0:FAT-VBR, 1:Any BR but not FAT, 2:Not a BR, 3:Disk error */ -2042:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs, /* File system object */ -2043:../../../Source/third_party/fatfs/src/ff.c **** DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ -2044:../../../Source/third_party/fatfs/src/ff.c **** ) -2045:../../../Source/third_party/fatfs/src/ff.c **** { - 132 .loc 1 2045 0 - 133 .cfi_startproc - 134 @ args = 0, pretend = 0, frame = 0 - 135 @ frame_needed = 0, uses_anonymous_args = 0 - 136 .LVL16: - 137 0000 10B5 push {r4, lr} - 138 .cfi_def_cfa_offset 8 - 139 .cfi_offset 4, -8 - 140 .cfi_offset 14, -4 - 141 0002 0446 mov r4, r0 - 142 0004 0A46 mov r2, r1 -2046:../../../Source/third_party/fatfs/src/ff.c **** if (disk_read(fs->drv, fs->win, sect, 1) != RES_OK) /* Load boot record */ - 143 .loc 1 2046 0 - 144 0006 4078 ldrb r0, [r0, #1] @ zero_extendqisi2 - 145 .LVL17: - 146 0008 04F13401 add r1, r4, #52 - 147 .LVL18: - 148 000c 0123 movs r3, #1 - 149 000e FFF7FEFF bl disk_read - 150 .LVL19: - 151 0012 80BB cbnz r0, .L12 -2047:../../../Source/third_party/fatfs/src/ff.c **** return 3; -2048:../../../Source/third_party/fatfs/src/ff.c **** if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 - 152 .loc 1 2048 0 - 153 0014 94F83322 ldrb r2, [r4, #563] @ zero_extendqisi2 - 154 0018 94F83232 ldrb r3, [r4, #562] @ zero_extendqisi2 - 155 001c 43EA0223 orr r3, r3, r2, lsl #8 - 156 0020 1BB2 sxth r3, r3 - 157 0022 184A ldr r2, .L16 - 158 0024 9342 cmp r3, r2 - 159 0026 28D1 bne .L13 -2049:../../../Source/third_party/fatfs/src/ff.c **** return 2; -2050:../../../Source/third_party/fatfs/src/ff.c **** -2051:../../../Source/third_party/fatfs/src/ff.c **** if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ - 160 .loc 1 2051 0 - 161 0028 94F86D10 ldrb r1, [r4, #109] @ zero_extendqisi2 - 162 002c 94F86C20 ldrb r2, [r4, #108] @ zero_extendqisi2 - 163 0030 1304 lsls r3, r2, #16 - 164 0032 43EA0162 orr r2, r3, r1, lsl #24 - 165 0036 94F86A30 ldrb r3, [r4, #106] @ zero_extendqisi2 - 166 003a 1343 orrs r3, r3, r2 - 167 003c 94F86B20 ldrb r2, [r4, #107] @ zero_extendqisi2 - 168 0040 43EA0223 orr r3, r3, r2, lsl #8 - 169 0044 23F07F43 bic r3, r3, #-16777216 - 170 0048 0F4A ldr r2, .L16+4 - 171 004a 9342 cmp r3, r2 - 172 004c 17D0 beq .L14 -2052:../../../Source/third_party/fatfs/src/ff.c **** return 0; -2053:../../../Source/third_party/fatfs/src/ff.c **** if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146) - 173 .loc 1 2053 0 - 174 004e 94F88900 ldrb r0, [r4, #137] @ zero_extendqisi2 - 175 0052 94F88830 ldrb r3, [r4, #136] @ zero_extendqisi2 - 176 0056 1B04 lsls r3, r3, #16 - 177 0058 43EA0060 orr r0, r3, r0, lsl #24 - 178 005c 94F88630 ldrb r3, [r4, #134] @ zero_extendqisi2 - 179 0060 0343 orrs r3, r3, r0 - 180 0062 94F88700 ldrb r0, [r4, #135] @ zero_extendqisi2 - 181 0066 43EA0020 orr r0, r3, r0, lsl #8 - 182 006a 20F07F43 bic r3, r0, #-16777216 -2047:../../../Source/third_party/fatfs/src/ff.c **** if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 - 183 .loc 1 2047 0 - 184 006e 981A subs r0, r3, r2 - 185 0070 18BF it ne - 186 0072 0120 movne r0, #1 - 187 0074 10BD pop {r4, pc} - 188 .LVL20: - 189 .L12: - 190 0076 0320 movs r0, #3 - 191 0078 10BD pop {r4, pc} - 192 .LVL21: - 193 .L13: -2049:../../../Source/third_party/fatfs/src/ff.c **** return 2; - 194 .loc 1 2049 0 - 195 007a 0220 movs r0, #2 - 196 007c 10BD pop {r4, pc} - 197 .LVL22: - 198 .L14: -2052:../../../Source/third_party/fatfs/src/ff.c **** return 0; - 199 .loc 1 2052 0 - 200 007e 0020 movs r0, #0 -2054:../../../Source/third_party/fatfs/src/ff.c **** return 0; -2055:../../../Source/third_party/fatfs/src/ff.c **** -2056:../../../Source/third_party/fatfs/src/ff.c **** return 1; -2057:../../../Source/third_party/fatfs/src/ff.c **** } - 201 .loc 1 2057 0 - 202 0080 10BD pop {r4, pc} - 203 .LVL23: - 204 .L17: - 205 0082 00BF .align 2 - 206 .L16: - 207 0084 55AAFFFF .word -21931 - 208 0088 46415400 .word 5521734 - 209 .cfi_endproc - 210 .LFE29: - 212 .section .text.sync_window,"ax",%progbits - 213 .align 2 - 214 .thumb - 215 .thumb_func - 217 sync_window: - 218 .LFB4: - 735:../../../Source/third_party/fatfs/src/ff.c **** DWORD wsect; - 219 .loc 1 735 0 - 220 .cfi_startproc - 221 @ args = 0, pretend = 0, frame = 0 - 222 @ frame_needed = 0, uses_anonymous_args = 0 - 223 .LVL24: - 740:../../../Source/third_party/fatfs/src/ff.c **** wsect = fs->winsect; /* Current sector number */ - 224 .loc 1 740 0 - 225 0000 0379 ldrb r3, [r0, #4] @ zero_extendqisi2 - 226 0002 43B3 cbz r3, .L21 - 735:../../../Source/third_party/fatfs/src/ff.c **** DWORD wsect; - 227 .loc 1 735 0 - 228 0004 2DE9F041 push {r4, r5, r6, r7, r8, lr} - 229 .cfi_def_cfa_offset 24 - 230 .cfi_offset 4, -24 - 231 .cfi_offset 5, -20 - 232 .cfi_offset 6, -16 - 233 .cfi_offset 7, -12 - 234 .cfi_offset 8, -8 - 235 .cfi_offset 14, -4 - 236 0008 0446 mov r4, r0 - 741:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) - 237 .loc 1 741 0 - 238 000a 056B ldr r5, [r0, #48] - 239 .LVL25: - 742:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; - 240 .loc 1 742 0 - 241 000c 00F13407 add r7, r0, #52 - 242 0010 4078 ldrb r0, [r0, #1] @ zero_extendqisi2 - 243 .LVL26: - 244 0012 3946 mov r1, r7 - 245 0014 2A46 mov r2, r5 - 246 0016 0123 movs r3, #1 - 247 0018 FFF7FEFF bl disk_write - 248 .LVL27: - 249 001c E8B9 cbnz r0, .L22 - 744:../../../Source/third_party/fatfs/src/ff.c **** if (wsect >= fs->fatbase && wsect < (fs->fatbase + fs->fsize)) { /* In FAT area? */ - 250 .loc 1 744 0 - 251 001e 0023 movs r3, #0 - 252 0020 2371 strb r3, [r4, #4] - 745:../../../Source/third_party/fatfs/src/ff.c **** for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ - 253 .loc 1 745 0 - 254 0022 636A ldr r3, [r4, #36] - 255 0024 9D42 cmp r5, r3 - 256 0026 1BD3 bcc .L23 - 745:../../../Source/third_party/fatfs/src/ff.c **** for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ - 257 .loc 1 745 0 is_stmt 0 discriminator 1 - 258 0028 E269 ldr r2, [r4, #28] - 259 002a 1344 add r3, r3, r2 - 260 002c 9D42 cmp r5, r3 - 261 002e 1AD2 bcs .L24 - 746:../../../Source/third_party/fatfs/src/ff.c **** wsect += fs->fsize; - 262 .loc 1 746 0 is_stmt 1 - 263 0030 E678 ldrb r6, [r4, #3] @ zero_extendqisi2 - 264 .LVL28: - 265 0032 012E cmp r6, #1 - 266 0034 1AD9 bls .L25 - 748:../../../Source/third_party/fatfs/src/ff.c **** } - 267 .loc 1 748 0 discriminator 3 - 268 0036 4FF00108 mov r8, #1 - 269 .L26: - 747:../../../Source/third_party/fatfs/src/ff.c **** disk_write(fs->drv, fs->win, wsect, 1); - 270 .loc 1 747 0 discriminator 3 - 271 003a E369 ldr r3, [r4, #28] - 272 003c 1D44 add r5, r5, r3 - 273 .LVL29: - 748:../../../Source/third_party/fatfs/src/ff.c **** } - 274 .loc 1 748 0 discriminator 3 - 275 003e 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 - 276 0040 3946 mov r1, r7 - 277 0042 2A46 mov r2, r5 - 278 0044 4346 mov r3, r8 - 279 0046 FFF7FEFF bl disk_write - 280 .LVL30: - 746:../../../Source/third_party/fatfs/src/ff.c **** wsect += fs->fsize; - 281 .loc 1 746 0 discriminator 3 - 282 004a 013E subs r6, r6, #1 - 283 .LVL31: - 284 004c 012E cmp r6, #1 - 285 004e F4D1 bne .L26 - 752:../../../Source/third_party/fatfs/src/ff.c **** } - 286 .loc 1 752 0 - 287 0050 0020 movs r0, #0 - 288 0052 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 289 .LVL32: - 290 .L21: - 291 .cfi_def_cfa_offset 0 - 292 .cfi_restore 4 - 293 .cfi_restore 5 - 294 .cfi_restore 6 - 295 .cfi_restore 7 - 296 .cfi_restore 8 - 297 .cfi_restore 14 - 298 0056 0020 movs r0, #0 - 299 .LVL33: - 753:../../../Source/third_party/fatfs/src/ff.c **** #endif - 300 .loc 1 753 0 - 301 0058 7047 bx lr - 302 .LVL34: - 303 .L22: - 304 .cfi_def_cfa_offset 24 - 305 .cfi_offset 4, -24 - 306 .cfi_offset 5, -20 - 307 .cfi_offset 6, -16 - 308 .cfi_offset 7, -12 - 309 .cfi_offset 8, -8 - 310 .cfi_offset 14, -4 - 743:../../../Source/third_party/fatfs/src/ff.c **** fs->wflag = 0; - 311 .loc 1 743 0 - 312 005a 0120 movs r0, #1 - 313 005c BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 314 .LVL35: - 315 .L23: - 752:../../../Source/third_party/fatfs/src/ff.c **** } - 316 .loc 1 752 0 - 317 0060 0020 movs r0, #0 - 318 0062 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 319 .LVL36: - 320 .L24: - 321 0066 0020 movs r0, #0 - 322 0068 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 323 .LVL37: - 324 .L25: - 325 006c 0020 movs r0, #0 - 753:../../../Source/third_party/fatfs/src/ff.c **** #endif - 326 .loc 1 753 0 - 327 006e BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 328 .cfi_endproc - 329 .LFE4: - 331 0072 00BF .section .text.move_window,"ax",%progbits - 332 .align 2 - 333 .thumb - 334 .thumb_func - 336 move_window: - 337 .LFB5: - 762:../../../Source/third_party/fatfs/src/ff.c **** if (sector != fs->winsect) { /* Changed current window */ - 338 .loc 1 762 0 - 339 .cfi_startproc - 340 @ args = 0, pretend = 0, frame = 0 - 341 @ frame_needed = 0, uses_anonymous_args = 0 - 342 .LVL38: - 343 0000 70B5 push {r4, r5, r6, lr} - 344 .cfi_def_cfa_offset 16 - 345 .cfi_offset 4, -16 - 346 .cfi_offset 5, -12 - 347 .cfi_offset 6, -8 - 348 .cfi_offset 14, -4 - 763:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY - 349 .loc 1 763 0 - 350 0002 036B ldr r3, [r0, #48] - 351 0004 8B42 cmp r3, r1 - 352 0006 0FD0 beq .L31 - 353 0008 0D46 mov r5, r1 - 354 000a 0446 mov r4, r0 - 765:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; - 355 .loc 1 765 0 - 356 000c FFF7FEFF bl sync_window - 357 .LVL39: - 358 0010 0646 mov r6, r0 - 359 0012 58B9 cbnz r0, .L32 - 768:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; - 360 .loc 1 768 0 - 361 0014 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 - 362 0016 04F13401 add r1, r4, #52 - 363 001a 2A46 mov r2, r5 - 364 001c 0123 movs r3, #1 - 365 001e FFF7FEFF bl disk_read - 366 .LVL40: - 367 0022 28B9 cbnz r0, .L33 - 770:../../../Source/third_party/fatfs/src/ff.c **** } - 368 .loc 1 770 0 - 369 0024 2563 str r5, [r4, #48] - 370 0026 04E0 b .L30 - 371 .LVL41: - 372 .L31: - 773:../../../Source/third_party/fatfs/src/ff.c **** } - 373 .loc 1 773 0 - 374 0028 0026 movs r6, #0 - 375 002a 02E0 b .L30 - 376 .LVL42: - 377 .L32: - 766:../../../Source/third_party/fatfs/src/ff.c **** #endif - 378 .loc 1 766 0 - 379 002c 0126 movs r6, #1 - 380 002e 00E0 b .L30 - 381 .L33: - 769:../../../Source/third_party/fatfs/src/ff.c **** fs->winsect = sector; - 382 .loc 1 769 0 - 383 0030 0126 movs r6, #1 - 384 .LVL43: - 385 .L30: - 774:../../../Source/third_party/fatfs/src/ff.c **** - 386 .loc 1 774 0 - 387 0032 3046 mov r0, r6 - 388 0034 70BD pop {r4, r5, r6, pc} - 389 .cfi_endproc - 390 .LFE5: - 392 0036 00BF .section .text.validate,"ax",%progbits - 393 .align 2 - 394 .thumb - 395 .thumb_func - 397 validate: - 398 .LFB31: -2058:../../../Source/third_party/fatfs/src/ff.c **** -2059:../../../Source/third_party/fatfs/src/ff.c **** -2060:../../../Source/third_party/fatfs/src/ff.c **** -2061:../../../Source/third_party/fatfs/src/ff.c **** -2062:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2063:../../../Source/third_party/fatfs/src/ff.c **** /* Check if the file system object is valid or not */ -2064:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2065:../../../Source/third_party/fatfs/src/ff.c **** -2066:../../../Source/third_party/fatfs/src/ff.c **** static -2067:../../../Source/third_party/fatfs/src/ff.c **** FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occurred */ -2068:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR **path, /* Pointer to pointer to the path name (drive number) */ -2069:../../../Source/third_party/fatfs/src/ff.c **** FATFS **rfs, /* Pointer to pointer to the found file system object */ -2070:../../../Source/third_party/fatfs/src/ff.c **** BYTE wmode /* !=0: Check write protection for write access */ -2071:../../../Source/third_party/fatfs/src/ff.c **** ) -2072:../../../Source/third_party/fatfs/src/ff.c **** { -2073:../../../Source/third_party/fatfs/src/ff.c **** BYTE fmt, b, pi, *tbl; -2074:../../../Source/third_party/fatfs/src/ff.c **** UINT vol; -2075:../../../Source/third_party/fatfs/src/ff.c **** DSTATUS stat; -2076:../../../Source/third_party/fatfs/src/ff.c **** DWORD bsect, fasize, tsect, sysect, nclst, szbfat; -2077:../../../Source/third_party/fatfs/src/ff.c **** WORD nrsv; -2078:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *p = *path; -2079:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs; -2080:../../../Source/third_party/fatfs/src/ff.c **** -2081:../../../Source/third_party/fatfs/src/ff.c **** -2082:../../../Source/third_party/fatfs/src/ff.c **** /* Get logical drive number from the path name */ -2083:../../../Source/third_party/fatfs/src/ff.c **** vol = p[0] - '0'; /* Is there a drive number? */ -2084:../../../Source/third_party/fatfs/src/ff.c **** if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */ -2085:../../../Source/third_party/fatfs/src/ff.c **** p += 2; *path = p; /* Return pointer to the path name */ -2086:../../../Source/third_party/fatfs/src/ff.c **** } else { /* No drive number, use default drive */ -2087:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_RPATH -2088:../../../Source/third_party/fatfs/src/ff.c **** vol = CurrVol; /* Use current drive */ -2089:../../../Source/third_party/fatfs/src/ff.c **** #else -2090:../../../Source/third_party/fatfs/src/ff.c **** vol = 0; /* Use drive 0 */ -2091:../../../Source/third_party/fatfs/src/ff.c **** #endif -2092:../../../Source/third_party/fatfs/src/ff.c **** } -2093:../../../Source/third_party/fatfs/src/ff.c **** -2094:../../../Source/third_party/fatfs/src/ff.c **** /* Check if the file system object is valid or not */ -2095:../../../Source/third_party/fatfs/src/ff.c **** *rfs = 0; -2096:../../../Source/third_party/fatfs/src/ff.c **** if (vol >= _VOLUMES) /* Is the drive number valid? */ -2097:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_DRIVE; -2098:../../../Source/third_party/fatfs/src/ff.c **** fs = FatFs[vol]; /* Get corresponding file system object */ -2099:../../../Source/third_party/fatfs/src/ff.c **** if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ -2100:../../../Source/third_party/fatfs/src/ff.c **** -2101:../../../Source/third_party/fatfs/src/ff.c **** ENTER_FF(fs); /* Lock volume */ -2102:../../../Source/third_party/fatfs/src/ff.c **** -2103:../../../Source/third_party/fatfs/src/ff.c **** *rfs = fs; /* Return pointer to the corresponding file system object */ -2104:../../../Source/third_party/fatfs/src/ff.c **** if (fs->fs_type) { /* If the volume has been mounted */ -2105:../../../Source/third_party/fatfs/src/ff.c **** stat = disk_status(fs->drv); -2106:../../../Source/third_party/fatfs/src/ff.c **** if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed) -2107:../../../Source/third_party/fatfs/src/ff.c **** if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check write protection if needed */ -2108:../../../Source/third_party/fatfs/src/ff.c **** return FR_WRITE_PROTECTED; -2109:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; /* The file system object is valid */ -2110:../../../Source/third_party/fatfs/src/ff.c **** } -2111:../../../Source/third_party/fatfs/src/ff.c **** } -2112:../../../Source/third_party/fatfs/src/ff.c **** -2113:../../../Source/third_party/fatfs/src/ff.c **** /* The file system object is not valid. */ -2114:../../../Source/third_party/fatfs/src/ff.c **** /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */ -2115:../../../Source/third_party/fatfs/src/ff.c **** -2116:../../../Source/third_party/fatfs/src/ff.c **** fs->fs_type = 0; /* Clear the file system object */ -2117:../../../Source/third_party/fatfs/src/ff.c **** fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */ -2118:../../../Source/third_party/fatfs/src/ff.c **** stat = disk_initialize(fs->drv); /* Initialize the physical drive */ -2119:../../../Source/third_party/fatfs/src/ff.c **** if (stat & STA_NOINIT) /* Check if the initialization succeeded */ -2120:../../../Source/third_party/fatfs/src/ff.c **** return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ -2121:../../../Source/third_party/fatfs/src/ff.c **** if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check disk write protection if needed */ -2122:../../../Source/third_party/fatfs/src/ff.c **** return FR_WRITE_PROTECTED; -2123:../../../Source/third_party/fatfs/src/ff.c **** #if _MAX_SS != 512 /* Get disk sector size (variable sector size cfg only) */ -2124:../../../Source/third_party/fatfs/src/ff.c **** if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK) -2125:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; -2126:../../../Source/third_party/fatfs/src/ff.c **** #endif -2127:../../../Source/third_party/fatfs/src/ff.c **** /* Search FAT partition on the drive. Supports only generic partitions, FDISK and SFD. */ -2128:../../../Source/third_party/fatfs/src/ff.c **** fmt = check_fs(fs, bsect = 0); /* Load sector 0 and check if it is an FAT-VBR (in SFD) */ -2129:../../../Source/third_party/fatfs/src/ff.c **** if (LD2PT(vol) && !fmt) fmt = 1; /* Force non-SFD if the volume is forced partition */ -2130:../../../Source/third_party/fatfs/src/ff.c **** if (fmt == 1) { /* Not an FAT-VBR, the physical drive can be partitioned */ -2131:../../../Source/third_party/fatfs/src/ff.c **** /* Check the partition listed in the partition table */ -2132:../../../Source/third_party/fatfs/src/ff.c **** pi = LD2PT(vol); -2133:../../../Source/third_party/fatfs/src/ff.c **** if (pi) pi--; -2134:../../../Source/third_party/fatfs/src/ff.c **** tbl = &fs->win[MBR_Table + pi * SZ_PTE];/* Partition table */ -2135:../../../Source/third_party/fatfs/src/ff.c **** if (tbl[4]) { /* Is the partition existing? */ -2136:../../../Source/third_party/fatfs/src/ff.c **** bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ -2137:../../../Source/third_party/fatfs/src/ff.c **** fmt = check_fs(fs, bsect); /* Check the partition */ -2138:../../../Source/third_party/fatfs/src/ff.c **** } -2139:../../../Source/third_party/fatfs/src/ff.c **** } -2140:../../../Source/third_party/fatfs/src/ff.c **** if (fmt == 3) return FR_DISK_ERR; -2141:../../../Source/third_party/fatfs/src/ff.c **** if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */ -2142:../../../Source/third_party/fatfs/src/ff.c **** -2143:../../../Source/third_party/fatfs/src/ff.c **** /* An FAT volume is found. Following code initializes the file system object */ -2144:../../../Source/third_party/fatfs/src/ff.c **** -2145:../../../Source/third_party/fatfs/src/ff.c **** if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* (BPB_BytsPerSec must be equal to the physical s -2146:../../../Source/third_party/fatfs/src/ff.c **** return FR_NO_FILESYSTEM; -2147:../../../Source/third_party/fatfs/src/ff.c **** -2148:../../../Source/third_party/fatfs/src/ff.c **** fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */ -2149:../../../Source/third_party/fatfs/src/ff.c **** if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32); -2150:../../../Source/third_party/fatfs/src/ff.c **** fs->fsize = fasize; -2151:../../../Source/third_party/fatfs/src/ff.c **** -2152:../../../Source/third_party/fatfs/src/ff.c **** fs->n_fats = b = fs->win[BPB_NumFATs]; /* Number of FAT copies */ -2153:../../../Source/third_party/fatfs/src/ff.c **** if (b != 1 && b != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ -2154:../../../Source/third_party/fatfs/src/ff.c **** fasize *= b; /* Number of sectors for FAT area */ -2155:../../../Source/third_party/fatfs/src/ff.c **** -2156:../../../Source/third_party/fatfs/src/ff.c **** fs->csize = b = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ -2157:../../../Source/third_party/fatfs/src/ff.c **** if (!b || (b & (b - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ -2158:../../../Source/third_party/fatfs/src/ff.c **** -2159:../../../Source/third_party/fatfs/src/ff.c **** fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */ -2160:../../../Source/third_party/fatfs/src/ff.c **** if (fs->n_rootdir % (SS(fs) / SZ_DIR)) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be sector -2161:../../../Source/third_party/fatfs/src/ff.c **** -2162:../../../Source/third_party/fatfs/src/ff.c **** tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */ -2163:../../../Source/third_party/fatfs/src/ff.c **** if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32); -2164:../../../Source/third_party/fatfs/src/ff.c **** -2165:../../../Source/third_party/fatfs/src/ff.c **** nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */ -2166:../../../Source/third_party/fatfs/src/ff.c **** if (!nrsv) return FR_NO_FILESYSTEM; /* (BPB_RsvdSecCnt must not be 0) */ -2167:../../../Source/third_party/fatfs/src/ff.c **** -2168:../../../Source/third_party/fatfs/src/ff.c **** /* Determine the FAT sub type */ -2169:../../../Source/third_party/fatfs/src/ff.c **** sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIR); /* RSV+FAT+DIR */ -2170:../../../Source/third_party/fatfs/src/ff.c **** if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ -2171:../../../Source/third_party/fatfs/src/ff.c **** nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ -2172:../../../Source/third_party/fatfs/src/ff.c **** if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ -2173:../../../Source/third_party/fatfs/src/ff.c **** fmt = FS_FAT12; -2174:../../../Source/third_party/fatfs/src/ff.c **** if (nclst >= MIN_FAT16) fmt = FS_FAT16; -2175:../../../Source/third_party/fatfs/src/ff.c **** if (nclst >= MIN_FAT32) fmt = FS_FAT32; -2176:../../../Source/third_party/fatfs/src/ff.c **** -2177:../../../Source/third_party/fatfs/src/ff.c **** /* Boundaries and Limits */ -2178:../../../Source/third_party/fatfs/src/ff.c **** fs->n_fatent = nclst + 2; /* Number of FAT entries */ -2179:../../../Source/third_party/fatfs/src/ff.c **** fs->volbase = bsect; /* Volume start sector */ -2180:../../../Source/third_party/fatfs/src/ff.c **** fs->fatbase = bsect + nrsv; /* FAT start sector */ -2181:../../../Source/third_party/fatfs/src/ff.c **** fs->database = bsect + sysect; /* Data start sector */ -2182:../../../Source/third_party/fatfs/src/ff.c **** if (fmt == FS_FAT32) { -2183:../../../Source/third_party/fatfs/src/ff.c **** if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ -2184:../../../Source/third_party/fatfs/src/ff.c **** fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ -2185:../../../Source/third_party/fatfs/src/ff.c **** szbfat = fs->n_fatent * 4; /* (Required FAT size) */ -2186:../../../Source/third_party/fatfs/src/ff.c **** } else { -2187:../../../Source/third_party/fatfs/src/ff.c **** if (!fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ -2188:../../../Source/third_party/fatfs/src/ff.c **** fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ -2189:../../../Source/third_party/fatfs/src/ff.c **** szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */ -2190:../../../Source/third_party/fatfs/src/ff.c **** fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); -2191:../../../Source/third_party/fatfs/src/ff.c **** } -2192:../../../Source/third_party/fatfs/src/ff.c **** if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (BPB_FATSz must not be less than required) */ -2193:../../../Source/third_party/fatfs/src/ff.c **** return FR_NO_FILESYSTEM; -2194:../../../Source/third_party/fatfs/src/ff.c **** -2195:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -2196:../../../Source/third_party/fatfs/src/ff.c **** /* Initialize cluster allocation information */ -2197:../../../Source/third_party/fatfs/src/ff.c **** fs->free_clust = 0xFFFFFFFF; -2198:../../../Source/third_party/fatfs/src/ff.c **** fs->last_clust = 0; -2199:../../../Source/third_party/fatfs/src/ff.c **** -2200:../../../Source/third_party/fatfs/src/ff.c **** /* Get fsinfo if available */ -2201:../../../Source/third_party/fatfs/src/ff.c **** if (fmt == FS_FAT32) { -2202:../../../Source/third_party/fatfs/src/ff.c **** fs->fsi_flag = 0; -2203:../../../Source/third_party/fatfs/src/ff.c **** fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo); -2204:../../../Source/third_party/fatfs/src/ff.c **** if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK && -2205:../../../Source/third_party/fatfs/src/ff.c **** LD_WORD(fs->win+BS_55AA) == 0xAA55 && -2206:../../../Source/third_party/fatfs/src/ff.c **** LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 && -2207:../../../Source/third_party/fatfs/src/ff.c **** LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) { -2208:../../../Source/third_party/fatfs/src/ff.c **** fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free); -2209:../../../Source/third_party/fatfs/src/ff.c **** fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count); -2210:../../../Source/third_party/fatfs/src/ff.c **** } -2211:../../../Source/third_party/fatfs/src/ff.c **** } -2212:../../../Source/third_party/fatfs/src/ff.c **** #endif -2213:../../../Source/third_party/fatfs/src/ff.c **** fs->fs_type = fmt; /* FAT sub-type */ -2214:../../../Source/third_party/fatfs/src/ff.c **** fs->id = ++Fsid; /* File system mount ID */ -2215:../../../Source/third_party/fatfs/src/ff.c **** fs->winsect = 0; /* Invalidate sector cache */ -2216:../../../Source/third_party/fatfs/src/ff.c **** fs->wflag = 0; -2217:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_RPATH -2218:../../../Source/third_party/fatfs/src/ff.c **** fs->cdir = 0; /* Current directory (root dir) */ -2219:../../../Source/third_party/fatfs/src/ff.c **** #endif -2220:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_LOCK /* Clear file lock semaphores */ -2221:../../../Source/third_party/fatfs/src/ff.c **** clear_lock(fs); -2222:../../../Source/third_party/fatfs/src/ff.c **** #endif -2223:../../../Source/third_party/fatfs/src/ff.c **** -2224:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; -2225:../../../Source/third_party/fatfs/src/ff.c **** } -2226:../../../Source/third_party/fatfs/src/ff.c **** -2227:../../../Source/third_party/fatfs/src/ff.c **** -2228:../../../Source/third_party/fatfs/src/ff.c **** -2229:../../../Source/third_party/fatfs/src/ff.c **** -2230:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2231:../../../Source/third_party/fatfs/src/ff.c **** /* Check if the file/dir object is valid or not */ -2232:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2233:../../../Source/third_party/fatfs/src/ff.c **** -2234:../../../Source/third_party/fatfs/src/ff.c **** static -2235:../../../Source/third_party/fatfs/src/ff.c **** FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ -2236:../../../Source/third_party/fatfs/src/ff.c **** void* obj /* Pointer to the object FIL/DIR to check validity */ -2237:../../../Source/third_party/fatfs/src/ff.c **** ) -2238:../../../Source/third_party/fatfs/src/ff.c **** { - 399 .loc 1 2238 0 - 400 .cfi_startproc - 401 @ args = 0, pretend = 0, frame = 0 - 402 @ frame_needed = 0, uses_anonymous_args = 0 - 403 .LVL44: -2239:../../../Source/third_party/fatfs/src/ff.c **** FIL *fil = (FIL*)obj; /* Assuming offset of fs and id in the FIL/DIR is identical */ -2240:../../../Source/third_party/fatfs/src/ff.c **** -2241:../../../Source/third_party/fatfs/src/ff.c **** -2242:../../../Source/third_party/fatfs/src/ff.c **** if (!fil || !fil->fs || !fil->fs->fs_type || fil->fs->id != fil->id) - 404 .loc 1 2242 0 - 405 0000 90B1 cbz r0, .L37 -2238:../../../Source/third_party/fatfs/src/ff.c **** FIL *fil = (FIL*)obj; /* Assuming offset of fs and id in the FIL/DIR is identical */ - 406 .loc 1 2238 0 discriminator 1 - 407 0002 08B5 push {r3, lr} - 408 .cfi_def_cfa_offset 8 - 409 .cfi_offset 3, -8 - 410 .cfi_offset 14, -4 - 411 .loc 1 2242 0 discriminator 1 - 412 0004 0368 ldr r3, [r0] - 413 0006 8BB1 cbz r3, .L38 - 414 .loc 1 2242 0 is_stmt 0 discriminator 2 - 415 0008 1978 ldrb r1, [r3] @ zero_extendqisi2 - 416 000a 89B1 cbz r1, .L39 - 417 .loc 1 2242 0 discriminator 3 - 418 000c D988 ldrh r1, [r3, #6] - 419 000e 8288 ldrh r2, [r0, #4] - 420 0010 9142 cmp r1, r2 - 421 0012 0FD1 bne .L40 -2243:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_OBJECT; -2244:../../../Source/third_party/fatfs/src/ff.c **** -2245:../../../Source/third_party/fatfs/src/ff.c **** ENTER_FF(fil->fs); /* Lock file system */ -2246:../../../Source/third_party/fatfs/src/ff.c **** -2247:../../../Source/third_party/fatfs/src/ff.c **** if (disk_status(fil->fs->drv) & STA_NOINIT) - 422 .loc 1 2247 0 is_stmt 1 - 423 0014 5878 ldrb r0, [r3, #1] @ zero_extendqisi2 - 424 .LVL45: - 425 0016 FFF7FEFF bl disk_status - 426 .LVL46: - 427 001a 00F00100 and r0, r0, #1 -2248:../../../Source/third_party/fatfs/src/ff.c **** return FR_NOT_READY; -2249:../../../Source/third_party/fatfs/src/ff.c **** -2250:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; - 428 .loc 1 2250 0 - 429 001e 0028 cmp r0, #0 - 430 0020 14BF ite ne - 431 0022 0320 movne r0, #3 - 432 0024 0020 moveq r0, #0 - 433 0026 08BD pop {r3, pc} - 434 .LVL47: - 435 .L37: - 436 .cfi_def_cfa_offset 0 - 437 .cfi_restore 3 - 438 .cfi_restore 14 -2243:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_OBJECT; - 439 .loc 1 2243 0 - 440 0028 0920 movs r0, #9 - 441 .LVL48: -2251:../../../Source/third_party/fatfs/src/ff.c **** } - 442 .loc 1 2251 0 - 443 002a 7047 bx lr - 444 .LVL49: - 445 .L38: - 446 .cfi_def_cfa_offset 8 - 447 .cfi_offset 3, -8 - 448 .cfi_offset 14, -4 -2243:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_OBJECT; - 449 .loc 1 2243 0 - 450 002c 0920 movs r0, #9 - 451 .LVL50: - 452 002e 08BD pop {r3, pc} - 453 .LVL51: - 454 .L39: - 455 0030 0920 movs r0, #9 - 456 .LVL52: - 457 0032 08BD pop {r3, pc} - 458 .LVL53: - 459 .L40: - 460 0034 0920 movs r0, #9 - 461 .LVL54: - 462 .loc 1 2251 0 - 463 0036 08BD pop {r3, pc} - 464 .cfi_endproc - 465 .LFE31: - 467 .section .text.chk_mounted,"ax",%progbits - 468 .align 2 - 469 .thumb - 470 .thumb_func - 472 chk_mounted: - 473 .LFB30: -2072:../../../Source/third_party/fatfs/src/ff.c **** BYTE fmt, b, pi, *tbl; - 474 .loc 1 2072 0 - 475 .cfi_startproc - 476 @ args = 0, pretend = 0, frame = 0 - 477 @ frame_needed = 0, uses_anonymous_args = 0 - 478 .LVL55: - 479 0000 F8B5 push {r3, r4, r5, r6, r7, lr} - 480 .cfi_def_cfa_offset 24 - 481 .cfi_offset 3, -24 - 482 .cfi_offset 4, -20 - 483 .cfi_offset 5, -16 - 484 .cfi_offset 6, -12 - 485 .cfi_offset 7, -8 - 486 .cfi_offset 14, -4 -2078:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs; - 487 .loc 1 2078 0 - 488 0002 0468 ldr r4, [r0] - 489 .LVL56: -2083:../../../Source/third_party/fatfs/src/ff.c **** if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */ - 490 .loc 1 2083 0 - 491 0004 2378 ldrb r3, [r4] @ zero_extendqisi2 - 492 0006 303B subs r3, r3, #48 - 493 .LVL57: -2084:../../../Source/third_party/fatfs/src/ff.c **** p += 2; *path = p; /* Return pointer to the path name */ - 494 .loc 1 2084 0 - 495 0008 092B cmp r3, #9 - 496 000a 00F28D81 bhi .L44 -2084:../../../Source/third_party/fatfs/src/ff.c **** p += 2; *path = p; /* Return pointer to the path name */ - 497 .loc 1 2084 0 is_stmt 0 discriminator 1 - 498 000e 6578 ldrb r5, [r4, #1] @ zero_extendqisi2 - 499 0010 3A2D cmp r5, #58 - 500 0012 40F08981 bne .L44 - 501 .LVL58: -2085:../../../Source/third_party/fatfs/src/ff.c **** } else { /* No drive number, use default drive */ - 502 .loc 1 2085 0 is_stmt 1 - 503 0016 0234 adds r4, r4, #2 - 504 .LVL59: - 505 0018 0460 str r4, [r0] -2095:../../../Source/third_party/fatfs/src/ff.c **** if (vol >= _VOLUMES) /* Is the drive number valid? */ - 506 .loc 1 2095 0 - 507 001a 0020 movs r0, #0 - 508 .LVL60: - 509 001c 0860 str r0, [r1] -2096:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_DRIVE; - 510 .loc 1 2096 0 - 511 001e 002B cmp r3, #0 - 512 0020 40F05A81 bne .L62 - 513 .LVL61: - 514 .L58: -2098:../../../Source/third_party/fatfs/src/ff.c **** if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ - 515 .loc 1 2098 0 - 516 0024 C94B ldr r3, .L92 - 517 0026 1C68 ldr r4, [r3] - 518 .LVL62: -2099:../../../Source/third_party/fatfs/src/ff.c **** - 519 .loc 1 2099 0 - 520 0028 002C cmp r4, #0 - 521 002a 00F05781 beq .L63 - 522 002e 1546 mov r5, r2 -2103:../../../Source/third_party/fatfs/src/ff.c **** if (fs->fs_type) { /* If the volume has been mounted */ - 523 .loc 1 2103 0 - 524 0030 0C60 str r4, [r1] -2104:../../../Source/third_party/fatfs/src/ff.c **** stat = disk_status(fs->drv); - 525 .loc 1 2104 0 - 526 0032 2378 ldrb r3, [r4] @ zero_extendqisi2 - 527 0034 83B1 cbz r3, .L46 -2105:../../../Source/third_party/fatfs/src/ff.c **** if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed) - 528 .loc 1 2105 0 - 529 0036 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 - 530 0038 FFF7FEFF bl disk_status - 531 .LVL63: -2106:../../../Source/third_party/fatfs/src/ff.c **** if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check write protection if needed */ - 532 .loc 1 2106 0 - 533 003c 10F0010F tst r0, #1 - 534 0040 0AD1 bne .L46 -2107:../../../Source/third_party/fatfs/src/ff.c **** return FR_WRITE_PROTECTED; - 535 .loc 1 2107 0 - 536 0042 002D cmp r5, #0 - 537 0044 00F04C81 beq .L64 -2107:../../../Source/third_party/fatfs/src/ff.c **** return FR_WRITE_PROTECTED; - 538 .loc 1 2107 0 is_stmt 0 discriminator 1 - 539 0048 00F00400 and r0, r0, #4 - 540 .LVL64: - 541 004c C0B2 uxtb r0, r0 -2108:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; /* The file system object is valid */ - 542 .loc 1 2108 0 is_stmt 1 discriminator 1 - 543 004e 0028 cmp r0, #0 - 544 0050 0CBF ite eq - 545 0052 0020 moveq r0, #0 - 546 0054 0A20 movne r0, #10 - 547 0056 F8BD pop {r3, r4, r5, r6, r7, pc} - 548 .LVL65: - 549 .L46: -2116:../../../Source/third_party/fatfs/src/ff.c **** fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */ - 550 .loc 1 2116 0 - 551 0058 0020 movs r0, #0 - 552 005a 2070 strb r0, [r4] -2117:../../../Source/third_party/fatfs/src/ff.c **** stat = disk_initialize(fs->drv); /* Initialize the physical drive */ - 553 .loc 1 2117 0 - 554 005c 6070 strb r0, [r4, #1] -2118:../../../Source/third_party/fatfs/src/ff.c **** if (stat & STA_NOINIT) /* Check if the initialization succeeded */ - 555 .loc 1 2118 0 - 556 005e FFF7FEFF bl disk_initialize - 557 .LVL66: -2119:../../../Source/third_party/fatfs/src/ff.c **** return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ - 558 .loc 1 2119 0 - 559 0062 10F0010F tst r0, #1 - 560 0066 40F03D81 bne .L66 -2121:../../../Source/third_party/fatfs/src/ff.c **** return FR_WRITE_PROTECTED; - 561 .loc 1 2121 0 - 562 006a 1DB1 cbz r5, .L47 -2121:../../../Source/third_party/fatfs/src/ff.c **** return FR_WRITE_PROTECTED; - 563 .loc 1 2121 0 is_stmt 0 discriminator 1 - 564 006c 10F0040F tst r0, #4 - 565 0070 40F03A81 bne .L67 - 566 .L47: - 567 .LVL67: -2128:../../../Source/third_party/fatfs/src/ff.c **** if (LD2PT(vol) && !fmt) fmt = 1; /* Force non-SFD if the volume is forced partition */ - 568 .loc 1 2128 0 is_stmt 1 - 569 0074 2046 mov r0, r4 - 570 .LVL68: - 571 0076 0021 movs r1, #0 - 572 0078 FFF7FEFF bl check_fs - 573 .LVL69: -2130:../../../Source/third_party/fatfs/src/ff.c **** /* Check the partition listed in the partition table */ - 574 .loc 1 2130 0 - 575 007c 0128 cmp r0, #1 - 576 007e 17D1 bne .L68 - 577 .LVL70: -2135:../../../Source/third_party/fatfs/src/ff.c **** bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ - 578 .loc 1 2135 0 - 579 0080 94F8F631 ldrb r3, [r4, #502] @ zero_extendqisi2 - 580 0084 002B cmp r3, #0 - 581 0086 00F03181 beq .L69 -2136:../../../Source/third_party/fatfs/src/ff.c **** fmt = check_fs(fs, bsect); /* Check the partition */ - 582 .loc 1 2136 0 - 583 008a 94F8FD21 ldrb r2, [r4, #509] @ zero_extendqisi2 - 584 008e 94F8FC31 ldrb r3, [r4, #508] @ zero_extendqisi2 - 585 0092 1B04 lsls r3, r3, #16 - 586 0094 43EA0263 orr r3, r3, r2, lsl #24 - 587 0098 94F8FA51 ldrb r5, [r4, #506] @ zero_extendqisi2 - 588 009c 2B43 orrs r3, r3, r5 - 589 009e 94F8FB51 ldrb r5, [r4, #507] @ zero_extendqisi2 - 590 00a2 43EA0525 orr r5, r3, r5, lsl #8 - 591 .LVL71: -2137:../../../Source/third_party/fatfs/src/ff.c **** } - 592 .loc 1 2137 0 - 593 00a6 2046 mov r0, r4 - 594 .LVL72: - 595 00a8 2946 mov r1, r5 - 596 00aa FFF7FEFF bl check_fs - 597 .LVL73: - 598 00ae 00E0 b .L48 - 599 .LVL74: - 600 .L68: -2128:../../../Source/third_party/fatfs/src/ff.c **** if (LD2PT(vol) && !fmt) fmt = 1; /* Force non-SFD if the volume is forced partition */ - 601 .loc 1 2128 0 - 602 00b0 0025 movs r5, #0 - 603 .LVL75: - 604 .L48: -2140:../../../Source/third_party/fatfs/src/ff.c **** if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */ - 605 .loc 1 2140 0 - 606 00b2 0328 cmp r0, #3 - 607 00b4 00F01C81 beq .L70 -2141:../../../Source/third_party/fatfs/src/ff.c **** - 608 .loc 1 2141 0 - 609 00b8 0028 cmp r0, #0 - 610 00ba 40F01B81 bne .L71 -2145:../../../Source/third_party/fatfs/src/ff.c **** return FR_NO_FILESYSTEM; - 611 .loc 1 2145 0 - 612 00be 94F84020 ldrb r2, [r4, #64] @ zero_extendqisi2 - 613 00c2 94F83F30 ldrb r3, [r4, #63] @ zero_extendqisi2 - 614 00c6 43EA0223 orr r3, r3, r2, lsl #8 - 615 00ca 1BB2 sxth r3, r3 - 616 00cc B3F5007F cmp r3, #512 - 617 00d0 40F01281 bne .L72 -2148:../../../Source/third_party/fatfs/src/ff.c **** if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32); - 618 .loc 1 2148 0 - 619 00d4 94F84B00 ldrb r0, [r4, #75] @ zero_extendqisi2 - 620 .LVL76: - 621 00d8 94F84A30 ldrb r3, [r4, #74] @ zero_extendqisi2 - 622 .LVL77: -2149:../../../Source/third_party/fatfs/src/ff.c **** fs->fsize = fasize; - 623 .loc 1 2149 0 - 624 00dc 53EA0020 orrs r0, r3, r0, lsl #8 - 625 .LVL78: - 626 00e0 0DD1 bne .L49 -2149:../../../Source/third_party/fatfs/src/ff.c **** fs->fsize = fasize; - 627 .loc 1 2149 0 is_stmt 0 discriminator 1 - 628 00e2 94F85B20 ldrb r2, [r4, #91] @ zero_extendqisi2 - 629 00e6 94F85A30 ldrb r3, [r4, #90] @ zero_extendqisi2 - 630 00ea 1B04 lsls r3, r3, #16 - 631 00ec 43EA0263 orr r3, r3, r2, lsl #24 - 632 00f0 94F85800 ldrb r0, [r4, #88] @ zero_extendqisi2 - 633 .LVL79: - 634 00f4 0343 orrs r3, r3, r0 - 635 00f6 94F85900 ldrb r0, [r4, #89] @ zero_extendqisi2 - 636 00fa 43EA0020 orr r0, r3, r0, lsl #8 - 637 .LVL80: - 638 .L49: -2150:../../../Source/third_party/fatfs/src/ff.c **** - 639 .loc 1 2150 0 is_stmt 1 - 640 00fe E061 str r0, [r4, #28] -2152:../../../Source/third_party/fatfs/src/ff.c **** if (b != 1 && b != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ - 641 .loc 1 2152 0 - 642 0100 94F84470 ldrb r7, [r4, #68] @ zero_extendqisi2 - 643 .LVL81: - 644 0104 E770 strb r7, [r4, #3] -2153:../../../Source/third_party/fatfs/src/ff.c **** fasize *= b; /* Number of sectors for FAT area */ - 645 .loc 1 2153 0 - 646 0106 7B1E subs r3, r7, #1 - 647 0108 DBB2 uxtb r3, r3 - 648 010a 012B cmp r3, #1 - 649 010c 00F2F680 bhi .L73 - 650 .LVL82: -2156:../../../Source/third_party/fatfs/src/ff.c **** if (!b || (b & (b - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ - 651 .loc 1 2156 0 - 652 0110 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 - 653 .LVL83: - 654 0114 A370 strb r3, [r4, #2] -2157:../../../Source/third_party/fatfs/src/ff.c **** - 655 .loc 1 2157 0 - 656 0116 002B cmp r3, #0 - 657 0118 00F0F280 beq .L74 -2157:../../../Source/third_party/fatfs/src/ff.c **** - 658 .loc 1 2157 0 is_stmt 0 discriminator 2 - 659 011c 5A1E subs r2, r3, #1 - 660 011e 1A42 tst r2, r3 - 661 0120 40F0F080 bne .L75 -2159:../../../Source/third_party/fatfs/src/ff.c **** if (fs->n_rootdir % (SS(fs) / SZ_DIR)) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be sector - 662 .loc 1 2159 0 is_stmt 1 - 663 0124 94F84660 ldrb r6, [r4, #70] @ zero_extendqisi2 - 664 0128 94F84520 ldrb r2, [r4, #69] @ zero_extendqisi2 - 665 012c 42EA0626 orr r6, r2, r6, lsl #8 - 666 0130 2681 strh r6, [r4, #8] @ movhi -2160:../../../Source/third_party/fatfs/src/ff.c **** - 667 .loc 1 2160 0 - 668 0132 16F00F0F tst r6, #15 - 669 0136 40F0E780 bne .L76 -2162:../../../Source/third_party/fatfs/src/ff.c **** if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32); - 670 .loc 1 2162 0 - 671 013a 94F84810 ldrb r1, [r4, #72] @ zero_extendqisi2 - 672 013e 94F84720 ldrb r2, [r4, #71] @ zero_extendqisi2 - 673 .LVL84: -2163:../../../Source/third_party/fatfs/src/ff.c **** - 674 .loc 1 2163 0 - 675 0142 52EA0122 orrs r2, r2, r1, lsl #8 - 676 .LVL85: - 677 0146 0DD1 bne .L50 -2163:../../../Source/third_party/fatfs/src/ff.c **** - 678 .loc 1 2163 0 is_stmt 0 discriminator 1 - 679 0148 94F85710 ldrb r1, [r4, #87] @ zero_extendqisi2 - 680 014c 94F85620 ldrb r2, [r4, #86] @ zero_extendqisi2 - 681 .LVL86: - 682 0150 1204 lsls r2, r2, #16 - 683 0152 42EA0161 orr r1, r2, r1, lsl #24 - 684 0156 94F85420 ldrb r2, [r4, #84] @ zero_extendqisi2 - 685 015a 0A43 orrs r2, r2, r1 - 686 015c 94F85510 ldrb r1, [r4, #85] @ zero_extendqisi2 - 687 0160 42EA0122 orr r2, r2, r1, lsl #8 - 688 .LVL87: - 689 .L50: -2165:../../../Source/third_party/fatfs/src/ff.c **** if (!nrsv) return FR_NO_FILESYSTEM; /* (BPB_RsvdSecCnt must not be 0) */ - 690 .loc 1 2165 0 is_stmt 1 - 691 0164 94F843E0 ldrb lr, [r4, #67] @ zero_extendqisi2 - 692 0168 94F84210 ldrb r1, [r4, #66] @ zero_extendqisi2 - 693 .LVL88: -2166:../../../Source/third_party/fatfs/src/ff.c **** - 694 .loc 1 2166 0 - 695 016c 51EA0E21 orrs r1, r1, lr, lsl #8 - 696 .LVL89: - 697 0170 00F0CC80 beq .L77 -2154:../../../Source/third_party/fatfs/src/ff.c **** - 698 .loc 1 2154 0 - 699 0174 07FB00F7 mul r7, r7, r0 - 700 .LVL90: - 701 0178 01EB161C add ip, r1, r6, lsr #4 -2169:../../../Source/third_party/fatfs/src/ff.c **** if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ - 702 .loc 1 2169 0 - 703 017c BC44 add ip, ip, r7 - 704 .LVL91: -2170:../../../Source/third_party/fatfs/src/ff.c **** nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ - 705 .loc 1 2170 0 - 706 017e 6245 cmp r2, ip - 707 0180 C0F0C680 bcc .L78 -2171:../../../Source/third_party/fatfs/src/ff.c **** if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ - 708 .loc 1 2171 0 - 709 0184 CCEB0202 rsb r2, ip, r2 - 710 .LVL92: - 711 0188 B2FBF3F3 udiv r3, r2, r3 - 712 .LVL93: -2172:../../../Source/third_party/fatfs/src/ff.c **** fmt = FS_FAT12; - 713 .loc 1 2172 0 - 714 018c 002B cmp r3, #0 - 715 018e 00F0C180 beq .L79 - 716 .LVL94: -2174:../../../Source/third_party/fatfs/src/ff.c **** if (nclst >= MIN_FAT32) fmt = FS_FAT32; - 717 .loc 1 2174 0 - 718 0192 40F6F57E movw lr, #4085 - 719 .LVL95: - 720 0196 7345 cmp r3, lr - 721 0198 94BF ite ls - 722 019a 4FF0010E movls lr, #1 - 723 019e 4FF0020E movhi lr, #2 - 724 .LVL96: -2175:../../../Source/third_party/fatfs/src/ff.c **** - 725 .loc 1 2175 0 - 726 01a2 4FF6F572 movw r2, #65525 - 727 01a6 9342 cmp r3, r2 - 728 01a8 00F2C180 bhi .L52 -2178:../../../Source/third_party/fatfs/src/ff.c **** fs->volbase = bsect; /* Volume start sector */ - 729 .loc 1 2178 0 - 730 01ac 0233 adds r3, r3, #2 - 731 .LVL97: - 732 01ae A361 str r3, [r4, #24] -2179:../../../Source/third_party/fatfs/src/ff.c **** fs->fatbase = bsect + nrsv; /* FAT start sector */ - 733 .loc 1 2179 0 - 734 01b0 2562 str r5, [r4, #32] -2180:../../../Source/third_party/fatfs/src/ff.c **** fs->database = bsect + sysect; /* Data start sector */ - 735 .loc 1 2180 0 - 736 01b2 2944 add r1, r1, r5 - 737 01b4 6162 str r1, [r4, #36] -2181:../../../Source/third_party/fatfs/src/ff.c **** if (fmt == FS_FAT32) { - 738 .loc 1 2181 0 - 739 01b6 0CEB0502 add r2, ip, r5 - 740 01ba E262 str r2, [r4, #44] -2182:../../../Source/third_party/fatfs/src/ff.c **** if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ - 741 .loc 1 2182 0 - 742 01bc BEF1030F cmp lr, #3 - 743 01c0 19D1 bne .L53 - 744 .LVL98: - 745 .L59: -2183:../../../Source/third_party/fatfs/src/ff.c **** fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ - 746 .loc 1 2183 0 - 747 01c2 002E cmp r6, #0 - 748 01c4 40F0A880 bne .L81 -2184:../../../Source/third_party/fatfs/src/ff.c **** szbfat = fs->n_fatent * 4; /* (Required FAT size) */ - 749 .loc 1 2184 0 - 750 01c8 94F86310 ldrb r1, [r4, #99] @ zero_extendqisi2 - 751 01cc 94F86220 ldrb r2, [r4, #98] @ zero_extendqisi2 - 752 01d0 1204 lsls r2, r2, #16 - 753 01d2 42EA0161 orr r1, r2, r1, lsl #24 - 754 01d6 94F86020 ldrb r2, [r4, #96] @ zero_extendqisi2 - 755 01da 0A43 orrs r2, r2, r1 - 756 01dc 94F86110 ldrb r1, [r4, #97] @ zero_extendqisi2 - 757 01e0 42EA0122 orr r2, r2, r1, lsl #8 - 758 01e4 A262 str r2, [r4, #40] - 759 .LVL99: -2185:../../../Source/third_party/fatfs/src/ff.c **** } else { - 760 .loc 1 2185 0 - 761 01e6 9B00 lsls r3, r3, #2 - 762 .LVL100: -2192:../../../Source/third_party/fatfs/src/ff.c **** return FR_NO_FILESYSTEM; - 763 .loc 1 2192 0 - 764 01e8 03F2FF13 addw r3, r3, #511 - 765 .LVL101: - 766 01ec B0EB532F cmp r0, r3, lsr #9 - 767 01f0 C0F09480 bcc .L82 - 768 01f4 BAE0 b .L89 - 769 .LVL102: - 770 .L53: -2187:../../../Source/third_party/fatfs/src/ff.c **** fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ - 771 .loc 1 2187 0 - 772 01f6 002E cmp r6, #0 - 773 01f8 00F09280 beq .L83 -2188:../../../Source/third_party/fatfs/src/ff.c **** szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */ - 774 .loc 1 2188 0 - 775 01fc 3944 add r1, r1, r7 - 776 01fe A162 str r1, [r4, #40] -2190:../../../Source/third_party/fatfs/src/ff.c **** } - 777 .loc 1 2190 0 - 778 0200 BEF1020F cmp lr, #2 - 779 0204 0FBF iteee eq - 780 0206 5B00 lsleq r3, r3, #1 - 781 .LVL103: - 782 0208 03EB4302 addne r2, r3, r3, lsl #1 - 783 020c 03F00103 andne r3, r3, #1 - 784 0210 03EB5203 addne r3, r3, r2, lsr #1 - 785 0214 A4E0 b .L56 - 786 .LVL104: - 787 .L61: -2205:../../../Source/third_party/fatfs/src/ff.c **** LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 && - 788 .loc 1 2205 0 discriminator 1 - 789 0216 94F83322 ldrb r2, [r4, #563] @ zero_extendqisi2 - 790 021a 94F83232 ldrb r3, [r4, #562] @ zero_extendqisi2 - 791 021e 43EA0223 orr r3, r3, r2, lsl #8 -2204:../../../Source/third_party/fatfs/src/ff.c **** LD_WORD(fs->win+BS_55AA) == 0xAA55 && - 792 .loc 1 2204 0 discriminator 1 - 793 0222 1BB2 sxth r3, r3 - 794 0224 4A4A ldr r2, .L92+4 - 795 0226 9342 cmp r3, r2 - 796 0228 42D1 bne .L84 -2206:../../../Source/third_party/fatfs/src/ff.c **** LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) { - 797 .loc 1 2206 0 - 798 022a 94F83720 ldrb r2, [r4, #55] @ zero_extendqisi2 - 799 022e 94F83630 ldrb r3, [r4, #54] @ zero_extendqisi2 - 800 0232 1B04 lsls r3, r3, #16 - 801 0234 43EA0262 orr r2, r3, r2, lsl #24 - 802 0238 94F83430 ldrb r3, [r4, #52] @ zero_extendqisi2 - 803 023c 1343 orrs r3, r3, r2 - 804 023e 94F83520 ldrb r2, [r4, #53] @ zero_extendqisi2 - 805 0242 43EA0223 orr r3, r3, r2, lsl #8 -2205:../../../Source/third_party/fatfs/src/ff.c **** LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 && - 806 .loc 1 2205 0 - 807 0246 434A ldr r2, .L92+8 - 808 0248 9342 cmp r3, r2 - 809 024a 34D1 bne .L85 -2207:../../../Source/third_party/fatfs/src/ff.c **** fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free); - 810 .loc 1 2207 0 - 811 024c 94F81B22 ldrb r2, [r4, #539] @ zero_extendqisi2 - 812 0250 94F81A32 ldrb r3, [r4, #538] @ zero_extendqisi2 - 813 0254 1B04 lsls r3, r3, #16 - 814 0256 43EA0262 orr r2, r3, r2, lsl #24 - 815 025a 94F81832 ldrb r3, [r4, #536] @ zero_extendqisi2 - 816 025e 1343 orrs r3, r3, r2 - 817 0260 94F81922 ldrb r2, [r4, #537] @ zero_extendqisi2 - 818 0264 43EA0223 orr r3, r3, r2, lsl #8 -2206:../../../Source/third_party/fatfs/src/ff.c **** LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) { - 819 .loc 1 2206 0 - 820 0268 3B4A ldr r2, .L92+12 - 821 026a 9342 cmp r3, r2 - 822 026c 26D1 bne .L86 -2208:../../../Source/third_party/fatfs/src/ff.c **** fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count); - 823 .loc 1 2208 0 - 824 026e 94F82322 ldrb r2, [r4, #547] @ zero_extendqisi2 - 825 0272 94F82232 ldrb r3, [r4, #546] @ zero_extendqisi2 - 826 0276 1B04 lsls r3, r3, #16 - 827 0278 43EA0262 orr r2, r3, r2, lsl #24 - 828 027c 94F82032 ldrb r3, [r4, #544] @ zero_extendqisi2 - 829 0280 1343 orrs r3, r3, r2 - 830 0282 94F82122 ldrb r2, [r4, #545] @ zero_extendqisi2 - 831 0286 43EA0223 orr r3, r3, r2, lsl #8 - 832 028a E360 str r3, [r4, #12] -2209:../../../Source/third_party/fatfs/src/ff.c **** } - 833 .loc 1 2209 0 - 834 028c 94F81F22 ldrb r2, [r4, #543] @ zero_extendqisi2 - 835 0290 94F81E32 ldrb r3, [r4, #542] @ zero_extendqisi2 - 836 0294 1B04 lsls r3, r3, #16 - 837 0296 43EA0262 orr r2, r3, r2, lsl #24 - 838 029a 94F81C32 ldrb r3, [r4, #540] @ zero_extendqisi2 - 839 029e 1343 orrs r3, r3, r2 - 840 02a0 94F81D22 ldrb r2, [r4, #541] @ zero_extendqisi2 - 841 02a4 43EA0223 orr r3, r3, r2, lsl #8 - 842 02a8 2361 str r3, [r4, #16] - 843 02aa 4FF0030E mov lr, #3 - 844 02ae 07E0 b .L57 - 845 .L84: - 846 02b0 4FF0030E mov lr, #3 - 847 02b4 04E0 b .L57 - 848 .L85: - 849 02b6 4FF0030E mov lr, #3 - 850 02ba 01E0 b .L57 - 851 .L86: - 852 02bc 4FF0030E mov lr, #3 - 853 .LVL105: - 854 .L57: -2213:../../../Source/third_party/fatfs/src/ff.c **** fs->id = ++Fsid; /* File system mount ID */ - 855 .loc 1 2213 0 - 856 02c0 84F800E0 strb lr, [r4] -2214:../../../Source/third_party/fatfs/src/ff.c **** fs->winsect = 0; /* Invalidate sector cache */ - 857 .loc 1 2214 0 - 858 02c4 254A ldr r2, .L92+16 - 859 02c6 1388 ldrh r3, [r2] - 860 02c8 0133 adds r3, r3, #1 - 861 02ca 9BB2 uxth r3, r3 - 862 02cc 1380 strh r3, [r2] @ movhi - 863 02ce E380 strh r3, [r4, #6] @ movhi -2215:../../../Source/third_party/fatfs/src/ff.c **** fs->wflag = 0; - 864 .loc 1 2215 0 - 865 02d0 0020 movs r0, #0 - 866 02d2 2063 str r0, [r4, #48] -2216:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_RPATH - 867 .loc 1 2216 0 - 868 02d4 2071 strb r0, [r4, #4] -2224:../../../Source/third_party/fatfs/src/ff.c **** } - 869 .loc 1 2224 0 - 870 02d6 F8BD pop {r3, r4, r5, r6, r7, pc} - 871 .LVL106: - 872 .L62: -2097:../../../Source/third_party/fatfs/src/ff.c **** fs = FatFs[vol]; /* Get corresponding file system object */ - 873 .loc 1 2097 0 - 874 02d8 0B20 movs r0, #11 - 875 02da F8BD pop {r3, r4, r5, r6, r7, pc} - 876 .LVL107: - 877 .L63: -2099:../../../Source/third_party/fatfs/src/ff.c **** - 878 .loc 1 2099 0 - 879 02dc 0C20 movs r0, #12 - 880 02de F8BD pop {r3, r4, r5, r6, r7, pc} - 881 .LVL108: - 882 .L64: -2109:../../../Source/third_party/fatfs/src/ff.c **** } - 883 .loc 1 2109 0 - 884 02e0 0020 movs r0, #0 - 885 .LVL109: - 886 02e2 F8BD pop {r3, r4, r5, r6, r7, pc} - 887 .LVL110: - 888 .L66: -2120:../../../Source/third_party/fatfs/src/ff.c **** if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check disk write protection if needed */ - 889 .loc 1 2120 0 - 890 02e4 0320 movs r0, #3 - 891 .LVL111: - 892 02e6 F8BD pop {r3, r4, r5, r6, r7, pc} - 893 .LVL112: - 894 .L67: -2122:../../../Source/third_party/fatfs/src/ff.c **** #if _MAX_SS != 512 /* Get disk sector size (variable sector size cfg only) */ - 895 .loc 1 2122 0 - 896 02e8 0A20 movs r0, #10 - 897 .LVL113: - 898 02ea F8BD pop {r3, r4, r5, r6, r7, pc} - 899 .LVL114: - 900 .L69: -2141:../../../Source/third_party/fatfs/src/ff.c **** - 901 .loc 1 2141 0 - 902 02ec 0D20 movs r0, #13 - 903 .LVL115: - 904 02ee F8BD pop {r3, r4, r5, r6, r7, pc} - 905 .LVL116: - 906 .L70: -2140:../../../Source/third_party/fatfs/src/ff.c **** if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */ - 907 .loc 1 2140 0 - 908 02f0 0120 movs r0, #1 - 909 .LVL117: - 910 02f2 F8BD pop {r3, r4, r5, r6, r7, pc} - 911 .LVL118: - 912 .L71: -2141:../../../Source/third_party/fatfs/src/ff.c **** - 913 .loc 1 2141 0 - 914 02f4 0D20 movs r0, #13 - 915 .LVL119: - 916 02f6 F8BD pop {r3, r4, r5, r6, r7, pc} - 917 .LVL120: - 918 .L72: -2146:../../../Source/third_party/fatfs/src/ff.c **** - 919 .loc 1 2146 0 - 920 02f8 0D20 movs r0, #13 - 921 .LVL121: - 922 02fa F8BD pop {r3, r4, r5, r6, r7, pc} - 923 .LVL122: - 924 .L73: -2153:../../../Source/third_party/fatfs/src/ff.c **** fasize *= b; /* Number of sectors for FAT area */ - 925 .loc 1 2153 0 - 926 02fc 0D20 movs r0, #13 - 927 .LVL123: - 928 02fe F8BD pop {r3, r4, r5, r6, r7, pc} - 929 .LVL124: - 930 .L74: -2157:../../../Source/third_party/fatfs/src/ff.c **** - 931 .loc 1 2157 0 - 932 0300 0D20 movs r0, #13 - 933 .LVL125: - 934 0302 F8BD pop {r3, r4, r5, r6, r7, pc} - 935 .LVL126: - 936 .L75: - 937 0304 0D20 movs r0, #13 - 938 .LVL127: - 939 0306 F8BD pop {r3, r4, r5, r6, r7, pc} - 940 .LVL128: - 941 .L76: -2160:../../../Source/third_party/fatfs/src/ff.c **** - 942 .loc 1 2160 0 - 943 0308 0D20 movs r0, #13 - 944 .LVL129: - 945 030a F8BD pop {r3, r4, r5, r6, r7, pc} - 946 .LVL130: - 947 .L77: -2166:../../../Source/third_party/fatfs/src/ff.c **** - 948 .loc 1 2166 0 - 949 030c 0D20 movs r0, #13 - 950 .LVL131: - 951 030e F8BD pop {r3, r4, r5, r6, r7, pc} - 952 .LVL132: - 953 .L78: -2170:../../../Source/third_party/fatfs/src/ff.c **** nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ - 954 .loc 1 2170 0 - 955 0310 0D20 movs r0, #13 - 956 .LVL133: - 957 0312 F8BD pop {r3, r4, r5, r6, r7, pc} - 958 .LVL134: - 959 .L79: -2172:../../../Source/third_party/fatfs/src/ff.c **** fmt = FS_FAT12; - 960 .loc 1 2172 0 - 961 0314 0D20 movs r0, #13 - 962 .LVL135: - 963 0316 F8BD pop {r3, r4, r5, r6, r7, pc} - 964 .LVL136: - 965 .L81: -2183:../../../Source/third_party/fatfs/src/ff.c **** fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ - 966 .loc 1 2183 0 - 967 0318 0D20 movs r0, #13 - 968 .LVL137: - 969 031a F8BD pop {r3, r4, r5, r6, r7, pc} - 970 .LVL138: - 971 .L82: -2193:../../../Source/third_party/fatfs/src/ff.c **** - 972 .loc 1 2193 0 - 973 031c 0D20 movs r0, #13 - 974 .LVL139: - 975 031e F8BD pop {r3, r4, r5, r6, r7, pc} - 976 .LVL140: - 977 .L83: -2187:../../../Source/third_party/fatfs/src/ff.c **** fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ - 978 .loc 1 2187 0 - 979 0320 0D20 movs r0, #13 - 980 .LVL141: - 981 0322 F8BD pop {r3, r4, r5, r6, r7, pc} - 982 .LVL142: - 983 .L87: -2193:../../../Source/third_party/fatfs/src/ff.c **** - 984 .loc 1 2193 0 - 985 0324 0D20 movs r0, #13 - 986 .LVL143: - 987 0326 F8BD pop {r3, r4, r5, r6, r7, pc} - 988 .LVL144: - 989 .L44: -2095:../../../Source/third_party/fatfs/src/ff.c **** if (vol >= _VOLUMES) /* Is the drive number valid? */ - 990 .loc 1 2095 0 - 991 0328 0023 movs r3, #0 - 992 032a 0B60 str r3, [r1] - 993 032c 7AE6 b .L58 - 994 .LVL145: - 995 .L52: -2178:../../../Source/third_party/fatfs/src/ff.c **** fs->volbase = bsect; /* Volume start sector */ - 996 .loc 1 2178 0 - 997 032e 0233 adds r3, r3, #2 - 998 .LVL146: - 999 0330 A361 str r3, [r4, #24] -2179:../../../Source/third_party/fatfs/src/ff.c **** fs->fatbase = bsect + nrsv; /* FAT start sector */ - 1000 .loc 1 2179 0 - 1001 0332 2562 str r5, [r4, #32] -2180:../../../Source/third_party/fatfs/src/ff.c **** fs->database = bsect + sysect; /* Data start sector */ - 1002 .loc 1 2180 0 - 1003 0334 2944 add r1, r1, r5 - 1004 0336 6162 str r1, [r4, #36] -2181:../../../Source/third_party/fatfs/src/ff.c **** if (fmt == FS_FAT32) { - 1005 .loc 1 2181 0 - 1006 0338 0CEB0502 add r2, ip, r5 - 1007 033c E262 str r2, [r4, #44] - 1008 033e 40E7 b .L59 - 1009 .LVL147: - 1010 .L90: -2197:../../../Source/third_party/fatfs/src/ff.c **** fs->last_clust = 0; - 1011 .loc 1 2197 0 - 1012 0340 4FF0FF33 mov r3, #-1 - 1013 0344 2361 str r3, [r4, #16] -2198:../../../Source/third_party/fatfs/src/ff.c **** - 1014 .loc 1 2198 0 - 1015 0346 0023 movs r3, #0 - 1016 0348 E360 str r3, [r4, #12] - 1017 034a B9E7 b .L57 - 1018 .L93: - 1019 .align 2 - 1020 .L92: - 1021 034c 00000000 .word .LANCHOR0 - 1022 0350 55AAFFFF .word -21931 - 1023 0354 52526141 .word 1096897106 - 1024 0358 72724161 .word 1631679090 - 1025 035c 00000000 .word .LANCHOR1 - 1026 .LVL148: - 1027 .L56: -2192:../../../Source/third_party/fatfs/src/ff.c **** return FR_NO_FILESYSTEM; - 1028 .loc 1 2192 0 - 1029 0360 03F2FF13 addw r3, r3, #511 - 1030 .LVL149: - 1031 0364 B0EB532F cmp r0, r3, lsr #9 - 1032 .LVL150: - 1033 0368 DCD3 bcc .L87 - 1034 036a E9E7 b .L90 - 1035 .LVL151: - 1036 .L89: -2197:../../../Source/third_party/fatfs/src/ff.c **** fs->last_clust = 0; - 1037 .loc 1 2197 0 - 1038 036c 4FF0FF33 mov r3, #-1 - 1039 .LVL152: - 1040 0370 2361 str r3, [r4, #16] -2198:../../../Source/third_party/fatfs/src/ff.c **** - 1041 .loc 1 2198 0 - 1042 0372 0023 movs r3, #0 - 1043 0374 E360 str r3, [r4, #12] -2202:../../../Source/third_party/fatfs/src/ff.c **** fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo); - 1044 .loc 1 2202 0 - 1045 0376 6371 strb r3, [r4, #5] -2203:../../../Source/third_party/fatfs/src/ff.c **** if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK && - 1046 .loc 1 2203 0 - 1047 0378 94F86520 ldrb r2, [r4, #101] @ zero_extendqisi2 - 1048 037c 94F86430 ldrb r3, [r4, #100] @ zero_extendqisi2 - 1049 0380 43EA0222 orr r2, r3, r2, lsl #8 - 1050 0384 2A44 add r2, r2, r5 - 1051 0386 6261 str r2, [r4, #20] -2204:../../../Source/third_party/fatfs/src/ff.c **** LD_WORD(fs->win+BS_55AA) == 0xAA55 && - 1052 .loc 1 2204 0 - 1053 0388 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 - 1054 .LVL153: - 1055 038a 04F13401 add r1, r4, #52 - 1056 038e 0123 movs r3, #1 - 1057 0390 FFF7FEFF bl disk_read - 1058 .LVL154: - 1059 0394 0028 cmp r0, #0 - 1060 0396 3FF43EAF beq .L61 - 1061 039a 4FF0030E mov lr, #3 - 1062 039e 8FE7 b .L57 - 1063 .cfi_endproc - 1064 .LFE30: - 1066 .section .text.get_fileinfo,"ax",%progbits - 1067 .align 2 - 1068 .thumb - 1069 .thumb_func - 1071 get_fileinfo: - 1072 .LFB27: -1901:../../../Source/third_party/fatfs/src/ff.c **** UINT i; - 1073 .loc 1 1901 0 - 1074 .cfi_startproc - 1075 @ args = 0, pretend = 0, frame = 0 - 1076 @ frame_needed = 0, uses_anonymous_args = 0 - 1077 .LVL155: - 1078 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} - 1079 .cfi_def_cfa_offset 32 - 1080 .cfi_offset 3, -32 - 1081 .cfi_offset 4, -28 - 1082 .cfi_offset 5, -24 - 1083 .cfi_offset 6, -20 - 1084 .cfi_offset 7, -16 - 1085 .cfi_offset 8, -12 - 1086 .cfi_offset 9, -8 - 1087 .cfi_offset 14, -4 -1907:../../../Source/third_party/fatfs/src/ff.c **** if (dj->sect) { - 1088 .loc 1 1907 0 - 1089 0004 01F10902 add r2, r1, #9 - 1090 .LVL156: -1908:../../../Source/third_party/fatfs/src/ff.c **** dir = dj->dir; - 1091 .loc 1 1908 0 - 1092 0008 0369 ldr r3, [r0, #16] - 1093 000a 002B cmp r3, #0 - 1094 000c 67D0 beq .L95 -1909:../../../Source/third_party/fatfs/src/ff.c **** nt = dir[DIR_NTres]; /* NT flag */ - 1095 .loc 1 1909 0 - 1096 000e 4469 ldr r4, [r0, #20] - 1097 .LVL157: -1910:../../../Source/third_party/fatfs/src/ff.c **** for (i = 0; i < 8; i++) { /* Copy name body */ - 1098 .loc 1 1910 0 - 1099 0010 94F80CC0 ldrb ip, [r4, #12] @ zero_extendqisi2 - 1100 .LVL158: -1912:../../../Source/third_party/fatfs/src/ff.c **** if (c == ' ') break; - 1101 .loc 1 1912 0 - 1102 0014 2378 ldrb r3, [r4] @ zero_extendqisi2 - 1103 .LVL159: -1913:../../../Source/third_party/fatfs/src/ff.c **** if (c == NDDE) c = (TCHAR)DDE; - 1104 .loc 1 1913 0 - 1105 0016 202B cmp r3, #32 - 1106 0018 20D0 beq .L107 - 1107 001a 2646 mov r6, r4 - 1108 001c 01F11107 add r7, r1, #17 -1914:../../../Source/third_party/fatfs/src/ff.c **** if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20; - 1109 .loc 1 1914 0 - 1110 0020 4FF0E508 mov r8, #229 -1915:../../../Source/third_party/fatfs/src/ff.c **** #if _LFN_UNICODE - 1111 .loc 1 1915 0 - 1112 0024 0CF0080E and lr, ip, #8 - 1113 0028 5FFA8EFE uxtb lr, lr - 1114 002c 03E0 b .L97 - 1115 .L99: -1912:../../../Source/third_party/fatfs/src/ff.c **** if (c == ' ') break; - 1116 .loc 1 1912 0 - 1117 002e 16F8013F ldrb r3, [r6, #1]! @ zero_extendqisi2 - 1118 .LVL160: -1913:../../../Source/third_party/fatfs/src/ff.c **** if (c == NDDE) c = (TCHAR)DDE; - 1119 .loc 1 1913 0 - 1120 0032 202B cmp r3, #32 - 1121 0034 14D0 beq .L108 - 1122 .LVL161: - 1123 .L97: -1914:../../../Source/third_party/fatfs/src/ff.c **** if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20; - 1124 .loc 1 1914 0 - 1125 0036 052B cmp r3, #5 - 1126 0038 0AD0 beq .L109 -1915:../../../Source/third_party/fatfs/src/ff.c **** #if _LFN_UNICODE - 1127 .loc 1 1915 0 - 1128 003a BEF1000F cmp lr, #0 - 1129 003e 08D0 beq .L98 -1915:../../../Source/third_party/fatfs/src/ff.c **** #if _LFN_UNICODE - 1130 .loc 1 1915 0 is_stmt 0 discriminator 1 - 1131 0040 A3F14105 sub r5, r3, #65 - 1132 0044 EDB2 uxtb r5, r5 - 1133 0046 192D cmp r5, #25 - 1134 0048 03D8 bhi .L98 -1915:../../../Source/third_party/fatfs/src/ff.c **** #if _LFN_UNICODE - 1135 .loc 1 1915 0 discriminator 2 - 1136 004a 2033 adds r3, r3, #32 - 1137 .LVL162: - 1138 004c DBB2 uxtb r3, r3 - 1139 .LVL163: - 1140 004e 00E0 b .L98 - 1141 .L109: -1914:../../../Source/third_party/fatfs/src/ff.c **** if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20; - 1142 .loc 1 1914 0 is_stmt 1 - 1143 0050 4346 mov r3, r8 - 1144 .LVL164: - 1145 .L98: -1922:../../../Source/third_party/fatfs/src/ff.c **** } - 1146 .loc 1 1922 0 discriminator 2 - 1147 0052 02F8013B strb r3, [r2], #1 - 1148 .LVL165: -1911:../../../Source/third_party/fatfs/src/ff.c **** c = dir[i]; - 1149 .loc 1 1911 0 discriminator 2 - 1150 0056 BA42 cmp r2, r7 - 1151 0058 E9D1 bne .L99 - 1152 005a 02E0 b .L96 - 1153 .L107: -1907:../../../Source/third_party/fatfs/src/ff.c **** if (dj->sect) { - 1154 .loc 1 1907 0 - 1155 005c 1746 mov r7, r2 - 1156 005e 00E0 b .L96 - 1157 .L108: -1922:../../../Source/third_party/fatfs/src/ff.c **** } - 1158 .loc 1 1922 0 - 1159 0060 1746 mov r7, r2 - 1160 .LVL166: - 1161 .L96: -1924:../../../Source/third_party/fatfs/src/ff.c **** *p++ = '.'; - 1162 .loc 1 1924 0 - 1163 0062 237A ldrb r3, [r4, #8] @ zero_extendqisi2 - 1164 .LVL167: - 1165 0064 202B cmp r3, #32 - 1166 0066 1ED0 beq .L110 -1925:../../../Source/third_party/fatfs/src/ff.c **** for (i = 8; i < 11; i++) { - 1167 .loc 1 1925 0 - 1168 0068 7E1C adds r6, r7, #1 - 1169 .LVL168: - 1170 006a 2E23 movs r3, #46 - 1171 006c 3B70 strb r3, [r7] - 1172 .LVL169: -1927:../../../Source/third_party/fatfs/src/ff.c **** if (c == ' ') break; - 1173 .loc 1 1927 0 - 1174 006e 237A ldrb r3, [r4, #8] @ zero_extendqisi2 - 1175 .LVL170: -1928:../../../Source/third_party/fatfs/src/ff.c **** if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20; - 1176 .loc 1 1928 0 - 1177 0070 202B cmp r3, #32 - 1178 0072 1AD0 beq .L111 - 1179 0074 04F1080E add lr, r4, #8 - 1180 0078 3A1D adds r2, r7, #4 -1929:../../../Source/third_party/fatfs/src/ff.c **** #if _LFN_UNICODE - 1181 .loc 1 1929 0 - 1182 007a 0CF0100C and ip, ip, #16 - 1183 .LVL171: - 1184 007e 5FFA8CF5 uxtb r5, ip - 1185 0082 03E0 b .L101 - 1186 .LVL172: - 1187 .L103: -1927:../../../Source/third_party/fatfs/src/ff.c **** if (c == ' ') break; - 1188 .loc 1 1927 0 - 1189 0084 1EF8013F ldrb r3, [lr, #1]! @ zero_extendqisi2 - 1190 .LVL173: -1928:../../../Source/third_party/fatfs/src/ff.c **** if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20; - 1191 .loc 1 1928 0 - 1192 0088 202B cmp r3, #32 - 1193 008a 10D0 beq .L112 - 1194 .LVL174: - 1195 .L101: -1929:../../../Source/third_party/fatfs/src/ff.c **** #if _LFN_UNICODE - 1196 .loc 1 1929 0 - 1197 008c 35B1 cbz r5, .L102 -1929:../../../Source/third_party/fatfs/src/ff.c **** #if _LFN_UNICODE - 1198 .loc 1 1929 0 is_stmt 0 discriminator 1 - 1199 008e A3F14107 sub r7, r3, #65 - 1200 0092 FFB2 uxtb r7, r7 - 1201 0094 192F cmp r7, #25 - 1202 0096 9CBF itt ls - 1203 0098 2033 addls r3, r3, #32 - 1204 .LVL175: - 1205 009a DBB2 uxtbls r3, r3 - 1206 .LVL176: - 1207 .L102: -1936:../../../Source/third_party/fatfs/src/ff.c **** } - 1208 .loc 1 1936 0 is_stmt 1 discriminator 2 - 1209 009c 06F8013B strb r3, [r6], #1 - 1210 .LVL177: -1926:../../../Source/third_party/fatfs/src/ff.c **** c = dir[i]; - 1211 .loc 1 1926 0 discriminator 2 - 1212 00a0 9642 cmp r6, r2 - 1213 00a2 EFD1 bne .L103 - 1214 00a4 04E0 b .L100 - 1215 .LVL178: - 1216 .L110: - 1217 00a6 3A46 mov r2, r7 - 1218 .LVL179: - 1219 00a8 02E0 b .L100 - 1220 .LVL180: - 1221 .L111: -1925:../../../Source/third_party/fatfs/src/ff.c **** for (i = 8; i < 11; i++) { - 1222 .loc 1 1925 0 - 1223 00aa 3246 mov r2, r6 - 1224 00ac 00E0 b .L100 - 1225 .LVL181: - 1226 .L112: -1936:../../../Source/third_party/fatfs/src/ff.c **** } - 1227 .loc 1 1936 0 - 1228 00ae 3246 mov r2, r6 - 1229 .LVL182: - 1230 .L100: -1939:../../../Source/third_party/fatfs/src/ff.c **** fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */ - 1231 .loc 1 1939 0 - 1232 00b0 E37A ldrb r3, [r4, #11] @ zero_extendqisi2 - 1233 00b2 0B72 strb r3, [r1, #8] -1940:../../../Source/third_party/fatfs/src/ff.c **** fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */ - 1234 .loc 1 1940 0 - 1235 00b4 E67F ldrb r6, [r4, #31] @ zero_extendqisi2 - 1236 00b6 A57F ldrb r5, [r4, #30] @ zero_extendqisi2 - 1237 00b8 2B04 lsls r3, r5, #16 - 1238 00ba 43EA0665 orr r5, r3, r6, lsl #24 - 1239 00be 237F ldrb r3, [r4, #28] @ zero_extendqisi2 - 1240 00c0 2B43 orrs r3, r3, r5 - 1241 00c2 657F ldrb r5, [r4, #29] @ zero_extendqisi2 - 1242 00c4 43EA0523 orr r3, r3, r5, lsl #8 - 1243 00c8 0B60 str r3, [r1] -1941:../../../Source/third_party/fatfs/src/ff.c **** fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */ - 1244 .loc 1 1941 0 - 1245 00ca 657E ldrb r5, [r4, #25] @ zero_extendqisi2 - 1246 00cc 237E ldrb r3, [r4, #24] @ zero_extendqisi2 - 1247 00ce 43EA0523 orr r3, r3, r5, lsl #8 - 1248 00d2 8B80 strh r3, [r1, #4] @ movhi -1942:../../../Source/third_party/fatfs/src/ff.c **** } - 1249 .loc 1 1942 0 - 1250 00d4 E57D ldrb r5, [r4, #23] @ zero_extendqisi2 - 1251 00d6 A37D ldrb r3, [r4, #22] @ zero_extendqisi2 - 1252 00d8 43EA0523 orr r3, r3, r5, lsl #8 - 1253 00dc CB80 strh r3, [r1, #6] @ movhi - 1254 .LVL183: - 1255 .L95: -1944:../../../Source/third_party/fatfs/src/ff.c **** - 1256 .loc 1 1944 0 - 1257 00de 0023 movs r3, #0 - 1258 00e0 1370 strb r3, [r2] -1947:../../../Source/third_party/fatfs/src/ff.c **** TCHAR *tp = fno->lfname; - 1259 .loc 1 1947 0 - 1260 00e2 8F69 ldr r7, [r1, #24] - 1261 00e4 67B3 cbz r7, .L94 -1947:../../../Source/third_party/fatfs/src/ff.c **** TCHAR *tp = fno->lfname; - 1262 .loc 1 1947 0 is_stmt 0 discriminator 1 - 1263 00e6 CB69 ldr r3, [r1, #28] - 1264 00e8 53B3 cbz r3, .L94 - 1265 .LVL184: - 1266 .LBB2: -1952:../../../Source/third_party/fatfs/src/ff.c **** lfn = dj->lfn; - 1267 .loc 1 1952 0 is_stmt 1 - 1268 00ea 0369 ldr r3, [r0, #16] - 1269 00ec EBB1 cbz r3, .L113 -1952:../../../Source/third_party/fatfs/src/ff.c **** lfn = dj->lfn; - 1270 .loc 1 1952 0 is_stmt 0 discriminator 1 - 1271 00ee 028C ldrh r2, [r0, #32] - 1272 .LVL185: - 1273 00f0 4FF6FF73 movw r3, #65535 - 1274 00f4 9A42 cmp r2, r3 - 1275 00f6 1AD0 beq .L114 -1953:../../../Source/third_party/fatfs/src/ff.c **** while ((w = *lfn++) != 0) { /* Get an LFN char */ - 1276 .loc 1 1953 0 is_stmt 1 - 1277 00f8 D0F81C80 ldr r8, [r0, #28] - 1278 .LVL186: -1954:../../../Source/third_party/fatfs/src/ff.c **** #if !_LFN_UNICODE - 1279 .loc 1 1954 0 - 1280 00fc B8F80000 ldrh r0, [r8] - 1281 .LVL187: - 1282 0100 B8B1 cbz r0, .L115 - 1283 0102 0D46 mov r5, r1 - 1284 0104 7E1E subs r6, r7, #1 - 1285 0106 0024 movs r4, #0 -1956:../../../Source/third_party/fatfs/src/ff.c **** if (!w) { i = 0; break; } /* Could not convert, no LFN */ - 1286 .loc 1 1956 0 - 1287 0108 A146 mov r9, r4 - 1288 .LVL188: - 1289 .L106: - 1290 010a 4946 mov r1, r9 - 1291 010c FFF7FEFF bl ff_convert - 1292 .LVL189: -1957:../../../Source/third_party/fatfs/src/ff.c **** if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */ - 1293 .loc 1 1957 0 - 1294 0110 88B1 cbz r0, .L116 -1961:../../../Source/third_party/fatfs/src/ff.c **** tp[i++] = (TCHAR)w; - 1295 .loc 1 1961 0 - 1296 0112 EB69 ldr r3, [r5, #28] - 1297 0114 013B subs r3, r3, #1 - 1298 0116 A342 cmp r3, r4 - 1299 0118 0FD9 bls .L117 -1962:../../../Source/third_party/fatfs/src/ff.c **** } - 1300 .loc 1 1962 0 - 1301 011a 0134 adds r4, r4, #1 - 1302 .LVL190: - 1303 011c 06F8010F strb r0, [r6, #1]! - 1304 .LVL191: -1954:../../../Source/third_party/fatfs/src/ff.c **** #if !_LFN_UNICODE - 1305 .loc 1 1954 0 - 1306 0120 38F81400 ldrh r0, [r8, r4, lsl #1] - 1307 .LVL192: - 1308 0124 0028 cmp r0, #0 - 1309 0126 F0D1 bne .L106 - 1310 0128 08E0 b .L105 - 1311 .LVL193: - 1312 .L113: -1951:../../../Source/third_party/fatfs/src/ff.c **** if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */ - 1313 .loc 1 1951 0 - 1314 012a 0024 movs r4, #0 - 1315 012c 06E0 b .L105 - 1316 .LVL194: - 1317 .L114: - 1318 012e 0024 movs r4, #0 - 1319 0130 04E0 b .L105 - 1320 .LVL195: - 1321 .L115: - 1322 0132 0024 movs r4, #0 - 1323 0134 02E0 b .L105 - 1324 .LVL196: - 1325 .L116: -1957:../../../Source/third_party/fatfs/src/ff.c **** if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */ - 1326 .loc 1 1957 0 - 1327 0136 0024 movs r4, #0 - 1328 .LVL197: - 1329 0138 00E0 b .L105 - 1330 .LVL198: - 1331 .L117: -1961:../../../Source/third_party/fatfs/src/ff.c **** tp[i++] = (TCHAR)w; - 1332 .loc 1 1961 0 - 1333 013a 0024 movs r4, #0 - 1334 .LVL199: - 1335 .L105: -1965:../../../Source/third_party/fatfs/src/ff.c **** } - 1336 .loc 1 1965 0 - 1337 013c 0023 movs r3, #0 - 1338 013e 3B55 strb r3, [r7, r4] - 1339 .LVL200: - 1340 .L94: - 1341 0140 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} - 1342 .LBE2: - 1343 .cfi_endproc - 1344 .LFE27: - 1346 .section .text.sync_fs,"ax",%progbits - 1347 .align 2 - 1348 .thumb - 1349 .thumb_func - 1351 sync_fs: - 1352 .LFB6: - 787:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 1353 .loc 1 787 0 - 1354 .cfi_startproc - 1355 @ args = 0, pretend = 0, frame = 0 - 1356 @ frame_needed = 0, uses_anonymous_args = 0 - 1357 .LVL201: - 1358 0000 10B5 push {r4, lr} - 1359 .cfi_def_cfa_offset 8 - 1360 .cfi_offset 4, -8 - 1361 .cfi_offset 14, -4 - 1362 0002 0446 mov r4, r0 - 791:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 1363 .loc 1 791 0 - 1364 0004 FFF7FEFF bl sync_window - 1365 .LVL202: - 792:../../../Source/third_party/fatfs/src/ff.c **** /* Update FSInfo sector if needed */ - 1366 .loc 1 792 0 - 1367 0008 0346 mov r3, r0 - 1368 000a 0028 cmp r0, #0 - 1369 000c 54D1 bne .L121 - 794:../../../Source/third_party/fatfs/src/ff.c **** fs->winsect = 0; - 1370 .loc 1 794 0 - 1371 000e 2378 ldrb r3, [r4] @ zero_extendqisi2 - 1372 0010 032B cmp r3, #3 - 1373 0012 49D1 bne .L122 - 794:../../../Source/third_party/fatfs/src/ff.c **** fs->winsect = 0; - 1374 .loc 1 794 0 is_stmt 0 discriminator 1 - 1375 0014 6379 ldrb r3, [r4, #5] @ zero_extendqisi2 - 1376 0016 002B cmp r3, #0 - 1377 0018 46D0 beq .L122 - 795:../../../Source/third_party/fatfs/src/ff.c **** /* Create FSInfo structure */ - 1378 .loc 1 795 0 is_stmt 1 - 1379 001a 0023 movs r3, #0 - 1380 001c 2363 str r3, [r4, #48] - 797:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(fs->win+BS_55AA, 0xAA55); - 1381 .loc 1 797 0 - 1382 001e 04F13401 add r1, r4, #52 - 1383 .LVL203: - 1384 0022 04F50D70 add r0, r4, #564 - 1385 .LVL204: - 1386 .LBB5: - 1387 .LBB6: - 557:../../../Source/third_party/fatfs/src/ff.c **** - 1388 .loc 1 557 0 - 1389 0026 0B46 mov r3, r1 - 560:../../../Source/third_party/fatfs/src/ff.c **** } - 1390 .loc 1 560 0 - 1391 0028 0022 movs r2, #0 - 1392 .LVL205: - 1393 .L123: - 1394 002a 03F8012B strb r2, [r3], #1 - 1395 .LVL206: - 559:../../../Source/third_party/fatfs/src/ff.c **** *d++ = (BYTE)val; - 1396 .loc 1 559 0 - 1397 002e 8342 cmp r3, r0 - 1398 0030 FBD1 bne .L123 - 1399 .LBE6: - 1400 .LBE5: - 798:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(fs->win+FSI_LeadSig, 0x41615252); - 1401 .loc 1 798 0 - 1402 0032 5523 movs r3, #85 - 1403 .LVL207: - 1404 0034 84F83232 strb r3, [r4, #562] - 1405 0038 AA23 movs r3, #170 - 1406 003a 84F83332 strb r3, [r4, #563] - 799:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(fs->win+FSI_StrucSig, 0x61417272); - 1407 .loc 1 799 0 - 1408 003e 5223 movs r3, #82 - 1409 0040 84F83430 strb r3, [r4, #52] - 1410 0044 84F83530 strb r3, [r4, #53] - 1411 0048 6123 movs r3, #97 - 1412 004a 84F83630 strb r3, [r4, #54] - 1413 004e 4122 movs r2, #65 - 1414 0050 84F83720 strb r2, [r4, #55] - 800:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust); - 1415 .loc 1 800 0 - 1416 0054 7220 movs r0, #114 - 1417 0056 84F81802 strb r0, [r4, #536] - 1418 005a 84F81902 strb r0, [r4, #537] - 1419 005e 84F81A22 strb r2, [r4, #538] - 1420 0062 84F81B32 strb r3, [r4, #539] - 801:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust); - 1421 .loc 1 801 0 - 1422 0066 2369 ldr r3, [r4, #16] - 1423 0068 84F81C32 strb r3, [r4, #540] - 1424 006c C3F30722 ubfx r2, r3, #8, #8 - 1425 0070 84F81D22 strb r2, [r4, #541] - 1426 0074 1A0C lsrs r2, r3, #16 - 1427 0076 84F81E22 strb r2, [r4, #542] - 1428 007a 1B0E lsrs r3, r3, #24 - 1429 007c 84F81F32 strb r3, [r4, #543] - 802:../../../Source/third_party/fatfs/src/ff.c **** /* Write it into the FSInfo sector */ - 1430 .loc 1 802 0 - 1431 0080 E368 ldr r3, [r4, #12] - 1432 0082 84F82032 strb r3, [r4, #544] - 1433 0086 C3F30722 ubfx r2, r3, #8, #8 - 1434 008a 84F82122 strb r2, [r4, #545] - 1435 008e 1A0C lsrs r2, r3, #16 - 1436 0090 84F82222 strb r2, [r4, #546] - 1437 0094 1B0E lsrs r3, r3, #24 - 1438 0096 84F82332 strb r3, [r4, #547] - 804:../../../Source/third_party/fatfs/src/ff.c **** fs->fsi_flag = 0; - 1439 .loc 1 804 0 - 1440 009a 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 - 1441 009c 6269 ldr r2, [r4, #20] - 1442 009e 0123 movs r3, #1 - 1443 00a0 FFF7FEFF bl disk_write - 1444 .LVL208: - 805:../../../Source/third_party/fatfs/src/ff.c **** } - 1445 .loc 1 805 0 - 1446 00a4 0023 movs r3, #0 - 1447 00a6 6371 strb r3, [r4, #5] - 1448 .LVL209: - 1449 .L122: - 808:../../../Source/third_party/fatfs/src/ff.c **** res = FR_DISK_ERR; - 1450 .loc 1 808 0 - 1451 00a8 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 - 1452 00aa 0021 movs r1, #0 - 1453 00ac 0A46 mov r2, r1 - 1454 00ae FFF7FEFF bl disk_ioctl - 1455 .LVL210: - 791:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 1456 .loc 1 791 0 - 1457 00b2 031C adds r3, r0, #0 - 1458 00b4 18BF it ne - 1459 00b6 0123 movne r3, #1 - 1460 .L121: - 1461 .LVL211: - 813:../../../Source/third_party/fatfs/src/ff.c **** #endif - 1462 .loc 1 813 0 - 1463 00b8 1846 mov r0, r3 - 1464 00ba 10BD pop {r4, pc} - 1465 .cfi_endproc - 1466 .LFE6: - 1468 .section .text.clust2sect,"ax",%progbits - 1469 .align 2 - 1470 .global clust2sect - 1471 .thumb - 1472 .thumb_func - 1474 clust2sect: - 1475 .LFB7: - 828:../../../Source/third_party/fatfs/src/ff.c **** clst -= 2; - 1476 .loc 1 828 0 - 1477 .cfi_startproc - 1478 @ args = 0, pretend = 0, frame = 0 - 1479 @ frame_needed = 0, uses_anonymous_args = 0 - 1480 @ link register save eliminated. - 1481 .LVL212: - 829:../../../Source/third_party/fatfs/src/ff.c **** if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */ - 1482 .loc 1 829 0 - 1483 0000 0239 subs r1, r1, #2 - 1484 .LVL213: - 830:../../../Source/third_party/fatfs/src/ff.c **** return clst * fs->csize + fs->database; - 1485 .loc 1 830 0 - 1486 0002 8369 ldr r3, [r0, #24] - 1487 0004 023B subs r3, r3, #2 - 1488 0006 9942 cmp r1, r3 - 831:../../../Source/third_party/fatfs/src/ff.c **** } - 1489 .loc 1 831 0 - 1490 0008 3DBF ittte cc - 1491 000a 8278 ldrbcc r2, [r0, #2] @ zero_extendqisi2 - 1492 000c C36A ldrcc r3, [r0, #44] - 1493 000e 02FB0130 mlacc r0, r2, r1, r3 - 1494 .LVL214: - 830:../../../Source/third_party/fatfs/src/ff.c **** return clst * fs->csize + fs->database; - 1495 .loc 1 830 0 - 1496 0012 0020 movcs r0, #0 - 832:../../../Source/third_party/fatfs/src/ff.c **** - 1497 .loc 1 832 0 - 1498 0014 7047 bx lr - 1499 .cfi_endproc - 1500 .LFE7: - 1502 0016 00BF .section .text.get_fat,"ax",%progbits - 1503 .align 2 - 1504 .global get_fat - 1505 .thumb - 1506 .thumb_func - 1508 get_fat: - 1509 .LFB8: - 846:../../../Source/third_party/fatfs/src/ff.c **** UINT wc, bc; - 1510 .loc 1 846 0 - 1511 .cfi_startproc - 1512 @ args = 0, pretend = 0, frame = 0 - 1513 @ frame_needed = 0, uses_anonymous_args = 0 - 1514 .LVL215: - 851:../../../Source/third_party/fatfs/src/ff.c **** return 1; - 1515 .loc 1 851 0 - 1516 0000 0129 cmp r1, #1 - 1517 0002 5FD9 bls .L135 - 846:../../../Source/third_party/fatfs/src/ff.c **** UINT wc, bc; - 1518 .loc 1 846 0 discriminator 1 - 1519 0004 F8B5 push {r3, r4, r5, r6, r7, lr} - 1520 .cfi_def_cfa_offset 24 - 1521 .cfi_offset 3, -24 - 1522 .cfi_offset 4, -20 - 1523 .cfi_offset 5, -16 - 1524 .cfi_offset 6, -12 - 1525 .cfi_offset 7, -8 - 1526 .cfi_offset 14, -4 - 851:../../../Source/third_party/fatfs/src/ff.c **** return 1; - 1527 .loc 1 851 0 discriminator 1 - 1528 0006 8369 ldr r3, [r0, #24] - 1529 0008 9942 cmp r1, r3 - 1530 000a 5DD2 bcs .L136 - 1531 000c 0C46 mov r4, r1 - 1532 000e 0646 mov r6, r0 - 854:../../../Source/third_party/fatfs/src/ff.c **** case FS_FAT12 : - 1533 .loc 1 854 0 - 1534 0010 0378 ldrb r3, [r0] @ zero_extendqisi2 - 1535 0012 022B cmp r3, #2 - 1536 0014 28D0 beq .L131 - 1537 0016 032B cmp r3, #3 - 1538 0018 38D0 beq .L132 - 1539 001a 012B cmp r3, #1 - 1540 001c 56D1 bne .L142 - 1541 .LVL216: - 856:../../../Source/third_party/fatfs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; - 1542 .loc 1 856 0 - 1543 001e 01EB5107 add r7, r1, r1, lsr #1 - 1544 .LVL217: - 857:../../../Source/third_party/fatfs/src/ff.c **** wc = fs->win[bc % SS(fs)]; bc++; - 1545 .loc 1 857 0 - 1546 0022 416A ldr r1, [r0, #36] - 1547 .LVL218: - 1548 0024 01EB5721 add r1, r1, r7, lsr #9 - 1549 0028 FFF7FEFF bl move_window - 1550 .LVL219: - 1551 002c 0028 cmp r0, #0 - 1552 002e 50D1 bne .L138 - 858:../../../Source/third_party/fatfs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; - 1553 .loc 1 858 0 - 1554 0030 C7F30803 ubfx r3, r7, #0, #9 - 1555 0034 3344 add r3, r3, r6 - 1556 0036 93F83450 ldrb r5, [r3, #52] @ zero_extendqisi2 - 1557 .LVL220: - 1558 003a 0137 adds r7, r7, #1 - 1559 .LVL221: - 859:../../../Source/third_party/fatfs/src/ff.c **** wc |= fs->win[bc % SS(fs)] << 8; - 1560 .loc 1 859 0 - 1561 003c 716A ldr r1, [r6, #36] - 1562 003e 3046 mov r0, r6 - 1563 0040 01EB5721 add r1, r1, r7, lsr #9 - 1564 0044 FFF7FEFF bl move_window - 1565 .LVL222: - 1566 0048 0028 cmp r0, #0 - 1567 004a 45D1 bne .L139 - 860:../../../Source/third_party/fatfs/src/ff.c **** return (clst & 1) ? (wc >> 4) : (wc & 0xFFF); - 1568 .loc 1 860 0 - 1569 004c C7F30807 ubfx r7, r7, #0, #9 - 1570 .LVL223: - 1571 0050 F119 adds r1, r6, r7 - 1572 0052 91F83400 ldrb r0, [r1, #52] @ zero_extendqisi2 - 1573 0056 45EA0020 orr r0, r5, r0, lsl #8 - 1574 .LVL224: - 861:../../../Source/third_party/fatfs/src/ff.c **** - 1575 .loc 1 861 0 - 1576 005a 14F0010F tst r4, #1 - 1577 005e 14BF ite ne - 1578 0060 0009 lsrne r0, r0, #4 - 1579 .LVL225: - 1580 0062 C0F30B00 ubfxeq r0, r0, #0, #12 - 1581 0066 F8BD pop {r3, r4, r5, r6, r7, pc} - 1582 .LVL226: - 1583 .L131: - 864:../../../Source/third_party/fatfs/src/ff.c **** p = &fs->win[clst * 2 % SS(fs)]; - 1584 .loc 1 864 0 - 1585 0068 416A ldr r1, [r0, #36] - 1586 .LVL227: - 1587 006a 01EB1421 add r1, r1, r4, lsr #8 - 1588 006e FFF7FEFF bl move_window - 1589 .LVL228: - 1590 0072 A0BB cbnz r0, .L140 - 865:../../../Source/third_party/fatfs/src/ff.c **** return LD_WORD(p); - 1591 .loc 1 865 0 - 1592 0074 6100 lsls r1, r4, #1 - 1593 0076 01F4FF71 and r1, r1, #510 - 1594 .LVL229: - 866:../../../Source/third_party/fatfs/src/ff.c **** - 1595 .loc 1 866 0 - 1596 007a 7318 adds r3, r6, r1 - 1597 007c 93F83430 ldrb r3, [r3, #52] @ zero_extendqisi2 - 1598 0080 3144 add r1, r1, r6 - 1599 .LVL230: - 1600 0082 91F83500 ldrb r0, [r1, #53] @ zero_extendqisi2 - 1601 0086 43EA0020 orr r0, r3, r0, lsl #8 - 1602 008a F8BD pop {r3, r4, r5, r6, r7, pc} - 1603 .LVL231: - 1604 .L132: - 869:../../../Source/third_party/fatfs/src/ff.c **** p = &fs->win[clst * 4 % SS(fs)]; - 1605 .loc 1 869 0 - 1606 008c 416A ldr r1, [r0, #36] - 1607 .LVL232: - 1608 008e 01EBD411 add r1, r1, r4, lsr #7 - 1609 0092 FFF7FEFF bl move_window - 1610 .LVL233: - 1611 0096 28BB cbnz r0, .L141 - 870:../../../Source/third_party/fatfs/src/ff.c **** return LD_DWORD(p) & 0x0FFFFFFF; - 1612 .loc 1 870 0 - 1613 0098 A100 lsls r1, r4, #2 - 1614 009a 01F4FE71 and r1, r1, #508 - 1615 009e 7218 adds r2, r6, r1 - 1616 .LVL234: - 871:../../../Source/third_party/fatfs/src/ff.c **** } - 1617 .loc 1 871 0 - 1618 00a0 92F83600 ldrb r0, [r2, #54] @ zero_extendqisi2 - 1619 00a4 92F83730 ldrb r3, [r2, #55] @ zero_extendqisi2 - 1620 00a8 1B06 lsls r3, r3, #24 - 1621 00aa 43EA0043 orr r3, r3, r0, lsl #16 - 1622 00ae 92F83500 ldrb r0, [r2, #53] @ zero_extendqisi2 - 1623 00b2 43EA0020 orr r0, r3, r0, lsl #8 - 1624 00b6 3144 add r1, r1, r6 - 1625 00b8 91F83430 ldrb r3, [r1, #52] @ zero_extendqisi2 - 1626 00bc 1843 orrs r0, r0, r3 - 1627 00be 20F07040 bic r0, r0, #-268435456 - 1628 00c2 F8BD pop {r3, r4, r5, r6, r7, pc} - 1629 .LVL235: - 1630 .L135: - 1631 .cfi_def_cfa_offset 0 - 1632 .cfi_restore 3 - 1633 .cfi_restore 4 - 1634 .cfi_restore 5 - 1635 .cfi_restore 6 - 1636 .cfi_restore 7 - 1637 .cfi_restore 14 - 852:../../../Source/third_party/fatfs/src/ff.c **** - 1638 .loc 1 852 0 - 1639 00c4 0120 movs r0, #1 - 1640 .LVL236: - 875:../../../Source/third_party/fatfs/src/ff.c **** - 1641 .loc 1 875 0 - 1642 00c6 7047 bx lr - 1643 .LVL237: - 1644 .L136: - 1645 .cfi_def_cfa_offset 24 - 1646 .cfi_offset 3, -24 - 1647 .cfi_offset 4, -20 - 1648 .cfi_offset 5, -16 - 1649 .cfi_offset 6, -12 - 1650 .cfi_offset 7, -8 - 1651 .cfi_offset 14, -4 - 852:../../../Source/third_party/fatfs/src/ff.c **** - 1652 .loc 1 852 0 - 1653 00c8 0120 movs r0, #1 - 1654 .LVL238: - 1655 00ca F8BD pop {r3, r4, r5, r6, r7, pc} - 1656 .LVL239: - 1657 .L142: - 874:../../../Source/third_party/fatfs/src/ff.c **** } - 1658 .loc 1 874 0 - 1659 00cc 4FF0FF30 mov r0, #-1 - 1660 .LVL240: - 1661 00d0 F8BD pop {r3, r4, r5, r6, r7, pc} - 1662 .LVL241: - 1663 .L138: - 1664 00d2 4FF0FF30 mov r0, #-1 - 1665 00d6 F8BD pop {r3, r4, r5, r6, r7, pc} - 1666 .LVL242: - 1667 .L139: - 1668 00d8 4FF0FF30 mov r0, #-1 - 1669 00dc F8BD pop {r3, r4, r5, r6, r7, pc} - 1670 .LVL243: - 1671 .L140: - 1672 00de 4FF0FF30 mov r0, #-1 - 1673 00e2 F8BD pop {r3, r4, r5, r6, r7, pc} - 1674 .LVL244: - 1675 .L141: - 1676 00e4 4FF0FF30 mov r0, #-1 - 875:../../../Source/third_party/fatfs/src/ff.c **** - 1677 .loc 1 875 0 - 1678 00e8 F8BD pop {r3, r4, r5, r6, r7, pc} - 1679 .cfi_endproc - 1680 .LFE8: - 1682 00ea 00BF .section .text.dir_sdi,"ax",%progbits - 1683 .align 2 - 1684 .thumb - 1685 .thumb_func - 1687 dir_sdi: - 1688 .LFB12: -1092:../../../Source/third_party/fatfs/src/ff.c **** DWORD clst; - 1689 .loc 1 1092 0 - 1690 .cfi_startproc - 1691 @ args = 0, pretend = 0, frame = 0 - 1692 @ frame_needed = 0, uses_anonymous_args = 0 - 1693 .LVL245: - 1694 0000 70B5 push {r4, r5, r6, lr} - 1695 .cfi_def_cfa_offset 16 - 1696 .cfi_offset 4, -16 - 1697 .cfi_offset 5, -12 - 1698 .cfi_offset 6, -8 - 1699 .cfi_offset 14, -4 - 1700 0002 0546 mov r5, r0 - 1701 0004 0C46 mov r4, r1 -1097:../../../Source/third_party/fatfs/src/ff.c **** clst = dj->sclust; - 1702 .loc 1 1097 0 - 1703 0006 E980 strh r1, [r5, #6] @ movhi -1098:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 1 || clst >= dj->fs->n_fatent) /* Check start cluster range */ - 1704 .loc 1 1098 0 - 1705 0008 8168 ldr r1, [r0, #8] - 1706 .LVL246: -1099:../../../Source/third_party/fatfs/src/ff.c **** return FR_INT_ERR; - 1707 .loc 1 1099 0 - 1708 000a 0129 cmp r1, #1 - 1709 000c 38D0 beq .L151 -1099:../../../Source/third_party/fatfs/src/ff.c **** return FR_INT_ERR; - 1710 .loc 1 1099 0 is_stmt 0 discriminator 1 - 1711 000e 0368 ldr r3, [r0] - 1712 0010 9A69 ldr r2, [r3, #24] - 1713 0012 9142 cmp r1, r2 - 1714 0014 36D2 bcs .L152 -1101:../../../Source/third_party/fatfs/src/ff.c **** clst = dj->fs->dirbase; - 1715 .loc 1 1101 0 is_stmt 1 - 1716 0016 71B9 cbnz r1, .L146 -1101:../../../Source/third_party/fatfs/src/ff.c **** clst = dj->fs->dirbase; - 1717 .loc 1 1101 0 is_stmt 0 discriminator 1 - 1718 0018 1A78 ldrb r2, [r3] @ zero_extendqisi2 - 1719 001a 032A cmp r2, #3 - 1720 001c 01D1 bne .L147 -1102:../../../Source/third_party/fatfs/src/ff.c **** - 1721 .loc 1 1102 0 is_stmt 1 - 1722 001e 996A ldr r1, [r3, #40] - 1723 .LVL247: -1104:../../../Source/third_party/fatfs/src/ff.c **** dj->clust = clst; - 1724 .loc 1 1104 0 - 1725 0020 49B9 cbnz r1, .L146 - 1726 .L147: - 1727 .LVL248: -1105:../../../Source/third_party/fatfs/src/ff.c **** if (idx >= dj->fs->n_rootdir) /* Index is out of range */ - 1728 .loc 1 1105 0 - 1729 0022 0022 movs r2, #0 - 1730 0024 EA60 str r2, [r5, #12] -1106:../../../Source/third_party/fatfs/src/ff.c **** return FR_INT_ERR; - 1731 .loc 1 1106 0 - 1732 0026 1A89 ldrh r2, [r3, #8] - 1733 0028 A242 cmp r2, r4 - 1734 002a 2DD9 bls .L153 -1108:../../../Source/third_party/fatfs/src/ff.c **** } - 1735 .loc 1 1108 0 - 1736 002c 9B6A ldr r3, [r3, #40] - 1737 002e 03EB1413 add r3, r3, r4, lsr #4 - 1738 0032 2B61 str r3, [r5, #16] - 1739 0034 1BE0 b .L148 - 1740 .LVL249: - 1741 .L146: -1111:../../../Source/third_party/fatfs/src/ff.c **** while (idx >= ic) { /* Follow cluster chain */ - 1742 .loc 1 1111 0 - 1743 0036 9E78 ldrb r6, [r3, #2] @ zero_extendqisi2 - 1744 0038 3601 lsls r6, r6, #4 - 1745 .LVL250: -1112:../../../Source/third_party/fatfs/src/ff.c **** clst = get_fat(dj->fs, clst); /* Get next cluster */ - 1746 .loc 1 1112 0 - 1747 003a B442 cmp r4, r6 - 1748 003c 10D3 bcc .L149 - 1749 .LVL251: - 1750 .L157: -1113:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ - 1751 .loc 1 1113 0 - 1752 003e 2868 ldr r0, [r5] - 1753 0040 FFF7FEFF bl get_fat - 1754 .LVL252: - 1755 0044 0146 mov r1, r0 - 1756 .LVL253: -1114:../../../Source/third_party/fatfs/src/ff.c **** if (clst < 2 || clst >= dj->fs->n_fatent) /* Reached to end of table or int error */ - 1757 .loc 1 1114 0 - 1758 0046 B0F1FF3F cmp r0, #-1 - 1759 004a 1FD0 beq .L154 -1115:../../../Source/third_party/fatfs/src/ff.c **** return FR_INT_ERR; - 1760 .loc 1 1115 0 - 1761 004c 0128 cmp r0, #1 - 1762 004e 1FD9 bls .L155 -1115:../../../Source/third_party/fatfs/src/ff.c **** return FR_INT_ERR; - 1763 .loc 1 1115 0 is_stmt 0 discriminator 1 - 1764 0050 2B68 ldr r3, [r5] - 1765 0052 9B69 ldr r3, [r3, #24] - 1766 0054 9842 cmp r0, r3 - 1767 0056 1DD2 bcs .L156 -1117:../../../Source/third_party/fatfs/src/ff.c **** } - 1768 .loc 1 1117 0 is_stmt 1 - 1769 0058 A41B subs r4, r4, r6 - 1770 .LVL254: - 1771 005a A4B2 uxth r4, r4 - 1772 .LVL255: -1112:../../../Source/third_party/fatfs/src/ff.c **** clst = get_fat(dj->fs, clst); /* Get next cluster */ - 1773 .loc 1 1112 0 - 1774 005c A642 cmp r6, r4 - 1775 005e EED9 bls .L157 - 1776 .LVL256: - 1777 .L149: -1119:../../../Source/third_party/fatfs/src/ff.c **** dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */ - 1778 .loc 1 1119 0 - 1779 0060 E960 str r1, [r5, #12] -1120:../../../Source/third_party/fatfs/src/ff.c **** } - 1780 .loc 1 1120 0 - 1781 0062 2868 ldr r0, [r5] - 1782 0064 FFF7FEFF bl clust2sect - 1783 .LVL257: - 1784 0068 00EB1410 add r0, r0, r4, lsr #4 - 1785 006c 2861 str r0, [r5, #16] - 1786 .LVL258: - 1787 .L148: -1123:../../../Source/third_party/fatfs/src/ff.c **** - 1788 .loc 1 1123 0 - 1789 006e 04F00F04 and r4, r4, #15 - 1790 .LVL259: - 1791 0072 2B68 ldr r3, [r5] - 1792 0074 03EB4414 add r4, r3, r4, lsl #5 - 1793 0078 3434 adds r4, r4, #52 - 1794 007a 6C61 str r4, [r5, #20] -1125:../../../Source/third_party/fatfs/src/ff.c **** } - 1795 .loc 1 1125 0 - 1796 007c 0020 movs r0, #0 - 1797 007e 70BD pop {r4, r5, r6, pc} - 1798 .LVL260: - 1799 .L151: -1100:../../../Source/third_party/fatfs/src/ff.c **** if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */ - 1800 .loc 1 1100 0 - 1801 0080 0220 movs r0, #2 - 1802 .LVL261: - 1803 0082 70BD pop {r4, r5, r6, pc} - 1804 .LVL262: - 1805 .L152: - 1806 0084 0220 movs r0, #2 - 1807 .LVL263: - 1808 0086 70BD pop {r4, r5, r6, pc} - 1809 .LVL264: - 1810 .L153: -1107:../../../Source/third_party/fatfs/src/ff.c **** dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */ - 1811 .loc 1 1107 0 - 1812 0088 0220 movs r0, #2 - 1813 .LVL265: - 1814 008a 70BD pop {r4, r5, r6, pc} - 1815 .LVL266: - 1816 .L154: -1114:../../../Source/third_party/fatfs/src/ff.c **** if (clst < 2 || clst >= dj->fs->n_fatent) /* Reached to end of table or int error */ - 1817 .loc 1 1114 0 - 1818 008c 0120 movs r0, #1 - 1819 .LVL267: - 1820 008e 70BD pop {r4, r5, r6, pc} - 1821 .LVL268: - 1822 .L155: -1116:../../../Source/third_party/fatfs/src/ff.c **** idx -= ic; - 1823 .loc 1 1116 0 - 1824 0090 0220 movs r0, #2 - 1825 .LVL269: - 1826 0092 70BD pop {r4, r5, r6, pc} - 1827 .LVL270: - 1828 .L156: - 1829 0094 0220 movs r0, #2 - 1830 .LVL271: -1126:../../../Source/third_party/fatfs/src/ff.c **** - 1831 .loc 1 1126 0 - 1832 0096 70BD pop {r4, r5, r6, pc} - 1833 .cfi_endproc - 1834 .LFE12: - 1836 .section .text.put_fat,"ax",%progbits - 1837 .align 2 - 1838 .global put_fat - 1839 .thumb - 1840 .thumb_func - 1842 put_fat: - 1843 .LFB9: - 890:../../../Source/third_party/fatfs/src/ff.c **** UINT bc; - 1844 .loc 1 890 0 - 1845 .cfi_startproc - 1846 @ args = 0, pretend = 0, frame = 0 - 1847 @ frame_needed = 0, uses_anonymous_args = 0 - 1848 .LVL272: - 1849 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} - 1850 .cfi_def_cfa_offset 24 - 1851 .cfi_offset 4, -24 - 1852 .cfi_offset 5, -20 - 1853 .cfi_offset 6, -16 - 1854 .cfi_offset 7, -12 - 1855 .cfi_offset 8, -8 - 1856 .cfi_offset 14, -4 - 1857 0004 0C46 mov r4, r1 - 896:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INT_ERR; - 1858 .loc 1 896 0 - 1859 0006 0129 cmp r1, #1 - 1860 0008 7ED9 bls .L170 - 1861 000a 0546 mov r5, r0 - 1862 000c 1746 mov r7, r2 - 896:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INT_ERR; - 1863 .loc 1 896 0 is_stmt 0 discriminator 1 - 1864 000e 8369 ldr r3, [r0, #24] - 1865 0010 9942 cmp r1, r3 - 1866 0012 7BD2 bcs .L171 - 900:../../../Source/third_party/fatfs/src/ff.c **** case FS_FAT12 : - 1867 .loc 1 900 0 is_stmt 1 - 1868 0014 0378 ldrb r3, [r0] @ zero_extendqisi2 - 1869 0016 022B cmp r3, #2 - 1870 0018 3DD0 beq .L163 - 1871 001a 032B cmp r3, #3 - 1872 001c 4DD0 beq .L164 - 1873 001e 012B cmp r3, #1 - 1874 0020 6AD1 bne .L175 - 1875 .LVL273: - 902:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(fs, fs->fatbase + (bc / SS(fs))); - 1876 .loc 1 902 0 - 1877 0022 01EB5108 add r8, r1, r1, lsr #1 - 1878 .LVL274: - 903:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 1879 .loc 1 903 0 - 1880 0026 416A ldr r1, [r0, #36] - 1881 .LVL275: - 1882 0028 01EB5821 add r1, r1, r8, lsr #9 - 1883 002c FFF7FEFF bl move_window - 1884 .LVL276: - 904:../../../Source/third_party/fatfs/src/ff.c **** p = &fs->win[bc % SS(fs)]; - 1885 .loc 1 904 0 - 1886 0030 0646 mov r6, r0 - 1887 0032 0028 cmp r0, #0 - 1888 0034 65D1 bne .L162 - 905:../../../Source/third_party/fatfs/src/ff.c **** *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; - 1889 .loc 1 905 0 - 1890 0036 C8F30803 ubfx r3, r8, #0, #9 - 1891 .LVL277: - 906:../../../Source/third_party/fatfs/src/ff.c **** bc++; - 1892 .loc 1 906 0 - 1893 003a 14F0010F tst r4, #1 - 1894 003e 16D0 beq .L166 - 906:../../../Source/third_party/fatfs/src/ff.c **** bc++; - 1895 .loc 1 906 0 is_stmt 0 discriminator 1 - 1896 0040 2B44 add r3, r3, r5 - 1897 .LVL278: - 1898 0042 93F83420 ldrb r2, [r3, #52] @ zero_extendqisi2 - 1899 0046 02F00F02 and r2, r2, #15 - 1900 004a F9B2 uxtb r1, r7 - 1901 004c 42EA0112 orr r2, r2, r1, lsl #4 - 1902 0050 83F83420 strb r2, [r3, #52] - 907:../../../Source/third_party/fatfs/src/ff.c **** fs->wflag = 1; - 1903 .loc 1 907 0 is_stmt 1 discriminator 1 - 1904 0054 08F10108 add r8, r8, #1 - 1905 .LVL279: - 908:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(fs, fs->fatbase + (bc / SS(fs))); - 1906 .loc 1 908 0 discriminator 1 - 1907 0058 0123 movs r3, #1 - 1908 005a 2B71 strb r3, [r5, #4] - 909:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 1909 .loc 1 909 0 discriminator 1 - 1910 005c 696A ldr r1, [r5, #36] - 1911 005e 2846 mov r0, r5 - 1912 .LVL280: - 1913 0060 01EB5821 add r1, r1, r8, lsr #9 - 1914 0064 FFF7FEFF bl move_window - 1915 .LVL281: - 910:../../../Source/third_party/fatfs/src/ff.c **** p = &fs->win[bc % SS(fs)]; - 1916 .loc 1 910 0 discriminator 1 - 1917 0068 0028 cmp r0, #0 - 1918 006a 47D1 bne .L173 - 1919 006c 50E0 b .L176 - 1920 .LVL282: - 1921 .L166: - 906:../../../Source/third_party/fatfs/src/ff.c **** bc++; - 1922 .loc 1 906 0 discriminator 2 - 1923 006e 2B44 add r3, r3, r5 - 1924 .LVL283: - 1925 0070 83F83470 strb r7, [r3, #52] - 907:../../../Source/third_party/fatfs/src/ff.c **** fs->wflag = 1; - 1926 .loc 1 907 0 discriminator 2 - 1927 0074 08F10108 add r8, r8, #1 - 1928 .LVL284: - 908:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(fs, fs->fatbase + (bc / SS(fs))); - 1929 .loc 1 908 0 discriminator 2 - 1930 0078 0123 movs r3, #1 - 1931 007a 2B71 strb r3, [r5, #4] - 909:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 1932 .loc 1 909 0 discriminator 2 - 1933 007c 696A ldr r1, [r5, #36] - 1934 007e 2846 mov r0, r5 - 1935 .LVL285: - 1936 0080 01EB5821 add r1, r1, r8, lsr #9 - 1937 0084 FFF7FEFF bl move_window - 1938 .LVL286: - 910:../../../Source/third_party/fatfs/src/ff.c **** p = &fs->win[bc % SS(fs)]; - 1939 .loc 1 910 0 discriminator 2 - 1940 0088 D0BB cbnz r0, .L174 - 1941 008a 46E0 b .L177 - 1942 .LVL287: - 1943 .L169: - 912:../../../Source/third_party/fatfs/src/ff.c **** break; - 1944 .loc 1 912 0 discriminator 4 - 1945 008c 05EB0803 add r3, r5, r8 - 1946 0090 83F83470 strb r7, [r3, #52] - 913:../../../Source/third_party/fatfs/src/ff.c **** - 1947 .loc 1 913 0 discriminator 4 - 1948 0094 35E0 b .L162 - 1949 .LVL288: - 1950 .L163: - 916:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 1951 .loc 1 916 0 - 1952 0096 416A ldr r1, [r0, #36] - 1953 .LVL289: - 1954 0098 01EB1421 add r1, r1, r4, lsr #8 - 1955 009c FFF7FEFF bl move_window - 1956 .LVL290: - 917:../../../Source/third_party/fatfs/src/ff.c **** p = &fs->win[clst * 2 % SS(fs)]; - 1957 .loc 1 917 0 - 1958 00a0 0646 mov r6, r0 - 1959 00a2 70BB cbnz r0, .L162 - 918:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(p, (WORD)val); - 1960 .loc 1 918 0 - 1961 00a4 6400 lsls r4, r4, #1 - 1962 .LVL291: - 1963 00a6 04F4FF74 and r4, r4, #510 - 1964 .LVL292: - 919:../../../Source/third_party/fatfs/src/ff.c **** break; - 1965 .loc 1 919 0 - 1966 00aa 2B19 adds r3, r5, r4 - 1967 00ac 83F83470 strb r7, [r3, #52] - 1968 00b0 C7F30727 ubfx r7, r7, #8, #8 - 1969 .LVL293: - 1970 00b4 83F83570 strb r7, [r3, #53] - 920:../../../Source/third_party/fatfs/src/ff.c **** - 1971 .loc 1 920 0 - 1972 00b8 23E0 b .L162 - 1973 .LVL294: - 1974 .L164: - 923:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 1975 .loc 1 923 0 - 1976 00ba 416A ldr r1, [r0, #36] - 1977 .LVL295: - 1978 00bc 01EBD411 add r1, r1, r4, lsr #7 - 1979 00c0 FFF7FEFF bl move_window - 1980 .LVL296: - 924:../../../Source/third_party/fatfs/src/ff.c **** p = &fs->win[clst * 4 % SS(fs)]; - 1981 .loc 1 924 0 - 1982 00c4 0646 mov r6, r0 - 1983 00c6 E0B9 cbnz r0, .L162 - 925:../../../Source/third_party/fatfs/src/ff.c **** val |= LD_DWORD(p) & 0xF0000000; - 1984 .loc 1 925 0 - 1985 00c8 A400 lsls r4, r4, #2 - 1986 .LVL297: - 1987 00ca 04F4FE74 and r4, r4, #508 - 1988 00ce 2A19 adds r2, r5, r4 - 1989 .LVL298: - 926:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(p, val); - 1990 .loc 1 926 0 - 1991 00d0 92F83730 ldrb r3, [r2, #55] @ zero_extendqisi2 - 1992 00d4 1B06 lsls r3, r3, #24 - 1993 00d6 2C44 add r4, r4, r5 - 1994 00d8 03F07043 and r3, r3, #-268435456 - 1995 00dc 1F43 orrs r7, r7, r3 - 1996 .LVL299: - 927:../../../Source/third_party/fatfs/src/ff.c **** break; - 1997 .loc 1 927 0 - 1998 00de 84F83470 strb r7, [r4, #52] - 1999 00e2 C7F30723 ubfx r3, r7, #8, #8 - 2000 00e6 82F83530 strb r3, [r2, #53] - 2001 00ea 3B0C lsrs r3, r7, #16 - 2002 00ec 82F83630 strb r3, [r2, #54] - 2003 00f0 3F0E lsrs r7, r7, #24 - 2004 .LVL300: - 2005 00f2 82F83770 strb r7, [r2, #55] - 2006 .LVL301: - 928:../../../Source/third_party/fatfs/src/ff.c **** - 2007 .loc 1 928 0 - 2008 00f6 04E0 b .L162 - 2009 .LVL302: - 2010 .L175: - 931:../../../Source/third_party/fatfs/src/ff.c **** } - 2011 .loc 1 931 0 - 2012 00f8 0226 movs r6, #2 - 2013 00fa 02E0 b .L162 - 2014 .LVL303: - 2015 .L173: - 909:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 2016 .loc 1 909 0 - 2017 00fc 0646 mov r6, r0 - 2018 00fe 00E0 b .L162 - 2019 .L174: - 2020 0100 0646 mov r6, r0 - 2021 .LVL304: - 2022 .L162: - 933:../../../Source/third_party/fatfs/src/ff.c **** } - 2023 .loc 1 933 0 - 2024 0102 0123 movs r3, #1 - 2025 0104 2B71 strb r3, [r5, #4] - 2026 0106 14E0 b .L178 - 2027 .LVL305: - 2028 .L170: - 897:../../../Source/third_party/fatfs/src/ff.c **** - 2029 .loc 1 897 0 - 2030 0108 0226 movs r6, #2 - 2031 010a 12E0 b .L178 - 2032 .L171: - 2033 010c 0226 movs r6, #2 - 2034 .LVL306: - 2035 010e 10E0 b .L178 - 2036 .LVL307: - 2037 .L176: - 911:../../../Source/third_party/fatfs/src/ff.c **** *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); - 2038 .loc 1 911 0 - 2039 0110 C8F30808 ubfx r8, r8, #0, #9 - 2040 .LVL308: - 912:../../../Source/third_party/fatfs/src/ff.c **** break; - 2041 .loc 1 912 0 - 2042 0114 C7F30717 ubfx r7, r7, #4, #8 - 2043 .LVL309: - 2044 0118 B8E7 b .L169 - 2045 .LVL310: - 2046 .L177: - 911:../../../Source/third_party/fatfs/src/ff.c **** *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); - 2047 .loc 1 911 0 - 2048 011a C8F30808 ubfx r8, r8, #0, #9 - 2049 .LVL311: - 912:../../../Source/third_party/fatfs/src/ff.c **** break; - 2050 .loc 1 912 0 - 2051 011e 05EB0803 add r3, r5, r8 - 2052 0122 93F83430 ldrb r3, [r3, #52] @ zero_extendqisi2 - 2053 0126 23F00F03 bic r3, r3, #15 - 2054 012a C7F30327 ubfx r7, r7, #8, #4 - 2055 .LVL312: - 2056 012e 1F43 orrs r7, r7, r3 - 2057 0130 ACE7 b .L169 - 2058 .LVL313: - 2059 .L178: - 937:../../../Source/third_party/fatfs/src/ff.c **** #endif /* !_FS_READONLY */ - 2060 .loc 1 937 0 - 2061 0132 3046 mov r0, r6 - 2062 0134 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 2063 .cfi_endproc - 2064 .LFE9: - 2066 .section .text.create_chain,"ax",%progbits - 2067 .align 2 - 2068 .thumb - 2069 .thumb_func - 2071 create_chain: - 2072 .LFB11: -1005:../../../Source/third_party/fatfs/src/ff.c **** DWORD cs, ncl, scl; - 2073 .loc 1 1005 0 - 2074 .cfi_startproc - 2075 @ args = 0, pretend = 0, frame = 0 - 2076 @ frame_needed = 0, uses_anonymous_args = 0 - 2077 .LVL314: - 2078 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} - 2079 .cfi_def_cfa_offset 24 - 2080 .cfi_offset 4, -24 - 2081 .cfi_offset 5, -20 - 2082 .cfi_offset 6, -16 - 2083 .cfi_offset 7, -12 - 2084 .cfi_offset 8, -8 - 2085 .cfi_offset 14, -4 - 2086 0004 0546 mov r5, r0 -1010:../../../Source/third_party/fatfs/src/ff.c **** scl = fs->last_clust; /* Get suggested start point */ - 2087 .loc 1 1010 0 - 2088 0006 8846 mov r8, r1 - 2089 0008 31B9 cbnz r1, .L181 -1011:../../../Source/third_party/fatfs/src/ff.c **** if (!scl || scl >= fs->n_fatent) scl = 1; - 2090 .loc 1 1011 0 - 2091 000a C668 ldr r6, [r0, #12] - 2092 .LVL315: -1012:../../../Source/third_party/fatfs/src/ff.c **** } - 2093 .loc 1 1012 0 - 2094 000c 6EB1 cbz r6, .L189 -1012:../../../Source/third_party/fatfs/src/ff.c **** } - 2095 .loc 1 1012 0 is_stmt 0 discriminator 2 - 2096 000e 8369 ldr r3, [r0, #24] - 2097 0010 9E42 cmp r6, r3 - 2098 0012 28BF it cs - 2099 0014 0126 movcs r6, #1 - 2100 .LVL316: - 2101 0016 09E0 b .L182 - 2102 .LVL317: - 2103 .L181: -1015:../../../Source/third_party/fatfs/src/ff.c **** if (cs < 2) return 1; /* It is an invalid cluster */ - 2104 .loc 1 1015 0 is_stmt 1 - 2105 0018 FFF7FEFF bl get_fat - 2106 .LVL318: -1016:../../../Source/third_party/fatfs/src/ff.c **** if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ - 2107 .loc 1 1016 0 - 2108 001c 0128 cmp r0, #1 - 2109 001e 41D9 bls .L190 -1017:../../../Source/third_party/fatfs/src/ff.c **** scl = clst; - 2110 .loc 1 1017 0 - 2111 0020 AB69 ldr r3, [r5, #24] - 2112 0022 9842 cmp r0, r3 - 2113 0024 4FD3 bcc .L183 -1018:../../../Source/third_party/fatfs/src/ff.c **** } - 2114 .loc 1 1018 0 - 2115 0026 4646 mov r6, r8 - 2116 0028 00E0 b .L182 - 2117 .LVL319: - 2118 .L189: -1012:../../../Source/third_party/fatfs/src/ff.c **** } - 2119 .loc 1 1012 0 - 2120 002a 0126 movs r6, #1 - 2121 .LVL320: - 2122 .L182: -1021:../../../Source/third_party/fatfs/src/ff.c **** for (;;) { - 2123 .loc 1 1021 0 - 2124 002c 3446 mov r4, r6 -1025:../../../Source/third_party/fatfs/src/ff.c **** if (ncl > scl) return 0; /* No free cluster */ - 2125 .loc 1 1025 0 - 2126 002e 0227 movs r7, #2 - 2127 .LVL321: - 2128 .L186: -1023:../../../Source/third_party/fatfs/src/ff.c **** if (ncl >= fs->n_fatent) { /* Wrap around */ - 2129 .loc 1 1023 0 - 2130 0030 0134 adds r4, r4, #1 - 2131 .LVL322: -1024:../../../Source/third_party/fatfs/src/ff.c **** ncl = 2; - 2132 .loc 1 1024 0 - 2133 0032 AB69 ldr r3, [r5, #24] - 2134 0034 9C42 cmp r4, r3 - 2135 0036 02D3 bcc .L184 - 2136 .LVL323: -1026:../../../Source/third_party/fatfs/src/ff.c **** } - 2137 .loc 1 1026 0 - 2138 0038 012E cmp r6, #1 - 2139 003a 36D9 bls .L192 -1025:../../../Source/third_party/fatfs/src/ff.c **** if (ncl > scl) return 0; /* No free cluster */ - 2140 .loc 1 1025 0 - 2141 003c 3C46 mov r4, r7 - 2142 .LVL324: - 2143 .L184: -1028:../../../Source/third_party/fatfs/src/ff.c **** if (cs == 0) break; /* Found a free cluster */ - 2144 .loc 1 1028 0 - 2145 003e 2846 mov r0, r5 - 2146 0040 2146 mov r1, r4 - 2147 0042 FFF7FEFF bl get_fat - 2148 .LVL325: -1029:../../../Source/third_party/fatfs/src/ff.c **** if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */ - 2149 .loc 1 1029 0 - 2150 0046 38B1 cbz r0, .L185 -1030:../../../Source/third_party/fatfs/src/ff.c **** return cs; - 2151 .loc 1 1030 0 - 2152 0048 B0F1FF3F cmp r0, #-1 - 2153 004c 30D0 beq .L193 -1030:../../../Source/third_party/fatfs/src/ff.c **** return cs; - 2154 .loc 1 1030 0 is_stmt 0 discriminator 1 - 2155 004e 0128 cmp r0, #1 - 2156 0050 32D0 beq .L194 -1032:../../../Source/third_party/fatfs/src/ff.c **** } - 2157 .loc 1 1032 0 is_stmt 1 - 2158 0052 B442 cmp r4, r6 - 2159 0054 ECD1 bne .L186 - 2160 0056 32E0 b .L195 - 2161 .L185: - 2162 0058 2646 mov r6, r4 - 2163 .LVL326: -1035:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK && clst != 0) { - 2164 .loc 1 1035 0 - 2165 005a 2846 mov r0, r5 - 2166 .LVL327: - 2167 005c 2146 mov r1, r4 - 2168 005e 6FF07042 mvn r2, #-268435456 - 2169 0062 FFF7FEFF bl put_fat - 2170 .LVL328: -1036:../../../Source/third_party/fatfs/src/ff.c **** res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */ - 2171 .loc 1 1036 0 - 2172 0066 0346 mov r3, r0 - 2173 0068 A8B9 cbnz r0, .L187 -1036:../../../Source/third_party/fatfs/src/ff.c **** res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */ - 2174 .loc 1 1036 0 is_stmt 0 discriminator 1 - 2175 006a B8F1000F cmp r8, #0 - 2176 006e 06D0 beq .L188 -1037:../../../Source/third_party/fatfs/src/ff.c **** } - 2177 .loc 1 1037 0 is_stmt 1 - 2178 0070 2846 mov r0, r5 - 2179 .LVL329: - 2180 0072 4146 mov r1, r8 - 2181 0074 2246 mov r2, r4 - 2182 0076 FFF7FEFF bl put_fat - 2183 .LVL330: -1039:../../../Source/third_party/fatfs/src/ff.c **** fs->last_clust = ncl; /* Update FSINFO */ - 2184 .loc 1 1039 0 - 2185 007a 0346 mov r3, r0 - 2186 007c 58B9 cbnz r0, .L187 - 2187 .L188: - 2188 .LVL331: -1040:../../../Source/third_party/fatfs/src/ff.c **** if (fs->free_clust != 0xFFFFFFFF) { - 2189 .loc 1 1040 0 - 2190 007e EE60 str r6, [r5, #12] -1041:../../../Source/third_party/fatfs/src/ff.c **** fs->free_clust--; - 2191 .loc 1 1041 0 - 2192 0080 2B69 ldr r3, [r5, #16] - 2193 0082 B3F1FF3F cmp r3, #-1 - 2194 0086 1DD0 beq .L196 -1042:../../../Source/third_party/fatfs/src/ff.c **** fs->fsi_flag = 1; - 2195 .loc 1 1042 0 - 2196 0088 013B subs r3, r3, #1 - 2197 008a 2B61 str r3, [r5, #16] -1043:../../../Source/third_party/fatfs/src/ff.c **** } - 2198 .loc 1 1043 0 - 2199 008c 0123 movs r3, #1 - 2200 008e 6B71 strb r3, [r5, #5] - 2201 0090 2046 mov r0, r4 - 2202 0092 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 2203 .LVL332: - 2204 .L187: -1046:../../../Source/third_party/fatfs/src/ff.c **** } - 2205 .loc 1 1046 0 - 2206 0096 012B cmp r3, #1 - 2207 0098 0CBF ite eq - 2208 009a 4FF0FF30 moveq r0, #-1 - 2209 009e 0120 movne r0, #1 - 2210 00a0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 2211 .LVL333: - 2212 .L190: -1016:../../../Source/third_party/fatfs/src/ff.c **** if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ - 2213 .loc 1 1016 0 - 2214 00a4 0120 movs r0, #1 - 2215 .LVL334: - 2216 00a6 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 2217 .LVL335: - 2218 .L192: -1026:../../../Source/third_party/fatfs/src/ff.c **** } - 2219 .loc 1 1026 0 - 2220 00aa 0020 movs r0, #0 - 2221 00ac BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 2222 .LVL336: - 2223 .L193: -1028:../../../Source/third_party/fatfs/src/ff.c **** if (cs == 0) break; /* Found a free cluster */ - 2224 .loc 1 1028 0 - 2225 00b0 4FF0FF30 mov r0, #-1 - 2226 .LVL337: - 2227 00b4 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 2228 .LVL338: - 2229 .L194: - 2230 00b8 0120 movs r0, #1 - 2231 .LVL339: - 2232 00ba BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 2233 .LVL340: - 2234 .L195: -1032:../../../Source/third_party/fatfs/src/ff.c **** } - 2235 .loc 1 1032 0 - 2236 00be 0020 movs r0, #0 - 2237 .LVL341: - 2238 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 2239 .LVL342: - 2240 .L196: - 2241 00c4 2046 mov r0, r4 - 2242 .LVL343: - 2243 .L183: -1050:../../../Source/third_party/fatfs/src/ff.c **** #endif /* !_FS_READONLY */ - 2244 .loc 1 1050 0 - 2245 00c6 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 2246 .cfi_endproc - 2247 .LFE11: - 2249 00ca 00BF .section .text.dir_next,"ax",%progbits - 2250 .align 2 - 2251 .thumb - 2252 .thumb_func - 2254 dir_next: - 2255 .LFB13: -1140:../../../Source/third_party/fatfs/src/ff.c **** DWORD clst; - 2256 .loc 1 1140 0 - 2257 .cfi_startproc - 2258 @ args = 0, pretend = 0, frame = 0 - 2259 @ frame_needed = 0, uses_anonymous_args = 0 - 2260 .LVL344: - 2261 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} - 2262 .cfi_def_cfa_offset 32 - 2263 .cfi_offset 3, -32 - 2264 .cfi_offset 4, -28 - 2265 .cfi_offset 5, -24 - 2266 .cfi_offset 6, -20 - 2267 .cfi_offset 7, -16 - 2268 .cfi_offset 8, -12 - 2269 .cfi_offset 9, -8 - 2270 .cfi_offset 14, -4 -1146:../../../Source/third_party/fatfs/src/ff.c **** if (!i || !dj->sect) /* Report EOT when index has reached 65535 */ - 2271 .loc 1 1146 0 - 2272 0004 C488 ldrh r4, [r0, #6] - 2273 0006 0134 adds r4, r4, #1 - 2274 0008 A4B2 uxth r4, r4 - 2275 .LVL345: -1147:../../../Source/third_party/fatfs/src/ff.c **** return FR_NO_FILE; - 2276 .loc 1 1147 0 - 2277 000a 002C cmp r4, #0 - 2278 000c 6CD0 beq .L207 -1147:../../../Source/third_party/fatfs/src/ff.c **** return FR_NO_FILE; - 2279 .loc 1 1147 0 is_stmt 0 discriminator 1 - 2280 000e 0369 ldr r3, [r0, #16] - 2281 0010 002B cmp r3, #0 - 2282 0012 6CD0 beq .L208 - 2283 0014 0E46 mov r6, r1 - 2284 0016 0546 mov r5, r0 -1150:../../../Source/third_party/fatfs/src/ff.c **** dj->sect++; /* Next sector */ - 2285 .loc 1 1150 0 is_stmt 1 - 2286 0018 14F00F07 ands r7, r4, #15 - 2287 001c 5BD1 bne .L201 -1151:../../../Source/third_party/fatfs/src/ff.c **** - 2288 .loc 1 1151 0 - 2289 001e 0133 adds r3, r3, #1 - 2290 0020 0361 str r3, [r0, #16] -1153:../../../Source/third_party/fatfs/src/ff.c **** if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */ - 2291 .loc 1 1153 0 - 2292 0022 C168 ldr r1, [r0, #12] - 2293 .LVL346: - 2294 0024 21B9 cbnz r1, .L202 -1154:../../../Source/third_party/fatfs/src/ff.c **** return FR_NO_FILE; - 2295 .loc 1 1154 0 - 2296 0026 0368 ldr r3, [r0] - 2297 0028 1B89 ldrh r3, [r3, #8] - 2298 002a A342 cmp r3, r4 - 2299 002c 62D9 bls .L209 - 2300 002e 52E0 b .L201 - 2301 .L202: -1158:../../../Source/third_party/fatfs/src/ff.c **** clst = get_fat(dj->fs, dj->clust); /* Get next cluster */ - 2302 .loc 1 1158 0 - 2303 0030 0068 ldr r0, [r0] - 2304 .LVL347: - 2305 0032 8378 ldrb r3, [r0, #2] @ zero_extendqisi2 - 2306 0034 013B subs r3, r3, #1 - 2307 0036 13EA1413 ands r3, r3, r4, lsr #4 - 2308 003a 4CD1 bne .L201 -1159:../../../Source/third_party/fatfs/src/ff.c **** if (clst <= 1) return FR_INT_ERR; - 2309 .loc 1 1159 0 - 2310 003c FFF7FEFF bl get_fat - 2311 .LVL348: - 2312 0040 8046 mov r8, r0 - 2313 .LVL349: -1160:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; - 2314 .loc 1 1160 0 - 2315 0042 0128 cmp r0, #1 - 2316 0044 59D9 bls .L210 -1161:../../../Source/third_party/fatfs/src/ff.c **** if (clst >= dj->fs->n_fatent) { /* When it reached end of dynamic table */ - 2317 .loc 1 1161 0 - 2318 0046 B0F1FF3F cmp r0, #-1 - 2319 004a 59D0 beq .L211 -1162:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY - 2320 .loc 1 1162 0 - 2321 004c 2868 ldr r0, [r5] - 2322 .LVL350: - 2323 004e 8369 ldr r3, [r0, #24] - 2324 0050 9845 cmp r8, r3 - 2325 0052 39D3 bcc .L203 - 2326 .LBB10: -1165:../../../Source/third_party/fatfs/src/ff.c **** clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */ - 2327 .loc 1 1165 0 - 2328 0054 002E cmp r6, #0 - 2329 0056 56D0 beq .L212 -1166:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0) return FR_DENIED; /* No free cluster */ - 2330 .loc 1 1166 0 - 2331 0058 E968 ldr r1, [r5, #12] - 2332 005a FFF7FEFF bl create_chain - 2333 .LVL351: -1167:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 1) return FR_INT_ERR; - 2334 .loc 1 1167 0 - 2335 005e 8046 mov r8, r0 - 2336 0060 0028 cmp r0, #0 - 2337 0062 53D0 beq .L213 -1168:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; - 2338 .loc 1 1168 0 - 2339 0064 0128 cmp r0, #1 - 2340 0066 54D0 beq .L214 -1169:../../../Source/third_party/fatfs/src/ff.c **** /* Clean-up stretched table */ - 2341 .loc 1 1169 0 - 2342 0068 B0F1FF3F cmp r0, #-1 - 2343 006c 54D0 beq .L215 -1171:../../../Source/third_party/fatfs/src/ff.c **** mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */ - 2344 .loc 1 1171 0 - 2345 006e 2868 ldr r0, [r5] - 2346 .LVL352: - 2347 0070 FFF7FEFF bl sync_window - 2348 .LVL353: - 2349 0074 0028 cmp r0, #0 - 2350 0076 52D1 bne .L216 -1172:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */ - 2351 .loc 1 1172 0 - 2352 0078 2B68 ldr r3, [r5] - 2353 007a 03F13402 add r2, r3, #52 - 2354 .LVL354: - 2355 007e 03F50D73 add r3, r3, #564 - 2356 .LBB11: - 2357 .LBB12: - 560:../../../Source/third_party/fatfs/src/ff.c **** } - 2358 .loc 1 560 0 - 2359 0082 0021 movs r1, #0 - 2360 .LVL355: - 2361 .L204: - 2362 0084 02F8011B strb r1, [r2], #1 - 2363 .LVL356: - 559:../../../Source/third_party/fatfs/src/ff.c **** *d++ = (BYTE)val; - 2364 .loc 1 559 0 - 2365 0088 9A42 cmp r2, r3 - 2366 008a FBD1 bne .L204 - 2367 .LBE12: - 2368 .LBE11: -1173:../../../Source/third_party/fatfs/src/ff.c **** for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */ - 2369 .loc 1 1173 0 - 2370 008c 2E68 ldr r6, [r5] - 2371 .LVL357: - 2372 008e 3046 mov r0, r6 - 2373 0090 4146 mov r1, r8 - 2374 0092 FFF7FEFF bl clust2sect - 2375 .LVL358: - 2376 0096 3063 str r0, [r6, #48] - 2377 .LVL359: -1174:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->wflag = 1; - 2378 .loc 1 1174 0 - 2379 0098 0026 movs r6, #0 -1175:../../../Source/third_party/fatfs/src/ff.c **** if (sync_window(dj->fs)) return FR_DISK_ERR; - 2380 .loc 1 1175 0 - 2381 009a 4FF00109 mov r9, #1 -1174:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->wflag = 1; - 2382 .loc 1 1174 0 - 2383 009e 0BE0 b .L205 - 2384 .LVL360: - 2385 .L206: -1175:../../../Source/third_party/fatfs/src/ff.c **** if (sync_window(dj->fs)) return FR_DISK_ERR; - 2386 .loc 1 1175 0 - 2387 00a0 83F80490 strb r9, [r3, #4] -1176:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->winsect++; - 2388 .loc 1 1176 0 - 2389 00a4 2868 ldr r0, [r5] - 2390 00a6 FFF7FEFF bl sync_window - 2391 .LVL361: - 2392 00aa 0136 adds r6, r6, #1 - 2393 .LVL362: - 2394 00ac 0028 cmp r0, #0 - 2395 00ae 39D1 bne .L217 -1177:../../../Source/third_party/fatfs/src/ff.c **** } - 2396 .loc 1 1177 0 discriminator 2 - 2397 00b0 2A68 ldr r2, [r5] - 2398 00b2 136B ldr r3, [r2, #48] - 2399 00b4 0133 adds r3, r3, #1 - 2400 00b6 1363 str r3, [r2, #48] - 2401 .LVL363: - 2402 .L205: - 2403 00b8 F1B2 uxtb r1, r6 - 2404 .LVL364: -1174:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->wflag = 1; - 2405 .loc 1 1174 0 discriminator 1 - 2406 00ba 2B68 ldr r3, [r5] - 2407 00bc 9A78 ldrb r2, [r3, #2] @ zero_extendqisi2 - 2408 00be 8A42 cmp r2, r1 - 2409 00c0 EED8 bhi .L206 -1179:../../../Source/third_party/fatfs/src/ff.c **** #else - 2410 .loc 1 1179 0 - 2411 00c2 1A6B ldr r2, [r3, #48] - 2412 00c4 521A subs r2, r2, r1 - 2413 00c6 1A63 str r2, [r3, #48] - 2414 .LVL365: - 2415 .L203: - 2416 .LBE10: -1184:../../../Source/third_party/fatfs/src/ff.c **** dj->sect = clust2sect(dj->fs, clst); - 2417 .loc 1 1184 0 - 2418 00c8 C5F80C80 str r8, [r5, #12] -1185:../../../Source/third_party/fatfs/src/ff.c **** } - 2419 .loc 1 1185 0 - 2420 00cc 2868 ldr r0, [r5] - 2421 00ce 4146 mov r1, r8 - 2422 00d0 FFF7FEFF bl clust2sect - 2423 .LVL366: - 2424 00d4 2861 str r0, [r5, #16] - 2425 .LVL367: - 2426 .L201: -1190:../../../Source/third_party/fatfs/src/ff.c **** dj->dir = dj->fs->win + (i % (SS(dj->fs) / SZ_DIR)) * SZ_DIR; - 2427 .loc 1 1190 0 - 2428 00d6 EC80 strh r4, [r5, #6] @ movhi -1191:../../../Source/third_party/fatfs/src/ff.c **** - 2429 .loc 1 1191 0 - 2430 00d8 2B68 ldr r3, [r5] - 2431 00da 03EB4713 add r3, r3, r7, lsl #5 - 2432 00de 3433 adds r3, r3, #52 - 2433 00e0 6B61 str r3, [r5, #20] -1193:../../../Source/third_party/fatfs/src/ff.c **** } - 2434 .loc 1 1193 0 - 2435 00e2 0020 movs r0, #0 - 2436 00e4 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} - 2437 .LVL368: - 2438 .L207: -1148:../../../Source/third_party/fatfs/src/ff.c **** - 2439 .loc 1 1148 0 - 2440 00e8 0420 movs r0, #4 - 2441 .LVL369: - 2442 00ea BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} - 2443 .LVL370: - 2444 .L208: - 2445 00ee 0420 movs r0, #4 - 2446 .LVL371: - 2447 00f0 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} - 2448 .LVL372: - 2449 .L209: -1155:../../../Source/third_party/fatfs/src/ff.c **** } - 2450 .loc 1 1155 0 - 2451 00f4 0420 movs r0, #4 - 2452 .LVL373: - 2453 00f6 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} - 2454 .LVL374: - 2455 .L210: -1160:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; - 2456 .loc 1 1160 0 - 2457 00fa 0220 movs r0, #2 - 2458 .LVL375: - 2459 00fc BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} - 2460 .LVL376: - 2461 .L211: -1161:../../../Source/third_party/fatfs/src/ff.c **** if (clst >= dj->fs->n_fatent) { /* When it reached end of dynamic table */ - 2462 .loc 1 1161 0 - 2463 0100 0120 movs r0, #1 - 2464 .LVL377: - 2465 0102 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} - 2466 .LVL378: - 2467 .L212: - 2468 .LBB13: -1165:../../../Source/third_party/fatfs/src/ff.c **** clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */ - 2469 .loc 1 1165 0 - 2470 0106 0420 movs r0, #4 - 2471 0108 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} - 2472 .LVL379: - 2473 .L213: -1167:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 1) return FR_INT_ERR; - 2474 .loc 1 1167 0 - 2475 010c 0720 movs r0, #7 - 2476 .LVL380: - 2477 010e BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} - 2478 .LVL381: - 2479 .L214: -1168:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; - 2480 .loc 1 1168 0 - 2481 0112 0220 movs r0, #2 - 2482 .LVL382: - 2483 0114 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} - 2484 .LVL383: - 2485 .L215: -1169:../../../Source/third_party/fatfs/src/ff.c **** /* Clean-up stretched table */ - 2486 .loc 1 1169 0 - 2487 0118 0120 movs r0, #1 - 2488 .LVL384: - 2489 011a BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} - 2490 .LVL385: - 2491 .L216: -1171:../../../Source/third_party/fatfs/src/ff.c **** mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */ - 2492 .loc 1 1171 0 - 2493 011e 0120 movs r0, #1 - 2494 0120 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} - 2495 .LVL386: - 2496 .L217: -1176:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->winsect++; - 2497 .loc 1 1176 0 - 2498 0124 0120 movs r0, #1 - 2499 .LBE13: -1194:../../../Source/third_party/fatfs/src/ff.c **** - 2500 .loc 1 1194 0 - 2501 0126 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} - 2502 .cfi_endproc - 2503 .LFE13: - 2505 012a 00BF .section .text.dir_find,"ax",%progbits - 2506 .align 2 - 2507 .thumb - 2508 .thumb_func - 2510 dir_find: - 2511 .LFB22: -1448:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 2512 .loc 1 1448 0 - 2513 .cfi_startproc - 2514 @ args = 0, pretend = 0, frame = 16 - 2515 @ frame_needed = 0, uses_anonymous_args = 0 - 2516 .LVL387: - 2517 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} - 2518 .cfi_def_cfa_offset 36 - 2519 .cfi_offset 4, -36 - 2520 .cfi_offset 5, -32 - 2521 .cfi_offset 6, -28 - 2522 .cfi_offset 7, -24 - 2523 .cfi_offset 8, -20 - 2524 .cfi_offset 9, -16 - 2525 .cfi_offset 10, -12 - 2526 .cfi_offset 11, -8 - 2527 .cfi_offset 14, -4 - 2528 0004 85B0 sub sp, sp, #20 - 2529 .cfi_def_cfa_offset 56 - 2530 0006 0546 mov r5, r0 -1455:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) return res; - 2531 .loc 1 1455 0 - 2532 0008 0021 movs r1, #0 - 2533 000a FFF7FEFF bl dir_sdi - 2534 .LVL388: -1456:../../../Source/third_party/fatfs/src/ff.c **** - 2535 .loc 1 1456 0 - 2536 000e 0028 cmp r0, #0 - 2537 0010 40F09680 bne .L237 - 2538 0014 4FF0FF09 mov r9, #255 - 2539 0018 4F46 mov r7, r9 -1470:../../../Source/third_party/fatfs/src/ff.c **** } else { - 2540 .loc 1 1470 0 - 2541 001a C846 mov r8, r9 - 2542 001c 524B ldr r3, .L252 - 2543 001e 03F10D0B add fp, r3, #13 - 2544 .L236: - 2545 .LVL389: -1462:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 2546 .loc 1 1462 0 - 2547 0022 2868 ldr r0, [r5] - 2548 .LVL390: - 2549 0024 2969 ldr r1, [r5, #16] - 2550 0026 FFF7FEFF bl move_window - 2551 .LVL391: -1463:../../../Source/third_party/fatfs/src/ff.c **** dir = dj->dir; /* Ptr to the directory entry of current index */ - 2552 .loc 1 1463 0 - 2553 002a 0028 cmp r0, #0 - 2554 002c 40F08980 bne .L238 -1464:../../../Source/third_party/fatfs/src/ff.c **** c = dir[DIR_Name]; - 2555 .loc 1 1464 0 - 2556 0030 6C69 ldr r4, [r5, #20] - 2557 .LVL392: -1465:../../../Source/third_party/fatfs/src/ff.c **** if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ - 2558 .loc 1 1465 0 - 2559 0032 2678 ldrb r6, [r4] @ zero_extendqisi2 - 2560 .LVL393: -1466:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN /* LFN configuration */ - 2561 .loc 1 1466 0 - 2562 0034 002E cmp r6, #0 - 2563 0036 00F08580 beq .L239 -1468:../../../Source/third_party/fatfs/src/ff.c **** if (c == DDE || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ - 2564 .loc 1 1468 0 - 2565 003a E37A ldrb r3, [r4, #11] @ zero_extendqisi2 - 2566 003c 03F03F02 and r2, r3, #63 - 2567 .LVL394: -1469:../../../Source/third_party/fatfs/src/ff.c **** ord = 0xFF; - 2568 .loc 1 1469 0 - 2569 0040 E52E cmp r6, #229 - 2570 0042 6ED0 beq .L240 -1469:../../../Source/third_party/fatfs/src/ff.c **** ord = 0xFF; - 2571 .loc 1 1469 0 is_stmt 0 discriminator 1 - 2572 0044 13F0080F tst r3, #8 - 2573 0048 02D0 beq .L223 -1469:../../../Source/third_party/fatfs/src/ff.c **** ord = 0xFF; - 2574 .loc 1 1469 0 discriminator 2 - 2575 004a 0F2A cmp r2, #15 - 2576 004c 6BD1 bne .L241 - 2577 004e 01E0 b .L224 - 2578 .L223: -1472:../../../Source/third_party/fatfs/src/ff.c **** if (dj->lfn) { - 2579 .loc 1 1472 0 is_stmt 1 - 2580 0050 0F2A cmp r2, #15 - 2581 0052 4BD1 bne .L225 - 2582 .L224: -1473:../../../Source/third_party/fatfs/src/ff.c **** if (c & LLE) { /* Is it start of LFN sequence? */ - 2583 .loc 1 1473 0 - 2584 0054 D5F81CA0 ldr r10, [r5, #28] - 2585 0058 BAF1000F cmp r10, #0 - 2586 005c 68D0 beq .L222 -1474:../../../Source/third_party/fatfs/src/ff.c **** sum = dir[LDIR_Chksum]; - 2587 .loc 1 1474 0 - 2588 005e 16F0400F tst r6, #64 - 2589 0062 06D0 beq .L226 -1475:../../../Source/third_party/fatfs/src/ff.c **** c &= ~LLE; ord = c; /* LFN start order */ - 2590 .loc 1 1475 0 - 2591 0064 94F80D90 ldrb r9, [r4, #13] @ zero_extendqisi2 - 2592 .LVL395: -1476:../../../Source/third_party/fatfs/src/ff.c **** dj->lfn_idx = dj->index; - 2593 .loc 1 1476 0 - 2594 0068 06F0BF06 and r6, r6, #191 - 2595 .LVL396: -1477:../../../Source/third_party/fatfs/src/ff.c **** } - 2596 .loc 1 1477 0 - 2597 006c EB88 ldrh r3, [r5, #6] - 2598 006e 2B84 strh r3, [r5, #32] @ movhi - 2599 0070 03E0 b .L227 - 2600 .LVL397: - 2601 .L226: -1480:../../../Source/third_party/fatfs/src/ff.c **** } - 2602 .loc 1 1480 0 - 2603 0072 B742 cmp r7, r6 - 2604 0074 18BF it ne - 2605 0076 4746 movne r7, r8 - 2606 .LVL398: - 2607 0078 5AD1 bne .L222 - 2608 .L227: - 2609 .LVL399: -1480:../../../Source/third_party/fatfs/src/ff.c **** } - 2610 .loc 1 1480 0 is_stmt 0 discriminator 1 - 2611 007a 637B ldrb r3, [r4, #13] @ zero_extendqisi2 - 2612 007c 0193 str r3, [sp, #4] - 2613 007e 4B45 cmp r3, r9 - 2614 0080 53D1 bne .L243 - 2615 .LVL400: - 2616 .LBB18: - 2617 .LBB19: -1286:../../../Source/third_party/fatfs/src/ff.c **** s = 0; wc = 1; - 2618 .loc 1 1286 0 is_stmt 1 - 2619 0082 2378 ldrb r3, [r4] @ zero_extendqisi2 - 2620 0084 23F04003 bic r3, r3, #64 - 2621 0088 013B subs r3, r3, #1 - 2622 008a 03EB4309 add r9, r3, r3, lsl #1 - 2623 .LVL401: - 2624 008e 03EB8909 add r9, r3, r9, lsl #2 - 2625 .LVL402: - 2626 0092 354F ldr r7, .L252 -1287:../../../Source/third_party/fatfs/src/ff.c **** do { - 2627 .loc 1 1287 0 - 2628 0094 0120 movs r0, #1 - 2629 .LVL403: - 2630 .L231: -1289:../../../Source/third_party/fatfs/src/ff.c **** if (wc) { /* Last char has not been processed */ - 2631 .loc 1 1289 0 - 2632 0096 17F8012B ldrb r2, [r7], #1 @ zero_extendqisi2 - 2633 .LVL404: - 2634 009a A318 adds r3, r4, r2 - 2635 009c 5978 ldrb r1, [r3, #1] @ zero_extendqisi2 - 2636 009e A35C ldrb r3, [r4, r2] @ zero_extendqisi2 - 2637 00a0 43EA0123 orr r3, r3, r1, lsl #8 - 2638 .LVL405: -1290:../../../Source/third_party/fatfs/src/ff.c **** wc = ff_wtoupper(uc); /* Convert it to upper case */ - 2639 .loc 1 1290 0 - 2640 00a4 98B1 cbz r0, .L228 -1291:../../../Source/third_party/fatfs/src/ff.c **** if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */ - 2641 .loc 1 1291 0 - 2642 00a6 1846 mov r0, r3 - 2643 .LVL406: - 2644 00a8 FFF7FEFF bl ff_wtoupper - 2645 .LVL407: - 2646 00ac 0290 str r0, [sp, #8] - 2647 .LVL408: -1292:../../../Source/third_party/fatfs/src/ff.c **** return 0; /* Not matched */ - 2648 .loc 1 1292 0 - 2649 00ae B9F1FE0F cmp r9, #254 - 2650 00b2 52D8 bhi .L229 - 2651 00b4 09F10103 add r3, r9, #1 - 2652 00b8 0393 str r3, [sp, #12] - 2653 .LVL409: - 2654 00ba 3AF81900 ldrh r0, [r10, r9, lsl #1] - 2655 00be FFF7FEFF bl ff_wtoupper - 2656 .LVL410: - 2657 00c2 029A ldr r2, [sp, #8] - 2658 00c4 8242 cmp r2, r0 - 2659 00c6 48D1 bne .L229 - 2660 00c8 DDF80C90 ldr r9, [sp, #12] - 2661 00cc 03E0 b .L230 - 2662 .LVL411: - 2663 .L228: -1295:../../../Source/third_party/fatfs/src/ff.c **** } - 2664 .loc 1 1295 0 - 2665 00ce 4FF6FF72 movw r2, #65535 - 2666 00d2 9342 cmp r3, r2 - 2667 00d4 41D1 bne .L229 - 2668 .LVL412: - 2669 .L230: -1297:../../../Source/third_party/fatfs/src/ff.c **** - 2670 .loc 1 1297 0 - 2671 00d6 5F45 cmp r7, fp - 2672 00d8 DDD1 bne .L231 -1299:../../../Source/third_party/fatfs/src/ff.c **** return 0; - 2673 .loc 1 1299 0 - 2674 00da 2378 ldrb r3, [r4] @ zero_extendqisi2 - 2675 00dc 13F0400F tst r3, #64 - 2676 00e0 36D0 beq .L232 - 2677 00e2 A8B3 cbz r0, .L232 - 2678 00e4 3AF81930 ldrh r3, [r10, r9, lsl #1] - 2679 00e8 93B3 cbz r3, .L232 - 2680 00ea 36E0 b .L229 - 2681 .LVL413: - 2682 .L225: - 2683 .LBE19: - 2684 .LBE18: -1483:../../../Source/third_party/fatfs/src/ff.c **** ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */ - 2685 .loc 1 1483 0 - 2686 00ec 27B9 cbnz r7, .L233 -1483:../../../Source/third_party/fatfs/src/ff.c **** ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */ - 2687 .loc 1 1483 0 is_stmt 0 discriminator 1 - 2688 00ee 2046 mov r0, r4 - 2689 .LVL414: - 2690 00f0 FFF7FEFF bl sum_sfn - 2691 .LVL415: - 2692 00f4 4845 cmp r0, r9 - 2693 00f6 27D0 beq .L244 - 2694 .L233: - 2695 .LVL416: -1484:../../../Source/third_party/fatfs/src/ff.c **** if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */ - 2696 .loc 1 1484 0 is_stmt 1 - 2697 00f8 4FF6FF73 movw r3, #65535 - 2698 00fc 2B84 strh r3, [r5, #32] @ movhi -1485:../../../Source/third_party/fatfs/src/ff.c **** } - 2699 .loc 1 1485 0 - 2700 00fe AB69 ldr r3, [r5, #24] - 2701 0100 DA7A ldrb r2, [r3, #11] @ zero_extendqisi2 - 2702 0102 12F0010F tst r2, #1 - 2703 0106 12D1 bne .L245 - 2704 0108 04F10B00 add r0, r4, #11 - 2705 010c 01E0 b .L234 - 2706 .LVL417: - 2707 .L235: - 2708 .LBB20: - 2709 .LBB21: - 569:../../../Source/third_party/fatfs/src/ff.c **** return r; - 2710 .loc 1 569 0 - 2711 010e 8442 cmp r4, r0 - 2712 0110 1CD0 beq .L246 - 2713 .LVL418: - 2714 .L234: - 2715 0112 14F8011B ldrb r1, [r4], #1 @ zero_extendqisi2 - 2716 .LVL419: - 2717 0116 13F8012B ldrb r2, [r3], #1 @ zero_extendqisi2 - 2718 .LVL420: - 2719 011a 9142 cmp r1, r2 - 2720 011c F7D0 beq .L235 - 2721 .LBE21: - 2722 .LBE20: -1484:../../../Source/third_party/fatfs/src/ff.c **** if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */ - 2723 .loc 1 1484 0 - 2724 011e 4746 mov r7, r8 - 2725 0120 06E0 b .L222 - 2726 .LVL421: - 2727 .L240: -1470:../../../Source/third_party/fatfs/src/ff.c **** } else { - 2728 .loc 1 1470 0 - 2729 0122 4746 mov r7, r8 - 2730 .LVL422: - 2731 0124 04E0 b .L222 - 2732 .LVL423: - 2733 .L241: - 2734 0126 4746 mov r7, r8 - 2735 .LVL424: - 2736 0128 02E0 b .L222 - 2737 .LVL425: - 2738 .L243: -1480:../../../Source/third_party/fatfs/src/ff.c **** } - 2739 .loc 1 1480 0 - 2740 012a 4746 mov r7, r8 - 2741 012c 00E0 b .L222 - 2742 .LVL426: - 2743 .L245: -1484:../../../Source/third_party/fatfs/src/ff.c **** if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */ - 2744 .loc 1 1484 0 - 2745 012e 4746 mov r7, r8 - 2746 .LVL427: - 2747 .L222: -1492:../../../Source/third_party/fatfs/src/ff.c **** } while (res == FR_OK); - 2748 .loc 1 1492 0 - 2749 0130 2846 mov r0, r5 - 2750 0132 0021 movs r1, #0 - 2751 0134 FFF7FEFF bl dir_next - 2752 .LVL428: -1493:../../../Source/third_party/fatfs/src/ff.c **** - 2753 .loc 1 1493 0 - 2754 0138 0028 cmp r0, #0 - 2755 013a 3FF472AF beq .L236 - 2756 013e 10E0 b .L250 - 2757 .LVL429: - 2758 .L237: - 2759 0140 0FE0 b .L250 - 2760 .LVL430: - 2761 .L238: - 2762 0142 0EE0 b .L250 - 2763 .LVL431: - 2764 .L239: -1466:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN /* LFN configuration */ - 2765 .loc 1 1466 0 - 2766 0144 0420 movs r0, #4 - 2767 .LVL432: - 2768 0146 0CE0 b .L250 - 2769 .L244: -1462:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 2770 .loc 1 1462 0 - 2771 0148 0020 movs r0, #0 - 2772 014a 0AE0 b .L250 - 2773 .LVL433: - 2774 .L246: - 2775 014c 0020 movs r0, #0 - 2776 .LVL434: - 2777 014e 08E0 b .L250 - 2778 .LVL435: - 2779 .L232: -1480:../../../Source/third_party/fatfs/src/ff.c **** } - 2780 .loc 1 1480 0 - 2781 0150 013E subs r6, r6, #1 - 2782 .LVL436: - 2783 0152 F7B2 uxtb r7, r6 - 2784 .LVL437: - 2785 0154 DDF80490 ldr r9, [sp, #4] - 2786 .LVL438: - 2787 0158 EAE7 b .L222 - 2788 .LVL439: - 2789 .L229: -1484:../../../Source/third_party/fatfs/src/ff.c **** if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */ - 2790 .loc 1 1484 0 - 2791 015a DDF80490 ldr r9, [sp, #4] -1480:../../../Source/third_party/fatfs/src/ff.c **** } - 2792 .loc 1 1480 0 - 2793 015e 4746 mov r7, r8 - 2794 0160 E6E7 b .L222 - 2795 .LVL440: - 2796 .L250: -1496:../../../Source/third_party/fatfs/src/ff.c **** - 2797 .loc 1 1496 0 - 2798 0162 05B0 add sp, sp, #20 - 2799 .cfi_def_cfa_offset 36 - 2800 @ sp needed - 2801 0164 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} - 2802 .LVL441: - 2803 .L253: - 2804 .align 2 - 2805 .L252: - 2806 0168 00000000 .word .LANCHOR2 - 2807 .cfi_endproc - 2808 .LFE22: - 2810 .section .text.follow_path,"ax",%progbits - 2811 .align 2 - 2812 .thumb - 2813 .thumb_func - 2815 follow_path: - 2816 .LFB28: -1983:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 2817 .loc 1 1983 0 - 2818 .cfi_startproc - 2819 @ args = 0, pretend = 0, frame = 8 - 2820 @ frame_needed = 0, uses_anonymous_args = 0 - 2821 .LVL442: - 2822 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} - 2823 .cfi_def_cfa_offset 36 - 2824 .cfi_offset 4, -36 - 2825 .cfi_offset 5, -32 - 2826 .cfi_offset 6, -28 - 2827 .cfi_offset 7, -24 - 2828 .cfi_offset 8, -20 - 2829 .cfi_offset 9, -16 - 2830 .cfi_offset 10, -12 - 2831 .cfi_offset 11, -8 - 2832 .cfi_offset 14, -4 - 2833 0004 83B0 sub sp, sp, #12 - 2834 .cfi_def_cfa_offset 48 - 2835 0006 0546 mov r5, r0 - 2836 0008 8946 mov r9, r1 -1995:../../../Source/third_party/fatfs/src/ff.c **** path++; - 2837 .loc 1 1995 0 - 2838 000a 0B78 ldrb r3, [r1] @ zero_extendqisi2 - 2839 000c 2F2B cmp r3, #47 - 2840 000e 01D0 beq .L255 -1995:../../../Source/third_party/fatfs/src/ff.c **** path++; - 2841 .loc 1 1995 0 is_stmt 0 discriminator 1 - 2842 0010 5C2B cmp r3, #92 - 2843 0012 01D1 bne .L256 - 2844 .L255: -1996:../../../Source/third_party/fatfs/src/ff.c **** dj->sclust = 0; /* Start from the root dir */ - 2845 .loc 1 1996 0 is_stmt 1 - 2846 0014 09F10109 add r9, r9, #1 - 2847 .LVL443: - 2848 .L256: -1997:../../../Source/third_party/fatfs/src/ff.c **** #endif - 2849 .loc 1 1997 0 - 2850 0018 0023 movs r3, #0 - 2851 001a AB60 str r3, [r5, #8] -2000:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(dj, 0); - 2852 .loc 1 2000 0 - 2853 001c 99F80030 ldrb r3, [r9] @ zero_extendqisi2 - 2854 0020 1F2B cmp r3, #31 - 2855 0022 07D8 bhi .L322 -2001:../../../Source/third_party/fatfs/src/ff.c **** dj->dir = 0; - 2856 .loc 1 2001 0 - 2857 0024 2846 mov r0, r5 - 2858 .LVL444: - 2859 0026 0021 movs r1, #0 - 2860 0028 FFF7FEFF bl dir_sdi - 2861 .LVL445: - 2862 002c 0346 mov r3, r0 - 2863 .LVL446: -2002:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Follow path */ - 2864 .loc 1 2002 0 - 2865 002e 0022 movs r2, #0 - 2866 0030 6A61 str r2, [r5, #20] - 2867 0032 5CE1 b .L316 - 2868 .LVL447: - 2869 .L322: - 2870 0034 CA46 mov r10, r9 - 2871 .LVL448: - 2872 .LBB30: - 2873 .LBB31: -1699:../../../Source/third_party/fatfs/src/ff.c **** lfn = dj->lfn; - 2874 .loc 1 1699 0 - 2875 0036 19F8013B ldrb r3, [r9], #1 @ zero_extendqisi2 - 2876 .LVL449: - 2877 003a 2F2B cmp r3, #47 - 2878 003c FAD0 beq .L322 - 2879 003e 5C2B cmp r3, #92 - 2880 0040 F8D0 beq .L322 -1700:../../../Source/third_party/fatfs/src/ff.c **** si = di = 0; - 2881 .loc 1 1700 0 - 2882 0042 EE69 ldr r6, [r5, #28] - 2883 .LVL450: -1703:../../../Source/third_party/fatfs/src/ff.c **** if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ - 2884 .loc 1 1703 0 - 2885 0044 9AF80000 ldrb r0, [r10] @ zero_extendqisi2 - 2886 .LVL451: -1704:../../../Source/third_party/fatfs/src/ff.c **** if (di >= _MAX_LFN) /* Reject too long name */ - 2887 .loc 1 1704 0 - 2888 0048 1F28 cmp r0, #31 - 2889 004a 40F22681 bls .L309 - 2890 004e 2F28 cmp r0, #47 - 2891 0050 00F02981 beq .L310 - 2892 0054 5C28 cmp r0, #92 - 2893 0056 00F02A81 beq .L311 - 2894 005a A6F10208 sub r8, r6, #2 - 2895 005e 5746 mov r7, r10 - 2896 0060 0124 movs r4, #1 -1715:../../../Source/third_party/fatfs/src/ff.c **** if (!w) return FR_INVALID_NAME; /* Reject invalid code */ - 2897 .loc 1 1715 0 - 2898 0062 A346 mov fp, r4 - 2899 0064 0AE0 b .L262 - 2900 .LVL452: - 2901 .L323: -1704:../../../Source/third_party/fatfs/src/ff.c **** if (di >= _MAX_LFN) /* Reject too long name */ - 2902 .loc 1 1704 0 - 2903 0066 2F28 cmp r0, #47 - 2904 0068 00F02481 beq .L261 - 2905 006c 5C28 cmp r0, #92 - 2906 006e 00F02181 beq .L261 -1705:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_NAME; - 2907 .loc 1 1705 0 - 2908 0072 B9F5807F cmp r9, #256 - 2909 0076 00F03081 beq .L263 -1703:../../../Source/third_party/fatfs/src/ff.c **** if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ - 2910 .loc 1 1703 0 - 2911 007a 4C46 mov r4, r9 - 2912 .LVL453: - 2913 .L262: -1715:../../../Source/third_party/fatfs/src/ff.c **** if (!w) return FR_INVALID_NAME; /* Reject invalid code */ - 2914 .loc 1 1715 0 - 2915 007c 5946 mov r1, fp - 2916 007e FFF7FEFF bl ff_convert - 2917 .LVL454: -1716:../../../Source/third_party/fatfs/src/ff.c **** #endif - 2918 .loc 1 1716 0 - 2919 0082 0146 mov r1, r0 - 2920 0084 0028 cmp r0, #0 - 2921 0086 00F02881 beq .L263 -1718:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_NAME; - 2922 .loc 1 1718 0 - 2923 008a 7F28 cmp r0, #127 - 2924 008c 09D8 bhi .L264 - 2925 .LVL455: - 2926 .LBB32: - 2927 .LBB33: - 576:../../../Source/third_party/fatfs/src/ff.c **** return *str; - 2928 .loc 1 576 0 - 2929 008e 2229 cmp r1, #34 - 2930 0090 00F0E880 beq .L265 - 2931 0094 984A ldr r2, .L334 - 2932 .LVL456: - 2933 .L266: - 2934 0096 12F8013F ldrb r3, [r2, #1]! @ zero_extendqisi2 - 2935 .LVL457: - 2936 009a 13B1 cbz r3, .L264 - 2937 009c 9842 cmp r0, r3 - 2938 009e FAD1 bne .L266 - 2939 00a0 E0E0 b .L265 - 2940 .LVL458: - 2941 .L264: - 2942 .LBE33: - 2943 .LBE32: -1720:../../../Source/third_party/fatfs/src/ff.c **** } - 2944 .loc 1 1720 0 - 2945 00a2 28F8021F strh r1, [r8, #2]! @ movhi -1703:../../../Source/third_party/fatfs/src/ff.c **** if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ - 2946 .loc 1 1703 0 - 2947 00a6 04F10109 add r9, r4, #1 - 2948 .LVL459: - 2949 00aa 17F8010F ldrb r0, [r7, #1]! @ zero_extendqisi2 - 2950 .LVL460: -1704:../../../Source/third_party/fatfs/src/ff.c **** if (di >= _MAX_LFN) /* Reject too long name */ - 2951 .loc 1 1704 0 - 2952 00ae 1F28 cmp r0, #31 - 2953 00b0 D9D8 bhi .L323 - 2954 00b2 F5E0 b .L260 - 2955 .LVL461: - 2956 .L304: -1734:../../../Source/third_party/fatfs/src/ff.c **** w = lfn[di-1]; - 2957 .loc 1 1734 0 - 2958 00b4 002C cmp r4, #0 - 2959 00b6 00F0D580 beq .L265 - 2960 00ba 06EB4402 add r2, r6, r4, lsl #1 - 2961 .LVL462: - 2962 .L270: -1735:../../../Source/third_party/fatfs/src/ff.c **** if (w != ' ' && w != '.') break; - 2963 .loc 1 1735 0 - 2964 00be 32F8023D ldrh r3, [r2, #-2]! - 2965 .LVL463: -1736:../../../Source/third_party/fatfs/src/ff.c **** di--; - 2966 .loc 1 1736 0 - 2967 00c2 202B cmp r3, #32 - 2968 00c4 01D0 beq .L268 - 2969 00c6 2E2B cmp r3, #46 - 2970 00c8 02D1 bne .L269 - 2971 .L268: - 2972 .LVL464: -1734:../../../Source/third_party/fatfs/src/ff.c **** w = lfn[di-1]; - 2973 .loc 1 1734 0 - 2974 00ca 013C subs r4, r4, #1 - 2975 .LVL465: - 2976 00cc F7D1 bne .L270 - 2977 00ce C9E0 b .L265 - 2978 .L269: -1739:../../../Source/third_party/fatfs/src/ff.c **** - 2979 .loc 1 1739 0 - 2980 00d0 002C cmp r4, #0 - 2981 00d2 00F00281 beq .L263 -1741:../../../Source/third_party/fatfs/src/ff.c **** - 2982 .loc 1 1741 0 - 2983 00d6 6000 lsls r0, r4, #1 - 2984 00d8 0023 movs r3, #0 - 2985 .LVL466: - 2986 00da 26F81430 strh r3, [r6, r4, lsl #1] @ movhi - 2987 .LVL467: -1744:../../../Source/third_party/fatfs/src/ff.c **** for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ - 2988 .loc 1 1744 0 - 2989 00de AB69 ldr r3, [r5, #24] - 2990 .LVL468: - 2991 00e0 03F10B01 add r1, r3, #11 - 2992 .LBB34: - 2993 .LBB35: - 560:../../../Source/third_party/fatfs/src/ff.c **** } - 2994 .loc 1 560 0 - 2995 00e4 2022 movs r2, #32 - 2996 .LVL469: - 2997 .L271: - 2998 00e6 03F8012B strb r2, [r3], #1 - 2999 .LVL470: - 559:../../../Source/third_party/fatfs/src/ff.c **** *d++ = (BYTE)val; - 3000 .loc 1 559 0 - 3001 00ea 8B42 cmp r3, r1 - 3002 00ec FBD1 bne .L271 - 3003 00ee B11E subs r1, r6, #2 - 3004 .LVL471: - 3005 00f0 0023 movs r3, #0 - 3006 .LVL472: - 3007 00f2 00E0 b .L272 - 3008 .LVL473: - 3009 .L273: - 3010 .LBE35: - 3011 .LBE34: -1745:../../../Source/third_party/fatfs/src/ff.c **** if (si) cf |= NS_LOSS | NS_LFN; - 3012 .loc 1 1745 0 - 3013 00f4 0133 adds r3, r3, #1 - 3014 .LVL474: - 3015 .L272: - 3016 00f6 31F8022F ldrh r2, [r1, #2]! - 3017 00fa 202A cmp r2, #32 - 3018 00fc FAD0 beq .L273 - 3019 00fe 2E2A cmp r2, #46 - 3020 0100 F8D0 beq .L273 -1746:../../../Source/third_party/fatfs/src/ff.c **** while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ - 3021 .loc 1 1746 0 - 3022 0102 002B cmp r3, #0 - 3023 0104 00F0D980 beq .L274 - 3024 0108 47F00307 orr r7, r7, #3 - 3025 .LVL475: - 3026 010c D5E0 b .L274 - 3027 .LVL476: - 3028 .L277: -1747:../../../Source/third_party/fatfs/src/ff.c **** - 3029 .loc 1 1747 0 - 3030 010e 013C subs r4, r4, #1 - 3031 .LVL477: - 3032 0110 07D1 bne .L275 - 3033 .LVL478: - 3034 .L278: -1751:../../../Source/third_party/fatfs/src/ff.c **** if (!w) break; /* Break on end of the LFN */ - 3035 .loc 1 1751 0 - 3036 0112 4FF0080B mov fp, #8 - 3037 0116 4FF0000A mov r10, #0 - 3038 .LVL479: - 3039 011a CDF800A0 str r10, [sp] -1764:../../../Source/third_party/fatfs/src/ff.c **** } - 3040 .loc 1 1764 0 - 3041 011e 0194 str r4, [sp, #4] - 3042 0120 04E0 b .L276 - 3043 .LVL480: - 3044 .L275: -1747:../../../Source/third_party/fatfs/src/ff.c **** - 3045 .loc 1 1747 0 - 3046 0122 32F8021D ldrh r1, [r2, #-2]! - 3047 0126 2E29 cmp r1, #46 - 3048 0128 F1D1 bne .L277 - 3049 012a F2E7 b .L278 - 3050 .LVL481: - 3051 .L276: -1751:../../../Source/third_party/fatfs/src/ff.c **** if (!w) break; /* Break on end of the LFN */ - 3052 .loc 1 1751 0 - 3053 012c 03F10108 add r8, r3, #1 - 3054 .LVL482: - 3055 0130 36F81300 ldrh r0, [r6, r3, lsl #1] - 3056 .LVL483: -1752:../../../Source/third_party/fatfs/src/ff.c **** if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ - 3057 .loc 1 1752 0 - 3058 0134 0028 cmp r0, #0 - 3059 0136 60D0 beq .L279 -1753:../../../Source/third_party/fatfs/src/ff.c **** cf |= NS_LOSS | NS_LFN; continue; - 3060 .loc 1 1753 0 - 3061 0138 2028 cmp r0, #32 - 3062 013a 04D0 beq .L280 - 3063 013c 2E28 cmp r0, #46 - 3064 013e 06D1 bne .L281 - 3065 0140 4445 cmp r4, r8 - 3066 0142 00F0CC80 beq .L282 - 3067 .L280: -1754:../../../Source/third_party/fatfs/src/ff.c **** } - 3068 .loc 1 1754 0 - 3069 0146 47F00307 orr r7, r7, #3 - 3070 .LVL484: -1751:../../../Source/third_party/fatfs/src/ff.c **** if (!w) break; /* Break on end of the LFN */ - 3071 .loc 1 1751 0 - 3072 014a 4346 mov r3, r8 - 3073 014c EEE7 b .L276 - 3074 .L281: -1757:../../../Source/third_party/fatfs/src/ff.c **** if (ni == 11) { /* Long extension */ - 3075 .loc 1 1757 0 - 3076 014e DA45 cmp r10, fp - 3077 0150 02D2 bcs .L284 - 3078 0152 4445 cmp r4, r8 - 3079 0154 1AD1 bne .L324 - 3080 0156 C2E0 b .L282 - 3081 .L284: -1758:../../../Source/third_party/fatfs/src/ff.c **** cf |= NS_LOSS | NS_LFN; break; - 3082 .loc 1 1758 0 - 3083 0158 BBF10B0F cmp fp, #11 - 3084 015c 06D1 bne .L286 - 3085 .L308: -1759:../../../Source/third_party/fatfs/src/ff.c **** } - 3086 .loc 1 1759 0 - 3087 015e 47F00307 orr r7, r7, #3 - 3088 .LVL485: -1798:../../../Source/third_party/fatfs/src/ff.c **** - 3089 .loc 1 1798 0 - 3090 0162 AB69 ldr r3, [r5, #24] - 3091 0164 1A78 ldrb r2, [r3] @ zero_extendqisi2 - 3092 0166 E52A cmp r2, #229 - 3093 0168 59D1 bne .L288 - 3094 016a 4BE0 b .L312 - 3095 .L286: -1761:../../../Source/third_party/fatfs/src/ff.c **** if (si > di) break; /* No extension */ - 3096 .loc 1 1761 0 - 3097 016c 4445 cmp r4, r8 - 3098 016e 03D0 beq .L289 - 3099 0170 47F00307 orr r7, r7, #3 - 3100 .LVL486: -1762:../../../Source/third_party/fatfs/src/ff.c **** si = di; i = 8; ni = 11; /* Enter extension section */ - 3101 .loc 1 1762 0 - 3102 0174 A045 cmp r8, r4 - 3103 0176 40D8 bhi .L279 - 3104 .L289: - 3105 .LVL487: -1764:../../../Source/third_party/fatfs/src/ff.c **** } - 3106 .loc 1 1764 0 - 3107 0178 009B ldr r3, [sp] - 3108 017a 9B00 lsls r3, r3, #2 - 3109 017c DBB2 uxtb r3, r3 - 3110 017e 0093 str r3, [sp] - 3111 .LVL488: - 3112 0180 019B ldr r3, [sp, #4] -1763:../../../Source/third_party/fatfs/src/ff.c **** b <<= 2; continue; - 3113 .loc 1 1763 0 - 3114 0182 4FF00B0B mov fp, #11 - 3115 0186 4FF0080A mov r10, #8 - 3116 018a CFE7 b .L276 - 3117 .LVL489: - 3118 .L324: -1767:../../../Source/third_party/fatfs/src/ff.c **** #ifdef _EXCVT - 3119 .loc 1 1767 0 - 3120 018c 7F28 cmp r0, #127 - 3121 018e 40F29B80 bls .L290 -1769:../../../Source/third_party/fatfs/src/ff.c **** if (w) w = ExCvt[w - 0x80]; /* Convert extended char to upper (SBCS) */ - 3122 .loc 1 1769 0 - 3123 0192 0021 movs r1, #0 - 3124 0194 FFF7FEFF bl ff_convert - 3125 .LVL490: -1770:../../../Source/third_party/fatfs/src/ff.c **** #else - 3126 .loc 1 1770 0 - 3127 0198 0346 mov r3, r0 - 3128 019a 0028 cmp r0, #0 - 3129 019c 00F0A480 beq .L291 - 3130 01a0 564A ldr r2, .L334+4 - 3131 01a2 1344 add r3, r3, r2 - 3132 01a4 13F8801C ldrb r1, [r3, #-128] @ zero_extendqisi2 - 3133 01a8 88B2 uxth r0, r1 - 3134 .LVL491: -1774:../../../Source/third_party/fatfs/src/ff.c **** } - 3135 .loc 1 1774 0 - 3136 01aa 47F00207 orr r7, r7, #2 - 3137 .LVL492: -1783:../../../Source/third_party/fatfs/src/ff.c **** w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ - 3138 .loc 1 1783 0 - 3139 01ae 48B1 cbz r0, .L292 - 3140 .L305: - 3141 .LVL493: - 3142 .LBB36: - 3143 .LBB37: - 576:../../../Source/third_party/fatfs/src/ff.c **** return *str; - 3144 .loc 1 576 0 - 3145 01b0 2B29 cmp r1, #43 - 3146 01b2 07D0 beq .L292 - 3147 01b4 524A ldr r2, .L334+8 - 3148 .LVL494: - 3149 .L295: - 3150 01b6 12F8013F ldrb r3, [r2, #1]! @ zero_extendqisi2 - 3151 .LVL495: - 3152 01ba 002B cmp r3, #0 - 3153 01bc 00F08680 beq .L294 - 3154 01c0 9942 cmp r1, r3 - 3155 01c2 F8D1 bne .L295 - 3156 .LVL496: - 3157 .L292: - 3158 .LBE37: - 3159 .LBE36: -1784:../../../Source/third_party/fatfs/src/ff.c **** } else { - 3160 .loc 1 1784 0 - 3161 01c4 47F00307 orr r7, r7, #3 - 3162 .LVL497: - 3163 01c8 5F20 movs r0, #95 - 3164 01ca 0FE0 b .L296 - 3165 .LVL498: - 3166 .L306: -1787:../../../Source/third_party/fatfs/src/ff.c **** } else { - 3167 .loc 1 1787 0 - 3168 01cc 009B ldr r3, [sp] - 3169 01ce 43F00203 orr r3, r3, #2 - 3170 01d2 0093 str r3, [sp] - 3171 .LVL499: - 3172 01d4 0AE0 b .L296 - 3173 .L328: -1789:../../../Source/third_party/fatfs/src/ff.c **** b |= 1; w -= 0x20; - 3174 .loc 1 1789 0 - 3175 01d6 A0F16103 sub r3, r0, #97 - 3176 01da 9BB2 uxth r3, r3 - 3177 01dc 192B cmp r3, #25 - 3178 01de 05D8 bhi .L296 -1790:../../../Source/third_party/fatfs/src/ff.c **** } - 3179 .loc 1 1790 0 - 3180 01e0 009B ldr r3, [sp] - 3181 01e2 43F00103 orr r3, r3, #1 - 3182 01e6 0093 str r3, [sp] - 3183 .LVL500: - 3184 01e8 2038 subs r0, r0, #32 - 3185 .LVL501: - 3186 01ea 80B2 uxth r0, r0 - 3187 .LVL502: - 3188 .L296: -1795:../../../Source/third_party/fatfs/src/ff.c **** } - 3189 .loc 1 1795 0 - 3190 01ec AB69 ldr r3, [r5, #24] - 3191 01ee 03F80A00 strb r0, [r3, r10] -1751:../../../Source/third_party/fatfs/src/ff.c **** if (!w) break; /* Break on end of the LFN */ - 3192 .loc 1 1751 0 - 3193 01f2 4346 mov r3, r8 -1795:../../../Source/third_party/fatfs/src/ff.c **** } - 3194 .loc 1 1795 0 - 3195 01f4 0AF1010A add r10, r10, #1 - 3196 .LVL503: - 3197 01f8 98E7 b .L276 - 3198 .L279: -1798:../../../Source/third_party/fatfs/src/ff.c **** - 3199 .loc 1 1798 0 - 3200 01fa AB69 ldr r3, [r5, #24] - 3201 01fc 1A78 ldrb r2, [r3] @ zero_extendqisi2 - 3202 01fe E52A cmp r2, #229 - 3203 0200 06D1 bne .L313 - 3204 0202 01E0 b .L287 - 3205 .L312: - 3206 0204 4FF00B0B mov fp, #11 - 3207 .LVL504: - 3208 .L287: - 3209 0208 0522 movs r2, #5 - 3210 020a 1A70 strb r2, [r3] - 3211 020c 009B ldr r3, [sp] - 3212 020e 00E0 b .L297 - 3213 .LVL505: - 3214 .L313: - 3215 0210 009B ldr r3, [sp] - 3216 .LVL506: - 3217 .L297: -1800:../../../Source/third_party/fatfs/src/ff.c **** if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capital - 3218 .loc 1 1800 0 - 3219 0212 BBF1080F cmp fp, #8 - 3220 0216 02D1 bne .L288 - 3221 0218 9B00 lsls r3, r3, #2 - 3222 021a DBB2 uxtb r3, r3 - 3223 021c 0093 str r3, [sp] - 3224 .LVL507: - 3225 .L288: -1801:../../../Source/third_party/fatfs/src/ff.c **** cf |= NS_LFN; - 3226 .loc 1 1801 0 - 3227 021e 009A ldr r2, [sp] - 3228 0220 02F00C03 and r3, r2, #12 - 3229 0224 0C2B cmp r3, #12 - 3230 0226 03D0 beq .L298 - 3231 0228 02F00302 and r2, r2, #3 - 3232 022c 032A cmp r2, #3 - 3233 022e 01D1 bne .L299 - 3234 .L298: -1802:../../../Source/third_party/fatfs/src/ff.c **** if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are create - 3235 .loc 1 1802 0 - 3236 0230 47F00207 orr r7, r7, #2 - 3237 .LVL508: - 3238 .L299: -1803:../../../Source/third_party/fatfs/src/ff.c **** if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ - 3239 .loc 1 1803 0 - 3240 0234 17F0020F tst r7, #2 - 3241 0238 0AD1 bne .L300 -1804:../../../Source/third_party/fatfs/src/ff.c **** if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ - 3242 .loc 1 1804 0 - 3243 023a 009A ldr r2, [sp] - 3244 023c 02F00302 and r2, r2, #3 - 3245 0240 012A cmp r2, #1 - 3246 0242 08BF it eq - 3247 0244 47F01007 orreq r7, r7, #16 - 3248 .LVL509: -1805:../../../Source/third_party/fatfs/src/ff.c **** } - 3249 .loc 1 1805 0 - 3250 0248 042B cmp r3, #4 - 3251 024a 08BF it eq - 3252 024c 47F00807 orreq r7, r7, #8 - 3253 .LVL510: - 3254 .L300: -1808:../../../Source/third_party/fatfs/src/ff.c **** - 3255 .loc 1 1808 0 - 3256 0250 AB69 ldr r3, [r5, #24] - 3257 0252 DF72 strb r7, [r3, #11] - 3258 .LBE31: - 3259 .LBE30: -2007:../../../Source/third_party/fatfs/src/ff.c **** ns = *(dj->fn+NS); - 3260 .loc 1 2007 0 - 3261 0254 2846 mov r0, r5 - 3262 .LVL511: - 3263 0256 FFF7FEFF bl dir_find - 3264 .LVL512: -2008:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) { /* Failed to find the object */ - 3265 .loc 1 2008 0 - 3266 025a AB69 ldr r3, [r5, #24] - 3267 025c DA7A ldrb r2, [r3, #11] @ zero_extendqisi2 - 3268 .LVL513: -2009:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_NO_FILE) break; /* Abort if any hard error occurred */ - 3269 .loc 1 2009 0 - 3270 025e 0346 mov r3, r0 - 3271 0260 60B1 cbz r0, .L326 - 3272 0262 01E0 b .L302 - 3273 .LVL514: - 3274 .L265: - 3275 0264 0623 movs r3, #6 - 3276 0266 42E0 b .L316 - 3277 .LVL515: - 3278 .L302: -2010:../../../Source/third_party/fatfs/src/ff.c **** /* Object not found */ - 3279 .loc 1 2010 0 - 3280 0268 0428 cmp r0, #4 - 3281 026a 40D1 bne .L316 -2017:../../../Source/third_party/fatfs/src/ff.c **** } - 3282 .loc 1 2017 0 - 3283 026c 02F00403 and r3, r2, #4 - 3284 0270 DBB2 uxtb r3, r3 - 3285 0272 002B cmp r3, #0 - 3286 0274 14BF ite ne - 3287 0276 0346 movne r3, r0 - 3288 0278 0523 moveq r3, #5 - 3289 027a 38E0 b .L316 - 3290 .L326: -2021:../../../Source/third_party/fatfs/src/ff.c **** dir = dj->dir; /* There is next segment. Follow the sub directory */ - 3291 .loc 1 2021 0 - 3292 027c 12F0040F tst r2, #4 - 3293 0280 35D1 bne .L316 -2022:../../../Source/third_party/fatfs/src/ff.c **** if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */ - 3294 .loc 1 2022 0 - 3295 0282 6969 ldr r1, [r5, #20] - 3296 .LVL516: -2023:../../../Source/third_party/fatfs/src/ff.c **** res = FR_NO_PATH; break; - 3297 .loc 1 2023 0 - 3298 0284 CB7A ldrb r3, [r1, #11] @ zero_extendqisi2 - 3299 0286 13F0100F tst r3, #16 - 3300 028a 04D0 beq .L315 -2026:../../../Source/third_party/fatfs/src/ff.c **** } - 3301 .loc 1 2026 0 - 3302 028c 2868 ldr r0, [r5] - 3303 .LVL517: - 3304 028e FFF7FEFF bl ld_clust - 3305 .LVL518: - 3306 0292 A860 str r0, [r5, #8] -2027:../../../Source/third_party/fatfs/src/ff.c **** } - 3307 .loc 1 2027 0 - 3308 0294 CEE6 b .L322 - 3309 .LVL519: - 3310 .L315: -2024:../../../Source/third_party/fatfs/src/ff.c **** } - 3311 .loc 1 2024 0 - 3312 0296 0523 movs r3, #5 - 3313 0298 29E0 b .L316 - 3314 .LVL520: - 3315 .L309: - 3316 .LBB40: - 3317 .LBB38: -1701:../../../Source/third_party/fatfs/src/ff.c **** for (;;) { - 3318 .loc 1 1701 0 - 3319 029a 0024 movs r4, #0 -1703:../../../Source/third_party/fatfs/src/ff.c **** if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ - 3320 .loc 1 1703 0 - 3321 029c 4FF00109 mov r9, #1 - 3322 .LVL521: - 3323 .L260: -1722:../../../Source/third_party/fatfs/src/ff.c **** cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ - 3324 .loc 1 1722 0 - 3325 02a0 D144 add r9, r9, r10 - 3326 .LVL522: -1723:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_RPATH - 3327 .loc 1 1723 0 - 3328 02a2 0427 movs r7, #4 - 3329 02a4 06E7 b .L304 - 3330 .LVL523: - 3331 .L310: -1701:../../../Source/third_party/fatfs/src/ff.c **** for (;;) { - 3332 .loc 1 1701 0 - 3333 02a6 0024 movs r4, #0 -1703:../../../Source/third_party/fatfs/src/ff.c **** if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ - 3334 .loc 1 1703 0 - 3335 02a8 4FF00109 mov r9, #1 - 3336 02ac 02E0 b .L261 - 3337 .L311: -1701:../../../Source/third_party/fatfs/src/ff.c **** for (;;) { - 3338 .loc 1 1701 0 - 3339 02ae 0024 movs r4, #0 -1703:../../../Source/third_party/fatfs/src/ff.c **** if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ - 3340 .loc 1 1703 0 - 3341 02b0 4FF00109 mov r9, #1 - 3342 .LVL524: - 3343 .L261: -1722:../../../Source/third_party/fatfs/src/ff.c **** cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ - 3344 .loc 1 1722 0 - 3345 02b4 D144 add r9, r9, r10 - 3346 .LVL525: -1723:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_RPATH - 3347 .loc 1 1723 0 - 3348 02b6 0027 movs r7, #0 - 3349 02b8 FCE6 b .L304 - 3350 .LVL526: - 3351 .L274: -1747:../../../Source/third_party/fatfs/src/ff.c **** - 3352 .loc 1 1747 0 - 3353 02ba 811E subs r1, r0, #2 - 3354 02bc 7218 adds r2, r6, r1 - 3355 02be 715A ldrh r1, [r6, r1] - 3356 02c0 2E29 cmp r1, #46 - 3357 02c2 3FF426AF beq .L278 - 3358 02c6 22E7 b .L277 - 3359 .LVL527: - 3360 .L290: -1783:../../../Source/third_party/fatfs/src/ff.c **** w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ - 3361 .loc 1 1783 0 - 3362 02c8 0146 mov r1, r0 - 3363 .LVL528: - 3364 02ca 71E7 b .L305 - 3365 .LVL529: - 3366 .L294: -1786:../../../Source/third_party/fatfs/src/ff.c **** b |= 2; - 3367 .loc 1 1786 0 - 3368 02cc A0F14103 sub r3, r0, #65 - 3369 02d0 9BB2 uxth r3, r3 - 3370 02d2 192B cmp r3, #25 - 3371 02d4 7FF67AAF bls .L306 - 3372 02d8 7DE7 b .L328 - 3373 .LVL530: - 3374 .L263: - 3375 .LBE38: - 3376 .LBE40: -2017:../../../Source/third_party/fatfs/src/ff.c **** } - 3377 .loc 1 2017 0 - 3378 02da 0623 movs r3, #6 - 3379 .LVL531: - 3380 02dc 07E0 b .L316 - 3381 .LVL532: - 3382 .L282: - 3383 .LBB41: - 3384 .LBB39: -1758:../../../Source/third_party/fatfs/src/ff.c **** cf |= NS_LOSS | NS_LFN; break; - 3385 .loc 1 1758 0 - 3386 02de BBF10B0F cmp fp, #11 - 3387 02e2 7FF449AF bne .L289 - 3388 02e6 3AE7 b .L308 - 3389 .L291: - 3390 .LVL533: -1774:../../../Source/third_party/fatfs/src/ff.c **** } - 3391 .loc 1 1774 0 - 3392 02e8 47F00207 orr r7, r7, #2 - 3393 .LVL534: - 3394 02ec 6AE7 b .L292 - 3395 .LVL535: - 3396 .L316: - 3397 .LBE39: - 3398 .LBE41: -2031:../../../Source/third_party/fatfs/src/ff.c **** - 3399 .loc 1 2031 0 - 3400 02ee 1846 mov r0, r3 - 3401 02f0 03B0 add sp, sp, #12 - 3402 .cfi_def_cfa_offset 36 - 3403 @ sp needed - 3404 02f2 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} - 3405 .LVL536: - 3406 .L335: - 3407 02f6 00BF .align 2 - 3408 .L334: - 3409 02f8 00000000 .word .LC0 - 3410 02fc 00000000 .word .LANCHOR3 - 3411 0300 0C000000 .word .LC1 - 3412 .cfi_endproc - 3413 .LFE28: - 3415 .section .text.dir_read,"ax",%progbits - 3416 .align 2 - 3417 .thumb - 3418 .thumb_func - 3420 dir_read: - 3421 .LFB23: -1510:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 3422 .loc 1 1510 0 - 3423 .cfi_startproc - 3424 @ args = 0, pretend = 0, frame = 0 - 3425 @ frame_needed = 0, uses_anonymous_args = 0 - 3426 .LVL537: - 3427 0000 2DE9F84F push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr} - 3428 .cfi_def_cfa_offset 40 - 3429 .cfi_offset 3, -40 - 3430 .cfi_offset 4, -36 - 3431 .cfi_offset 5, -32 - 3432 .cfi_offset 6, -28 - 3433 .cfi_offset 7, -24 - 3434 .cfi_offset 8, -20 - 3435 .cfi_offset 9, -16 - 3436 .cfi_offset 10, -12 - 3437 .cfi_offset 11, -8 - 3438 .cfi_offset 14, -4 - 3439 0004 0446 mov r4, r0 - 3440 0006 8846 mov r8, r1 - 3441 .LVL538: -1514:../../../Source/third_party/fatfs/src/ff.c **** #endif - 3442 .loc 1 1514 0 - 3443 0008 4FF0FF09 mov r9, #255 - 3444 000c 4D46 mov r5, r9 -1517:../../../Source/third_party/fatfs/src/ff.c **** while (dj->sect) { - 3445 .loc 1 1517 0 - 3446 000e 0423 movs r3, #4 -1527:../../../Source/third_party/fatfs/src/ff.c **** } else { - 3447 .loc 1 1527 0 - 3448 0010 4F46 mov r7, r9 - 3449 0012 DFF814B1 ldr fp, .L366 - 3450 0016 0BF10D0A add r10, fp, #13 -1518:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(dj->fs, dj->sect); - 3451 .loc 1 1518 0 - 3452 001a 6FE0 b .L337 - 3453 .LVL539: - 3454 .L350: -1519:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 3455 .loc 1 1519 0 - 3456 001c 2068 ldr r0, [r4] - 3457 001e FFF7FEFF bl move_window - 3458 .LVL540: -1520:../../../Source/third_party/fatfs/src/ff.c **** dir = dj->dir; /* Ptr to the directory entry of current index */ - 3459 .loc 1 1520 0 - 3460 0022 0646 mov r6, r0 - 3461 0024 0028 cmp r0, #0 - 3462 0026 6ED1 bne .L352 -1521:../../../Source/third_party/fatfs/src/ff.c **** c = dir[DIR_Name]; - 3463 .loc 1 1521 0 - 3464 0028 6069 ldr r0, [r4, #20] - 3465 .LVL541: -1522:../../../Source/third_party/fatfs/src/ff.c **** if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ - 3466 .loc 1 1522 0 - 3467 002a 0378 ldrb r3, [r0] @ zero_extendqisi2 - 3468 .LVL542: -1523:../../../Source/third_party/fatfs/src/ff.c **** a = dir[DIR_Attr] & AM_MASK; - 3469 .loc 1 1523 0 - 3470 002c 002B cmp r3, #0 - 3471 002e 74D0 beq .L353 -1524:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN /* LFN configuration */ - 3472 .loc 1 1524 0 - 3473 0030 C27A ldrb r2, [r0, #11] @ zero_extendqisi2 - 3474 .LVL543: -1526:../../../Source/third_party/fatfs/src/ff.c **** ord = 0xFF; - 3475 .loc 1 1526 0 - 3476 0032 E52B cmp r3, #229 - 3477 0034 55D0 beq .L354 -1526:../../../Source/third_party/fatfs/src/ff.c **** ord = 0xFF; - 3478 .loc 1 1526 0 is_stmt 0 discriminator 1 - 3479 0036 2E2B cmp r3, #46 - 3480 0038 55D0 beq .L355 -1524:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN /* LFN configuration */ - 3481 .loc 1 1524 0 is_stmt 1 discriminator 2 - 3482 003a 02F03F02 and r2, r2, #63 - 3483 .LVL544: -1526:../../../Source/third_party/fatfs/src/ff.c **** ord = 0xFF; - 3484 .loc 1 1526 0 discriminator 2 - 3485 003e 082A cmp r2, #8 - 3486 0040 14BF ite ne - 3487 0042 0021 movne r1, #0 - 3488 0044 0121 moveq r1, #1 - 3489 0046 4145 cmp r1, r8 - 3490 0048 4FD1 bne .L356 -1529:../../../Source/third_party/fatfs/src/ff.c **** if (c & LLE) { /* Is it start of LFN sequence? */ - 3491 .loc 1 1529 0 - 3492 004a 0F2A cmp r2, #15 - 3493 004c 40D1 bne .L340 -1530:../../../Source/third_party/fatfs/src/ff.c **** sum = dir[LDIR_Chksum]; - 3494 .loc 1 1530 0 - 3495 004e 13F0400F tst r3, #64 - 3496 0052 06D0 beq .L341 -1531:../../../Source/third_party/fatfs/src/ff.c **** c &= ~LLE; ord = c; - 3497 .loc 1 1531 0 - 3498 0054 90F80D90 ldrb r9, [r0, #13] @ zero_extendqisi2 - 3499 .LVL545: -1532:../../../Source/third_party/fatfs/src/ff.c **** dj->lfn_idx = dj->index; - 3500 .loc 1 1532 0 - 3501 0058 03F0BF03 and r3, r3, #191 - 3502 .LVL546: -1533:../../../Source/third_party/fatfs/src/ff.c **** } - 3503 .loc 1 1533 0 - 3504 005c E288 ldrh r2, [r4, #6] - 3505 005e 2284 strh r2, [r4, #32] @ movhi - 3506 .LVL547: - 3507 0060 03E0 b .L342 - 3508 .LVL548: - 3509 .L341: -1536:../../../Source/third_party/fatfs/src/ff.c **** } else { /* An SFN entry is found */ - 3510 .loc 1 1536 0 - 3511 0062 9D42 cmp r5, r3 - 3512 0064 18BF it ne - 3513 0066 3D46 movne r5, r7 - 3514 .LVL549: - 3515 0068 42D1 bne .L339 - 3516 .LVL550: - 3517 .L342: -1536:../../../Source/third_party/fatfs/src/ff.c **** } else { /* An SFN entry is found */ - 3518 .loc 1 1536 0 is_stmt 0 discriminator 1 - 3519 006a 90F80DE0 ldrb lr, [r0, #13] @ zero_extendqisi2 - 3520 006e CE45 cmp lr, r9 - 3521 0070 3DD1 bne .L358 -1536:../../../Source/third_party/fatfs/src/ff.c **** } else { /* An SFN entry is found */ - 3522 .loc 1 1536 0 discriminator 3 - 3523 0072 D4F81C90 ldr r9, [r4, #28] - 3524 .LVL551: - 3525 .LBB44: - 3526 .LBB45: -1317:../../../Source/third_party/fatfs/src/ff.c **** - 3527 .loc 1 1317 0 is_stmt 1 discriminator 3 - 3528 0076 0278 ldrb r2, [r0] @ zero_extendqisi2 - 3529 0078 02F03F02 and r2, r2, #63 - 3530 007c 013A subs r2, r2, #1 - 3531 007e 02EB4206 add r6, r2, r2, lsl #1 - 3532 0082 02EB8606 add r6, r2, r6, lsl #2 - 3533 .LVL552: - 3534 0086 5D46 mov r5, fp -1319:../../../Source/third_party/fatfs/src/ff.c **** do { - 3535 .loc 1 1319 0 discriminator 3 - 3536 0088 4FF0010C mov ip, #1 -1326:../../../Source/third_party/fatfs/src/ff.c **** } - 3537 .loc 1 1326 0 discriminator 3 - 3538 008c 6146 mov r1, ip - 3539 .LVL553: - 3540 .L346: -1321:../../../Source/third_party/fatfs/src/ff.c **** if (wc) { /* Last char has not been processed */ - 3541 .loc 1 1321 0 - 3542 008e 15F8012B ldrb r2, [r5], #1 @ zero_extendqisi2 - 3543 .LVL554: - 3544 0092 00EB020C add ip, r0, r2 - 3545 0096 9CF801C0 ldrb ip, [ip, #1] @ zero_extendqisi2 - 3546 009a 825C ldrb r2, [r0, r2] @ zero_extendqisi2 - 3547 009c 42EA0C22 orr r2, r2, ip, lsl #8 - 3548 .LVL555: -1322:../../../Source/third_party/fatfs/src/ff.c **** if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ - 3549 .loc 1 1322 0 - 3550 00a0 31B1 cbz r1, .L343 -1323:../../../Source/third_party/fatfs/src/ff.c **** lfnbuf[i++] = wc = uc; /* Store it */ - 3551 .loc 1 1323 0 - 3552 00a2 FE2E cmp r6, #254 - 3553 00a4 36D8 bhi .L344 - 3554 .LVL556: -1324:../../../Source/third_party/fatfs/src/ff.c **** } else { - 3555 .loc 1 1324 0 - 3556 00a6 29F81620 strh r2, [r9, r6, lsl #1] @ movhi - 3557 00aa 1146 mov r1, r2 - 3558 00ac 0136 adds r6, r6, #1 - 3559 .LVL557: - 3560 00ae 03E0 b .L345 - 3561 .LVL558: - 3562 .L343: -1326:../../../Source/third_party/fatfs/src/ff.c **** } - 3563 .loc 1 1326 0 - 3564 00b0 4FF6FF7C movw ip, #65535 - 3565 00b4 6245 cmp r2, ip - 3566 00b6 2DD1 bne .L344 - 3567 .LVL559: - 3568 .L345: -1328:../../../Source/third_party/fatfs/src/ff.c **** - 3569 .loc 1 1328 0 - 3570 00b8 5545 cmp r5, r10 - 3571 00ba E8D1 bne .L346 -1330:../../../Source/third_party/fatfs/src/ff.c **** if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ - 3572 .loc 1 1330 0 - 3573 00bc 0278 ldrb r2, [r0] @ zero_extendqisi2 - 3574 .LVL560: - 3575 00be 12F0400F tst r2, #64 - 3576 00c2 23D0 beq .L347 -1331:../../../Source/third_party/fatfs/src/ff.c **** lfnbuf[i] = 0; - 3577 .loc 1 1331 0 - 3578 00c4 FE2E cmp r6, #254 - 3579 00c6 25D8 bhi .L344 -1332:../../../Source/third_party/fatfs/src/ff.c **** } - 3580 .loc 1 1332 0 - 3581 00c8 0022 movs r2, #0 - 3582 00ca 29F81620 strh r2, [r9, r6, lsl #1] @ movhi - 3583 00ce 1DE0 b .L347 - 3584 .LVL561: - 3585 .L340: - 3586 .LBE45: - 3587 .LBE44: -1538:../../../Source/third_party/fatfs/src/ff.c **** dj->lfn_idx = 0xFFFF; /* It has no LFN. */ - 3588 .loc 1 1538 0 - 3589 00d0 1DB9 cbnz r5, .L348 -1538:../../../Source/third_party/fatfs/src/ff.c **** dj->lfn_idx = 0xFFFF; /* It has no LFN. */ - 3590 .loc 1 1538 0 is_stmt 0 discriminator 1 - 3591 00d2 FFF7FEFF bl sum_sfn - 3592 .LVL562: - 3593 00d6 4845 cmp r0, r9 - 3594 00d8 23D0 beq .L360 - 3595 .L348: -1539:../../../Source/third_party/fatfs/src/ff.c **** break; - 3596 .loc 1 1539 0 is_stmt 1 - 3597 00da 4FF6FF73 movw r3, #65535 - 3598 00de 2384 strh r3, [r4, #32] @ movhi - 3599 00e0 1FE0 b .L360 - 3600 .LVL563: - 3601 .L354: -1527:../../../Source/third_party/fatfs/src/ff.c **** } else { - 3602 .loc 1 1527 0 - 3603 00e2 3D46 mov r5, r7 - 3604 .LVL564: - 3605 00e4 04E0 b .L339 - 3606 .LVL565: - 3607 .L355: - 3608 00e6 3D46 mov r5, r7 - 3609 .LVL566: - 3610 00e8 02E0 b .L339 - 3611 .LVL567: - 3612 .L356: - 3613 00ea 3D46 mov r5, r7 - 3614 .LVL568: - 3615 00ec 00E0 b .L339 - 3616 .LVL569: - 3617 .L358: -1536:../../../Source/third_party/fatfs/src/ff.c **** } else { /* An SFN entry is found */ - 3618 .loc 1 1536 0 - 3619 00ee 3D46 mov r5, r7 - 3620 .LVL570: - 3621 .L339: -1547:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 3622 .loc 1 1547 0 - 3623 00f0 2046 mov r0, r4 - 3624 .LVL571: - 3625 00f2 0021 movs r1, #0 - 3626 00f4 FFF7FEFF bl dir_next - 3627 .LVL572: -1548:../../../Source/third_party/fatfs/src/ff.c **** } - 3628 .loc 1 1548 0 - 3629 00f8 0346 mov r3, r0 - 3630 00fa 80B9 cbnz r0, .L359 - 3631 .LVL573: - 3632 .L337: -1518:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(dj->fs, dj->sect); - 3633 .loc 1 1518 0 - 3634 00fc 2169 ldr r1, [r4, #16] - 3635 00fe 0029 cmp r1, #0 - 3636 0100 8CD1 bne .L350 - 3637 0102 1E46 mov r6, r3 -1551:../../../Source/third_party/fatfs/src/ff.c **** - 3638 .loc 1 1551 0 - 3639 0104 6BB1 cbz r3, .L360 - 3640 .L352: - 3641 .LVL574: -1551:../../../Source/third_party/fatfs/src/ff.c **** - 3642 .loc 1 1551 0 is_stmt 0 discriminator 1 - 3643 0106 0023 movs r3, #0 - 3644 0108 2361 str r3, [r4, #16] - 3645 010a 0AE0 b .L360 - 3646 .LVL575: - 3647 .L347: -1536:../../../Source/third_party/fatfs/src/ff.c **** } else { /* An SFN entry is found */ - 3648 .loc 1 1536 0 is_stmt 1 - 3649 010c 013B subs r3, r3, #1 - 3650 .LVL576: - 3651 010e DDB2 uxtb r5, r3 - 3652 .LVL577: - 3653 0110 F146 mov r9, lr - 3654 .LVL578: - 3655 0112 EDE7 b .L339 - 3656 .LVL579: - 3657 .L344: - 3658 0114 F146 mov r9, lr - 3659 .LVL580: - 3660 0116 3D46 mov r5, r7 - 3661 0118 EAE7 b .L339 - 3662 .LVL581: - 3663 .L353: -1523:../../../Source/third_party/fatfs/src/ff.c **** a = dir[DIR_Attr] & AM_MASK; - 3664 .loc 1 1523 0 - 3665 011a 0426 movs r6, #4 - 3666 011c F3E7 b .L352 - 3667 .LVL582: - 3668 .L359: -1547:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 3669 .loc 1 1547 0 - 3670 011e 0646 mov r6, r0 - 3671 0120 F1E7 b .L352 - 3672 .LVL583: - 3673 .L360: -1554:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */ - 3674 .loc 1 1554 0 - 3675 0122 3046 mov r0, r6 - 3676 0124 BDE8F88F pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc} - 3677 .LVL584: - 3678 .L367: - 3679 .align 2 - 3680 .L366: - 3681 0128 00000000 .word .LANCHOR2 - 3682 .cfi_endproc - 3683 .LFE23: - 3685 .section .text.dir_remove,"ax",%progbits - 3686 .align 2 - 3687 .thumb - 3688 .thumb_func - 3690 dir_remove: - 3691 .LFB25: -1645:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 3692 .loc 1 1645 0 - 3693 .cfi_startproc - 3694 @ args = 0, pretend = 0, frame = 0 - 3695 @ frame_needed = 0, uses_anonymous_args = 0 - 3696 .LVL585: - 3697 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} - 3698 .cfi_def_cfa_offset 24 - 3699 .cfi_offset 4, -24 - 3700 .cfi_offset 5, -20 - 3701 .cfi_offset 6, -16 - 3702 .cfi_offset 7, -12 - 3703 .cfi_offset 8, -8 - 3704 .cfi_offset 14, -4 - 3705 0004 0446 mov r4, r0 -1650:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of th - 3706 .loc 1 1650 0 - 3707 0006 C588 ldrh r5, [r0, #6] - 3708 .LVL586: -1651:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 3709 .loc 1 1651 0 - 3710 0008 018C ldrh r1, [r0, #32] - 3711 000a 4FF6FF73 movw r3, #65535 - 3712 000e 9942 cmp r1, r3 - 3713 0010 08BF it eq - 3714 0012 2946 moveq r1, r5 - 3715 0014 FFF7FEFF bl dir_sdi - 3716 .LVL587: -1652:../../../Source/third_party/fatfs/src/ff.c **** do { - 3717 .loc 1 1652 0 - 3718 0018 0346 mov r3, r0 - 3719 001a D0B9 cbnz r0, .L370 -1656:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->wflag = 1; - 3720 .loc 1 1656 0 - 3721 001c E527 movs r7, #229 -1657:../../../Source/third_party/fatfs/src/ff.c **** if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ - 3722 .loc 1 1657 0 - 3723 001e 0126 movs r6, #1 -1659:../../../Source/third_party/fatfs/src/ff.c **** } while (res == FR_OK); - 3724 .loc 1 1659 0 - 3725 0020 4FF00008 mov r8, #0 - 3726 .L373: -1654:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 3727 .loc 1 1654 0 - 3728 0024 2068 ldr r0, [r4] - 3729 .LVL588: - 3730 0026 2169 ldr r1, [r4, #16] - 3731 0028 FFF7FEFF bl move_window - 3732 .LVL589: -1655:../../../Source/third_party/fatfs/src/ff.c **** *dj->dir = DDE; /* Mark the entry "deleted" */ - 3733 .loc 1 1655 0 - 3734 002c 0346 mov r3, r0 - 3735 002e 68B9 cbnz r0, .L371 -1656:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->wflag = 1; - 3736 .loc 1 1656 0 - 3737 0030 6269 ldr r2, [r4, #20] - 3738 0032 1770 strb r7, [r2] -1657:../../../Source/third_party/fatfs/src/ff.c **** if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ - 3739 .loc 1 1657 0 - 3740 0034 2268 ldr r2, [r4] - 3741 0036 1671 strb r6, [r2, #4] -1658:../../../Source/third_party/fatfs/src/ff.c **** res = dir_next(dj, 0); /* Next entry */ - 3742 .loc 1 1658 0 - 3743 0038 E288 ldrh r2, [r4, #6] - 3744 003a AA42 cmp r2, r5 - 3745 003c 09D2 bcs .L370 -1659:../../../Source/third_party/fatfs/src/ff.c **** } while (res == FR_OK); - 3746 .loc 1 1659 0 - 3747 003e 2046 mov r0, r4 - 3748 .LVL590: - 3749 0040 4146 mov r1, r8 - 3750 0042 FFF7FEFF bl dir_next - 3751 .LVL591: -1660:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) res = FR_INT_ERR; - 3752 .loc 1 1660 0 - 3753 0046 0346 mov r3, r0 - 3754 0048 0028 cmp r0, #0 - 3755 004a EBD0 beq .L373 - 3756 .L371: - 3757 .LVL592: -1661:../../../Source/third_party/fatfs/src/ff.c **** } - 3758 .loc 1 1661 0 - 3759 004c 042B cmp r3, #4 - 3760 004e 08BF it eq - 3761 0050 0223 moveq r3, #2 - 3762 .LVL593: - 3763 .L370: -1676:../../../Source/third_party/fatfs/src/ff.c **** #endif /* !_FS_READONLY */ - 3764 .loc 1 1676 0 - 3765 0052 1846 mov r0, r3 - 3766 0054 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 3767 .cfi_endproc - 3768 .LFE25: - 3770 .section .text.remove_chain,"ax",%progbits - 3771 .align 2 - 3772 .thumb - 3773 .thumb_func - 3775 remove_chain: - 3776 .LFB10: - 952:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 3777 .loc 1 952 0 - 3778 .cfi_startproc - 3779 @ args = 0, pretend = 0, frame = 0 - 3780 @ frame_needed = 0, uses_anonymous_args = 0 - 3781 .LVL594: - 3782 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} - 3783 .cfi_def_cfa_offset 24 - 3784 .cfi_offset 4, -24 - 3785 .cfi_offset 5, -20 - 3786 .cfi_offset 6, -16 - 3787 .cfi_offset 7, -12 - 3788 .cfi_offset 8, -8 - 3789 .cfi_offset 14, -4 - 3790 0004 0D46 mov r5, r1 - 959:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INT_ERR; - 3791 .loc 1 959 0 - 3792 0006 0129 cmp r1, #1 - 3793 0008 27D9 bls .L381 - 3794 000a 0446 mov r4, r0 - 959:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INT_ERR; - 3795 .loc 1 959 0 is_stmt 0 discriminator 1 - 3796 000c 8369 ldr r3, [r0, #24] - 3797 000e 9942 cmp r1, r3 - 3798 0010 25D2 bcs .L382 - 969:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 3799 .loc 1 969 0 is_stmt 1 - 3800 0012 0027 movs r7, #0 - 973:../../../Source/third_party/fatfs/src/ff.c **** } - 3801 .loc 1 973 0 - 3802 0014 4FF00108 mov r8, #1 - 3803 0018 1AE0 b .L378 - 3804 .LVL595: - 3805 .L380: - 965:../../../Source/third_party/fatfs/src/ff.c **** if (nxt == 0) break; /* Empty cluster? */ - 3806 .loc 1 965 0 - 3807 001a 2046 mov r0, r4 - 3808 001c 2946 mov r1, r5 - 3809 001e FFF7FEFF bl get_fat - 3810 .LVL596: - 966:../../../Source/third_party/fatfs/src/ff.c **** if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */ - 3811 .loc 1 966 0 - 3812 0022 0646 mov r6, r0 - 3813 0024 E8B1 cbz r0, .L383 - 967:../../../Source/third_party/fatfs/src/ff.c **** if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ - 3814 .loc 1 967 0 - 3815 0026 0128 cmp r0, #1 - 3816 0028 1DD0 beq .L384 - 968:../../../Source/third_party/fatfs/src/ff.c **** res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ - 3817 .loc 1 968 0 - 3818 002a B0F1FF3F cmp r0, #-1 - 3819 002e 1CD0 beq .L385 - 969:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 3820 .loc 1 969 0 - 3821 0030 2046 mov r0, r4 - 3822 .LVL597: - 3823 0032 2946 mov r1, r5 - 3824 0034 3A46 mov r2, r7 - 3825 0036 FFF7FEFF bl put_fat - 3826 .LVL598: - 970:../../../Source/third_party/fatfs/src/ff.c **** if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */ - 3827 .loc 1 970 0 - 3828 003a 0346 mov r3, r0 - 3829 003c B0B9 cbnz r0, .L377 - 971:../../../Source/third_party/fatfs/src/ff.c **** fs->free_clust++; - 3830 .loc 1 971 0 - 3831 003e 2369 ldr r3, [r4, #16] - 3832 0040 B3F1FF3F cmp r3, #-1 - 3833 0044 03D0 beq .L379 - 972:../../../Source/third_party/fatfs/src/ff.c **** fs->fsi_flag = 1; - 3834 .loc 1 972 0 - 3835 0046 0133 adds r3, r3, #1 - 3836 0048 2361 str r3, [r4, #16] - 973:../../../Source/third_party/fatfs/src/ff.c **** } - 3837 .loc 1 973 0 - 3838 004a 84F80580 strb r8, [r4, #5] - 3839 .L379: - 952:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 3840 .loc 1 952 0 - 3841 004e 3546 mov r5, r6 - 3842 .LVL599: - 3843 .L378: - 964:../../../Source/third_party/fatfs/src/ff.c **** nxt = get_fat(fs, clst); /* Get cluster status */ - 3844 .loc 1 964 0 - 3845 0050 A369 ldr r3, [r4, #24] - 3846 0052 9D42 cmp r5, r3 - 3847 0054 E1D3 bcc .L380 - 3848 0056 0023 movs r3, #0 - 3849 0058 08E0 b .L377 - 3850 .LVL600: - 3851 .L381: - 960:../../../Source/third_party/fatfs/src/ff.c **** - 3852 .loc 1 960 0 - 3853 005a 0223 movs r3, #2 - 3854 005c 06E0 b .L377 - 3855 .L382: - 3856 005e 0223 movs r3, #2 - 3857 0060 04E0 b .L377 - 3858 .LVL601: - 3859 .L383: - 3860 0062 0023 movs r3, #0 - 3861 0064 02E0 b .L377 - 3862 .L384: - 967:../../../Source/third_party/fatfs/src/ff.c **** if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ - 3863 .loc 1 967 0 - 3864 0066 0223 movs r3, #2 - 3865 0068 00E0 b .L377 - 3866 .L385: - 968:../../../Source/third_party/fatfs/src/ff.c **** res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ - 3867 .loc 1 968 0 - 3868 006a 0123 movs r3, #1 - 3869 .LVL602: - 3870 .L377: - 990:../../../Source/third_party/fatfs/src/ff.c **** #endif - 3871 .loc 1 990 0 - 3872 006c 1846 mov r0, r3 - 3873 006e BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 3874 .cfi_endproc - 3875 .LFE10: - 3877 0072 00BF .section .text.gen_numname,"ax",%progbits - 3878 .align 2 - 3879 .global gen_numname - 3880 .thumb - 3881 .thumb_func - 3883 gen_numname: - 3884 .LFB20: -1383:../../../Source/third_party/fatfs/src/ff.c **** BYTE ns[8], c; - 3885 .loc 1 1383 0 - 3886 .cfi_startproc - 3887 @ args = 0, pretend = 0, frame = 8 - 3888 @ frame_needed = 0, uses_anonymous_args = 0 - 3889 .LVL603: - 3890 0000 70B5 push {r4, r5, r6, lr} - 3891 .cfi_def_cfa_offset 16 - 3892 .cfi_offset 4, -16 - 3893 .cfi_offset 5, -12 - 3894 .cfi_offset 6, -8 - 3895 .cfi_offset 14, -4 - 3896 0002 82B0 sub sp, sp, #8 - 3897 .cfi_def_cfa_offset 24 - 3898 0004 0546 mov r5, r0 - 3899 0006 1646 mov r6, r2 - 3900 0008 1C46 mov r4, r3 -1388:../../../Source/third_party/fatfs/src/ff.c **** - 3901 .loc 1 1388 0 - 3902 000a 0B22 movs r2, #11 - 3903 .LVL604: - 3904 000c FFF7FEFF bl mem_cpy - 3905 .LVL605: -1390:../../../Source/third_party/fatfs/src/ff.c **** do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn); - 3906 .loc 1 1390 0 - 3907 0010 052C cmp r4, #5 - 3908 0012 09D9 bls .L388 - 3909 .LVL606: - 3910 .L400: -1391:../../../Source/third_party/fatfs/src/ff.c **** } - 3911 .loc 1 1391 0 discriminator 1 - 3912 0014 E303 lsls r3, r4, #15 - 3913 0016 43EA5404 orr r4, r3, r4, lsr #1 - 3914 .LVL607: - 3915 001a 36F8023B ldrh r3, [r6], #2 - 3916 .LVL608: - 3917 001e 1C44 add r4, r4, r3 - 3918 0020 A4B2 uxth r4, r4 - 3919 .LVL609: - 3920 0022 3388 ldrh r3, [r6] - 3921 0024 002B cmp r3, #0 - 3922 0026 F5D1 bne .L400 - 3923 .LVL610: - 3924 .L388: - 3925 0028 02A8 add r0, sp, #8 -1383:../../../Source/third_party/fatfs/src/ff.c **** BYTE ns[8], c; - 3926 .loc 1 1383 0 - 3927 002a 0722 movs r2, #7 - 3928 .L391: - 3929 .LVL611: -1397:../../../Source/third_party/fatfs/src/ff.c **** if (c > '9') c += 7; - 3930 .loc 1 1397 0 - 3931 002c 04F00F01 and r1, r4, #15 - 3932 0030 01F13003 add r3, r1, #48 - 3933 .LVL612: -1398:../../../Source/third_party/fatfs/src/ff.c **** ns[i--] = c; - 3934 .loc 1 1398 0 - 3935 0034 392B cmp r3, #57 - 3936 0036 88BF it hi - 3937 0038 01F13703 addhi r3, r1, #55 - 3938 .LVL613: -1399:../../../Source/third_party/fatfs/src/ff.c **** seq /= 16; - 3939 .loc 1 1399 0 - 3940 003c 013A subs r2, r2, #1 - 3941 .LVL614: - 3942 003e 00F8013D strb r3, [r0, #-1]! - 3943 .LVL615: -1401:../../../Source/third_party/fatfs/src/ff.c **** ns[i] = '~'; - 3944 .loc 1 1401 0 - 3945 0042 2409 lsrs r4, r4, #4 - 3946 .LVL616: - 3947 0044 F2D1 bne .L391 -1399:../../../Source/third_party/fatfs/src/ff.c **** seq /= 16; - 3948 .loc 1 1399 0 - 3949 0046 1446 mov r4, r2 -1402:../../../Source/third_party/fatfs/src/ff.c **** - 3950 .loc 1 1402 0 - 3951 0048 7E21 movs r1, #126 - 3952 004a 02AB add r3, sp, #8 - 3953 .LVL617: - 3954 004c 1344 add r3, r3, r2 - 3955 004e 03F8081C strb r1, [r3, #-8] - 3956 .LVL618: -1405:../../../Source/third_party/fatfs/src/ff.c **** if (IsDBCS1(dst[j])) { - 3957 .loc 1 1405 0 - 3958 0052 62B1 cbz r2, .L396 - 3959 0054 2B78 ldrb r3, [r5] @ zero_extendqisi2 - 3960 0056 202B cmp r3, #32 - 3961 0058 0BD0 beq .L397 - 3962 005a 2946 mov r1, r5 - 3963 005c 0023 movs r3, #0 - 3964 .LVL619: - 3965 .L393: -1405:../../../Source/third_party/fatfs/src/ff.c **** if (IsDBCS1(dst[j])) { - 3966 .loc 1 1405 0 is_stmt 0 discriminator 2 - 3967 005e 0133 adds r3, r3, #1 - 3968 .LVL620: - 3969 0060 A342 cmp r3, r4 - 3970 0062 08D0 beq .L398 -1405:../../../Source/third_party/fatfs/src/ff.c **** if (IsDBCS1(dst[j])) { - 3971 .loc 1 1405 0 discriminator 3 - 3972 0064 11F8010F ldrb r0, [r1, #1]! @ zero_extendqisi2 - 3973 0068 2028 cmp r0, #32 - 3974 006a F8D1 bne .L393 - 3975 006c 04E0 b .L392 - 3976 .LVL621: - 3977 .L396: -1405:../../../Source/third_party/fatfs/src/ff.c **** if (IsDBCS1(dst[j])) { - 3978 .loc 1 1405 0 - 3979 006e 1346 mov r3, r2 - 3980 0070 02E0 b .L392 - 3981 .L397: - 3982 0072 0023 movs r3, #0 - 3983 0074 00E0 b .L392 - 3984 .LVL622: - 3985 .L398: - 3986 0076 1346 mov r3, r2 - 3987 .LVL623: - 3988 .L392: - 3989 0078 E818 adds r0, r5, r3 -1412:../../../Source/third_party/fatfs/src/ff.c **** } while (j < 8); - 3990 .loc 1 1412 0 is_stmt 1 - 3991 007a 2024 movs r4, #32 - 3992 .L395: - 3993 .LVL624: - 3994 007c 0133 adds r3, r3, #1 - 3995 .LVL625: - 3996 007e 072A cmp r2, #7 - 3997 0080 05D8 bhi .L399 - 3998 .LVL626: -1412:../../../Source/third_party/fatfs/src/ff.c **** } while (j < 8); - 3999 .loc 1 1412 0 is_stmt 0 discriminator 1 - 4000 0082 02A9 add r1, sp, #8 - 4001 0084 1144 add r1, r1, r2 - 4002 0086 11F8081C ldrb r1, [r1, #-8] @ zero_extendqisi2 - 4003 008a 0132 adds r2, r2, #1 - 4004 .LVL627: - 4005 008c 00E0 b .L394 - 4006 .L399: -1412:../../../Source/third_party/fatfs/src/ff.c **** } while (j < 8); - 4007 .loc 1 1412 0 - 4008 008e 2146 mov r1, r4 - 4009 .L394: -1412:../../../Source/third_party/fatfs/src/ff.c **** } while (j < 8); - 4010 .loc 1 1412 0 discriminator 4 - 4011 0090 00F8011B strb r1, [r0], #1 -1413:../../../Source/third_party/fatfs/src/ff.c **** } - 4012 .loc 1 1413 0 is_stmt 1 discriminator 4 - 4013 0094 072B cmp r3, #7 - 4014 0096 F1D9 bls .L395 -1414:../../../Source/third_party/fatfs/src/ff.c **** #endif - 4015 .loc 1 1414 0 - 4016 0098 02B0 add sp, sp, #8 - 4017 .cfi_def_cfa_offset 16 - 4018 @ sp needed - 4019 009a 70BD pop {r4, r5, r6, pc} - 4020 .cfi_endproc - 4021 .LFE20: - 4023 .section .text.dir_register,"ax",%progbits - 4024 .align 2 - 4025 .thumb - 4026 .thumb_func - 4028 dir_register: - 4029 .LFB24: -1567:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 4030 .loc 1 1567 0 - 4031 .cfi_startproc - 4032 @ args = 0, pretend = 0, frame = 24 - 4033 @ frame_needed = 0, uses_anonymous_args = 0 - 4034 .LVL628: - 4035 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} - 4036 .cfi_def_cfa_offset 36 - 4037 .cfi_offset 4, -36 - 4038 .cfi_offset 5, -32 - 4039 .cfi_offset 6, -28 - 4040 .cfi_offset 7, -24 - 4041 .cfi_offset 8, -20 - 4042 .cfi_offset 9, -16 - 4043 .cfi_offset 10, -12 - 4044 .cfi_offset 11, -8 - 4045 .cfi_offset 14, -4 - 4046 0004 87B0 sub sp, sp, #28 - 4047 .cfi_def_cfa_offset 64 - 4048 0006 0446 mov r4, r0 -1575:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(sn, fn, 12); - 4049 .loc 1 1575 0 - 4050 0008 8769 ldr r7, [r0, #24] - 4051 .LVL629: - 4052 000a C669 ldr r6, [r0, #28] - 4053 .LVL630: -1576:../../../Source/third_party/fatfs/src/ff.c **** - 4054 .loc 1 1576 0 - 4055 000c 03A8 add r0, sp, #12 - 4056 .LVL631: - 4057 000e 3946 mov r1, r7 - 4058 0010 0C22 movs r2, #12 - 4059 0012 FFF7FEFF bl mem_cpy - 4060 .LVL632: -1581:../../../Source/third_party/fatfs/src/ff.c **** fn[NS] = 0; dj->lfn = 0; /* Find only SFN */ - 4061 .loc 1 1581 0 - 4062 0016 9DF81730 ldrb r3, [sp, #23] @ zero_extendqisi2 - 4063 001a 13F0010F tst r3, #1 - 4064 001e 1DD0 beq .L408 -1582:../../../Source/third_party/fatfs/src/ff.c **** for (n = 1; n < 100; n++) { - 4065 .loc 1 1582 0 - 4066 0020 0023 movs r3, #0 - 4067 0022 FB72 strb r3, [r7, #11] - 4068 0024 E361 str r3, [r4, #28] - 4069 .LVL633: -1583:../../../Source/third_party/fatfs/src/ff.c **** gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ - 4070 .loc 1 1583 0 - 4071 0026 0125 movs r5, #1 - 4072 .LVL634: - 4073 .L410: -1584:../../../Source/third_party/fatfs/src/ff.c **** res = dir_find(dj); /* Check if the name collides with existing SFN */ - 4074 .loc 1 1584 0 - 4075 0028 3846 mov r0, r7 - 4076 002a 03A9 add r1, sp, #12 - 4077 002c 3246 mov r2, r6 - 4078 002e 2B46 mov r3, r5 - 4079 0030 FFF7FEFF bl gen_numname - 4080 .LVL635: -1585:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 4081 .loc 1 1585 0 - 4082 0034 2046 mov r0, r4 - 4083 0036 FFF7FEFF bl dir_find - 4084 .LVL636: -1586:../../../Source/third_party/fatfs/src/ff.c **** } - 4085 .loc 1 1586 0 - 4086 003a 28B9 cbnz r0, .L409 -1583:../../../Source/third_party/fatfs/src/ff.c **** gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ - 4087 .loc 1 1583 0 discriminator 2 - 4088 003c 0135 adds r5, r5, #1 - 4089 .LVL637: - 4090 003e ADB2 uxth r5, r5 - 4091 .LVL638: - 4092 0040 642D cmp r5, #100 - 4093 0042 F1D1 bne .L410 -1588:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ - 4094 .loc 1 1588 0 - 4095 0044 0720 movs r0, #7 - 4096 0046 D9E0 b .L443 - 4097 .LVL639: - 4098 .L409: - 4099 0048 642D cmp r5, #100 - 4100 004a 00F0BE80 beq .L431 -1589:../../../Source/third_party/fatfs/src/ff.c **** fn[NS] = sn[NS]; dj->lfn = lfn; - 4101 .loc 1 1589 0 - 4102 004e 0428 cmp r0, #4 - 4103 0050 40F0BD80 bne .L432 -1590:../../../Source/third_party/fatfs/src/ff.c **** } - 4104 .loc 1 1590 0 - 4105 0054 9DF81730 ldrb r3, [sp, #23] @ zero_extendqisi2 - 4106 0058 FB72 strb r3, [r7, #11] - 4107 005a E661 str r6, [r4, #28] - 4108 .LVL640: - 4109 .L408: -1593:../../../Source/third_party/fatfs/src/ff.c **** for (n = 0; lfn[n]; n++) ; - 4110 .loc 1 1593 0 - 4111 005c 9DF81730 ldrb r3, [sp, #23] @ zero_extendqisi2 - 4112 0060 13F0020F tst r3, #2 - 4113 0064 13D0 beq .L433 - 4114 .LVL641: -1594:../../../Source/third_party/fatfs/src/ff.c **** ne = (n + 25) / 13; - 4115 .loc 1 1594 0 discriminator 1 - 4116 0066 3388 ldrh r3, [r6] - 4117 0068 3BB1 cbz r3, .L434 -1594:../../../Source/third_party/fatfs/src/ff.c **** ne = (n + 25) / 13; - 4118 .loc 1 1594 0 is_stmt 0 - 4119 006a 0023 movs r3, #0 - 4120 .LVL642: - 4121 .L414: -1594:../../../Source/third_party/fatfs/src/ff.c **** ne = (n + 25) / 13; - 4122 .loc 1 1594 0 discriminator 3 - 4123 006c 0133 adds r3, r3, #1 - 4124 .LVL643: - 4125 006e 9BB2 uxth r3, r3 - 4126 .LVL644: - 4127 0070 36F81320 ldrh r2, [r6, r3, lsl #1] - 4128 0074 002A cmp r2, #0 - 4129 0076 F9D1 bne .L414 - 4130 0078 00E0 b .L413 - 4131 .LVL645: - 4132 .L434: -1594:../../../Source/third_party/fatfs/src/ff.c **** ne = (n + 25) / 13; - 4133 .loc 1 1594 0 - 4134 007a 0023 movs r3, #0 - 4135 .LVL646: - 4136 .L413: -1595:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Otherwise allocate an entry for an SFN */ - 4137 .loc 1 1595 0 is_stmt 1 - 4138 007c 1933 adds r3, r3, #25 - 4139 007e 614D ldr r5, .L448 - 4140 0080 85FB0325 smull r2, r5, r5, r3 - 4141 0084 DB17 asrs r3, r3, #31 - 4142 0086 C3EBA505 rsb r5, r3, r5, asr #2 - 4143 008a ADB2 uxth r5, r5 - 4144 .LVL647: - 4145 008c 00E0 b .L412 - 4146 .LVL648: - 4147 .L433: -1597:../../../Source/third_party/fatfs/src/ff.c **** } - 4148 .loc 1 1597 0 - 4149 008e 0125 movs r5, #1 - 4150 .L412: - 4151 .LVL649: - 4152 .LBB52: - 4153 .LBB53: -1214:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 4154 .loc 1 1214 0 - 4155 0090 2046 mov r0, r4 - 4156 0092 0021 movs r1, #0 - 4157 0094 FFF7FEFF bl dir_sdi - 4158 .LVL650: -1215:../../../Source/third_party/fatfs/src/ff.c **** n = 0; - 4159 .loc 1 1215 0 - 4160 0098 0346 mov r3, r0 - 4161 009a 0028 cmp r0, #0 - 4162 009c 40F0AD80 bne .L415 - 4163 00a0 0026 movs r6, #0 - 4164 .LVL651: -1223:../../../Source/third_party/fatfs/src/ff.c **** } - 4165 .loc 1 1223 0 - 4166 00a2 B046 mov r8, r6 -1225:../../../Source/third_party/fatfs/src/ff.c **** } while (res == FR_OK); - 4167 .loc 1 1225 0 - 4168 00a4 0127 movs r7, #1 - 4169 .LVL652: - 4170 .L419: -1218:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 4171 .loc 1 1218 0 - 4172 00a6 2068 ldr r0, [r4] - 4173 .LVL653: - 4174 00a8 2169 ldr r1, [r4, #16] - 4175 00aa FFF7FEFF bl move_window - 4176 .LVL654: -1219:../../../Source/third_party/fatfs/src/ff.c **** if (dj->dir[0] == DDE || dj->dir[0] == 0) { /* Is it a blank entry? */ - 4177 .loc 1 1219 0 - 4178 00ae 0346 mov r3, r0 - 4179 00b0 0028 cmp r0, #0 - 4180 00b2 40F0A280 bne .L415 -1220:../../../Source/third_party/fatfs/src/ff.c **** if (++n == nent) break; /* A block of contiguous entry is found */ - 4181 .loc 1 1220 0 - 4182 00b6 6369 ldr r3, [r4, #20] - 4183 00b8 1B78 ldrb r3, [r3] @ zero_extendqisi2 - 4184 00ba E52B cmp r3, #229 - 4185 00bc 00D0 beq .L416 - 4186 00be 1BB9 cbnz r3, .L435 - 4187 .L416: -1221:../../../Source/third_party/fatfs/src/ff.c **** } else { - 4188 .loc 1 1221 0 - 4189 00c0 0136 adds r6, r6, #1 - 4190 .LVL655: - 4191 00c2 B542 cmp r5, r6 - 4192 00c4 01D1 bne .L417 - 4193 00c6 83E0 b .L418 - 4194 .L435: -1223:../../../Source/third_party/fatfs/src/ff.c **** } - 4195 .loc 1 1223 0 - 4196 00c8 4646 mov r6, r8 - 4197 .LVL656: - 4198 .L417: -1225:../../../Source/third_party/fatfs/src/ff.c **** } while (res == FR_OK); - 4199 .loc 1 1225 0 - 4200 00ca 2046 mov r0, r4 - 4201 .LVL657: - 4202 00cc 3946 mov r1, r7 - 4203 00ce FFF7FEFF bl dir_next - 4204 .LVL658: -1226:../../../Source/third_party/fatfs/src/ff.c **** } - 4205 .loc 1 1226 0 - 4206 00d2 0346 mov r3, r0 - 4207 00d4 0028 cmp r0, #0 - 4208 00d6 E6D0 beq .L419 - 4209 00d8 8FE0 b .L415 - 4210 .LVL659: - 4211 .L429: - 4212 .LBE53: - 4213 .LBE52: -1602:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 4214 .loc 1 1602 0 - 4215 00da E188 ldrh r1, [r4, #6] - 4216 00dc 491B subs r1, r1, r5 - 4217 00de 2046 mov r0, r4 - 4218 00e0 89B2 uxth r1, r1 - 4219 00e2 FFF7FEFF bl dir_sdi - 4220 .LVL660: -1603:../../../Source/third_party/fatfs/src/ff.c **** sum = sum_sfn(dj->fn); /* Sum value of the SFN tied to the LFN */ - 4221 .loc 1 1603 0 - 4222 00e6 0346 mov r3, r0 - 4223 00e8 0028 cmp r0, #0 - 4224 00ea 40F08480 bne .L420 -1604:../../../Source/third_party/fatfs/src/ff.c **** do { /* Store LFN entries in bottom first */ - 4225 .loc 1 1604 0 - 4226 00ee A069 ldr r0, [r4, #24] - 4227 .LVL661: - 4228 00f0 FFF7FEFF bl sum_sfn - 4229 .LVL662: - 4230 00f4 0190 str r0, [sp, #4] - 4231 .LVL663: - 4232 .LBB54: - 4233 .LBB55: -1353:../../../Source/third_party/fatfs/src/ff.c **** dir[LDIR_Type] = 0; - 4234 .loc 1 1353 0 - 4235 00f6 0F27 movs r7, #15 - 4236 00f8 434B ldr r3, .L448+4 - 4237 00fa 03F10D06 add r6, r3, #13 - 4238 .LVL664: - 4239 .L426: - 4240 .LBE55: - 4241 .LBE54: -1606:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 4242 .loc 1 1606 0 - 4243 00fe 2068 ldr r0, [r4] - 4244 0100 2169 ldr r1, [r4, #16] - 4245 0102 FFF7FEFF bl move_window - 4246 .LVL665: -1607:../../../Source/third_party/fatfs/src/ff.c **** fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum); - 4247 .loc 1 1607 0 - 4248 0106 0346 mov r3, r0 - 4249 0108 0028 cmp r0, #0 - 4250 010a 74D1 bne .L420 -1608:../../../Source/third_party/fatfs/src/ff.c **** dj->fs->wflag = 1; - 4251 .loc 1 1608 0 - 4252 010c D4F81C90 ldr r9, [r4, #28] - 4253 0110 6069 ldr r0, [r4, #20] - 4254 .LVL666: - 4255 0112 5FFA85FB uxtb fp, r5 - 4256 .LVL667: - 4257 .LBB58: - 4258 .LBB56: -1352:../../../Source/third_party/fatfs/src/ff.c **** dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ - 4259 .loc 1 1352 0 - 4260 0116 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 - 4261 011a 4373 strb r3, [r0, #13] -1353:../../../Source/third_party/fatfs/src/ff.c **** dir[LDIR_Type] = 0; - 4262 .loc 1 1353 0 - 4263 011c C772 strb r7, [r0, #11] -1354:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+LDIR_FstClusLO, 0); - 4264 .loc 1 1354 0 - 4265 011e 0023 movs r3, #0 - 4266 0120 0373 strb r3, [r0, #12] -1355:../../../Source/third_party/fatfs/src/ff.c **** - 4267 .loc 1 1355 0 - 4268 0122 8376 strb r3, [r0, #26] - 4269 0124 C376 strb r3, [r0, #27] -1357:../../../Source/third_party/fatfs/src/ff.c **** s = wc = 0; - 4270 .loc 1 1357 0 - 4271 0126 0BF1FF32 add r2, fp, #-1 - 4272 012a 02EB4201 add r1, r2, r2, lsl #1 - 4273 012e 02EB8101 add r1, r2, r1, lsl #2 - 4274 .LVL668: - 4275 0132 354A ldr r2, .L448+4 -1360:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+LfnOfs[s], wc); /* Put it */ - 4276 .loc 1 1360 0 - 4277 0134 4FF6FF7E movw lr, #65535 -1361:../../../Source/third_party/fatfs/src/ff.c **** if (!wc) wc = 0xFFFF; /* Padding chars following last char */ - 4278 .loc 1 1361 0 - 4279 0138 4FF0FF0A mov r10, #255 - 4280 .LVL669: - 4281 .L423: -1360:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+LfnOfs[s], wc); /* Put it */ - 4282 .loc 1 1360 0 - 4283 013c 7345 cmp r3, lr - 4284 013e 4BD0 beq .L421 - 4285 0140 01F1010C add ip, r1, #1 - 4286 .LVL670: - 4287 0144 39F81130 ldrh r3, [r9, r1, lsl #1] - 4288 .LVL671: -1361:../../../Source/third_party/fatfs/src/ff.c **** if (!wc) wc = 0xFFFF; /* Padding chars following last char */ - 4289 .loc 1 1361 0 - 4290 0148 1178 ldrb r1, [r2] @ zero_extendqisi2 - 4291 014a 4354 strb r3, [r0, r1] - 4292 014c 0144 add r1, r1, r0 - 4293 014e 4FEA1328 lsr r8, r3, #8 - 4294 0152 81F80180 strb r8, [r1, #1] -1362:../../../Source/third_party/fatfs/src/ff.c **** } while (++s < 13); - 4295 .loc 1 1362 0 - 4296 0156 13B9 cbnz r3, .L436 -1360:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+LfnOfs[s], wc); /* Put it */ - 4297 .loc 1 1360 0 - 4298 0158 6146 mov r1, ip - 4299 .LVL672: -1362:../../../Source/third_party/fatfs/src/ff.c **** } while (++s < 13); - 4300 .loc 1 1362 0 - 4301 015a 7346 mov r3, lr - 4302 015c 00E0 b .L422 - 4303 .LVL673: - 4304 .L436: -1360:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+LfnOfs[s], wc); /* Put it */ - 4305 .loc 1 1360 0 - 4306 015e 6146 mov r1, ip - 4307 .LVL674: - 4308 .L422: - 4309 0160 0132 adds r2, r2, #1 - 4310 .LVL675: -1363:../../../Source/third_party/fatfs/src/ff.c **** if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLE; /* Bottom LFN part is the start of LFN sequence */ - 4311 .loc 1 1363 0 - 4312 0162 B242 cmp r2, r6 - 4313 0164 EAD1 bne .L423 -1364:../../../Source/third_party/fatfs/src/ff.c **** dir[LDIR_Ord] = ord; /* Set the LFN order */ - 4314 .loc 1 1364 0 - 4315 0166 4FF6FF72 movw r2, #65535 - 4316 .LVL676: - 4317 016a 9342 cmp r3, r2 - 4318 016c 02D0 beq .L424 - 4319 016e 39F81130 ldrh r3, [r9, r1, lsl #1] - 4320 0172 0BB9 cbnz r3, .L425 - 4321 .L424: - 4322 0174 4BF0400B orr fp, fp, #64 - 4323 .LVL677: - 4324 .L425: -1365:../../../Source/third_party/fatfs/src/ff.c **** } - 4325 .loc 1 1365 0 - 4326 0178 80F800B0 strb fp, [r0] - 4327 .LBE56: - 4328 .LBE58: -1609:../../../Source/third_party/fatfs/src/ff.c **** res = dir_next(dj, 0); /* Next entry */ - 4329 .loc 1 1609 0 - 4330 017c 2368 ldr r3, [r4] - 4331 017e 0122 movs r2, #1 - 4332 0180 1A71 strb r2, [r3, #4] -1610:../../../Source/third_party/fatfs/src/ff.c **** } while (res == FR_OK && --ne); - 4333 .loc 1 1610 0 - 4334 0182 2046 mov r0, r4 - 4335 .LVL678: - 4336 0184 0021 movs r1, #0 - 4337 .LVL679: - 4338 0186 FFF7FEFF bl dir_next - 4339 .LVL680: -1611:../../../Source/third_party/fatfs/src/ff.c **** } - 4340 .loc 1 1611 0 - 4341 018a 0346 mov r3, r0 - 4342 018c 0028 cmp r0, #0 - 4343 018e 32D1 bne .L420 -1611:../../../Source/third_party/fatfs/src/ff.c **** } - 4344 .loc 1 1611 0 is_stmt 0 discriminator 1 - 4345 0190 013D subs r5, r5, #1 - 4346 .LVL681: - 4347 0192 ADB2 uxth r5, r5 - 4348 .LVL682: - 4349 0194 002D cmp r5, #0 - 4350 0196 B2D1 bne .L426 - 4351 0198 26E0 b .L427 - 4352 .LVL683: - 4353 .L430: -1621:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(dj->dir, dj->fn, 11); /* Put SFN */ - 4354 .loc 1 1621 0 is_stmt 1 - 4355 019a 6369 ldr r3, [r4, #20] - 4356 .LVL684: - 4357 019c 03F12001 add r1, r3, #32 - 4358 .LBB59: - 4359 .LBB60: - 560:../../../Source/third_party/fatfs/src/ff.c **** } - 4360 .loc 1 560 0 - 4361 01a0 0022 movs r2, #0 - 4362 .LVL685: - 4363 .L428: - 4364 01a2 03F8012B strb r2, [r3], #1 - 4365 .LVL686: - 559:../../../Source/third_party/fatfs/src/ff.c **** *d++ = (BYTE)val; - 4366 .loc 1 559 0 - 4367 01a6 8B42 cmp r3, r1 - 4368 01a8 FBD1 bne .L428 - 4369 .LBE60: - 4370 .LBE59: -1622:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN - 4371 .loc 1 1622 0 - 4372 01aa 6069 ldr r0, [r4, #20] - 4373 .LVL687: - 4374 01ac A169 ldr r1, [r4, #24] - 4375 .LVL688: - 4376 01ae 0B22 movs r2, #11 - 4377 01b0 FFF7FEFF bl mem_cpy - 4378 .LVL689: -1624:../../../Source/third_party/fatfs/src/ff.c **** #endif - 4379 .loc 1 1624 0 - 4380 01b4 6269 ldr r2, [r4, #20] - 4381 01b6 A369 ldr r3, [r4, #24] - 4382 01b8 DB7A ldrb r3, [r3, #11] @ zero_extendqisi2 - 4383 01ba 03F01803 and r3, r3, #24 - 4384 01be 1373 strb r3, [r2, #12] -1626:../../../Source/third_party/fatfs/src/ff.c **** } - 4385 .loc 1 1626 0 - 4386 01c0 2368 ldr r3, [r4] - 4387 01c2 0122 movs r2, #1 - 4388 01c4 1A71 strb r2, [r3, #4] -1619:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 4389 .loc 1 1619 0 - 4390 01c6 0020 movs r0, #0 - 4391 01c8 18E0 b .L443 - 4392 .LVL690: - 4393 .L431: -1588:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ - 4394 .loc 1 1588 0 - 4395 01ca 0720 movs r0, #7 - 4396 .LVL691: - 4397 01cc 16E0 b .L443 - 4398 .LVL692: - 4399 .L432: - 4400 01ce 15E0 b .L443 - 4401 .LVL693: - 4402 .L418: -1601:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(dj, (WORD)(dj->index - ne)); - 4403 .loc 1 1601 0 - 4404 01d0 013D subs r5, r5, #1 - 4405 .LVL694: - 4406 01d2 ADB2 uxth r5, r5 - 4407 .LVL695: - 4408 01d4 45B1 cbz r5, .L427 - 4409 01d6 80E7 b .L429 - 4410 .LVL696: - 4411 .L421: - 4412 .LBB61: - 4413 .LBB57: -1361:../../../Source/third_party/fatfs/src/ff.c **** if (!wc) wc = 0xFFFF; /* Padding chars following last char */ - 4414 .loc 1 1361 0 - 4415 01d8 92F800C0 ldrb ip, [r2] @ zero_extendqisi2 - 4416 01dc 00F80CA0 strb r10, [r0, ip] - 4417 01e0 8444 add ip, ip, r0 - 4418 01e2 8CF801A0 strb r10, [ip, #1] - 4419 01e6 BBE7 b .L422 - 4420 .LVL697: - 4421 .L427: - 4422 .LBE57: - 4423 .LBE61: -1619:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 4424 .loc 1 1619 0 - 4425 01e8 2068 ldr r0, [r4] - 4426 01ea 2169 ldr r1, [r4, #16] - 4427 01ec FFF7FEFF bl move_window - 4428 .LVL698: -1620:../../../Source/third_party/fatfs/src/ff.c **** mem_set(dj->dir, 0, SZ_DIR); /* Clean the entry */ - 4429 .loc 1 1620 0 - 4430 01f0 0028 cmp r0, #0 - 4431 01f2 D2D0 beq .L430 - 4432 01f4 02E0 b .L443 - 4433 .L420: - 4434 .LVL699: -1619:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 4435 .loc 1 1619 0 - 4436 01f6 1846 mov r0, r3 - 4437 01f8 00E0 b .L443 - 4438 .LVL700: - 4439 .L415: -1585:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 4440 .loc 1 1585 0 - 4441 01fa 1846 mov r0, r3 - 4442 .LVL701: - 4443 .L443: -1631:../../../Source/third_party/fatfs/src/ff.c **** #endif /* !_FS_READONLY */ - 4444 .loc 1 1631 0 - 4445 01fc 07B0 add sp, sp, #28 - 4446 .cfi_def_cfa_offset 36 - 4447 @ sp needed - 4448 01fe BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} - 4449 .LVL702: - 4450 .L449: - 4451 0202 00BF .align 2 - 4452 .L448: - 4453 0204 4FECC44E .word 1321528399 - 4454 0208 00000000 .word .LANCHOR2 - 4455 .cfi_endproc - 4456 .LFE24: - 4458 .section .text.f_mount,"ax",%progbits - 4459 .align 2 - 4460 .global f_mount - 4461 .thumb - 4462 .thumb_func - 4464 f_mount: - 4465 .LFB32: -2252:../../../Source/third_party/fatfs/src/ff.c **** -2253:../../../Source/third_party/fatfs/src/ff.c **** -2254:../../../Source/third_party/fatfs/src/ff.c **** -2255:../../../Source/third_party/fatfs/src/ff.c **** -2256:../../../Source/third_party/fatfs/src/ff.c **** /*-------------------------------------------------------------------------- -2257:../../../Source/third_party/fatfs/src/ff.c **** -2258:../../../Source/third_party/fatfs/src/ff.c **** Public Functions -2259:../../../Source/third_party/fatfs/src/ff.c **** -2260:../../../Source/third_party/fatfs/src/ff.c **** --------------------------------------------------------------------------*/ -2261:../../../Source/third_party/fatfs/src/ff.c **** -2262:../../../Source/third_party/fatfs/src/ff.c **** -2263:../../../Source/third_party/fatfs/src/ff.c **** -2264:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2265:../../../Source/third_party/fatfs/src/ff.c **** /* Mount/Unmount a Logical Drive */ -2266:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2267:../../../Source/third_party/fatfs/src/ff.c **** -2268:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_mount ( -2269:../../../Source/third_party/fatfs/src/ff.c **** BYTE vol, /* Logical drive number to be mounted/unmounted */ -2270:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs /* Pointer to new file system object (NULL for unmount)*/ -2271:../../../Source/third_party/fatfs/src/ff.c **** ) -2272:../../../Source/third_party/fatfs/src/ff.c **** { - 4466 .loc 1 2272 0 - 4467 .cfi_startproc - 4468 @ args = 0, pretend = 0, frame = 0 - 4469 @ frame_needed = 0, uses_anonymous_args = 0 - 4470 @ link register save eliminated. - 4471 .LVL703: -2273:../../../Source/third_party/fatfs/src/ff.c **** FATFS *rfs; -2274:../../../Source/third_party/fatfs/src/ff.c **** -2275:../../../Source/third_party/fatfs/src/ff.c **** -2276:../../../Source/third_party/fatfs/src/ff.c **** if (vol >= _VOLUMES) /* Check if the drive number is valid */ - 4472 .loc 1 2276 0 - 4473 0000 58B9 cbnz r0, .L454 -2277:../../../Source/third_party/fatfs/src/ff.c **** return FR_INVALID_DRIVE; -2278:../../../Source/third_party/fatfs/src/ff.c **** rfs = FatFs[vol]; /* Get current fs object */ - 4474 .loc 1 2278 0 - 4475 0002 074B ldr r3, .L455 - 4476 0004 1B68 ldr r3, [r3] - 4477 .LVL704: -2279:../../../Source/third_party/fatfs/src/ff.c **** -2280:../../../Source/third_party/fatfs/src/ff.c **** if (rfs) { - 4478 .loc 1 2280 0 - 4479 0006 0BB1 cbz r3, .L452 -2281:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_LOCK -2282:../../../Source/third_party/fatfs/src/ff.c **** clear_lock(rfs); -2283:../../../Source/third_party/fatfs/src/ff.c **** #endif -2284:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_REENTRANT /* Discard sync object of the current volume */ -2285:../../../Source/third_party/fatfs/src/ff.c **** if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR; -2286:../../../Source/third_party/fatfs/src/ff.c **** #endif -2287:../../../Source/third_party/fatfs/src/ff.c **** rfs->fs_type = 0; /* Clear old fs object */ - 4480 .loc 1 2287 0 - 4481 0008 0022 movs r2, #0 - 4482 000a 1A70 strb r2, [r3] - 4483 .L452: -2288:../../../Source/third_party/fatfs/src/ff.c **** } -2289:../../../Source/third_party/fatfs/src/ff.c **** -2290:../../../Source/third_party/fatfs/src/ff.c **** if (fs) { - 4484 .loc 1 2290 0 - 4485 000c 09B1 cbz r1, .L453 -2291:../../../Source/third_party/fatfs/src/ff.c **** fs->fs_type = 0; /* Clear new fs object */ - 4486 .loc 1 2291 0 - 4487 000e 0023 movs r3, #0 - 4488 .LVL705: - 4489 0010 0B70 strb r3, [r1] - 4490 .L453: -2292:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_REENTRANT /* Create sync object for the new volume */ -2293:../../../Source/third_party/fatfs/src/ff.c **** if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR; -2294:../../../Source/third_party/fatfs/src/ff.c **** #endif -2295:../../../Source/third_party/fatfs/src/ff.c **** } -2296:../../../Source/third_party/fatfs/src/ff.c **** FatFs[vol] = fs; /* Register new fs object */ - 4491 .loc 1 2296 0 - 4492 0012 034B ldr r3, .L455 - 4493 0014 1960 str r1, [r3] -2297:../../../Source/third_party/fatfs/src/ff.c **** -2298:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; - 4494 .loc 1 2298 0 - 4495 0016 0020 movs r0, #0 - 4496 .LVL706: - 4497 0018 7047 bx lr - 4498 .LVL707: - 4499 .L454: -2277:../../../Source/third_party/fatfs/src/ff.c **** rfs = FatFs[vol]; /* Get current fs object */ - 4500 .loc 1 2277 0 - 4501 001a 0B20 movs r0, #11 - 4502 .LVL708: -2299:../../../Source/third_party/fatfs/src/ff.c **** } - 4503 .loc 1 2299 0 - 4504 001c 7047 bx lr - 4505 .L456: - 4506 001e 00BF .align 2 - 4507 .L455: - 4508 0020 00000000 .word .LANCHOR0 - 4509 .cfi_endproc - 4510 .LFE32: - 4512 .section .text.f_open,"ax",%progbits - 4513 .align 2 - 4514 .global f_open - 4515 .thumb - 4516 .thumb_func - 4518 f_open: - 4519 .LFB33: -2300:../../../Source/third_party/fatfs/src/ff.c **** -2301:../../../Source/third_party/fatfs/src/ff.c **** -2302:../../../Source/third_party/fatfs/src/ff.c **** -2303:../../../Source/third_party/fatfs/src/ff.c **** -2304:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2305:../../../Source/third_party/fatfs/src/ff.c **** /* Open or Create a File */ -2306:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2307:../../../Source/third_party/fatfs/src/ff.c **** -2308:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_open ( -2309:../../../Source/third_party/fatfs/src/ff.c **** FIL *fp, /* Pointer to the blank file object */ -2310:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *path, /* Pointer to the file name */ -2311:../../../Source/third_party/fatfs/src/ff.c **** BYTE mode /* Access mode and file open mode flags */ -2312:../../../Source/third_party/fatfs/src/ff.c **** ) -2313:../../../Source/third_party/fatfs/src/ff.c **** { - 4520 .loc 1 2313 0 - 4521 .cfi_startproc - 4522 @ args = 0, pretend = 0, frame = 56 - 4523 @ frame_needed = 0, uses_anonymous_args = 0 - 4524 .LVL709: - 4525 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} - 4526 .cfi_def_cfa_offset 28 - 4527 .cfi_offset 4, -28 - 4528 .cfi_offset 5, -24 - 4529 .cfi_offset 6, -20 - 4530 .cfi_offset 7, -16 - 4531 .cfi_offset 8, -12 - 4532 .cfi_offset 9, -8 - 4533 .cfi_offset 14, -4 - 4534 0004 8FB0 sub sp, sp, #60 - 4535 .cfi_def_cfa_offset 88 - 4536 0006 0191 str r1, [sp, #4] -2314:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -2315:../../../Source/third_party/fatfs/src/ff.c **** DIR dj; -2316:../../../Source/third_party/fatfs/src/ff.c **** BYTE *dir; -2317:../../../Source/third_party/fatfs/src/ff.c **** DEF_NAMEBUF; -2318:../../../Source/third_party/fatfs/src/ff.c **** -2319:../../../Source/third_party/fatfs/src/ff.c **** -2320:../../../Source/third_party/fatfs/src/ff.c **** if (!fp) return FR_INVALID_OBJECT; - 4537 .loc 1 2320 0 - 4538 0008 0028 cmp r0, #0 - 4539 000a 00F08D80 beq .L475 - 4540 000e 0446 mov r4, r0 - 4541 0010 1546 mov r5, r2 -2321:../../../Source/third_party/fatfs/src/ff.c **** fp->fs = 0; /* Clear file object */ - 4542 .loc 1 2321 0 - 4543 0012 0023 movs r3, #0 - 4544 0014 0360 str r3, [r0] - 4545 .LVL710: -2322:../../../Source/third_party/fatfs/src/ff.c **** -2323:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -2324:../../../Source/third_party/fatfs/src/ff.c **** mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW; -2325:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ)); - 4546 .loc 1 2325 0 - 4547 0016 01A8 add r0, sp, #4 - 4548 .LVL711: - 4549 0018 05A9 add r1, sp, #20 - 4550 .LVL712: - 4551 001a 02F01E02 and r2, r2, #30 - 4552 .LVL713: - 4553 001e FFF7FEFF bl chk_mounted - 4554 .LVL714: -2326:../../../Source/third_party/fatfs/src/ff.c **** #else -2327:../../../Source/third_party/fatfs/src/ff.c **** mode &= FA_READ; -2328:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&path, &dj.fs, 0); -2329:../../../Source/third_party/fatfs/src/ff.c **** #endif -2330:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 4555 .loc 1 2330 0 - 4556 0022 0028 cmp r0, #0 - 4557 0024 40F08280 bne .L476 -2324:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ)); - 4558 .loc 1 2324 0 - 4559 0028 05F01F07 and r7, r5, #31 -2331:../../../Source/third_party/fatfs/src/ff.c **** INIT_BUF(dj); - 4560 .loc 1 2331 0 - 4561 002c 02AB add r3, sp, #8 - 4562 002e 0B93 str r3, [sp, #44] - 4563 0030 534B ldr r3, .L487 - 4564 0032 0C93 str r3, [sp, #48] -2332:../../../Source/third_party/fatfs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ - 4565 .loc 1 2332 0 - 4566 0034 05A8 add r0, sp, #20 - 4567 .LVL715: - 4568 0036 0199 ldr r1, [sp, #4] - 4569 0038 FFF7FEFF bl follow_path - 4570 .LVL716: -2333:../../../Source/third_party/fatfs/src/ff.c **** dir = dj.dir; - 4571 .loc 1 2333 0 - 4572 003c 0A9E ldr r6, [sp, #40] - 4573 .LVL717: -2334:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY /* R/W configuration */ -2335:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 4574 .loc 1 2335 0 - 4575 003e 0346 mov r3, r0 - 4576 0040 0028 cmp r0, #0 - 4577 0042 74D1 bne .L459 -2336:../../../Source/third_party/fatfs/src/ff.c **** if (!dir) /* Current dir itself */ - 4578 .loc 1 2336 0 - 4579 0044 002E cmp r6, #0 - 4580 0046 7BD1 bne .L482 - 4581 0048 75E0 b .L460 - 4582 .LVL718: - 4583 .L468: - 4584 .LBB65: -2337:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INVALID_NAME; -2338:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_LOCK -2339:../../../Source/third_party/fatfs/src/ff.c **** else -2340:../../../Source/third_party/fatfs/src/ff.c **** res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); -2341:../../../Source/third_party/fatfs/src/ff.c **** #endif -2342:../../../Source/third_party/fatfs/src/ff.c **** } -2343:../../../Source/third_party/fatfs/src/ff.c **** /* Create or Open a file */ -2344:../../../Source/third_party/fatfs/src/ff.c **** if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { -2345:../../../Source/third_party/fatfs/src/ff.c **** DWORD dw, cl; -2346:../../../Source/third_party/fatfs/src/ff.c **** -2347:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) { /* No file, create new */ -2348:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ - 4585 .loc 1 2348 0 - 4586 004a 042B cmp r3, #4 - 4587 004c 40F08880 bne .L462 -2349:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_LOCK -2350:../../../Source/third_party/fatfs/src/ff.c **** res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; -2351:../../../Source/third_party/fatfs/src/ff.c **** #else -2352:../../../Source/third_party/fatfs/src/ff.c **** res = dir_register(&dj); - 4588 .loc 1 2352 0 - 4589 0050 05A8 add r0, sp, #20 - 4590 0052 FFF7FEFF bl dir_register - 4591 .LVL719: -2353:../../../Source/third_party/fatfs/src/ff.c **** #endif -2354:../../../Source/third_party/fatfs/src/ff.c **** mode |= FA_CREATE_ALWAYS; /* File is created */ - 4592 .loc 1 2354 0 - 4593 0056 47F00807 orr r7, r7, #8 - 4594 .LVL720: -2355:../../../Source/third_party/fatfs/src/ff.c **** dir = dj.dir; /* New entry */ - 4595 .loc 1 2355 0 - 4596 005a 0A9E ldr r6, [sp, #40] -2356:../../../Source/third_party/fatfs/src/ff.c **** } -2357:../../../Source/third_party/fatfs/src/ff.c **** else { /* Any object is already existing */ -2358:../../../Source/third_party/fatfs/src/ff.c **** if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ -2359:../../../Source/third_party/fatfs/src/ff.c **** res = FR_DENIED; -2360:../../../Source/third_party/fatfs/src/ff.c **** } else { -2361:../../../Source/third_party/fatfs/src/ff.c **** if (mode & FA_CREATE_NEW) /* Cannot create as new file */ -2362:../../../Source/third_party/fatfs/src/ff.c **** res = FR_EXIST; -2363:../../../Source/third_party/fatfs/src/ff.c **** } -2364:../../../Source/third_party/fatfs/src/ff.c **** } -2365:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */ - 4597 .loc 1 2365 0 - 4598 005c 0346 mov r3, r0 - 4599 005e 48B1 cbz r0, .L463 - 4600 0060 75E0 b .L464 - 4601 .LVL721: - 4602 .L470: -2358:../../../Source/third_party/fatfs/src/ff.c **** res = FR_DENIED; - 4603 .loc 1 2358 0 - 4604 0062 F37A ldrb r3, [r6, #11] @ zero_extendqisi2 - 4605 0064 13F0110F tst r3, #17 - 4606 0068 40F08380 bne .L477 -2361:../../../Source/third_party/fatfs/src/ff.c **** res = FR_EXIST; - 4607 .loc 1 2361 0 - 4608 006c 15F0040F tst r5, #4 - 4609 0070 40F08180 bne .L478 - 4610 .LVL722: - 4611 .L463: - 4612 .loc 1 2365 0 discriminator 1 - 4613 0074 17F0080F tst r7, #8 - 4614 0078 6DD0 beq .L466 -2366:../../../Source/third_party/fatfs/src/ff.c **** dw = get_fattime(); /* Created time */ - 4615 .loc 1 2366 0 - 4616 007a FFF7FEFF bl get_fattime - 4617 .LVL723: -2367:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(dir+DIR_CrtTime, dw); - 4618 .loc 1 2367 0 - 4619 007e B073 strb r0, [r6, #14] - 4620 0080 C0F30723 ubfx r3, r0, #8, #8 - 4621 0084 F373 strb r3, [r6, #15] - 4622 0086 030C lsrs r3, r0, #16 - 4623 0088 3374 strb r3, [r6, #16] - 4624 008a 000E lsrs r0, r0, #24 - 4625 .LVL724: - 4626 008c 7074 strb r0, [r6, #17] -2368:../../../Source/third_party/fatfs/src/ff.c **** dir[DIR_Attr] = 0; /* Reset attribute */ - 4627 .loc 1 2368 0 - 4628 008e 0025 movs r5, #0 - 4629 0090 F572 strb r5, [r6, #11] -2369:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */ - 4630 .loc 1 2369 0 - 4631 0092 3577 strb r5, [r6, #28] - 4632 0094 7577 strb r5, [r6, #29] - 4633 0096 B577 strb r5, [r6, #30] - 4634 0098 F577 strb r5, [r6, #31] -2370:../../../Source/third_party/fatfs/src/ff.c **** cl = ld_clust(dj.fs, dir); /* Get start cluster */ - 4635 .loc 1 2370 0 - 4636 009a DDF81480 ldr r8, [sp, #20] - 4637 009e 4046 mov r0, r8 - 4638 00a0 3146 mov r1, r6 - 4639 00a2 FFF7FEFF bl ld_clust - 4640 .LVL725: - 4641 .LBB66: - 4642 .LBB67: -1261:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+DIR_FstClusHI, cl >> 16); - 4643 .loc 1 1261 0 - 4644 00a6 B576 strb r5, [r6, #26] - 4645 00a8 F576 strb r5, [r6, #27] -1262:../../../Source/third_party/fatfs/src/ff.c **** } - 4646 .loc 1 1262 0 - 4647 00aa 3575 strb r5, [r6, #20] - 4648 00ac 7575 strb r5, [r6, #21] - 4649 .LBE67: - 4650 .LBE66: -2371:../../../Source/third_party/fatfs/src/ff.c **** st_clust(dir, 0); /* cluster = 0 */ -2372:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->wflag = 1; - 4651 .loc 1 2372 0 - 4652 00ae 0123 movs r3, #1 - 4653 00b0 88F80430 strb r3, [r8, #4] -2373:../../../Source/third_party/fatfs/src/ff.c **** if (cl) { /* Remove the cluster chain if exist */ - 4654 .loc 1 2373 0 - 4655 00b4 0546 mov r5, r0 - 4656 00b6 0028 cmp r0, #0 - 4657 00b8 4DD0 beq .L466 -2374:../../../Source/third_party/fatfs/src/ff.c **** dw = dj.fs->winsect; - 4658 .loc 1 2374 0 - 4659 00ba D8F83090 ldr r9, [r8, #48] - 4660 .LVL726: -2375:../../../Source/third_party/fatfs/src/ff.c **** res = remove_chain(dj.fs, cl); - 4661 .loc 1 2375 0 - 4662 00be 4046 mov r0, r8 - 4663 .LVL727: - 4664 00c0 2946 mov r1, r5 - 4665 00c2 FFF7FEFF bl remove_chain - 4666 .LVL728: -2376:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 4667 .loc 1 2376 0 - 4668 00c6 0346 mov r3, r0 - 4669 00c8 0028 cmp r0, #0 - 4670 00ca 40D1 bne .L464 -2377:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */ - 4671 .loc 1 2377 0 - 4672 00cc 0598 ldr r0, [sp, #20] - 4673 .LVL729: - 4674 00ce 013D subs r5, r5, #1 - 4675 .LVL730: - 4676 00d0 C560 str r5, [r0, #12] -2378:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(dj.fs, dw); - 4677 .loc 1 2378 0 - 4678 00d2 4946 mov r1, r9 - 4679 00d4 FFF7FEFF bl move_window - 4680 .LVL731: - 4681 .LBE65: -2379:../../../Source/third_party/fatfs/src/ff.c **** } -2380:../../../Source/third_party/fatfs/src/ff.c **** } -2381:../../../Source/third_party/fatfs/src/ff.c **** } -2382:../../../Source/third_party/fatfs/src/ff.c **** } -2383:../../../Source/third_party/fatfs/src/ff.c **** else { /* Open an existing file */ -2384:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { /* Follow succeeded */ -2385:../../../Source/third_party/fatfs/src/ff.c **** if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */ -2386:../../../Source/third_party/fatfs/src/ff.c **** res = FR_NO_FILE; -2387:../../../Source/third_party/fatfs/src/ff.c **** } else { -2388:../../../Source/third_party/fatfs/src/ff.c **** if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ -2389:../../../Source/third_party/fatfs/src/ff.c **** res = FR_DENIED; -2390:../../../Source/third_party/fatfs/src/ff.c **** } -2391:../../../Source/third_party/fatfs/src/ff.c **** } -2392:../../../Source/third_party/fatfs/src/ff.c **** } -2393:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 4682 .loc 1 2393 0 - 4683 00d8 38B1 cbz r0, .L467 - 4684 00da 4DE0 b .L483 - 4685 .LVL732: - 4686 .L485: -2388:../../../Source/third_party/fatfs/src/ff.c **** res = FR_DENIED; - 4687 .loc 1 2388 0 - 4688 00dc 15F0020F tst r5, #2 - 4689 00e0 39D0 beq .L466 -2388:../../../Source/third_party/fatfs/src/ff.c **** res = FR_DENIED; - 4690 .loc 1 2388 0 is_stmt 0 discriminator 1 - 4691 00e2 13F0010F tst r3, #1 - 4692 00e6 2FD1 bne .L479 - 4693 00e8 35E0 b .L466 - 4694 .LVL733: - 4695 .L467: -2394:../../../Source/third_party/fatfs/src/ff.c **** if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ -2395:../../../Source/third_party/fatfs/src/ff.c **** mode |= FA__WRITTEN; - 4696 .loc 1 2395 0 is_stmt 1 - 4697 00ea 47F02007 orr r7, r7, #32 - 4698 .LVL734: - 4699 .L473: -2396:../../../Source/third_party/fatfs/src/ff.c **** fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ - 4700 .loc 1 2396 0 - 4701 00ee 059B ldr r3, [sp, #20] - 4702 00f0 1B6B ldr r3, [r3, #48] - 4703 00f2 E361 str r3, [r4, #28] -2397:../../../Source/third_party/fatfs/src/ff.c **** fp->dir_ptr = dir; - 4704 .loc 1 2397 0 - 4705 00f4 2662 str r6, [r4, #32] - 4706 .L472: -2398:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_LOCK -2399:../../../Source/third_party/fatfs/src/ff.c **** fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); -2400:../../../Source/third_party/fatfs/src/ff.c **** if (!fp->lockid) res = FR_INT_ERR; -2401:../../../Source/third_party/fatfs/src/ff.c **** #endif -2402:../../../Source/third_party/fatfs/src/ff.c **** } -2403:../../../Source/third_party/fatfs/src/ff.c **** -2404:../../../Source/third_party/fatfs/src/ff.c **** #else /* R/O configuration */ -2405:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { /* Follow succeeded */ -2406:../../../Source/third_party/fatfs/src/ff.c **** dir = dj.dir; -2407:../../../Source/third_party/fatfs/src/ff.c **** if (!dir) { /* Current dir itself */ -2408:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INVALID_NAME; -2409:../../../Source/third_party/fatfs/src/ff.c **** } else { -2410:../../../Source/third_party/fatfs/src/ff.c **** if (dir[DIR_Attr] & AM_DIR) /* It is a directory */ -2411:../../../Source/third_party/fatfs/src/ff.c **** res = FR_NO_FILE; -2412:../../../Source/third_party/fatfs/src/ff.c **** } -2413:../../../Source/third_party/fatfs/src/ff.c **** } -2414:../../../Source/third_party/fatfs/src/ff.c **** #endif -2415:../../../Source/third_party/fatfs/src/ff.c **** FREE_BUF(); -2416:../../../Source/third_party/fatfs/src/ff.c **** -2417:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -2418:../../../Source/third_party/fatfs/src/ff.c **** fp->flag = mode; /* File access mode */ - 4707 .loc 1 2418 0 - 4708 00f6 A771 strb r7, [r4, #6] -2419:../../../Source/third_party/fatfs/src/ff.c **** fp->sclust = ld_clust(dj.fs, dir); /* File start cluster */ - 4709 .loc 1 2419 0 - 4710 00f8 059D ldr r5, [sp, #20] - 4711 00fa 2846 mov r0, r5 - 4712 00fc 3146 mov r1, r6 - 4713 00fe FFF7FEFF bl ld_clust - 4714 .LVL735: - 4715 0102 2061 str r0, [r4, #16] -2420:../../../Source/third_party/fatfs/src/ff.c **** fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */ - 4716 .loc 1 2420 0 - 4717 0104 F17F ldrb r1, [r6, #31] @ zero_extendqisi2 - 4718 0106 B27F ldrb r2, [r6, #30] @ zero_extendqisi2 - 4719 0108 1304 lsls r3, r2, #16 - 4720 010a 43EA0162 orr r2, r3, r1, lsl #24 - 4721 010e 337F ldrb r3, [r6, #28] @ zero_extendqisi2 - 4722 0110 1343 orrs r3, r3, r2 - 4723 0112 727F ldrb r2, [r6, #29] @ zero_extendqisi2 - 4724 0114 43EA0223 orr r3, r3, r2, lsl #8 - 4725 0118 E360 str r3, [r4, #12] -2421:../../../Source/third_party/fatfs/src/ff.c **** fp->fptr = 0; /* File pointer */ - 4726 .loc 1 2421 0 - 4727 011a 0020 movs r0, #0 - 4728 011c A060 str r0, [r4, #8] -2422:../../../Source/third_party/fatfs/src/ff.c **** fp->dsect = 0; - 4729 .loc 1 2422 0 - 4730 011e A061 str r0, [r4, #24] -2423:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_FASTSEEK -2424:../../../Source/third_party/fatfs/src/ff.c **** fp->cltbl = 0; /* Normal seek mode */ -2425:../../../Source/third_party/fatfs/src/ff.c **** #endif -2426:../../../Source/third_party/fatfs/src/ff.c **** fp->fs = dj.fs; fp->id = dj.fs->id; /* Validate file object */ - 4731 .loc 1 2426 0 - 4732 0120 2560 str r5, [r4] - 4733 0122 EB88 ldrh r3, [r5, #6] - 4734 0124 A380 strh r3, [r4, #4] @ movhi - 4735 0126 27E0 b .L483 - 4736 .LVL736: - 4737 .L475: -2320:../../../Source/third_party/fatfs/src/ff.c **** fp->fs = 0; /* Clear file object */ - 4738 .loc 1 2320 0 - 4739 0128 0920 movs r0, #9 - 4740 .LVL737: - 4741 012a 25E0 b .L483 - 4742 .LVL738: - 4743 .L476: - 4744 012c 24E0 b .L483 - 4745 .LVL739: - 4746 .L459: -2344:../../../Source/third_party/fatfs/src/ff.c **** DWORD dw, cl; - 4747 .loc 1 2344 0 - 4748 012e 15F01C0F tst r5, #28 - 4749 0132 8AD1 bne .L468 - 4750 0134 0BE0 b .L464 - 4751 .LVL740: - 4752 .L460: - 4753 0136 15F01C0F tst r5, #28 - 4754 013a 10D1 bne .L480 -2337:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_LOCK - 4755 .loc 1 2337 0 - 4756 013c 0623 movs r3, #6 - 4757 013e 06E0 b .L464 - 4758 .LVL741: - 4759 .L482: -2344:../../../Source/third_party/fatfs/src/ff.c **** DWORD dw, cl; - 4760 .loc 1 2344 0 - 4761 0140 15F01C0F tst r5, #28 - 4762 0144 8DD1 bne .L470 - 4763 0146 0FE0 b .L484 - 4764 .L479: -2389:../../../Source/third_party/fatfs/src/ff.c **** } - 4765 .loc 1 2389 0 - 4766 0148 0723 movs r3, #7 - 4767 014a 00E0 b .L464 - 4768 .L481: -2386:../../../Source/third_party/fatfs/src/ff.c **** } else { - 4769 .loc 1 2386 0 - 4770 014c 0423 movs r3, #4 - 4771 .LVL742: - 4772 .L464: -2417:../../../Source/third_party/fatfs/src/ff.c **** fp->flag = mode; /* File access mode */ - 4773 .loc 1 2417 0 - 4774 014e 002B cmp r3, #0 - 4775 0150 D1D0 beq .L472 - 4776 0152 1846 mov r0, r3 - 4777 0154 10E0 b .L483 - 4778 .LVL743: - 4779 .L466: -2394:../../../Source/third_party/fatfs/src/ff.c **** mode |= FA__WRITTEN; - 4780 .loc 1 2394 0 - 4781 0156 17F0080F tst r7, #8 - 4782 015a C6D1 bne .L467 - 4783 015c C7E7 b .L473 - 4784 .LVL744: - 4785 .L480: -2337:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_LOCK - 4786 .loc 1 2337 0 - 4787 015e 0623 movs r3, #6 - 4788 .LVL745: - 4789 .L462: - 4790 .LBB68: -2354:../../../Source/third_party/fatfs/src/ff.c **** dir = dj.dir; /* New entry */ - 4791 .loc 1 2354 0 - 4792 0160 47F00807 orr r7, r7, #8 - 4793 .LVL746: -2355:../../../Source/third_party/fatfs/src/ff.c **** } - 4794 .loc 1 2355 0 - 4795 0164 0A9E ldr r6, [sp, #40] - 4796 0166 F2E7 b .L464 - 4797 .LVL747: - 4798 .L484: - 4799 .LBE68: -2385:../../../Source/third_party/fatfs/src/ff.c **** res = FR_NO_FILE; - 4800 .loc 1 2385 0 - 4801 0168 F37A ldrb r3, [r6, #11] @ zero_extendqisi2 - 4802 016a 13F0100F tst r3, #16 - 4803 016e EDD1 bne .L481 - 4804 0170 B4E7 b .L485 - 4805 .L477: - 4806 .LBB69: -2359:../../../Source/third_party/fatfs/src/ff.c **** } else { - 4807 .loc 1 2359 0 - 4808 0172 0720 movs r0, #7 - 4809 0174 00E0 b .L483 - 4810 .L478: -2362:../../../Source/third_party/fatfs/src/ff.c **** } - 4811 .loc 1 2362 0 - 4812 0176 0820 movs r0, #8 - 4813 .LVL748: - 4814 .L483: - 4815 .LBE69: -2427:../../../Source/third_party/fatfs/src/ff.c **** } -2428:../../../Source/third_party/fatfs/src/ff.c **** } -2429:../../../Source/third_party/fatfs/src/ff.c **** -2430:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(dj.fs, res); -2431:../../../Source/third_party/fatfs/src/ff.c **** } - 4816 .loc 1 2431 0 - 4817 0178 0FB0 add sp, sp, #60 - 4818 .cfi_def_cfa_offset 28 - 4819 @ sp needed - 4820 017a BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} - 4821 .LVL749: - 4822 .L488: - 4823 017e 00BF .align 2 - 4824 .L487: - 4825 0180 00000000 .word .LANCHOR4 - 4826 .cfi_endproc - 4827 .LFE33: - 4829 .section .text.f_read,"ax",%progbits - 4830 .align 2 - 4831 .global f_read - 4832 .thumb - 4833 .thumb_func - 4835 f_read: - 4836 .LFB34: -2432:../../../Source/third_party/fatfs/src/ff.c **** -2433:../../../Source/third_party/fatfs/src/ff.c **** -2434:../../../Source/third_party/fatfs/src/ff.c **** -2435:../../../Source/third_party/fatfs/src/ff.c **** -2436:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2437:../../../Source/third_party/fatfs/src/ff.c **** /* Read File */ -2438:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2439:../../../Source/third_party/fatfs/src/ff.c **** -2440:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_read ( -2441:../../../Source/third_party/fatfs/src/ff.c **** FIL *fp, /* Pointer to the file object */ -2442:../../../Source/third_party/fatfs/src/ff.c **** void *buff, /* Pointer to data buffer */ -2443:../../../Source/third_party/fatfs/src/ff.c **** UINT btr, /* Number of bytes to read */ -2444:../../../Source/third_party/fatfs/src/ff.c **** UINT *br /* Pointer to number of bytes read */ -2445:../../../Source/third_party/fatfs/src/ff.c **** ) -2446:../../../Source/third_party/fatfs/src/ff.c **** { - 4837 .loc 1 2446 0 - 4838 .cfi_startproc - 4839 @ args = 0, pretend = 0, frame = 8 - 4840 @ frame_needed = 0, uses_anonymous_args = 0 - 4841 .LVL750: - 4842 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} - 4843 .cfi_def_cfa_offset 36 - 4844 .cfi_offset 4, -36 - 4845 .cfi_offset 5, -32 - 4846 .cfi_offset 6, -28 - 4847 .cfi_offset 7, -24 - 4848 .cfi_offset 8, -20 - 4849 .cfi_offset 9, -16 - 4850 .cfi_offset 10, -12 - 4851 .cfi_offset 11, -8 - 4852 .cfi_offset 14, -4 - 4853 0004 83B0 sub sp, sp, #12 - 4854 .cfi_def_cfa_offset 48 - 4855 0006 0446 mov r4, r0 - 4856 0008 8946 mov r9, r1 - 4857 000a 1546 mov r5, r2 - 4858 000c 9846 mov r8, r3 - 4859 .LVL751: -2447:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -2448:../../../Source/third_party/fatfs/src/ff.c **** DWORD clst, sect, remain; -2449:../../../Source/third_party/fatfs/src/ff.c **** UINT rcnt, cc; -2450:../../../Source/third_party/fatfs/src/ff.c **** BYTE csect, *rbuff = (BYTE*)buff; -2451:../../../Source/third_party/fatfs/src/ff.c **** -2452:../../../Source/third_party/fatfs/src/ff.c **** -2453:../../../Source/third_party/fatfs/src/ff.c **** *br = 0; /* Clear read byte counter */ - 4860 .loc 1 2453 0 - 4861 000e 0023 movs r3, #0 - 4862 .LVL752: - 4863 0010 C8F80030 str r3, [r8] -2454:../../../Source/third_party/fatfs/src/ff.c **** -2455:../../../Source/third_party/fatfs/src/ff.c **** res = validate(fp); /* Check validity */ - 4864 .loc 1 2455 0 - 4865 0014 FFF7FEFF bl validate - 4866 .LVL753: -2456:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) LEAVE_FF(fp->fs, res); - 4867 .loc 1 2456 0 - 4868 0018 0028 cmp r0, #0 - 4869 001a 40F0B580 bne .L507 -2457:../../../Source/third_party/fatfs/src/ff.c **** if (fp->flag & FA__ERROR) /* Aborted file? */ - 4870 .loc 1 2457 0 - 4871 001e A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 4872 0020 13F0800F tst r3, #128 - 4873 0024 40F0B180 bne .L508 -2458:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, FR_INT_ERR); -2459:../../../Source/third_party/fatfs/src/ff.c **** if (!(fp->flag & FA_READ)) /* Check access mode */ - 4874 .loc 1 2459 0 - 4875 0028 13F0010F tst r3, #1 - 4876 002c 00F0AF80 beq .L509 -2460:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, FR_DENIED); -2461:../../../Source/third_party/fatfs/src/ff.c **** remain = fp->fsize - fp->fptr; - 4877 .loc 1 2461 0 - 4878 0030 E368 ldr r3, [r4, #12] - 4879 0032 A668 ldr r6, [r4, #8] - 4880 0034 9E1B subs r6, r3, r6 - 4881 .LVL754: - 4882 0036 AE42 cmp r6, r5 - 4883 0038 28BF it cs - 4884 003a 2E46 movcs r6, r5 - 4885 .LVL755: -2462:../../../Source/third_party/fatfs/src/ff.c **** if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ -2463:../../../Source/third_party/fatfs/src/ff.c **** -2464:../../../Source/third_party/fatfs/src/ff.c **** for ( ; btr; /* Repeat until all data read */ - 4886 .loc 1 2464 0 - 4887 003c 002E cmp r6, #0 - 4888 003e 00F0A880 beq .L510 -2465:../../../Source/third_party/fatfs/src/ff.c **** rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { -2466:../../../Source/third_party/fatfs/src/ff.c **** if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ -2467:../../../Source/third_party/fatfs/src/ff.c **** csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ -2468:../../../Source/third_party/fatfs/src/ff.c **** if (!csect) { /* On the cluster boundary? */ -2469:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fptr == 0) { /* On the top of the file? */ -2470:../../../Source/third_party/fatfs/src/ff.c **** clst = fp->sclust; /* Follow from the origin */ -2471:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Middle or end of the file */ -2472:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_FASTSEEK -2473:../../../Source/third_party/fatfs/src/ff.c **** if (fp->cltbl) -2474:../../../Source/third_party/fatfs/src/ff.c **** clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ -2475:../../../Source/third_party/fatfs/src/ff.c **** else -2476:../../../Source/third_party/fatfs/src/ff.c **** #endif -2477:../../../Source/third_party/fatfs/src/ff.c **** clst = get_fat(fp->fs, fp->clust); /* Follow cluster chain on the FAT */ -2478:../../../Source/third_party/fatfs/src/ff.c **** } -2479:../../../Source/third_party/fatfs/src/ff.c **** if (clst < 2) ABORT(fp->fs, FR_INT_ERR); -2480:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); -2481:../../../Source/third_party/fatfs/src/ff.c **** fp->clust = clst; /* Update current cluster */ -2482:../../../Source/third_party/fatfs/src/ff.c **** } -2483:../../../Source/third_party/fatfs/src/ff.c **** sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ -2484:../../../Source/third_party/fatfs/src/ff.c **** if (!sect) ABORT(fp->fs, FR_INT_ERR); -2485:../../../Source/third_party/fatfs/src/ff.c **** sect += csect; -2486:../../../Source/third_party/fatfs/src/ff.c **** cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ -2487:../../../Source/third_party/fatfs/src/ff.c **** if (cc) { /* Read maximum contiguous sectors directly */ -2488:../../../Source/third_party/fatfs/src/ff.c **** if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ -2489:../../../Source/third_party/fatfs/src/ff.c **** cc = fp->fs->csize - csect; -2490:../../../Source/third_party/fatfs/src/ff.c **** if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK) -2491:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); -2492:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it -2493:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_TINY -2494:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fs->wflag && fp->fs->winsect - sect < cc) -2495:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs)); -2496:../../../Source/third_party/fatfs/src/ff.c **** #else -2497:../../../Source/third_party/fatfs/src/ff.c **** if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc) -2498:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); -2499:../../../Source/third_party/fatfs/src/ff.c **** #endif -2500:../../../Source/third_party/fatfs/src/ff.c **** #endif -2501:../../../Source/third_party/fatfs/src/ff.c **** rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ -2502:../../../Source/third_party/fatfs/src/ff.c **** continue; -2503:../../../Source/third_party/fatfs/src/ff.c **** } -2504:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_TINY -2505:../../../Source/third_party/fatfs/src/ff.c **** if (fp->dsect != sect) { /* Load data sector if not in cache */ -2506:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -2507:../../../Source/third_party/fatfs/src/ff.c **** if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ -2508:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) -2509:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); -2510:../../../Source/third_party/fatfs/src/ff.c **** fp->flag &= ~FA__DIRTY; -2511:../../../Source/third_party/fatfs/src/ff.c **** } -2512:../../../Source/third_party/fatfs/src/ff.c **** #endif -2513:../../../Source/third_party/fatfs/src/ff.c **** if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) /* Fill sector cache */ - 4889 .loc 1 2513 0 - 4890 0042 04F12403 add r3, r4, #36 - 4891 .LVL756: - 4892 0046 0193 str r3, [sp, #4] - 4893 .LVL757: - 4894 .L511: -2466:../../../Source/third_party/fatfs/src/ff.c **** csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - 4895 .loc 1 2466 0 - 4896 0048 A368 ldr r3, [r4, #8] - 4897 004a C3F30802 ubfx r2, r3, #0, #9 - 4898 004e 002A cmp r2, #0 - 4899 0050 7ED1 bne .L491 -2467:../../../Source/third_party/fatfs/src/ff.c **** if (!csect) { /* On the cluster boundary? */ - 4900 .loc 1 2467 0 - 4901 0052 2068 ldr r0, [r4] - 4902 0054 8778 ldrb r7, [r0, #2] @ zero_extendqisi2 - 4903 0056 013F subs r7, r7, #1 - 4904 0058 07EA5327 and r7, r7, r3, lsr #9 - 4905 .LVL758: -2468:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fptr == 0) { /* On the top of the file? */ - 4906 .loc 1 2468 0 - 4907 005c 17F0FF07 ands r7, r7, #255 - 4908 .LVL759: - 4909 0060 17D1 bne .L492 -2469:../../../Source/third_party/fatfs/src/ff.c **** clst = fp->sclust; /* Follow from the origin */ - 4910 .loc 1 2469 0 - 4911 0062 0BB9 cbnz r3, .L493 -2470:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Middle or end of the file */ - 4912 .loc 1 2470 0 - 4913 0064 2069 ldr r0, [r4, #16] - 4914 .LVL760: - 4915 0066 02E0 b .L494 - 4916 .LVL761: - 4917 .L493: -2477:../../../Source/third_party/fatfs/src/ff.c **** } - 4918 .loc 1 2477 0 - 4919 0068 6169 ldr r1, [r4, #20] - 4920 006a FFF7FEFF bl get_fat - 4921 .LVL762: - 4922 .L494: -2479:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - 4923 .loc 1 2479 0 - 4924 006e 0128 cmp r0, #1 - 4925 0070 05D8 bhi .L495 -2479:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - 4926 .loc 1 2479 0 is_stmt 0 discriminator 1 - 4927 0072 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 4928 0074 63F07F03 orn r3, r3, #127 - 4929 0078 A371 strb r3, [r4, #6] - 4930 007a 0220 movs r0, #2 - 4931 .LVL763: - 4932 007c 8AE0 b .L490 - 4933 .LVL764: - 4934 .L495: -2480:../../../Source/third_party/fatfs/src/ff.c **** fp->clust = clst; /* Update current cluster */ - 4935 .loc 1 2480 0 is_stmt 1 - 4936 007e B0F1FF3F cmp r0, #-1 - 4937 0082 05D1 bne .L496 -2480:../../../Source/third_party/fatfs/src/ff.c **** fp->clust = clst; /* Update current cluster */ - 4938 .loc 1 2480 0 is_stmt 0 discriminator 1 - 4939 0084 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 4940 0086 63F07F03 orn r3, r3, #127 - 4941 008a A371 strb r3, [r4, #6] - 4942 008c 0120 movs r0, #1 - 4943 .LVL765: - 4944 008e 81E0 b .L490 - 4945 .LVL766: - 4946 .L496: -2481:../../../Source/third_party/fatfs/src/ff.c **** } - 4947 .loc 1 2481 0 is_stmt 1 - 4948 0090 6061 str r0, [r4, #20] - 4949 .LVL767: - 4950 .L492: -2483:../../../Source/third_party/fatfs/src/ff.c **** if (!sect) ABORT(fp->fs, FR_INT_ERR); - 4951 .loc 1 2483 0 - 4952 0092 D4F800B0 ldr fp, [r4] - 4953 0096 5846 mov r0, fp - 4954 0098 6169 ldr r1, [r4, #20] - 4955 009a FFF7FEFF bl clust2sect - 4956 .LVL768: -2484:../../../Source/third_party/fatfs/src/ff.c **** sect += csect; - 4957 .loc 1 2484 0 - 4958 009e 8246 mov r10, r0 - 4959 00a0 28B9 cbnz r0, .L497 -2484:../../../Source/third_party/fatfs/src/ff.c **** sect += csect; - 4960 .loc 1 2484 0 is_stmt 0 discriminator 1 - 4961 00a2 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 4962 00a4 63F07F03 orn r3, r3, #127 - 4963 00a8 A371 strb r3, [r4, #6] - 4964 00aa 0220 movs r0, #2 - 4965 .LVL769: - 4966 00ac 72E0 b .L490 - 4967 .LVL770: - 4968 .L497: -2485:../../../Source/third_party/fatfs/src/ff.c **** cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ - 4969 .loc 1 2485 0 is_stmt 1 - 4970 00ae BA44 add r10, r10, r7 - 4971 .LVL771: -2487:../../../Source/third_party/fatfs/src/ff.c **** if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ - 4972 .loc 1 2487 0 - 4973 00b0 750A lsrs r5, r6, #9 - 4974 .LVL772: - 4975 00b2 25D0 beq .L498 -2488:../../../Source/third_party/fatfs/src/ff.c **** cc = fp->fs->csize - csect; - 4976 .loc 1 2488 0 - 4977 00b4 9BF80230 ldrb r3, [fp, #2] @ zero_extendqisi2 - 4978 00b8 EA19 adds r2, r5, r7 - 4979 00ba 9A42 cmp r2, r3 -2489:../../../Source/third_party/fatfs/src/ff.c **** if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK) - 4980 .loc 1 2489 0 - 4981 00bc 88BF it hi - 4982 00be DD1B subhi r5, r3, r7 - 4983 .LVL773: -2490:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); - 4984 .loc 1 2490 0 - 4985 00c0 9BF80100 ldrb r0, [fp, #1] @ zero_extendqisi2 - 4986 00c4 4946 mov r1, r9 - 4987 00c6 5246 mov r2, r10 - 4988 00c8 EBB2 uxtb r3, r5 - 4989 00ca FFF7FEFF bl disk_read - 4990 .LVL774: - 4991 00ce 28B1 cbz r0, .L500 -2491:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it - 4992 .loc 1 2491 0 - 4993 00d0 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 4994 00d2 63F07F03 orn r3, r3, #127 - 4995 00d6 A371 strb r3, [r4, #6] - 4996 00d8 0120 movs r0, #1 - 4997 00da 5BE0 b .L490 - 4998 .L500: -2497:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); - 4999 .loc 1 2497 0 - 5000 00dc A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5001 00de 13F0400F tst r3, #64 - 5002 00e2 0BD0 beq .L501 -2497:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); - 5003 .loc 1 2497 0 is_stmt 0 discriminator 1 - 5004 00e4 A069 ldr r0, [r4, #24] - 5005 00e6 CAEB0000 rsb r0, r10, r0 - 5006 00ea 8542 cmp r5, r0 - 5007 00ec 06D9 bls .L501 -2498:../../../Source/third_party/fatfs/src/ff.c **** #endif - 5008 .loc 1 2498 0 is_stmt 1 - 5009 00ee 09EB4020 add r0, r9, r0, lsl #9 - 5010 00f2 0199 ldr r1, [sp, #4] - 5011 00f4 4FF40072 mov r2, #512 - 5012 00f8 FFF7FEFF bl mem_cpy - 5013 .LVL775: - 5014 .L501: -2501:../../../Source/third_party/fatfs/src/ff.c **** continue; - 5015 .loc 1 2501 0 - 5016 00fc 6D02 lsls r5, r5, #9 - 5017 .LVL776: -2502:../../../Source/third_party/fatfs/src/ff.c **** } - 5018 .loc 1 2502 0 - 5019 00fe 35E0 b .L502 - 5020 .LVL777: - 5021 .L498: -2505:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY - 5022 .loc 1 2505 0 - 5023 0100 A269 ldr r2, [r4, #24] - 5024 0102 5245 cmp r2, r10 - 5025 0104 22D0 beq .L503 -2507:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - 5026 .loc 1 2507 0 - 5027 0106 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5028 0108 13F0400F tst r3, #64 - 5029 010c 10D0 beq .L504 -2508:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); - 5030 .loc 1 2508 0 - 5031 010e 9BF80100 ldrb r0, [fp, #1] @ zero_extendqisi2 - 5032 0112 0199 ldr r1, [sp, #4] - 5033 0114 0123 movs r3, #1 - 5034 0116 FFF7FEFF bl disk_write - 5035 .LVL778: - 5036 011a 28B1 cbz r0, .L505 -2509:../../../Source/third_party/fatfs/src/ff.c **** fp->flag &= ~FA__DIRTY; - 5037 .loc 1 2509 0 - 5038 011c A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5039 011e 63F07F03 orn r3, r3, #127 - 5040 0122 A371 strb r3, [r4, #6] - 5041 0124 0120 movs r0, #1 - 5042 0126 35E0 b .L490 - 5043 .L505: -2510:../../../Source/third_party/fatfs/src/ff.c **** } - 5044 .loc 1 2510 0 - 5045 0128 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5046 012a 23F04003 bic r3, r3, #64 - 5047 012e A371 strb r3, [r4, #6] - 5048 .L504: - 5049 .loc 1 2513 0 - 5050 0130 2368 ldr r3, [r4] - 5051 0132 5878 ldrb r0, [r3, #1] @ zero_extendqisi2 - 5052 0134 0199 ldr r1, [sp, #4] - 5053 0136 5246 mov r2, r10 - 5054 0138 0123 movs r3, #1 - 5055 013a FFF7FEFF bl disk_read - 5056 .LVL779: - 5057 013e 28B1 cbz r0, .L503 -2514:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); - 5058 .loc 1 2514 0 - 5059 0140 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5060 0142 63F07F03 orn r3, r3, #127 - 5061 0146 A371 strb r3, [r4, #6] - 5062 0148 0120 movs r0, #1 - 5063 014a 23E0 b .L490 - 5064 .L503: -2515:../../../Source/third_party/fatfs/src/ff.c **** } -2516:../../../Source/third_party/fatfs/src/ff.c **** #endif -2517:../../../Source/third_party/fatfs/src/ff.c **** fp->dsect = sect; - 5065 .loc 1 2517 0 - 5066 014c C4F818A0 str r10, [r4, #24] - 5067 .LVL780: - 5068 .L491: -2518:../../../Source/third_party/fatfs/src/ff.c **** } -2519:../../../Source/third_party/fatfs/src/ff.c **** rcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer - 5069 .loc 1 2519 0 - 5070 0150 A168 ldr r1, [r4, #8] - 5071 0152 C1F30801 ubfx r1, r1, #0, #9 - 5072 0156 C1F50075 rsb r5, r1, #512 - 5073 .LVL781: - 5074 015a B542 cmp r5, r6 - 5075 015c 28BF it cs - 5076 015e 3546 movcs r5, r6 - 5077 .LVL782: -2520:../../../Source/third_party/fatfs/src/ff.c **** if (rcnt > btr) rcnt = btr; -2521:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_TINY -2522:../../../Source/third_party/fatfs/src/ff.c **** if (move_window(fp->fs, fp->dsect)) /* Move sector window */ -2523:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); -2524:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ -2525:../../../Source/third_party/fatfs/src/ff.c **** #else -2526:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ - 5078 .loc 1 2526 0 - 5079 0160 2144 add r1, r1, r4 - 5080 0162 4846 mov r0, r9 - 5081 0164 2431 adds r1, r1, #36 - 5082 0166 2A46 mov r2, r5 - 5083 0168 FFF7FEFF bl mem_cpy - 5084 .LVL783: - 5085 .L502: -2465:../../../Source/third_party/fatfs/src/ff.c **** if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - 5086 .loc 1 2465 0 - 5087 016c A944 add r9, r9, r5 - 5088 .LVL784: - 5089 016e A368 ldr r3, [r4, #8] - 5090 0170 2B44 add r3, r3, r5 - 5091 0172 A360 str r3, [r4, #8] - 5092 0174 D8F80030 ldr r3, [r8] - 5093 0178 2B44 add r3, r3, r5 - 5094 017a C8F80030 str r3, [r8] - 5095 .LVL785: -2464:../../../Source/third_party/fatfs/src/ff.c **** rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { - 5096 .loc 1 2464 0 - 5097 017e 761B subs r6, r6, r5 - 5098 .LVL786: - 5099 0180 7FF462AF bne .L511 -2527:../../../Source/third_party/fatfs/src/ff.c **** #endif -2528:../../../Source/third_party/fatfs/src/ff.c **** } -2529:../../../Source/third_party/fatfs/src/ff.c **** -2530:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, FR_OK); - 5100 .loc 1 2530 0 - 5101 0184 0020 movs r0, #0 - 5102 0186 05E0 b .L490 - 5103 .LVL787: - 5104 .L507: - 5105 0188 04E0 b .L490 - 5106 .L508: -2458:../../../Source/third_party/fatfs/src/ff.c **** if (!(fp->flag & FA_READ)) /* Check access mode */ - 5107 .loc 1 2458 0 - 5108 018a 0220 movs r0, #2 - 5109 .LVL788: - 5110 018c 02E0 b .L490 - 5111 .LVL789: - 5112 .L509: -2460:../../../Source/third_party/fatfs/src/ff.c **** remain = fp->fsize - fp->fptr; - 5113 .loc 1 2460 0 - 5114 018e 0720 movs r0, #7 - 5115 .LVL790: - 5116 0190 00E0 b .L490 - 5117 .LVL791: - 5118 .L510: - 5119 .loc 1 2530 0 - 5120 0192 0020 movs r0, #0 - 5121 .LVL792: - 5122 .L490: -2531:../../../Source/third_party/fatfs/src/ff.c **** } - 5123 .loc 1 2531 0 - 5124 0194 03B0 add sp, sp, #12 - 5125 .cfi_def_cfa_offset 36 - 5126 @ sp needed - 5127 0196 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} - 5128 .cfi_endproc - 5129 .LFE34: - 5131 019a 00BF .section .text.f_write,"ax",%progbits - 5132 .align 2 - 5133 .global f_write - 5134 .thumb - 5135 .thumb_func - 5137 f_write: - 5138 .LFB35: -2532:../../../Source/third_party/fatfs/src/ff.c **** -2533:../../../Source/third_party/fatfs/src/ff.c **** -2534:../../../Source/third_party/fatfs/src/ff.c **** -2535:../../../Source/third_party/fatfs/src/ff.c **** -2536:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -2537:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2538:../../../Source/third_party/fatfs/src/ff.c **** /* Write File */ -2539:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2540:../../../Source/third_party/fatfs/src/ff.c **** -2541:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_write ( -2542:../../../Source/third_party/fatfs/src/ff.c **** FIL *fp, /* Pointer to the file object */ -2543:../../../Source/third_party/fatfs/src/ff.c **** const void *buff, /* Pointer to the data to be written */ -2544:../../../Source/third_party/fatfs/src/ff.c **** UINT btw, /* Number of bytes to write */ -2545:../../../Source/third_party/fatfs/src/ff.c **** UINT *bw /* Pointer to number of bytes written */ -2546:../../../Source/third_party/fatfs/src/ff.c **** ) -2547:../../../Source/third_party/fatfs/src/ff.c **** { - 5139 .loc 1 2547 0 - 5140 .cfi_startproc - 5141 @ args = 0, pretend = 0, frame = 8 - 5142 @ frame_needed = 0, uses_anonymous_args = 0 - 5143 .LVL793: - 5144 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} - 5145 .cfi_def_cfa_offset 36 - 5146 .cfi_offset 4, -36 - 5147 .cfi_offset 5, -32 - 5148 .cfi_offset 6, -28 - 5149 .cfi_offset 7, -24 - 5150 .cfi_offset 8, -20 - 5151 .cfi_offset 9, -16 - 5152 .cfi_offset 10, -12 - 5153 .cfi_offset 11, -8 - 5154 .cfi_offset 14, -4 - 5155 0004 83B0 sub sp, sp, #12 - 5156 .cfi_def_cfa_offset 48 - 5157 0006 0446 mov r4, r0 - 5158 0008 8946 mov r9, r1 - 5159 000a 1646 mov r6, r2 - 5160 000c 9846 mov r8, r3 - 5161 .LVL794: -2548:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -2549:../../../Source/third_party/fatfs/src/ff.c **** DWORD clst, sect; -2550:../../../Source/third_party/fatfs/src/ff.c **** UINT wcnt, cc; -2551:../../../Source/third_party/fatfs/src/ff.c **** const BYTE *wbuff = (const BYTE*)buff; -2552:../../../Source/third_party/fatfs/src/ff.c **** BYTE csect; -2553:../../../Source/third_party/fatfs/src/ff.c **** -2554:../../../Source/third_party/fatfs/src/ff.c **** -2555:../../../Source/third_party/fatfs/src/ff.c **** *bw = 0; /* Clear write byte counter */ - 5162 .loc 1 2555 0 - 5163 000e 0023 movs r3, #0 - 5164 .LVL795: - 5165 0010 C8F80030 str r3, [r8] -2556:../../../Source/third_party/fatfs/src/ff.c **** -2557:../../../Source/third_party/fatfs/src/ff.c **** res = validate(fp); /* Check validity */ - 5166 .loc 1 2557 0 - 5167 0014 FFF7FEFF bl validate - 5168 .LVL796: -2558:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) LEAVE_FF(fp->fs, res); - 5169 .loc 1 2558 0 - 5170 0018 0028 cmp r0, #0 - 5171 001a 40F0D080 bne .L535 -2559:../../../Source/third_party/fatfs/src/ff.c **** if (fp->flag & FA__ERROR) /* Aborted file? */ - 5172 .loc 1 2559 0 - 5173 001e A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5174 0020 13F0800F tst r3, #128 - 5175 0024 40F0CC80 bne .L536 -2560:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, FR_INT_ERR); -2561:../../../Source/third_party/fatfs/src/ff.c **** if (!(fp->flag & FA_WRITE)) /* Check access mode */ - 5176 .loc 1 2561 0 - 5177 0028 13F0020F tst r3, #2 - 5178 002c 00F0CA80 beq .L537 -2562:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, FR_DENIED); -2563:../../../Source/third_party/fatfs/src/ff.c **** if ((DWORD)(fp->fsize + btw) < fp->fsize) btw = 0; /* File size cannot reach 4GB */ - 5179 .loc 1 2563 0 - 5180 0030 E368 ldr r3, [r4, #12] - 5181 0032 DE42 cmn r6, r3 - 5182 0034 80F0B880 bcs .L516 -2564:../../../Source/third_party/fatfs/src/ff.c **** -2565:../../../Source/third_party/fatfs/src/ff.c **** for ( ; btw; /* Repeat until all data written */ - 5183 .loc 1 2565 0 - 5184 0038 002E cmp r6, #0 - 5185 003a 00F0B580 beq .L516 -2566:../../../Source/third_party/fatfs/src/ff.c **** wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { -2567:../../../Source/third_party/fatfs/src/ff.c **** if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ -2568:../../../Source/third_party/fatfs/src/ff.c **** csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ -2569:../../../Source/third_party/fatfs/src/ff.c **** if (!csect) { /* On the cluster boundary? */ -2570:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fptr == 0) { /* On the top of the file? */ -2571:../../../Source/third_party/fatfs/src/ff.c **** clst = fp->sclust; /* Follow from the origin */ -2572:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0) /* When no cluster is allocated, */ -2573:../../../Source/third_party/fatfs/src/ff.c **** fp->sclust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */ -2574:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Middle or end of the file */ -2575:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_FASTSEEK -2576:../../../Source/third_party/fatfs/src/ff.c **** if (fp->cltbl) -2577:../../../Source/third_party/fatfs/src/ff.c **** clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ -2578:../../../Source/third_party/fatfs/src/ff.c **** else -2579:../../../Source/third_party/fatfs/src/ff.c **** #endif -2580:../../../Source/third_party/fatfs/src/ff.c **** clst = create_chain(fp->fs, fp->clust); /* Follow or stretch cluster chain on the FAT */ -2581:../../../Source/third_party/fatfs/src/ff.c **** } -2582:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ -2583:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 1) ABORT(fp->fs, FR_INT_ERR); -2584:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); -2585:../../../Source/third_party/fatfs/src/ff.c **** fp->clust = clst; /* Update current cluster */ -2586:../../../Source/third_party/fatfs/src/ff.c **** } -2587:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_TINY -2588:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fs->winsect == fp->dsect && sync_window(fp->fs)) /* Write-back sector cache */ -2589:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); -2590:../../../Source/third_party/fatfs/src/ff.c **** #else -2591:../../../Source/third_party/fatfs/src/ff.c **** if (fp->flag & FA__DIRTY) { /* Write-back sector cache */ -2592:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) -2593:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); -2594:../../../Source/third_party/fatfs/src/ff.c **** fp->flag &= ~FA__DIRTY; -2595:../../../Source/third_party/fatfs/src/ff.c **** } -2596:../../../Source/third_party/fatfs/src/ff.c **** #endif -2597:../../../Source/third_party/fatfs/src/ff.c **** sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ -2598:../../../Source/third_party/fatfs/src/ff.c **** if (!sect) ABORT(fp->fs, FR_INT_ERR); -2599:../../../Source/third_party/fatfs/src/ff.c **** sect += csect; -2600:../../../Source/third_party/fatfs/src/ff.c **** cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ -2601:../../../Source/third_party/fatfs/src/ff.c **** if (cc) { /* Write maximum contiguous sectors directly */ -2602:../../../Source/third_party/fatfs/src/ff.c **** if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ -2603:../../../Source/third_party/fatfs/src/ff.c **** cc = fp->fs->csize - csect; -2604:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK) -2605:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); -2606:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_TINY -2607:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct -2608:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs)); -2609:../../../Source/third_party/fatfs/src/ff.c **** fp->fs->wflag = 0; -2610:../../../Source/third_party/fatfs/src/ff.c **** } -2611:../../../Source/third_party/fatfs/src/ff.c **** #else -2612:../../../Source/third_party/fatfs/src/ff.c **** if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write -2613:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs)); -2614:../../../Source/third_party/fatfs/src/ff.c **** fp->flag &= ~FA__DIRTY; -2615:../../../Source/third_party/fatfs/src/ff.c **** } -2616:../../../Source/third_party/fatfs/src/ff.c **** #endif -2617:../../../Source/third_party/fatfs/src/ff.c **** wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ -2618:../../../Source/third_party/fatfs/src/ff.c **** continue; -2619:../../../Source/third_party/fatfs/src/ff.c **** } -2620:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_TINY -2621:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fptr >= fp->fsize) { /* Avoid silly cache filling at growing edge */ -2622:../../../Source/third_party/fatfs/src/ff.c **** if (sync_window(fp->fs)) ABORT(fp->fs, FR_DISK_ERR); -2623:../../../Source/third_party/fatfs/src/ff.c **** fp->fs->winsect = sect; -2624:../../../Source/third_party/fatfs/src/ff.c **** } -2625:../../../Source/third_party/fatfs/src/ff.c **** #else -2626:../../../Source/third_party/fatfs/src/ff.c **** if (fp->dsect != sect) { /* Fill sector cache with file data */ -2627:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fptr < fp->fsize && -2628:../../../Source/third_party/fatfs/src/ff.c **** disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) - 5186 .loc 1 2628 0 - 5187 003e 04F12403 add r3, r4, #36 - 5188 0042 0193 str r3, [sp, #4] - 5189 .LVL797: - 5190 .L538: -2567:../../../Source/third_party/fatfs/src/ff.c **** csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - 5191 .loc 1 2567 0 - 5192 0044 A368 ldr r3, [r4, #8] - 5193 0046 C3F30802 ubfx r2, r3, #0, #9 - 5194 004a 002A cmp r2, #0 - 5195 004c 40F08E80 bne .L517 -2568:../../../Source/third_party/fatfs/src/ff.c **** if (!csect) { /* On the cluster boundary? */ - 5196 .loc 1 2568 0 - 5197 0050 2068 ldr r0, [r4] - 5198 0052 8778 ldrb r7, [r0, #2] @ zero_extendqisi2 - 5199 0054 013F subs r7, r7, #1 - 5200 0056 07EA5327 and r7, r7, r3, lsr #9 - 5201 .LVL798: -2569:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fptr == 0) { /* On the top of the file? */ - 5202 .loc 1 2569 0 - 5203 005a 17F0FF07 ands r7, r7, #255 - 5204 .LVL799: - 5205 005e 21D1 bne .L518 -2570:../../../Source/third_party/fatfs/src/ff.c **** clst = fp->sclust; /* Follow from the origin */ - 5206 .loc 1 2570 0 - 5207 0060 3BB9 cbnz r3, .L519 -2571:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0) /* When no cluster is allocated, */ - 5208 .loc 1 2571 0 - 5209 0062 2369 ldr r3, [r4, #16] - 5210 .LVL800: -2572:../../../Source/third_party/fatfs/src/ff.c **** fp->sclust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */ - 5211 .loc 1 2572 0 - 5212 0064 63B9 cbnz r3, .L520 -2573:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Middle or end of the file */ - 5213 .loc 1 2573 0 - 5214 0066 0021 movs r1, #0 - 5215 0068 FFF7FEFF bl create_chain - 5216 .LVL801: - 5217 006c 0346 mov r3, r0 - 5218 .LVL802: - 5219 006e 2061 str r0, [r4, #16] - 5220 0070 03E0 b .L521 - 5221 .LVL803: - 5222 .L519: -2580:../../../Source/third_party/fatfs/src/ff.c **** } - 5223 .loc 1 2580 0 - 5224 0072 6169 ldr r1, [r4, #20] - 5225 0074 FFF7FEFF bl create_chain - 5226 .LVL804: - 5227 0078 0346 mov r3, r0 - 5228 .LVL805: - 5229 .L521: -2582:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 1) ABORT(fp->fs, FR_INT_ERR); - 5230 .loc 1 2582 0 - 5231 007a 002B cmp r3, #0 - 5232 007c 00F09480 beq .L516 - 5233 .LVL806: - 5234 .L520: -2583:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - 5235 .loc 1 2583 0 - 5236 0080 012B cmp r3, #1 - 5237 0082 05D1 bne .L522 -2583:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - 5238 .loc 1 2583 0 is_stmt 0 discriminator 1 - 5239 0084 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5240 .LVL807: - 5241 0086 63F07F03 orn r3, r3, #127 - 5242 008a A371 strb r3, [r4, #6] - 5243 008c 0220 movs r0, #2 - 5244 008e 9AE0 b .L515 - 5245 .LVL808: - 5246 .L522: -2584:../../../Source/third_party/fatfs/src/ff.c **** fp->clust = clst; /* Update current cluster */ - 5247 .loc 1 2584 0 is_stmt 1 - 5248 0090 B3F1FF3F cmp r3, #-1 - 5249 0094 05D1 bne .L523 -2584:../../../Source/third_party/fatfs/src/ff.c **** fp->clust = clst; /* Update current cluster */ - 5250 .loc 1 2584 0 is_stmt 0 discriminator 1 - 5251 0096 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5252 .LVL809: - 5253 0098 63F07F03 orn r3, r3, #127 - 5254 009c A371 strb r3, [r4, #6] - 5255 009e 0120 movs r0, #1 - 5256 00a0 91E0 b .L515 - 5257 .LVL810: - 5258 .L523: -2585:../../../Source/third_party/fatfs/src/ff.c **** } - 5259 .loc 1 2585 0 is_stmt 1 - 5260 00a2 6361 str r3, [r4, #20] - 5261 .LVL811: - 5262 .L518: -2591:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - 5263 .loc 1 2591 0 - 5264 00a4 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5265 00a6 13F0400F tst r3, #64 - 5266 00aa 11D0 beq .L524 -2592:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); - 5267 .loc 1 2592 0 - 5268 00ac 2368 ldr r3, [r4] - 5269 00ae 5878 ldrb r0, [r3, #1] @ zero_extendqisi2 - 5270 00b0 0199 ldr r1, [sp, #4] - 5271 00b2 A269 ldr r2, [r4, #24] - 5272 00b4 0123 movs r3, #1 - 5273 00b6 FFF7FEFF bl disk_write - 5274 .LVL812: - 5275 00ba 28B1 cbz r0, .L525 -2593:../../../Source/third_party/fatfs/src/ff.c **** fp->flag &= ~FA__DIRTY; - 5276 .loc 1 2593 0 - 5277 00bc A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5278 00be 63F07F03 orn r3, r3, #127 - 5279 00c2 A371 strb r3, [r4, #6] - 5280 00c4 0120 movs r0, #1 - 5281 00c6 7EE0 b .L515 - 5282 .L525: -2594:../../../Source/third_party/fatfs/src/ff.c **** } - 5283 .loc 1 2594 0 - 5284 00c8 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5285 00ca 23F04003 bic r3, r3, #64 - 5286 00ce A371 strb r3, [r4, #6] - 5287 .L524: -2597:../../../Source/third_party/fatfs/src/ff.c **** if (!sect) ABORT(fp->fs, FR_INT_ERR); - 5288 .loc 1 2597 0 - 5289 00d0 D4F800B0 ldr fp, [r4] - 5290 00d4 5846 mov r0, fp - 5291 00d6 6169 ldr r1, [r4, #20] - 5292 00d8 FFF7FEFF bl clust2sect - 5293 .LVL813: -2598:../../../Source/third_party/fatfs/src/ff.c **** sect += csect; - 5294 .loc 1 2598 0 - 5295 00dc 8246 mov r10, r0 - 5296 00de 28B9 cbnz r0, .L526 -2598:../../../Source/third_party/fatfs/src/ff.c **** sect += csect; - 5297 .loc 1 2598 0 is_stmt 0 discriminator 1 - 5298 00e0 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5299 00e2 63F07F03 orn r3, r3, #127 - 5300 00e6 A371 strb r3, [r4, #6] - 5301 00e8 0220 movs r0, #2 - 5302 .LVL814: - 5303 00ea 6CE0 b .L515 - 5304 .LVL815: - 5305 .L526: -2599:../../../Source/third_party/fatfs/src/ff.c **** cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ - 5306 .loc 1 2599 0 is_stmt 1 - 5307 00ec BA44 add r10, r10, r7 - 5308 .LVL816: -2601:../../../Source/third_party/fatfs/src/ff.c **** if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ - 5309 .loc 1 2601 0 - 5310 00ee 750A lsrs r5, r6, #9 - 5311 .LVL817: - 5312 00f0 25D0 beq .L527 -2602:../../../Source/third_party/fatfs/src/ff.c **** cc = fp->fs->csize - csect; - 5313 .loc 1 2602 0 - 5314 00f2 9BF80230 ldrb r3, [fp, #2] @ zero_extendqisi2 - 5315 00f6 EA19 adds r2, r5, r7 - 5316 00f8 9A42 cmp r2, r3 -2603:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK) - 5317 .loc 1 2603 0 - 5318 00fa 88BF it hi - 5319 00fc DD1B subhi r5, r3, r7 - 5320 .LVL818: -2604:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); - 5321 .loc 1 2604 0 - 5322 00fe 9BF80100 ldrb r0, [fp, #1] @ zero_extendqisi2 - 5323 0102 4946 mov r1, r9 - 5324 0104 5246 mov r2, r10 - 5325 0106 EBB2 uxtb r3, r5 - 5326 0108 FFF7FEFF bl disk_write - 5327 .LVL819: - 5328 010c 28B1 cbz r0, .L529 -2605:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_TINY - 5329 .loc 1 2605 0 - 5330 010e A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5331 0110 63F07F03 orn r3, r3, #127 - 5332 0114 A371 strb r3, [r4, #6] - 5333 0116 0120 movs r0, #1 - 5334 0118 55E0 b .L515 - 5335 .L529: -2612:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs)); - 5336 .loc 1 2612 0 - 5337 011a A169 ldr r1, [r4, #24] - 5338 011c CAEB0101 rsb r1, r10, r1 - 5339 0120 8D42 cmp r5, r1 - 5340 0122 0AD9 bls .L530 -2613:../../../Source/third_party/fatfs/src/ff.c **** fp->flag &= ~FA__DIRTY; - 5341 .loc 1 2613 0 - 5342 0124 0198 ldr r0, [sp, #4] - 5343 0126 09EB4121 add r1, r9, r1, lsl #9 - 5344 012a 4FF40072 mov r2, #512 - 5345 012e FFF7FEFF bl mem_cpy - 5346 .LVL820: -2614:../../../Source/third_party/fatfs/src/ff.c **** } - 5347 .loc 1 2614 0 - 5348 0132 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5349 0134 23F04003 bic r3, r3, #64 - 5350 0138 A371 strb r3, [r4, #6] - 5351 .L530: -2617:../../../Source/third_party/fatfs/src/ff.c **** continue; - 5352 .loc 1 2617 0 - 5353 013a 6D02 lsls r5, r5, #9 - 5354 .LVL821: -2618:../../../Source/third_party/fatfs/src/ff.c **** } - 5355 .loc 1 2618 0 - 5356 013c 28E0 b .L531 - 5357 .LVL822: - 5358 .L527: -2626:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fptr < fp->fsize && - 5359 .loc 1 2626 0 - 5360 013e A369 ldr r3, [r4, #24] - 5361 0140 5345 cmp r3, r10 - 5362 0142 11D0 beq .L532 -2627:../../../Source/third_party/fatfs/src/ff.c **** disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) - 5363 .loc 1 2627 0 - 5364 0144 A268 ldr r2, [r4, #8] - 5365 0146 E368 ldr r3, [r4, #12] - 5366 0148 9A42 cmp r2, r3 - 5367 014a 0DD2 bcs .L532 - 5368 .loc 1 2628 0 discriminator 1 - 5369 014c 9BF80100 ldrb r0, [fp, #1] @ zero_extendqisi2 - 5370 0150 0199 ldr r1, [sp, #4] - 5371 0152 5246 mov r2, r10 - 5372 0154 0123 movs r3, #1 - 5373 0156 FFF7FEFF bl disk_read - 5374 .LVL823: -2627:../../../Source/third_party/fatfs/src/ff.c **** disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) - 5375 .loc 1 2627 0 discriminator 1 - 5376 015a 28B1 cbz r0, .L532 -2629:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); - 5377 .loc 1 2629 0 - 5378 015c A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5379 015e 63F07F03 orn r3, r3, #127 - 5380 0162 A371 strb r3, [r4, #6] - 5381 0164 0120 movs r0, #1 - 5382 0166 2EE0 b .L515 - 5383 .L532: -2630:../../../Source/third_party/fatfs/src/ff.c **** } -2631:../../../Source/third_party/fatfs/src/ff.c **** #endif -2632:../../../Source/third_party/fatfs/src/ff.c **** fp->dsect = sect; - 5384 .loc 1 2632 0 - 5385 0168 C4F818A0 str r10, [r4, #24] - 5386 .LVL824: - 5387 .L517: -2633:../../../Source/third_party/fatfs/src/ff.c **** } -2634:../../../Source/third_party/fatfs/src/ff.c **** wcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */ - 5388 .loc 1 2634 0 - 5389 016c A068 ldr r0, [r4, #8] - 5390 016e C0F30800 ubfx r0, r0, #0, #9 - 5391 0172 C0F50075 rsb r5, r0, #512 - 5392 .LVL825: - 5393 0176 B542 cmp r5, r6 - 5394 0178 28BF it cs - 5395 017a 3546 movcs r5, r6 - 5396 .LVL826: -2635:../../../Source/third_party/fatfs/src/ff.c **** if (wcnt > btw) wcnt = btw; -2636:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_TINY -2637:../../../Source/third_party/fatfs/src/ff.c **** if (move_window(fp->fs, fp->dsect)) /* Move sector window */ -2638:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); -2639:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ -2640:../../../Source/third_party/fatfs/src/ff.c **** fp->fs->wflag = 1; -2641:../../../Source/third_party/fatfs/src/ff.c **** #else -2642:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ - 5397 .loc 1 2642 0 - 5398 017c 2044 add r0, r0, r4 - 5399 017e 2430 adds r0, r0, #36 - 5400 0180 4946 mov r1, r9 - 5401 0182 2A46 mov r2, r5 - 5402 0184 FFF7FEFF bl mem_cpy - 5403 .LVL827: -2643:../../../Source/third_party/fatfs/src/ff.c **** fp->flag |= FA__DIRTY; - 5404 .loc 1 2643 0 - 5405 0188 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5406 018a 43F04003 orr r3, r3, #64 - 5407 018e A371 strb r3, [r4, #6] - 5408 .L531: -2566:../../../Source/third_party/fatfs/src/ff.c **** if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - 5409 .loc 1 2566 0 - 5410 0190 A944 add r9, r9, r5 - 5411 .LVL828: - 5412 0192 A368 ldr r3, [r4, #8] - 5413 0194 2B44 add r3, r3, r5 - 5414 0196 A360 str r3, [r4, #8] - 5415 0198 D8F80030 ldr r3, [r8] - 5416 019c 2B44 add r3, r3, r5 - 5417 019e C8F80030 str r3, [r8] - 5418 .LVL829: -2565:../../../Source/third_party/fatfs/src/ff.c **** wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { - 5419 .loc 1 2565 0 - 5420 01a2 761B subs r6, r6, r5 - 5421 .LVL830: - 5422 01a4 7FF44EAF bne .L538 - 5423 .LVL831: - 5424 .L516: -2644:../../../Source/third_party/fatfs/src/ff.c **** #endif -2645:../../../Source/third_party/fatfs/src/ff.c **** } -2646:../../../Source/third_party/fatfs/src/ff.c **** -2647:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ - 5425 .loc 1 2647 0 - 5426 01a8 A368 ldr r3, [r4, #8] - 5427 01aa E268 ldr r2, [r4, #12] - 5428 01ac 9342 cmp r3, r2 - 5429 01ae 88BF it hi - 5430 01b0 E360 strhi r3, [r4, #12] -2648:../../../Source/third_party/fatfs/src/ff.c **** fp->flag |= FA__WRITTEN; /* Set file change flag */ - 5431 .loc 1 2648 0 - 5432 01b2 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5433 01b4 43F02003 orr r3, r3, #32 - 5434 01b8 A371 strb r3, [r4, #6] -2649:../../../Source/third_party/fatfs/src/ff.c **** -2650:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, FR_OK); - 5435 .loc 1 2650 0 - 5436 01ba 0020 movs r0, #0 - 5437 01bc 03E0 b .L515 - 5438 .LVL832: - 5439 .L535: - 5440 01be 02E0 b .L515 - 5441 .L536: -2560:../../../Source/third_party/fatfs/src/ff.c **** if (!(fp->flag & FA_WRITE)) /* Check access mode */ - 5442 .loc 1 2560 0 - 5443 01c0 0220 movs r0, #2 - 5444 .LVL833: - 5445 01c2 00E0 b .L515 - 5446 .LVL834: - 5447 .L537: -2562:../../../Source/third_party/fatfs/src/ff.c **** if ((DWORD)(fp->fsize + btw) < fp->fsize) btw = 0; /* File size cannot reach 4GB */ - 5448 .loc 1 2562 0 - 5449 01c4 0720 movs r0, #7 - 5450 .LVL835: - 5451 .L515: -2651:../../../Source/third_party/fatfs/src/ff.c **** } - 5452 .loc 1 2651 0 - 5453 01c6 03B0 add sp, sp, #12 - 5454 .cfi_def_cfa_offset 36 - 5455 @ sp needed - 5456 01c8 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} - 5457 .cfi_endproc - 5458 .LFE35: - 5460 .section .text.f_sync,"ax",%progbits - 5461 .align 2 - 5462 .global f_sync - 5463 .thumb - 5464 .thumb_func - 5466 f_sync: - 5467 .LFB36: -2652:../../../Source/third_party/fatfs/src/ff.c **** -2653:../../../Source/third_party/fatfs/src/ff.c **** -2654:../../../Source/third_party/fatfs/src/ff.c **** -2655:../../../Source/third_party/fatfs/src/ff.c **** -2656:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2657:../../../Source/third_party/fatfs/src/ff.c **** /* Synchronize the File Object */ -2658:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2659:../../../Source/third_party/fatfs/src/ff.c **** -2660:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_sync ( -2661:../../../Source/third_party/fatfs/src/ff.c **** FIL *fp /* Pointer to the file object */ -2662:../../../Source/third_party/fatfs/src/ff.c **** ) -2663:../../../Source/third_party/fatfs/src/ff.c **** { - 5468 .loc 1 2663 0 - 5469 .cfi_startproc - 5470 @ args = 0, pretend = 0, frame = 0 - 5471 @ frame_needed = 0, uses_anonymous_args = 0 - 5472 .LVL836: - 5473 0000 38B5 push {r3, r4, r5, lr} - 5474 .cfi_def_cfa_offset 16 - 5475 .cfi_offset 3, -16 - 5476 .cfi_offset 4, -12 - 5477 .cfi_offset 5, -8 - 5478 .cfi_offset 14, -4 - 5479 0002 0446 mov r4, r0 -2664:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -2665:../../../Source/third_party/fatfs/src/ff.c **** DWORD tm; -2666:../../../Source/third_party/fatfs/src/ff.c **** BYTE *dir; -2667:../../../Source/third_party/fatfs/src/ff.c **** -2668:../../../Source/third_party/fatfs/src/ff.c **** -2669:../../../Source/third_party/fatfs/src/ff.c **** res = validate(fp); /* Check validity of the object */ - 5480 .loc 1 2669 0 - 5481 0004 FFF7FEFF bl validate - 5482 .LVL837: -2670:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 5483 .loc 1 2670 0 - 5484 0008 0028 cmp r0, #0 - 5485 000a 49D1 bne .L544 -2671:../../../Source/third_party/fatfs/src/ff.c **** if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ - 5486 .loc 1 2671 0 - 5487 000c A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5488 000e 13F0200F tst r3, #32 - 5489 0012 46D0 beq .L545 -2672:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_TINY /* Write-back dirty buffer */ -2673:../../../Source/third_party/fatfs/src/ff.c **** if (fp->flag & FA__DIRTY) { - 5490 .loc 1 2673 0 - 5491 0014 13F0400F tst r3, #64 - 5492 0018 0DD0 beq .L543 -2674:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - 5493 .loc 1 2674 0 - 5494 001a 2146 mov r1, r4 - 5495 001c 51F8243B ldr r3, [r1], #36 - 5496 0020 5878 ldrb r0, [r3, #1] @ zero_extendqisi2 - 5497 .LVL838: - 5498 0022 A269 ldr r2, [r4, #24] - 5499 0024 0123 movs r3, #1 - 5500 0026 FFF7FEFF bl disk_write - 5501 .LVL839: - 5502 002a 0028 cmp r0, #0 - 5503 002c 3BD1 bne .L546 -2675:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, FR_DISK_ERR); -2676:../../../Source/third_party/fatfs/src/ff.c **** fp->flag &= ~FA__DIRTY; - 5504 .loc 1 2676 0 - 5505 002e A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5506 0030 23F04003 bic r3, r3, #64 - 5507 0034 A371 strb r3, [r4, #6] - 5508 .L543: -2677:../../../Source/third_party/fatfs/src/ff.c **** } -2678:../../../Source/third_party/fatfs/src/ff.c **** #endif -2679:../../../Source/third_party/fatfs/src/ff.c **** /* Update the directory entry */ -2680:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(fp->fs, fp->dir_sect); - 5509 .loc 1 2680 0 - 5510 0036 2068 ldr r0, [r4] - 5511 0038 E169 ldr r1, [r4, #28] - 5512 003a FFF7FEFF bl move_window - 5513 .LVL840: -2681:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 5514 .loc 1 2681 0 - 5515 003e 0028 cmp r0, #0 - 5516 0040 33D1 bne .L547 -2682:../../../Source/third_party/fatfs/src/ff.c **** dir = fp->dir_ptr; - 5517 .loc 1 2682 0 - 5518 0042 256A ldr r5, [r4, #32] - 5519 .LVL841: -2683:../../../Source/third_party/fatfs/src/ff.c **** dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ - 5520 .loc 1 2683 0 - 5521 0044 EB7A ldrb r3, [r5, #11] @ zero_extendqisi2 - 5522 0046 43F02003 orr r3, r3, #32 - 5523 004a EB72 strb r3, [r5, #11] -2684:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */ - 5524 .loc 1 2684 0 - 5525 004c E368 ldr r3, [r4, #12] - 5526 004e 2B77 strb r3, [r5, #28] - 5527 0050 A389 ldrh r3, [r4, #12] - 5528 0052 1B0A lsrs r3, r3, #8 - 5529 0054 6B77 strb r3, [r5, #29] - 5530 0056 E389 ldrh r3, [r4, #14] - 5531 0058 AB77 strb r3, [r5, #30] - 5532 005a E37B ldrb r3, [r4, #15] @ zero_extendqisi2 - 5533 005c EB77 strb r3, [r5, #31] -2685:../../../Source/third_party/fatfs/src/ff.c **** st_clust(dir, fp->sclust); /* Update start cluster */ - 5534 .loc 1 2685 0 - 5535 005e 2369 ldr r3, [r4, #16] - 5536 .LVL842: - 5537 .LBB72: - 5538 .LBB73: -1261:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+DIR_FstClusHI, cl >> 16); - 5539 .loc 1 1261 0 - 5540 0060 AB76 strb r3, [r5, #26] - 5541 0062 C3F30722 ubfx r2, r3, #8, #8 - 5542 0066 EA76 strb r2, [r5, #27] -1262:../../../Source/third_party/fatfs/src/ff.c **** } - 5543 .loc 1 1262 0 - 5544 0068 1B0C lsrs r3, r3, #16 - 5545 .LVL843: - 5546 006a 2B75 strb r3, [r5, #20] - 5547 006c 1B0A lsrs r3, r3, #8 - 5548 006e 6B75 strb r3, [r5, #21] - 5549 .LBE73: - 5550 .LBE72: -2686:../../../Source/third_party/fatfs/src/ff.c **** tm = get_fattime(); /* Update updated time */ - 5551 .loc 1 2686 0 - 5552 0070 FFF7FEFF bl get_fattime - 5553 .LVL844: -2687:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(dir+DIR_WrtTime, tm); - 5554 .loc 1 2687 0 - 5555 0074 A875 strb r0, [r5, #22] - 5556 0076 C0F30723 ubfx r3, r0, #8, #8 - 5557 007a EB75 strb r3, [r5, #23] - 5558 007c 030C lsrs r3, r0, #16 - 5559 007e 2B76 strb r3, [r5, #24] - 5560 0080 000E lsrs r0, r0, #24 - 5561 .LVL845: - 5562 0082 6876 strb r0, [r5, #25] -2688:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+DIR_LstAccDate, 0); - 5563 .loc 1 2688 0 - 5564 0084 0023 movs r3, #0 - 5565 0086 AB74 strb r3, [r5, #18] - 5566 0088 EB74 strb r3, [r5, #19] -2689:../../../Source/third_party/fatfs/src/ff.c **** fp->flag &= ~FA__WRITTEN; - 5567 .loc 1 2689 0 - 5568 008a A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5569 008c 23F02003 bic r3, r3, #32 - 5570 0090 A371 strb r3, [r4, #6] -2690:../../../Source/third_party/fatfs/src/ff.c **** fp->fs->wflag = 1; - 5571 .loc 1 2690 0 - 5572 0092 2368 ldr r3, [r4] - 5573 0094 0122 movs r2, #1 - 5574 0096 1A71 strb r2, [r3, #4] -2691:../../../Source/third_party/fatfs/src/ff.c **** res = sync_fs(fp->fs); - 5575 .loc 1 2691 0 - 5576 0098 2068 ldr r0, [r4] - 5577 009a FFF7FEFF bl sync_fs - 5578 .LVL846: - 5579 009e 38BD pop {r3, r4, r5, pc} - 5580 .LVL847: - 5581 .L544: - 5582 00a0 38BD pop {r3, r4, r5, pc} - 5583 .LVL848: - 5584 .L545: -2669:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 5585 .loc 1 2669 0 - 5586 00a2 0020 movs r0, #0 - 5587 .LVL849: - 5588 00a4 38BD pop {r3, r4, r5, pc} - 5589 .LVL850: - 5590 .L546: -2675:../../../Source/third_party/fatfs/src/ff.c **** fp->flag &= ~FA__DIRTY; - 5591 .loc 1 2675 0 - 5592 00a6 0120 movs r0, #1 - 5593 00a8 38BD pop {r3, r4, r5, pc} - 5594 .LVL851: - 5595 .L547: -2692:../../../Source/third_party/fatfs/src/ff.c **** } -2693:../../../Source/third_party/fatfs/src/ff.c **** } -2694:../../../Source/third_party/fatfs/src/ff.c **** } -2695:../../../Source/third_party/fatfs/src/ff.c **** -2696:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, res); -2697:../../../Source/third_party/fatfs/src/ff.c **** } - 5596 .loc 1 2697 0 - 5597 00aa 38BD pop {r3, r4, r5, pc} - 5598 .cfi_endproc - 5599 .LFE36: - 5601 .section .text.f_close,"ax",%progbits - 5602 .align 2 - 5603 .global f_close - 5604 .thumb - 5605 .thumb_func - 5607 f_close: - 5608 .LFB37: -2698:../../../Source/third_party/fatfs/src/ff.c **** -2699:../../../Source/third_party/fatfs/src/ff.c **** #endif /* !_FS_READONLY */ -2700:../../../Source/third_party/fatfs/src/ff.c **** -2701:../../../Source/third_party/fatfs/src/ff.c **** -2702:../../../Source/third_party/fatfs/src/ff.c **** -2703:../../../Source/third_party/fatfs/src/ff.c **** -2704:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2705:../../../Source/third_party/fatfs/src/ff.c **** /* Close File */ -2706:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2707:../../../Source/third_party/fatfs/src/ff.c **** -2708:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_close ( -2709:../../../Source/third_party/fatfs/src/ff.c **** FIL *fp /* Pointer to the file object to be closed */ -2710:../../../Source/third_party/fatfs/src/ff.c **** ) -2711:../../../Source/third_party/fatfs/src/ff.c **** { - 5609 .loc 1 2711 0 - 5610 .cfi_startproc - 5611 @ args = 0, pretend = 0, frame = 0 - 5612 @ frame_needed = 0, uses_anonymous_args = 0 - 5613 .LVL852: - 5614 0000 10B5 push {r4, lr} - 5615 .cfi_def_cfa_offset 8 - 5616 .cfi_offset 4, -8 - 5617 .cfi_offset 14, -4 - 5618 0002 0446 mov r4, r0 -2712:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -2713:../../../Source/third_party/fatfs/src/ff.c **** -2714:../../../Source/third_party/fatfs/src/ff.c **** -2715:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_READONLY -2716:../../../Source/third_party/fatfs/src/ff.c **** res = validate(fp); -2717:../../../Source/third_party/fatfs/src/ff.c **** { -2718:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_REENTRANT -2719:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs = fp->fs; -2720:../../../Source/third_party/fatfs/src/ff.c **** #endif -2721:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) fp->fs = 0; /* Discard file object */ -2722:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fs, res); -2723:../../../Source/third_party/fatfs/src/ff.c **** } -2724:../../../Source/third_party/fatfs/src/ff.c **** #else -2725:../../../Source/third_party/fatfs/src/ff.c **** res = f_sync(fp); /* Flush cached data */ - 5619 .loc 1 2725 0 - 5620 0004 FFF7FEFF bl f_sync - 5621 .LVL853: -2726:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_LOCK -2727:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { /* Decrement open counter */ -2728:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_REENTRANT -2729:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs = fp->fs;; -2730:../../../Source/third_party/fatfs/src/ff.c **** res = validate(fp); -2731:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -2732:../../../Source/third_party/fatfs/src/ff.c **** res = dec_lock(fp->lockid); -2733:../../../Source/third_party/fatfs/src/ff.c **** unlock_fs(fs, FR_OK); -2734:../../../Source/third_party/fatfs/src/ff.c **** } -2735:../../../Source/third_party/fatfs/src/ff.c **** #else -2736:../../../Source/third_party/fatfs/src/ff.c **** res = dec_lock(fp->lockid); -2737:../../../Source/third_party/fatfs/src/ff.c **** #endif -2738:../../../Source/third_party/fatfs/src/ff.c **** } -2739:../../../Source/third_party/fatfs/src/ff.c **** #endif -2740:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) fp->fs = 0; /* Discard file object */ - 5622 .loc 1 2740 0 - 5623 0008 0346 mov r3, r0 - 5624 000a 08B9 cbnz r0, .L550 - 5625 .loc 1 2740 0 is_stmt 0 discriminator 1 - 5626 000c 0022 movs r2, #0 - 5627 000e 2260 str r2, [r4] - 5628 .L550: -2741:../../../Source/third_party/fatfs/src/ff.c **** return res; -2742:../../../Source/third_party/fatfs/src/ff.c **** #endif -2743:../../../Source/third_party/fatfs/src/ff.c **** } - 5629 .loc 1 2743 0 is_stmt 1 - 5630 0010 1846 mov r0, r3 - 5631 .LVL854: - 5632 0012 10BD pop {r4, pc} - 5633 .cfi_endproc - 5634 .LFE37: - 5636 .section .text.f_lseek,"ax",%progbits - 5637 .align 2 - 5638 .global f_lseek - 5639 .thumb - 5640 .thumb_func - 5642 f_lseek: - 5643 .LFB38: -2744:../../../Source/third_party/fatfs/src/ff.c **** -2745:../../../Source/third_party/fatfs/src/ff.c **** -2746:../../../Source/third_party/fatfs/src/ff.c **** -2747:../../../Source/third_party/fatfs/src/ff.c **** -2748:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2749:../../../Source/third_party/fatfs/src/ff.c **** /* Current Drive/Directory Handlings */ -2750:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2751:../../../Source/third_party/fatfs/src/ff.c **** -2752:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_RPATH >= 1 -2753:../../../Source/third_party/fatfs/src/ff.c **** -2754:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_chdrive ( -2755:../../../Source/third_party/fatfs/src/ff.c **** BYTE drv /* Drive number */ -2756:../../../Source/third_party/fatfs/src/ff.c **** ) -2757:../../../Source/third_party/fatfs/src/ff.c **** { -2758:../../../Source/third_party/fatfs/src/ff.c **** if (drv >= _VOLUMES) return FR_INVALID_DRIVE; -2759:../../../Source/third_party/fatfs/src/ff.c **** -2760:../../../Source/third_party/fatfs/src/ff.c **** CurrVol = drv; -2761:../../../Source/third_party/fatfs/src/ff.c **** -2762:../../../Source/third_party/fatfs/src/ff.c **** return FR_OK; -2763:../../../Source/third_party/fatfs/src/ff.c **** } -2764:../../../Source/third_party/fatfs/src/ff.c **** -2765:../../../Source/third_party/fatfs/src/ff.c **** -2766:../../../Source/third_party/fatfs/src/ff.c **** -2767:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_chdir ( -2768:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *path /* Pointer to the directory path */ -2769:../../../Source/third_party/fatfs/src/ff.c **** ) -2770:../../../Source/third_party/fatfs/src/ff.c **** { -2771:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -2772:../../../Source/third_party/fatfs/src/ff.c **** DIR dj; -2773:../../../Source/third_party/fatfs/src/ff.c **** DEF_NAMEBUF; -2774:../../../Source/third_party/fatfs/src/ff.c **** -2775:../../../Source/third_party/fatfs/src/ff.c **** -2776:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&path, &dj.fs, 0); -2777:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -2778:../../../Source/third_party/fatfs/src/ff.c **** INIT_BUF(dj); -2779:../../../Source/third_party/fatfs/src/ff.c **** res = follow_path(&dj, path); /* Follow the path */ -2780:../../../Source/third_party/fatfs/src/ff.c **** FREE_BUF(); -2781:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { /* Follow completed */ -2782:../../../Source/third_party/fatfs/src/ff.c **** if (!dj.dir) { -2783:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->cdir = dj.sclust; /* Start directory itself */ -2784:../../../Source/third_party/fatfs/src/ff.c **** } else { -2785:../../../Source/third_party/fatfs/src/ff.c **** if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */ -2786:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->cdir = ld_clust(dj.fs, dj.dir); -2787:../../../Source/third_party/fatfs/src/ff.c **** else -2788:../../../Source/third_party/fatfs/src/ff.c **** res = FR_NO_PATH; /* Reached but a file */ -2789:../../../Source/third_party/fatfs/src/ff.c **** } -2790:../../../Source/third_party/fatfs/src/ff.c **** } -2791:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) res = FR_NO_PATH; -2792:../../../Source/third_party/fatfs/src/ff.c **** } -2793:../../../Source/third_party/fatfs/src/ff.c **** -2794:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(dj.fs, res); -2795:../../../Source/third_party/fatfs/src/ff.c **** } -2796:../../../Source/third_party/fatfs/src/ff.c **** -2797:../../../Source/third_party/fatfs/src/ff.c **** -2798:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_RPATH >= 2 -2799:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_getcwd ( -2800:../../../Source/third_party/fatfs/src/ff.c **** TCHAR *buff, /* Pointer to the directory path */ -2801:../../../Source/third_party/fatfs/src/ff.c **** UINT len /* Size of path */ -2802:../../../Source/third_party/fatfs/src/ff.c **** ) -2803:../../../Source/third_party/fatfs/src/ff.c **** { -2804:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -2805:../../../Source/third_party/fatfs/src/ff.c **** DIR dj; -2806:../../../Source/third_party/fatfs/src/ff.c **** UINT i, n; -2807:../../../Source/third_party/fatfs/src/ff.c **** DWORD ccl; -2808:../../../Source/third_party/fatfs/src/ff.c **** TCHAR *tp; -2809:../../../Source/third_party/fatfs/src/ff.c **** FILINFO fno; -2810:../../../Source/third_party/fatfs/src/ff.c **** DEF_NAMEBUF; -2811:../../../Source/third_party/fatfs/src/ff.c **** -2812:../../../Source/third_party/fatfs/src/ff.c **** -2813:../../../Source/third_party/fatfs/src/ff.c **** *buff = 0; -2814:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted((const TCHAR**)&buff, &dj.fs, 0); /* Get current volume */ -2815:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -2816:../../../Source/third_party/fatfs/src/ff.c **** INIT_BUF(dj); -2817:../../../Source/third_party/fatfs/src/ff.c **** i = len; /* Bottom of buffer (dir stack base) */ -2818:../../../Source/third_party/fatfs/src/ff.c **** dj.sclust = dj.fs->cdir; /* Start to follow upper dir from current dir */ -2819:../../../Source/third_party/fatfs/src/ff.c **** while ((ccl = dj.sclust) != 0) { /* Repeat while current dir is a sub-dir */ -2820:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(&dj, 1); /* Get parent dir */ -2821:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -2822:../../../Source/third_party/fatfs/src/ff.c **** res = dir_read(&dj, 0); -2823:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -2824:../../../Source/third_party/fatfs/src/ff.c **** dj.sclust = ld_clust(dj.fs, dj.dir); /* Goto parent dir */ -2825:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(&dj, 0); -2826:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -2827:../../../Source/third_party/fatfs/src/ff.c **** do { /* Find the entry links to the child dir */ -2828:../../../Source/third_party/fatfs/src/ff.c **** res = dir_read(&dj, 0); -2829:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -2830:../../../Source/third_party/fatfs/src/ff.c **** if (ccl == ld_clust(dj.fs, dj.dir)) break; /* Found the entry */ -2831:../../../Source/third_party/fatfs/src/ff.c **** res = dir_next(&dj, 0); -2832:../../../Source/third_party/fatfs/src/ff.c **** } while (res == FR_OK); -2833:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ -2834:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -2835:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN -2836:../../../Source/third_party/fatfs/src/ff.c **** fno.lfname = buff; -2837:../../../Source/third_party/fatfs/src/ff.c **** fno.lfsize = i; -2838:../../../Source/third_party/fatfs/src/ff.c **** #endif -2839:../../../Source/third_party/fatfs/src/ff.c **** get_fileinfo(&dj, &fno); /* Get the dir name and push it to the buffer */ -2840:../../../Source/third_party/fatfs/src/ff.c **** tp = fno.fname; -2841:../../../Source/third_party/fatfs/src/ff.c **** if (_USE_LFN && *buff) tp = buff; -2842:../../../Source/third_party/fatfs/src/ff.c **** for (n = 0; tp[n]; n++) ; -2843:../../../Source/third_party/fatfs/src/ff.c **** if (i < n + 3) { -2844:../../../Source/third_party/fatfs/src/ff.c **** res = FR_NOT_ENOUGH_CORE; break; -2845:../../../Source/third_party/fatfs/src/ff.c **** } -2846:../../../Source/third_party/fatfs/src/ff.c **** while (n) buff[--i] = tp[--n]; -2847:../../../Source/third_party/fatfs/src/ff.c **** buff[--i] = '/'; -2848:../../../Source/third_party/fatfs/src/ff.c **** } -2849:../../../Source/third_party/fatfs/src/ff.c **** tp = buff; -2850:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -2851:../../../Source/third_party/fatfs/src/ff.c **** *tp++ = '0' + CurrVol; /* Put drive number */ -2852:../../../Source/third_party/fatfs/src/ff.c **** *tp++ = ':'; -2853:../../../Source/third_party/fatfs/src/ff.c **** if (i == len) { /* Root-dir */ -2854:../../../Source/third_party/fatfs/src/ff.c **** *tp++ = '/'; -2855:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Sub-dir */ -2856:../../../Source/third_party/fatfs/src/ff.c **** do /* Add stacked path str */ -2857:../../../Source/third_party/fatfs/src/ff.c **** *tp++ = buff[i++]; -2858:../../../Source/third_party/fatfs/src/ff.c **** while (i < len); -2859:../../../Source/third_party/fatfs/src/ff.c **** } -2860:../../../Source/third_party/fatfs/src/ff.c **** } -2861:../../../Source/third_party/fatfs/src/ff.c **** *tp = 0; -2862:../../../Source/third_party/fatfs/src/ff.c **** FREE_BUF(); -2863:../../../Source/third_party/fatfs/src/ff.c **** } -2864:../../../Source/third_party/fatfs/src/ff.c **** -2865:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(dj.fs, res); -2866:../../../Source/third_party/fatfs/src/ff.c **** } -2867:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _FS_RPATH >= 2 */ -2868:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _FS_RPATH >= 1 */ -2869:../../../Source/third_party/fatfs/src/ff.c **** -2870:../../../Source/third_party/fatfs/src/ff.c **** -2871:../../../Source/third_party/fatfs/src/ff.c **** -2872:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_MINIMIZE <= 2 -2873:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2874:../../../Source/third_party/fatfs/src/ff.c **** /* Seek File R/W Pointer */ -2875:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -2876:../../../Source/third_party/fatfs/src/ff.c **** -2877:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_lseek ( -2878:../../../Source/third_party/fatfs/src/ff.c **** FIL *fp, /* Pointer to the file object */ -2879:../../../Source/third_party/fatfs/src/ff.c **** DWORD ofs /* File pointer from top of file */ -2880:../../../Source/third_party/fatfs/src/ff.c **** ) -2881:../../../Source/third_party/fatfs/src/ff.c **** { - 5644 .loc 1 2881 0 - 5645 .cfi_startproc - 5646 @ args = 0, pretend = 0, frame = 0 - 5647 @ frame_needed = 0, uses_anonymous_args = 0 - 5648 .LVL855: - 5649 0000 70B5 push {r4, r5, r6, lr} - 5650 .cfi_def_cfa_offset 16 - 5651 .cfi_offset 4, -16 - 5652 .cfi_offset 5, -12 - 5653 .cfi_offset 6, -8 - 5654 .cfi_offset 14, -4 - 5655 0002 0446 mov r4, r0 - 5656 0004 0D46 mov r5, r1 -2882:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -2883:../../../Source/third_party/fatfs/src/ff.c **** -2884:../../../Source/third_party/fatfs/src/ff.c **** -2885:../../../Source/third_party/fatfs/src/ff.c **** res = validate(fp); /* Check validity of the object */ - 5657 .loc 1 2885 0 - 5658 0006 FFF7FEFF bl validate - 5659 .LVL856: -2886:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) LEAVE_FF(fp->fs, res); - 5660 .loc 1 2886 0 - 5661 000a 0028 cmp r0, #0 - 5662 000c 40F0BC80 bne .L573 -2887:../../../Source/third_party/fatfs/src/ff.c **** if (fp->flag & FA__ERROR) /* Check abort flag */ - 5663 .loc 1 2887 0 - 5664 0010 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5665 0012 13F0800F tst r3, #128 - 5666 0016 40F0B880 bne .L574 - 5667 .LBB74: -2888:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, FR_INT_ERR); -2889:../../../Source/third_party/fatfs/src/ff.c **** -2890:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_FASTSEEK -2891:../../../Source/third_party/fatfs/src/ff.c **** if (fp->cltbl) { /* Fast seek */ -2892:../../../Source/third_party/fatfs/src/ff.c **** DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl; -2893:../../../Source/third_party/fatfs/src/ff.c **** -2894:../../../Source/third_party/fatfs/src/ff.c **** if (ofs == CREATE_LINKMAP) { /* Create CLMT */ -2895:../../../Source/third_party/fatfs/src/ff.c **** tbl = fp->cltbl; -2896:../../../Source/third_party/fatfs/src/ff.c **** tlen = *tbl++; ulen = 2; /* Given table size and required table size */ -2897:../../../Source/third_party/fatfs/src/ff.c **** cl = fp->sclust; /* Top of the chain */ -2898:../../../Source/third_party/fatfs/src/ff.c **** if (cl) { -2899:../../../Source/third_party/fatfs/src/ff.c **** do { -2900:../../../Source/third_party/fatfs/src/ff.c **** /* Get a fragment */ -2901:../../../Source/third_party/fatfs/src/ff.c **** tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ -2902:../../../Source/third_party/fatfs/src/ff.c **** do { -2903:../../../Source/third_party/fatfs/src/ff.c **** pcl = cl; ncl++; -2904:../../../Source/third_party/fatfs/src/ff.c **** cl = get_fat(fp->fs, cl); -2905:../../../Source/third_party/fatfs/src/ff.c **** if (cl <= 1) ABORT(fp->fs, FR_INT_ERR); -2906:../../../Source/third_party/fatfs/src/ff.c **** if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); -2907:../../../Source/third_party/fatfs/src/ff.c **** } while (cl == pcl + 1); -2908:../../../Source/third_party/fatfs/src/ff.c **** if (ulen <= tlen) { /* Store the length and top of the fragment */ -2909:../../../Source/third_party/fatfs/src/ff.c **** *tbl++ = ncl; *tbl++ = tcl; -2910:../../../Source/third_party/fatfs/src/ff.c **** } -2911:../../../Source/third_party/fatfs/src/ff.c **** } while (cl < fp->fs->n_fatent); /* Repeat until end of chain */ -2912:../../../Source/third_party/fatfs/src/ff.c **** } -2913:../../../Source/third_party/fatfs/src/ff.c **** *fp->cltbl = ulen; /* Number of items used */ -2914:../../../Source/third_party/fatfs/src/ff.c **** if (ulen <= tlen) -2915:../../../Source/third_party/fatfs/src/ff.c **** *tbl = 0; /* Terminate table */ -2916:../../../Source/third_party/fatfs/src/ff.c **** else -2917:../../../Source/third_party/fatfs/src/ff.c **** res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ -2918:../../../Source/third_party/fatfs/src/ff.c **** -2919:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Fast seek */ -2920:../../../Source/third_party/fatfs/src/ff.c **** if (ofs > fp->fsize) /* Clip offset at the file size */ -2921:../../../Source/third_party/fatfs/src/ff.c **** ofs = fp->fsize; -2922:../../../Source/third_party/fatfs/src/ff.c **** fp->fptr = ofs; /* Set file pointer */ -2923:../../../Source/third_party/fatfs/src/ff.c **** if (ofs) { -2924:../../../Source/third_party/fatfs/src/ff.c **** fp->clust = clmt_clust(fp, ofs - 1); -2925:../../../Source/third_party/fatfs/src/ff.c **** dsc = clust2sect(fp->fs, fp->clust); -2926:../../../Source/third_party/fatfs/src/ff.c **** if (!dsc) ABORT(fp->fs, FR_INT_ERR); -2927:../../../Source/third_party/fatfs/src/ff.c **** dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1); -2928:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) { /* Refill sector cache if needed */ -2929:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_TINY -2930:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -2931:../../../Source/third_party/fatfs/src/ff.c **** if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ -2932:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) -2933:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); -2934:../../../Source/third_party/fatfs/src/ff.c **** fp->flag &= ~FA__DIRTY; -2935:../../../Source/third_party/fatfs/src/ff.c **** } -2936:../../../Source/third_party/fatfs/src/ff.c **** #endif -2937:../../../Source/third_party/fatfs/src/ff.c **** if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK) /* Load current sector */ -2938:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); -2939:../../../Source/third_party/fatfs/src/ff.c **** #endif -2940:../../../Source/third_party/fatfs/src/ff.c **** fp->dsect = dsc; -2941:../../../Source/third_party/fatfs/src/ff.c **** } -2942:../../../Source/third_party/fatfs/src/ff.c **** } -2943:../../../Source/third_party/fatfs/src/ff.c **** } -2944:../../../Source/third_party/fatfs/src/ff.c **** } else -2945:../../../Source/third_party/fatfs/src/ff.c **** #endif -2946:../../../Source/third_party/fatfs/src/ff.c **** -2947:../../../Source/third_party/fatfs/src/ff.c **** /* Normal Seek */ -2948:../../../Source/third_party/fatfs/src/ff.c **** { -2949:../../../Source/third_party/fatfs/src/ff.c **** DWORD clst, bcs, nsect, ifptr; -2950:../../../Source/third_party/fatfs/src/ff.c **** -2951:../../../Source/third_party/fatfs/src/ff.c **** if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ - 5668 .loc 1 2951 0 - 5669 001a E268 ldr r2, [r4, #12] - 5670 001c AA42 cmp r2, r5 - 5671 001e 05D2 bcs .L554 -2952:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -2953:../../../Source/third_party/fatfs/src/ff.c **** && !(fp->flag & FA_WRITE) - 5672 .loc 1 2953 0 - 5673 0020 03F00203 and r3, r3, #2 - 5674 0024 DBB2 uxtb r3, r3 -2954:../../../Source/third_party/fatfs/src/ff.c **** #endif -2955:../../../Source/third_party/fatfs/src/ff.c **** ) ofs = fp->fsize; - 5675 .loc 1 2955 0 - 5676 0026 002B cmp r3, #0 - 5677 0028 08BF it eq - 5678 002a 1546 moveq r5, r2 - 5679 .LVL857: - 5680 .L554: -2956:../../../Source/third_party/fatfs/src/ff.c **** -2957:../../../Source/third_party/fatfs/src/ff.c **** ifptr = fp->fptr; - 5681 .loc 1 2957 0 - 5682 002c A368 ldr r3, [r4, #8] - 5683 .LVL858: -2958:../../../Source/third_party/fatfs/src/ff.c **** fp->fptr = nsect = 0; - 5684 .loc 1 2958 0 - 5685 002e 0022 movs r2, #0 - 5686 0030 A260 str r2, [r4, #8] -2959:../../../Source/third_party/fatfs/src/ff.c **** if (ofs) { - 5687 .loc 1 2959 0 - 5688 0032 002D cmp r5, #0 - 5689 0034 00F0AB80 beq .L575 -2960:../../../Source/third_party/fatfs/src/ff.c **** bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ - 5690 .loc 1 2960 0 - 5691 0038 2068 ldr r0, [r4] - 5692 .LVL859: - 5693 003a 8678 ldrb r6, [r0, #2] @ zero_extendqisi2 - 5694 003c 7602 lsls r6, r6, #9 - 5695 .LVL860: -2961:../../../Source/third_party/fatfs/src/ff.c **** if (ifptr > 0 && - 5696 .loc 1 2961 0 - 5697 003e 6BB1 cbz r3, .L555 -2962:../../../Source/third_party/fatfs/src/ff.c **** (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ - 5698 .loc 1 2962 0 discriminator 1 - 5699 0040 013B subs r3, r3, #1 - 5700 .LVL861: - 5701 0042 6A1E subs r2, r5, #1 - 5702 0044 B2FBF6F2 udiv r2, r2, r6 - 5703 0048 B3FBF6F1 udiv r1, r3, r6 -2961:../../../Source/third_party/fatfs/src/ff.c **** if (ifptr > 0 && - 5704 .loc 1 2961 0 discriminator 1 - 5705 004c 8A42 cmp r2, r1 - 5706 004e 05D3 bcc .L555 -2963:../../../Source/third_party/fatfs/src/ff.c **** fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */ - 5707 .loc 1 2963 0 - 5708 0050 7242 negs r2, r6 - 5709 0052 1340 ands r3, r3, r2 - 5710 .LVL862: - 5711 0054 A360 str r3, [r4, #8] -2964:../../../Source/third_party/fatfs/src/ff.c **** ofs -= fp->fptr; - 5712 .loc 1 2964 0 - 5713 0056 ED1A subs r5, r5, r3 - 5714 .LVL863: -2965:../../../Source/third_party/fatfs/src/ff.c **** clst = fp->clust; - 5715 .loc 1 2965 0 - 5716 0058 6169 ldr r1, [r4, #20] - 5717 .LVL864: - 5718 005a 17E0 b .L556 - 5719 .LVL865: - 5720 .L555: -2966:../../../Source/third_party/fatfs/src/ff.c **** } else { /* When seek to back cluster, */ -2967:../../../Source/third_party/fatfs/src/ff.c **** clst = fp->sclust; /* start from the first cluster */ - 5721 .loc 1 2967 0 - 5722 005c 2169 ldr r1, [r4, #16] - 5723 .LVL866: -2968:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -2969:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0) { /* If no cluster chain, create a new chain */ - 5724 .loc 1 2969 0 - 5725 005e A1B9 cbnz r1, .L557 -2970:../../../Source/third_party/fatfs/src/ff.c **** clst = create_chain(fp->fs, 0); - 5726 .loc 1 2970 0 - 5727 0060 FFF7FEFF bl create_chain - 5728 .LVL867: - 5729 0064 0146 mov r1, r0 - 5730 .LVL868: -2971:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 1) ABORT(fp->fs, FR_INT_ERR); - 5731 .loc 1 2971 0 - 5732 0066 0128 cmp r0, #1 - 5733 0068 05D1 bne .L558 - 5734 .loc 1 2971 0 is_stmt 0 discriminator 1 - 5735 006a A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5736 006c 63F07F03 orn r3, r3, #127 - 5737 0070 A371 strb r3, [r4, #6] - 5738 0072 0220 movs r0, #2 - 5739 .LVL869: - 5740 0074 70BD pop {r4, r5, r6, pc} - 5741 .LVL870: - 5742 .L558: -2972:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - 5743 .loc 1 2972 0 is_stmt 1 - 5744 0076 B0F1FF3F cmp r0, #-1 - 5745 007a 05D1 bne .L559 - 5746 .loc 1 2972 0 is_stmt 0 discriminator 1 - 5747 007c A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5748 007e 63F07F03 orn r3, r3, #127 - 5749 0082 A371 strb r3, [r4, #6] - 5750 0084 0120 movs r0, #1 - 5751 .LVL871: - 5752 0086 70BD pop {r4, r5, r6, pc} - 5753 .LVL872: - 5754 .L559: -2973:../../../Source/third_party/fatfs/src/ff.c **** fp->sclust = clst; - 5755 .loc 1 2973 0 is_stmt 1 - 5756 0088 2061 str r0, [r4, #16] - 5757 .LVL873: - 5758 .L557: -2974:../../../Source/third_party/fatfs/src/ff.c **** } -2975:../../../Source/third_party/fatfs/src/ff.c **** #endif -2976:../../../Source/third_party/fatfs/src/ff.c **** fp->clust = clst; - 5759 .loc 1 2976 0 - 5760 008a 6161 str r1, [r4, #20] - 5761 .L556: -2977:../../../Source/third_party/fatfs/src/ff.c **** } -2978:../../../Source/third_party/fatfs/src/ff.c **** if (clst != 0) { - 5762 .loc 1 2978 0 - 5763 008c 0029 cmp r1, #0 - 5764 008e 40D0 beq .L576 -2979:../../../Source/third_party/fatfs/src/ff.c **** while (ofs > bcs) { /* Cluster following loop */ - 5765 .loc 1 2979 0 - 5766 0090 B542 cmp r5, r6 - 5767 0092 2BD9 bls .L561 - 5768 .L580: -2980:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -2981:../../../Source/third_party/fatfs/src/ff.c **** if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ - 5769 .loc 1 2981 0 - 5770 0094 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5771 0096 13F0020F tst r3, #2 - 5772 009a 05D0 beq .L562 -2982:../../../Source/third_party/fatfs/src/ff.c **** clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */ - 5773 .loc 1 2982 0 - 5774 009c 2068 ldr r0, [r4] - 5775 009e FFF7FEFF bl create_chain - 5776 .LVL874: -2983:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0) { /* When disk gets full, clip file size */ - 5777 .loc 1 2983 0 - 5778 00a2 0146 mov r1, r0 - 5779 00a4 20B9 cbnz r0, .L563 - 5780 00a6 20E0 b .L577 - 5781 .LVL875: - 5782 .L562: -2984:../../../Source/third_party/fatfs/src/ff.c **** ofs = bcs; break; -2985:../../../Source/third_party/fatfs/src/ff.c **** } -2986:../../../Source/third_party/fatfs/src/ff.c **** } else -2987:../../../Source/third_party/fatfs/src/ff.c **** #endif -2988:../../../Source/third_party/fatfs/src/ff.c **** clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */ - 5783 .loc 1 2988 0 - 5784 00a8 2068 ldr r0, [r4] - 5785 00aa FFF7FEFF bl get_fat - 5786 .LVL876: - 5787 00ae 0146 mov r1, r0 - 5788 .LVL877: - 5789 .L563: -2989:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - 5790 .loc 1 2989 0 - 5791 00b0 B1F1FF3F cmp r1, #-1 - 5792 00b4 05D1 bne .L564 - 5793 .loc 1 2989 0 is_stmt 0 discriminator 1 - 5794 00b6 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5795 00b8 63F07F03 orn r3, r3, #127 - 5796 00bc A371 strb r3, [r4, #6] - 5797 00be 0120 movs r0, #1 - 5798 .LVL878: - 5799 00c0 70BD pop {r4, r5, r6, pc} - 5800 .LVL879: - 5801 .L564: -2990:../../../Source/third_party/fatfs/src/ff.c **** if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR); - 5802 .loc 1 2990 0 is_stmt 1 - 5803 00c2 0129 cmp r1, #1 - 5804 00c4 03D9 bls .L565 - 5805 .loc 1 2990 0 is_stmt 0 discriminator 2 - 5806 00c6 2368 ldr r3, [r4] - 5807 00c8 9B69 ldr r3, [r3, #24] - 5808 00ca 9942 cmp r1, r3 - 5809 00cc 05D3 bcc .L566 - 5810 .L565: - 5811 .loc 1 2990 0 discriminator 3 - 5812 00ce A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5813 00d0 63F07F03 orn r3, r3, #127 - 5814 00d4 A371 strb r3, [r4, #6] - 5815 00d6 0220 movs r0, #2 - 5816 .LVL880: - 5817 00d8 70BD pop {r4, r5, r6, pc} - 5818 .LVL881: - 5819 .L566: -2991:../../../Source/third_party/fatfs/src/ff.c **** fp->clust = clst; - 5820 .loc 1 2991 0 is_stmt 1 - 5821 00da 6161 str r1, [r4, #20] -2992:../../../Source/third_party/fatfs/src/ff.c **** fp->fptr += bcs; - 5822 .loc 1 2992 0 - 5823 00dc A368 ldr r3, [r4, #8] - 5824 00de 3344 add r3, r3, r6 - 5825 00e0 A360 str r3, [r4, #8] -2993:../../../Source/third_party/fatfs/src/ff.c **** ofs -= bcs; - 5826 .loc 1 2993 0 - 5827 00e2 AD1B subs r5, r5, r6 - 5828 .LVL882: -2979:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY - 5829 .loc 1 2979 0 - 5830 00e4 AE42 cmp r6, r5 - 5831 00e6 D5D3 bcc .L580 - 5832 .LVL883: - 5833 00e8 00E0 b .L561 - 5834 .L577: -2984:../../../Source/third_party/fatfs/src/ff.c **** } - 5835 .loc 1 2984 0 - 5836 00ea 3546 mov r5, r6 - 5837 .LVL884: - 5838 .L561: -2994:../../../Source/third_party/fatfs/src/ff.c **** } -2995:../../../Source/third_party/fatfs/src/ff.c **** fp->fptr += ofs; - 5839 .loc 1 2995 0 - 5840 00ec A368 ldr r3, [r4, #8] - 5841 00ee 2B44 add r3, r3, r5 - 5842 00f0 A360 str r3, [r4, #8] -2996:../../../Source/third_party/fatfs/src/ff.c **** if (ofs % SS(fp->fs)) { - 5843 .loc 1 2996 0 - 5844 00f2 C5F30803 ubfx r3, r5, #0, #9 - 5845 00f6 73B1 cbz r3, .L578 -2997:../../../Source/third_party/fatfs/src/ff.c **** nsect = clust2sect(fp->fs, clst); /* Current sector */ - 5846 .loc 1 2997 0 - 5847 00f8 2068 ldr r0, [r4] - 5848 00fa FFF7FEFF bl clust2sect - 5849 .LVL885: -2998:../../../Source/third_party/fatfs/src/ff.c **** if (!nsect) ABORT(fp->fs, FR_INT_ERR); - 5850 .loc 1 2998 0 - 5851 00fe 28B9 cbnz r0, .L568 - 5852 .loc 1 2998 0 is_stmt 0 discriminator 1 - 5853 0100 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5854 0102 63F07F03 orn r3, r3, #127 - 5855 0106 A371 strb r3, [r4, #6] - 5856 0108 0220 movs r0, #2 - 5857 .LVL886: - 5858 010a 70BD pop {r4, r5, r6, pc} - 5859 .LVL887: - 5860 .L568: -2999:../../../Source/third_party/fatfs/src/ff.c **** nsect += ofs / SS(fp->fs); - 5861 .loc 1 2999 0 is_stmt 1 - 5862 010c 00EB5525 add r5, r0, r5, lsr #9 - 5863 .LVL888: - 5864 0110 02E0 b .L560 - 5865 .LVL889: - 5866 .L576: -2958:../../../Source/third_party/fatfs/src/ff.c **** if (ofs) { - 5867 .loc 1 2958 0 - 5868 0112 0025 movs r5, #0 - 5869 .LVL890: - 5870 0114 00E0 b .L560 - 5871 .LVL891: - 5872 .L578: - 5873 0116 0025 movs r5, #0 - 5874 .LVL892: - 5875 .L560: -3000:../../../Source/third_party/fatfs/src/ff.c **** } -3001:../../../Source/third_party/fatfs/src/ff.c **** } -3002:../../../Source/third_party/fatfs/src/ff.c **** } -3003:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { /* Fill sector cache if needed */ - 5876 .loc 1 3003 0 - 5877 0118 A368 ldr r3, [r4, #8] - 5878 011a C3F30803 ubfx r3, r3, #0, #9 - 5879 011e 43B3 cbz r3, .L569 - 5880 .loc 1 3003 0 is_stmt 0 discriminator 1 - 5881 0120 A269 ldr r2, [r4, #24] - 5882 0122 AA42 cmp r2, r5 - 5883 0124 25D0 beq .L569 -3004:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_TINY -3005:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -3006:../../../Source/third_party/fatfs/src/ff.c **** if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ - 5884 .loc 1 3006 0 is_stmt 1 - 5885 0126 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5886 0128 13F0400F tst r3, #64 - 5887 012c 11D0 beq .L570 -3007:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) - 5888 .loc 1 3007 0 - 5889 012e 2146 mov r1, r4 - 5890 0130 51F8243B ldr r3, [r1], #36 - 5891 0134 5878 ldrb r0, [r3, #1] @ zero_extendqisi2 - 5892 0136 0123 movs r3, #1 - 5893 0138 FFF7FEFF bl disk_write - 5894 .LVL893: - 5895 013c 28B1 cbz r0, .L571 -3008:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); - 5896 .loc 1 3008 0 - 5897 013e A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5898 0140 63F07F03 orn r3, r3, #127 - 5899 0144 A371 strb r3, [r4, #6] - 5900 0146 0120 movs r0, #1 - 5901 0148 70BD pop {r4, r5, r6, pc} - 5902 .LVL894: - 5903 .L571: -3009:../../../Source/third_party/fatfs/src/ff.c **** fp->flag &= ~FA__DIRTY; - 5904 .loc 1 3009 0 - 5905 014a A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5906 014c 23F04003 bic r3, r3, #64 - 5907 0150 A371 strb r3, [r4, #6] - 5908 .L570: -3010:../../../Source/third_party/fatfs/src/ff.c **** } -3011:../../../Source/third_party/fatfs/src/ff.c **** #endif -3012:../../../Source/third_party/fatfs/src/ff.c **** if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK) /* Fill sector cache */ - 5909 .loc 1 3012 0 - 5910 0152 2146 mov r1, r4 - 5911 0154 51F8243B ldr r3, [r1], #36 - 5912 0158 5878 ldrb r0, [r3, #1] @ zero_extendqisi2 - 5913 015a 2A46 mov r2, r5 - 5914 015c 0123 movs r3, #1 - 5915 015e FFF7FEFF bl disk_read - 5916 .LVL895: - 5917 0162 28B1 cbz r0, .L572 -3013:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); - 5918 .loc 1 3013 0 - 5919 0164 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5920 0166 63F07F03 orn r3, r3, #127 - 5921 016a A371 strb r3, [r4, #6] - 5922 016c 0120 movs r0, #1 - 5923 016e 70BD pop {r4, r5, r6, pc} - 5924 .LVL896: - 5925 .L572: -3014:../../../Source/third_party/fatfs/src/ff.c **** #endif -3015:../../../Source/third_party/fatfs/src/ff.c **** fp->dsect = nsect; - 5926 .loc 1 3015 0 - 5927 0170 A561 str r5, [r4, #24] - 5928 .L569: -3016:../../../Source/third_party/fatfs/src/ff.c **** } -3017:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -3018:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fptr > fp->fsize) { /* Set file change flag if the file size is extended */ - 5929 .loc 1 3018 0 - 5930 0172 A368 ldr r3, [r4, #8] - 5931 0174 E268 ldr r2, [r4, #12] - 5932 0176 9342 cmp r3, r2 - 5933 0178 0BD9 bls .L579 -3019:../../../Source/third_party/fatfs/src/ff.c **** fp->fsize = fp->fptr; - 5934 .loc 1 3019 0 - 5935 017a E360 str r3, [r4, #12] -3020:../../../Source/third_party/fatfs/src/ff.c **** fp->flag |= FA__WRITTEN; - 5936 .loc 1 3020 0 - 5937 017c A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 5938 017e 43F02003 orr r3, r3, #32 - 5939 0182 A371 strb r3, [r4, #6] - 5940 .LBE74: -3021:../../../Source/third_party/fatfs/src/ff.c **** } -3022:../../../Source/third_party/fatfs/src/ff.c **** #endif -3023:../../../Source/third_party/fatfs/src/ff.c **** } -3024:../../../Source/third_party/fatfs/src/ff.c **** -3025:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, res); - 5941 .loc 1 3025 0 - 5942 0184 0020 movs r0, #0 - 5943 0186 70BD pop {r4, r5, r6, pc} - 5944 .LVL897: - 5945 .L573: - 5946 0188 70BD pop {r4, r5, r6, pc} - 5947 .LVL898: - 5948 .L574: -2888:../../../Source/third_party/fatfs/src/ff.c **** - 5949 .loc 1 2888 0 - 5950 018a 0220 movs r0, #2 - 5951 .LVL899: - 5952 018c 70BD pop {r4, r5, r6, pc} - 5953 .LVL900: - 5954 .L575: - 5955 .loc 1 3025 0 - 5956 018e 0020 movs r0, #0 - 5957 .LVL901: - 5958 0190 70BD pop {r4, r5, r6, pc} - 5959 .LVL902: - 5960 .L579: - 5961 0192 0020 movs r0, #0 -3026:../../../Source/third_party/fatfs/src/ff.c **** } - 5962 .loc 1 3026 0 - 5963 0194 70BD pop {r4, r5, r6, pc} - 5964 .cfi_endproc - 5965 .LFE38: - 5967 0196 00BF .section .text.f_opendir,"ax",%progbits - 5968 .align 2 - 5969 .global f_opendir - 5970 .thumb - 5971 .thumb_func - 5973 f_opendir: - 5974 .LFB39: -3027:../../../Source/third_party/fatfs/src/ff.c **** -3028:../../../Source/third_party/fatfs/src/ff.c **** -3029:../../../Source/third_party/fatfs/src/ff.c **** -3030:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_MINIMIZE <= 1 -3031:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3032:../../../Source/third_party/fatfs/src/ff.c **** /* Create a Directory Object */ -3033:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3034:../../../Source/third_party/fatfs/src/ff.c **** -3035:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_opendir ( -3036:../../../Source/third_party/fatfs/src/ff.c **** DIR *dj, /* Pointer to directory object to create */ -3037:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *path /* Pointer to the directory path */ -3038:../../../Source/third_party/fatfs/src/ff.c **** ) -3039:../../../Source/third_party/fatfs/src/ff.c **** { - 5975 .loc 1 3039 0 - 5976 .cfi_startproc - 5977 @ args = 0, pretend = 0, frame = 24 - 5978 @ frame_needed = 0, uses_anonymous_args = 0 - 5979 .LVL903: - 5980 0000 30B5 push {r4, r5, lr} - 5981 .cfi_def_cfa_offset 12 - 5982 .cfi_offset 4, -12 - 5983 .cfi_offset 5, -8 - 5984 .cfi_offset 14, -4 - 5985 0002 87B0 sub sp, sp, #28 - 5986 .cfi_def_cfa_offset 40 - 5987 0004 0191 str r1, [sp, #4] -3040:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -3041:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs; -3042:../../../Source/third_party/fatfs/src/ff.c **** DEF_NAMEBUF; -3043:../../../Source/third_party/fatfs/src/ff.c **** -3044:../../../Source/third_party/fatfs/src/ff.c **** -3045:../../../Source/third_party/fatfs/src/ff.c **** if (!dj) return FR_INVALID_OBJECT; - 5988 .loc 1 3045 0 - 5989 0006 30B3 cbz r0, .L591 - 5990 0008 0446 mov r4, r0 -3046:../../../Source/third_party/fatfs/src/ff.c **** -3047:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&path, &dj->fs, 0); - 5991 .loc 1 3047 0 - 5992 000a 01A8 add r0, sp, #4 - 5993 .LVL904: - 5994 000c 2146 mov r1, r4 - 5995 .LVL905: - 5996 000e 0022 movs r2, #0 - 5997 0010 FFF7FEFF bl chk_mounted - 5998 .LVL906: -3048:../../../Source/third_party/fatfs/src/ff.c **** fs = dj->fs; - 5999 .loc 1 3048 0 - 6000 0014 2568 ldr r5, [r4] - 6001 .LVL907: -3049:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 6002 .loc 1 3049 0 - 6003 0016 D8B9 cbnz r0, .L585 -3050:../../../Source/third_party/fatfs/src/ff.c **** INIT_BUF(*dj); - 6004 .loc 1 3050 0 - 6005 0018 03AB add r3, sp, #12 - 6006 001a A361 str r3, [r4, #24] - 6007 001c 184B ldr r3, .L597 - 6008 001e E361 str r3, [r4, #28] -3051:../../../Source/third_party/fatfs/src/ff.c **** res = follow_path(dj, path); /* Follow the path to the directory */ - 6009 .loc 1 3051 0 - 6010 0020 2046 mov r0, r4 - 6011 .LVL908: - 6012 0022 0199 ldr r1, [sp, #4] - 6013 0024 FFF7FEFF bl follow_path - 6014 .LVL909: -3052:../../../Source/third_party/fatfs/src/ff.c **** FREE_BUF(); -3053:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { /* Follow completed */ - 6015 .loc 1 3053 0 - 6016 0028 0346 mov r3, r0 - 6017 002a 10BB cbnz r0, .L586 -3054:../../../Source/third_party/fatfs/src/ff.c **** if (dj->dir) { /* It is not the root dir */ - 6018 .loc 1 3054 0 - 6019 002c 6169 ldr r1, [r4, #20] - 6020 002e B1B1 cbz r1, .L587 -3055:../../../Source/third_party/fatfs/src/ff.c **** if (dj->dir[DIR_Attr] & AM_DIR) { /* The object is a directory */ - 6021 .loc 1 3055 0 - 6022 0030 CB7A ldrb r3, [r1, #11] @ zero_extendqisi2 - 6023 0032 13F0100F tst r3, #16 - 6024 0036 06D0 beq .L592 -3056:../../../Source/third_party/fatfs/src/ff.c **** dj->sclust = ld_clust(fs, dj->dir); - 6025 .loc 1 3056 0 - 6026 0038 2846 mov r0, r5 - 6027 .LVL910: - 6028 003a FFF7FEFF bl ld_clust - 6029 .LVL911: - 6030 003e A060 str r0, [r4, #8] - 6031 0040 0DE0 b .L587 - 6032 .LVL912: - 6033 .L595: -3057:../../../Source/third_party/fatfs/src/ff.c **** } else { /* The object is not a directory */ -3058:../../../Source/third_party/fatfs/src/ff.c **** res = FR_NO_PATH; -3059:../../../Source/third_party/fatfs/src/ff.c **** } -3060:../../../Source/third_party/fatfs/src/ff.c **** } -3061:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -3062:../../../Source/third_party/fatfs/src/ff.c **** dj->id = fs->id; -3063:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(dj, 0); /* Rewind dir */ -3064:../../../Source/third_party/fatfs/src/ff.c **** } -3065:../../../Source/third_party/fatfs/src/ff.c **** } -3066:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) res = FR_NO_PATH; -3067:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) dj->fs = 0; /* Invalidate the dir object if function faild */ - 6034 .loc 1 3067 0 - 6035 0042 53B1 cbz r3, .L593 - 6036 0044 00E0 b .L588 - 6037 .LVL913: - 6038 .L592: -3058:../../../Source/third_party/fatfs/src/ff.c **** } - 6039 .loc 1 3058 0 - 6040 0046 0523 movs r3, #5 - 6041 .LVL914: - 6042 .L588: - 6043 .loc 1 3067 0 discriminator 1 - 6044 0048 0022 movs r2, #0 - 6045 004a 2260 str r2, [r4] - 6046 004c 1846 mov r0, r3 - 6047 004e 14E0 b .L594 - 6048 .LVL915: - 6049 .L585: -3068:../../../Source/third_party/fatfs/src/ff.c **** } else { -3069:../../../Source/third_party/fatfs/src/ff.c **** dj->fs = 0; - 6050 .loc 1 3069 0 - 6051 0050 0022 movs r2, #0 - 6052 0052 2260 str r2, [r4] - 6053 0054 11E0 b .L594 - 6054 .LVL916: - 6055 .L591: -3045:../../../Source/third_party/fatfs/src/ff.c **** - 6056 .loc 1 3045 0 - 6057 0056 0920 movs r0, #9 - 6058 .LVL917: - 6059 0058 0FE0 b .L594 - 6060 .LVL918: - 6061 .L593: - 6062 005a 0020 movs r0, #0 - 6063 005c 0DE0 b .L594 - 6064 .LVL919: - 6065 .L587: -3062:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(dj, 0); /* Rewind dir */ - 6066 .loc 1 3062 0 - 6067 005e EB88 ldrh r3, [r5, #6] - 6068 0060 A380 strh r3, [r4, #4] @ movhi -3063:../../../Source/third_party/fatfs/src/ff.c **** } - 6069 .loc 1 3063 0 - 6070 0062 2046 mov r0, r4 - 6071 0064 0021 movs r1, #0 - 6072 0066 FFF7FEFF bl dir_sdi - 6073 .LVL920: - 6074 006a 0346 mov r3, r0 - 6075 .LVL921: -3066:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) dj->fs = 0; /* Invalidate the dir object if function faild */ - 6076 .loc 1 3066 0 - 6077 006c 0428 cmp r0, #4 - 6078 006e E8D1 bne .L595 - 6079 0070 01E0 b .L589 - 6080 .L586: - 6081 0072 0428 cmp r0, #4 - 6082 0074 E8D1 bne .L588 - 6083 .L589: - 6084 .LVL922: -3039:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 6085 .loc 1 3039 0 - 6086 0076 0523 movs r3, #5 - 6087 0078 E6E7 b .L588 - 6088 .LVL923: - 6089 .L594: -3070:../../../Source/third_party/fatfs/src/ff.c **** } -3071:../../../Source/third_party/fatfs/src/ff.c **** -3072:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fs, res); -3073:../../../Source/third_party/fatfs/src/ff.c **** } - 6090 .loc 1 3073 0 - 6091 007a 07B0 add sp, sp, #28 - 6092 .cfi_def_cfa_offset 12 - 6093 @ sp needed - 6094 007c 30BD pop {r4, r5, pc} - 6095 .LVL924: - 6096 .L598: - 6097 007e 00BF .align 2 - 6098 .L597: - 6099 0080 00000000 .word .LANCHOR4 - 6100 .cfi_endproc - 6101 .LFE39: - 6103 .section .text.f_readdir,"ax",%progbits - 6104 .align 2 - 6105 .global f_readdir - 6106 .thumb - 6107 .thumb_func - 6109 f_readdir: - 6110 .LFB40: -3074:../../../Source/third_party/fatfs/src/ff.c **** -3075:../../../Source/third_party/fatfs/src/ff.c **** -3076:../../../Source/third_party/fatfs/src/ff.c **** -3077:../../../Source/third_party/fatfs/src/ff.c **** -3078:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3079:../../../Source/third_party/fatfs/src/ff.c **** /* Read Directory Entry in Sequence */ -3080:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3081:../../../Source/third_party/fatfs/src/ff.c **** -3082:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_readdir ( -3083:../../../Source/third_party/fatfs/src/ff.c **** DIR *dj, /* Pointer to the open directory object */ -3084:../../../Source/third_party/fatfs/src/ff.c **** FILINFO *fno /* Pointer to file information to return */ -3085:../../../Source/third_party/fatfs/src/ff.c **** ) -3086:../../../Source/third_party/fatfs/src/ff.c **** { - 6111 .loc 1 3086 0 - 6112 .cfi_startproc - 6113 @ args = 0, pretend = 0, frame = 16 - 6114 @ frame_needed = 0, uses_anonymous_args = 0 - 6115 .LVL925: - 6116 0000 70B5 push {r4, r5, r6, lr} - 6117 .cfi_def_cfa_offset 16 - 6118 .cfi_offset 4, -16 - 6119 .cfi_offset 5, -12 - 6120 .cfi_offset 6, -8 - 6121 .cfi_offset 14, -4 - 6122 0002 84B0 sub sp, sp, #16 - 6123 .cfi_def_cfa_offset 32 - 6124 0004 0446 mov r4, r0 - 6125 0006 0E46 mov r6, r1 -3087:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -3088:../../../Source/third_party/fatfs/src/ff.c **** DEF_NAMEBUF; -3089:../../../Source/third_party/fatfs/src/ff.c **** -3090:../../../Source/third_party/fatfs/src/ff.c **** -3091:../../../Source/third_party/fatfs/src/ff.c **** res = validate(dj); /* Check validity of the object */ - 6126 .loc 1 3091 0 - 6127 0008 FFF7FEFF bl validate - 6128 .LVL926: -3092:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 6129 .loc 1 3092 0 - 6130 000c 0546 mov r5, r0 - 6131 000e 20BB cbnz r0, .L600 -3093:../../../Source/third_party/fatfs/src/ff.c **** if (!fno) { - 6132 .loc 1 3093 0 - 6133 0010 2EB9 cbnz r6, .L601 -3094:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(dj, 0); /* Rewind the directory object */ - 6134 .loc 1 3094 0 - 6135 0012 2046 mov r0, r4 - 6136 .LVL927: - 6137 0014 0021 movs r1, #0 - 6138 0016 FFF7FEFF bl dir_sdi - 6139 .LVL928: - 6140 001a 0546 mov r5, r0 - 6141 .LVL929: - 6142 001c 1DE0 b .L600 - 6143 .LVL930: - 6144 .L601: -3095:../../../Source/third_party/fatfs/src/ff.c **** } else { -3096:../../../Source/third_party/fatfs/src/ff.c **** INIT_BUF(*dj); - 6145 .loc 1 3096 0 - 6146 001e 01AB add r3, sp, #4 - 6147 0020 A361 str r3, [r4, #24] - 6148 0022 0F4B ldr r3, .L607 - 6149 0024 E361 str r3, [r4, #28] -3097:../../../Source/third_party/fatfs/src/ff.c **** res = dir_read(dj, 0); /* Read an item */ - 6150 .loc 1 3097 0 - 6151 0026 2046 mov r0, r4 - 6152 .LVL931: - 6153 0028 0021 movs r1, #0 - 6154 002a FFF7FEFF bl dir_read - 6155 .LVL932: -3098:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) { /* Reached end of dir */ - 6156 .loc 1 3098 0 - 6157 002e 0428 cmp r0, #4 - 6158 0030 02D1 bne .L602 -3099:../../../Source/third_party/fatfs/src/ff.c **** dj->sect = 0; - 6159 .loc 1 3099 0 - 6160 0032 0023 movs r3, #0 - 6161 0034 2361 str r3, [r4, #16] - 6162 .LVL933: - 6163 0036 00E0 b .L603 - 6164 .LVL934: - 6165 .L602: -3100:../../../Source/third_party/fatfs/src/ff.c **** res = FR_OK; -3101:../../../Source/third_party/fatfs/src/ff.c **** } -3102:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { /* A valid entry is found */ - 6166 .loc 1 3102 0 - 6167 0038 60B9 cbnz r0, .L604 - 6168 .LVL935: - 6169 .L603: -3103:../../../Source/third_party/fatfs/src/ff.c **** get_fileinfo(dj, fno); /* Get the object information */ - 6170 .loc 1 3103 0 - 6171 003a 2046 mov r0, r4 - 6172 003c 3146 mov r1, r6 - 6173 003e FFF7FEFF bl get_fileinfo - 6174 .LVL936: -3104:../../../Source/third_party/fatfs/src/ff.c **** res = dir_next(dj, 0); /* Increment index for next */ - 6175 .loc 1 3104 0 - 6176 0042 2046 mov r0, r4 - 6177 0044 0021 movs r1, #0 - 6178 0046 FFF7FEFF bl dir_next - 6179 .LVL937: -3105:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) { - 6180 .loc 1 3105 0 - 6181 004a 0428 cmp r0, #4 - 6182 004c 04D1 bne .L605 -3106:../../../Source/third_party/fatfs/src/ff.c **** dj->sect = 0; - 6183 .loc 1 3106 0 - 6184 004e 0023 movs r3, #0 - 6185 0050 2361 str r3, [r4, #16] - 6186 .LVL938: - 6187 0052 02E0 b .L600 - 6188 .LVL939: - 6189 .L604: -3097:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) { /* Reached end of dir */ - 6190 .loc 1 3097 0 - 6191 0054 0546 mov r5, r0 - 6192 0056 00E0 b .L600 - 6193 .L605: -3104:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) { - 6194 .loc 1 3104 0 - 6195 0058 0546 mov r5, r0 - 6196 .LVL940: - 6197 .L600: -3107:../../../Source/third_party/fatfs/src/ff.c **** res = FR_OK; -3108:../../../Source/third_party/fatfs/src/ff.c **** } -3109:../../../Source/third_party/fatfs/src/ff.c **** } -3110:../../../Source/third_party/fatfs/src/ff.c **** FREE_BUF(); -3111:../../../Source/third_party/fatfs/src/ff.c **** } -3112:../../../Source/third_party/fatfs/src/ff.c **** } -3113:../../../Source/third_party/fatfs/src/ff.c **** -3114:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(dj->fs, res); -3115:../../../Source/third_party/fatfs/src/ff.c **** } - 6198 .loc 1 3115 0 - 6199 005a 2846 mov r0, r5 - 6200 005c 04B0 add sp, sp, #16 - 6201 .cfi_def_cfa_offset 16 - 6202 @ sp needed - 6203 005e 70BD pop {r4, r5, r6, pc} - 6204 .LVL941: - 6205 .L608: - 6206 .align 2 - 6207 .L607: - 6208 0060 00000000 .word .LANCHOR4 - 6209 .cfi_endproc - 6210 .LFE40: - 6212 .section .text.f_stat,"ax",%progbits - 6213 .align 2 - 6214 .global f_stat - 6215 .thumb - 6216 .thumb_func - 6218 f_stat: - 6219 .LFB41: -3116:../../../Source/third_party/fatfs/src/ff.c **** -3117:../../../Source/third_party/fatfs/src/ff.c **** -3118:../../../Source/third_party/fatfs/src/ff.c **** -3119:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_MINIMIZE == 0 -3120:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3121:../../../Source/third_party/fatfs/src/ff.c **** /* Get File Status */ -3122:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3123:../../../Source/third_party/fatfs/src/ff.c **** -3124:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_stat ( -3125:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *path, /* Pointer to the file path */ -3126:../../../Source/third_party/fatfs/src/ff.c **** FILINFO *fno /* Pointer to file information to return */ -3127:../../../Source/third_party/fatfs/src/ff.c **** ) -3128:../../../Source/third_party/fatfs/src/ff.c **** { - 6220 .loc 1 3128 0 - 6221 .cfi_startproc - 6222 @ args = 0, pretend = 0, frame = 56 - 6223 @ frame_needed = 0, uses_anonymous_args = 0 - 6224 .LVL942: - 6225 0000 30B5 push {r4, r5, lr} - 6226 .cfi_def_cfa_offset 12 - 6227 .cfi_offset 4, -12 - 6228 .cfi_offset 5, -8 - 6229 .cfi_offset 14, -4 - 6230 0002 8FB0 sub sp, sp, #60 - 6231 .cfi_def_cfa_offset 72 - 6232 0004 0EAB add r3, sp, #56 - 6233 0006 43F8340D str r0, [r3, #-52]! - 6234 000a 0D46 mov r5, r1 -3129:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -3130:../../../Source/third_party/fatfs/src/ff.c **** DIR dj; -3131:../../../Source/third_party/fatfs/src/ff.c **** DEF_NAMEBUF; -3132:../../../Source/third_party/fatfs/src/ff.c **** -3133:../../../Source/third_party/fatfs/src/ff.c **** -3134:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&path, &dj.fs, 0); - 6235 .loc 1 3134 0 - 6236 000c 1846 mov r0, r3 - 6237 .LVL943: - 6238 000e 05A9 add r1, sp, #20 - 6239 .LVL944: - 6240 0010 0022 movs r2, #0 - 6241 0012 FFF7FEFF bl chk_mounted - 6242 .LVL945: -3135:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 6243 .loc 1 3135 0 - 6244 0016 0446 mov r4, r0 - 6245 0018 88B9 cbnz r0, .L610 -3136:../../../Source/third_party/fatfs/src/ff.c **** INIT_BUF(dj); - 6246 .loc 1 3136 0 - 6247 001a 02AB add r3, sp, #8 - 6248 001c 0B93 str r3, [sp, #44] - 6249 001e 094B ldr r3, .L613 - 6250 0020 0C93 str r3, [sp, #48] -3137:../../../Source/third_party/fatfs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ - 6251 .loc 1 3137 0 - 6252 0022 05A8 add r0, sp, #20 - 6253 .LVL946: - 6254 0024 0199 ldr r1, [sp, #4] - 6255 0026 FFF7FEFF bl follow_path - 6256 .LVL947: -3138:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { /* Follow completed */ - 6257 .loc 1 3138 0 - 6258 002a 0446 mov r4, r0 - 6259 002c 38B9 cbnz r0, .L610 -3139:../../../Source/third_party/fatfs/src/ff.c **** if (dj.dir) /* Found an object */ - 6260 .loc 1 3139 0 - 6261 002e 0A9B ldr r3, [sp, #40] - 6262 0030 23B1 cbz r3, .L611 -3140:../../../Source/third_party/fatfs/src/ff.c **** get_fileinfo(&dj, fno); - 6263 .loc 1 3140 0 - 6264 0032 05A8 add r0, sp, #20 - 6265 .LVL948: - 6266 0034 2946 mov r1, r5 - 6267 0036 FFF7FEFF bl get_fileinfo - 6268 .LVL949: - 6269 003a 00E0 b .L610 - 6270 .LVL950: - 6271 .L611: -3141:../../../Source/third_party/fatfs/src/ff.c **** else /* It is root dir */ -3142:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INVALID_NAME; - 6272 .loc 1 3142 0 - 6273 003c 0624 movs r4, #6 - 6274 .LVL951: - 6275 .L610: -3143:../../../Source/third_party/fatfs/src/ff.c **** } -3144:../../../Source/third_party/fatfs/src/ff.c **** FREE_BUF(); -3145:../../../Source/third_party/fatfs/src/ff.c **** } -3146:../../../Source/third_party/fatfs/src/ff.c **** -3147:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(dj.fs, res); -3148:../../../Source/third_party/fatfs/src/ff.c **** } - 6276 .loc 1 3148 0 - 6277 003e 2046 mov r0, r4 - 6278 0040 0FB0 add sp, sp, #60 - 6279 .cfi_def_cfa_offset 12 - 6280 @ sp needed - 6281 0042 30BD pop {r4, r5, pc} - 6282 .LVL952: - 6283 .L614: - 6284 .align 2 - 6285 .L613: - 6286 0044 00000000 .word .LANCHOR4 - 6287 .cfi_endproc - 6288 .LFE41: - 6290 .section .text.f_getfree,"ax",%progbits - 6291 .align 2 - 6292 .global f_getfree - 6293 .thumb - 6294 .thumb_func - 6296 f_getfree: - 6297 .LFB42: -3149:../../../Source/third_party/fatfs/src/ff.c **** -3150:../../../Source/third_party/fatfs/src/ff.c **** -3151:../../../Source/third_party/fatfs/src/ff.c **** -3152:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -3153:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3154:../../../Source/third_party/fatfs/src/ff.c **** /* Get Number of Free Clusters */ -3155:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3156:../../../Source/third_party/fatfs/src/ff.c **** -3157:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_getfree ( -3158:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *path, /* Path name of the logical drive number */ -3159:../../../Source/third_party/fatfs/src/ff.c **** DWORD *nclst, /* Pointer to a variable to return number of free clusters */ -3160:../../../Source/third_party/fatfs/src/ff.c **** FATFS **fatfs /* Pointer to return pointer to corresponding file system object */ -3161:../../../Source/third_party/fatfs/src/ff.c **** ) -3162:../../../Source/third_party/fatfs/src/ff.c **** { - 6298 .loc 1 3162 0 - 6299 .cfi_startproc - 6300 @ args = 0, pretend = 0, frame = 8 - 6301 @ frame_needed = 0, uses_anonymous_args = 0 - 6302 .LVL953: - 6303 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} - 6304 .cfi_def_cfa_offset 36 - 6305 .cfi_offset 4, -36 - 6306 .cfi_offset 5, -32 - 6307 .cfi_offset 6, -28 - 6308 .cfi_offset 7, -24 - 6309 .cfi_offset 8, -20 - 6310 .cfi_offset 9, -16 - 6311 .cfi_offset 10, -12 - 6312 .cfi_offset 11, -8 - 6313 .cfi_offset 14, -4 - 6314 0004 83B0 sub sp, sp, #12 - 6315 .cfi_def_cfa_offset 48 - 6316 0006 02AB add r3, sp, #8 - 6317 0008 43F8040D str r0, [r3, #-4]! - 6318 000c 8A46 mov r10, r1 - 6319 000e 1446 mov r4, r2 -3163:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -3164:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs; -3165:../../../Source/third_party/fatfs/src/ff.c **** DWORD n, clst, sect, stat; -3166:../../../Source/third_party/fatfs/src/ff.c **** UINT i; -3167:../../../Source/third_party/fatfs/src/ff.c **** BYTE fat, *p; -3168:../../../Source/third_party/fatfs/src/ff.c **** -3169:../../../Source/third_party/fatfs/src/ff.c **** -3170:../../../Source/third_party/fatfs/src/ff.c **** /* Get drive number */ -3171:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&path, fatfs, 0); - 6320 .loc 1 3171 0 - 6321 0010 1846 mov r0, r3 - 6322 .LVL954: - 6323 0012 1146 mov r1, r2 - 6324 .LVL955: - 6325 0014 0022 movs r2, #0 - 6326 .LVL956: - 6327 0016 FFF7FEFF bl chk_mounted - 6328 .LVL957: -3172:../../../Source/third_party/fatfs/src/ff.c **** fs = *fatfs; - 6329 .loc 1 3172 0 - 6330 001a 2568 ldr r5, [r4] - 6331 .LVL958: -3173:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 6332 .loc 1 3173 0 - 6333 001c 8146 mov r9, r0 - 6334 001e 0028 cmp r0, #0 - 6335 0020 60D1 bne .L633 -3174:../../../Source/third_party/fatfs/src/ff.c **** /* If free_clust is valid, return it without full cluster scan */ -3175:../../../Source/third_party/fatfs/src/ff.c **** if (fs->free_clust <= fs->n_fatent - 2) { - 6336 .loc 1 3175 0 - 6337 0022 2B69 ldr r3, [r5, #16] - 6338 0024 AC69 ldr r4, [r5, #24] - 6339 .LVL959: - 6340 0026 A21E subs r2, r4, #2 - 6341 0028 9342 cmp r3, r2 - 6342 002a 02D8 bhi .L617 -3176:../../../Source/third_party/fatfs/src/ff.c **** *nclst = fs->free_clust; - 6343 .loc 1 3176 0 - 6344 002c CAF80030 str r3, [r10] - 6345 0030 58E0 b .L633 - 6346 .L617: -3177:../../../Source/third_party/fatfs/src/ff.c **** } else { -3178:../../../Source/third_party/fatfs/src/ff.c **** /* Get number of free clusters */ -3179:../../../Source/third_party/fatfs/src/ff.c **** fat = fs->fs_type; - 6347 .loc 1 3179 0 - 6348 0032 2F78 ldrb r7, [r5] @ zero_extendqisi2 - 6349 .LVL960: -3180:../../../Source/third_party/fatfs/src/ff.c **** n = 0; -3181:../../../Source/third_party/fatfs/src/ff.c **** if (fat == FS_FAT12) { - 6350 .loc 1 3181 0 - 6351 0034 012F cmp r7, #1 - 6352 0036 11D1 bne .L618 - 6353 0038 0224 movs r4, #2 - 6354 003a 0026 movs r6, #0 - 6355 .LVL961: - 6356 .L621: -3182:../../../Source/third_party/fatfs/src/ff.c **** clst = 2; -3183:../../../Source/third_party/fatfs/src/ff.c **** do { -3184:../../../Source/third_party/fatfs/src/ff.c **** stat = get_fat(fs, clst); - 6357 .loc 1 3184 0 - 6358 003c 2846 mov r0, r5 - 6359 003e 2146 mov r1, r4 - 6360 0040 FFF7FEFF bl get_fat - 6361 .LVL962: -3185:../../../Source/third_party/fatfs/src/ff.c **** if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } - 6362 .loc 1 3185 0 - 6363 0044 B0F1FF3F cmp r0, #-1 - 6364 0048 45D0 beq .L630 -3186:../../../Source/third_party/fatfs/src/ff.c **** if (stat == 1) { res = FR_INT_ERR; break; } - 6365 .loc 1 3186 0 - 6366 004a 0128 cmp r0, #1 - 6367 004c 46D0 beq .L631 -3187:../../../Source/third_party/fatfs/src/ff.c **** if (stat == 0) n++; - 6368 .loc 1 3187 0 - 6369 004e 00B9 cbnz r0, .L620 - 6370 .loc 1 3187 0 is_stmt 0 discriminator 1 - 6371 0050 0136 adds r6, r6, #1 - 6372 .LVL963: - 6373 .L620: -3188:../../../Source/third_party/fatfs/src/ff.c **** } while (++clst < fs->n_fatent); - 6374 .loc 1 3188 0 is_stmt 1 - 6375 0052 0134 adds r4, r4, #1 - 6376 .LVL964: - 6377 0054 AB69 ldr r3, [r5, #24] - 6378 0056 9C42 cmp r4, r3 - 6379 0058 F0D3 bcc .L621 - 6380 005a 41E0 b .L619 - 6381 .LVL965: - 6382 .L618: -3189:../../../Source/third_party/fatfs/src/ff.c **** } else { -3190:../../../Source/third_party/fatfs/src/ff.c **** clst = fs->n_fatent; -3191:../../../Source/third_party/fatfs/src/ff.c **** sect = fs->fatbase; - 6383 .loc 1 3191 0 - 6384 005c 696A ldr r1, [r5, #36] - 6385 .LVL966: -3192:../../../Source/third_party/fatfs/src/ff.c **** i = 0; p = 0; - 6386 .loc 1 3192 0 - 6387 005e 0023 movs r3, #0 - 6388 0060 9E46 mov lr, r3 -3180:../../../Source/third_party/fatfs/src/ff.c **** if (fat == FS_FAT12) { - 6389 .loc 1 3180 0 - 6390 0062 1E46 mov r6, r3 -3193:../../../Source/third_party/fatfs/src/ff.c **** do { -3194:../../../Source/third_party/fatfs/src/ff.c **** if (!i) { -3195:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(fs, sect++); -3196:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; -3197:../../../Source/third_party/fatfs/src/ff.c **** p = fs->win; -3198:../../../Source/third_party/fatfs/src/ff.c **** i = SS(fs); - 6391 .loc 1 3198 0 - 6392 0064 4FF4007B mov fp, #512 - 6393 .LVL967: - 6394 .L628: -3194:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(fs, sect++); - 6395 .loc 1 3194 0 - 6396 0068 BEF1000F cmp lr, #0 - 6397 006c 0AD1 bne .L622 - 6398 .LVL968: -3195:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 6399 .loc 1 3195 0 - 6400 006e 01F10108 add r8, r1, #1 - 6401 .LVL969: - 6402 0072 2846 mov r0, r5 - 6403 0074 FFF7FEFF bl move_window - 6404 .LVL970: -3196:../../../Source/third_party/fatfs/src/ff.c **** p = fs->win; - 6405 .loc 1 3196 0 - 6406 0078 0346 mov r3, r0 - 6407 007a 18BB cbnz r0, .L632 - 6408 .LVL971: -3197:../../../Source/third_party/fatfs/src/ff.c **** i = SS(fs); - 6409 .loc 1 3197 0 - 6410 007c 05F13403 add r3, r5, #52 - 6411 .LVL972: -3195:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 6412 .loc 1 3195 0 - 6413 0080 4146 mov r1, r8 - 6414 .loc 1 3198 0 - 6415 0082 DE46 mov lr, fp - 6416 .LVL973: - 6417 .L622: -3199:../../../Source/third_party/fatfs/src/ff.c **** } -3200:../../../Source/third_party/fatfs/src/ff.c **** if (fat == FS_FAT16) { - 6418 .loc 1 3200 0 - 6419 0084 022F cmp r7, #2 - 6420 0086 09D1 bne .L624 -3201:../../../Source/third_party/fatfs/src/ff.c **** if (LD_WORD(p) == 0) n++; - 6421 .loc 1 3201 0 - 6422 0088 5878 ldrb r0, [r3, #1] @ zero_extendqisi2 - 6423 008a 1A78 ldrb r2, [r3] @ zero_extendqisi2 - 6424 008c 52EA0022 orrs r2, r2, r0, lsl #8 - 6425 0090 08BF it eq - 6426 0092 0136 addeq r6, r6, #1 - 6427 .LVL974: -3202:../../../Source/third_party/fatfs/src/ff.c **** p += 2; i -= 2; - 6428 .loc 1 3202 0 - 6429 0094 0233 adds r3, r3, #2 - 6430 .LVL975: - 6431 0096 AEF1020E sub lr, lr, #2 - 6432 .LVL976: - 6433 009a 10E0 b .L626 - 6434 .LVL977: - 6435 .L624: -3203:../../../Source/third_party/fatfs/src/ff.c **** } else { -3204:../../../Source/third_party/fatfs/src/ff.c **** if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++; - 6436 .loc 1 3204 0 - 6437 009c D878 ldrb r0, [r3, #3] @ zero_extendqisi2 - 6438 009e 9A78 ldrb r2, [r3, #2] @ zero_extendqisi2 - 6439 00a0 1204 lsls r2, r2, #16 - 6440 00a2 42EA0062 orr r2, r2, r0, lsl #24 - 6441 00a6 1878 ldrb r0, [r3] @ zero_extendqisi2 - 6442 00a8 0243 orrs r2, r2, r0 - 6443 00aa 5878 ldrb r0, [r3, #1] @ zero_extendqisi2 - 6444 00ac 42EA0022 orr r2, r2, r0, lsl #8 - 6445 00b0 22F07042 bic r2, r2, #-268435456 - 6446 00b4 02B9 cbnz r2, .L627 - 6447 .loc 1 3204 0 is_stmt 0 discriminator 1 - 6448 00b6 0136 adds r6, r6, #1 - 6449 .LVL978: - 6450 .L627: -3205:../../../Source/third_party/fatfs/src/ff.c **** p += 4; i -= 4; - 6451 .loc 1 3205 0 is_stmt 1 - 6452 00b8 0433 adds r3, r3, #4 - 6453 .LVL979: - 6454 00ba AEF1040E sub lr, lr, #4 - 6455 .LVL980: - 6456 .L626: -3206:../../../Source/third_party/fatfs/src/ff.c **** } -3207:../../../Source/third_party/fatfs/src/ff.c **** } while (--clst); - 6457 .loc 1 3207 0 - 6458 00be 013C subs r4, r4, #1 - 6459 .LVL981: - 6460 00c0 D2D1 bne .L628 - 6461 00c2 00E0 b .L623 - 6462 .LVL982: - 6463 .L632: -3195:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 6464 .loc 1 3195 0 - 6465 00c4 8146 mov r9, r0 - 6466 .LVL983: - 6467 .L623: -3208:../../../Source/third_party/fatfs/src/ff.c **** } -3209:../../../Source/third_party/fatfs/src/ff.c **** fs->free_clust = n; - 6468 .loc 1 3209 0 - 6469 00c6 2E61 str r6, [r5, #16] -3210:../../../Source/third_party/fatfs/src/ff.c **** if (fat == FS_FAT32) fs->fsi_flag = 1; - 6470 .loc 1 3210 0 - 6471 00c8 032F cmp r7, #3 - 6472 00ca 04BF itt eq - 6473 00cc 0123 moveq r3, #1 - 6474 00ce 6B71 strbeq r3, [r5, #5] - 6475 .L629: -3211:../../../Source/third_party/fatfs/src/ff.c **** *nclst = n; - 6476 .loc 1 3211 0 - 6477 00d0 CAF80060 str r6, [r10] - 6478 00d4 06E0 b .L633 - 6479 .LVL984: - 6480 .L630: -3185:../../../Source/third_party/fatfs/src/ff.c **** if (stat == 1) { res = FR_INT_ERR; break; } - 6481 .loc 1 3185 0 - 6482 00d6 4FF00109 mov r9, #1 - 6483 00da 01E0 b .L619 - 6484 .L631: -3186:../../../Source/third_party/fatfs/src/ff.c **** if (stat == 0) n++; - 6485 .loc 1 3186 0 - 6486 00dc 4FF00209 mov r9, #2 - 6487 .L619: - 6488 .LVL985: -3209:../../../Source/third_party/fatfs/src/ff.c **** if (fat == FS_FAT32) fs->fsi_flag = 1; - 6489 .loc 1 3209 0 - 6490 00e0 2E61 str r6, [r5, #16] - 6491 00e2 F5E7 b .L629 - 6492 .LVL986: - 6493 .L633: -3212:../../../Source/third_party/fatfs/src/ff.c **** } -3213:../../../Source/third_party/fatfs/src/ff.c **** } -3214:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fs, res); -3215:../../../Source/third_party/fatfs/src/ff.c **** } - 6494 .loc 1 3215 0 - 6495 00e4 4846 mov r0, r9 - 6496 00e6 03B0 add sp, sp, #12 - 6497 .cfi_def_cfa_offset 36 - 6498 @ sp needed - 6499 00e8 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} - 6500 .cfi_endproc - 6501 .LFE42: - 6503 .section .text.f_truncate,"ax",%progbits - 6504 .align 2 - 6505 .global f_truncate - 6506 .thumb - 6507 .thumb_func - 6509 f_truncate: - 6510 .LFB43: -3216:../../../Source/third_party/fatfs/src/ff.c **** -3217:../../../Source/third_party/fatfs/src/ff.c **** -3218:../../../Source/third_party/fatfs/src/ff.c **** -3219:../../../Source/third_party/fatfs/src/ff.c **** -3220:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3221:../../../Source/third_party/fatfs/src/ff.c **** /* Truncate File */ -3222:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3223:../../../Source/third_party/fatfs/src/ff.c **** -3224:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_truncate ( -3225:../../../Source/third_party/fatfs/src/ff.c **** FIL *fp /* Pointer to the file object */ -3226:../../../Source/third_party/fatfs/src/ff.c **** ) -3227:../../../Source/third_party/fatfs/src/ff.c **** { - 6511 .loc 1 3227 0 - 6512 .cfi_startproc - 6513 @ args = 0, pretend = 0, frame = 0 - 6514 @ frame_needed = 0, uses_anonymous_args = 0 - 6515 .LVL987: - 6516 0000 70B5 push {r4, r5, r6, lr} - 6517 .cfi_def_cfa_offset 16 - 6518 .cfi_offset 4, -16 - 6519 .cfi_offset 5, -12 - 6520 .cfi_offset 6, -8 - 6521 .cfi_offset 14, -4 - 6522 0002 0446 mov r4, r0 -3228:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -3229:../../../Source/third_party/fatfs/src/ff.c **** DWORD ncl; -3230:../../../Source/third_party/fatfs/src/ff.c **** -3231:../../../Source/third_party/fatfs/src/ff.c **** -3232:../../../Source/third_party/fatfs/src/ff.c **** res = validate(fp); /* Check validity of the object */ - 6523 .loc 1 3232 0 - 6524 0004 FFF7FEFF bl validate - 6525 .LVL988: -3233:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 6526 .loc 1 3233 0 - 6527 0008 0546 mov r5, r0 - 6528 000a 0028 cmp r0, #0 - 6529 000c 45D1 bne .L650 -3234:../../../Source/third_party/fatfs/src/ff.c **** if (fp->flag & FA__ERROR) { /* Check abort flag */ - 6530 .loc 1 3234 0 - 6531 000e A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 6532 0010 13F0800F tst r3, #128 - 6533 0014 3BD1 bne .L647 -3235:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INT_ERR; -3236:../../../Source/third_party/fatfs/src/ff.c **** } else { -3237:../../../Source/third_party/fatfs/src/ff.c **** if (!(fp->flag & FA_WRITE)) /* Check access mode */ - 6534 .loc 1 3237 0 - 6535 0016 13F0020F tst r3, #2 - 6536 001a 3AD0 beq .L648 - 6537 001c 32E0 b .L651 - 6538 .LVL989: - 6539 .L646: -3238:../../../Source/third_party/fatfs/src/ff.c **** res = FR_DENIED; -3239:../../../Source/third_party/fatfs/src/ff.c **** } -3240:../../../Source/third_party/fatfs/src/ff.c **** } -3241:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -3242:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fsize > fp->fptr) { -3243:../../../Source/third_party/fatfs/src/ff.c **** fp->fsize = fp->fptr; /* Set file size to current R/W point */ - 6540 .loc 1 3243 0 - 6541 001e E260 str r2, [r4, #12] -3244:../../../Source/third_party/fatfs/src/ff.c **** fp->flag |= FA__WRITTEN; - 6542 .loc 1 3244 0 - 6543 0020 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 6544 0022 43F02003 orr r3, r3, #32 - 6545 0026 A371 strb r3, [r4, #6] -3245:../../../Source/third_party/fatfs/src/ff.c **** if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ - 6546 .loc 1 3245 0 - 6547 0028 3AB9 cbnz r2, .L640 -3246:../../../Source/third_party/fatfs/src/ff.c **** res = remove_chain(fp->fs, fp->sclust); - 6548 .loc 1 3246 0 - 6549 002a 2068 ldr r0, [r4] - 6550 002c 2169 ldr r1, [r4, #16] - 6551 002e FFF7FEFF bl remove_chain - 6552 .LVL990: - 6553 0032 0546 mov r5, r0 - 6554 .LVL991: -3247:../../../Source/third_party/fatfs/src/ff.c **** fp->sclust = 0; - 6555 .loc 1 3247 0 - 6556 0034 0023 movs r3, #0 - 6557 0036 2361 str r3, [r4, #16] - 6558 0038 1CE0 b .L641 - 6559 .LVL992: - 6560 .L640: -3248:../../../Source/third_party/fatfs/src/ff.c **** } else { /* When truncate a part of the file, remove remaining clusters */ -3249:../../../Source/third_party/fatfs/src/ff.c **** ncl = get_fat(fp->fs, fp->clust); - 6561 .loc 1 3249 0 - 6562 003a 2068 ldr r0, [r4] - 6563 003c 6169 ldr r1, [r4, #20] - 6564 003e FFF7FEFF bl get_fat - 6565 .LVL993: - 6566 0042 0646 mov r6, r0 - 6567 .LVL994: -3250:../../../Source/third_party/fatfs/src/ff.c **** res = FR_OK; -3251:../../../Source/third_party/fatfs/src/ff.c **** if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; -3252:../../../Source/third_party/fatfs/src/ff.c **** if (ncl == 1) res = FR_INT_ERR; - 6568 .loc 1 3252 0 - 6569 0044 0128 cmp r0, #1 - 6570 0046 17D0 beq .L649 -3250:../../../Source/third_party/fatfs/src/ff.c **** res = FR_OK; - 6571 .loc 1 3250 0 - 6572 0048 B0F1FF3F cmp r0, #-1 - 6573 004c 14BF ite ne - 6574 004e 0023 movne r3, #0 - 6575 0050 0123 moveq r3, #1 -3253:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK && ncl < fp->fs->n_fatent) { - 6576 .loc 1 3253 0 - 6577 0052 03BB cbnz r3, .L643 - 6578 .loc 1 3253 0 is_stmt 0 discriminator 1 - 6579 0054 2068 ldr r0, [r4] - 6580 .LVL995: - 6581 0056 8369 ldr r3, [r0, #24] - 6582 0058 9E42 cmp r6, r3 - 6583 005a 1ED2 bcs .L650 -3254:../../../Source/third_party/fatfs/src/ff.c **** res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF); - 6584 .loc 1 3254 0 is_stmt 1 - 6585 005c 6169 ldr r1, [r4, #20] - 6586 005e 6FF07042 mvn r2, #-268435456 - 6587 0062 FFF7FEFF bl put_fat - 6588 .LVL996: -3255:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) res = remove_chain(fp->fs, ncl); - 6589 .loc 1 3255 0 - 6590 0066 0346 mov r3, r0 - 6591 0068 A8B9 cbnz r0, .L643 - 6592 .loc 1 3255 0 is_stmt 0 discriminator 1 - 6593 006a 2068 ldr r0, [r4] - 6594 .LVL997: - 6595 006c 3146 mov r1, r6 - 6596 006e FFF7FEFF bl remove_chain - 6597 .LVL998: - 6598 0072 0546 mov r5, r0 - 6599 .LVL999: - 6600 .L641: -3256:../../../Source/third_party/fatfs/src/ff.c **** } -3257:../../../Source/third_party/fatfs/src/ff.c **** } -3258:../../../Source/third_party/fatfs/src/ff.c **** } -3259:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) fp->flag |= FA__ERROR; - 6601 .loc 1 3259 0 is_stmt 1 - 6602 0074 0DB9 cbnz r5, .L642 - 6603 0076 10E0 b .L650 - 6604 .LVL1000: - 6605 .L649: -3252:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK && ncl < fp->fs->n_fatent) { - 6606 .loc 1 3252 0 - 6607 0078 0225 movs r5, #2 - 6608 .LVL1001: - 6609 .L642: - 6610 .loc 1 3259 0 discriminator 1 - 6611 007a A379 ldrb r3, [r4, #6] @ zero_extendqisi2 - 6612 007c 63F07F03 orn r3, r3, #127 - 6613 0080 A371 strb r3, [r4, #6] - 6614 0082 0AE0 b .L650 - 6615 .LVL1002: - 6616 .L651: -3242:../../../Source/third_party/fatfs/src/ff.c **** fp->fsize = fp->fptr; /* Set file size to current R/W point */ - 6617 .loc 1 3242 0 - 6618 0084 A268 ldr r2, [r4, #8] - 6619 0086 E368 ldr r3, [r4, #12] - 6620 0088 9342 cmp r3, r2 - 6621 008a C8D8 bhi .L646 - 6622 008c 05E0 b .L650 - 6623 .LVL1003: - 6624 .L647: -3235:../../../Source/third_party/fatfs/src/ff.c **** } else { - 6625 .loc 1 3235 0 - 6626 008e 0225 movs r5, #2 - 6627 0090 03E0 b .L650 - 6628 .L648: -3238:../../../Source/third_party/fatfs/src/ff.c **** } - 6629 .loc 1 3238 0 - 6630 0092 0725 movs r5, #7 - 6631 .LVL1004: - 6632 0094 01E0 b .L650 - 6633 .LVL1005: - 6634 .L643: -3227:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; - 6635 .loc 1 3227 0 - 6636 0096 1D46 mov r5, r3 - 6637 0098 EFE7 b .L642 - 6638 .LVL1006: - 6639 .L650: -3260:../../../Source/third_party/fatfs/src/ff.c **** } -3261:../../../Source/third_party/fatfs/src/ff.c **** -3262:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, res); -3263:../../../Source/third_party/fatfs/src/ff.c **** } - 6640 .loc 1 3263 0 - 6641 009a 2846 mov r0, r5 - 6642 009c 70BD pop {r4, r5, r6, pc} - 6643 .cfi_endproc - 6644 .LFE43: - 6646 009e 00BF .section .text.f_unlink,"ax",%progbits - 6647 .align 2 - 6648 .global f_unlink - 6649 .thumb - 6650 .thumb_func - 6652 f_unlink: - 6653 .LFB44: -3264:../../../Source/third_party/fatfs/src/ff.c **** -3265:../../../Source/third_party/fatfs/src/ff.c **** -3266:../../../Source/third_party/fatfs/src/ff.c **** -3267:../../../Source/third_party/fatfs/src/ff.c **** -3268:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3269:../../../Source/third_party/fatfs/src/ff.c **** /* Delete a File or Directory */ -3270:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3271:../../../Source/third_party/fatfs/src/ff.c **** -3272:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_unlink ( -3273:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *path /* Pointer to the file or directory path */ -3274:../../../Source/third_party/fatfs/src/ff.c **** ) -3275:../../../Source/third_party/fatfs/src/ff.c **** { - 6654 .loc 1 3275 0 - 6655 .cfi_startproc - 6656 @ args = 0, pretend = 0, frame = 96 - 6657 @ frame_needed = 0, uses_anonymous_args = 0 - 6658 .LVL1007: - 6659 0000 30B5 push {r4, r5, lr} - 6660 .cfi_def_cfa_offset 12 - 6661 .cfi_offset 4, -12 - 6662 .cfi_offset 5, -8 - 6663 .cfi_offset 14, -4 - 6664 0002 99B0 sub sp, sp, #100 - 6665 .cfi_def_cfa_offset 112 - 6666 0004 18AB add r3, sp, #96 - 6667 0006 43F85C0D str r0, [r3, #-92]! -3276:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -3277:../../../Source/third_party/fatfs/src/ff.c **** DIR dj, sdj; -3278:../../../Source/third_party/fatfs/src/ff.c **** BYTE *dir; -3279:../../../Source/third_party/fatfs/src/ff.c **** DWORD dclst; -3280:../../../Source/third_party/fatfs/src/ff.c **** DEF_NAMEBUF; -3281:../../../Source/third_party/fatfs/src/ff.c **** -3282:../../../Source/third_party/fatfs/src/ff.c **** -3283:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&path, &dj.fs, 1); - 6668 .loc 1 3283 0 - 6669 000a 1846 mov r0, r3 - 6670 .LVL1008: - 6671 000c 0FA9 add r1, sp, #60 - 6672 000e 0122 movs r2, #1 - 6673 0010 FFF7FEFF bl chk_mounted - 6674 .LVL1009: -3284:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 6675 .loc 1 3284 0 - 6676 0014 0346 mov r3, r0 - 6677 0016 0028 cmp r0, #0 - 6678 0018 4AD1 bne .L667 -3285:../../../Source/third_party/fatfs/src/ff.c **** INIT_BUF(dj); - 6679 .loc 1 3285 0 - 6680 001a 03AB add r3, sp, #12 - 6681 001c 1593 str r3, [sp, #84] - 6682 001e 264B ldr r3, .L670 - 6683 0020 1693 str r3, [sp, #88] -3286:../../../Source/third_party/fatfs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ - 6684 .loc 1 3286 0 - 6685 0022 0FA8 add r0, sp, #60 - 6686 .LVL1010: - 6687 0024 0199 ldr r1, [sp, #4] - 6688 0026 FFF7FEFF bl follow_path - 6689 .LVL1011: -3287:../../../Source/third_party/fatfs/src/ff.c **** if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) -3288:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INVALID_NAME; /* Cannot remove dot entry */ -3289:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_LOCK -3290:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */ -3291:../../../Source/third_party/fatfs/src/ff.c **** #endif -3292:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { /* The object is accessible */ - 6690 .loc 1 3292 0 - 6691 002a 0346 mov r3, r0 - 6692 002c 0028 cmp r0, #0 - 6693 002e 3FD1 bne .L667 -3293:../../../Source/third_party/fatfs/src/ff.c **** dir = dj.dir; - 6694 .loc 1 3293 0 - 6695 0030 1499 ldr r1, [sp, #80] - 6696 .LVL1012: -3294:../../../Source/third_party/fatfs/src/ff.c **** if (!dir) { - 6697 .loc 1 3294 0 - 6698 0032 31B3 cbz r1, .L664 -3295:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INVALID_NAME; /* Cannot remove the start directory */ -3296:../../../Source/third_party/fatfs/src/ff.c **** } else { -3297:../../../Source/third_party/fatfs/src/ff.c **** if (dir[DIR_Attr] & AM_RDO) - 6699 .loc 1 3297 0 - 6700 0034 CC7A ldrb r4, [r1, #11] @ zero_extendqisi2 - 6701 0036 14F0010F tst r4, #1 - 6702 003a 24D1 bne .L665 - 6703 003c 25E0 b .L668 - 6704 .LVL1013: - 6705 .L661: -3298:../../../Source/third_party/fatfs/src/ff.c **** res = FR_DENIED; /* Cannot remove R/O object */ -3299:../../../Source/third_party/fatfs/src/ff.c **** } -3300:../../../Source/third_party/fatfs/src/ff.c **** dclst = ld_clust(dj.fs, dir); -3301:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */ -3302:../../../Source/third_party/fatfs/src/ff.c **** if (dclst < 2) { - 6706 .loc 1 3302 0 - 6707 003e 012D cmp r5, #1 - 6708 0040 2ED9 bls .L666 -3303:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INT_ERR; -3304:../../../Source/third_party/fatfs/src/ff.c **** } else { -3305:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(&sdj, &dj, sizeof (DIR)); /* Check if the sub-dir is empty or not */ - 6709 .loc 1 3305 0 - 6710 0042 06A8 add r0, sp, #24 - 6711 .LVL1014: - 6712 0044 0FA9 add r1, sp, #60 - 6713 0046 2422 movs r2, #36 - 6714 0048 FFF7FEFF bl mem_cpy - 6715 .LVL1015: -3306:../../../Source/third_party/fatfs/src/ff.c **** sdj.sclust = dclst; - 6716 .loc 1 3306 0 - 6717 004c 0895 str r5, [sp, #32] -3307:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(&sdj, 2); /* Exclude dot entries */ - 6718 .loc 1 3307 0 - 6719 004e 06A8 add r0, sp, #24 - 6720 0050 0221 movs r1, #2 - 6721 0052 FFF7FEFF bl dir_sdi - 6722 .LVL1016: -3308:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 6723 .loc 1 3308 0 - 6724 0056 0346 mov r3, r0 - 6725 0058 50BB cbnz r0, .L667 -3309:../../../Source/third_party/fatfs/src/ff.c **** res = dir_read(&sdj, 0); /* Read an item */ - 6726 .loc 1 3309 0 - 6727 005a 06A8 add r0, sp, #24 - 6728 .LVL1017: - 6729 005c 0021 movs r1, #0 - 6730 005e FFF7FEFF bl dir_read - 6731 .LVL1018: -3310:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK /* Not empty dir */ - 6732 .loc 1 3310 0 - 6733 0062 0346 mov r3, r0 - 6734 0064 C8B9 cbnz r0, .L658 -3311:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_RPATH -3312:../../../Source/third_party/fatfs/src/ff.c **** || dclst == dj.fs->cdir /* Current dir */ -3313:../../../Source/third_party/fatfs/src/ff.c **** #endif -3314:../../../Source/third_party/fatfs/src/ff.c **** ) res = FR_DENIED; - 6735 .loc 1 3314 0 - 6736 0066 0723 movs r3, #7 - 6737 .LVL1019: - 6738 0068 22E0 b .L667 - 6739 .LVL1020: - 6740 .L663: -3315:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) res = FR_OK; /* Empty */ -3316:../../../Source/third_party/fatfs/src/ff.c **** } -3317:../../../Source/third_party/fatfs/src/ff.c **** } -3318:../../../Source/third_party/fatfs/src/ff.c **** } -3319:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -3320:../../../Source/third_party/fatfs/src/ff.c **** res = dir_remove(&dj); /* Remove the directory entry */ -3321:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -3322:../../../Source/third_party/fatfs/src/ff.c **** if (dclst) /* Remove the cluster chain if exist */ - 6741 .loc 1 3322 0 - 6742 006a 2DB1 cbz r5, .L659 -3323:../../../Source/third_party/fatfs/src/ff.c **** res = remove_chain(dj.fs, dclst); - 6743 .loc 1 3323 0 - 6744 006c 0F98 ldr r0, [sp, #60] - 6745 .LVL1021: - 6746 006e 2946 mov r1, r5 - 6747 0070 FFF7FEFF bl remove_chain - 6748 .LVL1022: -3324:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) res = sync_fs(dj.fs); - 6749 .loc 1 3324 0 - 6750 0074 0346 mov r3, r0 - 6751 0076 D8B9 cbnz r0, .L667 - 6752 .L659: - 6753 .LVL1023: - 6754 .loc 1 3324 0 is_stmt 0 discriminator 1 - 6755 0078 0F98 ldr r0, [sp, #60] - 6756 007a FFF7FEFF bl sync_fs - 6757 .LVL1024: - 6758 007e 0346 mov r3, r0 - 6759 .LVL1025: - 6760 0080 16E0 b .L667 - 6761 .LVL1026: - 6762 .L664: -3295:../../../Source/third_party/fatfs/src/ff.c **** } else { - 6763 .loc 1 3295 0 is_stmt 1 - 6764 0082 0623 movs r3, #6 - 6765 0084 14E0 b .L667 - 6766 .L665: -3298:../../../Source/third_party/fatfs/src/ff.c **** } - 6767 .loc 1 3298 0 - 6768 0086 0723 movs r3, #7 - 6769 0088 12E0 b .L667 - 6770 .L668: - 6771 .LVL1027: -3300:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */ - 6772 .loc 1 3300 0 - 6773 008a 0F98 ldr r0, [sp, #60] - 6774 008c FFF7FEFF bl ld_clust - 6775 .LVL1028: - 6776 0090 0546 mov r5, r0 - 6777 .LVL1029: -3301:../../../Source/third_party/fatfs/src/ff.c **** if (dclst < 2) { - 6778 .loc 1 3301 0 - 6779 0092 14F0100F tst r4, #16 - 6780 0096 D2D1 bne .L661 - 6781 0098 04E0 b .L662 - 6782 .LVL1030: - 6783 .L658: -3315:../../../Source/third_party/fatfs/src/ff.c **** } - 6784 .loc 1 3315 0 - 6785 009a 0428 cmp r0, #4 - 6786 009c 02D0 beq .L662 - 6787 009e 07E0 b .L667 - 6788 .LVL1031: - 6789 .L666: -3303:../../../Source/third_party/fatfs/src/ff.c **** } else { - 6790 .loc 1 3303 0 - 6791 00a0 0223 movs r3, #2 - 6792 .LVL1032: - 6793 00a2 05E0 b .L667 - 6794 .LVL1033: - 6795 .L662: -3320:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 6796 .loc 1 3320 0 - 6797 00a4 0FA8 add r0, sp, #60 - 6798 00a6 FFF7FEFF bl dir_remove - 6799 .LVL1034: -3321:../../../Source/third_party/fatfs/src/ff.c **** if (dclst) /* Remove the cluster chain if exist */ - 6800 .loc 1 3321 0 - 6801 00aa 0346 mov r3, r0 - 6802 00ac 0028 cmp r0, #0 - 6803 00ae DCD0 beq .L663 - 6804 .LVL1035: - 6805 .L667: -3325:../../../Source/third_party/fatfs/src/ff.c **** } -3326:../../../Source/third_party/fatfs/src/ff.c **** } -3327:../../../Source/third_party/fatfs/src/ff.c **** } -3328:../../../Source/third_party/fatfs/src/ff.c **** FREE_BUF(); -3329:../../../Source/third_party/fatfs/src/ff.c **** } -3330:../../../Source/third_party/fatfs/src/ff.c **** -3331:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(dj.fs, res); -3332:../../../Source/third_party/fatfs/src/ff.c **** } - 6806 .loc 1 3332 0 - 6807 00b0 1846 mov r0, r3 - 6808 00b2 19B0 add sp, sp, #100 - 6809 .cfi_def_cfa_offset 12 - 6810 @ sp needed - 6811 00b4 30BD pop {r4, r5, pc} - 6812 .LVL1036: - 6813 .L671: - 6814 00b6 00BF .align 2 - 6815 .L670: - 6816 00b8 00000000 .word .LANCHOR4 - 6817 .cfi_endproc - 6818 .LFE44: - 6820 .section .text.f_mkdir,"ax",%progbits - 6821 .align 2 - 6822 .global f_mkdir - 6823 .thumb - 6824 .thumb_func - 6826 f_mkdir: - 6827 .LFB45: -3333:../../../Source/third_party/fatfs/src/ff.c **** -3334:../../../Source/third_party/fatfs/src/ff.c **** -3335:../../../Source/third_party/fatfs/src/ff.c **** -3336:../../../Source/third_party/fatfs/src/ff.c **** -3337:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3338:../../../Source/third_party/fatfs/src/ff.c **** /* Create a Directory */ -3339:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3340:../../../Source/third_party/fatfs/src/ff.c **** -3341:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_mkdir ( -3342:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *path /* Pointer to the directory path */ -3343:../../../Source/third_party/fatfs/src/ff.c **** ) -3344:../../../Source/third_party/fatfs/src/ff.c **** { - 6828 .loc 1 3344 0 - 6829 .cfi_startproc - 6830 @ args = 0, pretend = 0, frame = 56 - 6831 @ frame_needed = 0, uses_anonymous_args = 0 - 6832 .LVL1037: - 6833 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} - 6834 .cfi_def_cfa_offset 36 - 6835 .cfi_offset 4, -36 - 6836 .cfi_offset 5, -32 - 6837 .cfi_offset 6, -28 - 6838 .cfi_offset 7, -24 - 6839 .cfi_offset 8, -20 - 6840 .cfi_offset 9, -16 - 6841 .cfi_offset 10, -12 - 6842 .cfi_offset 11, -8 - 6843 .cfi_offset 14, -4 - 6844 0004 8FB0 sub sp, sp, #60 - 6845 .cfi_def_cfa_offset 96 - 6846 0006 0EAC add r4, sp, #56 - 6847 0008 44F8340D str r0, [r4, #-52]! -3345:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -3346:../../../Source/third_party/fatfs/src/ff.c **** DIR dj; -3347:../../../Source/third_party/fatfs/src/ff.c **** BYTE *dir, n; -3348:../../../Source/third_party/fatfs/src/ff.c **** DWORD dsc, dcl, pcl, tm = get_fattime(); - 6848 .loc 1 3348 0 - 6849 000c FFF7FEFF bl get_fattime - 6850 .LVL1038: - 6851 0010 0746 mov r7, r0 - 6852 .LVL1039: -3349:../../../Source/third_party/fatfs/src/ff.c **** DEF_NAMEBUF; -3350:../../../Source/third_party/fatfs/src/ff.c **** -3351:../../../Source/third_party/fatfs/src/ff.c **** -3352:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&path, &dj.fs, 1); - 6853 .loc 1 3352 0 - 6854 0012 2046 mov r0, r4 - 6855 .LVL1040: - 6856 0014 05A9 add r1, sp, #20 - 6857 0016 0122 movs r2, #1 - 6858 0018 FFF7FEFF bl chk_mounted - 6859 .LVL1041: -3353:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 6860 .loc 1 3353 0 - 6861 001c 0446 mov r4, r0 - 6862 .LVL1042: - 6863 001e 0028 cmp r0, #0 - 6864 0020 40F0CE80 bne .L691 -3354:../../../Source/third_party/fatfs/src/ff.c **** INIT_BUF(dj); - 6865 .loc 1 3354 0 - 6866 0024 02AB add r3, sp, #8 - 6867 0026 0B93 str r3, [sp, #44] - 6868 0028 674B ldr r3, .L699 - 6869 002a 0C93 str r3, [sp, #48] -3355:../../../Source/third_party/fatfs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ - 6870 .loc 1 3355 0 - 6871 002c 05A8 add r0, sp, #20 - 6872 .LVL1043: - 6873 002e 0199 ldr r1, [sp, #4] - 6874 0030 FFF7FEFF bl follow_path - 6875 .LVL1044: -3356:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ - 6876 .loc 1 3356 0 - 6877 0034 0446 mov r4, r0 - 6878 0036 0028 cmp r0, #0 - 6879 0038 00F0B480 beq .L687 -3357:../../../Source/third_party/fatfs/src/ff.c **** if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT)) -3358:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INVALID_NAME; -3359:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) { /* Can create a new directory */ - 6880 .loc 1 3359 0 - 6881 003c 0428 cmp r0, #4 - 6882 003e 40F0BF80 bne .L691 -3360:../../../Source/third_party/fatfs/src/ff.c **** dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */ - 6883 .loc 1 3360 0 - 6884 0042 0598 ldr r0, [sp, #20] - 6885 .LVL1045: - 6886 0044 0021 movs r1, #0 - 6887 0046 FFF7FEFF bl create_chain - 6888 .LVL1046: -3361:../../../Source/third_party/fatfs/src/ff.c **** res = FR_OK; -3362:../../../Source/third_party/fatfs/src/ff.c **** if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ - 6889 .loc 1 3362 0 - 6890 004a 8146 mov r9, r0 - 6891 004c 0028 cmp r0, #0 - 6892 004e 00F08280 beq .L688 -3363:../../../Source/third_party/fatfs/src/ff.c **** if (dcl == 1) res = FR_INT_ERR; - 6893 .loc 1 3363 0 - 6894 0052 0128 cmp r0, #1 - 6895 0054 00F08180 beq .L689 - 6896 0058 ABE0 b .L696 - 6897 .L697: -3364:../../../Source/third_party/fatfs/src/ff.c **** if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; -3365:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) /* Flush FAT */ -3366:../../../Source/third_party/fatfs/src/ff.c **** res = sync_window(dj.fs); - 6898 .loc 1 3366 0 - 6899 005a 0598 ldr r0, [sp, #20] - 6900 .LVL1047: - 6901 005c FFF7FEFF bl sync_window - 6902 .LVL1048: - 6903 0060 0446 mov r4, r0 - 6904 .LVL1049: - 6905 0062 FFE7 b .L685 - 6906 .LVL1050: - 6907 .L685: -3367:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { /* Initialize the new directory table */ - 6908 .loc 1 3367 0 - 6909 0064 002C cmp r4, #0 - 6910 0066 74D1 bne .L684 -3368:../../../Source/third_party/fatfs/src/ff.c **** dsc = clust2sect(dj.fs, dcl); - 6911 .loc 1 3368 0 - 6912 0068 059E ldr r6, [sp, #20] - 6913 006a 3046 mov r0, r6 - 6914 006c 4946 mov r1, r9 - 6915 006e FFF7FEFF bl clust2sect - 6916 .LVL1051: - 6917 0072 0446 mov r4, r0 - 6918 .LVL1052: -3369:../../../Source/third_party/fatfs/src/ff.c **** dir = dj.fs->win; - 6919 .loc 1 3369 0 - 6920 0074 06F13403 add r3, r6, #52 - 6921 0078 0093 str r3, [sp] - 6922 .LVL1053: - 6923 007a 06F50D75 add r5, r6, #564 - 6924 .LBB87: - 6925 .LBB88: - 560:../../../Source/third_party/fatfs/src/ff.c **** } - 6926 .loc 1 560 0 - 6927 007e 0022 movs r2, #0 - 6928 .LVL1054: - 6929 .L677: - 6930 0080 03F8012B strb r2, [r3], #1 - 6931 .LVL1055: - 559:../../../Source/third_party/fatfs/src/ff.c **** *d++ = (BYTE)val; - 6932 .loc 1 559 0 - 6933 0084 AB42 cmp r3, r5 - 6934 0086 FBD1 bne .L677 - 6935 0088 06F13F01 add r1, r6, #63 - 6936 008c 009B ldr r3, [sp] - 6937 .LVL1056: - 6938 .LBE88: - 6939 .LBE87: - 6940 .LBB89: - 6941 .LBB90: - 560:../../../Source/third_party/fatfs/src/ff.c **** } - 6942 .loc 1 560 0 - 6943 008e 2022 movs r2, #32 - 6944 .L678: - 6945 .LVL1057: - 6946 0090 03F8012B strb r2, [r3], #1 - 6947 .LVL1058: - 559:../../../Source/third_party/fatfs/src/ff.c **** *d++ = (BYTE)val; - 6948 .loc 1 559 0 - 6949 0094 8B42 cmp r3, r1 - 6950 0096 FBD1 bne .L678 - 6951 .LBE90: - 6952 .LBE89: -3370:../../../Source/third_party/fatfs/src/ff.c **** mem_set(dir, 0, SS(dj.fs)); -3371:../../../Source/third_party/fatfs/src/ff.c **** mem_set(dir+DIR_Name, ' ', 11); /* Create "." entry */ -3372:../../../Source/third_party/fatfs/src/ff.c **** dir[DIR_Name] = '.'; - 6953 .loc 1 3372 0 - 6954 0098 4FF02E08 mov r8, #46 - 6955 009c 86F83480 strb r8, [r6, #52] -3373:../../../Source/third_party/fatfs/src/ff.c **** dir[DIR_Attr] = AM_DIR; - 6956 .loc 1 3373 0 - 6957 00a0 1023 movs r3, #16 - 6958 .LVL1059: - 6959 00a2 86F83F30 strb r3, [r6, #63] -3374:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(dir+DIR_WrtTime, tm); - 6960 .loc 1 3374 0 - 6961 00a6 86F84A70 strb r7, [r6, #74] - 6962 00aa C7F30723 ubfx r3, r7, #8, #8 - 6963 00ae 86F84B30 strb r3, [r6, #75] - 6964 00b2 3B0C lsrs r3, r7, #16 - 6965 00b4 86F84C30 strb r3, [r6, #76] - 6966 00b8 3B0E lsrs r3, r7, #24 - 6967 00ba 86F84D30 strb r3, [r6, #77] - 6968 .LVL1060: - 6969 .LBB91: - 6970 .LBB92: -1261:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+DIR_FstClusHI, cl >> 16); - 6971 .loc 1 1261 0 - 6972 00be 86F84E90 strb r9, [r6, #78] - 6973 00c2 C9F30723 ubfx r3, r9, #8, #8 - 6974 00c6 86F84F30 strb r3, [r6, #79] -1262:../../../Source/third_party/fatfs/src/ff.c **** } - 6975 .loc 1 1262 0 - 6976 00ca 4FEA1943 lsr r3, r9, #16 - 6977 00ce 86F84830 strb r3, [r6, #72] - 6978 00d2 1B0A lsrs r3, r3, #8 - 6979 00d4 86F84930 strb r3, [r6, #73] - 6980 .LBE92: - 6981 .LBE91: -3375:../../../Source/third_party/fatfs/src/ff.c **** st_clust(dir, dcl); -3376:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(dir+SZ_DIR, dir, SZ_DIR); /* Create ".." entry */ - 6982 .loc 1 3376 0 - 6983 00d8 06F15400 add r0, r6, #84 - 6984 .LVL1061: - 6985 00dc 0099 ldr r1, [sp] - 6986 00de 2022 movs r2, #32 - 6987 00e0 FFF7FEFF bl mem_cpy - 6988 .LVL1062: -3377:../../../Source/third_party/fatfs/src/ff.c **** dir[33] = '.'; pcl = dj.sclust; - 6989 .loc 1 3377 0 - 6990 00e4 86F85580 strb r8, [r6, #85] - 6991 00e8 079B ldr r3, [sp, #28] - 6992 .LVL1063: -3378:../../../Source/third_party/fatfs/src/ff.c **** if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase) - 6993 .loc 1 3378 0 - 6994 00ea 059A ldr r2, [sp, #20] - 6995 00ec 1178 ldrb r1, [r2] @ zero_extendqisi2 - 6996 00ee 0329 cmp r1, #3 - 6997 00f0 03D1 bne .L679 - 6998 .loc 1 3378 0 is_stmt 0 discriminator 1 - 6999 00f2 916A ldr r1, [r2, #40] -3379:../../../Source/third_party/fatfs/src/ff.c **** pcl = 0; - 7000 .loc 1 3379 0 is_stmt 1 discriminator 1 - 7001 00f4 9942 cmp r1, r3 - 7002 00f6 08BF it eq - 7003 00f8 0023 moveq r3, #0 - 7004 .LVL1064: - 7005 .L679: - 7006 .LBB93: - 7007 .LBB94: -1261:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+DIR_FstClusHI, cl >> 16); - 7008 .loc 1 1261 0 - 7009 00fa 86F86E30 strb r3, [r6, #110] - 7010 00fe C3F30721 ubfx r1, r3, #8, #8 - 7011 0102 86F86F10 strb r1, [r6, #111] -1262:../../../Source/third_party/fatfs/src/ff.c **** } - 7012 .loc 1 1262 0 - 7013 0106 1B0C lsrs r3, r3, #16 - 7014 .LVL1065: - 7015 0108 86F86830 strb r3, [r6, #104] - 7016 010c 1B0A lsrs r3, r3, #8 - 7017 010e 86F86930 strb r3, [r6, #105] - 7018 .LBE94: - 7019 .LBE93: -3380:../../../Source/third_party/fatfs/src/ff.c **** st_clust(dir+SZ_DIR, pcl); -3381:../../../Source/third_party/fatfs/src/ff.c **** for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */ - 7020 .loc 1 3381 0 - 7021 0112 9378 ldrb r3, [r2, #2] @ zero_extendqisi2 - 7022 .LVL1066: - 7023 0114 002B cmp r3, #0 - 7024 0116 47D0 beq .L680 - 7025 0118 03F1FF3A add r10, r3, #-1 - 7026 011c 5FFA8AFA uxtb r10, r10 - 7027 0120 0AF1010A add r10, r10, #1 - 7028 0124 A244 add r10, r10, r4 -3382:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->winsect = dsc++; -3383:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->wflag = 1; - 7029 .loc 1 3383 0 - 7030 0126 4FF0010B mov fp, #1 - 7031 .LBB95: - 7032 .LBB96: - 560:../../../Source/third_party/fatfs/src/ff.c **** } - 7033 .loc 1 560 0 - 7034 012a 0026 movs r6, #0 - 7035 .LVL1067: - 7036 .L682: - 7037 .LBE96: - 7038 .LBE95: -3382:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->winsect = dsc++; - 7039 .loc 1 3382 0 - 7040 012c 0598 ldr r0, [sp, #20] - 7041 012e 04F10108 add r8, r4, #1 - 7042 .LVL1068: - 7043 0132 0463 str r4, [r0, #48] - 7044 .loc 1 3383 0 - 7045 0134 80F804B0 strb fp, [r0, #4] -3384:../../../Source/third_party/fatfs/src/ff.c **** res = sync_window(dj.fs); - 7046 .loc 1 3384 0 - 7047 0138 FFF7FEFF bl sync_window - 7048 .LVL1069: -3385:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) break; - 7049 .loc 1 3385 0 - 7050 013c 0446 mov r4, r0 - 7051 013e 40B9 cbnz r0, .L684 - 7052 0140 009B ldr r3, [sp] - 7053 .L681: - 7054 .LVL1070: - 7055 .LBB98: - 7056 .LBB97: - 560:../../../Source/third_party/fatfs/src/ff.c **** } - 7057 .loc 1 560 0 - 7058 0142 03F8016B strb r6, [r3], #1 - 7059 .LVL1071: - 559:../../../Source/third_party/fatfs/src/ff.c **** *d++ = (BYTE)val; - 7060 .loc 1 559 0 - 7061 0146 AB42 cmp r3, r5 - 7062 0148 FBD1 bne .L681 - 7063 .LVL1072: - 7064 .LBE97: - 7065 .LBE98: -3382:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->wflag = 1; - 7066 .loc 1 3382 0 discriminator 2 - 7067 014a 4446 mov r4, r8 -3381:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->winsect = dsc++; - 7068 .loc 1 3381 0 discriminator 2 - 7069 014c D045 cmp r8, r10 - 7070 014e EDD1 bne .L682 - 7071 .LVL1073: - 7072 0150 2AE0 b .L680 - 7073 .LVL1074: - 7074 .L684: -3386:../../../Source/third_party/fatfs/src/ff.c **** mem_set(dir, 0, SS(dj.fs)); -3387:../../../Source/third_party/fatfs/src/ff.c **** } -3388:../../../Source/third_party/fatfs/src/ff.c **** } -3389:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */ -3390:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) { - 7075 .loc 1 3390 0 - 7076 0152 44B1 cbz r4, .L683 - 7077 0154 02E0 b .L674 - 7078 .LVL1075: - 7079 .L688: -3362:../../../Source/third_party/fatfs/src/ff.c **** if (dcl == 1) res = FR_INT_ERR; - 7080 .loc 1 3362 0 - 7081 0156 0724 movs r4, #7 - 7082 0158 00E0 b .L674 - 7083 .L689: -3363:../../../Source/third_party/fatfs/src/ff.c **** if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; - 7084 .loc 1 3363 0 - 7085 015a 0224 movs r4, #2 - 7086 .LVL1076: - 7087 .L674: -3391:../../../Source/third_party/fatfs/src/ff.c **** remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */ - 7088 .loc 1 3391 0 - 7089 015c 0598 ldr r0, [sp, #20] - 7090 015e 4946 mov r1, r9 - 7091 0160 FFF7FEFF bl remove_chain - 7092 .LVL1077: - 7093 0164 2CE0 b .L691 - 7094 .L683: -3392:../../../Source/third_party/fatfs/src/ff.c **** } else { -3393:../../../Source/third_party/fatfs/src/ff.c **** dir = dj.dir; - 7095 .loc 1 3393 0 - 7096 0166 0A9B ldr r3, [sp, #40] - 7097 .LVL1078: -3394:../../../Source/third_party/fatfs/src/ff.c **** dir[DIR_Attr] = AM_DIR; /* Attribute */ - 7098 .loc 1 3394 0 - 7099 0168 1022 movs r2, #16 - 7100 016a DA72 strb r2, [r3, #11] -3395:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(dir+DIR_WrtTime, tm); /* Created time */ - 7101 .loc 1 3395 0 - 7102 016c 9F75 strb r7, [r3, #22] - 7103 016e C7F30722 ubfx r2, r7, #8, #8 - 7104 0172 DA75 strb r2, [r3, #23] - 7105 0174 3A0C lsrs r2, r7, #16 - 7106 0176 1A76 strb r2, [r3, #24] - 7107 0178 3F0E lsrs r7, r7, #24 - 7108 .LVL1079: - 7109 017a 5F76 strb r7, [r3, #25] - 7110 .LVL1080: - 7111 .LBB99: - 7112 .LBB100: -1261:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+DIR_FstClusHI, cl >> 16); - 7113 .loc 1 1261 0 - 7114 017c 83F81A90 strb r9, [r3, #26] - 7115 0180 C9F30722 ubfx r2, r9, #8, #8 - 7116 0184 DA76 strb r2, [r3, #27] -1262:../../../Source/third_party/fatfs/src/ff.c **** } - 7117 .loc 1 1262 0 - 7118 0186 4FEA1949 lsr r9, r9, #16 - 7119 .LVL1081: - 7120 018a 83F81490 strb r9, [r3, #20] - 7121 018e 4FEA1929 lsr r9, r9, #8 - 7122 0192 83F81590 strb r9, [r3, #21] - 7123 .LBE100: - 7124 .LBE99: -3396:../../../Source/third_party/fatfs/src/ff.c **** st_clust(dir, dcl); /* Table start cluster */ -3397:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->wflag = 1; - 7125 .loc 1 3397 0 - 7126 0196 0598 ldr r0, [sp, #20] - 7127 0198 0123 movs r3, #1 - 7128 .LVL1082: - 7129 019a 0371 strb r3, [r0, #4] -3398:../../../Source/third_party/fatfs/src/ff.c **** res = sync_fs(dj.fs); - 7130 .loc 1 3398 0 - 7131 019c FFF7FEFF bl sync_fs - 7132 .LVL1083: - 7133 01a0 0446 mov r4, r0 - 7134 .LVL1084: - 7135 01a2 0DE0 b .L691 - 7136 .LVL1085: - 7137 .L687: -3356:../../../Source/third_party/fatfs/src/ff.c **** if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT)) - 7138 .loc 1 3356 0 - 7139 01a4 0824 movs r4, #8 - 7140 .LVL1086: - 7141 01a6 0BE0 b .L691 - 7142 .LVL1087: - 7143 .L680: -3389:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) { - 7144 .loc 1 3389 0 - 7145 01a8 05A8 add r0, sp, #20 - 7146 01aa FFF7FEFF bl dir_register - 7147 .LVL1088: - 7148 01ae 0446 mov r4, r0 - 7149 01b0 CFE7 b .L684 - 7150 .LVL1089: - 7151 .L696: -3364:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) /* Flush FAT */ - 7152 .loc 1 3364 0 - 7153 01b2 B0F1FF3F cmp r0, #-1 - 7154 01b6 08BF it eq - 7155 01b8 0124 moveq r4, #1 - 7156 01ba 3FF453AF beq .L685 - 7157 01be 4CE7 b .L697 - 7158 .LVL1090: - 7159 .L691: -3399:../../../Source/third_party/fatfs/src/ff.c **** } -3400:../../../Source/third_party/fatfs/src/ff.c **** } -3401:../../../Source/third_party/fatfs/src/ff.c **** FREE_BUF(); -3402:../../../Source/third_party/fatfs/src/ff.c **** } -3403:../../../Source/third_party/fatfs/src/ff.c **** -3404:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(dj.fs, res); -3405:../../../Source/third_party/fatfs/src/ff.c **** } - 7160 .loc 1 3405 0 - 7161 01c0 2046 mov r0, r4 - 7162 01c2 0FB0 add sp, sp, #60 - 7163 .cfi_def_cfa_offset 36 - 7164 @ sp needed - 7165 01c4 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} - 7166 .LVL1091: - 7167 .L700: - 7168 .align 2 - 7169 .L699: - 7170 01c8 00000000 .word .LANCHOR4 - 7171 .cfi_endproc - 7172 .LFE45: - 7174 .section .text.f_chmod,"ax",%progbits - 7175 .align 2 - 7176 .global f_chmod - 7177 .thumb - 7178 .thumb_func - 7180 f_chmod: - 7181 .LFB46: -3406:../../../Source/third_party/fatfs/src/ff.c **** -3407:../../../Source/third_party/fatfs/src/ff.c **** -3408:../../../Source/third_party/fatfs/src/ff.c **** -3409:../../../Source/third_party/fatfs/src/ff.c **** -3410:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3411:../../../Source/third_party/fatfs/src/ff.c **** /* Change Attribute */ -3412:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3413:../../../Source/third_party/fatfs/src/ff.c **** -3414:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_chmod ( -3415:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *path, /* Pointer to the file path */ -3416:../../../Source/third_party/fatfs/src/ff.c **** BYTE value, /* Attribute bits */ -3417:../../../Source/third_party/fatfs/src/ff.c **** BYTE mask /* Attribute mask to change */ -3418:../../../Source/third_party/fatfs/src/ff.c **** ) -3419:../../../Source/third_party/fatfs/src/ff.c **** { - 7182 .loc 1 3419 0 - 7183 .cfi_startproc - 7184 @ args = 0, pretend = 0, frame = 56 - 7185 @ frame_needed = 0, uses_anonymous_args = 0 - 7186 .LVL1092: - 7187 0000 30B5 push {r4, r5, lr} - 7188 .cfi_def_cfa_offset 12 - 7189 .cfi_offset 4, -12 - 7190 .cfi_offset 5, -8 - 7191 .cfi_offset 14, -4 - 7192 0002 8FB0 sub sp, sp, #60 - 7193 .cfi_def_cfa_offset 72 - 7194 0004 0EAB add r3, sp, #56 - 7195 0006 43F8340D str r0, [r3, #-52]! - 7196 000a 0C46 mov r4, r1 - 7197 000c 1546 mov r5, r2 -3420:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -3421:../../../Source/third_party/fatfs/src/ff.c **** DIR dj; -3422:../../../Source/third_party/fatfs/src/ff.c **** BYTE *dir; -3423:../../../Source/third_party/fatfs/src/ff.c **** DEF_NAMEBUF; -3424:../../../Source/third_party/fatfs/src/ff.c **** -3425:../../../Source/third_party/fatfs/src/ff.c **** -3426:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&path, &dj.fs, 1); - 7198 .loc 1 3426 0 - 7199 000e 1846 mov r0, r3 - 7200 .LVL1093: - 7201 0010 05A9 add r1, sp, #20 - 7202 .LVL1094: - 7203 0012 0122 movs r2, #1 - 7204 .LVL1095: - 7205 0014 FFF7FEFF bl chk_mounted - 7206 .LVL1096: -3427:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 7207 .loc 1 3427 0 - 7208 0018 0346 mov r3, r0 - 7209 001a D8B9 cbnz r0, .L702 -3428:../../../Source/third_party/fatfs/src/ff.c **** INIT_BUF(dj); - 7210 .loc 1 3428 0 - 7211 001c 02AB add r3, sp, #8 - 7212 001e 0B93 str r3, [sp, #44] - 7213 0020 0E4B ldr r3, .L705 - 7214 0022 0C93 str r3, [sp, #48] -3429:../../../Source/third_party/fatfs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ - 7215 .loc 1 3429 0 - 7216 0024 05A8 add r0, sp, #20 - 7217 .LVL1097: - 7218 0026 0199 ldr r1, [sp, #4] - 7219 0028 FFF7FEFF bl follow_path - 7220 .LVL1098: -3430:../../../Source/third_party/fatfs/src/ff.c **** FREE_BUF(); -3431:../../../Source/third_party/fatfs/src/ff.c **** if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) -3432:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INVALID_NAME; -3433:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 7221 .loc 1 3433 0 - 7222 002c 0346 mov r3, r0 - 7223 002e 88B9 cbnz r0, .L702 -3434:../../../Source/third_party/fatfs/src/ff.c **** dir = dj.dir; - 7224 .loc 1 3434 0 - 7225 0030 0A9B ldr r3, [sp, #40] - 7226 .LVL1099: -3435:../../../Source/third_party/fatfs/src/ff.c **** if (!dir) { /* Is it a root directory? */ - 7227 .loc 1 3435 0 - 7228 0032 73B1 cbz r3, .L703 -3436:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INVALID_NAME; -3437:../../../Source/third_party/fatfs/src/ff.c **** } else { /* File or sub directory */ -3438:../../../Source/third_party/fatfs/src/ff.c **** mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ - 7229 .loc 1 3438 0 - 7230 0034 05F02705 and r5, r5, #39 - 7231 .LVL1100: -3439:../../../Source/third_party/fatfs/src/ff.c **** dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ - 7232 .loc 1 3439 0 - 7233 0038 DA7A ldrb r2, [r3, #11] @ zero_extendqisi2 - 7234 003a 22EA0502 bic r2, r2, r5 - 7235 003e 2C40 ands r4, r4, r5 - 7236 0040 1443 orrs r4, r4, r2 - 7237 0042 DC72 strb r4, [r3, #11] -3440:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->wflag = 1; - 7238 .loc 1 3440 0 - 7239 0044 0598 ldr r0, [sp, #20] - 7240 .LVL1101: - 7241 0046 0123 movs r3, #1 - 7242 .LVL1102: - 7243 0048 0371 strb r3, [r0, #4] -3441:../../../Source/third_party/fatfs/src/ff.c **** res = sync_fs(dj.fs); - 7244 .loc 1 3441 0 - 7245 004a FFF7FEFF bl sync_fs - 7246 .LVL1103: - 7247 004e 0346 mov r3, r0 - 7248 .LVL1104: - 7249 0050 00E0 b .L702 - 7250 .LVL1105: - 7251 .L703: -3436:../../../Source/third_party/fatfs/src/ff.c **** } else { /* File or sub directory */ - 7252 .loc 1 3436 0 - 7253 0052 0623 movs r3, #6 - 7254 .LVL1106: - 7255 .L702: -3442:../../../Source/third_party/fatfs/src/ff.c **** } -3443:../../../Source/third_party/fatfs/src/ff.c **** } -3444:../../../Source/third_party/fatfs/src/ff.c **** } -3445:../../../Source/third_party/fatfs/src/ff.c **** -3446:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(dj.fs, res); -3447:../../../Source/third_party/fatfs/src/ff.c **** } - 7256 .loc 1 3447 0 - 7257 0054 1846 mov r0, r3 - 7258 0056 0FB0 add sp, sp, #60 - 7259 .cfi_def_cfa_offset 12 - 7260 @ sp needed - 7261 0058 30BD pop {r4, r5, pc} - 7262 .LVL1107: - 7263 .L706: - 7264 005a 00BF .align 2 - 7265 .L705: - 7266 005c 00000000 .word .LANCHOR4 - 7267 .cfi_endproc - 7268 .LFE46: - 7270 .section .text.f_utime,"ax",%progbits - 7271 .align 2 - 7272 .global f_utime - 7273 .thumb - 7274 .thumb_func - 7276 f_utime: - 7277 .LFB47: -3448:../../../Source/third_party/fatfs/src/ff.c **** -3449:../../../Source/third_party/fatfs/src/ff.c **** -3450:../../../Source/third_party/fatfs/src/ff.c **** -3451:../../../Source/third_party/fatfs/src/ff.c **** -3452:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3453:../../../Source/third_party/fatfs/src/ff.c **** /* Change Timestamp */ -3454:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3455:../../../Source/third_party/fatfs/src/ff.c **** -3456:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_utime ( -3457:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *path, /* Pointer to the file/directory name */ -3458:../../../Source/third_party/fatfs/src/ff.c **** const FILINFO *fno /* Pointer to the time stamp to be set */ -3459:../../../Source/third_party/fatfs/src/ff.c **** ) -3460:../../../Source/third_party/fatfs/src/ff.c **** { - 7278 .loc 1 3460 0 - 7279 .cfi_startproc - 7280 @ args = 0, pretend = 0, frame = 56 - 7281 @ frame_needed = 0, uses_anonymous_args = 0 - 7282 .LVL1108: - 7283 0000 10B5 push {r4, lr} - 7284 .cfi_def_cfa_offset 8 - 7285 .cfi_offset 4, -8 - 7286 .cfi_offset 14, -4 - 7287 0002 8EB0 sub sp, sp, #56 - 7288 .cfi_def_cfa_offset 64 - 7289 0004 0EAB add r3, sp, #56 - 7290 0006 43F8340D str r0, [r3, #-52]! - 7291 000a 0C46 mov r4, r1 -3461:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -3462:../../../Source/third_party/fatfs/src/ff.c **** DIR dj; -3463:../../../Source/third_party/fatfs/src/ff.c **** BYTE *dir; -3464:../../../Source/third_party/fatfs/src/ff.c **** DEF_NAMEBUF; -3465:../../../Source/third_party/fatfs/src/ff.c **** -3466:../../../Source/third_party/fatfs/src/ff.c **** -3467:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&path, &dj.fs, 1); - 7292 .loc 1 3467 0 - 7293 000c 1846 mov r0, r3 - 7294 .LVL1109: - 7295 000e 05A9 add r1, sp, #20 - 7296 .LVL1110: - 7297 0010 0122 movs r2, #1 - 7298 0012 FFF7FEFF bl chk_mounted - 7299 .LVL1111: -3468:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 7300 .loc 1 3468 0 - 7301 0016 0346 mov r3, r0 - 7302 0018 E8B9 cbnz r0, .L708 -3469:../../../Source/third_party/fatfs/src/ff.c **** INIT_BUF(dj); - 7303 .loc 1 3469 0 - 7304 001a 02AB add r3, sp, #8 - 7305 001c 0B93 str r3, [sp, #44] - 7306 001e 0F4B ldr r3, .L711 - 7307 0020 0C93 str r3, [sp, #48] -3470:../../../Source/third_party/fatfs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ - 7308 .loc 1 3470 0 - 7309 0022 05A8 add r0, sp, #20 - 7310 .LVL1112: - 7311 0024 0199 ldr r1, [sp, #4] - 7312 0026 FFF7FEFF bl follow_path - 7313 .LVL1113: -3471:../../../Source/third_party/fatfs/src/ff.c **** FREE_BUF(); -3472:../../../Source/third_party/fatfs/src/ff.c **** if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) -3473:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INVALID_NAME; -3474:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 7314 .loc 1 3474 0 - 7315 002a 0346 mov r3, r0 - 7316 002c 98B9 cbnz r0, .L708 -3475:../../../Source/third_party/fatfs/src/ff.c **** dir = dj.dir; - 7317 .loc 1 3475 0 - 7318 002e 0A9B ldr r3, [sp, #40] - 7319 .LVL1114: -3476:../../../Source/third_party/fatfs/src/ff.c **** if (!dir) { /* Root directory */ - 7320 .loc 1 3476 0 - 7321 0030 83B1 cbz r3, .L709 -3477:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INVALID_NAME; -3478:../../../Source/third_party/fatfs/src/ff.c **** } else { /* File or sub-directory */ -3479:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+DIR_WrtTime, fno->ftime); - 7322 .loc 1 3479 0 - 7323 0032 E288 ldrh r2, [r4, #6] - 7324 0034 9A75 strb r2, [r3, #22] - 7325 0036 E288 ldrh r2, [r4, #6] - 7326 0038 120A lsrs r2, r2, #8 - 7327 003a DA75 strb r2, [r3, #23] -3480:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+DIR_WrtDate, fno->fdate); - 7328 .loc 1 3480 0 - 7329 003c A288 ldrh r2, [r4, #4] - 7330 003e 1A76 strb r2, [r3, #24] - 7331 0040 A288 ldrh r2, [r4, #4] - 7332 0042 120A lsrs r2, r2, #8 - 7333 0044 5A76 strb r2, [r3, #25] -3481:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->wflag = 1; - 7334 .loc 1 3481 0 - 7335 0046 0598 ldr r0, [sp, #20] - 7336 .LVL1115: - 7337 0048 0123 movs r3, #1 - 7338 .LVL1116: - 7339 004a 0371 strb r3, [r0, #4] -3482:../../../Source/third_party/fatfs/src/ff.c **** res = sync_fs(dj.fs); - 7340 .loc 1 3482 0 - 7341 004c FFF7FEFF bl sync_fs - 7342 .LVL1117: - 7343 0050 0346 mov r3, r0 - 7344 .LVL1118: - 7345 0052 00E0 b .L708 - 7346 .LVL1119: - 7347 .L709: -3477:../../../Source/third_party/fatfs/src/ff.c **** } else { /* File or sub-directory */ - 7348 .loc 1 3477 0 - 7349 0054 0623 movs r3, #6 - 7350 .LVL1120: - 7351 .L708: -3483:../../../Source/third_party/fatfs/src/ff.c **** } -3484:../../../Source/third_party/fatfs/src/ff.c **** } -3485:../../../Source/third_party/fatfs/src/ff.c **** } -3486:../../../Source/third_party/fatfs/src/ff.c **** -3487:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(dj.fs, res); -3488:../../../Source/third_party/fatfs/src/ff.c **** } - 7352 .loc 1 3488 0 - 7353 0056 1846 mov r0, r3 - 7354 0058 0EB0 add sp, sp, #56 - 7355 .cfi_def_cfa_offset 8 - 7356 .LVL1121: - 7357 @ sp needed - 7358 005a 10BD pop {r4, pc} - 7359 .LVL1122: - 7360 .L712: - 7361 .align 2 - 7362 .L711: - 7363 005c 00000000 .word .LANCHOR4 - 7364 .cfi_endproc - 7365 .LFE47: - 7367 .section .text.f_rename,"ax",%progbits - 7368 .align 2 - 7369 .global f_rename - 7370 .thumb - 7371 .thumb_func - 7373 f_rename: - 7374 .LFB48: -3489:../../../Source/third_party/fatfs/src/ff.c **** -3490:../../../Source/third_party/fatfs/src/ff.c **** -3491:../../../Source/third_party/fatfs/src/ff.c **** -3492:../../../Source/third_party/fatfs/src/ff.c **** -3493:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3494:../../../Source/third_party/fatfs/src/ff.c **** /* Rename File/Directory */ -3495:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3496:../../../Source/third_party/fatfs/src/ff.c **** -3497:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_rename ( -3498:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *path_old, /* Pointer to the old name */ -3499:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR *path_new /* Pointer to the new name */ -3500:../../../Source/third_party/fatfs/src/ff.c **** ) -3501:../../../Source/third_party/fatfs/src/ff.c **** { - 7375 .loc 1 3501 0 - 7376 .cfi_startproc - 7377 @ args = 0, pretend = 0, frame = 120 - 7378 @ frame_needed = 0, uses_anonymous_args = 0 - 7379 .LVL1123: - 7380 0000 30B5 push {r4, r5, lr} - 7381 .cfi_def_cfa_offset 12 - 7382 .cfi_offset 4, -12 - 7383 .cfi_offset 5, -8 - 7384 .cfi_offset 14, -4 - 7385 0002 9FB0 sub sp, sp, #124 - 7386 .cfi_def_cfa_offset 136 - 7387 0004 1EAB add r3, sp, #120 - 7388 0006 43F8740D str r0, [r3, #-116]! - 7389 000a 0C46 mov r4, r1 -3502:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -3503:../../../Source/third_party/fatfs/src/ff.c **** DIR djo, djn; -3504:../../../Source/third_party/fatfs/src/ff.c **** BYTE buf[21], *dir; -3505:../../../Source/third_party/fatfs/src/ff.c **** DWORD dw; -3506:../../../Source/third_party/fatfs/src/ff.c **** DEF_NAMEBUF; -3507:../../../Source/third_party/fatfs/src/ff.c **** -3508:../../../Source/third_party/fatfs/src/ff.c **** -3509:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&path_old, &djo.fs, 1); - 7390 .loc 1 3509 0 - 7391 000c 1846 mov r0, r3 - 7392 .LVL1124: - 7393 000e 15A9 add r1, sp, #84 - 7394 .LVL1125: - 7395 0010 0122 movs r2, #1 - 7396 0012 FFF7FEFF bl chk_mounted - 7397 .LVL1126: -3510:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 7398 .loc 1 3510 0 - 7399 0016 0346 mov r3, r0 - 7400 0018 0028 cmp r0, #0 - 7401 001a 7ED1 bne .L724 -3511:../../../Source/third_party/fatfs/src/ff.c **** djn.fs = djo.fs; - 7402 .loc 1 3511 0 - 7403 001c 159B ldr r3, [sp, #84] - 7404 001e 0C93 str r3, [sp, #48] -3512:../../../Source/third_party/fatfs/src/ff.c **** INIT_BUF(djo); - 7405 .loc 1 3512 0 - 7406 0020 03AB add r3, sp, #12 - 7407 0022 1B93 str r3, [sp, #108] - 7408 0024 3E4B ldr r3, .L726 - 7409 0026 1C93 str r3, [sp, #112] -3513:../../../Source/third_party/fatfs/src/ff.c **** res = follow_path(&djo, path_old); /* Check old object */ - 7410 .loc 1 3513 0 - 7411 0028 15A8 add r0, sp, #84 - 7412 .LVL1127: - 7413 002a 0199 ldr r1, [sp, #4] - 7414 002c FFF7FEFF bl follow_path - 7415 .LVL1128: -3514:../../../Source/third_party/fatfs/src/ff.c **** if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT)) -3515:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INVALID_NAME; -3516:../../../Source/third_party/fatfs/src/ff.c **** #if _FS_LOCK -3517:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) res = chk_lock(&djo, 2); -3518:../../../Source/third_party/fatfs/src/ff.c **** #endif -3519:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { /* Old object is found */ - 7416 .loc 1 3519 0 - 7417 0030 0346 mov r3, r0 - 7418 0032 0028 cmp r0, #0 - 7419 0034 71D1 bne .L724 -3520:../../../Source/third_party/fatfs/src/ff.c **** if (!djo.dir) { /* Is root dir? */ - 7420 .loc 1 3520 0 - 7421 0036 1A99 ldr r1, [sp, #104] - 7422 0038 0029 cmp r1, #0 - 7423 003a 62D0 beq .L720 -3521:../../../Source/third_party/fatfs/src/ff.c **** res = FR_NO_FILE; -3522:../../../Source/third_party/fatfs/src/ff.c **** } else { -3523:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */ - 7424 .loc 1 3523 0 - 7425 003c 06A8 add r0, sp, #24 - 7426 .LVL1129: - 7427 003e 0B31 adds r1, r1, #11 - 7428 0040 1522 movs r2, #21 - 7429 0042 FFF7FEFF bl mem_cpy - 7430 .LVL1130: -3524:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(&djn, &djo, sizeof (DIR)); /* Check new object */ - 7431 .loc 1 3524 0 - 7432 0046 0CA8 add r0, sp, #48 - 7433 0048 15A9 add r1, sp, #84 - 7434 004a 2422 movs r2, #36 - 7435 004c FFF7FEFF bl mem_cpy - 7436 .LVL1131: -3525:../../../Source/third_party/fatfs/src/ff.c **** res = follow_path(&djn, path_new); - 7437 .loc 1 3525 0 - 7438 0050 0CA8 add r0, sp, #48 - 7439 0052 2146 mov r1, r4 - 7440 0054 FFF7FEFF bl follow_path - 7441 .LVL1132: -3526:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */ - 7442 .loc 1 3526 0 - 7443 0058 0346 mov r3, r0 - 7444 005a 0028 cmp r0, #0 - 7445 005c 53D0 beq .L721 -3527:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */ - 7446 .loc 1 3527 0 - 7447 005e 0428 cmp r0, #4 - 7448 0060 5BD1 bne .L724 -3528:../../../Source/third_party/fatfs/src/ff.c **** /* Start critical section that any interruption can cause a cross-link */ -3529:../../../Source/third_party/fatfs/src/ff.c **** res = dir_register(&djn); /* Register the new entry */ - 7449 .loc 1 3529 0 - 7450 0062 0CA8 add r0, sp, #48 - 7451 .LVL1133: - 7452 0064 FFF7FEFF bl dir_register - 7453 .LVL1134: -3530:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { - 7454 .loc 1 3530 0 - 7455 0068 0346 mov r3, r0 - 7456 006a 0028 cmp r0, #0 - 7457 006c 55D1 bne .L724 -3531:../../../Source/third_party/fatfs/src/ff.c **** dir = djn.dir; /* Copy object information except for name */ - 7458 .loc 1 3531 0 - 7459 006e 119C ldr r4, [sp, #68] - 7460 .LVL1135: -3532:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(dir+13, buf+2, 19); - 7461 .loc 1 3532 0 - 7462 0070 04F10D00 add r0, r4, #13 - 7463 .LVL1136: - 7464 0074 0DF11A01 add r1, sp, #26 - 7465 0078 1322 movs r2, #19 - 7466 007a FFF7FEFF bl mem_cpy - 7467 .LVL1137: -3533:../../../Source/third_party/fatfs/src/ff.c **** dir[DIR_Attr] = buf[0] | AM_ARC; - 7468 .loc 1 3533 0 - 7469 007e 9DF81830 ldrb r3, [sp, #24] @ zero_extendqisi2 - 7470 0082 43F02003 orr r3, r3, #32 - 7471 0086 E372 strb r3, [r4, #11] -3534:../../../Source/third_party/fatfs/src/ff.c **** djo.fs->wflag = 1; - 7472 .loc 1 3534 0 - 7473 0088 159D ldr r5, [sp, #84] - 7474 008a 0123 movs r3, #1 - 7475 008c 2B71 strb r3, [r5, #4] -3535:../../../Source/third_party/fatfs/src/ff.c **** if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the direct - 7476 .loc 1 3535 0 - 7477 008e 0E9B ldr r3, [sp, #56] - 7478 0090 179A ldr r2, [sp, #92] - 7479 0092 9A42 cmp r2, r3 - 7480 0094 3BD0 beq .L715 - 7481 .loc 1 3535 0 is_stmt 0 discriminator 1 - 7482 0096 E37A ldrb r3, [r4, #11] @ zero_extendqisi2 - 7483 0098 13F0100F tst r3, #16 - 7484 009c 37D0 beq .L715 -3536:../../../Source/third_party/fatfs/src/ff.c **** dw = clust2sect(djo.fs, ld_clust(djo.fs, dir)); - 7485 .loc 1 3536 0 is_stmt 1 - 7486 009e 2846 mov r0, r5 - 7487 00a0 2146 mov r1, r4 - 7488 00a2 FFF7FEFF bl ld_clust - 7489 .LVL1138: - 7490 00a6 0146 mov r1, r0 - 7491 00a8 2846 mov r0, r5 - 7492 00aa FFF7FEFF bl clust2sect - 7493 .LVL1139: -3537:../../../Source/third_party/fatfs/src/ff.c **** if (!dw) { - 7494 .loc 1 3537 0 - 7495 00ae 0146 mov r1, r0 - 7496 00b0 58B3 cbz r0, .L722 -3538:../../../Source/third_party/fatfs/src/ff.c **** res = FR_INT_ERR; -3539:../../../Source/third_party/fatfs/src/ff.c **** } else { -3540:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(djo.fs, dw); - 7497 .loc 1 3540 0 - 7498 00b2 2846 mov r0, r5 - 7499 .LVL1140: - 7500 00b4 FFF7FEFF bl move_window - 7501 .LVL1141: -3541:../../../Source/third_party/fatfs/src/ff.c **** dir = djo.fs->win+SZ_DIR; /* .. entry */ - 7502 .loc 1 3541 0 - 7503 00b8 159A ldr r2, [sp, #84] - 7504 .LVL1142: -3542:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK && dir[1] == '.') { - 7505 .loc 1 3542 0 - 7506 00ba 0346 mov r3, r0 - 7507 00bc 68BB cbnz r0, .L724 - 7508 .loc 1 3542 0 is_stmt 0 discriminator 1 - 7509 00be 92F85530 ldrb r3, [r2, #85] @ zero_extendqisi2 - 7510 00c2 2E2B cmp r3, #46 - 7511 00c4 23D1 bne .L715 -3543:../../../Source/third_party/fatfs/src/ff.c **** dw = (djo.fs->fs_type == FS_FAT32 && djn.sclust == djo.fs->dirbase) ? 0 : djn.sclust; - 7512 .loc 1 3543 0 is_stmt 1 - 7513 00c6 1378 ldrb r3, [r2] @ zero_extendqisi2 - 7514 00c8 032B cmp r3, #3 - 7515 00ca 03D1 bne .L717 - 7516 .loc 1 3543 0 is_stmt 0 discriminator 2 - 7517 00cc 936A ldr r3, [r2, #40] - 7518 00ce 0E99 ldr r1, [sp, #56] - 7519 00d0 9942 cmp r1, r3 - 7520 00d2 01D0 beq .L723 - 7521 .L717: - 7522 .loc 1 3543 0 discriminator 3 - 7523 00d4 0E9B ldr r3, [sp, #56] - 7524 00d6 00E0 b .L718 - 7525 .L723: - 7526 .loc 1 3543 0 - 7527 00d8 0023 movs r3, #0 - 7528 .L718: - 7529 .LVL1143: - 7530 .LBB103: - 7531 .LBB104: -1261:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(dir+DIR_FstClusHI, cl >> 16); - 7532 .loc 1 1261 0 is_stmt 1 discriminator 6 - 7533 00da 82F86E30 strb r3, [r2, #110] - 7534 00de C3F30721 ubfx r1, r3, #8, #8 - 7535 00e2 82F86F10 strb r1, [r2, #111] -1262:../../../Source/third_party/fatfs/src/ff.c **** } - 7536 .loc 1 1262 0 discriminator 6 - 7537 00e6 1B0C lsrs r3, r3, #16 - 7538 .LVL1144: - 7539 00e8 82F86830 strb r3, [r2, #104] - 7540 00ec 1B0A lsrs r3, r3, #8 - 7541 00ee 82F86930 strb r3, [r2, #105] - 7542 .LBE104: - 7543 .LBE103: -3544:../../../Source/third_party/fatfs/src/ff.c **** st_clust(dir, dw); -3545:../../../Source/third_party/fatfs/src/ff.c **** djo.fs->wflag = 1; - 7544 .loc 1 3545 0 discriminator 6 - 7545 00f2 0123 movs r3, #1 - 7546 00f4 1371 strb r3, [r2, #4] - 7547 00f6 0AE0 b .L715 - 7548 .LVL1145: - 7549 .L719: -3546:../../../Source/third_party/fatfs/src/ff.c **** } -3547:../../../Source/third_party/fatfs/src/ff.c **** } -3548:../../../Source/third_party/fatfs/src/ff.c **** } -3549:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -3550:../../../Source/third_party/fatfs/src/ff.c **** res = dir_remove(&djo); /* Remove old entry */ -3551:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) -3552:../../../Source/third_party/fatfs/src/ff.c **** res = sync_fs(djo.fs); - 7550 .loc 1 3552 0 - 7551 00f8 1598 ldr r0, [sp, #84] - 7552 .LVL1146: - 7553 00fa FFF7FEFF bl sync_fs - 7554 .LVL1147: - 7555 00fe 0346 mov r3, r0 - 7556 .LVL1148: - 7557 0100 0BE0 b .L724 - 7558 .LVL1149: - 7559 .L720: -3521:../../../Source/third_party/fatfs/src/ff.c **** } else { - 7560 .loc 1 3521 0 - 7561 0102 0423 movs r3, #4 - 7562 0104 09E0 b .L724 - 7563 .L721: -3526:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */ - 7564 .loc 1 3526 0 - 7565 0106 0823 movs r3, #8 - 7566 0108 07E0 b .L724 - 7567 .LVL1150: - 7568 .L722: -3538:../../../Source/third_party/fatfs/src/ff.c **** } else { - 7569 .loc 1 3538 0 - 7570 010a 0223 movs r3, #2 - 7571 .LVL1151: - 7572 010c 05E0 b .L724 - 7573 .LVL1152: - 7574 .L715: -3550:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) - 7575 .loc 1 3550 0 - 7576 010e 15A8 add r0, sp, #84 - 7577 0110 FFF7FEFF bl dir_remove - 7578 .LVL1153: -3551:../../../Source/third_party/fatfs/src/ff.c **** res = sync_fs(djo.fs); - 7579 .loc 1 3551 0 - 7580 0114 0346 mov r3, r0 - 7581 0116 0028 cmp r0, #0 - 7582 0118 EED0 beq .L719 - 7583 .LVL1154: - 7584 .L724: -3553:../../../Source/third_party/fatfs/src/ff.c **** } -3554:../../../Source/third_party/fatfs/src/ff.c **** } -3555:../../../Source/third_party/fatfs/src/ff.c **** /* End critical section */ -3556:../../../Source/third_party/fatfs/src/ff.c **** } -3557:../../../Source/third_party/fatfs/src/ff.c **** } -3558:../../../Source/third_party/fatfs/src/ff.c **** } -3559:../../../Source/third_party/fatfs/src/ff.c **** FREE_BUF(); -3560:../../../Source/third_party/fatfs/src/ff.c **** } -3561:../../../Source/third_party/fatfs/src/ff.c **** -3562:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(djo.fs, res); -3563:../../../Source/third_party/fatfs/src/ff.c **** } - 7585 .loc 1 3563 0 - 7586 011a 1846 mov r0, r3 - 7587 011c 1FB0 add sp, sp, #124 - 7588 .cfi_def_cfa_offset 12 - 7589 @ sp needed - 7590 011e 30BD pop {r4, r5, pc} - 7591 .LVL1155: - 7592 .L727: - 7593 .align 2 - 7594 .L726: - 7595 0120 00000000 .word .LANCHOR4 - 7596 .cfi_endproc - 7597 .LFE48: - 7599 .section .text.f_gets,"ax",%progbits - 7600 .align 2 - 7601 .global f_gets - 7602 .thumb - 7603 .thumb_func - 7605 f_gets: - 7606 .LFB49: -3564:../../../Source/third_party/fatfs/src/ff.c **** -3565:../../../Source/third_party/fatfs/src/ff.c **** #endif /* !_FS_READONLY */ -3566:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _FS_MINIMIZE == 0 */ -3567:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _FS_MINIMIZE <= 1 */ -3568:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _FS_MINIMIZE <= 2 */ -3569:../../../Source/third_party/fatfs/src/ff.c **** -3570:../../../Source/third_party/fatfs/src/ff.c **** -3571:../../../Source/third_party/fatfs/src/ff.c **** -3572:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LABEL -3573:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3574:../../../Source/third_party/fatfs/src/ff.c **** /* Get volume label */ -3575:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3576:../../../Source/third_party/fatfs/src/ff.c **** -3577:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_getlabel ( -3578:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR* path, /* Path name of the logical drive number */ -3579:../../../Source/third_party/fatfs/src/ff.c **** TCHAR* label, /* Pointer to a buffer to return the volume label */ -3580:../../../Source/third_party/fatfs/src/ff.c **** DWORD* sn /* Pointer to a variable to return the volume serial number */ -3581:../../../Source/third_party/fatfs/src/ff.c **** ) -3582:../../../Source/third_party/fatfs/src/ff.c **** { -3583:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -3584:../../../Source/third_party/fatfs/src/ff.c **** DIR dj; -3585:../../../Source/third_party/fatfs/src/ff.c **** UINT i, j; -3586:../../../Source/third_party/fatfs/src/ff.c **** -3587:../../../Source/third_party/fatfs/src/ff.c **** -3588:../../../Source/third_party/fatfs/src/ff.c **** /* Get logical drive */ -3589:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&path, &dj.fs, 0); -3590:../../../Source/third_party/fatfs/src/ff.c **** -3591:../../../Source/third_party/fatfs/src/ff.c **** /* Get volume label */ -3592:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK && label) { -3593:../../../Source/third_party/fatfs/src/ff.c **** dj.sclust = 0; /* Open root dir */ -3594:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(&dj, 0); -3595:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -3596:../../../Source/third_party/fatfs/src/ff.c **** res = dir_read(&dj, 1); /* Get an entry with AM_VOL */ -3597:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { /* A volume label is exist */ -3598:../../../Source/third_party/fatfs/src/ff.c **** #if _LFN_UNICODE -3599:../../../Source/third_party/fatfs/src/ff.c **** WCHAR w; -3600:../../../Source/third_party/fatfs/src/ff.c **** i = j = 0; -3601:../../../Source/third_party/fatfs/src/ff.c **** do { -3602:../../../Source/third_party/fatfs/src/ff.c **** w = (i < 11) ? dj.dir[i++] : ' '; -3603:../../../Source/third_party/fatfs/src/ff.c **** if (IsDBCS1(w) && i < 11 && IsDBCS2(dj.dir[i])) -3604:../../../Source/third_party/fatfs/src/ff.c **** w = (w << 8) | dj.dir[i++]; -3605:../../../Source/third_party/fatfs/src/ff.c **** label[j++] = ff_convert(w, 1); -3606:../../../Source/third_party/fatfs/src/ff.c **** } while (j < 11); -3607:../../../Source/third_party/fatfs/src/ff.c **** #else -3608:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(label, dj.dir, 11); -3609:../../../Source/third_party/fatfs/src/ff.c **** #endif -3610:../../../Source/third_party/fatfs/src/ff.c **** j = 11; -3611:../../../Source/third_party/fatfs/src/ff.c **** do { -3612:../../../Source/third_party/fatfs/src/ff.c **** label[j] = 0; -3613:../../../Source/third_party/fatfs/src/ff.c **** if (!j) break; -3614:../../../Source/third_party/fatfs/src/ff.c **** } while (label[--j] == ' '); -3615:../../../Source/third_party/fatfs/src/ff.c **** } -3616:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) { /* No label, return nul string */ -3617:../../../Source/third_party/fatfs/src/ff.c **** label[0] = 0; -3618:../../../Source/third_party/fatfs/src/ff.c **** res = FR_OK; -3619:../../../Source/third_party/fatfs/src/ff.c **** } -3620:../../../Source/third_party/fatfs/src/ff.c **** } -3621:../../../Source/third_party/fatfs/src/ff.c **** } -3622:../../../Source/third_party/fatfs/src/ff.c **** -3623:../../../Source/third_party/fatfs/src/ff.c **** /* Get volume serial number */ -3624:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK && sn) { -3625:../../../Source/third_party/fatfs/src/ff.c **** res = move_window(dj.fs, dj.fs->volbase); -3626:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -3627:../../../Source/third_party/fatfs/src/ff.c **** i = dj.fs->fs_type == FS_FAT32 ? BS_VolID32 : BS_VolID; -3628:../../../Source/third_party/fatfs/src/ff.c **** *sn = LD_DWORD(&dj.fs->win[i]); -3629:../../../Source/third_party/fatfs/src/ff.c **** } -3630:../../../Source/third_party/fatfs/src/ff.c **** } -3631:../../../Source/third_party/fatfs/src/ff.c **** -3632:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(dj.fs, res); -3633:../../../Source/third_party/fatfs/src/ff.c **** } -3634:../../../Source/third_party/fatfs/src/ff.c **** -3635:../../../Source/third_party/fatfs/src/ff.c **** -3636:../../../Source/third_party/fatfs/src/ff.c **** -3637:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -3638:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3639:../../../Source/third_party/fatfs/src/ff.c **** /* Set volume label */ -3640:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3641:../../../Source/third_party/fatfs/src/ff.c **** -3642:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_setlabel ( -3643:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR* label /* Pointer to the volume label to set */ -3644:../../../Source/third_party/fatfs/src/ff.c **** ) -3645:../../../Source/third_party/fatfs/src/ff.c **** { -3646:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -3647:../../../Source/third_party/fatfs/src/ff.c **** DIR dj; -3648:../../../Source/third_party/fatfs/src/ff.c **** BYTE vn[11]; -3649:../../../Source/third_party/fatfs/src/ff.c **** UINT i, j, sl; -3650:../../../Source/third_party/fatfs/src/ff.c **** WCHAR w; -3651:../../../Source/third_party/fatfs/src/ff.c **** DWORD tm; -3652:../../../Source/third_party/fatfs/src/ff.c **** -3653:../../../Source/third_party/fatfs/src/ff.c **** -3654:../../../Source/third_party/fatfs/src/ff.c **** /* Get logical drive */ -3655:../../../Source/third_party/fatfs/src/ff.c **** res = chk_mounted(&label, &dj.fs, 1); -3656:../../../Source/third_party/fatfs/src/ff.c **** if (res) LEAVE_FF(dj.fs, res); -3657:../../../Source/third_party/fatfs/src/ff.c **** -3658:../../../Source/third_party/fatfs/src/ff.c **** /* Create a volume label in directory form */ -3659:../../../Source/third_party/fatfs/src/ff.c **** vn[0] = 0; -3660:../../../Source/third_party/fatfs/src/ff.c **** for (sl = 0; label[sl]; sl++) ; /* Get name length */ -3661:../../../Source/third_party/fatfs/src/ff.c **** for ( ; sl && label[sl-1] == ' '; sl--) ; /* Remove trailing spaces */ -3662:../../../Source/third_party/fatfs/src/ff.c **** if (sl) { /* Create volume label in directory form */ -3663:../../../Source/third_party/fatfs/src/ff.c **** i = j = 0; -3664:../../../Source/third_party/fatfs/src/ff.c **** do { -3665:../../../Source/third_party/fatfs/src/ff.c **** #if _LFN_UNICODE -3666:../../../Source/third_party/fatfs/src/ff.c **** w = ff_convert(ff_wtoupper(label[i++]), 0); -3667:../../../Source/third_party/fatfs/src/ff.c **** #else -3668:../../../Source/third_party/fatfs/src/ff.c **** w = (BYTE)label[i++]; -3669:../../../Source/third_party/fatfs/src/ff.c **** if (IsDBCS1(w)) -3670:../../../Source/third_party/fatfs/src/ff.c **** w = (j < 10 && i < sl && IsDBCS2(label[i])) ? (w << 8) | (BYTE)label[i++] : 0; -3671:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_LFN -3672:../../../Source/third_party/fatfs/src/ff.c **** w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0); -3673:../../../Source/third_party/fatfs/src/ff.c **** #else -3674:../../../Source/third_party/fatfs/src/ff.c **** if (IsLower(w)) w -= 0x20; /* To upper ASCII chars */ -3675:../../../Source/third_party/fatfs/src/ff.c **** #ifdef _EXCVT -3676:../../../Source/third_party/fatfs/src/ff.c **** if (w >= 0x80) w = ExCvt[w - 0x80]; /* To upper extended chars (SBCS cfg) */ -3677:../../../Source/third_party/fatfs/src/ff.c **** #else -3678:../../../Source/third_party/fatfs/src/ff.c **** if (!_DF1S && w >= 0x80) w = 0; /* Reject extended chars (ASCII cfg) */ -3679:../../../Source/third_party/fatfs/src/ff.c **** #endif -3680:../../../Source/third_party/fatfs/src/ff.c **** #endif -3681:../../../Source/third_party/fatfs/src/ff.c **** #endif -3682:../../../Source/third_party/fatfs/src/ff.c **** if (!w || chk_chr("\"*+,.:;<=>\?[]|\x7F", w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) /* Reject i -3683:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(dj.fs, FR_INVALID_NAME); -3684:../../../Source/third_party/fatfs/src/ff.c **** if (w >= 0x100) vn[j++] = (BYTE)(w >> 8); -3685:../../../Source/third_party/fatfs/src/ff.c **** vn[j++] = (BYTE)w; -3686:../../../Source/third_party/fatfs/src/ff.c **** } while (i < sl); -3687:../../../Source/third_party/fatfs/src/ff.c **** while (j < 11) vn[j++] = ' '; -3688:../../../Source/third_party/fatfs/src/ff.c **** } -3689:../../../Source/third_party/fatfs/src/ff.c **** -3690:../../../Source/third_party/fatfs/src/ff.c **** /* Set volume label */ -3691:../../../Source/third_party/fatfs/src/ff.c **** dj.sclust = 0; /* Open root dir */ -3692:../../../Source/third_party/fatfs/src/ff.c **** res = dir_sdi(&dj, 0); -3693:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -3694:../../../Source/third_party/fatfs/src/ff.c **** res = dir_read(&dj, 1); /* Get an entry with AM_VOL */ -3695:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { /* A volume label is found */ -3696:../../../Source/third_party/fatfs/src/ff.c **** if (vn[0]) { -3697:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(dj.dir, vn, 11); /* Change the volume label name */ -3698:../../../Source/third_party/fatfs/src/ff.c **** tm = get_fattime(); -3699:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(dj.dir+DIR_WrtTime, tm); -3700:../../../Source/third_party/fatfs/src/ff.c **** } else { -3701:../../../Source/third_party/fatfs/src/ff.c **** dj.dir[0] = DDE; /* Remove the volume label */ -3702:../../../Source/third_party/fatfs/src/ff.c **** } -3703:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->wflag = 1; -3704:../../../Source/third_party/fatfs/src/ff.c **** res = sync_fs(dj.fs); -3705:../../../Source/third_party/fatfs/src/ff.c **** } else { /* No volume label is found or error */ -3706:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_NO_FILE) { -3707:../../../Source/third_party/fatfs/src/ff.c **** res = FR_OK; -3708:../../../Source/third_party/fatfs/src/ff.c **** if (vn[0]) { /* Create volume label as new */ -3709:../../../Source/third_party/fatfs/src/ff.c **** res = dir_alloc(&dj, 1); /* Allocate an entry for volume label */ -3710:../../../Source/third_party/fatfs/src/ff.c **** if (res == FR_OK) { -3711:../../../Source/third_party/fatfs/src/ff.c **** mem_set(dj.dir, 0, SZ_DIR); /* Set volume label */ -3712:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(dj.dir, vn, 11); -3713:../../../Source/third_party/fatfs/src/ff.c **** dj.dir[DIR_Attr] = AM_VOL; -3714:../../../Source/third_party/fatfs/src/ff.c **** tm = get_fattime(); -3715:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(dj.dir+DIR_WrtTime, tm); -3716:../../../Source/third_party/fatfs/src/ff.c **** dj.fs->wflag = 1; -3717:../../../Source/third_party/fatfs/src/ff.c **** res = sync_fs(dj.fs); -3718:../../../Source/third_party/fatfs/src/ff.c **** } -3719:../../../Source/third_party/fatfs/src/ff.c **** } -3720:../../../Source/third_party/fatfs/src/ff.c **** } -3721:../../../Source/third_party/fatfs/src/ff.c **** } -3722:../../../Source/third_party/fatfs/src/ff.c **** } -3723:../../../Source/third_party/fatfs/src/ff.c **** -3724:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(dj.fs, res); -3725:../../../Source/third_party/fatfs/src/ff.c **** } -3726:../../../Source/third_party/fatfs/src/ff.c **** -3727:../../../Source/third_party/fatfs/src/ff.c **** #endif /* !_FS_READONLY */ -3728:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _USE_LABEL */ -3729:../../../Source/third_party/fatfs/src/ff.c **** -3730:../../../Source/third_party/fatfs/src/ff.c **** -3731:../../../Source/third_party/fatfs/src/ff.c **** -3732:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3733:../../../Source/third_party/fatfs/src/ff.c **** /* Forward data to the stream directly (available on only tiny cfg) */ -3734:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3735:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_FORWARD && _FS_TINY -3736:../../../Source/third_party/fatfs/src/ff.c **** -3737:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_forward ( -3738:../../../Source/third_party/fatfs/src/ff.c **** FIL *fp, /* Pointer to the file object */ -3739:../../../Source/third_party/fatfs/src/ff.c **** UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ -3740:../../../Source/third_party/fatfs/src/ff.c **** UINT btf, /* Number of bytes to forward */ -3741:../../../Source/third_party/fatfs/src/ff.c **** UINT *bf /* Pointer to number of bytes forwarded */ -3742:../../../Source/third_party/fatfs/src/ff.c **** ) -3743:../../../Source/third_party/fatfs/src/ff.c **** { -3744:../../../Source/third_party/fatfs/src/ff.c **** FRESULT res; -3745:../../../Source/third_party/fatfs/src/ff.c **** DWORD remain, clst, sect; -3746:../../../Source/third_party/fatfs/src/ff.c **** UINT rcnt; -3747:../../../Source/third_party/fatfs/src/ff.c **** BYTE csect; -3748:../../../Source/third_party/fatfs/src/ff.c **** -3749:../../../Source/third_party/fatfs/src/ff.c **** -3750:../../../Source/third_party/fatfs/src/ff.c **** *bf = 0; /* Clear transfer byte counter */ -3751:../../../Source/third_party/fatfs/src/ff.c **** -3752:../../../Source/third_party/fatfs/src/ff.c **** res = validate(fp); /* Check validity of the object */ -3753:../../../Source/third_party/fatfs/src/ff.c **** if (res != FR_OK) LEAVE_FF(fp->fs, res); -3754:../../../Source/third_party/fatfs/src/ff.c **** if (fp->flag & FA__ERROR) /* Check error flag */ -3755:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, FR_INT_ERR); -3756:../../../Source/third_party/fatfs/src/ff.c **** if (!(fp->flag & FA_READ)) /* Check access mode */ -3757:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, FR_DENIED); -3758:../../../Source/third_party/fatfs/src/ff.c **** -3759:../../../Source/third_party/fatfs/src/ff.c **** remain = fp->fsize - fp->fptr; -3760:../../../Source/third_party/fatfs/src/ff.c **** if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */ -3761:../../../Source/third_party/fatfs/src/ff.c **** -3762:../../../Source/third_party/fatfs/src/ff.c **** for ( ; btf && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */ -3763:../../../Source/third_party/fatfs/src/ff.c **** fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { -3764:../../../Source/third_party/fatfs/src/ff.c **** csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ -3765:../../../Source/third_party/fatfs/src/ff.c **** if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ -3766:../../../Source/third_party/fatfs/src/ff.c **** if (!csect) { /* On the cluster boundary? */ -3767:../../../Source/third_party/fatfs/src/ff.c **** clst = (fp->fptr == 0) ? /* On the top of the file? */ -3768:../../../Source/third_party/fatfs/src/ff.c **** fp->sclust : get_fat(fp->fs, fp->clust); -3769:../../../Source/third_party/fatfs/src/ff.c **** if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); -3770:../../../Source/third_party/fatfs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); -3771:../../../Source/third_party/fatfs/src/ff.c **** fp->clust = clst; /* Update current cluster */ -3772:../../../Source/third_party/fatfs/src/ff.c **** } -3773:../../../Source/third_party/fatfs/src/ff.c **** } -3774:../../../Source/third_party/fatfs/src/ff.c **** sect = clust2sect(fp->fs, fp->clust); /* Get current data sector */ -3775:../../../Source/third_party/fatfs/src/ff.c **** if (!sect) ABORT(fp->fs, FR_INT_ERR); -3776:../../../Source/third_party/fatfs/src/ff.c **** sect += csect; -3777:../../../Source/third_party/fatfs/src/ff.c **** if (move_window(fp->fs, sect)) /* Move sector window */ -3778:../../../Source/third_party/fatfs/src/ff.c **** ABORT(fp->fs, FR_DISK_ERR); -3779:../../../Source/third_party/fatfs/src/ff.c **** fp->dsect = sect; -3780:../../../Source/third_party/fatfs/src/ff.c **** rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */ -3781:../../../Source/third_party/fatfs/src/ff.c **** if (rcnt > btf) rcnt = btf; -3782:../../../Source/third_party/fatfs/src/ff.c **** rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt); -3783:../../../Source/third_party/fatfs/src/ff.c **** if (!rcnt) ABORT(fp->fs, FR_INT_ERR); -3784:../../../Source/third_party/fatfs/src/ff.c **** } -3785:../../../Source/third_party/fatfs/src/ff.c **** -3786:../../../Source/third_party/fatfs/src/ff.c **** LEAVE_FF(fp->fs, FR_OK); -3787:../../../Source/third_party/fatfs/src/ff.c **** } -3788:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _USE_FORWARD */ -3789:../../../Source/third_party/fatfs/src/ff.c **** -3790:../../../Source/third_party/fatfs/src/ff.c **** -3791:../../../Source/third_party/fatfs/src/ff.c **** -3792:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_MKFS && !_FS_READONLY -3793:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3794:../../../Source/third_party/fatfs/src/ff.c **** /* Create File System on the Drive */ -3795:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -3796:../../../Source/third_party/fatfs/src/ff.c **** #define N_ROOTDIR 512 /* Number of root dir entries for FAT12/16 */ -3797:../../../Source/third_party/fatfs/src/ff.c **** #define N_FATS 1 /* Number of FAT copies (1 or 2) */ -3798:../../../Source/third_party/fatfs/src/ff.c **** -3799:../../../Source/third_party/fatfs/src/ff.c **** -3800:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_mkfs ( -3801:../../../Source/third_party/fatfs/src/ff.c **** BYTE vol, /* Logical drive number */ -3802:../../../Source/third_party/fatfs/src/ff.c **** BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */ -3803:../../../Source/third_party/fatfs/src/ff.c **** UINT au /* Allocation unit size [bytes] */ -3804:../../../Source/third_party/fatfs/src/ff.c **** ) -3805:../../../Source/third_party/fatfs/src/ff.c **** { -3806:../../../Source/third_party/fatfs/src/ff.c **** static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0}; -3807:../../../Source/third_party/fatfs/src/ff.c **** static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512}; -3808:../../../Source/third_party/fatfs/src/ff.c **** BYTE fmt, md, sys, *tbl, pdrv, part; -3809:../../../Source/third_party/fatfs/src/ff.c **** DWORD n_clst, vs, n, wsect; -3810:../../../Source/third_party/fatfs/src/ff.c **** UINT i; -3811:../../../Source/third_party/fatfs/src/ff.c **** DWORD b_vol, b_fat, b_dir, b_data; /* LBA */ -3812:../../../Source/third_party/fatfs/src/ff.c **** DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */ -3813:../../../Source/third_party/fatfs/src/ff.c **** FATFS *fs; -3814:../../../Source/third_party/fatfs/src/ff.c **** DSTATUS stat; -3815:../../../Source/third_party/fatfs/src/ff.c **** -3816:../../../Source/third_party/fatfs/src/ff.c **** -3817:../../../Source/third_party/fatfs/src/ff.c **** /* Check mounted drive and clear work area */ -3818:../../../Source/third_party/fatfs/src/ff.c **** if (vol >= _VOLUMES) return FR_INVALID_DRIVE; -3819:../../../Source/third_party/fatfs/src/ff.c **** if (sfd > 1) return FR_INVALID_PARAMETER; -3820:../../../Source/third_party/fatfs/src/ff.c **** if (au & (au - 1)) return FR_INVALID_PARAMETER; -3821:../../../Source/third_party/fatfs/src/ff.c **** fs = FatFs[vol]; -3822:../../../Source/third_party/fatfs/src/ff.c **** if (!fs) return FR_NOT_ENABLED; -3823:../../../Source/third_party/fatfs/src/ff.c **** fs->fs_type = 0; -3824:../../../Source/third_party/fatfs/src/ff.c **** pdrv = LD2PD(vol); /* Physical drive */ -3825:../../../Source/third_party/fatfs/src/ff.c **** part = LD2PT(vol); /* Partition (0:auto detect, 1-4:get from partition table)*/ -3826:../../../Source/third_party/fatfs/src/ff.c **** -3827:../../../Source/third_party/fatfs/src/ff.c **** /* Get disk statics */ -3828:../../../Source/third_party/fatfs/src/ff.c **** stat = disk_initialize(pdrv); -3829:../../../Source/third_party/fatfs/src/ff.c **** if (stat & STA_NOINIT) return FR_NOT_READY; -3830:../../../Source/third_party/fatfs/src/ff.c **** if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; -3831:../../../Source/third_party/fatfs/src/ff.c **** #if _MAX_SS != 512 /* Get disk sector size */ -3832:../../../Source/third_party/fatfs/src/ff.c **** if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS) -3833:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; -3834:../../../Source/third_party/fatfs/src/ff.c **** #endif -3835:../../../Source/third_party/fatfs/src/ff.c **** if (_MULTI_PARTITION && part) { -3836:../../../Source/third_party/fatfs/src/ff.c **** /* Get partition information from partition table in the MBR */ -3837:../../../Source/third_party/fatfs/src/ff.c **** if (disk_read(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR; -3838:../../../Source/third_party/fatfs/src/ff.c **** if (LD_WORD(fs->win+BS_55AA) != 0xAA55) return FR_MKFS_ABORTED; -3839:../../../Source/third_party/fatfs/src/ff.c **** tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; -3840:../../../Source/third_party/fatfs/src/ff.c **** if (!tbl[4]) return FR_MKFS_ABORTED; /* No partition? */ -3841:../../../Source/third_party/fatfs/src/ff.c **** b_vol = LD_DWORD(tbl+8); /* Volume start sector */ -3842:../../../Source/third_party/fatfs/src/ff.c **** n_vol = LD_DWORD(tbl+12); /* Volume size */ -3843:../../../Source/third_party/fatfs/src/ff.c **** } else { -3844:../../../Source/third_party/fatfs/src/ff.c **** /* Create a partition in this function */ -3845:../../../Source/third_party/fatfs/src/ff.c **** if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128) -3846:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; -3847:../../../Source/third_party/fatfs/src/ff.c **** b_vol = (sfd) ? 0 : 63; /* Volume start sector */ -3848:../../../Source/third_party/fatfs/src/ff.c **** n_vol -= b_vol; /* Volume size */ -3849:../../../Source/third_party/fatfs/src/ff.c **** } -3850:../../../Source/third_party/fatfs/src/ff.c **** -3851:../../../Source/third_party/fatfs/src/ff.c **** if (!au) { /* AU auto selection */ -3852:../../../Source/third_party/fatfs/src/ff.c **** vs = n_vol / (2000 / (SS(fs) / 512)); -3853:../../../Source/third_party/fatfs/src/ff.c **** for (i = 0; vs < vst[i]; i++) ; -3854:../../../Source/third_party/fatfs/src/ff.c **** au = cst[i]; -3855:../../../Source/third_party/fatfs/src/ff.c **** } -3856:../../../Source/third_party/fatfs/src/ff.c **** au /= SS(fs); /* Number of sectors per cluster */ -3857:../../../Source/third_party/fatfs/src/ff.c **** if (au == 0) au = 1; -3858:../../../Source/third_party/fatfs/src/ff.c **** if (au > 128) au = 128; -3859:../../../Source/third_party/fatfs/src/ff.c **** -3860:../../../Source/third_party/fatfs/src/ff.c **** /* Pre-compute number of clusters and FAT sub-type */ -3861:../../../Source/third_party/fatfs/src/ff.c **** n_clst = n_vol / au; -3862:../../../Source/third_party/fatfs/src/ff.c **** fmt = FS_FAT12; -3863:../../../Source/third_party/fatfs/src/ff.c **** if (n_clst >= MIN_FAT16) fmt = FS_FAT16; -3864:../../../Source/third_party/fatfs/src/ff.c **** if (n_clst >= MIN_FAT32) fmt = FS_FAT32; -3865:../../../Source/third_party/fatfs/src/ff.c **** -3866:../../../Source/third_party/fatfs/src/ff.c **** /* Determine offset and size of FAT structure */ -3867:../../../Source/third_party/fatfs/src/ff.c **** if (fmt == FS_FAT32) { -3868:../../../Source/third_party/fatfs/src/ff.c **** n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs); -3869:../../../Source/third_party/fatfs/src/ff.c **** n_rsv = 32; -3870:../../../Source/third_party/fatfs/src/ff.c **** n_dir = 0; -3871:../../../Source/third_party/fatfs/src/ff.c **** } else { -3872:../../../Source/third_party/fatfs/src/ff.c **** n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4; -3873:../../../Source/third_party/fatfs/src/ff.c **** n_fat = (n_fat + SS(fs) - 1) / SS(fs); -3874:../../../Source/third_party/fatfs/src/ff.c **** n_rsv = 1; -3875:../../../Source/third_party/fatfs/src/ff.c **** n_dir = (DWORD)N_ROOTDIR * SZ_DIR / SS(fs); -3876:../../../Source/third_party/fatfs/src/ff.c **** } -3877:../../../Source/third_party/fatfs/src/ff.c **** b_fat = b_vol + n_rsv; /* FAT area start sector */ -3878:../../../Source/third_party/fatfs/src/ff.c **** b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */ -3879:../../../Source/third_party/fatfs/src/ff.c **** b_data = b_dir + n_dir; /* Data area start sector */ -3880:../../../Source/third_party/fatfs/src/ff.c **** if (n_vol < b_data + au - b_vol) return FR_MKFS_ABORTED; /* Too small volume */ -3881:../../../Source/third_party/fatfs/src/ff.c **** -3882:../../../Source/third_party/fatfs/src/ff.c **** /* Align data start sector to erase block boundary (for flash memory media) */ -3883:../../../Source/third_party/fatfs/src/ff.c **** if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1; -3884:../../../Source/third_party/fatfs/src/ff.c **** n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */ -3885:../../../Source/third_party/fatfs/src/ff.c **** n = (n - b_data) / N_FATS; -3886:../../../Source/third_party/fatfs/src/ff.c **** if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */ -3887:../../../Source/third_party/fatfs/src/ff.c **** n_rsv += n; -3888:../../../Source/third_party/fatfs/src/ff.c **** b_fat += n; -3889:../../../Source/third_party/fatfs/src/ff.c **** } else { /* FAT12/16: Expand FAT size */ -3890:../../../Source/third_party/fatfs/src/ff.c **** n_fat += n; -3891:../../../Source/third_party/fatfs/src/ff.c **** } -3892:../../../Source/third_party/fatfs/src/ff.c **** -3893:../../../Source/third_party/fatfs/src/ff.c **** /* Determine number of clusters and final check of validity of the FAT sub-type */ -3894:../../../Source/third_party/fatfs/src/ff.c **** n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au; -3895:../../../Source/third_party/fatfs/src/ff.c **** if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16) -3896:../../../Source/third_party/fatfs/src/ff.c **** || (fmt == FS_FAT32 && n_clst < MIN_FAT32)) -3897:../../../Source/third_party/fatfs/src/ff.c **** return FR_MKFS_ABORTED; -3898:../../../Source/third_party/fatfs/src/ff.c **** -3899:../../../Source/third_party/fatfs/src/ff.c **** switch (fmt) { /* Determine system ID for partition table */ -3900:../../../Source/third_party/fatfs/src/ff.c **** case FS_FAT12: sys = 0x01; break; -3901:../../../Source/third_party/fatfs/src/ff.c **** case FS_FAT16: sys = (n_vol < 0x10000) ? 0x04 : 0x06; break; -3902:../../../Source/third_party/fatfs/src/ff.c **** default: sys = 0x0C; -3903:../../../Source/third_party/fatfs/src/ff.c **** } -3904:../../../Source/third_party/fatfs/src/ff.c **** -3905:../../../Source/third_party/fatfs/src/ff.c **** if (_MULTI_PARTITION && part) { -3906:../../../Source/third_party/fatfs/src/ff.c **** /* Update system ID in the partition table */ -3907:../../../Source/third_party/fatfs/src/ff.c **** tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; -3908:../../../Source/third_party/fatfs/src/ff.c **** tbl[4] = sys; -3909:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR; -3910:../../../Source/third_party/fatfs/src/ff.c **** md = 0xF8; -3911:../../../Source/third_party/fatfs/src/ff.c **** } else { -3912:../../../Source/third_party/fatfs/src/ff.c **** if (sfd) { /* No partition table (SFD) */ -3913:../../../Source/third_party/fatfs/src/ff.c **** md = 0xF0; -3914:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Create partition table (FDISK) */ -3915:../../../Source/third_party/fatfs/src/ff.c **** mem_set(fs->win, 0, SS(fs)); -3916:../../../Source/third_party/fatfs/src/ff.c **** tbl = fs->win+MBR_Table; /* Create partition table for single partition in the drive */ -3917:../../../Source/third_party/fatfs/src/ff.c **** tbl[1] = 1; /* Partition start head */ -3918:../../../Source/third_party/fatfs/src/ff.c **** tbl[2] = 1; /* Partition start sector */ -3919:../../../Source/third_party/fatfs/src/ff.c **** tbl[3] = 0; /* Partition start cylinder */ -3920:../../../Source/third_party/fatfs/src/ff.c **** tbl[4] = sys; /* System type */ -3921:../../../Source/third_party/fatfs/src/ff.c **** tbl[5] = 254; /* Partition end head */ -3922:../../../Source/third_party/fatfs/src/ff.c **** n = (b_vol + n_vol) / 63 / 255; -3923:../../../Source/third_party/fatfs/src/ff.c **** tbl[6] = (BYTE)((n >> 2) | 63); /* Partition end sector */ -3924:../../../Source/third_party/fatfs/src/ff.c **** tbl[7] = (BYTE)n; /* End cylinder */ -3925:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+8, 63); /* Partition start in LBA */ -3926:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */ -3927:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(fs->win+BS_55AA, 0xAA55); /* MBR signature */ -3928:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) /* Write it to the MBR sector */ -3929:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; -3930:../../../Source/third_party/fatfs/src/ff.c **** md = 0xF8; -3931:../../../Source/third_party/fatfs/src/ff.c **** } -3932:../../../Source/third_party/fatfs/src/ff.c **** } -3933:../../../Source/third_party/fatfs/src/ff.c **** -3934:../../../Source/third_party/fatfs/src/ff.c **** /* Create BPB in the VBR */ -3935:../../../Source/third_party/fatfs/src/ff.c **** tbl = fs->win; /* Clear sector */ -3936:../../../Source/third_party/fatfs/src/ff.c **** mem_set(tbl, 0, SS(fs)); -3937:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */ -3938:../../../Source/third_party/fatfs/src/ff.c **** i = SS(fs); /* Sector size */ -3939:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(tbl+BPB_BytsPerSec, i); -3940:../../../Source/third_party/fatfs/src/ff.c **** tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */ -3941:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */ -3942:../../../Source/third_party/fatfs/src/ff.c **** tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ -3943:../../../Source/third_party/fatfs/src/ff.c **** i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of rootdir entries */ -3944:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(tbl+BPB_RootEntCnt, i); -3945:../../../Source/third_party/fatfs/src/ff.c **** if (n_vol < 0x10000) { /* Number of total sectors */ -3946:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(tbl+BPB_TotSec16, n_vol); -3947:../../../Source/third_party/fatfs/src/ff.c **** } else { -3948:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+BPB_TotSec32, n_vol); -3949:../../../Source/third_party/fatfs/src/ff.c **** } -3950:../../../Source/third_party/fatfs/src/ff.c **** tbl[BPB_Media] = md; /* Media descriptor */ -3951:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */ -3952:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */ -3953:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */ -3954:../../../Source/third_party/fatfs/src/ff.c **** n = get_fattime(); /* Use current time as VSN */ -3955:../../../Source/third_party/fatfs/src/ff.c **** if (fmt == FS_FAT32) { -3956:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+BS_VolID32, n); /* VSN */ -3957:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */ -3958:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */ -3959:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(tbl+BPB_FSInfo, 1); /* FSInfo record offset (VBR+1) */ -3960:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */ -3961:../../../Source/third_party/fatfs/src/ff.c **** tbl[BS_DrvNum32] = 0x80; /* Drive number */ -3962:../../../Source/third_party/fatfs/src/ff.c **** tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ -3963:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ -3964:../../../Source/third_party/fatfs/src/ff.c **** } else { -3965:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+BS_VolID, n); /* VSN */ -3966:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */ -3967:../../../Source/third_party/fatfs/src/ff.c **** tbl[BS_DrvNum] = 0x80; /* Drive number */ -3968:../../../Source/third_party/fatfs/src/ff.c **** tbl[BS_BootSig] = 0x29; /* Extended boot signature */ -3969:../../../Source/third_party/fatfs/src/ff.c **** mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ -3970:../../../Source/third_party/fatfs/src/ff.c **** } -3971:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */ -3972:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(pdrv, tbl, b_vol, 1) != RES_OK) /* Write it to the VBR sector */ -3973:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; -3974:../../../Source/third_party/fatfs/src/ff.c **** if (fmt == FS_FAT32) /* Write backup VBR if needed (VBR+6) */ -3975:../../../Source/third_party/fatfs/src/ff.c **** disk_write(pdrv, tbl, b_vol + 6, 1); -3976:../../../Source/third_party/fatfs/src/ff.c **** -3977:../../../Source/third_party/fatfs/src/ff.c **** /* Initialize FAT area */ -3978:../../../Source/third_party/fatfs/src/ff.c **** wsect = b_fat; -3979:../../../Source/third_party/fatfs/src/ff.c **** for (i = 0; i < N_FATS; i++) { /* Initialize each FAT copy */ -3980:../../../Source/third_party/fatfs/src/ff.c **** mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */ -3981:../../../Source/third_party/fatfs/src/ff.c **** n = md; /* Media descriptor byte */ -3982:../../../Source/third_party/fatfs/src/ff.c **** if (fmt != FS_FAT32) { -3983:../../../Source/third_party/fatfs/src/ff.c **** n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00; -3984:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */ -3985:../../../Source/third_party/fatfs/src/ff.c **** } else { -3986:../../../Source/third_party/fatfs/src/ff.c **** n |= 0xFFFFFF00; -3987:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */ -3988:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+4, 0xFFFFFFFF); -3989:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root dir */ -3990:../../../Source/third_party/fatfs/src/ff.c **** } -3991:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK) -3992:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; -3993:../../../Source/third_party/fatfs/src/ff.c **** mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */ -3994:../../../Source/third_party/fatfs/src/ff.c **** for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single se -3995:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK) -3996:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; -3997:../../../Source/third_party/fatfs/src/ff.c **** } -3998:../../../Source/third_party/fatfs/src/ff.c **** } -3999:../../../Source/third_party/fatfs/src/ff.c **** -4000:../../../Source/third_party/fatfs/src/ff.c **** /* Initialize root directory */ -4001:../../../Source/third_party/fatfs/src/ff.c **** i = (fmt == FS_FAT32) ? au : n_dir; -4002:../../../Source/third_party/fatfs/src/ff.c **** do { -4003:../../../Source/third_party/fatfs/src/ff.c **** if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK) -4004:../../../Source/third_party/fatfs/src/ff.c **** return FR_DISK_ERR; -4005:../../../Source/third_party/fatfs/src/ff.c **** } while (--i); -4006:../../../Source/third_party/fatfs/src/ff.c **** -4007:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_ERASE /* Erase data area if needed */ -4008:../../../Source/third_party/fatfs/src/ff.c **** { -4009:../../../Source/third_party/fatfs/src/ff.c **** DWORD eb[2]; -4010:../../../Source/third_party/fatfs/src/ff.c **** -4011:../../../Source/third_party/fatfs/src/ff.c **** eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1; -4012:../../../Source/third_party/fatfs/src/ff.c **** disk_ioctl(pdrv, CTRL_ERASE_SECTOR, eb); -4013:../../../Source/third_party/fatfs/src/ff.c **** } -4014:../../../Source/third_party/fatfs/src/ff.c **** #endif -4015:../../../Source/third_party/fatfs/src/ff.c **** -4016:../../../Source/third_party/fatfs/src/ff.c **** /* Create FSInfo if needed */ -4017:../../../Source/third_party/fatfs/src/ff.c **** if (fmt == FS_FAT32) { -4018:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+FSI_LeadSig, 0x41615252); -4019:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+FSI_StrucSig, 0x61417272); -4020:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); /* Number of free clusters */ -4021:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(tbl+FSI_Nxt_Free, 2); /* Last allocated cluster# */ -4022:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(tbl+BS_55AA, 0xAA55); -4023:../../../Source/third_party/fatfs/src/ff.c **** disk_write(pdrv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */ -4024:../../../Source/third_party/fatfs/src/ff.c **** disk_write(pdrv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */ -4025:../../../Source/third_party/fatfs/src/ff.c **** } -4026:../../../Source/third_party/fatfs/src/ff.c **** -4027:../../../Source/third_party/fatfs/src/ff.c **** return (disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR; -4028:../../../Source/third_party/fatfs/src/ff.c **** } -4029:../../../Source/third_party/fatfs/src/ff.c **** -4030:../../../Source/third_party/fatfs/src/ff.c **** -4031:../../../Source/third_party/fatfs/src/ff.c **** #if _MULTI_PARTITION -4032:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -4033:../../../Source/third_party/fatfs/src/ff.c **** /* Divide Physical Drive */ -4034:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -4035:../../../Source/third_party/fatfs/src/ff.c **** -4036:../../../Source/third_party/fatfs/src/ff.c **** FRESULT f_fdisk ( -4037:../../../Source/third_party/fatfs/src/ff.c **** BYTE pdrv, /* Physical drive number */ -4038:../../../Source/third_party/fatfs/src/ff.c **** const DWORD szt[], /* Pointer to the size table for each partitions */ -4039:../../../Source/third_party/fatfs/src/ff.c **** void* work /* Pointer to the working buffer */ -4040:../../../Source/third_party/fatfs/src/ff.c **** ) -4041:../../../Source/third_party/fatfs/src/ff.c **** { -4042:../../../Source/third_party/fatfs/src/ff.c **** UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl; -4043:../../../Source/third_party/fatfs/src/ff.c **** BYTE s_hd, e_hd, *p, *buf = (BYTE*)work; -4044:../../../Source/third_party/fatfs/src/ff.c **** DSTATUS stat; -4045:../../../Source/third_party/fatfs/src/ff.c **** DWORD sz_disk, sz_part, s_part; -4046:../../../Source/third_party/fatfs/src/ff.c **** -4047:../../../Source/third_party/fatfs/src/ff.c **** -4048:../../../Source/third_party/fatfs/src/ff.c **** stat = disk_initialize(pdrv); -4049:../../../Source/third_party/fatfs/src/ff.c **** if (stat & STA_NOINIT) return FR_NOT_READY; -4050:../../../Source/third_party/fatfs/src/ff.c **** if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; -4051:../../../Source/third_party/fatfs/src/ff.c **** if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR; -4052:../../../Source/third_party/fatfs/src/ff.c **** -4053:../../../Source/third_party/fatfs/src/ff.c **** /* Determine CHS in the table regardless of the drive geometry */ -4054:../../../Source/third_party/fatfs/src/ff.c **** for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ; -4055:../../../Source/third_party/fatfs/src/ff.c **** if (n == 256) n--; -4056:../../../Source/third_party/fatfs/src/ff.c **** e_hd = n - 1; -4057:../../../Source/third_party/fatfs/src/ff.c **** sz_cyl = 63 * n; -4058:../../../Source/third_party/fatfs/src/ff.c **** tot_cyl = sz_disk / sz_cyl; -4059:../../../Source/third_party/fatfs/src/ff.c **** -4060:../../../Source/third_party/fatfs/src/ff.c **** /* Create partition table */ -4061:../../../Source/third_party/fatfs/src/ff.c **** mem_set(buf, 0, _MAX_SS); -4062:../../../Source/third_party/fatfs/src/ff.c **** p = buf + MBR_Table; b_cyl = 0; -4063:../../../Source/third_party/fatfs/src/ff.c **** for (i = 0; i < 4; i++, p += SZ_PTE) { -4064:../../../Source/third_party/fatfs/src/ff.c **** p_cyl = (szt[i] <= 100) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl; -4065:../../../Source/third_party/fatfs/src/ff.c **** if (!p_cyl) continue; -4066:../../../Source/third_party/fatfs/src/ff.c **** s_part = (DWORD)sz_cyl * b_cyl; -4067:../../../Source/third_party/fatfs/src/ff.c **** sz_part = (DWORD)sz_cyl * p_cyl; -4068:../../../Source/third_party/fatfs/src/ff.c **** if (i == 0) { /* Exclude first track of cylinder 0 */ -4069:../../../Source/third_party/fatfs/src/ff.c **** s_hd = 1; -4070:../../../Source/third_party/fatfs/src/ff.c **** s_part += 63; sz_part -= 63; -4071:../../../Source/third_party/fatfs/src/ff.c **** } else { -4072:../../../Source/third_party/fatfs/src/ff.c **** s_hd = 0; -4073:../../../Source/third_party/fatfs/src/ff.c **** } -4074:../../../Source/third_party/fatfs/src/ff.c **** e_cyl = b_cyl + p_cyl - 1; -4075:../../../Source/third_party/fatfs/src/ff.c **** if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER; -4076:../../../Source/third_party/fatfs/src/ff.c **** -4077:../../../Source/third_party/fatfs/src/ff.c **** /* Set partition table */ -4078:../../../Source/third_party/fatfs/src/ff.c **** p[1] = s_hd; /* Start head */ -4079:../../../Source/third_party/fatfs/src/ff.c **** p[2] = (BYTE)((b_cyl >> 2) + 1); /* Start sector */ -4080:../../../Source/third_party/fatfs/src/ff.c **** p[3] = (BYTE)b_cyl; /* Start cylinder */ -4081:../../../Source/third_party/fatfs/src/ff.c **** p[4] = 0x06; /* System type (temporary setting) */ -4082:../../../Source/third_party/fatfs/src/ff.c **** p[5] = e_hd; /* End head */ -4083:../../../Source/third_party/fatfs/src/ff.c **** p[6] = (BYTE)((e_cyl >> 2) + 63); /* End sector */ -4084:../../../Source/third_party/fatfs/src/ff.c **** p[7] = (BYTE)e_cyl; /* End cylinder */ -4085:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(p + 8, s_part); /* Start sector in LBA */ -4086:../../../Source/third_party/fatfs/src/ff.c **** ST_DWORD(p + 12, sz_part); /* Partition size */ -4087:../../../Source/third_party/fatfs/src/ff.c **** -4088:../../../Source/third_party/fatfs/src/ff.c **** /* Next partition */ -4089:../../../Source/third_party/fatfs/src/ff.c **** b_cyl += p_cyl; -4090:../../../Source/third_party/fatfs/src/ff.c **** } -4091:../../../Source/third_party/fatfs/src/ff.c **** ST_WORD(p, 0xAA55); -4092:../../../Source/third_party/fatfs/src/ff.c **** -4093:../../../Source/third_party/fatfs/src/ff.c **** /* Write it to the MBR */ -4094:../../../Source/third_party/fatfs/src/ff.c **** return (disk_write(pdrv, buf, 0, 1) || disk_ioctl(pdrv, CTRL_SYNC, 0)) ? FR_DISK_ERR : FR_OK; -4095:../../../Source/third_party/fatfs/src/ff.c **** } -4096:../../../Source/third_party/fatfs/src/ff.c **** -4097:../../../Source/third_party/fatfs/src/ff.c **** -4098:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _MULTI_PARTITION */ -4099:../../../Source/third_party/fatfs/src/ff.c **** #endif /* _USE_MKFS && !_FS_READONLY */ -4100:../../../Source/third_party/fatfs/src/ff.c **** -4101:../../../Source/third_party/fatfs/src/ff.c **** -4102:../../../Source/third_party/fatfs/src/ff.c **** -4103:../../../Source/third_party/fatfs/src/ff.c **** -4104:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_STRFUNC -4105:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -4106:../../../Source/third_party/fatfs/src/ff.c **** /* Get a string from the file */ -4107:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -4108:../../../Source/third_party/fatfs/src/ff.c **** -4109:../../../Source/third_party/fatfs/src/ff.c **** TCHAR* f_gets ( -4110:../../../Source/third_party/fatfs/src/ff.c **** TCHAR* buff, /* Pointer to the string buffer to read */ -4111:../../../Source/third_party/fatfs/src/ff.c **** int len, /* Size of string buffer (characters) */ -4112:../../../Source/third_party/fatfs/src/ff.c **** FIL* fp /* Pointer to the file object */ -4113:../../../Source/third_party/fatfs/src/ff.c **** ) -4114:../../../Source/third_party/fatfs/src/ff.c **** { - 7607 .loc 1 4114 0 - 7608 .cfi_startproc - 7609 @ args = 0, pretend = 0, frame = 8 - 7610 @ frame_needed = 0, uses_anonymous_args = 0 - 7611 .LVL1156: - 7612 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} - 7613 .cfi_def_cfa_offset 24 - 7614 .cfi_offset 4, -24 - 7615 .cfi_offset 5, -20 - 7616 .cfi_offset 6, -16 - 7617 .cfi_offset 7, -12 - 7618 .cfi_offset 8, -8 - 7619 .cfi_offset 14, -4 - 7620 0004 82B0 sub sp, sp, #8 - 7621 .cfi_def_cfa_offset 32 - 7622 0006 8046 mov r8, r0 - 7623 0008 1746 mov r7, r2 - 7624 .LVL1157: -4115:../../../Source/third_party/fatfs/src/ff.c **** int n = 0; -4116:../../../Source/third_party/fatfs/src/ff.c **** TCHAR c, *p = buff; - 7625 .loc 1 4116 0 - 7626 000a 0546 mov r5, r0 -4115:../../../Source/third_party/fatfs/src/ff.c **** int n = 0; - 7627 .loc 1 4115 0 - 7628 000c 0024 movs r4, #0 -4117:../../../Source/third_party/fatfs/src/ff.c **** BYTE s[2]; -4118:../../../Source/third_party/fatfs/src/ff.c **** UINT rc; -4119:../../../Source/third_party/fatfs/src/ff.c **** -4120:../../../Source/third_party/fatfs/src/ff.c **** -4121:../../../Source/third_party/fatfs/src/ff.c **** while (n < len - 1) { /* Read bytes until buffer gets filled */ - 7629 .loc 1 4121 0 - 7630 000e 4E1E subs r6, r1, #1 - 7631 0010 11E0 b .L731 - 7632 .LVL1158: - 7633 .L732: -4122:../../../Source/third_party/fatfs/src/ff.c **** f_read(fp, s, 1, &rc); - 7634 .loc 1 4122 0 - 7635 0012 3846 mov r0, r7 - 7636 0014 01A9 add r1, sp, #4 - 7637 0016 0122 movs r2, #1 - 7638 0018 6B46 mov r3, sp - 7639 001a FFF7FEFF bl f_read - 7640 .LVL1159: -4123:../../../Source/third_party/fatfs/src/ff.c **** if (rc != 1) break; /* Break on EOF or error */ - 7641 .loc 1 4123 0 - 7642 001e 009B ldr r3, [sp] - 7643 0020 012B cmp r3, #1 - 7644 0022 0AD1 bne .L730 -4124:../../../Source/third_party/fatfs/src/ff.c **** c = s[0]; - 7645 .loc 1 4124 0 - 7646 0024 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 - 7647 .LVL1160: -4125:../../../Source/third_party/fatfs/src/ff.c **** #if _LFN_UNICODE /* Read a character in UTF-8 encoding */ -4126:../../../Source/third_party/fatfs/src/ff.c **** if (c >= 0x80) { -4127:../../../Source/third_party/fatfs/src/ff.c **** if (c < 0xC0) continue; /* Skip stray trailer */ -4128:../../../Source/third_party/fatfs/src/ff.c **** if (c < 0xE0) { /* Two-byte sequence */ -4129:../../../Source/third_party/fatfs/src/ff.c **** f_read(fp, s, 1, &rc); -4130:../../../Source/third_party/fatfs/src/ff.c **** if (rc != 1) break; -4131:../../../Source/third_party/fatfs/src/ff.c **** c = ((c & 0x1F) << 6) | (s[0] & 0x3F); -4132:../../../Source/third_party/fatfs/src/ff.c **** if (c < 0x80) c = '?'; -4133:../../../Source/third_party/fatfs/src/ff.c **** } else { -4134:../../../Source/third_party/fatfs/src/ff.c **** if (c < 0xF0) { /* Three-byte sequence */ -4135:../../../Source/third_party/fatfs/src/ff.c **** f_read(fp, s, 2, &rc); -4136:../../../Source/third_party/fatfs/src/ff.c **** if (rc != 2) break; -4137:../../../Source/third_party/fatfs/src/ff.c **** c = (c << 12) | ((s[0] & 0x3F) << 6) | (s[1] & 0x3F); -4138:../../../Source/third_party/fatfs/src/ff.c **** if (c < 0x800) c = '?'; -4139:../../../Source/third_party/fatfs/src/ff.c **** } else { /* Reject four-byte sequence */ -4140:../../../Source/third_party/fatfs/src/ff.c **** c = '?'; -4141:../../../Source/third_party/fatfs/src/ff.c **** } -4142:../../../Source/third_party/fatfs/src/ff.c **** } -4143:../../../Source/third_party/fatfs/src/ff.c **** } -4144:../../../Source/third_party/fatfs/src/ff.c **** #endif -4145:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_STRFUNC >= 2 -4146:../../../Source/third_party/fatfs/src/ff.c **** if (c == '\r') continue; /* Strip '\r' */ - 7648 .loc 1 4146 0 - 7649 0028 0D2B cmp r3, #13 - 7650 002a 04D0 beq .L731 - 7651 .LVL1161: -4147:../../../Source/third_party/fatfs/src/ff.c **** #endif -4148:../../../Source/third_party/fatfs/src/ff.c **** *p++ = c; - 7652 .loc 1 4148 0 - 7653 002c 05F8013B strb r3, [r5], #1 - 7654 .LVL1162: -4149:../../../Source/third_party/fatfs/src/ff.c **** n++; - 7655 .loc 1 4149 0 - 7656 0030 0134 adds r4, r4, #1 - 7657 .LVL1163: -4150:../../../Source/third_party/fatfs/src/ff.c **** if (c == '\n') break; /* Break on EOL */ - 7658 .loc 1 4150 0 - 7659 0032 0A2B cmp r3, #10 - 7660 0034 01D0 beq .L730 - 7661 .LVL1164: - 7662 .L731: -4121:../../../Source/third_party/fatfs/src/ff.c **** f_read(fp, s, 1, &rc); - 7663 .loc 1 4121 0 - 7664 0036 A642 cmp r6, r4 - 7665 0038 EBDC bgt .L732 - 7666 .L730: - 7667 .LVL1165: -4151:../../../Source/third_party/fatfs/src/ff.c **** } -4152:../../../Source/third_party/fatfs/src/ff.c **** *p = 0; - 7668 .loc 1 4152 0 - 7669 003a 0023 movs r3, #0 - 7670 003c 2B70 strb r3, [r5] -4153:../../../Source/third_party/fatfs/src/ff.c **** return n ? buff : 0; /* When no data read (eof or error), return with error. */ - 7671 .loc 1 4153 0 - 7672 003e 9C42 cmp r4, r3 -4154:../../../Source/third_party/fatfs/src/ff.c **** } - 7673 .loc 1 4154 0 - 7674 0040 14BF ite ne - 7675 0042 4046 movne r0, r8 - 7676 0044 1846 moveq r0, r3 - 7677 0046 02B0 add sp, sp, #8 - 7678 .cfi_def_cfa_offset 24 - 7679 @ sp needed - 7680 0048 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 7681 .cfi_endproc - 7682 .LFE49: - 7684 .section .text.f_putc,"ax",%progbits - 7685 .align 2 - 7686 .global f_putc - 7687 .thumb - 7688 .thumb_func - 7690 f_putc: - 7691 .LFB50: -4155:../../../Source/third_party/fatfs/src/ff.c **** -4156:../../../Source/third_party/fatfs/src/ff.c **** -4157:../../../Source/third_party/fatfs/src/ff.c **** -4158:../../../Source/third_party/fatfs/src/ff.c **** #if !_FS_READONLY -4159:../../../Source/third_party/fatfs/src/ff.c **** #include -4160:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -4161:../../../Source/third_party/fatfs/src/ff.c **** /* Put a character to the file */ -4162:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -4163:../../../Source/third_party/fatfs/src/ff.c **** -4164:../../../Source/third_party/fatfs/src/ff.c **** int f_putc ( -4165:../../../Source/third_party/fatfs/src/ff.c **** TCHAR c, /* A character to be output */ -4166:../../../Source/third_party/fatfs/src/ff.c **** FIL* fp /* Pointer to the file object */ -4167:../../../Source/third_party/fatfs/src/ff.c **** ) -4168:../../../Source/third_party/fatfs/src/ff.c **** { - 7692 .loc 1 4168 0 - 7693 .cfi_startproc - 7694 @ args = 0, pretend = 0, frame = 8 - 7695 @ frame_needed = 0, uses_anonymous_args = 0 - 7696 .LVL1166: - 7697 0000 30B5 push {r4, r5, lr} - 7698 .cfi_def_cfa_offset 12 - 7699 .cfi_offset 4, -12 - 7700 .cfi_offset 5, -8 - 7701 .cfi_offset 14, -4 - 7702 0002 83B0 sub sp, sp, #12 - 7703 .cfi_def_cfa_offset 24 - 7704 0004 0446 mov r4, r0 - 7705 0006 0D46 mov r5, r1 -4169:../../../Source/third_party/fatfs/src/ff.c **** UINT bw, btw; -4170:../../../Source/third_party/fatfs/src/ff.c **** BYTE s[3]; -4171:../../../Source/third_party/fatfs/src/ff.c **** -4172:../../../Source/third_party/fatfs/src/ff.c **** -4173:../../../Source/third_party/fatfs/src/ff.c **** #if _USE_STRFUNC >= 2 -4174:../../../Source/third_party/fatfs/src/ff.c **** if (c == '\n') f_putc ('\r', fp); /* LF -> CRLF conversion */ - 7706 .loc 1 4174 0 - 7707 0008 0A28 cmp r0, #10 - 7708 000a 02D1 bne .L738 - 7709 .loc 1 4174 0 is_stmt 0 discriminator 1 - 7710 000c 0D20 movs r0, #13 - 7711 .LVL1167: - 7712 000e FFF7FEFF bl f_putc - 7713 .LVL1168: - 7714 .L738: -4175:../../../Source/third_party/fatfs/src/ff.c **** #endif -4176:../../../Source/third_party/fatfs/src/ff.c **** -4177:../../../Source/third_party/fatfs/src/ff.c **** #if _LFN_UNICODE /* Write the character in UTF-8 encoding */ -4178:../../../Source/third_party/fatfs/src/ff.c **** if (c < 0x80) { /* 7-bit */ -4179:../../../Source/third_party/fatfs/src/ff.c **** s[0] = (BYTE)c; -4180:../../../Source/third_party/fatfs/src/ff.c **** btw = 1; -4181:../../../Source/third_party/fatfs/src/ff.c **** } else { -4182:../../../Source/third_party/fatfs/src/ff.c **** if (c < 0x800) { /* 11-bit */ -4183:../../../Source/third_party/fatfs/src/ff.c **** s[0] = (BYTE)(0xC0 | (c >> 6)); -4184:../../../Source/third_party/fatfs/src/ff.c **** s[1] = (BYTE)(0x80 | (c & 0x3F)); -4185:../../../Source/third_party/fatfs/src/ff.c **** btw = 2; -4186:../../../Source/third_party/fatfs/src/ff.c **** } else { /* 16-bit */ -4187:../../../Source/third_party/fatfs/src/ff.c **** s[0] = (BYTE)(0xE0 | (c >> 12)); -4188:../../../Source/third_party/fatfs/src/ff.c **** s[1] = (BYTE)(0x80 | ((c >> 6) & 0x3F)); -4189:../../../Source/third_party/fatfs/src/ff.c **** s[2] = (BYTE)(0x80 | (c & 0x3F)); -4190:../../../Source/third_party/fatfs/src/ff.c **** btw = 3; -4191:../../../Source/third_party/fatfs/src/ff.c **** } -4192:../../../Source/third_party/fatfs/src/ff.c **** } -4193:../../../Source/third_party/fatfs/src/ff.c **** #else /* Write the character without conversion */ -4194:../../../Source/third_party/fatfs/src/ff.c **** s[0] = (BYTE)c; - 7715 .loc 1 4194 0 is_stmt 1 - 7716 0012 02A9 add r1, sp, #8 - 7717 0014 01F8084D strb r4, [r1, #-8]! - 7718 .LVL1169: -4195:../../../Source/third_party/fatfs/src/ff.c **** btw = 1; -4196:../../../Source/third_party/fatfs/src/ff.c **** #endif -4197:../../../Source/third_party/fatfs/src/ff.c **** f_write(fp, s, btw, &bw); /* Write the char to the file */ - 7719 .loc 1 4197 0 - 7720 0018 2846 mov r0, r5 - 7721 001a 0122 movs r2, #1 - 7722 001c 01AB add r3, sp, #4 - 7723 001e FFF7FEFF bl f_write - 7724 .LVL1170: -4198:../../../Source/third_party/fatfs/src/ff.c **** return (bw == btw) ? 1 : EOF; /* Return the result */ - 7725 .loc 1 4198 0 - 7726 0022 019B ldr r3, [sp, #4] - 7727 0024 012B cmp r3, #1 -4199:../../../Source/third_party/fatfs/src/ff.c **** } - 7728 .loc 1 4199 0 - 7729 0026 0CBF ite eq - 7730 0028 0120 moveq r0, #1 - 7731 002a 4FF0FF30 movne r0, #-1 - 7732 002e 03B0 add sp, sp, #12 - 7733 .cfi_def_cfa_offset 12 - 7734 @ sp needed - 7735 0030 30BD pop {r4, r5, pc} - 7736 .cfi_endproc - 7737 .LFE50: - 7739 0032 00BF .section .text.f_puts,"ax",%progbits - 7740 .align 2 - 7741 .global f_puts - 7742 .thumb - 7743 .thumb_func - 7745 f_puts: - 7746 .LFB51: -4200:../../../Source/third_party/fatfs/src/ff.c **** -4201:../../../Source/third_party/fatfs/src/ff.c **** -4202:../../../Source/third_party/fatfs/src/ff.c **** -4203:../../../Source/third_party/fatfs/src/ff.c **** -4204:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -4205:../../../Source/third_party/fatfs/src/ff.c **** /* Put a string to the file */ -4206:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -4207:../../../Source/third_party/fatfs/src/ff.c **** -4208:../../../Source/third_party/fatfs/src/ff.c **** int f_puts ( -4209:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR* str, /* Pointer to the string to be output */ -4210:../../../Source/third_party/fatfs/src/ff.c **** FIL* fp /* Pointer to the file object */ -4211:../../../Source/third_party/fatfs/src/ff.c **** ) -4212:../../../Source/third_party/fatfs/src/ff.c **** { - 7747 .loc 1 4212 0 - 7748 .cfi_startproc - 7749 @ args = 0, pretend = 0, frame = 0 - 7750 @ frame_needed = 0, uses_anonymous_args = 0 - 7751 .LVL1171: - 7752 0000 70B5 push {r4, r5, r6, lr} - 7753 .cfi_def_cfa_offset 16 - 7754 .cfi_offset 4, -16 - 7755 .cfi_offset 5, -12 - 7756 .cfi_offset 6, -8 - 7757 .cfi_offset 14, -4 - 7758 0002 0546 mov r5, r0 - 7759 .LVL1172: -4213:../../../Source/third_party/fatfs/src/ff.c **** int n; -4214:../../../Source/third_party/fatfs/src/ff.c **** -4215:../../../Source/third_party/fatfs/src/ff.c **** -4216:../../../Source/third_party/fatfs/src/ff.c **** for (n = 0; *str; str++, n++) { - 7760 .loc 1 4216 0 - 7761 0004 0078 ldrb r0, [r0] @ zero_extendqisi2 - 7762 .LVL1173: - 7763 0006 68B1 cbz r0, .L746 - 7764 0008 0E46 mov r6, r1 - 7765 000a 6C1C adds r4, r5, #1 - 7766 .LVL1174: - 7767 .L745: -4217:../../../Source/third_party/fatfs/src/ff.c **** if (f_putc(*str, fp) == EOF) return EOF; - 7768 .loc 1 4217 0 - 7769 000c 3146 mov r1, r6 - 7770 000e FFF7FEFF bl f_putc - 7771 .LVL1175: - 7772 0012 B0F1FF3F cmp r0, #-1 - 7773 0016 07D0 beq .L744 - 7774 .LVL1176: - 7775 0018 631B subs r3, r4, r5 - 7776 .LVL1177: -4216:../../../Source/third_party/fatfs/src/ff.c **** if (f_putc(*str, fp) == EOF) return EOF; - 7777 .loc 1 4216 0 discriminator 2 - 7778 001a 14F8010B ldrb r0, [r4], #1 @ zero_extendqisi2 - 7779 .LVL1178: - 7780 001e 0028 cmp r0, #0 - 7781 0020 F4D1 bne .L745 - 7782 0022 00E0 b .L743 - 7783 .LVL1179: - 7784 .L746: -4216:../../../Source/third_party/fatfs/src/ff.c **** if (f_putc(*str, fp) == EOF) return EOF; - 7785 .loc 1 4216 0 is_stmt 0 - 7786 0024 0023 movs r3, #0 - 7787 .LVL1180: - 7788 .L743: -4218:../../../Source/third_party/fatfs/src/ff.c **** } -4219:../../../Source/third_party/fatfs/src/ff.c **** return n; - 7789 .loc 1 4219 0 is_stmt 1 - 7790 0026 1846 mov r0, r3 - 7791 .L744: -4220:../../../Source/third_party/fatfs/src/ff.c **** } - 7792 .loc 1 4220 0 - 7793 0028 70BD pop {r4, r5, r6, pc} - 7794 .cfi_endproc - 7795 .LFE51: - 7797 002a 00BF .section .text.f_printf,"ax",%progbits - 7798 .align 2 - 7799 .global f_printf - 7800 .thumb - 7801 .thumb_func - 7803 f_printf: - 7804 .LFB52: -4221:../../../Source/third_party/fatfs/src/ff.c **** -4222:../../../Source/third_party/fatfs/src/ff.c **** -4223:../../../Source/third_party/fatfs/src/ff.c **** -4224:../../../Source/third_party/fatfs/src/ff.c **** -4225:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -4226:../../../Source/third_party/fatfs/src/ff.c **** /* Put a formatted string to the file */ -4227:../../../Source/third_party/fatfs/src/ff.c **** /*-----------------------------------------------------------------------*/ -4228:../../../Source/third_party/fatfs/src/ff.c **** -4229:../../../Source/third_party/fatfs/src/ff.c **** int f_printf ( -4230:../../../Source/third_party/fatfs/src/ff.c **** FIL* fp, /* Pointer to the file object */ -4231:../../../Source/third_party/fatfs/src/ff.c **** const TCHAR* str, /* Pointer to the format string */ -4232:../../../Source/third_party/fatfs/src/ff.c **** ... /* Optional arguments... */ -4233:../../../Source/third_party/fatfs/src/ff.c **** ) -4234:../../../Source/third_party/fatfs/src/ff.c **** { - 7805 .loc 1 4234 0 - 7806 .cfi_startproc - 7807 @ args = 4, pretend = 12, frame = 32 - 7808 @ frame_needed = 0, uses_anonymous_args = 1 - 7809 .LVL1181: - 7810 0000 0EB4 push {r1, r2, r3} - 7811 .cfi_def_cfa_offset 12 - 7812 .cfi_offset 1, -12 - 7813 .cfi_offset 2, -8 - 7814 .cfi_offset 3, -4 - 7815 0002 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} - 7816 .cfi_def_cfa_offset 48 - 7817 .cfi_offset 4, -48 - 7818 .cfi_offset 5, -44 - 7819 .cfi_offset 6, -40 - 7820 .cfi_offset 7, -36 - 7821 .cfi_offset 8, -32 - 7822 .cfi_offset 9, -28 - 7823 .cfi_offset 10, -24 - 7824 .cfi_offset 11, -20 - 7825 .cfi_offset 14, -16 - 7826 0006 88B0 sub sp, sp, #32 - 7827 .cfi_def_cfa_offset 80 - 7828 0008 0190 str r0, [sp, #4] - 7829 000a 11AB add r3, sp, #68 - 7830 000c 53F8047B ldr r7, [r3], #4 -4235:../../../Source/third_party/fatfs/src/ff.c **** va_list arp; -4236:../../../Source/third_party/fatfs/src/ff.c **** BYTE f, r; -4237:../../../Source/third_party/fatfs/src/ff.c **** UINT i, j, w; -4238:../../../Source/third_party/fatfs/src/ff.c **** ULONG v; -4239:../../../Source/third_party/fatfs/src/ff.c **** TCHAR c, d, s[16], *p; -4240:../../../Source/third_party/fatfs/src/ff.c **** int res, chc, cc; -4241:../../../Source/third_party/fatfs/src/ff.c **** -4242:../../../Source/third_party/fatfs/src/ff.c **** -4243:../../../Source/third_party/fatfs/src/ff.c **** va_start(arp, str); - 7831 .loc 1 4243 0 - 7832 0010 0793 str r3, [sp, #28] - 7833 .LVL1182: -4244:../../../Source/third_party/fatfs/src/ff.c **** -4245:../../../Source/third_party/fatfs/src/ff.c **** for (cc = res = 0; cc != EOF; res += cc) { -4246:../../../Source/third_party/fatfs/src/ff.c **** c = *str++; - 7834 .loc 1 4246 0 - 7835 0012 7C1C adds r4, r7, #1 - 7836 .LVL1183: - 7837 0014 3878 ldrb r0, [r7] @ zero_extendqisi2 - 7838 .LVL1184: -4247:../../../Source/third_party/fatfs/src/ff.c **** if (c == 0) break; /* End of string */ - 7839 .loc 1 4247 0 - 7840 0016 0028 cmp r0, #0 - 7841 0018 00F04581 beq .L803 - 7842 001c 0025 movs r5, #0 - 7843 001e AB46 mov fp, r5 - 7844 0020 04E0 b .L751 - 7845 .LVL1185: - 7846 .L794: -4246:../../../Source/third_party/fatfs/src/ff.c **** if (c == 0) break; /* End of string */ - 7847 .loc 1 4246 0 - 7848 0022 7C1C adds r4, r7, #1 - 7849 .LVL1186: - 7850 0024 3878 ldrb r0, [r7] @ zero_extendqisi2 - 7851 .LVL1187: - 7852 .loc 1 4247 0 - 7853 0026 0028 cmp r0, #0 - 7854 0028 00F06881 beq .L814 - 7855 .LVL1188: - 7856 .L751: -4248:../../../Source/third_party/fatfs/src/ff.c **** if (c != '%') { /* Non escape character */ - 7857 .loc 1 4248 0 - 7858 002c 2528 cmp r0, #37 - 7859 002e 07D0 beq .L752 -4249:../../../Source/third_party/fatfs/src/ff.c **** cc = f_putc(c, fp); - 7860 .loc 1 4249 0 - 7861 0030 0199 ldr r1, [sp, #4] - 7862 0032 FFF7FEFF bl f_putc - 7863 .LVL1189: -4250:../../../Source/third_party/fatfs/src/ff.c **** if (cc != EOF) cc = 1; - 7864 .loc 1 4250 0 - 7865 0036 B0F1FF3F cmp r0, #-1 - 7866 003a 40F02F81 bne .L753 - 7867 003e 24E1 b .L799 - 7868 .LVL1190: - 7869 .L752: -4251:../../../Source/third_party/fatfs/src/ff.c **** continue; -4252:../../../Source/third_party/fatfs/src/ff.c **** } -4253:../../../Source/third_party/fatfs/src/ff.c **** w = f = 0; -4254:../../../Source/third_party/fatfs/src/ff.c **** c = *str++; - 7870 .loc 1 4254 0 - 7871 0040 7B78 ldrb r3, [r7, #1] @ zero_extendqisi2 - 7872 .LVL1191: -4255:../../../Source/third_party/fatfs/src/ff.c **** if (c == '0') { /* Flag: '0' padding */ - 7873 .loc 1 4255 0 - 7874 0042 302B cmp r3, #48 - 7875 0044 04D1 bne .L755 - 7876 .LVL1192: -4256:../../../Source/third_party/fatfs/src/ff.c **** f = 1; c = *str++; - 7877 .loc 1 4256 0 - 7878 0046 BB78 ldrb r3, [r7, #2] @ zero_extendqisi2 - 7879 .LVL1193: - 7880 0048 0337 adds r7, r7, #3 - 7881 .LVL1194: - 7882 004a 4FF0010E mov lr, #1 - 7883 004e 09E0 b .L756 - 7884 .LVL1195: - 7885 .L755: -4257:../../../Source/third_party/fatfs/src/ff.c **** } else { -4258:../../../Source/third_party/fatfs/src/ff.c **** if (c == '-') { /* Flag: left justified */ - 7886 .loc 1 4258 0 - 7887 0050 2D2B cmp r3, #45 - 7888 0052 03D0 beq .L757 -4254:../../../Source/third_party/fatfs/src/ff.c **** if (c == '0') { /* Flag: '0' padding */ - 7889 .loc 1 4254 0 - 7890 0054 0237 adds r7, r7, #2 - 7891 .LVL1196: -4253:../../../Source/third_party/fatfs/src/ff.c **** c = *str++; - 7892 .loc 1 4253 0 - 7893 0056 4FF0000E mov lr, #0 - 7894 005a 03E0 b .L756 - 7895 .LVL1197: - 7896 .L757: -4259:../../../Source/third_party/fatfs/src/ff.c **** f = 2; c = *str++; - 7897 .loc 1 4259 0 - 7898 005c BB78 ldrb r3, [r7, #2] @ zero_extendqisi2 - 7899 .LVL1198: - 7900 005e 0337 adds r7, r7, #3 - 7901 .LVL1199: - 7902 0060 4FF0020E mov lr, #2 - 7903 .LVL1200: - 7904 .L756: -4260:../../../Source/third_party/fatfs/src/ff.c **** } -4261:../../../Source/third_party/fatfs/src/ff.c **** } -4262:../../../Source/third_party/fatfs/src/ff.c **** while (IsDigit(c)) { /* Precision */ - 7905 .loc 1 4262 0 - 7906 0064 A3F13002 sub r2, r3, #48 - 7907 0068 D2B2 uxtb r2, r2 - 7908 006a 092A cmp r2, #9 - 7909 006c 0DD8 bhi .L804 - 7910 006e 0026 movs r6, #0 - 7911 .LVL1201: - 7912 .L759: -4263:../../../Source/third_party/fatfs/src/ff.c **** w = w * 10 + c - '0'; - 7913 .loc 1 4263 0 - 7914 0070 06EB8606 add r6, r6, r6, lsl #2 - 7915 .LVL1202: - 7916 0074 03EB4606 add r6, r3, r6, lsl #1 - 7917 0078 303E subs r6, r6, #48 - 7918 .LVL1203: -4264:../../../Source/third_party/fatfs/src/ff.c **** c = *str++; - 7919 .loc 1 4264 0 - 7920 007a 17F8013B ldrb r3, [r7], #1 @ zero_extendqisi2 - 7921 .LVL1204: -4262:../../../Source/third_party/fatfs/src/ff.c **** w = w * 10 + c - '0'; - 7922 .loc 1 4262 0 - 7923 007e A3F13002 sub r2, r3, #48 - 7924 0082 D2B2 uxtb r2, r2 - 7925 0084 092A cmp r2, #9 - 7926 0086 F3D9 bls .L759 - 7927 0088 00E0 b .L758 - 7928 .LVL1205: - 7929 .L804: - 7930 008a 0026 movs r6, #0 - 7931 .LVL1206: - 7932 .L758: -4265:../../../Source/third_party/fatfs/src/ff.c **** } -4266:../../../Source/third_party/fatfs/src/ff.c **** if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ - 7933 .loc 1 4266 0 - 7934 008c 03F0DF02 and r2, r3, #223 - 7935 0090 4C2A cmp r2, #76 - 7936 0092 03D1 bne .L760 -4267:../../../Source/third_party/fatfs/src/ff.c **** f |= 4; c = *str++; - 7937 .loc 1 4267 0 - 7938 0094 4EF0040E orr lr, lr, #4 - 7939 .LVL1207: - 7940 0098 3B78 ldrb r3, [r7] @ zero_extendqisi2 - 7941 .LVL1208: - 7942 009a 0137 adds r7, r7, #1 - 7943 .LVL1209: - 7944 .L760: -4268:../../../Source/third_party/fatfs/src/ff.c **** } -4269:../../../Source/third_party/fatfs/src/ff.c **** if (!c) break; - 7945 .loc 1 4269 0 - 7946 009c 002B cmp r3, #0 - 7947 009e 00F0F180 beq .L761 - 7948 .LVL1210: -4270:../../../Source/third_party/fatfs/src/ff.c **** d = c; -4271:../../../Source/third_party/fatfs/src/ff.c **** if (IsLower(d)) d -= 0x20; - 7949 .loc 1 4271 0 - 7950 00a2 A3F16102 sub r2, r3, #97 - 7951 00a6 D2B2 uxtb r2, r2 - 7952 00a8 192A cmp r2, #25 - 7953 00aa 9ABF itte ls - 7954 00ac A3F12002 subls r2, r3, #32 - 7955 00b0 D2B2 uxtbls r2, r2 - 7956 .LVL1211: -4270:../../../Source/third_party/fatfs/src/ff.c **** d = c; - 7957 .loc 1 4270 0 - 7958 00b2 1A46 movhi r2, r3 - 7959 .LVL1212: -4272:../../../Source/third_party/fatfs/src/ff.c **** switch (d) { /* Type is... */ - 7960 .loc 1 4272 0 - 7961 00b4 A2F14201 sub r1, r2, #66 - 7962 00b8 1629 cmp r1, #22 - 7963 00ba 61D8 bhi .L763 - 7964 00bc DFE811F0 tbh [pc, r1, lsl #1] - 7965 .L765: - 7966 00c0 0E01 .2byte (.L764-.L765)/2 - 7967 00c2 5700 .2byte (.L766-.L765)/2 - 7968 00c4 6600 .2byte (.L767-.L765)/2 - 7969 00c6 6000 .2byte (.L763-.L765)/2 - 7970 00c8 6000 .2byte (.L763-.L765)/2 - 7971 00ca 6000 .2byte (.L763-.L765)/2 - 7972 00cc 6000 .2byte (.L763-.L765)/2 - 7973 00ce 6000 .2byte (.L763-.L765)/2 - 7974 00d0 6000 .2byte (.L763-.L765)/2 - 7975 00d2 6000 .2byte (.L763-.L765)/2 - 7976 00d4 6000 .2byte (.L763-.L765)/2 - 7977 00d6 6000 .2byte (.L763-.L765)/2 - 7978 00d8 6000 .2byte (.L763-.L765)/2 - 7979 00da 1901 .2byte (.L768-.L765)/2 - 7980 00dc 6000 .2byte (.L763-.L765)/2 - 7981 00de 6000 .2byte (.L763-.L765)/2 - 7982 00e0 6000 .2byte (.L763-.L765)/2 - 7983 00e2 1700 .2byte (.L769-.L765)/2 - 7984 00e4 6000 .2byte (.L763-.L765)/2 - 7985 00e6 6600 .2byte (.L767-.L765)/2 - 7986 00e8 6000 .2byte (.L763-.L765)/2 - 7987 00ea 6000 .2byte (.L763-.L765)/2 - 7988 00ec E800 .2byte (.L770-.L765)/2 - 7989 .p2align 1 - 7990 .L769: -4273:../../../Source/third_party/fatfs/src/ff.c **** case 'S' : /* String */ -4274:../../../Source/third_party/fatfs/src/ff.c **** p = va_arg(arp, TCHAR*); - 7991 .loc 1 4274 0 - 7992 00ee 079B ldr r3, [sp, #28] - 7993 .LVL1213: - 7994 00f0 1A1D adds r2, r3, #4 - 7995 .LVL1214: - 7996 00f2 0792 str r2, [sp, #28] - 7997 00f4 1D68 ldr r5, [r3] - 7998 .LVL1215: -4275:../../../Source/third_party/fatfs/src/ff.c **** for (j = 0; p[j]; j++) ; - 7999 .loc 1 4275 0 - 8000 00f6 2B78 ldrb r3, [r5] @ zero_extendqisi2 - 8001 00f8 3BB1 cbz r3, .L806 - 8002 00fa 2B46 mov r3, r5 - 8003 00fc 0024 movs r4, #0 - 8004 .LVL1216: - 8005 .L772: - 8006 .loc 1 4275 0 is_stmt 0 discriminator 3 - 8007 00fe 0134 adds r4, r4, #1 - 8008 .LVL1217: - 8009 0100 13F8012F ldrb r2, [r3, #1]! @ zero_extendqisi2 - 8010 0104 002A cmp r2, #0 - 8011 0106 FAD1 bne .L772 - 8012 0108 00E0 b .L771 - 8013 .LVL1218: - 8014 .L806: - 8015 .loc 1 4275 0 - 8016 010a 0024 movs r4, #0 - 8017 .LVL1219: - 8018 .L771: -4276:../../../Source/third_party/fatfs/src/ff.c **** chc = 0; -4277:../../../Source/third_party/fatfs/src/ff.c **** if (!(f & 2)) { - 8019 .loc 1 4277 0 is_stmt 1 - 8020 010c 1EF0020F tst lr, #2 - 8021 0110 10D1 bne .L807 - 8022 .LVL1220: -4278:../../../Source/third_party/fatfs/src/ff.c **** while (j++ < w) chc += (cc = f_putc(' ', fp)); - 8023 .loc 1 4278 0 discriminator 1 - 8024 0112 631C adds r3, r4, #1 - 8025 .LVL1221: - 8026 0114 B442 cmp r4, r6 - 8027 0116 10D2 bcs .L808 - 8028 .loc 1 4278 0 is_stmt 0 - 8029 0118 4FF00008 mov r8, #0 - 8030 011c 4FF02009 mov r9, #32 - 8031 .LVL1222: - 8032 .L774: - 8033 .loc 1 4278 0 discriminator 2 - 8034 0120 4846 mov r0, r9 - 8035 0122 0199 ldr r1, [sp, #4] - 8036 0124 FFF7FEFF bl f_putc - 8037 .LVL1223: - 8038 0128 8044 add r8, r8, r0 - 8039 .LVL1224: - 8040 012a 0134 adds r4, r4, #1 - 8041 .LVL1225: - 8042 012c B442 cmp r4, r6 - 8043 012e F7D3 bcc .L774 - 8044 0130 741C adds r4, r6, #1 - 8045 .LVL1226: - 8046 0132 05E0 b .L773 - 8047 .LVL1227: - 8048 .L807: -4276:../../../Source/third_party/fatfs/src/ff.c **** chc = 0; - 8049 .loc 1 4276 0 is_stmt 1 - 8050 0134 4FF00008 mov r8, #0 - 8051 0138 02E0 b .L773 - 8052 .LVL1228: - 8053 .L808: - 8054 .loc 1 4278 0 - 8055 013a 1C46 mov r4, r3 - 8056 013c 4FF00008 mov r8, #0 - 8057 .LVL1229: - 8058 .L773: -4279:../../../Source/third_party/fatfs/src/ff.c **** } -4280:../../../Source/third_party/fatfs/src/ff.c **** chc += (cc = f_puts(p, fp)); - 8059 .loc 1 4280 0 - 8060 0140 2846 mov r0, r5 - 8061 0142 0199 ldr r1, [sp, #4] - 8062 0144 FFF7FEFF bl f_puts - 8063 .LVL1230: - 8064 0148 08EB0005 add r5, r8, r0 - 8065 .LVL1231: -4281:../../../Source/third_party/fatfs/src/ff.c **** while (j++ < w) chc += (cc = f_putc(' ', fp)); - 8066 .loc 1 4281 0 - 8067 014c B442 cmp r4, r6 - 8068 014e 09D2 bcs .L775 - 8069 0150 4FF02008 mov r8, #32 - 8070 .LVL1232: - 8071 .L776: - 8072 .loc 1 4281 0 is_stmt 0 discriminator 2 - 8073 0154 4046 mov r0, r8 - 8074 .LVL1233: - 8075 0156 0199 ldr r1, [sp, #4] - 8076 0158 FFF7FEFF bl f_putc - 8077 .LVL1234: - 8078 015c 0544 add r5, r5, r0 - 8079 .LVL1235: - 8080 015e 0134 adds r4, r4, #1 - 8081 .LVL1236: - 8082 0160 B442 cmp r4, r6 - 8083 0162 F7D3 bcc .L776 - 8084 .LVL1237: - 8085 .L775: -4282:../../../Source/third_party/fatfs/src/ff.c **** if (cc != EOF) cc = chc; - 8086 .loc 1 4282 0 is_stmt 1 - 8087 0164 B0F1FF3F cmp r0, #-1 - 8088 0168 40F08680 bne .L777 - 8089 016c 8DE0 b .L799 - 8090 .LVL1238: - 8091 .L766: -4283:../../../Source/third_party/fatfs/src/ff.c **** continue; -4284:../../../Source/third_party/fatfs/src/ff.c **** case 'C' : /* Character */ -4285:../../../Source/third_party/fatfs/src/ff.c **** cc = f_putc((TCHAR)va_arg(arp, int), fp); continue; - 8092 .loc 1 4285 0 - 8093 016e 079B ldr r3, [sp, #28] - 8094 .LVL1239: - 8095 0170 1A1D adds r2, r3, #4 - 8096 .LVL1240: - 8097 0172 0792 str r2, [sp, #28] - 8098 0174 1878 ldrb r0, [r3] @ zero_extendqisi2 - 8099 0176 0199 ldr r1, [sp, #4] - 8100 .LVL1241: - 8101 0178 FFF7FEFF bl f_putc - 8102 .LVL1242: - 8103 017c 0546 mov r5, r0 - 8104 .LVL1243: - 8105 017e 7BE0 b .L777 - 8106 .LVL1244: - 8107 .L763: -4286:../../../Source/third_party/fatfs/src/ff.c **** case 'B' : /* Binary */ -4287:../../../Source/third_party/fatfs/src/ff.c **** r = 2; break; -4288:../../../Source/third_party/fatfs/src/ff.c **** case 'O' : /* Octal */ -4289:../../../Source/third_party/fatfs/src/ff.c **** r = 8; break; -4290:../../../Source/third_party/fatfs/src/ff.c **** case 'D' : /* Signed decimal */ -4291:../../../Source/third_party/fatfs/src/ff.c **** case 'U' : /* Unsigned decimal */ -4292:../../../Source/third_party/fatfs/src/ff.c **** r = 10; break; -4293:../../../Source/third_party/fatfs/src/ff.c **** case 'X' : /* Hexdecimal */ -4294:../../../Source/third_party/fatfs/src/ff.c **** r = 16; break; -4295:../../../Source/third_party/fatfs/src/ff.c **** default: /* Unknown type (pass-through) */ -4296:../../../Source/third_party/fatfs/src/ff.c **** cc = f_putc(c, fp); continue; - 8108 .loc 1 4296 0 - 8109 0180 1846 mov r0, r3 - 8110 0182 0199 ldr r1, [sp, #4] - 8111 0184 FFF7FEFF bl f_putc - 8112 .LVL1245: - 8113 0188 0546 mov r5, r0 - 8114 .LVL1246: - 8115 018a 75E0 b .L777 - 8116 .LVL1247: - 8117 .L767: -4297:../../../Source/third_party/fatfs/src/ff.c **** } -4298:../../../Source/third_party/fatfs/src/ff.c **** -4299:../../../Source/third_party/fatfs/src/ff.c **** /* Get an argument and put it in numeral */ -4300:../../../Source/third_party/fatfs/src/ff.c **** v = (f & 4) ? (ULONG)va_arg(arp, long) : ((d == 'D') ? (ULONG)(long)va_arg(arp, int) : (ULONG)va_ - 8118 .loc 1 4300 0 - 8119 018c 1EF0040F tst lr, #4 - 8120 0190 09D0 beq .L809 -4292:../../../Source/third_party/fatfs/src/ff.c **** case 'X' : /* Hexdecimal */ - 8121 .loc 1 4292 0 - 8122 0192 0A25 movs r5, #10 - 8123 0194 00E0 b .L798 - 8124 .LVL1248: - 8125 .L813: -4294:../../../Source/third_party/fatfs/src/ff.c **** default: /* Unknown type (pass-through) */ - 8126 .loc 1 4294 0 - 8127 0196 1025 movs r5, #16 - 8128 .LVL1249: - 8129 .L798: - 8130 .loc 1 4300 0 discriminator 1 - 8131 0198 0799 ldr r1, [sp, #28] - 8132 019a 081D adds r0, r1, #4 - 8133 019c 0790 str r0, [sp, #28] - 8134 019e 0968 ldr r1, [r1] - 8135 .LVL1250: -4301:../../../Source/third_party/fatfs/src/ff.c **** if (d == 'D' && (v & 0x80000000)) { - 8136 .loc 1 4301 0 discriminator 1 - 8137 01a0 442A cmp r2, #68 - 8138 01a2 12D1 bne .L780 - 8139 01a4 0CE0 b .L779 - 8140 .LVL1251: - 8141 .L809: -4292:../../../Source/third_party/fatfs/src/ff.c **** case 'X' : /* Hexdecimal */ - 8142 .loc 1 4292 0 - 8143 01a6 0A25 movs r5, #10 - 8144 .LVL1252: - 8145 .L778: -4300:../../../Source/third_party/fatfs/src/ff.c **** if (d == 'D' && (v & 0x80000000)) { - 8146 .loc 1 4300 0 discriminator 2 - 8147 01a8 442A cmp r2, #68 - 8148 01aa 04D1 bne .L781 -4300:../../../Source/third_party/fatfs/src/ff.c **** if (d == 'D' && (v & 0x80000000)) { - 8149 .loc 1 4300 0 is_stmt 0 discriminator 4 - 8150 01ac 079A ldr r2, [sp, #28] - 8151 .LVL1253: - 8152 01ae 111D adds r1, r2, #4 - 8153 .LVL1254: - 8154 01b0 0791 str r1, [sp, #28] - 8155 01b2 1168 ldr r1, [r2] - 8156 .LVL1255: - 8157 01b4 04E0 b .L779 - 8158 .LVL1256: - 8159 .L781: -4300:../../../Source/third_party/fatfs/src/ff.c **** if (d == 'D' && (v & 0x80000000)) { - 8160 .loc 1 4300 0 discriminator 5 - 8161 01b6 079A ldr r2, [sp, #28] - 8162 .LVL1257: - 8163 01b8 111D adds r1, r2, #4 - 8164 .LVL1258: - 8165 01ba 0791 str r1, [sp, #28] - 8166 01bc 1168 ldr r1, [r2] - 8167 .LVL1259: - 8168 01be 04E0 b .L780 - 8169 .L779: - 8170 .loc 1 4301 0 is_stmt 1 discriminator 1 - 8171 01c0 0029 cmp r1, #0 -4302:../../../Source/third_party/fatfs/src/ff.c **** v = 0 - v; - 8172 .loc 1 4302 0 discriminator 1 - 8173 01c2 BCBF itt lt - 8174 01c4 4942 rsblt r1, r1, #0 - 8175 .LVL1260: -4303:../../../Source/third_party/fatfs/src/ff.c **** f |= 8; - 8176 .loc 1 4303 0 discriminator 1 - 8177 01c6 4EF0080E orrlt lr, lr, #8 - 8178 .LVL1261: - 8179 .L780: - 8180 01ca 0DF10B0C add ip, sp, #11 -4304:../../../Source/third_party/fatfs/src/ff.c **** } -4305:../../../Source/third_party/fatfs/src/ff.c **** i = 0; - 8181 .loc 1 4305 0 - 8182 01ce 0024 movs r4, #0 - 8183 .LVL1262: - 8184 .L785: -4306:../../../Source/third_party/fatfs/src/ff.c **** do { -4307:../../../Source/third_party/fatfs/src/ff.c **** d = (TCHAR)(v % r); v /= r; - 8185 .loc 1 4307 0 - 8186 01d0 B1FBF5F0 udiv r0, r1, r5 - 8187 01d4 05FB1012 mls r2, r5, r0, r1 - 8188 01d8 D2B2 uxtb r2, r2 - 8189 .LVL1263: - 8190 01da 0146 mov r1, r0 - 8191 .LVL1264: -4308:../../../Source/third_party/fatfs/src/ff.c **** if (d > 9) d += (c == 'x') ? 0x27 : 0x07; - 8192 .loc 1 4308 0 - 8193 01dc 092A cmp r2, #9 - 8194 01de 07D9 bls .L782 - 8195 .loc 1 4308 0 is_stmt 0 discriminator 1 - 8196 01e0 782B cmp r3, #120 - 8197 01e2 0CBF ite eq - 8198 01e4 4FF02708 moveq r8, #39 - 8199 01e8 4FF00708 movne r8, #7 - 8200 01ec 4244 add r2, r2, r8 - 8201 .LVL1265: - 8202 01ee D2B2 uxtb r2, r2 - 8203 .LVL1266: - 8204 .L782: -4309:../../../Source/third_party/fatfs/src/ff.c **** s[i++] = d + '0'; - 8205 .loc 1 4309 0 is_stmt 1 - 8206 01f0 0134 adds r4, r4, #1 - 8207 .LVL1267: - 8208 01f2 3032 adds r2, r2, #48 - 8209 .LVL1268: - 8210 01f4 0CF8012F strb r2, [ip, #1]! -4310:../../../Source/third_party/fatfs/src/ff.c **** } while (v && i < sizeof s / sizeof s[0]); - 8211 .loc 1 4310 0 - 8212 01f8 08B1 cbz r0, .L784 - 8213 .loc 1 4310 0 is_stmt 0 discriminator 1 - 8214 01fa 102C cmp r4, #16 - 8215 01fc E8D1 bne .L785 - 8216 .L784: -4311:../../../Source/third_party/fatfs/src/ff.c **** if (f & 8) s[i++] = '-'; - 8217 .loc 1 4311 0 is_stmt 1 - 8218 01fe 1EF0080F tst lr, #8 - 8219 0202 05D0 beq .L786 - 8220 .LVL1269: - 8221 .loc 1 4311 0 is_stmt 0 discriminator 1 - 8222 0204 08AB add r3, sp, #32 - 8223 .LVL1270: - 8224 0206 2344 add r3, r3, r4 - 8225 0208 2D22 movs r2, #45 - 8226 020a 03F8142C strb r2, [r3, #-20] - 8227 020e 0134 adds r4, r4, #1 - 8228 .LVL1271: - 8229 .L786: -4312:../../../Source/third_party/fatfs/src/ff.c **** j = i; d = (f & 1) ? '0' : ' '; - 8230 .loc 1 4312 0 is_stmt 1 - 8231 0210 0EF00103 and r3, lr, #1 - 8232 0214 002B cmp r3, #0 - 8233 0216 14BF ite ne - 8234 0218 4FF03009 movne r9, #48 - 8235 021c 4FF02009 moveq r9, #32 - 8236 .LVL1272: -4313:../../../Source/third_party/fatfs/src/ff.c **** chc = 0; -4314:../../../Source/third_party/fatfs/src/ff.c **** while (!(f & 2) && j++ < w) chc += (cc = f_putc(d, fp)); - 8237 .loc 1 4314 0 - 8238 0220 1EF0020F tst lr, #2 - 8239 0224 0BD1 bne .L812 - 8240 0226 04F10108 add r8, r4, #1 - 8241 .LVL1273: - 8242 022a B442 cmp r4, r6 -4313:../../../Source/third_party/fatfs/src/ff.c **** chc = 0; - 8243 .loc 1 4313 0 - 8244 022c 28BF it cs - 8245 022e 0025 movcs r5, #0 - 8246 .loc 1 4314 0 - 8247 0230 07D2 bcs .L788 - 8248 0232 43E0 b .L789 - 8249 .LVL1274: - 8250 .L800: - 8251 .loc 1 4314 0 is_stmt 0 discriminator 2 - 8252 0234 D045 cmp r8, r10 - 8253 0236 39D1 bne .L790 - 8254 0238 06F10108 add r8, r6, #1 - 8255 .LVL1275: - 8256 023c 01E0 b .L788 - 8257 .LVL1276: - 8258 .L812: -4312:../../../Source/third_party/fatfs/src/ff.c **** j = i; d = (f & 1) ? '0' : ' '; - 8259 .loc 1 4312 0 is_stmt 1 - 8260 023e A046 mov r8, r4 -4313:../../../Source/third_party/fatfs/src/ff.c **** chc = 0; - 8261 .loc 1 4313 0 - 8262 0240 0025 movs r5, #0 - 8263 .LVL1277: - 8264 .L788: - 8265 0242 03AB add r3, sp, #12 - 8266 0244 03EB0409 add r9, r3, r4 - 8267 .LVL1278: - 8268 .L791: -4315:../../../Source/third_party/fatfs/src/ff.c **** do chc += (cc = f_putc(s[--i], fp)); while(i); - 8269 .loc 1 4315 0 discriminator 1 - 8270 0248 013C subs r4, r4, #1 - 8271 .LVL1279: - 8272 024a 19F8010D ldrb r0, [r9, #-1]! @ zero_extendqisi2 - 8273 024e 0199 ldr r1, [sp, #4] - 8274 0250 FFF7FEFF bl f_putc - 8275 .LVL1280: - 8276 0254 0544 add r5, r5, r0 - 8277 .LVL1281: - 8278 0256 002C cmp r4, #0 - 8279 0258 F6D1 bne .L791 - 8280 .LVL1282: -4316:../../../Source/third_party/fatfs/src/ff.c **** while (j++ < w) chc += (cc = f_putc(' ', fp)); - 8281 .loc 1 4316 0 discriminator 1 - 8282 025a B045 cmp r8, r6 - 8283 025c 09D2 bcs .L792 - 8284 .loc 1 4316 0 is_stmt 0 - 8285 025e 2024 movs r4, #32 - 8286 .LVL1283: - 8287 .L793: - 8288 .loc 1 4316 0 discriminator 2 - 8289 0260 2046 mov r0, r4 - 8290 .LVL1284: - 8291 0262 0199 ldr r1, [sp, #4] - 8292 0264 FFF7FEFF bl f_putc - 8293 .LVL1285: - 8294 0268 0544 add r5, r5, r0 - 8295 .LVL1286: - 8296 026a 08F10108 add r8, r8, #1 - 8297 .LVL1287: - 8298 026e B045 cmp r8, r6 - 8299 0270 F6D3 bcc .L793 - 8300 .LVL1288: - 8301 .L792: -4317:../../../Source/third_party/fatfs/src/ff.c **** if (cc != EOF) cc = chc; - 8302 .loc 1 4317 0 is_stmt 1 - 8303 0272 B0F1FF3F cmp r0, #-1 - 8304 0276 08D0 beq .L799 - 8305 .LVL1289: - 8306 .L777: -4245:../../../Source/third_party/fatfs/src/ff.c **** c = *str++; - 8307 .loc 1 4245 0 discriminator 2 - 8308 0278 AB44 add fp, fp, r5 - 8309 .LVL1290: - 8310 027a B5F1FF3F cmp r5, #-1 - 8311 027e 7FF4D0AE bne .L794 - 8312 0282 02E0 b .L799 - 8313 .LVL1291: - 8314 .L761: -4318:../../../Source/third_party/fatfs/src/ff.c **** } -4319:../../../Source/third_party/fatfs/src/ff.c **** -4320:../../../Source/third_party/fatfs/src/ff.c **** va_end(arp); -4321:../../../Source/third_party/fatfs/src/ff.c **** return (cc == EOF) ? cc : res; - 8315 .loc 1 4321 0 - 8316 0284 B5F1FF3F cmp r5, #-1 - 8317 0288 38D1 bne .L814 - 8318 .LVL1292: - 8319 .L799: - 8320 .loc 1 4321 0 is_stmt 0 discriminator 1 - 8321 028a 4FF0FF3B mov fp, #-1 - 8322 .LVL1293: - 8323 028e 35E0 b .L814 - 8324 .LVL1294: - 8325 .L770: -4300:../../../Source/third_party/fatfs/src/ff.c **** if (d == 'D' && (v & 0x80000000)) { - 8326 .loc 1 4300 0 is_stmt 1 - 8327 0290 1EF0040F tst lr, #4 - 8328 0294 7FF47FAF bne .L813 -4294:../../../Source/third_party/fatfs/src/ff.c **** default: /* Unknown type (pass-through) */ - 8329 .loc 1 4294 0 - 8330 0298 1025 movs r5, #16 - 8331 029a 8CE7 b .L781 - 8332 .LVL1295: - 8333 .L753: -4245:../../../Source/third_party/fatfs/src/ff.c **** c = *str++; - 8334 .loc 1 4245 0 - 8335 029c 0BF1010B add fp, fp, #1 - 8336 .LVL1296: - 8337 02a0 2746 mov r7, r4 -4250:../../../Source/third_party/fatfs/src/ff.c **** continue; - 8338 .loc 1 4250 0 - 8339 02a2 0125 movs r5, #1 - 8340 02a4 BDE6 b .L794 - 8341 .LVL1297: - 8342 .L803: -4245:../../../Source/third_party/fatfs/src/ff.c **** c = *str++; - 8343 .loc 1 4245 0 - 8344 02a6 4FF0000B mov fp, #0 - 8345 02aa 27E0 b .L814 - 8346 .LVL1298: - 8347 .L790: -4314:../../../Source/third_party/fatfs/src/ff.c **** do chc += (cc = f_putc(s[--i], fp)); while(i); - 8348 .loc 1 4314 0 - 8349 02ac 4846 mov r0, r9 - 8350 02ae 0199 ldr r1, [sp, #4] - 8351 02b0 FFF7FEFF bl f_putc - 8352 .LVL1299: - 8353 02b4 0544 add r5, r5, r0 - 8354 .LVL1300: - 8355 02b6 08F10108 add r8, r8, #1 - 8356 .LVL1301: - 8357 02ba BBE7 b .L800 - 8358 .LVL1302: - 8359 .L789: - 8360 02bc 4846 mov r0, r9 - 8361 .LVL1303: - 8362 02be 0199 ldr r1, [sp, #4] - 8363 .LVL1304: - 8364 02c0 FFF7FEFF bl f_putc - 8365 .LVL1305: - 8366 02c4 0546 mov r5, r0 - 8367 .LVL1306: - 8368 02c6 04F10208 add r8, r4, #2 - 8369 .LVL1307: - 8370 02ca 06F1010A add r10, r6, #1 - 8371 02ce B1E7 b .L800 - 8372 .LVL1308: - 8373 .L801: -4300:../../../Source/third_party/fatfs/src/ff.c **** if (d == 'D' && (v & 0x80000000)) { - 8374 .loc 1 4300 0 - 8375 02d0 079A ldr r2, [sp, #28] - 8376 .LVL1309: - 8377 02d2 111D adds r1, r2, #4 - 8378 .LVL1310: - 8379 02d4 0791 str r1, [sp, #28] - 8380 02d6 1168 ldr r1, [r2] - 8381 .LVL1311: -4287:../../../Source/third_party/fatfs/src/ff.c **** case 'O' : /* Octal */ - 8382 .loc 1 4287 0 - 8383 02d8 0225 movs r5, #2 - 8384 02da 76E7 b .L780 - 8385 .LVL1312: - 8386 .L764: -4300:../../../Source/third_party/fatfs/src/ff.c **** if (d == 'D' && (v & 0x80000000)) { - 8387 .loc 1 4300 0 - 8388 02dc 1EF0040F tst lr, #4 - 8389 02e0 F6D1 bne .L801 -4287:../../../Source/third_party/fatfs/src/ff.c **** case 'O' : /* Octal */ - 8390 .loc 1 4287 0 - 8391 02e2 0225 movs r5, #2 - 8392 02e4 60E7 b .L778 - 8393 .LVL1313: - 8394 .L802: -4300:../../../Source/third_party/fatfs/src/ff.c **** if (d == 'D' && (v & 0x80000000)) { - 8395 .loc 1 4300 0 - 8396 02e6 079A ldr r2, [sp, #28] - 8397 .LVL1314: - 8398 02e8 111D adds r1, r2, #4 - 8399 .LVL1315: - 8400 02ea 0791 str r1, [sp, #28] - 8401 02ec 1168 ldr r1, [r2] - 8402 .LVL1316: -4289:../../../Source/third_party/fatfs/src/ff.c **** case 'D' : /* Signed decimal */ - 8403 .loc 1 4289 0 - 8404 02ee 0825 movs r5, #8 - 8405 02f0 6BE7 b .L780 - 8406 .LVL1317: - 8407 .L768: -4300:../../../Source/third_party/fatfs/src/ff.c **** if (d == 'D' && (v & 0x80000000)) { - 8408 .loc 1 4300 0 - 8409 02f2 1EF0040F tst lr, #4 - 8410 02f6 F6D1 bne .L802 -4289:../../../Source/third_party/fatfs/src/ff.c **** case 'D' : /* Signed decimal */ - 8411 .loc 1 4289 0 - 8412 02f8 0825 movs r5, #8 - 8413 02fa 5CE7 b .L781 - 8414 .LVL1318: - 8415 .L814: -4322:../../../Source/third_party/fatfs/src/ff.c **** } - 8416 .loc 1 4322 0 - 8417 02fc 5846 mov r0, fp - 8418 02fe 08B0 add sp, sp, #32 - 8419 .cfi_def_cfa_offset 48 - 8420 @ sp needed - 8421 0300 BDE8F04F pop {r4, r5, r6, r7, r8, r9, r10, fp, lr} - 8422 .cfi_restore 14 - 8423 .cfi_restore 11 - 8424 .cfi_restore 10 - 8425 .cfi_restore 9 - 8426 .cfi_restore 8 - 8427 .cfi_restore 7 - 8428 .cfi_restore 6 - 8429 .cfi_restore 5 - 8430 .cfi_restore 4 - 8431 .cfi_def_cfa_offset 12 - 8432 0304 03B0 add sp, sp, #12 - 8433 .cfi_restore 3 - 8434 .cfi_restore 2 - 8435 .cfi_restore 1 - 8436 .cfi_def_cfa_offset 0 - 8437 0306 7047 bx lr - 8438 .cfi_endproc - 8439 .LFE52: - 8441 .section .bss.LfnBuf,"aw",%nobits - 8442 .align 2 - 8443 .set .LANCHOR4,. + 0 - 8446 LfnBuf: - 8447 0000 00000000 .space 512 - 8447 00000000 - 8447 00000000 - 8447 00000000 - 8447 00000000 - 8448 .section .bss.Fsid,"aw",%nobits - 8449 .align 1 - 8450 .set .LANCHOR1,. + 0 - 8453 Fsid: - 8454 0000 0000 .space 2 - 8455 .section .rodata.str1.4,"aMS",%progbits,1 - 8456 .align 2 - 8457 .LC0: - 8458 0000 222A3A3C .ascii "\"*:<>?|\177\000" - 8458 3E3F7C7F - 8458 00 - 8459 0009 000000 .space 3 - 8460 .LC1: - 8461 000c 2B2C3B3D .ascii "+,;=[]\000" - 8461 5B5D00 - 8462 0013 00 .section .rodata.ExCvt,"a",%progbits - 8463 .align 2 - 8464 .set .LANCHOR3,. + 0 - 8467 ExCvt: - 8468 0000 80 .byte -128 - 8469 0001 9A .byte -102 - 8470 0002 90 .byte -112 - 8471 0003 41 .byte 65 - 8472 0004 8E .byte -114 - 8473 0005 41 .byte 65 - 8474 0006 8F .byte -113 - 8475 0007 80 .byte -128 - 8476 0008 45 .byte 69 - 8477 0009 45 .byte 69 - 8478 000a 45 .byte 69 - 8479 000b 49 .byte 73 - 8480 000c 49 .byte 73 - 8481 000d 49 .byte 73 - 8482 000e 8E .byte -114 - 8483 000f 8F .byte -113 - 8484 0010 90 .byte -112 - 8485 0011 92 .byte -110 - 8486 0012 92 .byte -110 - 8487 0013 4F .byte 79 - 8488 0014 99 .byte -103 - 8489 0015 4F .byte 79 - 8490 0016 55 .byte 85 - 8491 0017 55 .byte 85 - 8492 0018 59 .byte 89 - 8493 0019 99 .byte -103 - 8494 001a 9A .byte -102 - 8495 001b 9B .byte -101 - 8496 001c 9C .byte -100 - 8497 001d 9D .byte -99 - 8498 001e 9E .byte -98 - 8499 001f 9F .byte -97 - 8500 0020 41 .byte 65 - 8501 0021 49 .byte 73 - 8502 0022 4F .byte 79 - 8503 0023 55 .byte 85 - 8504 0024 A5 .byte -91 - 8505 0025 A5 .byte -91 - 8506 0026 A6 .byte -90 - 8507 0027 A7 .byte -89 - 8508 0028 A8 .byte -88 - 8509 0029 A9 .byte -87 - 8510 002a AA .byte -86 - 8511 002b AB .byte -85 - 8512 002c AC .byte -84 - 8513 002d 21 .byte 33 - 8514 002e AE .byte -82 - 8515 002f AF .byte -81 - 8516 0030 B0 .byte -80 - 8517 0031 B1 .byte -79 - 8518 0032 B2 .byte -78 - 8519 0033 B3 .byte -77 - 8520 0034 B4 .byte -76 - 8521 0035 B5 .byte -75 - 8522 0036 B6 .byte -74 - 8523 0037 B7 .byte -73 - 8524 0038 B8 .byte -72 - 8525 0039 B9 .byte -71 - 8526 003a BA .byte -70 - 8527 003b BB .byte -69 - 8528 003c BC .byte -68 - 8529 003d BD .byte -67 - 8530 003e BE .byte -66 - 8531 003f BF .byte -65 - 8532 0040 C0 .byte -64 - 8533 0041 C1 .byte -63 - 8534 0042 C2 .byte -62 - 8535 0043 C3 .byte -61 - 8536 0044 C4 .byte -60 - 8537 0045 C5 .byte -59 - 8538 0046 C6 .byte -58 - 8539 0047 C7 .byte -57 - 8540 0048 C8 .byte -56 - 8541 0049 C9 .byte -55 - 8542 004a CA .byte -54 - 8543 004b CB .byte -53 - 8544 004c CC .byte -52 - 8545 004d CD .byte -51 - 8546 004e CE .byte -50 - 8547 004f CF .byte -49 - 8548 0050 D0 .byte -48 - 8549 0051 D1 .byte -47 - 8550 0052 D2 .byte -46 - 8551 0053 D3 .byte -45 - 8552 0054 D4 .byte -44 - 8553 0055 D5 .byte -43 - 8554 0056 D6 .byte -42 - 8555 0057 D7 .byte -41 - 8556 0058 D8 .byte -40 - 8557 0059 D9 .byte -39 - 8558 005a DA .byte -38 - 8559 005b DB .byte -37 - 8560 005c DC .byte -36 - 8561 005d DD .byte -35 - 8562 005e DE .byte -34 - 8563 005f DF .byte -33 - 8564 0060 E0 .byte -32 - 8565 0061 E1 .byte -31 - 8566 0062 E2 .byte -30 - 8567 0063 E3 .byte -29 - 8568 0064 E4 .byte -28 - 8569 0065 E5 .byte -27 - 8570 0066 E6 .byte -26 - 8571 0067 E7 .byte -25 - 8572 0068 E8 .byte -24 - 8573 0069 E9 .byte -23 - 8574 006a EA .byte -22 - 8575 006b EB .byte -21 - 8576 006c EC .byte -20 - 8577 006d ED .byte -19 - 8578 006e EE .byte -18 - 8579 006f EF .byte -17 - 8580 0070 F0 .byte -16 - 8581 0071 F1 .byte -15 - 8582 0072 F2 .byte -14 - 8583 0073 F3 .byte -13 - 8584 0074 F4 .byte -12 - 8585 0075 F5 .byte -11 - 8586 0076 F6 .byte -10 - 8587 0077 F7 .byte -9 - 8588 0078 F8 .byte -8 - 8589 0079 F9 .byte -7 - 8590 007a FA .byte -6 - 8591 007b FB .byte -5 - 8592 007c FC .byte -4 - 8593 007d FD .byte -3 - 8594 007e FE .byte -2 - 8595 007f FF .byte -1 - 8596 .section .rodata.LfnOfs,"a",%progbits - 8597 .align 2 - 8598 .set .LANCHOR2,. + 0 - 8601 LfnOfs: - 8602 0000 01 .byte 1 - 8603 0001 03 .byte 3 - 8604 0002 05 .byte 5 - 8605 0003 07 .byte 7 - 8606 0004 09 .byte 9 - 8607 0005 0E .byte 14 - 8608 0006 10 .byte 16 - 8609 0007 12 .byte 18 - 8610 0008 14 .byte 20 - 8611 0009 16 .byte 22 - 8612 000a 18 .byte 24 - 8613 000b 1C .byte 28 - 8614 000c 1E .byte 30 - 8615 000d 000000 .section .bss.FatFs,"aw",%nobits - 8616 .align 2 - 8617 .set .LANCHOR0,. + 0 - 8620 FatFs: - 8621 0000 00000000 .space 4 - 8622 .text - 8623 .Letext0: - 8624 .file 2 "../../../Source/third_party/fatfs/src/integer.h" - 8625 .file 3 "../../../Source/third_party/fatfs/src/ff.h" - 8626 .file 4 "../../../Source/third_party/fatfs/src/diskio.h" - 8627 .file 5 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\lib\\gcc\\arm-none-eabi\\4.9 - 8628 .file 6 "" -DEFINED SYMBOLS - *ABS*:00000000 ff.c -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:19 .text.mem_cpy:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:23 .text.mem_cpy:00000000 mem_cpy -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:54 .text.ld_clust:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:58 .text.ld_clust:00000000 ld_clust -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:90 .text.sum_sfn:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:94 .text.sum_sfn:00000000 sum_sfn -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:126 .text.check_fs:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:130 .text.check_fs:00000000 check_fs -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:207 .text.check_fs:00000084 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:213 .text.sync_window:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:217 .text.sync_window:00000000 sync_window -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:332 .text.move_window:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:336 .text.move_window:00000000 move_window -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:393 .text.validate:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:397 .text.validate:00000000 validate -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:468 .text.chk_mounted:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:472 .text.chk_mounted:00000000 chk_mounted -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1021 .text.chk_mounted:0000034c $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1029 .text.chk_mounted:00000360 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1067 .text.get_fileinfo:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1071 .text.get_fileinfo:00000000 get_fileinfo -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1347 .text.sync_fs:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1351 .text.sync_fs:00000000 sync_fs -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1469 .text.clust2sect:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1474 .text.clust2sect:00000000 clust2sect -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1503 .text.get_fat:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1508 .text.get_fat:00000000 get_fat -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1683 .text.dir_sdi:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1687 .text.dir_sdi:00000000 dir_sdi -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1837 .text.put_fat:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:1842 .text.put_fat:00000000 put_fat -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:2067 .text.create_chain:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:2071 .text.create_chain:00000000 create_chain -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:2250 .text.dir_next:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:2254 .text.dir_next:00000000 dir_next -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:2506 .text.dir_find:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:2510 .text.dir_find:00000000 dir_find -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:2806 .text.dir_find:00000168 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:2811 .text.follow_path:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:2815 .text.follow_path:00000000 follow_path -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:3409 .text.follow_path:000002f8 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:3416 .text.dir_read:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:3420 .text.dir_read:00000000 dir_read -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:3681 .text.dir_read:00000128 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:3686 .text.dir_remove:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:3690 .text.dir_remove:00000000 dir_remove -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:3771 .text.remove_chain:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:3775 .text.remove_chain:00000000 remove_chain -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:3878 .text.gen_numname:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:3883 .text.gen_numname:00000000 gen_numname -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:4024 .text.dir_register:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:4028 .text.dir_register:00000000 dir_register -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:4453 .text.dir_register:00000204 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:4459 .text.f_mount:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:4464 .text.f_mount:00000000 f_mount -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:4508 .text.f_mount:00000020 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:4513 .text.f_open:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:4518 .text.f_open:00000000 f_open -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:4825 .text.f_open:00000180 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:4830 .text.f_read:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:4835 .text.f_read:00000000 f_read -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:5132 .text.f_write:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:5137 .text.f_write:00000000 f_write -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:5461 .text.f_sync:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:5466 .text.f_sync:00000000 f_sync -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:5602 .text.f_close:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:5607 .text.f_close:00000000 f_close -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:5637 .text.f_lseek:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:5642 .text.f_lseek:00000000 f_lseek -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:5968 .text.f_opendir:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:5973 .text.f_opendir:00000000 f_opendir -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6099 .text.f_opendir:00000080 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6104 .text.f_readdir:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6109 .text.f_readdir:00000000 f_readdir -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6208 .text.f_readdir:00000060 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6213 .text.f_stat:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6218 .text.f_stat:00000000 f_stat -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6286 .text.f_stat:00000044 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6291 .text.f_getfree:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6296 .text.f_getfree:00000000 f_getfree -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6504 .text.f_truncate:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6509 .text.f_truncate:00000000 f_truncate -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6647 .text.f_unlink:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6652 .text.f_unlink:00000000 f_unlink -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6816 .text.f_unlink:000000b8 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6821 .text.f_mkdir:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:6826 .text.f_mkdir:00000000 f_mkdir -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7170 .text.f_mkdir:000001c8 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7175 .text.f_chmod:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7180 .text.f_chmod:00000000 f_chmod -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7266 .text.f_chmod:0000005c $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7271 .text.f_utime:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7276 .text.f_utime:00000000 f_utime -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7363 .text.f_utime:0000005c $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7368 .text.f_rename:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7373 .text.f_rename:00000000 f_rename -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7595 .text.f_rename:00000120 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7600 .text.f_gets:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7605 .text.f_gets:00000000 f_gets -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7685 .text.f_putc:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7690 .text.f_putc:00000000 f_putc -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7740 .text.f_puts:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7745 .text.f_puts:00000000 f_puts -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7798 .text.f_printf:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7803 .text.f_printf:00000000 f_printf -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7966 .text.f_printf:000000c0 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:7989 .text.f_printf:000000ee $t -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:8442 .bss.LfnBuf:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:8446 .bss.LfnBuf:00000000 LfnBuf -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:8449 .bss.Fsid:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:8453 .bss.Fsid:00000000 Fsid -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:8456 .rodata.str1.4:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:8463 .rodata.ExCvt:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:8467 .rodata.ExCvt:00000000 ExCvt -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:8597 .rodata.LfnOfs:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:8601 .rodata.LfnOfs:00000000 LfnOfs -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:8616 .bss.FatFs:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\ccTxfLYu.s:8620 .bss.FatFs:00000000 FatFs - .debug_frame:00000010 $d - -UNDEFINED SYMBOLS -disk_read -disk_write -disk_status -disk_initialize -ff_convert -disk_ioctl -ff_wtoupper -get_fattime diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/file.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/file.lst deleted file mode 100644 index aded1148..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/file.lst +++ /dev/null @@ -1,22 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "file.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .Letext0: -DEFINED SYMBOLS - *ABS*:00000000 file.c - -NO UNDEFINED SYMBOLS diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/flash.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/flash.lst deleted file mode 100644 index 81a94ac3..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/flash.lst +++ /dev/null @@ -1,2133 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "flash.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.FlashLock,"ax",%progbits - 19 .align 2 - 20 .thumb - 21 .thumb_func - 23 FlashLock: - 24 .LFB13: - 25 .file 1 "../../../Source/ARMCM3_STM32/flash.c" - 1:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 2:../../../Source/ARMCM3_STM32/flash.c **** * \file Source\ARMCM3_STM32\flash.c - 3:../../../Source/ARMCM3_STM32/flash.c **** * \brief Bootloader flash driver source file. - 4:../../../Source/ARMCM3_STM32/flash.c **** * \ingroup Target_ARMCM3_STM32 - 5:../../../Source/ARMCM3_STM32/flash.c **** * \internal - 6:../../../Source/ARMCM3_STM32/flash.c **** *---------------------------------------------------------------------------------------- - 7:../../../Source/ARMCM3_STM32/flash.c **** * C O P Y R I G H T - 8:../../../Source/ARMCM3_STM32/flash.c **** *---------------------------------------------------------------------------------------- - 9:../../../Source/ARMCM3_STM32/flash.c **** * Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved - 10:../../../Source/ARMCM3_STM32/flash.c **** * - 11:../../../Source/ARMCM3_STM32/flash.c **** *---------------------------------------------------------------------------------------- - 12:../../../Source/ARMCM3_STM32/flash.c **** * L I C E N S E - 13:../../../Source/ARMCM3_STM32/flash.c **** *---------------------------------------------------------------------------------------- - 14:../../../Source/ARMCM3_STM32/flash.c **** * This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or - 15:../../../Source/ARMCM3_STM32/flash.c **** * modify it under the terms of the GNU General Public License as published by the Free - 16:../../../Source/ARMCM3_STM32/flash.c **** * Software Foundation, either version 3 of the License, or (at your option) any later - 17:../../../Source/ARMCM3_STM32/flash.c **** * version. - 18:../../../Source/ARMCM3_STM32/flash.c **** * - 19:../../../Source/ARMCM3_STM32/flash.c **** * OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; - 20:../../../Source/ARMCM3_STM32/flash.c **** * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - 21:../../../Source/ARMCM3_STM32/flash.c **** * PURPOSE. See the GNU General Public License for more details. - 22:../../../Source/ARMCM3_STM32/flash.c **** * - 23:../../../Source/ARMCM3_STM32/flash.c **** * You should have received a copy of the GNU General Public License along with OpenBLT. - 24:../../../Source/ARMCM3_STM32/flash.c **** * If not, see . - 25:../../../Source/ARMCM3_STM32/flash.c **** * - 26:../../../Source/ARMCM3_STM32/flash.c **** * A special exception to the GPL is included to allow you to distribute a combined work - 27:../../../Source/ARMCM3_STM32/flash.c **** * that includes OpenBLT without being obliged to provide the source code for any - 28:../../../Source/ARMCM3_STM32/flash.c **** * proprietary components. The exception text is included at the bottom of the license - 29:../../../Source/ARMCM3_STM32/flash.c **** * file . - 30:../../../Source/ARMCM3_STM32/flash.c **** * - 31:../../../Source/ARMCM3_STM32/flash.c **** * \endinternal - 32:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 33:../../../Source/ARMCM3_STM32/flash.c **** - 34:../../../Source/ARMCM3_STM32/flash.c **** /**************************************************************************************** - 35:../../../Source/ARMCM3_STM32/flash.c **** * Include files - 36:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 37:../../../Source/ARMCM3_STM32/flash.c **** #include "boot.h" /* bootloader generic header */ - 38:../../../Source/ARMCM3_STM32/flash.c **** - 39:../../../Source/ARMCM3_STM32/flash.c **** - 40:../../../Source/ARMCM3_STM32/flash.c **** /**************************************************************************************** - 41:../../../Source/ARMCM3_STM32/flash.c **** * Macro definitions - 42:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 43:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Value for an invalid flash sector. */ - 44:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_INVALID_SECTOR (0xff) - 45:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Value for an invalid flash address. */ - 46:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_INVALID_ADDRESS (0xffffffff) - 47:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Standard size of a flash block for writing. */ - 48:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_WRITE_BLOCK_SIZE (512) - 49:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Total numbers of sectors in array flashLayout[]. */ - 50:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_TOTAL_SECTORS (sizeof(flashLayout)/sizeof(flashLayout[0])) - 51:../../../Source/ARMCM3_STM32/flash.c **** #if (BOOT_NVM_SIZE_KB > 128) - 52:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Number of bytes to erase per erase operation. */ - 53:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_ERASE_BLOCK_SIZE (0x800) - 54:../../../Source/ARMCM3_STM32/flash.c **** #else - 55:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Number of bytes to erase per erase operation. */ - 56:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_ERASE_BLOCK_SIZE (0x400) - 57:../../../Source/ARMCM3_STM32/flash.c **** #endif - 58:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Macro for accessing the flash control registers. */ - 59:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH ((tFlashRegs *) (blt_int32u)0x40022000) - 60:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Offset into the user program's vector table where the checksum is located. */ - 61:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_VECTOR_TABLE_CS_OFFSET (0x150) - 62:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_KEY1 ((blt_int32u)0x45670123) - 63:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_KEY2 ((blt_int32u)0xCDEF89AB) - 64:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_LOCK_BIT ((blt_int32u)0x00000080) - 65:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_EOP_BIT ((blt_int32u)0x00000020) - 66:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_PGERR_BIT ((blt_int32u)0x00000004) - 67:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_WRPRTERR_BIT ((blt_int32u)0x00000010) - 68:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_BSY_BIT ((blt_int32u)0x00000001) - 69:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_PER_BIT ((blt_int32u)0x00000002) - 70:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_STRT_BIT ((blt_int32u)0x00000040) - 71:../../../Source/ARMCM3_STM32/flash.c **** #define FLASH_PG_BIT ((blt_int32u)0x00000001) - 72:../../../Source/ARMCM3_STM32/flash.c **** - 73:../../../Source/ARMCM3_STM32/flash.c **** - 74:../../../Source/ARMCM3_STM32/flash.c **** /**************************************************************************************** - 75:../../../Source/ARMCM3_STM32/flash.c **** * Type definitions - 76:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 77:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Flash sector descriptor type. */ - 78:../../../Source/ARMCM3_STM32/flash.c **** typedef struct - 79:../../../Source/ARMCM3_STM32/flash.c **** { - 80:../../../Source/ARMCM3_STM32/flash.c **** blt_addr sector_start; /**< sector start address */ - 81:../../../Source/ARMCM3_STM32/flash.c **** blt_int32u sector_size; /**< sector size in bytes */ - 82:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u sector_num; /**< sector number */ - 83:../../../Source/ARMCM3_STM32/flash.c **** } tFlashSector; - 84:../../../Source/ARMCM3_STM32/flash.c **** - 85:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Structure type for grouping flash block information. - 86:../../../Source/ARMCM3_STM32/flash.c **** * \details Programming is done per block of max FLASH_WRITE_BLOCK_SIZE. for this a - 87:../../../Source/ARMCM3_STM32/flash.c **** * flash block manager is implemented in this driver. this flash block manager - 88:../../../Source/ARMCM3_STM32/flash.c **** * depends on this flash block info structure. It holds the base address of - 89:../../../Source/ARMCM3_STM32/flash.c **** * the flash block and the data that should be programmed into the flash - 90:../../../Source/ARMCM3_STM32/flash.c **** * block. The .base_addr must be a multiple of FLASH_WRITE_BLOCK_SIZE. - 91:../../../Source/ARMCM3_STM32/flash.c **** */ - 92:../../../Source/ARMCM3_STM32/flash.c **** typedef struct - 93:../../../Source/ARMCM3_STM32/flash.c **** { - 94:../../../Source/ARMCM3_STM32/flash.c **** blt_addr base_addr; - 95:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u data[FLASH_WRITE_BLOCK_SIZE]; - 96:../../../Source/ARMCM3_STM32/flash.c **** } tFlashBlockInfo; - 97:../../../Source/ARMCM3_STM32/flash.c **** - 98:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Flash controller register layout type. */ - 99:../../../Source/ARMCM3_STM32/flash.c **** typedef struct - 100:../../../Source/ARMCM3_STM32/flash.c **** { - 101:../../../Source/ARMCM3_STM32/flash.c **** volatile blt_int32u ACR; /**< flash access control register */ - 102:../../../Source/ARMCM3_STM32/flash.c **** volatile blt_int32u KEYR; /**< FPEC key register */ - 103:../../../Source/ARMCM3_STM32/flash.c **** volatile blt_int32u OPTKEYR; /**< flash OPTKEY register */ - 104:../../../Source/ARMCM3_STM32/flash.c **** volatile blt_int32u SR; /**< flash status register */ - 105:../../../Source/ARMCM3_STM32/flash.c **** volatile blt_int32u CR; /**< flash control register */ - 106:../../../Source/ARMCM3_STM32/flash.c **** volatile blt_int32u AR; /**< flash address register */ - 107:../../../Source/ARMCM3_STM32/flash.c **** volatile blt_int32u RESERVED; - 108:../../../Source/ARMCM3_STM32/flash.c **** volatile blt_int32u OBR; /**< option byte register */ - 109:../../../Source/ARMCM3_STM32/flash.c **** volatile blt_int32u WRPR; /**< write protection register */ - 110:../../../Source/ARMCM3_STM32/flash.c **** } tFlashRegs; - 111:../../../Source/ARMCM3_STM32/flash.c **** - 112:../../../Source/ARMCM3_STM32/flash.c **** - 113:../../../Source/ARMCM3_STM32/flash.c **** /**************************************************************************************** - 114:../../../Source/ARMCM3_STM32/flash.c **** * Function prototypes - 115:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 116:../../../Source/ARMCM3_STM32/flash.c **** static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address); - 117:../../../Source/ARMCM3_STM32/flash.c **** static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr); - 118:../../../Source/ARMCM3_STM32/flash.c **** static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address, - 119:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u *data, blt_int32u len); - 120:../../../Source/ARMCM3_STM32/flash.c **** static blt_bool FlashWriteBlock(tFlashBlockInfo *block); - 121:../../../Source/ARMCM3_STM32/flash.c **** static blt_bool FlashEraseSectors(blt_int8u first_sector, blt_int8u last_sector); - 122:../../../Source/ARMCM3_STM32/flash.c **** static void FlashUnlock(void); - 123:../../../Source/ARMCM3_STM32/flash.c **** static void FlashLock(void); - 124:../../../Source/ARMCM3_STM32/flash.c **** static blt_int8u FlashGetSector(blt_addr address); - 125:../../../Source/ARMCM3_STM32/flash.c **** static blt_addr FlashGetSectorBaseAddr(blt_int8u sector); - 126:../../../Source/ARMCM3_STM32/flash.c **** static blt_addr FlashGetSectorSize(blt_int8u sector); - 127:../../../Source/ARMCM3_STM32/flash.c **** - 128:../../../Source/ARMCM3_STM32/flash.c **** - 129:../../../Source/ARMCM3_STM32/flash.c **** /**************************************************************************************** - 130:../../../Source/ARMCM3_STM32/flash.c **** * Local constant declarations - 131:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 132:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Array wit the layout of the flash memory. - 133:../../../Source/ARMCM3_STM32/flash.c **** * \details Also controls what part of the flash memory is reserved for the bootloader. - 134:../../../Source/ARMCM3_STM32/flash.c **** * If the bootloader size changes, the reserved sectors for the bootloader - 135:../../../Source/ARMCM3_STM32/flash.c **** * might need adjustment to make sure the bootloader doesn't get overwritten. - 136:../../../Source/ARMCM3_STM32/flash.c **** * The current flash layout does not reflect the minimum sector size of the - 137:../../../Source/ARMCM3_STM32/flash.c **** * physical flash (1 - 2kb), because this would make the table quit long and - 138:../../../Source/ARMCM3_STM32/flash.c **** * a waste of ROM. The minimum sector size is only really needed when erasing - 139:../../../Source/ARMCM3_STM32/flash.c **** * the flash. This can still be done in combination with macro - 140:../../../Source/ARMCM3_STM32/flash.c **** * FLASH_ERASE_BLOCK_SIZE. - 141:../../../Source/ARMCM3_STM32/flash.c **** */ - 142:../../../Source/ARMCM3_STM32/flash.c **** static const tFlashSector flashLayout[] = - 143:../../../Source/ARMCM3_STM32/flash.c **** { - 144:../../../Source/ARMCM3_STM32/flash.c **** /* space is reserved for a bootloader configuration with all supported communication - 145:../../../Source/ARMCM3_STM32/flash.c **** * interfaces enabled. when for example only UART is needed, than the space required - 146:../../../Source/ARMCM3_STM32/flash.c **** * for the bootloader can be made a lot smaller here. - 147:../../../Source/ARMCM3_STM32/flash.c **** */ - 148:../../../Source/ARMCM3_STM32/flash.c **** /* { 0x08000000, 0x02000, 0}, flash sector 0 - reserved for bootloader */ - 149:../../../Source/ARMCM3_STM32/flash.c **** /* { 0x08002000, 0x02000, 1}, flash sector 1 - reserved for bootloader */ - 150:../../../Source/ARMCM3_STM32/flash.c **** /* { 0x08004000, 0x02000, 2}, flash sector 2 - reserved for bootloader */ - 151:../../../Source/ARMCM3_STM32/flash.c **** { 0x08006000, 0x02000, 3}, /* flash sector 3 - 8kb */ - 152:../../../Source/ARMCM3_STM32/flash.c **** #if (BOOT_NVM_SIZE_KB > 32) - 153:../../../Source/ARMCM3_STM32/flash.c **** { 0x08008000, 0x02000, 4}, /* flash sector 4 - 8kb */ - 154:../../../Source/ARMCM3_STM32/flash.c **** { 0x0800A000, 0x02000, 5}, /* flash sector 5 - 8kb */ - 155:../../../Source/ARMCM3_STM32/flash.c **** { 0x0800C000, 0x02000, 6}, /* flash sector 6 - 8kb */ - 156:../../../Source/ARMCM3_STM32/flash.c **** { 0x0800E000, 0x02000, 7}, /* flash sector 7 - 8kb */ - 157:../../../Source/ARMCM3_STM32/flash.c **** #endif - 158:../../../Source/ARMCM3_STM32/flash.c **** #if (BOOT_NVM_SIZE_KB > 64) - 159:../../../Source/ARMCM3_STM32/flash.c **** { 0x08010000, 0x02000, 8}, /* flash sector 8 - 8kb */ - 160:../../../Source/ARMCM3_STM32/flash.c **** { 0x08012000, 0x02000, 9}, /* flash sector 9 - 8kb */ - 161:../../../Source/ARMCM3_STM32/flash.c **** { 0x08014000, 0x02000, 10}, /* flash sector 10 - 8kb */ - 162:../../../Source/ARMCM3_STM32/flash.c **** { 0x08016000, 0x02000, 11}, /* flash sector 11 - 8kb */ - 163:../../../Source/ARMCM3_STM32/flash.c **** { 0x08018000, 0x02000, 12}, /* flash sector 12 - 8kb */ - 164:../../../Source/ARMCM3_STM32/flash.c **** { 0x0801A000, 0x02000, 13}, /* flash sector 13 - 8kb */ - 165:../../../Source/ARMCM3_STM32/flash.c **** { 0x0801C000, 0x02000, 14}, /* flash sector 14 - 8kb */ - 166:../../../Source/ARMCM3_STM32/flash.c **** { 0x0801E000, 0x02000, 15}, /* flash sector 15 - 8kb */ - 167:../../../Source/ARMCM3_STM32/flash.c **** #endif - 168:../../../Source/ARMCM3_STM32/flash.c **** #if (BOOT_NVM_SIZE_KB > 128) - 169:../../../Source/ARMCM3_STM32/flash.c **** { 0x08020000, 0x08000, 16}, /* flash sector 16 - 32kb */ - 170:../../../Source/ARMCM3_STM32/flash.c **** { 0x08028000, 0x08000, 17}, /* flash sector 17 - 32kb */ - 171:../../../Source/ARMCM3_STM32/flash.c **** { 0x08030000, 0x08000, 18}, /* flash sector 18 - 32kb */ - 172:../../../Source/ARMCM3_STM32/flash.c **** { 0x08038000, 0x08000, 19}, /* flash sector 19 - 32kb */ - 173:../../../Source/ARMCM3_STM32/flash.c **** #endif - 174:../../../Source/ARMCM3_STM32/flash.c **** #if (BOOT_NVM_SIZE_KB > 256) - 175:../../../Source/ARMCM3_STM32/flash.c **** { 0x08040000, 0x08000, 20}, /* flash sector 20 - 32kb */ - 176:../../../Source/ARMCM3_STM32/flash.c **** { 0x08048000, 0x08000, 21}, /* flash sector 21 - 32kb */ - 177:../../../Source/ARMCM3_STM32/flash.c **** { 0x08050000, 0x08000, 22}, /* flash sector 22 - 32kb */ - 178:../../../Source/ARMCM3_STM32/flash.c **** { 0x08058000, 0x08000, 23}, /* flash sector 23 - 32kb */ - 179:../../../Source/ARMCM3_STM32/flash.c **** { 0x08060000, 0x08000, 24}, /* flash sector 24 - 32kb */ - 180:../../../Source/ARMCM3_STM32/flash.c **** { 0x08068000, 0x08000, 25}, /* flash sector 25 - 32kb */ - 181:../../../Source/ARMCM3_STM32/flash.c **** { 0x08070000, 0x08000, 26}, /* flash sector 26 - 32kb */ - 182:../../../Source/ARMCM3_STM32/flash.c **** { 0x08078000, 0x08000, 27}, /* flash sector 27 - 32kb */ - 183:../../../Source/ARMCM3_STM32/flash.c **** #endif - 184:../../../Source/ARMCM3_STM32/flash.c **** #if (BOOT_NVM_SIZE_KB > 512) - 185:../../../Source/ARMCM3_STM32/flash.c **** #error "BOOT_NVM_SIZE_KB > 512 is currently not supported." - 186:../../../Source/ARMCM3_STM32/flash.c **** #endif - 187:../../../Source/ARMCM3_STM32/flash.c **** }; - 188:../../../Source/ARMCM3_STM32/flash.c **** - 189:../../../Source/ARMCM3_STM32/flash.c **** - 190:../../../Source/ARMCM3_STM32/flash.c **** /**************************************************************************************** - 191:../../../Source/ARMCM3_STM32/flash.c **** * Local data declarations - 192:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 193:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Local variable with information about the flash block that is currently - 194:../../../Source/ARMCM3_STM32/flash.c **** * being operated on. - 195:../../../Source/ARMCM3_STM32/flash.c **** * \details The smallest amount of flash that can be programmed is - 196:../../../Source/ARMCM3_STM32/flash.c **** * FLASH_WRITE_BLOCK_SIZE. A flash block manager is implemented in this driver - 197:../../../Source/ARMCM3_STM32/flash.c **** * and stores info in this variable. Whenever new data should be flashed, it - 198:../../../Source/ARMCM3_STM32/flash.c **** * is first added to a RAM buffer, which is part of this variable. Whenever - 199:../../../Source/ARMCM3_STM32/flash.c **** * the RAM buffer, which has the size of a flash block, is full or data needs - 200:../../../Source/ARMCM3_STM32/flash.c **** * to be written to a different block, the contents of the RAM buffer are - 201:../../../Source/ARMCM3_STM32/flash.c **** * programmed to flash. The flash block manager requires some software - 202:../../../Source/ARMCM3_STM32/flash.c **** * overhead, yet results is faster flash programming because data is first - 203:../../../Source/ARMCM3_STM32/flash.c **** * harvested, ideally until there is enough to program an entire flash block, - 204:../../../Source/ARMCM3_STM32/flash.c **** * before the flash device is actually operated on. - 205:../../../Source/ARMCM3_STM32/flash.c **** */ - 206:../../../Source/ARMCM3_STM32/flash.c **** static tFlashBlockInfo blockInfo; - 207:../../../Source/ARMCM3_STM32/flash.c **** - 208:../../../Source/ARMCM3_STM32/flash.c **** /** \brief Local variable with information about the flash boot block. - 209:../../../Source/ARMCM3_STM32/flash.c **** * \details The first block of the user program holds the vector table, which on the - 210:../../../Source/ARMCM3_STM32/flash.c **** * STM32 is also the where the checksum is written to. Is it likely that - 211:../../../Source/ARMCM3_STM32/flash.c **** * the vector table is first flashed and then, at the end of the programming - 212:../../../Source/ARMCM3_STM32/flash.c **** * sequence, the checksum. This means that this flash block need to be written - 213:../../../Source/ARMCM3_STM32/flash.c **** * to twice. Normally this is not a problem with flash memory, as long as you - 214:../../../Source/ARMCM3_STM32/flash.c **** * write the same values to those bytes that are not supposed to be changed - 215:../../../Source/ARMCM3_STM32/flash.c **** * and the locations where you do write to are still in the erased 0xFF state. - 216:../../../Source/ARMCM3_STM32/flash.c **** * Unfortunately, writing twice to flash this way, does not work reliably on - 217:../../../Source/ARMCM3_STM32/flash.c **** * all micros. This is why we need to have an extra block, the bootblock, - 218:../../../Source/ARMCM3_STM32/flash.c **** * placed under the management of the block manager. This way is it possible - 219:../../../Source/ARMCM3_STM32/flash.c **** * to implement functionality so that the bootblock is only written to once - 220:../../../Source/ARMCM3_STM32/flash.c **** * at the end of the programming sequence. - 221:../../../Source/ARMCM3_STM32/flash.c **** */ - 222:../../../Source/ARMCM3_STM32/flash.c **** static tFlashBlockInfo bootBlockInfo; - 223:../../../Source/ARMCM3_STM32/flash.c **** - 224:../../../Source/ARMCM3_STM32/flash.c **** - 225:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 226:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Initializes the flash driver. - 227:../../../Source/ARMCM3_STM32/flash.c **** ** \return none. - 228:../../../Source/ARMCM3_STM32/flash.c **** ** - 229:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 230:../../../Source/ARMCM3_STM32/flash.c **** void FlashInit(void) - 231:../../../Source/ARMCM3_STM32/flash.c **** { - 232:../../../Source/ARMCM3_STM32/flash.c **** /* init the flash block info structs by setting the address to an invalid address */ - 233:../../../Source/ARMCM3_STM32/flash.c **** blockInfo.base_addr = FLASH_INVALID_ADDRESS; - 234:../../../Source/ARMCM3_STM32/flash.c **** bootBlockInfo.base_addr = FLASH_INVALID_ADDRESS; - 235:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashInit ***/ - 236:../../../Source/ARMCM3_STM32/flash.c **** - 237:../../../Source/ARMCM3_STM32/flash.c **** - 238:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 239:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Writes the data to flash through a flash block manager. Note that this - 240:../../../Source/ARMCM3_STM32/flash.c **** ** function also checks that no data is programmed outside the flash - 241:../../../Source/ARMCM3_STM32/flash.c **** ** memory region, so the bootloader can never be overwritten. - 242:../../../Source/ARMCM3_STM32/flash.c **** ** \param addr Start address. - 243:../../../Source/ARMCM3_STM32/flash.c **** ** \param len Length in bytes. - 244:../../../Source/ARMCM3_STM32/flash.c **** ** \param data Pointer to the data buffer. - 245:../../../Source/ARMCM3_STM32/flash.c **** ** \return BLT_TRUE if successful, BLT_FALSE otherwise. - 246:../../../Source/ARMCM3_STM32/flash.c **** ** - 247:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 248:../../../Source/ARMCM3_STM32/flash.c **** blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data) - 249:../../../Source/ARMCM3_STM32/flash.c **** { - 250:../../../Source/ARMCM3_STM32/flash.c **** blt_addr base_addr; - 251:../../../Source/ARMCM3_STM32/flash.c **** - 252:../../../Source/ARMCM3_STM32/flash.c **** /* make sure the addresses are within the flash device */ - 253:../../../Source/ARMCM3_STM32/flash.c **** if ( (FlashGetSector(addr) == FLASH_INVALID_SECTOR) || \ - 254:../../../Source/ARMCM3_STM32/flash.c **** (FlashGetSector(addr+len-1) == FLASH_INVALID_SECTOR) ) - 255:../../../Source/ARMCM3_STM32/flash.c **** { - 256:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 257:../../../Source/ARMCM3_STM32/flash.c **** } - 258:../../../Source/ARMCM3_STM32/flash.c **** - 259:../../../Source/ARMCM3_STM32/flash.c **** /* if this is the bootblock, then let the boot block manager handle it */ - 260:../../../Source/ARMCM3_STM32/flash.c **** base_addr = (addr/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE; - 261:../../../Source/ARMCM3_STM32/flash.c **** if (base_addr == flashLayout[0].sector_start) - 262:../../../Source/ARMCM3_STM32/flash.c **** { - 263:../../../Source/ARMCM3_STM32/flash.c **** /* let the boot block manager handle it */ - 264:../../../Source/ARMCM3_STM32/flash.c **** return FlashAddToBlock(&bootBlockInfo, addr, data, len); - 265:../../../Source/ARMCM3_STM32/flash.c **** } - 266:../../../Source/ARMCM3_STM32/flash.c **** /* let the block manager handle it */ - 267:../../../Source/ARMCM3_STM32/flash.c **** return FlashAddToBlock(&blockInfo, addr, data, len); - 268:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashWrite ***/ - 269:../../../Source/ARMCM3_STM32/flash.c **** - 270:../../../Source/ARMCM3_STM32/flash.c **** - 271:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 272:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Erases the flash memory. Note that this function also checks that no - 273:../../../Source/ARMCM3_STM32/flash.c **** ** data is erased outside the flash memory region, so the bootloader can - 274:../../../Source/ARMCM3_STM32/flash.c **** ** never be erased. - 275:../../../Source/ARMCM3_STM32/flash.c **** ** \param addr Start address. - 276:../../../Source/ARMCM3_STM32/flash.c **** ** \param len Length in bytes. - 277:../../../Source/ARMCM3_STM32/flash.c **** ** \return BLT_TRUE if successful, BLT_FALSE otherwise. - 278:../../../Source/ARMCM3_STM32/flash.c **** ** - 279:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 280:../../../Source/ARMCM3_STM32/flash.c **** blt_bool FlashErase(blt_addr addr, blt_int32u len) - 281:../../../Source/ARMCM3_STM32/flash.c **** { - 282:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u first_sector; - 283:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u last_sector; - 284:../../../Source/ARMCM3_STM32/flash.c **** - 285:../../../Source/ARMCM3_STM32/flash.c **** /* obtain the first and last sector number */ - 286:../../../Source/ARMCM3_STM32/flash.c **** first_sector = FlashGetSector(addr); - 287:../../../Source/ARMCM3_STM32/flash.c **** last_sector = FlashGetSector(addr+len-1); - 288:../../../Source/ARMCM3_STM32/flash.c **** /* check them */ - 289:../../../Source/ARMCM3_STM32/flash.c **** if ( (first_sector == FLASH_INVALID_SECTOR) || (last_sector == FLASH_INVALID_SECTOR) ) - 290:../../../Source/ARMCM3_STM32/flash.c **** { - 291:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 292:../../../Source/ARMCM3_STM32/flash.c **** } - 293:../../../Source/ARMCM3_STM32/flash.c **** /* erase the sectors */ - 294:../../../Source/ARMCM3_STM32/flash.c **** return FlashEraseSectors(first_sector, last_sector); - 295:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashErase ***/ - 296:../../../Source/ARMCM3_STM32/flash.c **** - 297:../../../Source/ARMCM3_STM32/flash.c **** - 298:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 299:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Writes a checksum of the user program to non-volatile memory. This is - 300:../../../Source/ARMCM3_STM32/flash.c **** ** performed once the entire user program has been programmed. Through - 301:../../../Source/ARMCM3_STM32/flash.c **** ** the checksum, the bootloader can check if the programming session - 302:../../../Source/ARMCM3_STM32/flash.c **** ** was completed, which indicates that a valid user programming is - 303:../../../Source/ARMCM3_STM32/flash.c **** ** present and can be started. - 304:../../../Source/ARMCM3_STM32/flash.c **** ** \return BLT_TRUE if successful, BLT_FALSE otherwise. - 305:../../../Source/ARMCM3_STM32/flash.c **** ** - 306:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 307:../../../Source/ARMCM3_STM32/flash.c **** blt_bool FlashWriteChecksum(void) - 308:../../../Source/ARMCM3_STM32/flash.c **** { - 309:../../../Source/ARMCM3_STM32/flash.c **** blt_int32u signature_checksum = 0; - 310:../../../Source/ARMCM3_STM32/flash.c **** - 311:../../../Source/ARMCM3_STM32/flash.c **** /* for the STM32 target we defined the checksum as the Two's complement value of the - 312:../../../Source/ARMCM3_STM32/flash.c **** * sum of the first 7 exception addresses. - 313:../../../Source/ARMCM3_STM32/flash.c **** * - 314:../../../Source/ARMCM3_STM32/flash.c **** * Layout of the vector table: - 315:../../../Source/ARMCM3_STM32/flash.c **** * 0x08000000 Initial stack pointer - 316:../../../Source/ARMCM3_STM32/flash.c **** * 0x08000004 Reset Handler - 317:../../../Source/ARMCM3_STM32/flash.c **** * 0x08000008 NMI Handler - 318:../../../Source/ARMCM3_STM32/flash.c **** * 0x0800000C Hard Fault Handler - 319:../../../Source/ARMCM3_STM32/flash.c **** * 0x08000010 MPU Fault Handler - 320:../../../Source/ARMCM3_STM32/flash.c **** * 0x08000014 Bus Fault Handler - 321:../../../Source/ARMCM3_STM32/flash.c **** * 0x08000018 Usage Fault Handler - 322:../../../Source/ARMCM3_STM32/flash.c **** * - 323:../../../Source/ARMCM3_STM32/flash.c **** * signature_checksum = Two's complement of (SUM(exception address values)) - 324:../../../Source/ARMCM3_STM32/flash.c **** * - 325:../../../Source/ARMCM3_STM32/flash.c **** * the bootloader writes this 32-bit checksum value right after the vector table - 326:../../../Source/ARMCM3_STM32/flash.c **** * of the user program. note that this means one extra dummy entry must be added - 327:../../../Source/ARMCM3_STM32/flash.c **** * at the end of the user program's vector table to reserve storage space for the - 328:../../../Source/ARMCM3_STM32/flash.c **** * checksum. - 329:../../../Source/ARMCM3_STM32/flash.c **** */ - 330:../../../Source/ARMCM3_STM32/flash.c **** - 331:../../../Source/ARMCM3_STM32/flash.c **** /* first check that the bootblock contains valid data. if not, this means the - 332:../../../Source/ARMCM3_STM32/flash.c **** * bootblock is not part of the reprogramming this time and therefore no - 333:../../../Source/ARMCM3_STM32/flash.c **** * new checksum needs to be written - 334:../../../Source/ARMCM3_STM32/flash.c **** */ - 335:../../../Source/ARMCM3_STM32/flash.c **** if (bootBlockInfo.base_addr == FLASH_INVALID_ADDRESS) - 336:../../../Source/ARMCM3_STM32/flash.c **** { - 337:../../../Source/ARMCM3_STM32/flash.c **** return BLT_TRUE; - 338:../../../Source/ARMCM3_STM32/flash.c **** } - 339:../../../Source/ARMCM3_STM32/flash.c **** - 340:../../../Source/ARMCM3_STM32/flash.c **** /* compute the checksum. note that the user program's vectors are not yet written - 341:../../../Source/ARMCM3_STM32/flash.c **** * to flash but are present in the bootblock data structure at this point. - 342:../../../Source/ARMCM3_STM32/flash.c **** */ - 343:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x00])); - 344:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x04])); - 345:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x08])); - 346:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x0C])); - 347:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x10])); - 348:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x14])); - 349:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x18])); - 350:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum = ~signature_checksum; /* one's complement */ - 351:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += 1; /* two's complement */ - 352:../../../Source/ARMCM3_STM32/flash.c **** - 353:../../../Source/ARMCM3_STM32/flash.c **** /* write the checksum */ - 354:../../../Source/ARMCM3_STM32/flash.c **** return FlashWrite(flashLayout[0].sector_start+FLASH_VECTOR_TABLE_CS_OFFSET, - 355:../../../Source/ARMCM3_STM32/flash.c **** sizeof(blt_addr), (blt_int8u*)&signature_checksum); - 356:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashWriteChecksum ***/ - 357:../../../Source/ARMCM3_STM32/flash.c **** - 358:../../../Source/ARMCM3_STM32/flash.c **** - 359:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 360:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Verifies the checksum, which indicates that a valid user program is - 361:../../../Source/ARMCM3_STM32/flash.c **** ** present and can be started. - 362:../../../Source/ARMCM3_STM32/flash.c **** ** \return BLT_TRUE if successful, BLT_FALSE otherwise. - 363:../../../Source/ARMCM3_STM32/flash.c **** ** - 364:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 365:../../../Source/ARMCM3_STM32/flash.c **** blt_bool FlashVerifyChecksum(void) - 366:../../../Source/ARMCM3_STM32/flash.c **** { - 367:../../../Source/ARMCM3_STM32/flash.c **** blt_int32u signature_checksum = 0; - 368:../../../Source/ARMCM3_STM32/flash.c **** - 369:../../../Source/ARMCM3_STM32/flash.c **** /* verify the checksum based on how it was written by CpuWriteChecksum() */ - 370:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start)); - 371:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x04)); - 372:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x08)); - 373:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x0C)); - 374:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x10)); - 375:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x14)); - 376:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x18)); - 377:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+FLASH_VECTOR_TABLE_CS_OFFSET)); - 378:../../../Source/ARMCM3_STM32/flash.c **** /* sum should add up to an unsigned 32-bit value of 0 */ - 379:../../../Source/ARMCM3_STM32/flash.c **** if (signature_checksum == 0) - 380:../../../Source/ARMCM3_STM32/flash.c **** { - 381:../../../Source/ARMCM3_STM32/flash.c **** /* checksum okay */ - 382:../../../Source/ARMCM3_STM32/flash.c **** return BLT_TRUE; - 383:../../../Source/ARMCM3_STM32/flash.c **** } - 384:../../../Source/ARMCM3_STM32/flash.c **** /* checksum incorrect */ - 385:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 386:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashVerifyChecksum ***/ - 387:../../../Source/ARMCM3_STM32/flash.c **** - 388:../../../Source/ARMCM3_STM32/flash.c **** - 389:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 390:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Finalizes the flash driver operations. There could still be data in - 391:../../../Source/ARMCM3_STM32/flash.c **** ** the currently active block that needs to be flashed. - 392:../../../Source/ARMCM3_STM32/flash.c **** ** \return BLT_TRUE if successful, BLT_FALSE otherwise. - 393:../../../Source/ARMCM3_STM32/flash.c **** ** - 394:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 395:../../../Source/ARMCM3_STM32/flash.c **** blt_bool FlashDone(void) - 396:../../../Source/ARMCM3_STM32/flash.c **** { - 397:../../../Source/ARMCM3_STM32/flash.c **** /* check if there is still data waiting to be programmed in the boot block */ - 398:../../../Source/ARMCM3_STM32/flash.c **** if (bootBlockInfo.base_addr != FLASH_INVALID_ADDRESS) - 399:../../../Source/ARMCM3_STM32/flash.c **** { - 400:../../../Source/ARMCM3_STM32/flash.c **** if (FlashWriteBlock(&bootBlockInfo) == BLT_FALSE) - 401:../../../Source/ARMCM3_STM32/flash.c **** { - 402:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 403:../../../Source/ARMCM3_STM32/flash.c **** } - 404:../../../Source/ARMCM3_STM32/flash.c **** } - 405:../../../Source/ARMCM3_STM32/flash.c **** - 406:../../../Source/ARMCM3_STM32/flash.c **** /* check if there is still data waiting to be programmed */ - 407:../../../Source/ARMCM3_STM32/flash.c **** if (blockInfo.base_addr != FLASH_INVALID_ADDRESS) - 408:../../../Source/ARMCM3_STM32/flash.c **** { - 409:../../../Source/ARMCM3_STM32/flash.c **** if (FlashWriteBlock(&blockInfo) == BLT_FALSE) - 410:../../../Source/ARMCM3_STM32/flash.c **** { - 411:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 412:../../../Source/ARMCM3_STM32/flash.c **** } - 413:../../../Source/ARMCM3_STM32/flash.c **** } - 414:../../../Source/ARMCM3_STM32/flash.c **** /* still here so all is okay */ - 415:../../../Source/ARMCM3_STM32/flash.c **** return BLT_TRUE; - 416:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashDone ***/ - 417:../../../Source/ARMCM3_STM32/flash.c **** - 418:../../../Source/ARMCM3_STM32/flash.c **** - 419:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 420:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Obtains the base address of the flash memory available to the user program. - 421:../../../Source/ARMCM3_STM32/flash.c **** ** This is basically the first address in the flashLayout table. - 422:../../../Source/ARMCM3_STM32/flash.c **** ** \return Base address. - 423:../../../Source/ARMCM3_STM32/flash.c **** ** - 424:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 425:../../../Source/ARMCM3_STM32/flash.c **** blt_addr FlashGetUserProgBaseAddress(void) - 426:../../../Source/ARMCM3_STM32/flash.c **** { - 427:../../../Source/ARMCM3_STM32/flash.c **** return flashLayout[0].sector_start; - 428:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashGetUserProgBaseAddress ***/ - 429:../../../Source/ARMCM3_STM32/flash.c **** - 430:../../../Source/ARMCM3_STM32/flash.c **** - 431:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 432:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Copies data currently in flash to the block->data and sets the - 433:../../../Source/ARMCM3_STM32/flash.c **** ** base address. - 434:../../../Source/ARMCM3_STM32/flash.c **** ** \param block Pointer to flash block info structure to operate on. - 435:../../../Source/ARMCM3_STM32/flash.c **** ** \param address Base address of the block data. - 436:../../../Source/ARMCM3_STM32/flash.c **** ** \return BLT_TRUE if successful, BLT_FALSE otherwise. - 437:../../../Source/ARMCM3_STM32/flash.c **** ** - 438:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 439:../../../Source/ARMCM3_STM32/flash.c **** static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address) - 440:../../../Source/ARMCM3_STM32/flash.c **** { - 441:../../../Source/ARMCM3_STM32/flash.c **** /* check address alignment */ - 442:../../../Source/ARMCM3_STM32/flash.c **** if ((address % FLASH_WRITE_BLOCK_SIZE) != 0) - 443:../../../Source/ARMCM3_STM32/flash.c **** { - 444:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 445:../../../Source/ARMCM3_STM32/flash.c **** } - 446:../../../Source/ARMCM3_STM32/flash.c **** /* make sure that we are initializing a new block and not the same one */ - 447:../../../Source/ARMCM3_STM32/flash.c **** if (block->base_addr == address) - 448:../../../Source/ARMCM3_STM32/flash.c **** { - 449:../../../Source/ARMCM3_STM32/flash.c **** /* block already initialized, so nothing to do */ - 450:../../../Source/ARMCM3_STM32/flash.c **** return BLT_TRUE; - 451:../../../Source/ARMCM3_STM32/flash.c **** } - 452:../../../Source/ARMCM3_STM32/flash.c **** /* set the base address and copies the current data from flash */ - 453:../../../Source/ARMCM3_STM32/flash.c **** block->base_addr = address; - 454:../../../Source/ARMCM3_STM32/flash.c **** CpuMemCopy((blt_addr)block->data, address, FLASH_WRITE_BLOCK_SIZE); - 455:../../../Source/ARMCM3_STM32/flash.c **** return BLT_TRUE; - 456:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashInitBlock ***/ - 457:../../../Source/ARMCM3_STM32/flash.c **** - 458:../../../Source/ARMCM3_STM32/flash.c **** - 459:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 460:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Switches blocks by programming the current one and initializing the - 461:../../../Source/ARMCM3_STM32/flash.c **** ** next. - 462:../../../Source/ARMCM3_STM32/flash.c **** ** \param block Pointer to flash block info structure to operate on. - 463:../../../Source/ARMCM3_STM32/flash.c **** ** \param base_addr Base address of the next block. - 464:../../../Source/ARMCM3_STM32/flash.c **** ** \return The pointer of the block info struct that is no being used, or a NULL - 465:../../../Source/ARMCM3_STM32/flash.c **** ** pointer in case of error. - 466:../../../Source/ARMCM3_STM32/flash.c **** ** - 467:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 468:../../../Source/ARMCM3_STM32/flash.c **** static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr) - 469:../../../Source/ARMCM3_STM32/flash.c **** { - 470:../../../Source/ARMCM3_STM32/flash.c **** /* check if a switch needs to be made away from the boot block. in this case the boot - 471:../../../Source/ARMCM3_STM32/flash.c **** * block shouldn't be written yet, because this is done at the end of the programming - 472:../../../Source/ARMCM3_STM32/flash.c **** * session by FlashDone(), this is right after the checksum was written. - 473:../../../Source/ARMCM3_STM32/flash.c **** */ - 474:../../../Source/ARMCM3_STM32/flash.c **** if (block == &bootBlockInfo) - 475:../../../Source/ARMCM3_STM32/flash.c **** { - 476:../../../Source/ARMCM3_STM32/flash.c **** /* switch from the boot block to the generic block info structure */ - 477:../../../Source/ARMCM3_STM32/flash.c **** block = &blockInfo; - 478:../../../Source/ARMCM3_STM32/flash.c **** } - 479:../../../Source/ARMCM3_STM32/flash.c **** /* check if a switch back into the bootblock is needed. in this case the generic block - 480:../../../Source/ARMCM3_STM32/flash.c **** * doesn't need to be written here yet. - 481:../../../Source/ARMCM3_STM32/flash.c **** */ - 482:../../../Source/ARMCM3_STM32/flash.c **** else if (base_addr == flashLayout[0].sector_start) - 483:../../../Source/ARMCM3_STM32/flash.c **** { - 484:../../../Source/ARMCM3_STM32/flash.c **** /* switch from the generic block to the boot block info structure */ - 485:../../../Source/ARMCM3_STM32/flash.c **** block = &bootBlockInfo; - 486:../../../Source/ARMCM3_STM32/flash.c **** base_addr = flashLayout[0].sector_start; - 487:../../../Source/ARMCM3_STM32/flash.c **** } - 488:../../../Source/ARMCM3_STM32/flash.c **** else - 489:../../../Source/ARMCM3_STM32/flash.c **** { - 490:../../../Source/ARMCM3_STM32/flash.c **** /* need to switch to a new block, so program the current one and init the next */ - 491:../../../Source/ARMCM3_STM32/flash.c **** if (FlashWriteBlock(block) == BLT_FALSE) - 492:../../../Source/ARMCM3_STM32/flash.c **** { - 493:../../../Source/ARMCM3_STM32/flash.c **** return BLT_NULL; - 494:../../../Source/ARMCM3_STM32/flash.c **** } - 495:../../../Source/ARMCM3_STM32/flash.c **** } - 496:../../../Source/ARMCM3_STM32/flash.c **** - 497:../../../Source/ARMCM3_STM32/flash.c **** /* initialize tne new block when necessary */ - 498:../../../Source/ARMCM3_STM32/flash.c **** if (FlashInitBlock(block, base_addr) == BLT_FALSE) - 499:../../../Source/ARMCM3_STM32/flash.c **** { - 500:../../../Source/ARMCM3_STM32/flash.c **** return BLT_NULL; - 501:../../../Source/ARMCM3_STM32/flash.c **** } - 502:../../../Source/ARMCM3_STM32/flash.c **** - 503:../../../Source/ARMCM3_STM32/flash.c **** /* still here to all is okay */ - 504:../../../Source/ARMCM3_STM32/flash.c **** return block; - 505:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashSwitchBlock ***/ - 506:../../../Source/ARMCM3_STM32/flash.c **** - 507:../../../Source/ARMCM3_STM32/flash.c **** - 508:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 509:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Programming is done per block. This function adds data to the block - 510:../../../Source/ARMCM3_STM32/flash.c **** ** that is currently collecting data to be written to flash. If the - 511:../../../Source/ARMCM3_STM32/flash.c **** ** address is outside of the current block, the current block is written - 512:../../../Source/ARMCM3_STM32/flash.c **** ** to flash an a new block is initialized. - 513:../../../Source/ARMCM3_STM32/flash.c **** ** \param block Pointer to flash block info structure to operate on. - 514:../../../Source/ARMCM3_STM32/flash.c **** ** \param address Flash destination address. - 515:../../../Source/ARMCM3_STM32/flash.c **** ** \param data Pointer to the byte array with data. - 516:../../../Source/ARMCM3_STM32/flash.c **** ** \param len Number of bytes to add to the block. - 517:../../../Source/ARMCM3_STM32/flash.c **** ** \return BLT_TRUE if successful, BLT_FALSE otherwise. - 518:../../../Source/ARMCM3_STM32/flash.c **** ** - 519:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 520:../../../Source/ARMCM3_STM32/flash.c **** static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address, - 521:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u *data, blt_int32u len) - 522:../../../Source/ARMCM3_STM32/flash.c **** { - 523:../../../Source/ARMCM3_STM32/flash.c **** blt_addr current_base_addr; - 524:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u *dst; - 525:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u *src; - 526:../../../Source/ARMCM3_STM32/flash.c **** - 527:../../../Source/ARMCM3_STM32/flash.c **** /* determine the current base address */ - 528:../../../Source/ARMCM3_STM32/flash.c **** current_base_addr = (address/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE; - 529:../../../Source/ARMCM3_STM32/flash.c **** - 530:../../../Source/ARMCM3_STM32/flash.c **** /* make sure the blockInfo is not uninitialized */ - 531:../../../Source/ARMCM3_STM32/flash.c **** if (block->base_addr == FLASH_INVALID_ADDRESS) - 532:../../../Source/ARMCM3_STM32/flash.c **** { - 533:../../../Source/ARMCM3_STM32/flash.c **** /* initialize the blockInfo struct for the current block */ - 534:../../../Source/ARMCM3_STM32/flash.c **** if (FlashInitBlock(block, current_base_addr) == BLT_FALSE) - 535:../../../Source/ARMCM3_STM32/flash.c **** { - 536:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 537:../../../Source/ARMCM3_STM32/flash.c **** } - 538:../../../Source/ARMCM3_STM32/flash.c **** } - 539:../../../Source/ARMCM3_STM32/flash.c **** - 540:../../../Source/ARMCM3_STM32/flash.c **** /* check if the new data fits in the current block */ - 541:../../../Source/ARMCM3_STM32/flash.c **** if (block->base_addr != current_base_addr) - 542:../../../Source/ARMCM3_STM32/flash.c **** { - 543:../../../Source/ARMCM3_STM32/flash.c **** /* need to switch to a new block, so program the current one and init the next */ - 544:../../../Source/ARMCM3_STM32/flash.c **** block = FlashSwitchBlock(block, current_base_addr); - 545:../../../Source/ARMCM3_STM32/flash.c **** if (block == BLT_NULL) - 546:../../../Source/ARMCM3_STM32/flash.c **** { - 547:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 548:../../../Source/ARMCM3_STM32/flash.c **** } - 549:../../../Source/ARMCM3_STM32/flash.c **** } - 550:../../../Source/ARMCM3_STM32/flash.c **** - 551:../../../Source/ARMCM3_STM32/flash.c **** /* add the data to the current block, but check for block overflow */ - 552:../../../Source/ARMCM3_STM32/flash.c **** dst = &(block->data[address - block->base_addr]); - 553:../../../Source/ARMCM3_STM32/flash.c **** src = data; - 554:../../../Source/ARMCM3_STM32/flash.c **** do - 555:../../../Source/ARMCM3_STM32/flash.c **** { - 556:../../../Source/ARMCM3_STM32/flash.c **** /* keep the watchdog happy */ - 557:../../../Source/ARMCM3_STM32/flash.c **** CopService(); - 558:../../../Source/ARMCM3_STM32/flash.c **** /* buffer overflow? */ - 559:../../../Source/ARMCM3_STM32/flash.c **** if ((blt_addr)(dst-&(block->data[0])) >= FLASH_WRITE_BLOCK_SIZE) - 560:../../../Source/ARMCM3_STM32/flash.c **** { - 561:../../../Source/ARMCM3_STM32/flash.c **** /* need to switch to a new block, so program the current one and init the next */ - 562:../../../Source/ARMCM3_STM32/flash.c **** block = FlashSwitchBlock(block, current_base_addr+FLASH_WRITE_BLOCK_SIZE); - 563:../../../Source/ARMCM3_STM32/flash.c **** if (block == BLT_NULL) - 564:../../../Source/ARMCM3_STM32/flash.c **** { - 565:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 566:../../../Source/ARMCM3_STM32/flash.c **** } - 567:../../../Source/ARMCM3_STM32/flash.c **** /* reset destination pointer */ - 568:../../../Source/ARMCM3_STM32/flash.c **** dst = &(block->data[0]); - 569:../../../Source/ARMCM3_STM32/flash.c **** } - 570:../../../Source/ARMCM3_STM32/flash.c **** /* write the data to the buffer */ - 571:../../../Source/ARMCM3_STM32/flash.c **** *dst = *src; - 572:../../../Source/ARMCM3_STM32/flash.c **** /* update pointers */ - 573:../../../Source/ARMCM3_STM32/flash.c **** dst++; - 574:../../../Source/ARMCM3_STM32/flash.c **** src++; - 575:../../../Source/ARMCM3_STM32/flash.c **** /* decrement byte counter */ - 576:../../../Source/ARMCM3_STM32/flash.c **** len--; - 577:../../../Source/ARMCM3_STM32/flash.c **** } - 578:../../../Source/ARMCM3_STM32/flash.c **** while (len > 0); - 579:../../../Source/ARMCM3_STM32/flash.c **** /* still here so all is good */ - 580:../../../Source/ARMCM3_STM32/flash.c **** return BLT_TRUE; - 581:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashAddToBlock ***/ - 582:../../../Source/ARMCM3_STM32/flash.c **** - 583:../../../Source/ARMCM3_STM32/flash.c **** - 584:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 585:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Programs FLASH_WRITE_BLOCK_SIZE bytes to flash from the block->data - 586:../../../Source/ARMCM3_STM32/flash.c **** ** array. - 587:../../../Source/ARMCM3_STM32/flash.c **** ** \param block Pointer to flash block info structure to operate on. - 588:../../../Source/ARMCM3_STM32/flash.c **** ** \return BLT_TRUE if successful, BLT_FALSE otherwise. - 589:../../../Source/ARMCM3_STM32/flash.c **** ** - 590:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 591:../../../Source/ARMCM3_STM32/flash.c **** static blt_bool FlashWriteBlock(tFlashBlockInfo *block) - 592:../../../Source/ARMCM3_STM32/flash.c **** { - 593:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u sector_num; - 594:../../../Source/ARMCM3_STM32/flash.c **** blt_bool result = BLT_TRUE; - 595:../../../Source/ARMCM3_STM32/flash.c **** blt_addr prog_addr; - 596:../../../Source/ARMCM3_STM32/flash.c **** blt_int32u prog_data; - 597:../../../Source/ARMCM3_STM32/flash.c **** blt_int32u word_cnt; - 598:../../../Source/ARMCM3_STM32/flash.c **** - 599:../../../Source/ARMCM3_STM32/flash.c **** /* check that address is actually within flash */ - 600:../../../Source/ARMCM3_STM32/flash.c **** sector_num = FlashGetSector(block->base_addr); - 601:../../../Source/ARMCM3_STM32/flash.c **** if (sector_num == FLASH_INVALID_SECTOR) - 602:../../../Source/ARMCM3_STM32/flash.c **** { - 603:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 604:../../../Source/ARMCM3_STM32/flash.c **** } - 605:../../../Source/ARMCM3_STM32/flash.c **** /* unlock the flash array */ - 606:../../../Source/ARMCM3_STM32/flash.c **** FlashUnlock(); - 607:../../../Source/ARMCM3_STM32/flash.c **** /* check that the flash peripheral is not busy */ - 608:../../../Source/ARMCM3_STM32/flash.c **** if ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT) - 609:../../../Source/ARMCM3_STM32/flash.c **** { - 610:../../../Source/ARMCM3_STM32/flash.c **** /* lock the flash array again */ - 611:../../../Source/ARMCM3_STM32/flash.c **** FlashLock(); - 612:../../../Source/ARMCM3_STM32/flash.c **** /* could not perform erase operation */ - 613:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 614:../../../Source/ARMCM3_STM32/flash.c **** } - 615:../../../Source/ARMCM3_STM32/flash.c **** /* set the program bit to indicate that we are about to program data */ - 616:../../../Source/ARMCM3_STM32/flash.c **** FLASH->CR |= FLASH_PG_BIT; - 617:../../../Source/ARMCM3_STM32/flash.c **** /* program all words in the block one by one */ - 618:../../../Source/ARMCM3_STM32/flash.c **** for (word_cnt=0; word_cnt<(FLASH_WRITE_BLOCK_SIZE/sizeof(blt_int32u)); word_cnt++) - 619:../../../Source/ARMCM3_STM32/flash.c **** { - 620:../../../Source/ARMCM3_STM32/flash.c **** prog_addr = block->base_addr + (word_cnt * sizeof(blt_int32u)); - 621:../../../Source/ARMCM3_STM32/flash.c **** prog_data = *(volatile blt_int32u*)(&block->data[word_cnt * sizeof(blt_int32u)]); - 622:../../../Source/ARMCM3_STM32/flash.c **** /* program the first half word */ - 623:../../../Source/ARMCM3_STM32/flash.c **** *(volatile blt_int16u*)prog_addr = (blt_int16u)prog_data; - 624:../../../Source/ARMCM3_STM32/flash.c **** /* wait for the program operation to complete */ - 625:../../../Source/ARMCM3_STM32/flash.c **** while ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT) - 626:../../../Source/ARMCM3_STM32/flash.c **** { - 627:../../../Source/ARMCM3_STM32/flash.c **** /* keep the watchdog happy */ - 628:../../../Source/ARMCM3_STM32/flash.c **** CopService(); - 629:../../../Source/ARMCM3_STM32/flash.c **** } - 630:../../../Source/ARMCM3_STM32/flash.c **** /* program the second half word */ - 631:../../../Source/ARMCM3_STM32/flash.c **** *(volatile blt_int16u*)(prog_addr+2) = (blt_int16u)(prog_data >> 16); - 632:../../../Source/ARMCM3_STM32/flash.c **** /* wait for the program operation to complete */ - 633:../../../Source/ARMCM3_STM32/flash.c **** while ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT) - 634:../../../Source/ARMCM3_STM32/flash.c **** { - 635:../../../Source/ARMCM3_STM32/flash.c **** /* keep the watchdog happy */ - 636:../../../Source/ARMCM3_STM32/flash.c **** CopService(); - 637:../../../Source/ARMCM3_STM32/flash.c **** } - 638:../../../Source/ARMCM3_STM32/flash.c **** /* verify that the written data is actually there */ - 639:../../../Source/ARMCM3_STM32/flash.c **** if (*(volatile blt_int32u*)prog_addr != prog_data) - 640:../../../Source/ARMCM3_STM32/flash.c **** { - 641:../../../Source/ARMCM3_STM32/flash.c **** result = BLT_FALSE; - 642:../../../Source/ARMCM3_STM32/flash.c **** break; - 643:../../../Source/ARMCM3_STM32/flash.c **** } - 644:../../../Source/ARMCM3_STM32/flash.c **** } - 645:../../../Source/ARMCM3_STM32/flash.c **** /* reset the program bit to indicate that we are done programming data */ - 646:../../../Source/ARMCM3_STM32/flash.c **** FLASH->CR &= ~FLASH_PG_BIT; - 647:../../../Source/ARMCM3_STM32/flash.c **** /* lock the flash array */ - 648:../../../Source/ARMCM3_STM32/flash.c **** FlashLock(); - 649:../../../Source/ARMCM3_STM32/flash.c **** /* still here so all is okay */ - 650:../../../Source/ARMCM3_STM32/flash.c **** return result; - 651:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashWriteBlock ***/ - 652:../../../Source/ARMCM3_STM32/flash.c **** - 653:../../../Source/ARMCM3_STM32/flash.c **** - 654:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 655:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Erases the flash sectors from first_sector up until last_sector. - 656:../../../Source/ARMCM3_STM32/flash.c **** ** \param first_sector First flash sector number. - 657:../../../Source/ARMCM3_STM32/flash.c **** ** \param last_sector Last flash sector number. - 658:../../../Source/ARMCM3_STM32/flash.c **** ** \return BLT_TRUE if successful, BLT_FALSE otherwise. - 659:../../../Source/ARMCM3_STM32/flash.c **** ** - 660:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 661:../../../Source/ARMCM3_STM32/flash.c **** static blt_bool FlashEraseSectors(blt_int8u first_sector, blt_int8u last_sector) - 662:../../../Source/ARMCM3_STM32/flash.c **** { - 663:../../../Source/ARMCM3_STM32/flash.c **** blt_int16u nr_of_blocks; - 664:../../../Source/ARMCM3_STM32/flash.c **** blt_int16u block_cnt; - 665:../../../Source/ARMCM3_STM32/flash.c **** blt_addr start_addr; - 666:../../../Source/ARMCM3_STM32/flash.c **** blt_addr end_addr; - 667:../../../Source/ARMCM3_STM32/flash.c **** - 668:../../../Source/ARMCM3_STM32/flash.c **** /* validate the sector numbers */ - 669:../../../Source/ARMCM3_STM32/flash.c **** if (first_sector > last_sector) - 670:../../../Source/ARMCM3_STM32/flash.c **** { - 671:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 672:../../../Source/ARMCM3_STM32/flash.c **** } - 673:../../../Source/ARMCM3_STM32/flash.c **** if ( (first_sector < flashLayout[0].sector_num) || \ - 674:../../../Source/ARMCM3_STM32/flash.c **** (last_sector > flashLayout[FLASH_TOTAL_SECTORS-1].sector_num) ) - 675:../../../Source/ARMCM3_STM32/flash.c **** { - 676:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 677:../../../Source/ARMCM3_STM32/flash.c **** } - 678:../../../Source/ARMCM3_STM32/flash.c **** /* unlock the flash array */ - 679:../../../Source/ARMCM3_STM32/flash.c **** FlashUnlock(); - 680:../../../Source/ARMCM3_STM32/flash.c **** /* check that the flash peripheral is not busy */ - 681:../../../Source/ARMCM3_STM32/flash.c **** if ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT) - 682:../../../Source/ARMCM3_STM32/flash.c **** { - 683:../../../Source/ARMCM3_STM32/flash.c **** /* lock the flash array again */ - 684:../../../Source/ARMCM3_STM32/flash.c **** FlashLock(); - 685:../../../Source/ARMCM3_STM32/flash.c **** /* could not perform erase operation */ - 686:../../../Source/ARMCM3_STM32/flash.c **** return BLT_FALSE; - 687:../../../Source/ARMCM3_STM32/flash.c **** } - 688:../../../Source/ARMCM3_STM32/flash.c **** /* set the page erase bit to indicate that we are about to erase a block */ - 689:../../../Source/ARMCM3_STM32/flash.c **** FLASH->CR |= FLASH_PER_BIT; - 690:../../../Source/ARMCM3_STM32/flash.c **** - 691:../../../Source/ARMCM3_STM32/flash.c **** /* determine how many blocks need to be erased */ - 692:../../../Source/ARMCM3_STM32/flash.c **** start_addr = FlashGetSectorBaseAddr(first_sector); - 693:../../../Source/ARMCM3_STM32/flash.c **** end_addr = FlashGetSectorBaseAddr(last_sector) + FlashGetSectorSize(last_sector) - 1; - 694:../../../Source/ARMCM3_STM32/flash.c **** nr_of_blocks = (end_addr - start_addr + 1) / FLASH_ERASE_BLOCK_SIZE; - 695:../../../Source/ARMCM3_STM32/flash.c **** - 696:../../../Source/ARMCM3_STM32/flash.c **** /* erase all blocks one by one */ - 697:../../../Source/ARMCM3_STM32/flash.c **** for (block_cnt=0; block_cntAR = start_addr + (block_cnt * FLASH_ERASE_BLOCK_SIZE); - 701:../../../Source/ARMCM3_STM32/flash.c **** /* start the block erase operation */ - 702:../../../Source/ARMCM3_STM32/flash.c **** FLASH->CR |= FLASH_STRT_BIT; - 703:../../../Source/ARMCM3_STM32/flash.c **** /* wait for the erase operation to complete */ - 704:../../../Source/ARMCM3_STM32/flash.c **** while ((FLASH->SR & FLASH_BSY_BIT) == FLASH_BSY_BIT) - 705:../../../Source/ARMCM3_STM32/flash.c **** { - 706:../../../Source/ARMCM3_STM32/flash.c **** /* keep the watchdog happy */ - 707:../../../Source/ARMCM3_STM32/flash.c **** CopService(); - 708:../../../Source/ARMCM3_STM32/flash.c **** } - 709:../../../Source/ARMCM3_STM32/flash.c **** } - 710:../../../Source/ARMCM3_STM32/flash.c **** /* reset the page erase bit because we're all done erasing */ - 711:../../../Source/ARMCM3_STM32/flash.c **** FLASH->CR &= ~FLASH_PER_BIT; - 712:../../../Source/ARMCM3_STM32/flash.c **** /* lock the flash array */ - 713:../../../Source/ARMCM3_STM32/flash.c **** FlashLock(); - 714:../../../Source/ARMCM3_STM32/flash.c **** /* still here so all went okay */ - 715:../../../Source/ARMCM3_STM32/flash.c **** return BLT_TRUE; - 716:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashEraseSectors ***/ - 717:../../../Source/ARMCM3_STM32/flash.c **** - 718:../../../Source/ARMCM3_STM32/flash.c **** - 719:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 720:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Unlocks the flash array so that erase and program operations can be - 721:../../../Source/ARMCM3_STM32/flash.c **** ** performed. - 722:../../../Source/ARMCM3_STM32/flash.c **** ** \return none. - 723:../../../Source/ARMCM3_STM32/flash.c **** ** - 724:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 725:../../../Source/ARMCM3_STM32/flash.c **** static void FlashUnlock(void) - 726:../../../Source/ARMCM3_STM32/flash.c **** { - 727:../../../Source/ARMCM3_STM32/flash.c **** /* authorize the FPEC to access bank 1 */ - 728:../../../Source/ARMCM3_STM32/flash.c **** FLASH->KEYR = FLASH_KEY1; - 729:../../../Source/ARMCM3_STM32/flash.c **** FLASH->KEYR = FLASH_KEY2; - 730:../../../Source/ARMCM3_STM32/flash.c **** /* clear all possibly pending status flags */ - 731:../../../Source/ARMCM3_STM32/flash.c **** FLASH->SR = (FLASH_EOP_BIT | FLASH_PGERR_BIT | FLASH_WRPRTERR_BIT); - 732:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashUnlock ***/ - 733:../../../Source/ARMCM3_STM32/flash.c **** - 734:../../../Source/ARMCM3_STM32/flash.c **** - 735:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 736:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Locks the flash array so that erase and program operations can no - 737:../../../Source/ARMCM3_STM32/flash.c **** ** longer be performed. - 738:../../../Source/ARMCM3_STM32/flash.c **** ** \return none. - 739:../../../Source/ARMCM3_STM32/flash.c **** ** - 740:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 741:../../../Source/ARMCM3_STM32/flash.c **** static void FlashLock(void) - 742:../../../Source/ARMCM3_STM32/flash.c **** { - 26 .loc 1 742 0 - 27 .cfi_startproc - 28 @ args = 0, pretend = 0, frame = 0 - 29 @ frame_needed = 0, uses_anonymous_args = 0 - 30 @ link register save eliminated. - 743:../../../Source/ARMCM3_STM32/flash.c **** /* set the lock bit to lock the FPEC */ - 744:../../../Source/ARMCM3_STM32/flash.c **** FLASH->CR |= FLASH_LOCK_BIT; - 31 .loc 1 744 0 - 32 0000 024A ldr r2, .L2 - 33 0002 1369 ldr r3, [r2, #16] - 34 0004 43F08003 orr r3, r3, #128 - 35 0008 1361 str r3, [r2, #16] - 36 000a 7047 bx lr - 37 .L3: - 38 .align 2 - 39 .L2: - 40 000c 00200240 .word 1073881088 - 41 .cfi_endproc - 42 .LFE13: - 44 .section .text.FlashGetSector,"ax",%progbits - 45 .align 2 - 46 .thumb - 47 .thumb_func - 49 FlashGetSector: - 50 .LFB14: - 745:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashLock ***/ - 746:../../../Source/ARMCM3_STM32/flash.c **** - 747:../../../Source/ARMCM3_STM32/flash.c **** - 748:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 749:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Determines the flash sector the address is in. - 750:../../../Source/ARMCM3_STM32/flash.c **** ** \param address Address in the flash sector. - 751:../../../Source/ARMCM3_STM32/flash.c **** ** \return Flash sector number or FLASH_INVALID_SECTOR. - 752:../../../Source/ARMCM3_STM32/flash.c **** ** - 753:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 754:../../../Source/ARMCM3_STM32/flash.c **** static blt_int8u FlashGetSector(blt_addr address) - 755:../../../Source/ARMCM3_STM32/flash.c **** { - 51 .loc 1 755 0 - 52 .cfi_startproc - 53 @ args = 0, pretend = 0, frame = 0 - 54 @ frame_needed = 0, uses_anonymous_args = 0 - 55 .LVL0: - 56 0000 F8B5 push {r3, r4, r5, r6, r7, lr} - 57 .cfi_def_cfa_offset 24 - 58 .cfi_offset 3, -24 - 59 .cfi_offset 4, -20 - 60 .cfi_offset 5, -16 - 61 .cfi_offset 6, -12 - 62 .cfi_offset 7, -8 - 63 .cfi_offset 14, -4 - 64 0002 0646 mov r6, r0 - 65 .LVL1: - 66 0004 0C4C ldr r4, .L10 - 67 0006 04F19C07 add r7, r4, #156 - 68 .loc 1 755 0 - 69 000a 0025 movs r5, #0 - 70 .LVL2: - 71 .L7: - 756:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u sectorIdx; - 757:../../../Source/ARMCM3_STM32/flash.c **** - 758:../../../Source/ARMCM3_STM32/flash.c **** /* search through the sectors to find the right one */ - 759:../../../Source/ARMCM3_STM32/flash.c **** for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++) - 760:../../../Source/ARMCM3_STM32/flash.c **** { - 761:../../../Source/ARMCM3_STM32/flash.c **** /* keep the watchdog happy */ - 762:../../../Source/ARMCM3_STM32/flash.c **** CopService(); - 72 .loc 1 762 0 - 73 000c FFF7FEFF bl CopService - 74 .LVL3: - 763:../../../Source/ARMCM3_STM32/flash.c **** /* is the address in this sector? */ - 764:../../../Source/ARMCM3_STM32/flash.c **** if ( (address >= flashLayout[sectorIdx].sector_start) && \ - 75 .loc 1 764 0 - 76 0010 2368 ldr r3, [r4] - 77 0012 B342 cmp r3, r6 - 78 0014 0AD8 bhi .L5 - 765:../../../Source/ARMCM3_STM32/flash.c **** (address < (flashLayout[sectorIdx].sector_start + \ - 79 .loc 1 765 0 discriminator 1 - 80 0016 6268 ldr r2, [r4, #4] - 81 0018 1344 add r3, r3, r2 - 764:../../../Source/ARMCM3_STM32/flash.c **** (address < (flashLayout[sectorIdx].sector_start + \ - 82 .loc 1 764 0 discriminator 1 - 83 001a 9E42 cmp r6, r3 - 84 001c 06D2 bcs .L5 - 766:../../../Source/ARMCM3_STM32/flash.c **** flashLayout[sectorIdx].sector_size)) ) - 767:../../../Source/ARMCM3_STM32/flash.c **** { - 768:../../../Source/ARMCM3_STM32/flash.c **** /* return the sector number */ - 769:../../../Source/ARMCM3_STM32/flash.c **** return flashLayout[sectorIdx].sector_num; - 85 .loc 1 769 0 - 86 001e 05EB4501 add r1, r5, r5, lsl #1 - 87 0022 054B ldr r3, .L10 - 88 0024 03EB8101 add r1, r3, r1, lsl #2 - 89 0028 087A ldrb r0, [r1, #8] @ zero_extendqisi2 - 90 002a F8BD pop {r3, r4, r5, r6, r7, pc} - 91 .LVL4: - 92 .L5: - 93 002c 0135 adds r5, r5, #1 - 94 .LVL5: - 95 002e 0C34 adds r4, r4, #12 - 759:../../../Source/ARMCM3_STM32/flash.c **** { - 96 .loc 1 759 0 discriminator 2 - 97 0030 BC42 cmp r4, r7 - 98 0032 EBD1 bne .L7 - 770:../../../Source/ARMCM3_STM32/flash.c **** } - 771:../../../Source/ARMCM3_STM32/flash.c **** } - 772:../../../Source/ARMCM3_STM32/flash.c **** /* still here so no valid sector found */ - 773:../../../Source/ARMCM3_STM32/flash.c **** return FLASH_INVALID_SECTOR; - 99 .loc 1 773 0 - 100 0034 FF20 movs r0, #255 - 774:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashGetSector ***/ - 101 .loc 1 774 0 - 102 0036 F8BD pop {r3, r4, r5, r6, r7, pc} - 103 .LVL6: - 104 .L11: - 105 .align 2 - 106 .L10: - 107 0038 00000000 .word .LANCHOR0 - 108 .cfi_endproc - 109 .LFE14: - 111 .section .text.FlashWriteBlock,"ax",%progbits - 112 .align 2 - 113 .thumb - 114 .thumb_func - 116 FlashWriteBlock: - 117 .LFB10: - 592:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u sector_num; - 118 .loc 1 592 0 - 119 .cfi_startproc - 120 @ args = 0, pretend = 0, frame = 0 - 121 @ frame_needed = 0, uses_anonymous_args = 0 - 122 .LVL7: - 123 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} - 124 .cfi_def_cfa_offset 24 - 125 .cfi_offset 4, -24 - 126 .cfi_offset 5, -20 - 127 .cfi_offset 6, -16 - 128 .cfi_offset 7, -12 - 129 .cfi_offset 8, -8 - 130 .cfi_offset 14, -4 - 131 0004 0746 mov r7, r0 - 132 .LVL8: - 600:../../../Source/ARMCM3_STM32/flash.c **** if (sector_num == FLASH_INVALID_SECTOR) - 133 .loc 1 600 0 - 134 0006 0068 ldr r0, [r0] - 135 .LVL9: - 136 0008 FFF7FEFF bl FlashGetSector - 137 .LVL10: - 601:../../../Source/ARMCM3_STM32/flash.c **** { - 138 .loc 1 601 0 - 139 000c FF28 cmp r0, #255 - 140 000e 49D0 beq .L21 - 141 .LBB4: - 142 .LBB5: - 728:../../../Source/ARMCM3_STM32/flash.c **** FLASH->KEYR = FLASH_KEY2; - 143 .loc 1 728 0 - 144 0010 264B ldr r3, .L29 - 145 0012 274A ldr r2, .L29+4 - 146 0014 5A60 str r2, [r3, #4] - 729:../../../Source/ARMCM3_STM32/flash.c **** /* clear all possibly pending status flags */ - 147 .loc 1 729 0 - 148 0016 02F18832 add r2, r2, #-2004318072 - 149 001a 5A60 str r2, [r3, #4] - 731:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashUnlock ***/ - 150 .loc 1 731 0 - 151 001c 3422 movs r2, #52 - 152 001e DA60 str r2, [r3, #12] - 153 .LBE5: - 154 .LBE4: - 608:../../../Source/ARMCM3_STM32/flash.c **** { - 155 .loc 1 608 0 - 156 0020 DB68 ldr r3, [r3, #12] - 157 0022 13F00103 ands r3, r3, #1 - 158 0026 04D0 beq .L14 - 611:../../../Source/ARMCM3_STM32/flash.c **** /* could not perform erase operation */ - 159 .loc 1 611 0 - 160 0028 FFF7FEFF bl FlashLock - 161 .LVL11: - 613:../../../Source/ARMCM3_STM32/flash.c **** } - 162 .loc 1 613 0 - 163 002c 0020 movs r0, #0 - 164 002e BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 165 .LVL12: - 166 .L14: - 616:../../../Source/ARMCM3_STM32/flash.c **** /* program all words in the block one by one */ - 167 .loc 1 616 0 - 168 0032 1E49 ldr r1, .L29 - 169 0034 0A69 ldr r2, [r1, #16] - 170 0036 42F00102 orr r2, r2, #1 - 171 003a 0A61 str r2, [r1, #16] - 172 .LVL13: - 625:../../../Source/ARMCM3_STM32/flash.c **** { - 173 .loc 1 625 0 - 174 003c 0C46 mov r4, r1 - 175 .LVL14: - 176 .L20: - 620:../../../Source/ARMCM3_STM32/flash.c **** prog_data = *(volatile blt_int32u*)(&block->data[word_cnt * sizeof(blt_int32u)]); - 177 .loc 1 620 0 - 178 003e 3A68 ldr r2, [r7] - 179 0040 03EB0208 add r8, r3, r2 - 180 .LVL15: - 181 0044 1E1D adds r6, r3, #4 - 621:../../../Source/ARMCM3_STM32/flash.c **** /* program the first half word */ - 182 .loc 1 621 0 - 183 0046 BD59 ldr r5, [r7, r6] - 184 .LVL16: - 623:../../../Source/ARMCM3_STM32/flash.c **** /* wait for the program operation to complete */ - 185 .loc 1 623 0 - 186 0048 A9B2 uxth r1, r5 - 187 004a 9952 strh r1, [r3, r2] @ movhi - 625:../../../Source/ARMCM3_STM32/flash.c **** { - 188 .loc 1 625 0 - 189 004c E368 ldr r3, [r4, #12] - 190 004e 13F0010F tst r3, #1 - 191 0052 05D0 beq .L15 - 192 .L24: - 628:../../../Source/ARMCM3_STM32/flash.c **** } - 193 .loc 1 628 0 - 194 0054 FFF7FEFF bl CopService - 195 .LVL17: - 625:../../../Source/ARMCM3_STM32/flash.c **** { - 196 .loc 1 625 0 - 197 0058 E368 ldr r3, [r4, #12] - 198 005a 13F0010F tst r3, #1 - 199 005e F9D1 bne .L24 - 200 .L15: - 631:../../../Source/ARMCM3_STM32/flash.c **** /* wait for the program operation to complete */ - 201 .loc 1 631 0 - 202 0060 2B0C lsrs r3, r5, #16 - 203 0062 A8F80230 strh r3, [r8, #2] @ movhi - 633:../../../Source/ARMCM3_STM32/flash.c **** { - 204 .loc 1 633 0 - 205 0066 E368 ldr r3, [r4, #12] - 206 0068 13F0010F tst r3, #1 - 207 006c 05D0 beq .L17 - 208 .L23: - 636:../../../Source/ARMCM3_STM32/flash.c **** } - 209 .loc 1 636 0 - 210 006e FFF7FEFF bl CopService - 211 .LVL18: - 633:../../../Source/ARMCM3_STM32/flash.c **** { - 212 .loc 1 633 0 - 213 0072 E368 ldr r3, [r4, #12] - 214 0074 13F0010F tst r3, #1 - 215 0078 F9D1 bne .L23 - 216 .L17: - 639:../../../Source/ARMCM3_STM32/flash.c **** { - 217 .loc 1 639 0 - 218 007a D8F80030 ldr r3, [r8] - 219 007e AB42 cmp r3, r5 - 220 0080 05D1 bne .L22 - 221 0082 3346 mov r3, r6 - 618:../../../Source/ARMCM3_STM32/flash.c **** { - 222 .loc 1 618 0 discriminator 2 - 223 0084 B6F5007F cmp r6, #512 - 224 0088 D9D1 bne .L20 - 594:../../../Source/ARMCM3_STM32/flash.c **** blt_addr prog_addr; - 225 .loc 1 594 0 - 226 008a 0124 movs r4, #1 - 227 008c 00E0 b .L19 - 228 .L22: - 641:../../../Source/ARMCM3_STM32/flash.c **** break; - 229 .loc 1 641 0 - 230 008e 0024 movs r4, #0 - 231 .L19: - 232 .LVL19: - 646:../../../Source/ARMCM3_STM32/flash.c **** /* lock the flash array */ - 233 .loc 1 646 0 - 234 0090 064A ldr r2, .L29 - 235 0092 1369 ldr r3, [r2, #16] - 236 0094 23F00103 bic r3, r3, #1 - 237 0098 1361 str r3, [r2, #16] - 648:../../../Source/ARMCM3_STM32/flash.c **** /* still here so all is okay */ - 238 .loc 1 648 0 - 239 009a FFF7FEFF bl FlashLock - 240 .LVL20: - 650:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashWriteBlock ***/ - 241 .loc 1 650 0 - 242 009e 2046 mov r0, r4 - 243 00a0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 244 .LVL21: - 245 .L21: - 603:../../../Source/ARMCM3_STM32/flash.c **** } - 246 .loc 1 603 0 - 247 00a4 0020 movs r0, #0 - 248 .LVL22: - 651:../../../Source/ARMCM3_STM32/flash.c **** - 249 .loc 1 651 0 - 250 00a6 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 251 .LVL23: - 252 .L30: - 253 00aa 00BF .align 2 - 254 .L29: - 255 00ac 00200240 .word 1073881088 - 256 00b0 23016745 .word 1164378403 - 257 .cfi_endproc - 258 .LFE10: - 260 .section .text.FlashSwitchBlock,"ax",%progbits - 261 .align 2 - 262 .thumb - 263 .thumb_func - 265 FlashSwitchBlock: - 266 .LFB8: - 469:../../../Source/ARMCM3_STM32/flash.c **** /* check if a switch needs to be made away from the boot block. in this case the boot - 267 .loc 1 469 0 - 268 .cfi_startproc - 269 @ args = 0, pretend = 0, frame = 0 - 270 @ frame_needed = 0, uses_anonymous_args = 0 - 271 .LVL24: - 272 0000 38B5 push {r3, r4, r5, lr} - 273 .cfi_def_cfa_offset 16 - 274 .cfi_offset 3, -16 - 275 .cfi_offset 4, -12 - 276 .cfi_offset 5, -8 - 277 .cfi_offset 14, -4 - 278 0002 0446 mov r4, r0 - 279 0004 0D46 mov r5, r1 - 474:../../../Source/ARMCM3_STM32/flash.c **** { - 280 .loc 1 474 0 - 281 0006 114B ldr r3, .L42 - 282 0008 9842 cmp r0, r3 - 283 000a 06D0 beq .L36 - 482:../../../Source/ARMCM3_STM32/flash.c **** { - 284 .loc 1 482 0 - 285 000c 104B ldr r3, .L42+4 - 286 000e 9942 cmp r1, r3 - 287 0010 08D0 beq .L37 - 491:../../../Source/ARMCM3_STM32/flash.c **** { - 288 .loc 1 491 0 - 289 0012 FFF7FEFF bl FlashWriteBlock - 290 .LVL25: - 291 0016 08B9 cbnz r0, .L32 - 292 0018 11E0 b .L38 - 293 .LVL26: - 294 .L36: - 477:../../../Source/ARMCM3_STM32/flash.c **** } - 295 .loc 1 477 0 - 296 001a 0E4C ldr r4, .L42+8 - 297 .LVL27: - 298 .L32: - 299 .LBB8: - 300 .LBB9: - 442:../../../Source/ARMCM3_STM32/flash.c **** { - 301 .loc 1 442 0 - 302 001c C5F30803 ubfx r3, r5, #0, #9 - 303 0020 7BB9 cbnz r3, .L39 - 304 0022 00E0 b .L33 - 305 .LVL28: - 306 .L37: - 307 .LBE9: - 308 .LBE8: - 485:../../../Source/ARMCM3_STM32/flash.c **** base_addr = flashLayout[0].sector_start; - 309 .loc 1 485 0 - 310 0024 094C ldr r4, .L42 - 311 .LVL29: - 312 .L33: - 313 .LBB11: - 314 .LBB10: - 447:../../../Source/ARMCM3_STM32/flash.c **** { - 315 .loc 1 447 0 - 316 0026 2368 ldr r3, [r4] - 317 0028 9D42 cmp r5, r3 - 318 002a 0CD0 beq .L35 - 453:../../../Source/ARMCM3_STM32/flash.c **** CpuMemCopy((blt_addr)block->data, address, FLASH_WRITE_BLOCK_SIZE); - 319 .loc 1 453 0 - 320 002c 2046 mov r0, r4 - 321 002e 40F8045B str r5, [r0], #4 - 454:../../../Source/ARMCM3_STM32/flash.c **** return BLT_TRUE; - 322 .loc 1 454 0 - 323 0032 2946 mov r1, r5 - 324 0034 4FF40072 mov r2, #512 - 325 0038 FFF7FEFF bl CpuMemCopy - 326 .LVL30: - 327 003c 03E0 b .L35 - 328 .LVL31: - 329 .L38: - 330 .LBE10: - 331 .LBE11: - 493:../../../Source/ARMCM3_STM32/flash.c **** } - 332 .loc 1 493 0 - 333 003e 0020 movs r0, #0 - 334 0040 38BD pop {r3, r4, r5, pc} - 335 .LVL32: - 336 .L39: - 500:../../../Source/ARMCM3_STM32/flash.c **** } - 337 .loc 1 500 0 - 338 0042 0020 movs r0, #0 - 339 0044 38BD pop {r3, r4, r5, pc} - 340 .LVL33: - 341 .L35: - 493:../../../Source/ARMCM3_STM32/flash.c **** } - 342 .loc 1 493 0 - 343 0046 2046 mov r0, r4 - 505:../../../Source/ARMCM3_STM32/flash.c **** - 344 .loc 1 505 0 - 345 0048 38BD pop {r3, r4, r5, pc} - 346 .LVL34: - 347 .L43: - 348 004a 00BF .align 2 - 349 .L42: - 350 004c 00000000 .word .LANCHOR2 - 351 0050 00600008 .word 134242304 - 352 0054 00000000 .word .LANCHOR1 - 353 .cfi_endproc - 354 .LFE8: - 356 .section .text.FlashAddToBlock,"ax",%progbits - 357 .align 2 - 358 .thumb - 359 .thumb_func - 361 FlashAddToBlock: - 362 .LFB9: - 522:../../../Source/ARMCM3_STM32/flash.c **** blt_addr current_base_addr; - 363 .loc 1 522 0 - 364 .cfi_startproc - 365 @ args = 0, pretend = 0, frame = 0 - 366 @ frame_needed = 0, uses_anonymous_args = 0 - 367 .LVL35: - 368 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} - 369 .cfi_def_cfa_offset 24 - 370 .cfi_offset 4, -24 - 371 .cfi_offset 5, -20 - 372 .cfi_offset 6, -16 - 373 .cfi_offset 7, -12 - 374 .cfi_offset 8, -8 - 375 .cfi_offset 14, -4 - 376 0004 0646 mov r6, r0 - 377 0006 0C46 mov r4, r1 - 378 0008 1746 mov r7, r2 - 379 000a 1D46 mov r5, r3 - 528:../../../Source/ARMCM3_STM32/flash.c **** - 380 .loc 1 528 0 - 381 000c 21F4FF78 bic r8, r1, #510 - 382 0010 28F00108 bic r8, r8, #1 - 383 .LVL36: - 531:../../../Source/ARMCM3_STM32/flash.c **** { - 384 .loc 1 531 0 - 385 0014 0368 ldr r3, [r0] - 386 .LVL37: - 387 0016 B3F1FF3F cmp r3, #-1 - 388 001a 06D1 bne .L45 - 389 .LVL38: - 390 .LBB14: - 391 .LBB15: - 453:../../../Source/ARMCM3_STM32/flash.c **** CpuMemCopy((blt_addr)block->data, address, FLASH_WRITE_BLOCK_SIZE); - 392 .loc 1 453 0 - 393 001c 40F8048B str r8, [r0], #4 - 394 .LVL39: - 454:../../../Source/ARMCM3_STM32/flash.c **** return BLT_TRUE; - 395 .loc 1 454 0 - 396 0020 4146 mov r1, r8 - 397 .LVL40: - 398 0022 4FF40072 mov r2, #512 - 399 .LVL41: - 400 0026 FFF7FEFF bl CpuMemCopy - 401 .LVL42: - 402 .L45: - 403 .LBE15: - 404 .LBE14: - 541:../../../Source/ARMCM3_STM32/flash.c **** { - 405 .loc 1 541 0 - 406 002a 3368 ldr r3, [r6] - 407 002c 4345 cmp r3, r8 - 408 002e 05D0 beq .L46 - 544:../../../Source/ARMCM3_STM32/flash.c **** if (block == BLT_NULL) - 409 .loc 1 544 0 - 410 0030 3046 mov r0, r6 - 411 0032 4146 mov r1, r8 - 412 0034 FFF7FEFF bl FlashSwitchBlock - 413 .LVL43: - 545:../../../Source/ARMCM3_STM32/flash.c **** { - 414 .loc 1 545 0 - 415 0038 0646 mov r6, r0 - 416 003a E0B1 cbz r0, .L50 - 417 .LVL44: - 418 .L46: - 552:../../../Source/ARMCM3_STM32/flash.c **** src = data; - 419 .loc 1 552 0 - 420 003c 3368 ldr r3, [r6] - 421 003e E41A subs r4, r4, r3 - 422 .LVL45: - 423 0040 3444 add r4, r4, r6 - 424 0042 0434 adds r4, r4, #4 - 425 .LVL46: - 562:../../../Source/ARMCM3_STM32/flash.c **** if (block == BLT_NULL) - 426 .loc 1 562 0 - 427 0044 08F50078 add r8, r8, #512 - 428 .LVL47: - 429 .L49: - 557:../../../Source/ARMCM3_STM32/flash.c **** /* buffer overflow? */ - 430 .loc 1 557 0 - 431 0048 FFF7FEFF bl CopService - 432 .LVL48: - 559:../../../Source/ARMCM3_STM32/flash.c **** { - 433 .loc 1 559 0 - 434 004c 331D adds r3, r6, #4 - 435 004e E31A subs r3, r4, r3 - 436 0050 B3F5007F cmp r3, #512 - 437 0054 06D3 bcc .L48 - 562:../../../Source/ARMCM3_STM32/flash.c **** if (block == BLT_NULL) - 438 .loc 1 562 0 - 439 0056 3046 mov r0, r6 - 440 0058 4146 mov r1, r8 - 441 005a FFF7FEFF bl FlashSwitchBlock - 442 .LVL49: - 563:../../../Source/ARMCM3_STM32/flash.c **** { - 443 .loc 1 563 0 - 444 005e 0646 mov r6, r0 - 445 0060 60B1 cbz r0, .L51 - 568:../../../Source/ARMCM3_STM32/flash.c **** } - 446 .loc 1 568 0 - 447 0062 041D adds r4, r0, #4 - 448 .LVL50: - 449 .L48: - 571:../../../Source/ARMCM3_STM32/flash.c **** /* update pointers */ - 450 .loc 1 571 0 - 451 0064 17F8013B ldrb r3, [r7], #1 @ zero_extendqisi2 - 452 .LVL51: - 453 0068 04F8013B strb r3, [r4], #1 - 454 .LVL52: - 578:../../../Source/ARMCM3_STM32/flash.c **** /* still here so all is good */ - 455 .loc 1 578 0 - 456 006c 013D subs r5, r5, #1 - 457 .LVL53: - 458 006e EBD1 bne .L49 - 580:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashAddToBlock ***/ - 459 .loc 1 580 0 - 460 0070 0120 movs r0, #1 - 461 0072 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 462 .LVL54: - 463 .L50: - 547:../../../Source/ARMCM3_STM32/flash.c **** } - 464 .loc 1 547 0 - 465 0076 0020 movs r0, #0 - 466 .LVL55: - 467 0078 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 468 .LVL56: - 469 .L51: - 565:../../../Source/ARMCM3_STM32/flash.c **** } - 470 .loc 1 565 0 - 471 007c 0020 movs r0, #0 - 472 .LVL57: - 581:../../../Source/ARMCM3_STM32/flash.c **** - 473 .loc 1 581 0 - 474 007e BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 475 .cfi_endproc - 476 .LFE9: - 478 0082 00BF .section .text.FlashInit,"ax",%progbits - 479 .align 2 - 480 .global FlashInit - 481 .thumb - 482 .thumb_func - 484 FlashInit: - 485 .LFB0: - 231:../../../Source/ARMCM3_STM32/flash.c **** /* init the flash block info structs by setting the address to an invalid address */ - 486 .loc 1 231 0 - 487 .cfi_startproc - 488 @ args = 0, pretend = 0, frame = 0 - 489 @ frame_needed = 0, uses_anonymous_args = 0 - 490 @ link register save eliminated. - 233:../../../Source/ARMCM3_STM32/flash.c **** bootBlockInfo.base_addr = FLASH_INVALID_ADDRESS; - 491 .loc 1 233 0 - 492 0000 4FF0FF33 mov r3, #-1 - 493 0004 024A ldr r2, .L55 - 494 0006 1360 str r3, [r2] - 234:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashInit ***/ - 495 .loc 1 234 0 - 496 0008 024A ldr r2, .L55+4 - 497 000a 1360 str r3, [r2] - 498 000c 7047 bx lr - 499 .L56: - 500 000e 00BF .align 2 - 501 .L55: - 502 0010 00000000 .word .LANCHOR1 - 503 0014 00000000 .word .LANCHOR2 - 504 .cfi_endproc - 505 .LFE0: - 507 .section .text.FlashWrite,"ax",%progbits - 508 .align 2 - 509 .global FlashWrite - 510 .thumb - 511 .thumb_func - 513 FlashWrite: - 514 .LFB1: - 249:../../../Source/ARMCM3_STM32/flash.c **** blt_addr base_addr; - 515 .loc 1 249 0 - 516 .cfi_startproc - 517 @ args = 0, pretend = 0, frame = 0 - 518 @ frame_needed = 0, uses_anonymous_args = 0 - 519 .LVL58: - 520 0000 70B5 push {r4, r5, r6, lr} - 521 .cfi_def_cfa_offset 16 - 522 .cfi_offset 4, -16 - 523 .cfi_offset 5, -12 - 524 .cfi_offset 6, -8 - 525 .cfi_offset 14, -4 - 526 0002 0446 mov r4, r0 - 527 0004 0D46 mov r5, r1 - 528 0006 1646 mov r6, r2 - 253:../../../Source/ARMCM3_STM32/flash.c **** (FlashGetSector(addr+len-1) == FLASH_INVALID_SECTOR) ) - 529 .loc 1 253 0 - 530 0008 FFF7FEFF bl FlashGetSector - 531 .LVL59: - 532 000c FF28 cmp r0, #255 - 533 000e 14D0 beq .L60 - 534 0010 681E subs r0, r5, #1 - 254:../../../Source/ARMCM3_STM32/flash.c **** { - 535 .loc 1 254 0 discriminator 1 - 536 0012 2044 add r0, r0, r4 - 537 0014 FFF7FEFF bl FlashGetSector - 538 .LVL60: - 253:../../../Source/ARMCM3_STM32/flash.c **** (FlashGetSector(addr+len-1) == FLASH_INVALID_SECTOR) ) - 539 .loc 1 253 0 discriminator 1 - 540 0018 FF28 cmp r0, #255 - 541 001a 10D0 beq .L61 - 542 .LVL61: - 260:../../../Source/ARMCM3_STM32/flash.c **** if (base_addr == flashLayout[0].sector_start) - 543 .loc 1 260 0 - 544 001c 24F4FF73 bic r3, r4, #510 - 545 0020 23F00103 bic r3, r3, #1 - 261:../../../Source/ARMCM3_STM32/flash.c **** { - 546 .loc 1 261 0 - 547 0024 074A ldr r2, .L63 - 548 0026 9342 cmp r3, r2 - 264:../../../Source/ARMCM3_STM32/flash.c **** } - 549 .loc 1 264 0 - 550 0028 0CBF ite eq - 551 002a 0748 ldreq r0, .L63+4 - 267:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashWrite ***/ - 552 .loc 1 267 0 - 553 002c 0748 ldrne r0, .L63+8 - 554 002e 2146 mov r1, r4 - 555 0030 3246 mov r2, r6 - 556 0032 2B46 mov r3, r5 - 557 0034 FFF7FEFF bl FlashAddToBlock - 558 .LVL62: - 559 0038 70BD pop {r4, r5, r6, pc} - 560 .LVL63: - 561 .L60: - 256:../../../Source/ARMCM3_STM32/flash.c **** } - 562 .loc 1 256 0 - 563 003a 0020 movs r0, #0 - 564 003c 70BD pop {r4, r5, r6, pc} - 565 .LVL64: - 566 .L61: - 567 003e 0020 movs r0, #0 - 268:../../../Source/ARMCM3_STM32/flash.c **** - 568 .loc 1 268 0 - 569 0040 70BD pop {r4, r5, r6, pc} - 570 .LVL65: - 571 .L64: - 572 0042 00BF .align 2 - 573 .L63: - 574 0044 00600008 .word 134242304 - 575 0048 00000000 .word .LANCHOR2 - 576 004c 00000000 .word .LANCHOR1 - 577 .cfi_endproc - 578 .LFE1: - 580 .section .text.FlashErase,"ax",%progbits - 581 .align 2 - 582 .global FlashErase - 583 .thumb - 584 .thumb_func - 586 FlashErase: - 587 .LFB2: - 281:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u first_sector; - 588 .loc 1 281 0 - 589 .cfi_startproc - 590 @ args = 0, pretend = 0, frame = 0 - 591 @ frame_needed = 0, uses_anonymous_args = 0 - 592 .LVL66: - 593 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} - 594 .cfi_def_cfa_offset 24 - 595 .cfi_offset 4, -24 - 596 .cfi_offset 5, -20 - 597 .cfi_offset 6, -16 - 598 .cfi_offset 7, -12 - 599 .cfi_offset 8, -8 - 600 .cfi_offset 14, -4 - 601 0004 0646 mov r6, r0 - 602 0006 0C46 mov r4, r1 - 286:../../../Source/ARMCM3_STM32/flash.c **** last_sector = FlashGetSector(addr+len-1); - 603 .loc 1 286 0 - 604 0008 FFF7FEFF bl FlashGetSector - 605 .LVL67: - 606 000c 0546 mov r5, r0 - 607 .LVL68: - 608 000e 601E subs r0, r4, #1 - 287:../../../Source/ARMCM3_STM32/flash.c **** /* check them */ - 609 .loc 1 287 0 - 610 0010 3044 add r0, r0, r6 - 611 0012 FFF7FEFF bl FlashGetSector - 612 .LVL69: - 613 0016 0446 mov r4, r0 - 614 .LVL70: - 615 .LBB26: - 616 .LBB27: - 669:../../../Source/ARMCM3_STM32/flash.c **** { - 617 .loc 1 669 0 - 618 0018 8542 cmp r5, r0 - 619 001a 00F28580 bhi .L81 - 673:../../../Source/ARMCM3_STM32/flash.c **** (last_sector > flashLayout[FLASH_TOTAL_SECTORS-1].sector_num) ) - 620 .loc 1 673 0 - 621 001e EB1E subs r3, r5, #3 - 622 0020 DBB2 uxtb r3, r3 - 623 0022 FB2B cmp r3, #251 - 624 0024 00F28380 bhi .L82 - 625 0028 0F28 cmp r0, #15 - 626 002a 00F28380 bhi .L83 - 627 .LBB28: - 628 .LBB29: - 728:../../../Source/ARMCM3_STM32/flash.c **** FLASH->KEYR = FLASH_KEY2; - 629 .loc 1 728 0 - 630 002e 434B ldr r3, .L91 - 631 0030 434A ldr r2, .L91+4 - 632 0032 5A60 str r2, [r3, #4] - 729:../../../Source/ARMCM3_STM32/flash.c **** /* clear all possibly pending status flags */ - 633 .loc 1 729 0 - 634 0034 02F18832 add r2, r2, #-2004318072 - 635 0038 5A60 str r2, [r3, #4] - 731:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashUnlock ***/ - 636 .loc 1 731 0 - 637 003a 3422 movs r2, #52 - 638 003c DA60 str r2, [r3, #12] - 639 .LBE29: - 640 .LBE28: - 681:../../../Source/ARMCM3_STM32/flash.c **** { - 641 .loc 1 681 0 - 642 003e DB68 ldr r3, [r3, #12] - 643 0040 13F0010F tst r3, #1 - 644 0044 04D0 beq .L67 - 684:../../../Source/ARMCM3_STM32/flash.c **** /* could not perform erase operation */ - 645 .loc 1 684 0 - 646 0046 FFF7FEFF bl FlashLock - 647 .LVL71: - 686:../../../Source/ARMCM3_STM32/flash.c **** } - 648 .loc 1 686 0 - 649 004a 0020 movs r0, #0 - 650 004c BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 651 .LVL72: - 652 .L67: - 689:../../../Source/ARMCM3_STM32/flash.c **** - 653 .loc 1 689 0 - 654 0050 3A4A ldr r2, .L91 - 655 0052 1369 ldr r3, [r2, #16] - 656 0054 43F00203 orr r3, r3, #2 - 657 0058 1361 str r3, [r2, #16] - 658 .LVL73: - 659 005a 3A4F ldr r7, .L91+8 - 660 005c B846 mov r8, r7 - 661 005e 0026 movs r6, #0 - 662 .LVL74: - 663 .L70: - 664 .LBB30: - 665 .LBB31: - 775:../../../Source/ARMCM3_STM32/flash.c **** - 776:../../../Source/ARMCM3_STM32/flash.c **** - 777:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 778:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Determines the flash sector base address. - 779:../../../Source/ARMCM3_STM32/flash.c **** ** \param sector Sector to get the base address of. - 780:../../../Source/ARMCM3_STM32/flash.c **** ** \return Flash sector base address or FLASH_INVALID_ADDRESS. - 781:../../../Source/ARMCM3_STM32/flash.c **** ** - 782:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 783:../../../Source/ARMCM3_STM32/flash.c **** static blt_addr FlashGetSectorBaseAddr(blt_int8u sector) - 784:../../../Source/ARMCM3_STM32/flash.c **** { - 785:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u sectorIdx; - 786:../../../Source/ARMCM3_STM32/flash.c **** - 787:../../../Source/ARMCM3_STM32/flash.c **** /* search through the sectors to find the right one */ - 788:../../../Source/ARMCM3_STM32/flash.c **** for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++) - 789:../../../Source/ARMCM3_STM32/flash.c **** { - 790:../../../Source/ARMCM3_STM32/flash.c **** /* keep the watchdog happy */ - 791:../../../Source/ARMCM3_STM32/flash.c **** CopService(); - 666 .loc 1 791 0 - 667 0060 FFF7FEFF bl CopService - 668 .LVL75: - 792:../../../Source/ARMCM3_STM32/flash.c **** if (flashLayout[sectorIdx].sector_num == sector) - 669 .loc 1 792 0 - 670 0064 98F80830 ldrb r3, [r8, #8] @ zero_extendqisi2 - 671 0068 AB42 cmp r3, r5 - 672 006a 05D1 bne .L68 - 793:../../../Source/ARMCM3_STM32/flash.c **** { - 794:../../../Source/ARMCM3_STM32/flash.c **** return flashLayout[sectorIdx].sector_start; - 673 .loc 1 794 0 - 674 006c 06EB4602 add r2, r6, r6, lsl #1 - 675 0070 344B ldr r3, .L91+8 - 676 0072 53F82250 ldr r5, [r3, r2, lsl #2] - 677 .LVL76: - 678 0076 06E0 b .L69 - 679 .LVL77: - 680 .L68: - 681 0078 0136 adds r6, r6, #1 - 682 .LVL78: - 683 007a 08F10C08 add r8, r8, #12 - 788:../../../Source/ARMCM3_STM32/flash.c **** { - 684 .loc 1 788 0 - 685 007e 0D2E cmp r6, #13 - 686 0080 EED1 bne .L70 - 795:../../../Source/ARMCM3_STM32/flash.c **** } - 796:../../../Source/ARMCM3_STM32/flash.c **** } - 797:../../../Source/ARMCM3_STM32/flash.c **** /* still here so no valid sector found */ - 798:../../../Source/ARMCM3_STM32/flash.c **** return FLASH_INVALID_ADDRESS; - 687 .loc 1 798 0 - 688 0082 4FF0FF35 mov r5, #-1 - 689 .LVL79: - 690 .L69: - 691 0086 B846 mov r8, r7 - 692 0088 0026 movs r6, #0 - 693 .LVL80: - 694 .L73: - 695 .LBE31: - 696 .LBE30: - 697 .LBB32: - 698 .LBB33: - 791:../../../Source/ARMCM3_STM32/flash.c **** if (flashLayout[sectorIdx].sector_num == sector) - 699 .loc 1 791 0 - 700 008a FFF7FEFF bl CopService - 701 .LVL81: - 792:../../../Source/ARMCM3_STM32/flash.c **** { - 702 .loc 1 792 0 - 703 008e 98F80830 ldrb r3, [r8, #8] @ zero_extendqisi2 - 704 0092 A342 cmp r3, r4 - 705 0094 05D1 bne .L71 - 794:../../../Source/ARMCM3_STM32/flash.c **** } - 706 .loc 1 794 0 - 707 0096 06EB4602 add r2, r6, r6, lsl #1 - 708 009a 2A4B ldr r3, .L91+8 - 709 009c 53F82280 ldr r8, [r3, r2, lsl #2] - 710 00a0 06E0 b .L72 - 711 .L71: - 712 .LVL82: - 713 00a2 0136 adds r6, r6, #1 - 714 .LVL83: - 715 00a4 08F10C08 add r8, r8, #12 - 788:../../../Source/ARMCM3_STM32/flash.c **** { - 716 .loc 1 788 0 - 717 00a8 0D2E cmp r6, #13 - 718 00aa EED1 bne .L73 - 719 .loc 1 798 0 - 720 00ac 4FF0FF38 mov r8, #-1 - 721 .L72: - 722 .LVL84: - 723 00b0 0026 movs r6, #0 - 724 .LVL85: - 725 .L76: - 726 .LBE33: - 727 .LBE32: - 728 .LBB34: - 729 .LBB35: - 799:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashGetSectorBaseAddr ***/ - 800:../../../Source/ARMCM3_STM32/flash.c **** - 801:../../../Source/ARMCM3_STM32/flash.c **** - 802:../../../Source/ARMCM3_STM32/flash.c **** /************************************************************************************//** - 803:../../../Source/ARMCM3_STM32/flash.c **** ** \brief Determines the flash sector size. - 804:../../../Source/ARMCM3_STM32/flash.c **** ** \param sector Sector to get the size of. - 805:../../../Source/ARMCM3_STM32/flash.c **** ** \return Flash sector size or 0. - 806:../../../Source/ARMCM3_STM32/flash.c **** ** - 807:../../../Source/ARMCM3_STM32/flash.c **** ****************************************************************************************/ - 808:../../../Source/ARMCM3_STM32/flash.c **** static blt_addr FlashGetSectorSize(blt_int8u sector) - 809:../../../Source/ARMCM3_STM32/flash.c **** { - 810:../../../Source/ARMCM3_STM32/flash.c **** blt_int8u sectorIdx; - 811:../../../Source/ARMCM3_STM32/flash.c **** - 812:../../../Source/ARMCM3_STM32/flash.c **** /* search through the sectors to find the right one */ - 813:../../../Source/ARMCM3_STM32/flash.c **** for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++) - 814:../../../Source/ARMCM3_STM32/flash.c **** { - 815:../../../Source/ARMCM3_STM32/flash.c **** /* keep the watchdog happy */ - 816:../../../Source/ARMCM3_STM32/flash.c **** CopService(); - 730 .loc 1 816 0 - 731 00b2 FFF7FEFF bl CopService - 732 .LVL86: - 817:../../../Source/ARMCM3_STM32/flash.c **** if (flashLayout[sectorIdx].sector_num == sector) - 733 .loc 1 817 0 - 734 00b6 3B7A ldrb r3, [r7, #8] @ zero_extendqisi2 - 735 00b8 A342 cmp r3, r4 - 736 00ba 06D1 bne .L74 - 818:../../../Source/ARMCM3_STM32/flash.c **** { - 819:../../../Source/ARMCM3_STM32/flash.c **** return flashLayout[sectorIdx].sector_size; - 737 .loc 1 819 0 - 738 00bc 06EB4602 add r2, r6, r6, lsl #1 - 739 00c0 204B ldr r3, .L91+8 - 740 00c2 03EB8202 add r2, r3, r2, lsl #2 - 741 00c6 5368 ldr r3, [r2, #4] - 742 00c8 04E0 b .L75 - 743 .L74: - 744 .LVL87: - 745 00ca 0136 adds r6, r6, #1 - 746 .LVL88: - 747 00cc 0C37 adds r7, r7, #12 - 813:../../../Source/ARMCM3_STM32/flash.c **** { - 748 .loc 1 813 0 - 749 00ce 0D2E cmp r6, #13 - 750 00d0 EFD1 bne .L76 - 820:../../../Source/ARMCM3_STM32/flash.c **** } - 821:../../../Source/ARMCM3_STM32/flash.c **** } - 822:../../../Source/ARMCM3_STM32/flash.c **** /* still here so no valid sector found */ - 823:../../../Source/ARMCM3_STM32/flash.c **** return 0; - 751 .loc 1 823 0 - 752 00d2 0023 movs r3, #0 - 753 .L75: - 754 .LVL89: - 755 00d4 C5EB0808 rsb r8, r5, r8 - 756 .LVL90: - 757 .LBE35: - 758 .LBE34: - 694:../../../Source/ARMCM3_STM32/flash.c **** - 759 .loc 1 694 0 - 760 00d8 4344 add r3, r3, r8 - 761 00da C3F38F23 ubfx r3, r3, #10, #16 - 762 .LVL91: - 697:../../../Source/ARMCM3_STM32/flash.c **** { - 763 .loc 1 697 0 - 764 00de CBB1 cbz r3, .L77 - 765 00e0 05F58066 add r6, r5, #1024 - 766 00e4 013B subs r3, r3, #1 - 767 .LVL92: - 768 00e6 9AB2 uxth r2, r3 - 769 00e8 06EB8226 add r6, r6, r2, lsl #10 - 700:../../../Source/ARMCM3_STM32/flash.c **** /* start the block erase operation */ - 770 .loc 1 700 0 - 771 00ec 134C ldr r4, .L91 - 772 .LVL93: - 773 .L80: - 774 00ee 6561 str r5, [r4, #20] - 702:../../../Source/ARMCM3_STM32/flash.c **** /* wait for the erase operation to complete */ - 775 .loc 1 702 0 - 776 00f0 2369 ldr r3, [r4, #16] - 777 00f2 43F04003 orr r3, r3, #64 - 778 00f6 2361 str r3, [r4, #16] - 704:../../../Source/ARMCM3_STM32/flash.c **** { - 779 .loc 1 704 0 - 780 00f8 E368 ldr r3, [r4, #12] - 781 00fa 13F0010F tst r3, #1 - 782 00fe 05D0 beq .L78 - 783 .L84: - 707:../../../Source/ARMCM3_STM32/flash.c **** } - 784 .loc 1 707 0 - 785 0100 FFF7FEFF bl CopService - 786 .LVL94: - 704:../../../Source/ARMCM3_STM32/flash.c **** { - 787 .loc 1 704 0 - 788 0104 E368 ldr r3, [r4, #12] - 789 0106 13F0010F tst r3, #1 - 790 010a F9D1 bne .L84 - 791 .L78: - 792 010c 05F58065 add r5, r5, #1024 - 697:../../../Source/ARMCM3_STM32/flash.c **** { - 793 .loc 1 697 0 - 794 0110 B542 cmp r5, r6 - 795 0112 ECD1 bne .L80 - 796 .L77: - 711:../../../Source/ARMCM3_STM32/flash.c **** /* lock the flash array */ - 797 .loc 1 711 0 - 798 0114 094A ldr r2, .L91 - 799 0116 1369 ldr r3, [r2, #16] - 800 0118 23F00203 bic r3, r3, #2 - 801 011c 1361 str r3, [r2, #16] - 713:../../../Source/ARMCM3_STM32/flash.c **** /* still here so all went okay */ - 802 .loc 1 713 0 - 803 011e FFF7FEFF bl FlashLock - 804 .LVL95: - 715:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashEraseSectors ***/ - 805 .loc 1 715 0 - 806 0122 0120 movs r0, #1 - 807 0124 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 808 .LVL96: - 809 .L81: - 671:../../../Source/ARMCM3_STM32/flash.c **** } - 810 .loc 1 671 0 - 811 0128 0020 movs r0, #0 - 812 .LVL97: - 813 012a BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 814 .LVL98: - 815 .L82: - 676:../../../Source/ARMCM3_STM32/flash.c **** } - 816 .loc 1 676 0 - 817 012e 0020 movs r0, #0 - 818 .LVL99: - 819 0130 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 820 .LVL100: - 821 .L83: - 822 0134 0020 movs r0, #0 - 823 .LVL101: - 824 .LBE27: - 825 .LBE26: - 295:../../../Source/ARMCM3_STM32/flash.c **** - 826 .loc 1 295 0 - 827 0136 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 828 .LVL102: - 829 .L92: - 830 013a 00BF .align 2 - 831 .L91: - 832 013c 00200240 .word 1073881088 - 833 0140 23016745 .word 1164378403 - 834 0144 00000000 .word .LANCHOR0 - 835 .cfi_endproc - 836 .LFE2: - 838 .section .text.FlashWriteChecksum,"ax",%progbits - 839 .align 2 - 840 .global FlashWriteChecksum - 841 .thumb - 842 .thumb_func - 844 FlashWriteChecksum: - 845 .LFB3: - 308:../../../Source/ARMCM3_STM32/flash.c **** blt_int32u signature_checksum = 0; - 846 .loc 1 308 0 - 847 .cfi_startproc - 848 @ args = 0, pretend = 0, frame = 8 - 849 @ frame_needed = 0, uses_anonymous_args = 0 - 335:../../../Source/ARMCM3_STM32/flash.c **** { - 850 .loc 1 335 0 - 851 0000 114B ldr r3, .L98 - 852 0002 1B68 ldr r3, [r3] - 853 0004 B3F1FF3F cmp r3, #-1 - 854 0008 18D0 beq .L95 - 308:../../../Source/ARMCM3_STM32/flash.c **** blt_int32u signature_checksum = 0; - 855 .loc 1 308 0 - 856 000a 00B5 push {lr} - 857 .cfi_def_cfa_offset 4 - 858 .cfi_offset 14, -4 - 859 000c 83B0 sub sp, sp, #12 - 860 .cfi_def_cfa_offset 16 - 344:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x08])); - 861 .loc 1 344 0 - 862 000e 0E4B ldr r3, .L98 - 863 0010 9968 ldr r1, [r3, #8] - 864 0012 5A68 ldr r2, [r3, #4] - 865 0014 1144 add r1, r1, r2 - 345:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x0C])); - 866 .loc 1 345 0 - 867 0016 DA68 ldr r2, [r3, #12] - 868 0018 1144 add r1, r1, r2 - 346:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x10])); - 869 .loc 1 346 0 - 870 001a 1A69 ldr r2, [r3, #16] - 871 001c 1144 add r1, r1, r2 - 347:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x14])); - 872 .loc 1 347 0 - 873 001e 5A69 ldr r2, [r3, #20] - 874 0020 1144 add r1, r1, r2 - 348:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x18])); - 875 .loc 1 348 0 - 876 0022 9A69 ldr r2, [r3, #24] - 877 0024 1144 add r1, r1, r2 - 349:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum = ~signature_checksum; /* one's complement */ - 878 .loc 1 349 0 - 879 0026 DA69 ldr r2, [r3, #28] - 880 0028 8B18 adds r3, r1, r2 - 351:../../../Source/ARMCM3_STM32/flash.c **** - 881 .loc 1 351 0 - 882 002a 5B42 negs r3, r3 - 883 002c 02AA add r2, sp, #8 - 884 002e 42F8043D str r3, [r2, #-4]! - 354:../../../Source/ARMCM3_STM32/flash.c **** sizeof(blt_addr), (blt_int8u*)&signature_checksum); - 885 .loc 1 354 0 - 886 0032 0648 ldr r0, .L98+4 - 887 0034 0421 movs r1, #4 - 888 0036 FFF7FEFF bl FlashWrite - 889 .LVL103: - 890 003a 01E0 b .L94 - 891 .L95: - 892 .cfi_def_cfa_offset 0 - 893 .cfi_restore 14 - 337:../../../Source/ARMCM3_STM32/flash.c **** } - 894 .loc 1 337 0 - 895 003c 0120 movs r0, #1 - 896 003e 7047 bx lr - 897 .L94: - 898 .cfi_def_cfa_offset 16 - 899 .cfi_offset 14, -4 - 356:../../../Source/ARMCM3_STM32/flash.c **** - 900 .loc 1 356 0 - 901 0040 03B0 add sp, sp, #12 - 902 .cfi_def_cfa_offset 4 - 903 @ sp needed - 904 0042 5DF804FB ldr pc, [sp], #4 - 905 .L99: - 906 0046 00BF .align 2 - 907 .L98: - 908 0048 00000000 .word .LANCHOR2 - 909 004c 50610008 .word 134242640 - 910 .cfi_endproc - 911 .LFE3: - 913 .section .text.FlashVerifyChecksum,"ax",%progbits - 914 .align 2 - 915 .global FlashVerifyChecksum - 916 .thumb - 917 .thumb_func - 919 FlashVerifyChecksum: - 920 .LFB4: - 366:../../../Source/ARMCM3_STM32/flash.c **** blt_int32u signature_checksum = 0; - 921 .loc 1 366 0 - 922 .cfi_startproc - 923 @ args = 0, pretend = 0, frame = 0 - 924 @ frame_needed = 0, uses_anonymous_args = 0 - 925 @ link register save eliminated. - 926 .LVL104: - 371:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x08)); - 927 .loc 1 371 0 - 928 0000 0D4B ldr r3, .L101 - 929 0002 1A68 ldr r2, [r3] - 930 0004 043B subs r3, r3, #4 - 931 0006 1B68 ldr r3, [r3] - 932 0008 1344 add r3, r3, r2 - 933 .LVL105: - 372:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x0C)); - 934 .loc 1 372 0 - 935 000a 0C4A ldr r2, .L101+4 - 936 000c 1268 ldr r2, [r2] - 937 000e 1344 add r3, r3, r2 - 938 .LVL106: - 373:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x10)); - 939 .loc 1 373 0 - 940 0010 0B4A ldr r2, .L101+8 - 941 0012 1268 ldr r2, [r2] - 942 0014 1344 add r3, r3, r2 - 943 .LVL107: - 374:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x14)); - 944 .loc 1 374 0 - 945 0016 0B4A ldr r2, .L101+12 - 946 0018 1168 ldr r1, [r2] - 947 001a 0B44 add r3, r3, r1 - 948 .LVL108: - 375:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x18)); - 949 .loc 1 375 0 - 950 001c 0432 adds r2, r2, #4 - 951 001e 1268 ldr r2, [r2] - 952 0020 1A44 add r2, r2, r3 - 953 .LVL109: - 376:../../../Source/ARMCM3_STM32/flash.c **** signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+FLASH_VECTOR_TABLE_CS_OFFSET)); - 954 .loc 1 376 0 - 955 0022 094B ldr r3, .L101+16 - 956 0024 1B68 ldr r3, [r3] - 957 0026 1344 add r3, r3, r2 - 958 .LVL110: - 377:../../../Source/ARMCM3_STM32/flash.c **** /* sum should add up to an unsigned 32-bit value of 0 */ - 959 .loc 1 377 0 - 960 0028 084A ldr r2, .L101+20 - 961 .LVL111: - 962 002a 1268 ldr r2, [r2] - 963 .LVL112: - 379:../../../Source/ARMCM3_STM32/flash.c **** { - 964 .loc 1 379 0 - 965 002c D342 cmn r3, r2 - 386:../../../Source/ARMCM3_STM32/flash.c **** - 966 .loc 1 386 0 - 967 002e 0CBF ite eq - 968 0030 0120 moveq r0, #1 - 969 0032 0020 movne r0, #0 - 970 0034 7047 bx lr - 971 .L102: - 972 0036 00BF .align 2 - 973 .L101: - 974 0038 04600008 .word 134242308 - 975 003c 08600008 .word 134242312 - 976 0040 0C600008 .word 134242316 - 977 0044 10600008 .word 134242320 - 978 0048 18600008 .word 134242328 - 979 004c 50610008 .word 134242640 - 980 .cfi_endproc - 981 .LFE4: - 983 .section .text.FlashDone,"ax",%progbits - 984 .align 2 - 985 .global FlashDone - 986 .thumb - 987 .thumb_func - 989 FlashDone: - 990 .LFB5: - 396:../../../Source/ARMCM3_STM32/flash.c **** /* check if there is still data waiting to be programmed in the boot block */ - 991 .loc 1 396 0 - 992 .cfi_startproc - 993 @ args = 0, pretend = 0, frame = 0 - 994 @ frame_needed = 0, uses_anonymous_args = 0 - 995 0000 08B5 push {r3, lr} - 996 .cfi_def_cfa_offset 8 - 997 .cfi_offset 3, -8 - 998 .cfi_offset 14, -4 - 398:../../../Source/ARMCM3_STM32/flash.c **** { - 999 .loc 1 398 0 - 1000 0002 0C4B ldr r3, .L108 - 1001 0004 1B68 ldr r3, [r3] - 1002 0006 B3F1FF3F cmp r3, #-1 - 1003 000a 04D0 beq .L104 - 400:../../../Source/ARMCM3_STM32/flash.c **** { - 1004 .loc 1 400 0 - 1005 000c 0948 ldr r0, .L108 - 1006 000e FFF7FEFF bl FlashWriteBlock - 1007 .LVL113: - 1008 0012 0346 mov r3, r0 - 1009 0014 60B1 cbz r0, .L105 - 1010 .L104: - 407:../../../Source/ARMCM3_STM32/flash.c **** { - 1011 .loc 1 407 0 - 1012 0016 084B ldr r3, .L108+4 - 1013 0018 1B68 ldr r3, [r3] - 1014 001a B3F1FF3F cmp r3, #-1 - 1015 001e 06D0 beq .L106 - 409:../../../Source/ARMCM3_STM32/flash.c **** { - 1016 .loc 1 409 0 - 1017 0020 0548 ldr r0, .L108+4 - 1018 0022 FFF7FEFF bl FlashWriteBlock - 1019 .LVL114: - 402:../../../Source/ARMCM3_STM32/flash.c **** } - 1020 .loc 1 402 0 - 1021 0026 031C adds r3, r0, #0 - 1022 0028 18BF it ne - 1023 002a 0123 movne r3, #1 - 1024 002c 00E0 b .L105 - 1025 .L106: - 415:../../../Source/ARMCM3_STM32/flash.c **** } /*** end of FlashDone ***/ - 1026 .loc 1 415 0 - 1027 002e 0123 movs r3, #1 - 1028 .L105: - 416:../../../Source/ARMCM3_STM32/flash.c **** - 1029 .loc 1 416 0 - 1030 0030 1846 mov r0, r3 - 1031 0032 08BD pop {r3, pc} - 1032 .L109: - 1033 .align 2 - 1034 .L108: - 1035 0034 00000000 .word .LANCHOR2 - 1036 0038 00000000 .word .LANCHOR1 - 1037 .cfi_endproc - 1038 .LFE5: - 1040 .section .text.FlashGetUserProgBaseAddress,"ax",%progbits - 1041 .align 2 - 1042 .global FlashGetUserProgBaseAddress - 1043 .thumb - 1044 .thumb_func - 1046 FlashGetUserProgBaseAddress: - 1047 .LFB6: - 426:../../../Source/ARMCM3_STM32/flash.c **** return flashLayout[0].sector_start; - 1048 .loc 1 426 0 - 1049 .cfi_startproc - 1050 @ args = 0, pretend = 0, frame = 0 - 1051 @ frame_needed = 0, uses_anonymous_args = 0 - 1052 @ link register save eliminated. - 428:../../../Source/ARMCM3_STM32/flash.c **** - 1053 .loc 1 428 0 - 1054 0000 0048 ldr r0, .L111 - 1055 0002 7047 bx lr - 1056 .L112: - 1057 .align 2 - 1058 .L111: - 1059 0004 00600008 .word 134242304 - 1060 .cfi_endproc - 1061 .LFE6: - 1063 .section .rodata.flashLayout,"a",%progbits - 1064 .align 2 - 1065 .set .LANCHOR0,. + 0 - 1068 flashLayout: - 1069 0000 00600008 .word 134242304 - 1070 0004 00200000 .word 8192 - 1071 0008 03 .byte 3 - 1072 0009 000000 .space 3 - 1073 000c 00800008 .word 134250496 - 1074 0010 00200000 .word 8192 - 1075 0014 04 .byte 4 - 1076 0015 000000 .space 3 - 1077 0018 00A00008 .word 134258688 - 1078 001c 00200000 .word 8192 - 1079 0020 05 .byte 5 - 1080 0021 000000 .space 3 - 1081 0024 00C00008 .word 134266880 - 1082 0028 00200000 .word 8192 - 1083 002c 06 .byte 6 - 1084 002d 000000 .space 3 - 1085 0030 00E00008 .word 134275072 - 1086 0034 00200000 .word 8192 - 1087 0038 07 .byte 7 - 1088 0039 000000 .space 3 - 1089 003c 00000108 .word 134283264 - 1090 0040 00200000 .word 8192 - 1091 0044 08 .byte 8 - 1092 0045 000000 .space 3 - 1093 0048 00200108 .word 134291456 - 1094 004c 00200000 .word 8192 - 1095 0050 09 .byte 9 - 1096 0051 000000 .space 3 - 1097 0054 00400108 .word 134299648 - 1098 0058 00200000 .word 8192 - 1099 005c 0A .byte 10 - 1100 005d 000000 .space 3 - 1101 0060 00600108 .word 134307840 - 1102 0064 00200000 .word 8192 - 1103 0068 0B .byte 11 - 1104 0069 000000 .space 3 - 1105 006c 00800108 .word 134316032 - 1106 0070 00200000 .word 8192 - 1107 0074 0C .byte 12 - 1108 0075 000000 .space 3 - 1109 0078 00A00108 .word 134324224 - 1110 007c 00200000 .word 8192 - 1111 0080 0D .byte 13 - 1112 0081 000000 .space 3 - 1113 0084 00C00108 .word 134332416 - 1114 0088 00200000 .word 8192 - 1115 008c 0E .byte 14 - 1116 008d 000000 .space 3 - 1117 0090 00E00108 .word 134340608 - 1118 0094 00200000 .word 8192 - 1119 0098 0F .byte 15 - 1120 0099 000000 .space 3 - 1121 .section .bss.bootBlockInfo,"aw",%nobits - 1122 .align 2 - 1123 .set .LANCHOR2,. + 0 - 1126 bootBlockInfo: - 1127 0000 00000000 .space 516 - 1127 00000000 - 1127 00000000 - 1127 00000000 - 1127 00000000 - 1128 .section .bss.blockInfo,"aw",%nobits - 1129 .align 2 - 1130 .set .LANCHOR1,. + 0 - 1133 blockInfo: - 1134 0000 00000000 .space 516 - 1134 00000000 - 1134 00000000 - 1134 00000000 - 1134 00000000 - 1135 .text - 1136 .Letext0: - 1137 .file 2 "../../../Source/ARMCM3_STM32/types.h" - 1138 .file 3 "../../../Source/cop.h" - 1139 .file 4 "../../../Source/ARMCM3_STM32/cpu.h" -DEFINED SYMBOLS - *ABS*:00000000 flash.c -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:19 .text.FlashLock:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:23 .text.FlashLock:00000000 FlashLock -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:40 .text.FlashLock:0000000c $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:45 .text.FlashGetSector:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:49 .text.FlashGetSector:00000000 FlashGetSector -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:107 .text.FlashGetSector:00000038 $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:112 .text.FlashWriteBlock:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:116 .text.FlashWriteBlock:00000000 FlashWriteBlock -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:255 .text.FlashWriteBlock:000000ac $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:261 .text.FlashSwitchBlock:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:265 .text.FlashSwitchBlock:00000000 FlashSwitchBlock -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:350 .text.FlashSwitchBlock:0000004c $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:357 .text.FlashAddToBlock:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:361 .text.FlashAddToBlock:00000000 FlashAddToBlock -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:479 .text.FlashInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:484 .text.FlashInit:00000000 FlashInit -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:502 .text.FlashInit:00000010 $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:508 .text.FlashWrite:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:513 .text.FlashWrite:00000000 FlashWrite -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:574 .text.FlashWrite:00000044 $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:581 .text.FlashErase:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:586 .text.FlashErase:00000000 FlashErase -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:832 .text.FlashErase:0000013c $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:839 .text.FlashWriteChecksum:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:844 .text.FlashWriteChecksum:00000000 FlashWriteChecksum -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:908 .text.FlashWriteChecksum:00000048 $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:914 .text.FlashVerifyChecksum:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:919 .text.FlashVerifyChecksum:00000000 FlashVerifyChecksum -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:974 .text.FlashVerifyChecksum:00000038 $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:984 .text.FlashDone:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:989 .text.FlashDone:00000000 FlashDone -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:1035 .text.FlashDone:00000034 $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:1041 .text.FlashGetUserProgBaseAddress:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:1046 .text.FlashGetUserProgBaseAddress:00000000 FlashGetUserProgBaseAddress -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:1059 .text.FlashGetUserProgBaseAddress:00000004 $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:1064 .rodata.flashLayout:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:1068 .rodata.flashLayout:00000000 flashLayout -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:1122 .bss.bootBlockInfo:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:1126 .bss.bootBlockInfo:00000000 bootBlockInfo -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:1129 .bss.blockInfo:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\cc2UpPQC.s:1133 .bss.blockInfo:00000000 blockInfo - .debug_frame:00000010 $d - -UNDEFINED SYMBOLS -CopService -CpuMemCopy diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/hooks.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/hooks.lst deleted file mode 100644 index 4eaef275..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/hooks.lst +++ /dev/null @@ -1,22 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "hooks.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .Letext0: -DEFINED SYMBOLS - *ABS*:00000000 hooks.c - -NO UNDEFINED SYMBOLS diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/main.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/main.lst deleted file mode 100644 index 97a651d5..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/main.lst +++ /dev/null @@ -1,431 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "main.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.main,"ax",%progbits - 19 .align 2 - 20 .global main - 21 .thumb - 22 .thumb_func - 24 main: - 25 .LFB29: - 26 .file 1 "main.c" - 1:main.c **** /************************************************************************************//** - 2:main.c **** * \file Demo\ARMCM3_STM32_Olimex_STM32P103_GCC\Boot\main.c - 3:main.c **** * \brief Bootloader application source file. - 4:main.c **** * \ingroup Boot_ARMCM3_STM32_Olimex_STM32P103_GCC - 5:main.c **** * \internal - 6:main.c **** *---------------------------------------------------------------------------------------- - 7:main.c **** * C O P Y R I G H T - 8:main.c **** *---------------------------------------------------------------------------------------- - 9:main.c **** * Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved - 10:main.c **** * - 11:main.c **** *---------------------------------------------------------------------------------------- - 12:main.c **** * L I C E N S E - 13:main.c **** *---------------------------------------------------------------------------------------- - 14:main.c **** * This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or - 15:main.c **** * modify it under the terms of the GNU General Public License as published by the Free - 16:main.c **** * Software Foundation, either version 3 of the License, or (at your option) any later - 17:main.c **** * version. - 18:main.c **** * - 19:main.c **** * OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; - 20:main.c **** * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - 21:main.c **** * PURPOSE. See the GNU General Public License for more details. - 22:main.c **** * - 23:main.c **** * You should have received a copy of the GNU General Public License along with OpenBLT. - 24:main.c **** * If not, see . - 25:main.c **** * - 26:main.c **** * A special exception to the GPL is included to allow you to distribute a combined work - 27:main.c **** * that includes OpenBLT without being obliged to provide the source code for any - 28:main.c **** * proprietary components. The exception text is included at the bottom of the license - 29:main.c **** * file . - 30:main.c **** * - 31:main.c **** * \endinternal - 32:main.c **** ****************************************************************************************/ - 33:main.c **** - 34:main.c **** /**************************************************************************************** - 35:main.c **** * Include files - 36:main.c **** ****************************************************************************************/ - 37:main.c **** #include "boot.h" /* bootloader generic header */ - 38:main.c **** #include "stm32f10x.h" /* microcontroller registers */ - 39:main.c **** #if (BOOT_FILE_LOGGING_ENABLE > 0) && (BOOT_COM_UART_ENABLE == 0) - 40:main.c **** #include "stm32f10x_conf.h" /* STM32 peripheral drivers */ - 41:main.c **** #endif - 42:main.c **** - 43:main.c **** - 44:main.c **** /**************************************************************************************** - 45:main.c **** * Function prototypes - 46:main.c **** ****************************************************************************************/ - 47:main.c **** static void Init(void); - 48:main.c **** - 49:main.c **** - 50:main.c **** /************************************************************************************//** - 51:main.c **** ** \brief This is the entry point for the bootloader application and is called - 52:main.c **** ** by the reset interrupt vector after the C-startup routines executed. - 53:main.c **** ** \return Program return code. - 54:main.c **** ** - 55:main.c **** ****************************************************************************************/ - 56:main.c **** int main(void) - 57:main.c **** { - 27 .loc 1 57 0 - 28 .cfi_startproc - 29 @ Volatile: function does not return. - 30 @ args = 0, pretend = 0, frame = 8 - 31 @ frame_needed = 0, uses_anonymous_args = 0 - 32 0000 00B5 push {lr} - 33 .cfi_def_cfa_offset 4 - 34 .cfi_offset 14, -4 - 35 0002 83B0 sub sp, sp, #12 - 36 .cfi_def_cfa_offset 16 - 37 .LBB4: - 38 .LBB5: - 58:main.c **** /* initialize the microcontroller */ - 59:main.c **** Init(); - 60:main.c **** /* initialize the bootloader */ - 61:main.c **** BootInit(); - 62:main.c **** - 63:main.c **** /* start the infinite program loop */ - 64:main.c **** while (1) - 65:main.c **** { - 66:main.c **** /* run the bootloader task */ - 67:main.c **** BootTask(); - 68:main.c **** } - 69:main.c **** - 70:main.c **** /* program should never get here */ - 71:main.c **** return 0; - 72:main.c **** } /*** end of main ***/ - 73:main.c **** - 74:main.c **** - 75:main.c **** /************************************************************************************//** - 76:main.c **** ** \brief Initializes the microcontroller. - 77:main.c **** ** \return none. - 78:main.c **** ** - 79:main.c **** ****************************************************************************************/ - 80:main.c **** static void Init(void) - 81:main.c **** { - 82:main.c **** volatile blt_int32u StartUpCounter = 0, HSEStatus = 0; - 39 .loc 1 82 0 - 40 0004 0023 movs r3, #0 - 41 0006 0093 str r3, [sp] - 42 0008 0193 str r3, [sp, #4] - 83:main.c **** blt_int32u pll_multiplier; - 84:main.c **** #if (BOOT_FILE_LOGGING_ENABLE > 0) && (BOOT_COM_UART_ENABLE == 0) - 85:main.c **** GPIO_InitTypeDef GPIO_InitStruct; - 86:main.c **** USART_InitTypeDef USART_InitStruct; - 87:main.c **** #endif - 88:main.c **** - 89:main.c **** /* reset the RCC clock configuration to the default reset state (for debug purpose) */ - 90:main.c **** /* set HSION bit */ - 91:main.c **** RCC->CR |= (blt_int32u)0x00000001; - 43 .loc 1 91 0 - 44 000a 03F18043 add r3, r3, #1073741824 - 45 000e 03F50433 add r3, r3, #135168 - 46 0012 1A68 ldr r2, [r3] - 47 0014 42F00102 orr r2, r2, #1 - 48 0018 1A60 str r2, [r3] - 92:main.c **** /* reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ - 93:main.c **** RCC->CFGR &= (blt_int32u)0xF8FF0000; - 49 .loc 1 93 0 - 50 001a 5968 ldr r1, [r3, #4] - 51 001c 434A ldr r2, .L12 - 52 001e 0A40 ands r2, r2, r1 - 53 0020 5A60 str r2, [r3, #4] - 94:main.c **** /* reset HSEON, CSSON and PLLON bits */ - 95:main.c **** RCC->CR &= (blt_int32u)0xFEF6FFFF; - 54 .loc 1 95 0 - 55 0022 1A68 ldr r2, [r3] - 56 0024 22F08472 bic r2, r2, #17301504 - 57 0028 22F48032 bic r2, r2, #65536 - 58 002c 1A60 str r2, [r3] - 96:main.c **** /* reset HSEBYP bit */ - 97:main.c **** RCC->CR &= (blt_int32u)0xFFFBFFFF; - 59 .loc 1 97 0 - 60 002e 1A68 ldr r2, [r3] - 61 0030 22F48022 bic r2, r2, #262144 - 62 0034 1A60 str r2, [r3] - 98:main.c **** /* reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - 99:main.c **** RCC->CFGR &= (blt_int32u)0xFF80FFFF; - 63 .loc 1 99 0 - 64 0036 5A68 ldr r2, [r3, #4] - 65 0038 22F4FE02 bic r2, r2, #8323072 - 66 003c 5A60 str r2, [r3, #4] - 100:main.c **** /* disable all interrupts and clear pending bits */ - 101:main.c **** RCC->CIR = 0x009F0000; - 67 .loc 1 101 0 - 68 003e 4FF41F02 mov r2, #10420224 - 69 0042 9A60 str r2, [r3, #8] - 102:main.c **** /* enable HSE */ - 103:main.c **** RCC->CR |= ((blt_int32u)RCC_CR_HSEON); - 70 .loc 1 103 0 - 71 0044 1A68 ldr r2, [r3] - 72 0046 42F48032 orr r2, r2, #65536 - 73 004a 1A60 str r2, [r3] - 104:main.c **** /* wait till HSE is ready and if Time out is reached exit */ - 105:main.c **** do - 106:main.c **** { - 107:main.c **** HSEStatus = RCC->CR & RCC_CR_HSERDY; - 74 .loc 1 107 0 - 75 004c 1946 mov r1, r3 - 108:main.c **** StartUpCounter++; - 109:main.c **** } - 110:main.c **** while((HSEStatus == 0) && (StartUpCounter != 1500)); - 76 .loc 1 110 0 - 77 004e 40F2DC52 movw r2, #1500 - 78 .L3: - 107:main.c **** StartUpCounter++; - 79 .loc 1 107 0 - 80 0052 0B68 ldr r3, [r1] - 81 0054 03F40033 and r3, r3, #131072 - 82 0058 0193 str r3, [sp, #4] - 108:main.c **** StartUpCounter++; - 83 .loc 1 108 0 - 84 005a 009B ldr r3, [sp] - 85 005c 0133 adds r3, r3, #1 - 86 005e 0093 str r3, [sp] - 87 .loc 1 110 0 - 88 0060 019B ldr r3, [sp, #4] - 89 0062 13B9 cbnz r3, .L2 - 90 0064 009B ldr r3, [sp] - 91 0066 9342 cmp r3, r2 - 92 0068 F3D1 bne .L3 - 93 .L2: - 111:main.c **** /* check if time out was reached */ - 112:main.c **** if ((RCC->CR & RCC_CR_HSERDY) == RESET) - 94 .loc 1 112 0 - 95 006a 314B ldr r3, .L12+4 - 96 006c 1B68 ldr r3, [r3] - 97 006e 13F4003F tst r3, #131072 - 98 0072 03D1 bne .L4 - 113:main.c **** { - 114:main.c **** /* cannot continue when HSE is not ready */ - 115:main.c **** ASSERT_RT(BLT_FALSE); - 99 .loc 1 115 0 - 100 0074 2F48 ldr r0, .L12+8 - 101 0076 7321 movs r1, #115 - 102 0078 FFF7FEFF bl AssertFailure - 103 .LVL0: - 104 .L4: - 116:main.c **** } - 117:main.c **** /* enable flash prefetch buffer */ - 118:main.c **** FLASH->ACR |= FLASH_ACR_PRFTBE; - 105 .loc 1 118 0 - 106 007c 2E4B ldr r3, .L12+12 - 107 007e 1A68 ldr r2, [r3] - 108 0080 42F01002 orr r2, r2, #16 - 109 0084 1A60 str r2, [r3] - 119:main.c **** /* reset flash wait state configuration to default 0 wait states */ - 120:main.c **** FLASH->ACR &= (blt_int32u)((blt_int32u)~FLASH_ACR_LATENCY); - 110 .loc 1 120 0 - 111 0086 1A68 ldr r2, [r3] - 112 0088 22F00302 bic r2, r2, #3 - 113 008c 1A60 str r2, [r3] - 121:main.c **** #if (BOOT_CPU_SYSTEM_SPEED_KHZ > 48000) - 122:main.c **** /* configure 2 flash wait states */ - 123:main.c **** FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_2; - 114 .loc 1 123 0 - 115 008e 1A68 ldr r2, [r3] - 116 0090 42F00202 orr r2, r2, #2 - 117 0094 1A60 str r2, [r3] - 124:main.c **** #elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000) - 125:main.c **** /* configure 1 flash wait states */ - 126:main.c **** FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_1; - 127:main.c **** #endif - 128:main.c **** /* HCLK = SYSCLK */ - 129:main.c **** RCC->CFGR |= (blt_int32u)RCC_CFGR_HPRE_DIV1; - 118 .loc 1 129 0 - 119 0096 A3F58053 sub r3, r3, #4096 - 120 009a 5A68 ldr r2, [r3, #4] - 121 009c 5A60 str r2, [r3, #4] - 130:main.c **** /* PCLK2 = HCLK/2 */ - 131:main.c **** RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE2_DIV2; - 122 .loc 1 131 0 - 123 009e 5A68 ldr r2, [r3, #4] - 124 00a0 42F40052 orr r2, r2, #8192 - 125 00a4 5A60 str r2, [r3, #4] - 132:main.c **** /* PCLK1 = HCLK/2 */ - 133:main.c **** RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE1_DIV2; - 126 .loc 1 133 0 - 127 00a6 5A68 ldr r2, [r3, #4] - 128 00a8 42F48062 orr r2, r2, #1024 - 129 00ac 5A60 str r2, [r3, #4] - 134:main.c **** /* reset PLL configuration */ - 135:main.c **** RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | \ - 130 .loc 1 135 0 - 131 00ae 5A68 ldr r2, [r3, #4] - 132 00b0 22F47C12 bic r2, r2, #4128768 - 133 00b4 5A60 str r2, [r3, #4] - 134 .LVL1: - 136:main.c **** RCC_CFGR_PLLMULL)); - 137:main.c **** /* assert that the pll_multiplier is between 2 and 16 */ - 138:main.c **** ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) >= 2); - 139:main.c **** ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) <= 16); - 140:main.c **** /* calculate multiplier value */ - 141:main.c **** pll_multiplier = BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ; - 142:main.c **** /* convert to register value */ - 143:main.c **** pll_multiplier = (blt_int32u)((pll_multiplier - 2) << 18); - 144:main.c **** /* set the PLL multiplier and clock source */ - 145:main.c **** RCC->CFGR |= (blt_int32u)(RCC_CFGR_PLLSRC_HSE | pll_multiplier); - 135 .loc 1 145 0 - 136 00b6 5A68 ldr r2, [r3, #4] - 137 00b8 42F4E812 orr r2, r2, #1900544 - 138 00bc 5A60 str r2, [r3, #4] - 146:main.c **** /* enable PLL */ - 147:main.c **** RCC->CR |= RCC_CR_PLLON; - 139 .loc 1 147 0 - 140 00be 1A68 ldr r2, [r3] - 141 00c0 42F08072 orr r2, r2, #16777216 - 142 00c4 1A60 str r2, [r3] - 143 .L5: - 148:main.c **** /* wait till PLL is ready */ - 149:main.c **** while((RCC->CR & RCC_CR_PLLRDY) == 0) - 144 .loc 1 149 0 - 145 00c6 1A68 ldr r2, [r3] - 146 00c8 12F0007F tst r2, #33554432 - 147 00cc FBD0 beq .L5 - 150:main.c **** { - 151:main.c **** } - 152:main.c **** /* select PLL as system clock source */ - 153:main.c **** RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_SW)); - 148 .loc 1 153 0 - 149 00ce 184B ldr r3, .L12+4 - 150 00d0 5A68 ldr r2, [r3, #4] - 151 00d2 22F00302 bic r2, r2, #3 - 152 00d6 5A60 str r2, [r3, #4] - 154:main.c **** RCC->CFGR |= (blt_int32u)RCC_CFGR_SW_PLL; - 153 .loc 1 154 0 - 154 00d8 5A68 ldr r2, [r3, #4] - 155 00da 42F00202 orr r2, r2, #2 - 156 00de 5A60 str r2, [r3, #4] - 155:main.c **** /* wait till PLL is used as system clock source */ - 156:main.c **** while ((RCC->CFGR & (blt_int32u)RCC_CFGR_SWS) != (blt_int32u)0x08) - 157 .loc 1 156 0 - 158 00e0 1A46 mov r2, r3 - 159 .L6: - 160 00e2 5368 ldr r3, [r2, #4] - 161 00e4 03F00C03 and r3, r3, #12 - 162 00e8 082B cmp r3, #8 - 163 00ea FAD1 bne .L6 - 157:main.c **** { - 158:main.c **** } - 159:main.c **** #if (BOOT_COM_CAN_ENABLE > 0) - 160:main.c **** /* enable clocks for CAN transmitter and receiver pins (GPIOB and AFIO) */ - 161:main.c **** RCC->APB2ENR |= (blt_int32u)(0x00000008 | 0x00000001); - 162:main.c **** /* configure CAN Rx (GPIOB8) as alternate function input pull-up */ - 163:main.c **** /* first reset the configuration */ - 164:main.c **** GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 0); - 165:main.c **** /* CNF8[1:0] = %10 and MODE8[1:0] = %00 */ - 166:main.c **** GPIOB->CRH |= (blt_int32u)((blt_int32u)0x8 << 0); - 167:main.c **** /* configure CAN Tx (GPIOB9) as alternate function push-pull */ - 168:main.c **** /* first reset the configuration */ - 169:main.c **** GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 4); - 170:main.c **** /* CNF9[1:0] = %10 and MODE9[1:0] = %11 */ - 171:main.c **** GPIOB->CRH |= (blt_int32u)((blt_int32u)0xb << 4); - 172:main.c **** /* remap CAN1 pins to PortB */ - 173:main.c **** AFIO->MAPR &= ~(blt_int32u)((blt_int32u)0x3 << 13); - 174:main.c **** AFIO->MAPR |= (blt_int32u)((blt_int32u)0x2 << 13); - 175:main.c **** /* enable clocks for CAN controller peripheral */ - 176:main.c **** RCC->APB1ENR |= (blt_int32u)0x02000000; - 177:main.c **** #endif - 178:main.c **** #if (BOOT_COM_UART_ENABLE > 0) - 179:main.c **** /* enable clock for USART2 peripheral */ - 180:main.c **** RCC->APB1ENR |= (blt_int32u)0x00020000; - 164 .loc 1 180 0 - 165 00ec 104B ldr r3, .L12+4 - 166 00ee DA69 ldr r2, [r3, #28] - 167 00f0 42F40032 orr r2, r2, #131072 - 168 00f4 DA61 str r2, [r3, #28] - 181:main.c **** /* enable clocks for USART2 transmitter and receiver pins (GPIOA and AFIO) */ - 182:main.c **** RCC->APB2ENR |= (blt_int32u)(0x00000004 | 0x00000001); - 169 .loc 1 182 0 - 170 00f6 9A69 ldr r2, [r3, #24] - 171 00f8 42F00502 orr r2, r2, #5 - 172 00fc 9A61 str r2, [r3, #24] - 183:main.c **** /* configure USART2 Tx (GPIOA2) as alternate function push-pull */ - 184:main.c **** /* first reset the configuration */ - 185:main.c **** GPIOA->CRL &= ~(blt_int32u)((blt_int32u)0xf << 8); - 173 .loc 1 185 0 - 174 00fe A3F58433 sub r3, r3, #67584 - 175 0102 1A68 ldr r2, [r3] - 176 0104 22F47062 bic r2, r2, #3840 - 177 0108 1A60 str r2, [r3] - 186:main.c **** /* CNF2[1:0] = %10 and MODE2[1:0] = %11 */ - 187:main.c **** GPIOA->CRL |= (blt_int32u)((blt_int32u)0xb << 8); - 178 .loc 1 187 0 - 179 010a 1A68 ldr r2, [r3] - 180 010c 42F43062 orr r2, r2, #2816 - 181 0110 1A60 str r2, [r3] - 188:main.c **** /* configure USART2 Rx (GPIOA3) as alternate function input floating */ - 189:main.c **** /* first reset the configuration */ - 190:main.c **** GPIOA->CRL &= ~(blt_int32u)((blt_int32u)0xf << 12); - 182 .loc 1 190 0 - 183 0112 1A68 ldr r2, [r3] - 184 0114 22F47042 bic r2, r2, #61440 - 185 0118 1A60 str r2, [r3] - 191:main.c **** /* CNF2[1:0] = %01 and MODE2[1:0] = %00 */ - 192:main.c **** GPIOA->CRL |= (blt_int32u)((blt_int32u)0x4 << 12); - 186 .loc 1 192 0 - 187 011a 1A68 ldr r2, [r3] - 188 011c 42F48042 orr r2, r2, #16384 - 189 0120 1A60 str r2, [r3] - 190 .LBE5: - 191 .LBE4: - 61:main.c **** - 192 .loc 1 61 0 - 193 0122 FFF7FEFF bl BootInit - 194 .LVL2: - 195 .L7: - 67:main.c **** } - 196 .loc 1 67 0 discriminator 1 - 197 0126 FFF7FEFF bl BootTask - 198 .LVL3: - 68:main.c **** - 199 .loc 1 68 0 discriminator 1 - 200 012a FCE7 b .L7 - 201 .L13: - 202 .align 2 - 203 .L12: - 204 012c 0000FFF8 .word -117506048 - 205 0130 00100240 .word 1073876992 - 206 0134 00000000 .word .LC0 - 207 0138 00200240 .word 1073881088 - 208 .cfi_endproc - 209 .LFE29: - 211 .section .rodata.str1.4,"aMS",%progbits,1 - 212 .align 2 - 213 .LC0: - 214 0000 6D61696E .ascii "main.c\000" - 214 2E6300 - 215 0007 00 .text - 216 .Letext0: - 217 .file 2 "../../../Source/ARMCM3_STM32/types.h" - 218 .file 3 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\mach - 219 .file 4 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\stdi - 220 .file 5 "./lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h" - 221 .file 6 "../../../Source/boot.h" - 222 .file 7 "./lib/CMSIS/CM3/CoreSupport/core_cm3.h" - 223 .file 8 "../../../Source/assert.h" -DEFINED SYMBOLS - *ABS*:00000000 main.c -C:\Users\lwngim1\AppData\Local\Temp\cc1yUehE.s:19 .text.main:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cc1yUehE.s:24 .text.main:00000000 main -C:\Users\lwngim1\AppData\Local\Temp\cc1yUehE.s:204 .text.main:0000012c $d -C:\Users\lwngim1\AppData\Local\Temp\cc1yUehE.s:212 .rodata.str1.4:00000000 $d - .debug_frame:00000010 $d - -UNDEFINED SYMBOLS -AssertFailure -BootInit -BootTask diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/mmc.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/mmc.lst deleted file mode 100644 index 1be649f6..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/mmc.lst +++ /dev/null @@ -1,2694 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "mmc.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.xchg_spi,"ax",%progbits - 19 .align 2 - 20 .thumb - 21 .thumb_func - 23 xchg_spi: - 24 .LFB33: - 25 .file 1 "./lib/fatfs/mmc.c" - 1:./lib/fatfs/mmc.c **** /*------------------------------------------------------------------------/ - 2:./lib/fatfs/mmc.c **** / MMCv3/SDv1/SDv2 (in SPI mode) control module - 3:./lib/fatfs/mmc.c **** /-------------------------------------------------------------------------/ - 4:./lib/fatfs/mmc.c **** / - 5:./lib/fatfs/mmc.c **** / Copyright (C) 2013, ChaN, all right reserved. - 6:./lib/fatfs/mmc.c **** / - 7:./lib/fatfs/mmc.c **** / * This software is a free software and there is NO WARRANTY. - 8:./lib/fatfs/mmc.c **** / * No restriction on use. You can use, modify and redistribute it for - 9:./lib/fatfs/mmc.c **** / personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. - 10:./lib/fatfs/mmc.c **** / * Redistributions of source code must retain the above copyright notice. - 11:./lib/fatfs/mmc.c **** / - 12:./lib/fatfs/mmc.c **** /-------------------------------------------------------------------------*/ - 13:./lib/fatfs/mmc.c **** - 14:./lib/fatfs/mmc.c **** - 15:./lib/fatfs/mmc.c **** /* - 16:./lib/fatfs/mmc.c **** * This file was modified from a sample available from the FatFs - 17:./lib/fatfs/mmc.c **** * web site. It was modified to work with a Olimex STM32-P103 - 18:./lib/fatfs/mmc.c **** * evaluation board. - 19:./lib/fatfs/mmc.c **** * - 20:./lib/fatfs/mmc.c **** */ - 21:./lib/fatfs/mmc.c **** #include "diskio.h" - 22:./lib/fatfs/mmc.c **** #include "stm32f10x.h" /* STM32 registers */ - 23:./lib/fatfs/mmc.c **** #include "stm32f10x_conf.h" /* STM32 peripheral drivers */ - 24:./lib/fatfs/mmc.c **** #include "boot.h" - 25:./lib/fatfs/mmc.c **** - 26:./lib/fatfs/mmc.c **** - 27:./lib/fatfs/mmc.c **** - 28:./lib/fatfs/mmc.c **** /*-------------------------------------------------------------------------- - 29:./lib/fatfs/mmc.c **** - 30:./lib/fatfs/mmc.c **** Module Private Functions - 31:./lib/fatfs/mmc.c **** - 32:./lib/fatfs/mmc.c **** ---------------------------------------------------------------------------*/ - 33:./lib/fatfs/mmc.c **** - 34:./lib/fatfs/mmc.c **** /* Definitions for MMC/SDC command */ - 35:./lib/fatfs/mmc.c **** #define CMD0 (0) /* GO_IDLE_STATE */ - 36:./lib/fatfs/mmc.c **** #define CMD1 (1) /* SEND_OP_COND */ - 37:./lib/fatfs/mmc.c **** #define ACMD41 (41|0x80) /* SEND_OP_COND (SDC) */ - 38:./lib/fatfs/mmc.c **** #define CMD8 (8) /* SEND_IF_COND */ - 39:./lib/fatfs/mmc.c **** #define CMD9 (9) /* SEND_CSD */ - 40:./lib/fatfs/mmc.c **** #define CMD10 (10) /* SEND_CID */ - 41:./lib/fatfs/mmc.c **** #define CMD12 (12) /* STOP_TRANSMISSION */ - 42:./lib/fatfs/mmc.c **** #define ACMD13 (13|0x80) /* SD_STATUS (SDC) */ - 43:./lib/fatfs/mmc.c **** #define CMD16 (16) /* SET_BLOCKLEN */ - 44:./lib/fatfs/mmc.c **** #define CMD17 (17) /* READ_SINGLE_BLOCK */ - 45:./lib/fatfs/mmc.c **** #define CMD18 (18) /* READ_MULTIPLE_BLOCK */ - 46:./lib/fatfs/mmc.c **** #define CMD23 (23) /* SET_BLOCK_COUNT */ - 47:./lib/fatfs/mmc.c **** #define ACMD23 (23|0x80) /* SET_WR_BLK_ERASE_COUNT (SDC) */ - 48:./lib/fatfs/mmc.c **** #define CMD24 (24) /* WRITE_BLOCK */ - 49:./lib/fatfs/mmc.c **** #define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */ - 50:./lib/fatfs/mmc.c **** #define CMD41 (41) /* SEND_OP_COND (ACMD) */ - 51:./lib/fatfs/mmc.c **** #define CMD55 (55) /* APP_CMD */ - 52:./lib/fatfs/mmc.c **** #define CMD58 (58) /* READ_OCR */ - 53:./lib/fatfs/mmc.c **** - 54:./lib/fatfs/mmc.c **** - 55:./lib/fatfs/mmc.c **** /* Control signals (Platform dependent) */ - 56:./lib/fatfs/mmc.c **** #define CS_LOW() GPIO_ResetBits(GPIOB, GPIO_Pin_12) /* MMC CS = L */ - 57:./lib/fatfs/mmc.c **** #define CS_HIGH() GPIO_SetBits(GPIOB, GPIO_Pin_12) /* MMC CS = H */ - 58:./lib/fatfs/mmc.c **** - 59:./lib/fatfs/mmc.c **** - 60:./lib/fatfs/mmc.c **** - 61:./lib/fatfs/mmc.c **** #define FCLK_SLOW() /* Set slow clock (100k-400k) */ - 62:./lib/fatfs/mmc.c **** #define FCLK_FAST() set_max_speed() /* Set fast clock (depends on the CSD) */ - 63:./lib/fatfs/mmc.c **** - 64:./lib/fatfs/mmc.c **** static volatile - 65:./lib/fatfs/mmc.c **** DSTATUS Stat = STA_NOINIT; /* Disk status */ - 66:./lib/fatfs/mmc.c **** - 67:./lib/fatfs/mmc.c **** static - 68:./lib/fatfs/mmc.c **** UINT CardType; - 69:./lib/fatfs/mmc.c **** - 70:./lib/fatfs/mmc.c **** - 71:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 72:./lib/fatfs/mmc.c **** /* Send 80 or so clock transitions with CS and DI held high. This is */ - 73:./lib/fatfs/mmc.c **** /* required after card power up to get it into SPI mode */ - 74:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 75:./lib/fatfs/mmc.c **** static - 76:./lib/fatfs/mmc.c **** void send_initial_clock_train(void) - 77:./lib/fatfs/mmc.c **** { - 78:./lib/fatfs/mmc.c **** GPIO_InitTypeDef GPIO_InitStructure; - 79:./lib/fatfs/mmc.c **** unsigned int i; - 80:./lib/fatfs/mmc.c **** - 81:./lib/fatfs/mmc.c **** /* Ensure CS is held high. */ - 82:./lib/fatfs/mmc.c **** CS_HIGH(); - 83:./lib/fatfs/mmc.c **** - 84:./lib/fatfs/mmc.c **** /* Switch the SSI TX line to a GPIO and drive it high too. */ - 85:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; - 86:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - 87:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - 88:./lib/fatfs/mmc.c **** GPIO_Init(GPIOB, &GPIO_InitStructure); - 89:./lib/fatfs/mmc.c **** GPIO_SetBits(GPIOB, GPIO_Pin_15); - 90:./lib/fatfs/mmc.c **** - 91:./lib/fatfs/mmc.c **** /* Send 10 bytes over the SSI. This causes the clock to wiggle the */ - 92:./lib/fatfs/mmc.c **** /* required number of times. */ - 93:./lib/fatfs/mmc.c **** for(i = 0 ; i < 10 ; i++) - 94:./lib/fatfs/mmc.c **** { - 95:./lib/fatfs/mmc.c **** /* Loop while DR register in not empty */ - 96:./lib/fatfs/mmc.c **** while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET) { ; } - 97:./lib/fatfs/mmc.c **** - 98:./lib/fatfs/mmc.c **** /* Send byte through the SPI peripheral */ - 99:./lib/fatfs/mmc.c **** SPI_I2S_SendData(SPI2, 0xff); - 100:./lib/fatfs/mmc.c **** - 101:./lib/fatfs/mmc.c **** /* Wait to receive a byte */ - 102:./lib/fatfs/mmc.c **** while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET) { ; } - 103:./lib/fatfs/mmc.c **** } - 104:./lib/fatfs/mmc.c **** - 105:./lib/fatfs/mmc.c **** /* Revert to hardware control of the SSI TX line. */ - 106:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; - 107:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - 108:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - 109:./lib/fatfs/mmc.c **** GPIO_Init(GPIOB, &GPIO_InitStructure); - 110:./lib/fatfs/mmc.c **** } - 111:./lib/fatfs/mmc.c **** - 112:./lib/fatfs/mmc.c **** - 113:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 114:./lib/fatfs/mmc.c **** /* Power Control (Platform dependent) */ - 115:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 116:./lib/fatfs/mmc.c **** /* When the target system does not support socket power control, there */ - 117:./lib/fatfs/mmc.c **** /* is nothing to do in these functions. */ - 118:./lib/fatfs/mmc.c **** - 119:./lib/fatfs/mmc.c **** static - 120:./lib/fatfs/mmc.c **** void power_on (void) - 121:./lib/fatfs/mmc.c **** { - 122:./lib/fatfs/mmc.c **** SPI_InitTypeDef SPI_InitStructure; - 123:./lib/fatfs/mmc.c **** GPIO_InitTypeDef GPIO_InitStructure; - 124:./lib/fatfs/mmc.c **** - 125:./lib/fatfs/mmc.c **** /* - 126:./lib/fatfs/mmc.c **** * This doesn't really turn the power on, but initializes the - 127:./lib/fatfs/mmc.c **** * SSI port and pins needed to talk to the card. - 128:./lib/fatfs/mmc.c **** */ - 129:./lib/fatfs/mmc.c **** - 130:./lib/fatfs/mmc.c **** /* Enable GPIO clock for CS */ - 131:./lib/fatfs/mmc.c **** RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); - 132:./lib/fatfs/mmc.c **** /* Enable SPI clock, SPI2: APB1 */ - 133:./lib/fatfs/mmc.c **** RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); - 134:./lib/fatfs/mmc.c **** /* Configure I/O for Flash Chip select (PB12) */ - 135:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; - 136:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - 137:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - 138:./lib/fatfs/mmc.c **** GPIO_Init(GPIOB, &GPIO_InitStructure); - 139:./lib/fatfs/mmc.c **** - 140:./lib/fatfs/mmc.c **** /* De-select the Card: Chip Select high */ - 141:./lib/fatfs/mmc.c **** GPIO_SetBits(GPIOB, GPIO_Pin_12); - 142:./lib/fatfs/mmc.c **** - 143:./lib/fatfs/mmc.c **** /* Configure SPI pins: SCK (PB13) and MOSI (PB15) with default alternate function (not re-mapped) - 144:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_15; - 145:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - 146:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - 147:./lib/fatfs/mmc.c **** GPIO_Init(GPIOB, &GPIO_InitStructure); - 148:./lib/fatfs/mmc.c **** /* Configure MISO (PB14) as Input with internal pull-up */ - 149:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14; - 150:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - 151:./lib/fatfs/mmc.c **** GPIO_Init(GPIOB, &GPIO_InitStructure); - 152:./lib/fatfs/mmc.c **** - 153:./lib/fatfs/mmc.c **** /* SPI configuration */ - 154:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - 155:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - 156:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - 157:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; - 158:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; - 159:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - 160:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256; // 72000kHz/256=281kHz < 400 - 161:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - 162:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_CRCPolynomial = 7; - 163:./lib/fatfs/mmc.c **** - 164:./lib/fatfs/mmc.c **** SPI_Init(SPI2, &SPI_InitStructure); - 165:./lib/fatfs/mmc.c **** SPI_CalculateCRC(SPI2, DISABLE); - 166:./lib/fatfs/mmc.c **** SPI_Cmd(SPI2, ENABLE); - 167:./lib/fatfs/mmc.c **** - 168:./lib/fatfs/mmc.c **** /* Set DI and CS high and apply more than 74 pulses to SCLK for the card */ - 169:./lib/fatfs/mmc.c **** /* to be able to accept a native command. */ - 170:./lib/fatfs/mmc.c **** send_initial_clock_train(); - 171:./lib/fatfs/mmc.c **** - 172:./lib/fatfs/mmc.c **** } - 173:./lib/fatfs/mmc.c **** // set the SSI speed to the max setting - 174:./lib/fatfs/mmc.c **** static - 175:./lib/fatfs/mmc.c **** void set_max_speed(void) - 176:./lib/fatfs/mmc.c **** { - 177:./lib/fatfs/mmc.c **** SPI_InitTypeDef SPI_InitStructure; - 178:./lib/fatfs/mmc.c **** - 179:./lib/fatfs/mmc.c **** /* Disable the SPI system */ - 180:./lib/fatfs/mmc.c **** SPI_Cmd(SPI2, DISABLE); - 181:./lib/fatfs/mmc.c **** - 182:./lib/fatfs/mmc.c **** /* MMC/SDC can work at the clock frequency up to 20/25MHz so pick a speed close to - 183:./lib/fatfs/mmc.c **** * this but not higher - 184:./lib/fatfs/mmc.c **** */ - 185:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - 186:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - 187:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - 188:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; - 189:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; - 190:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - 191:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; // 72MHz/4=18MHz < 20MHz - 192:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - 193:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_CRCPolynomial = 7; - 194:./lib/fatfs/mmc.c **** SPI_Init(SPI2, &SPI_InitStructure); - 195:./lib/fatfs/mmc.c **** SPI_CalculateCRC(SPI2, DISABLE); - 196:./lib/fatfs/mmc.c **** - 197:./lib/fatfs/mmc.c **** /* Enable the SPI system */ - 198:./lib/fatfs/mmc.c **** SPI_Cmd(SPI2, ENABLE); - 199:./lib/fatfs/mmc.c **** } - 200:./lib/fatfs/mmc.c **** - 201:./lib/fatfs/mmc.c **** static - 202:./lib/fatfs/mmc.c **** void power_off (void) - 203:./lib/fatfs/mmc.c **** { - 204:./lib/fatfs/mmc.c **** Stat |= STA_NOINIT; /* Force uninitialized */ - 205:./lib/fatfs/mmc.c **** } - 206:./lib/fatfs/mmc.c **** - 207:./lib/fatfs/mmc.c **** - 208:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 209:./lib/fatfs/mmc.c **** /* Transmit/Receive data to/from MMC via SPI (Platform dependent) */ - 210:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 211:./lib/fatfs/mmc.c **** - 212:./lib/fatfs/mmc.c **** static - 213:./lib/fatfs/mmc.c **** BYTE xchg_spi (BYTE dat) - 214:./lib/fatfs/mmc.c **** { - 26 .loc 1 214 0 - 27 .cfi_startproc - 28 @ args = 0, pretend = 0, frame = 0 - 29 @ frame_needed = 0, uses_anonymous_args = 0 - 30 .LVL0: - 31 0000 38B5 push {r3, r4, r5, lr} - 32 .cfi_def_cfa_offset 16 - 33 .cfi_offset 3, -16 - 34 .cfi_offset 4, -12 - 35 .cfi_offset 5, -8 - 36 .cfi_offset 14, -4 - 215:./lib/fatfs/mmc.c **** /* Send byte through the SPI peripheral */ - 216:./lib/fatfs/mmc.c **** SPI_I2S_SendData(SPI2, dat); - 37 .loc 1 216 0 - 38 0002 0146 mov r1, r0 - 39 0004 0748 ldr r0, .L5 - 40 .LVL1: - 41 0006 FFF7FEFF bl SPI_I2S_SendData - 42 .LVL2: - 217:./lib/fatfs/mmc.c **** - 218:./lib/fatfs/mmc.c **** /* Wait to receive a byte */ - 219:./lib/fatfs/mmc.c **** while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET) { ; } - 43 .loc 1 219 0 - 44 000a 064D ldr r5, .L5 - 45 000c 0124 movs r4, #1 - 46 .L2: - 47 .loc 1 219 0 is_stmt 0 discriminator 1 - 48 000e 2846 mov r0, r5 - 49 0010 2146 mov r1, r4 - 50 0012 FFF7FEFF bl SPI_I2S_GetFlagStatus - 51 .LVL3: - 52 0016 0028 cmp r0, #0 - 53 0018 F9D0 beq .L2 - 220:./lib/fatfs/mmc.c **** - 221:./lib/fatfs/mmc.c **** /* Return the byte read from the SPI bus */ - 222:./lib/fatfs/mmc.c **** return (BYTE)SPI_I2S_ReceiveData(SPI2); - 54 .loc 1 222 0 is_stmt 1 - 55 001a 0248 ldr r0, .L5 - 56 001c FFF7FEFF bl SPI_I2S_ReceiveData - 57 .LVL4: - 223:./lib/fatfs/mmc.c **** } - 58 .loc 1 223 0 - 59 0020 C0B2 uxtb r0, r0 - 60 0022 38BD pop {r3, r4, r5, pc} - 61 .L6: - 62 .align 2 - 63 .L5: - 64 0024 00380040 .word 1073756160 - 65 .cfi_endproc - 66 .LFE33: - 68 .section .text.wait_ready,"ax",%progbits - 69 .align 2 - 70 .thumb - 71 .thumb_func - 73 wait_ready: - 74 .LFB35: - 224:./lib/fatfs/mmc.c **** - 225:./lib/fatfs/mmc.c **** static - 226:./lib/fatfs/mmc.c **** void rcvr_spi_m (BYTE *dst) - 227:./lib/fatfs/mmc.c **** { - 228:./lib/fatfs/mmc.c **** *dst = xchg_spi(0xFF); - 229:./lib/fatfs/mmc.c **** } - 230:./lib/fatfs/mmc.c **** - 231:./lib/fatfs/mmc.c **** - 232:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 233:./lib/fatfs/mmc.c **** /* Wait for card ready */ - 234:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 235:./lib/fatfs/mmc.c **** - 236:./lib/fatfs/mmc.c **** static - 237:./lib/fatfs/mmc.c **** int wait_ready (void) - 238:./lib/fatfs/mmc.c **** { - 75 .loc 1 238 0 - 76 .cfi_startproc - 77 @ args = 0, pretend = 0, frame = 0 - 78 @ frame_needed = 0, uses_anonymous_args = 0 - 79 0000 70B5 push {r4, r5, r6, lr} - 80 .cfi_def_cfa_offset 16 - 81 .cfi_offset 4, -16 - 82 .cfi_offset 5, -12 - 83 .cfi_offset 6, -8 - 84 .cfi_offset 14, -4 - 239:./lib/fatfs/mmc.c **** BYTE d; - 240:./lib/fatfs/mmc.c **** ULONG timeOutTime; - 241:./lib/fatfs/mmc.c **** - 242:./lib/fatfs/mmc.c **** /* set timeout for 500 ms from now */ - 243:./lib/fatfs/mmc.c **** timeOutTime = TimerGet() + 500; - 85 .loc 1 243 0 - 86 0002 FFF7FEFF bl TimerGet - 87 .LVL5: - 88 0006 00F5FA76 add r6, r0, #500 - 89 .LVL6: - 244:./lib/fatfs/mmc.c **** - 245:./lib/fatfs/mmc.c **** do { - 246:./lib/fatfs/mmc.c **** d = xchg_spi(0xFF); - 90 .loc 1 246 0 - 91 000a FF25 movs r5, #255 - 92 .L9: - 93 .loc 1 246 0 is_stmt 0 discriminator 2 - 94 000c 2846 mov r0, r5 - 95 000e FFF7FEFF bl xchg_spi - 96 .LVL7: - 97 0012 0446 mov r4, r0 - 98 .LVL8: - 247:./lib/fatfs/mmc.c **** } while ((d != 0xFF) && (TimerGet() < timeOutTime)); - 99 .loc 1 247 0 is_stmt 1 discriminator 2 - 100 0014 FF28 cmp r0, #255 - 101 0016 03D0 beq .L8 - 102 .loc 1 247 0 is_stmt 0 discriminator 1 - 103 0018 FFF7FEFF bl TimerGet - 104 .LVL9: - 105 001c 8642 cmp r6, r0 - 106 001e F5D8 bhi .L9 - 107 .L8: - 248:./lib/fatfs/mmc.c **** - 249:./lib/fatfs/mmc.c **** return (d == 0xFF) ? 1 : 0; - 250:./lib/fatfs/mmc.c **** } - 108 .loc 1 250 0 is_stmt 1 - 109 0020 FF2C cmp r4, #255 - 110 0022 14BF ite ne - 111 0024 0020 movne r0, #0 - 112 0026 0120 moveq r0, #1 - 113 0028 70BD pop {r4, r5, r6, pc} - 114 .cfi_endproc - 115 .LFE35: - 117 002a 00BF .section .text.deselect,"ax",%progbits - 118 .align 2 - 119 .thumb - 120 .thumb_func - 122 deselect: - 123 .LFB36: - 251:./lib/fatfs/mmc.c **** - 252:./lib/fatfs/mmc.c **** - 253:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 254:./lib/fatfs/mmc.c **** /* Deselect the card and release SPI bus */ - 255:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 256:./lib/fatfs/mmc.c **** - 257:./lib/fatfs/mmc.c **** static - 258:./lib/fatfs/mmc.c **** void deselect (void) - 259:./lib/fatfs/mmc.c **** { - 124 .loc 1 259 0 - 125 .cfi_startproc - 126 @ args = 0, pretend = 0, frame = 0 - 127 @ frame_needed = 0, uses_anonymous_args = 0 - 128 0000 08B5 push {r3, lr} - 129 .cfi_def_cfa_offset 8 - 130 .cfi_offset 3, -8 - 131 .cfi_offset 14, -4 - 260:./lib/fatfs/mmc.c **** CS_HIGH(); - 132 .loc 1 260 0 - 133 0002 0448 ldr r0, .L14 - 134 0004 4FF48051 mov r1, #4096 - 135 0008 FFF7FEFF bl GPIO_SetBits - 136 .LVL10: - 261:./lib/fatfs/mmc.c **** xchg_spi(0xFF); /* Dummy clock (force DO hi-z for multiple slave SPI) */ - 137 .loc 1 261 0 - 138 000c FF20 movs r0, #255 - 139 000e FFF7FEFF bl xchg_spi - 140 .LVL11: - 141 0012 08BD pop {r3, pc} - 142 .L15: - 143 .align 2 - 144 .L14: - 145 0014 000C0140 .word 1073810432 - 146 .cfi_endproc - 147 .LFE36: - 149 .section .text.select,"ax",%progbits - 150 .align 2 - 151 .thumb - 152 .thumb_func - 154 select: - 155 .LFB37: - 262:./lib/fatfs/mmc.c **** } - 263:./lib/fatfs/mmc.c **** - 264:./lib/fatfs/mmc.c **** - 265:./lib/fatfs/mmc.c **** - 266:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 267:./lib/fatfs/mmc.c **** /* Select the card and wait ready */ - 268:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 269:./lib/fatfs/mmc.c **** - 270:./lib/fatfs/mmc.c **** static - 271:./lib/fatfs/mmc.c **** int select (void) /* 1:Successful, 0:Timeout */ - 272:./lib/fatfs/mmc.c **** { - 156 .loc 1 272 0 - 157 .cfi_startproc - 158 @ args = 0, pretend = 0, frame = 0 - 159 @ frame_needed = 0, uses_anonymous_args = 0 - 160 0000 10B5 push {r4, lr} - 161 .cfi_def_cfa_offset 8 - 162 .cfi_offset 4, -8 - 163 .cfi_offset 14, -4 - 273:./lib/fatfs/mmc.c **** CS_LOW(); - 164 .loc 1 273 0 - 165 0002 0948 ldr r0, .L20 - 166 0004 4FF48051 mov r1, #4096 - 167 0008 FFF7FEFF bl GPIO_ResetBits - 168 .LVL12: - 274:./lib/fatfs/mmc.c **** xchg_spi(0xFF); /* Dummy clock (force DO enabled) */ - 169 .loc 1 274 0 - 170 000c FF20 movs r0, #255 - 171 000e FFF7FEFF bl xchg_spi - 172 .LVL13: - 275:./lib/fatfs/mmc.c **** - 276:./lib/fatfs/mmc.c **** if (wait_ready()) return 1; /* OK */ - 173 .loc 1 276 0 - 174 0012 FFF7FEFF bl wait_ready - 175 .LVL14: - 176 0016 18B9 cbnz r0, .L18 - 177 0018 0446 mov r4, r0 - 277:./lib/fatfs/mmc.c **** deselect(); - 178 .loc 1 277 0 - 179 001a FFF7FEFF bl deselect - 180 .LVL15: - 278:./lib/fatfs/mmc.c **** return 0; /* Timeout */ - 181 .loc 1 278 0 - 182 001e 00E0 b .L17 - 183 .L18: - 276:./lib/fatfs/mmc.c **** deselect(); - 184 .loc 1 276 0 - 185 0020 0124 movs r4, #1 - 186 .L17: - 279:./lib/fatfs/mmc.c **** } - 187 .loc 1 279 0 - 188 0022 2046 mov r0, r4 - 189 0024 10BD pop {r4, pc} - 190 .L21: - 191 0026 00BF .align 2 - 192 .L20: - 193 0028 000C0140 .word 1073810432 - 194 .cfi_endproc - 195 .LFE37: - 197 .section .text.send_cmd,"ax",%progbits - 198 .align 2 - 199 .thumb - 200 .thumb_func - 202 send_cmd: - 203 .LFB40: - 280:./lib/fatfs/mmc.c **** - 281:./lib/fatfs/mmc.c **** - 282:./lib/fatfs/mmc.c **** - 283:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 284:./lib/fatfs/mmc.c **** /* Receive a data packet from MMC */ - 285:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 286:./lib/fatfs/mmc.c **** - 287:./lib/fatfs/mmc.c **** static - 288:./lib/fatfs/mmc.c **** int rcvr_datablock ( /* 1:OK, 0:Failed */ - 289:./lib/fatfs/mmc.c **** BYTE *buff, /* Data buffer to store received data */ - 290:./lib/fatfs/mmc.c **** UINT btr /* Byte count (must be multiple of 4) */ - 291:./lib/fatfs/mmc.c **** ) - 292:./lib/fatfs/mmc.c **** { - 293:./lib/fatfs/mmc.c **** BYTE token; - 294:./lib/fatfs/mmc.c **** ULONG timeOutTime; - 295:./lib/fatfs/mmc.c **** - 296:./lib/fatfs/mmc.c **** /* set timeout for 100 ms from now */ - 297:./lib/fatfs/mmc.c **** timeOutTime = TimerGet() + 100; - 298:./lib/fatfs/mmc.c **** - 299:./lib/fatfs/mmc.c **** do { /* Wait for data packet in timeout of 100ms */ - 300:./lib/fatfs/mmc.c **** token = xchg_spi(0xFF); - 301:./lib/fatfs/mmc.c **** } while ((token == 0xFF) && (TimerGet() < timeOutTime)); - 302:./lib/fatfs/mmc.c **** - 303:./lib/fatfs/mmc.c **** if(token != 0xFE) return 0; /* If not valid data token, retutn with error */ - 304:./lib/fatfs/mmc.c **** - 305:./lib/fatfs/mmc.c **** do { /* Receive the data block into buffer */ - 306:./lib/fatfs/mmc.c **** rcvr_spi_m(buff++); - 307:./lib/fatfs/mmc.c **** rcvr_spi_m(buff++); - 308:./lib/fatfs/mmc.c **** } while (btr -= 2); - 309:./lib/fatfs/mmc.c **** xchg_spi(0xFF); /* Discard CRC */ - 310:./lib/fatfs/mmc.c **** xchg_spi(0xFF); - 311:./lib/fatfs/mmc.c **** - 312:./lib/fatfs/mmc.c **** return 1; /* Return with success */ - 313:./lib/fatfs/mmc.c **** } - 314:./lib/fatfs/mmc.c **** - 315:./lib/fatfs/mmc.c **** - 316:./lib/fatfs/mmc.c **** - 317:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 318:./lib/fatfs/mmc.c **** /* Send a data packet to MMC */ - 319:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 320:./lib/fatfs/mmc.c **** - 321:./lib/fatfs/mmc.c **** #if _USE_WRITE - 322:./lib/fatfs/mmc.c **** static - 323:./lib/fatfs/mmc.c **** int xmit_datablock ( /* 1:OK, 0:Failed */ - 324:./lib/fatfs/mmc.c **** const BYTE *buff, /* 512 byte data block to be transmitted */ - 325:./lib/fatfs/mmc.c **** BYTE token /* Data token */ - 326:./lib/fatfs/mmc.c **** ) - 327:./lib/fatfs/mmc.c **** { - 328:./lib/fatfs/mmc.c **** BYTE resp; - 329:./lib/fatfs/mmc.c **** UINT wc; - 330:./lib/fatfs/mmc.c **** - 331:./lib/fatfs/mmc.c **** - 332:./lib/fatfs/mmc.c **** if (!wait_ready()) return 0; - 333:./lib/fatfs/mmc.c **** - 334:./lib/fatfs/mmc.c **** xchg_spi(token); /* Xmit a token */ - 335:./lib/fatfs/mmc.c **** if (token != 0xFD) { /* Not StopTran token */ - 336:./lib/fatfs/mmc.c **** wc = 512; - 337:./lib/fatfs/mmc.c **** do { /* Xmit the 512 byte data block to MMC */ - 338:./lib/fatfs/mmc.c **** xchg_spi(*buff++); - 339:./lib/fatfs/mmc.c **** xchg_spi(*buff++); - 340:./lib/fatfs/mmc.c **** } while (wc -= 2); - 341:./lib/fatfs/mmc.c **** xchg_spi(0xFF); /* CRC (Dummy) */ - 342:./lib/fatfs/mmc.c **** xchg_spi(0xFF); - 343:./lib/fatfs/mmc.c **** resp = xchg_spi(0xFF); /* Receive a data response */ - 344:./lib/fatfs/mmc.c **** if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ - 345:./lib/fatfs/mmc.c **** return 0; - 346:./lib/fatfs/mmc.c **** } - 347:./lib/fatfs/mmc.c **** - 348:./lib/fatfs/mmc.c **** return 1; - 349:./lib/fatfs/mmc.c **** } - 350:./lib/fatfs/mmc.c **** #endif - 351:./lib/fatfs/mmc.c **** - 352:./lib/fatfs/mmc.c **** - 353:./lib/fatfs/mmc.c **** - 354:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 355:./lib/fatfs/mmc.c **** /* Send a command packet to MMC */ - 356:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 357:./lib/fatfs/mmc.c **** - 358:./lib/fatfs/mmc.c **** static - 359:./lib/fatfs/mmc.c **** BYTE send_cmd ( - 360:./lib/fatfs/mmc.c **** BYTE cmd, /* Command byte */ - 361:./lib/fatfs/mmc.c **** DWORD arg /* Argument */ - 362:./lib/fatfs/mmc.c **** ) - 363:./lib/fatfs/mmc.c **** { - 204 .loc 1 363 0 - 205 .cfi_startproc - 206 @ args = 0, pretend = 0, frame = 0 - 207 @ frame_needed = 0, uses_anonymous_args = 0 - 208 .LVL16: - 209 0000 38B5 push {r3, r4, r5, lr} - 210 .cfi_def_cfa_offset 16 - 211 .cfi_offset 3, -16 - 212 .cfi_offset 4, -12 - 213 .cfi_offset 5, -8 - 214 .cfi_offset 14, -4 - 215 0002 0446 mov r4, r0 - 216 0004 0D46 mov r5, r1 - 364:./lib/fatfs/mmc.c **** BYTE n, res; - 365:./lib/fatfs/mmc.c **** - 366:./lib/fatfs/mmc.c **** - 367:./lib/fatfs/mmc.c **** if (cmd & 0x80) { /* ACMD is the command sequense of CMD55-CMD */ - 217 .loc 1 367 0 - 218 0006 10F0800F tst r0, #128 - 219 000a 07D0 beq .L23 - 220 .LVL17: - 368:./lib/fatfs/mmc.c **** cmd &= 0x7F; - 369:./lib/fatfs/mmc.c **** res = send_cmd(CMD55, 0); - 221 .loc 1 369 0 - 222 000c 3720 movs r0, #55 - 223 000e 0021 movs r1, #0 - 224 .LVL18: - 225 0010 FFF7F6FF bl send_cmd - 226 .LVL19: - 370:./lib/fatfs/mmc.c **** if (res > 1) return res; - 227 .loc 1 370 0 - 228 0014 0128 cmp r0, #1 - 229 0016 3AD8 bhi .L33 - 368:./lib/fatfs/mmc.c **** cmd &= 0x7F; - 230 .loc 1 368 0 - 231 0018 04F07F04 and r4, r4, #127 - 232 .LVL20: - 233 .L23: - 371:./lib/fatfs/mmc.c **** } - 372:./lib/fatfs/mmc.c **** - 373:./lib/fatfs/mmc.c **** /* Select the card and wait for ready */ - 374:./lib/fatfs/mmc.c **** deselect(); - 234 .loc 1 374 0 - 235 001c FFF7FEFF bl deselect - 236 .LVL21: - 375:./lib/fatfs/mmc.c **** if (!select()) return 0xFF; - 237 .loc 1 375 0 - 238 0020 FFF7FEFF bl select - 239 .LVL22: - 240 0024 48B3 cbz r0, .L30 - 376:./lib/fatfs/mmc.c **** - 377:./lib/fatfs/mmc.c **** /* Send command packet */ - 378:./lib/fatfs/mmc.c **** xchg_spi(0x40 | cmd); /* Start + Command index */ - 241 .loc 1 378 0 - 242 0026 44F04000 orr r0, r4, #64 - 243 002a FFF7FEFF bl xchg_spi - 244 .LVL23: - 379:./lib/fatfs/mmc.c **** xchg_spi((BYTE)(arg >> 24)); /* Argument[31..24] */ - 245 .loc 1 379 0 - 246 002e 280E lsrs r0, r5, #24 - 247 0030 FFF7FEFF bl xchg_spi - 248 .LVL24: - 380:./lib/fatfs/mmc.c **** xchg_spi((BYTE)(arg >> 16)); /* Argument[23..16] */ - 249 .loc 1 380 0 - 250 0034 C5F30740 ubfx r0, r5, #16, #8 - 251 0038 FFF7FEFF bl xchg_spi - 252 .LVL25: - 381:./lib/fatfs/mmc.c **** xchg_spi((BYTE)(arg >> 8)); /* Argument[15..8] */ - 253 .loc 1 381 0 - 254 003c C5F30720 ubfx r0, r5, #8, #8 - 255 0040 FFF7FEFF bl xchg_spi - 256 .LVL26: - 382:./lib/fatfs/mmc.c **** xchg_spi((BYTE)arg); /* Argument[7..0] */ - 257 .loc 1 382 0 - 258 0044 E8B2 uxtb r0, r5 - 259 0046 FFF7FEFF bl xchg_spi - 260 .LVL27: - 383:./lib/fatfs/mmc.c **** n = 0x01; /* Dummy CRC + Stop */ - 384:./lib/fatfs/mmc.c **** if (cmd == CMD0) n = 0x95; /* Valid CRC for CMD0(0) + Stop */ - 261 .loc 1 384 0 - 262 004a E4B1 cbz r4, .L25 - 385:./lib/fatfs/mmc.c **** if (cmd == CMD8) n = 0x87; /* Valid CRC for CMD8(0x1AA) + Stop */ - 263 .loc 1 385 0 - 264 004c 082C cmp r4, #8 - 265 004e 16D0 beq .L26 - 386:./lib/fatfs/mmc.c **** xchg_spi(n); - 266 .loc 1 386 0 - 267 0050 0120 movs r0, #1 - 268 0052 FFF7FEFF bl xchg_spi - 269 .LVL28: - 387:./lib/fatfs/mmc.c **** - 388:./lib/fatfs/mmc.c **** /* Receive command response */ - 389:./lib/fatfs/mmc.c **** if (cmd == CMD12) xchg_spi(0xFF); /* Skip a stuff byte on stop to read */ - 270 .loc 1 389 0 - 271 0056 0C2C cmp r4, #12 - 272 0058 02D1 bne .L27 - 273 .loc 1 389 0 is_stmt 0 discriminator 1 - 274 005a FF20 movs r0, #255 - 275 005c FFF7FEFF bl xchg_spi - 276 .LVL29: - 277 .L27: - 363:./lib/fatfs/mmc.c **** BYTE n, res; - 278 .loc 1 363 0 is_stmt 1 discriminator 2 - 279 0060 0A24 movs r4, #10 - 280 .LVL30: - 390:./lib/fatfs/mmc.c **** n = 10; /* Wait for a valid response in timeout of 10 attempts */ - 391:./lib/fatfs/mmc.c **** do - 392:./lib/fatfs/mmc.c **** res = xchg_spi(0xFF); - 281 .loc 1 392 0 discriminator 2 - 282 0062 FF25 movs r5, #255 - 283 .LVL31: - 284 .L28: - 285 0064 2846 mov r0, r5 - 286 0066 FFF7FEFF bl xchg_spi - 287 .LVL32: - 393:./lib/fatfs/mmc.c **** while ((res & 0x80) && --n); - 288 .loc 1 393 0 discriminator 2 - 289 006a 10F0800F tst r0, #128 - 290 006e 0ED0 beq .L33 - 291 .LVL33: - 292 0070 631E subs r3, r4, #1 - 293 .loc 1 393 0 is_stmt 0 discriminator 1 - 294 0072 13F0FF04 ands r4, r3, #255 - 295 .LVL34: - 296 0076 F5D1 bne .L28 - 297 0078 38BD pop {r3, r4, r5, pc} - 298 .LVL35: - 299 .L30: - 375:./lib/fatfs/mmc.c **** - 300 .loc 1 375 0 is_stmt 1 - 301 007a FF20 movs r0, #255 - 302 007c 38BD pop {r3, r4, r5, pc} - 303 .LVL36: - 304 .L26: - 386:./lib/fatfs/mmc.c **** - 305 .loc 1 386 0 - 306 007e 8720 movs r0, #135 - 307 0080 FFF7FEFF bl xchg_spi - 308 .LVL37: - 309 0084 ECE7 b .L27 - 310 .LVL38: - 311 .L25: - 312 0086 9520 movs r0, #149 - 313 0088 FFF7FEFF bl xchg_spi - 314 .LVL39: - 315 008c E8E7 b .L27 - 316 .LVL40: - 317 .L33: - 394:./lib/fatfs/mmc.c **** - 395:./lib/fatfs/mmc.c **** return res; /* Return with the response value */ - 396:./lib/fatfs/mmc.c **** } - 318 .loc 1 396 0 - 319 008e 38BD pop {r3, r4, r5, pc} - 320 .cfi_endproc - 321 .LFE40: - 323 .section .text.xmit_datablock,"ax",%progbits - 324 .align 2 - 325 .thumb - 326 .thumb_func - 328 xmit_datablock: - 329 .LFB39: - 327:./lib/fatfs/mmc.c **** BYTE resp; - 330 .loc 1 327 0 - 331 .cfi_startproc - 332 @ args = 0, pretend = 0, frame = 0 - 333 @ frame_needed = 0, uses_anonymous_args = 0 - 334 .LVL41: - 335 0000 38B5 push {r3, r4, r5, lr} - 336 .cfi_def_cfa_offset 16 - 337 .cfi_offset 3, -16 - 338 .cfi_offset 4, -12 - 339 .cfi_offset 5, -8 - 340 .cfi_offset 14, -4 - 341 0002 0546 mov r5, r0 - 342 0004 0C46 mov r4, r1 - 332:./lib/fatfs/mmc.c **** - 343 .loc 1 332 0 - 344 0006 FFF7FEFF bl wait_ready - 345 .LVL42: - 346 000a 0346 mov r3, r0 - 347 000c 18B3 cbz r0, .L36 - 334:./lib/fatfs/mmc.c **** if (token != 0xFD) { /* Not StopTran token */ - 348 .loc 1 334 0 - 349 000e 2046 mov r0, r4 - 350 0010 FFF7FEFF bl xchg_spi - 351 .LVL43: - 335:./lib/fatfs/mmc.c **** wc = 512; - 352 .loc 1 335 0 - 353 0014 FD2C cmp r4, #253 - 354 0016 1DD0 beq .L38 - 355 0018 AC1C adds r4, r5, #2 - 356 001a 05F20225 addw r5, r5, #514 - 357 .LVL44: - 358 .L37: - 338:./lib/fatfs/mmc.c **** xchg_spi(*buff++); - 359 .loc 1 338 0 discriminator 1 - 360 001e 14F8020C ldrb r0, [r4, #-2] @ zero_extendqisi2 - 361 0022 FFF7FEFF bl xchg_spi - 362 .LVL45: - 339:./lib/fatfs/mmc.c **** } while (wc -= 2); - 363 .loc 1 339 0 discriminator 1 - 364 0026 14F8010C ldrb r0, [r4, #-1] @ zero_extendqisi2 - 365 002a FFF7FEFF bl xchg_spi - 366 .LVL46: - 367 002e 0234 adds r4, r4, #2 - 368 .LVL47: - 340:./lib/fatfs/mmc.c **** xchg_spi(0xFF); /* CRC (Dummy) */ - 369 .loc 1 340 0 discriminator 1 - 370 0030 AC42 cmp r4, r5 - 371 0032 F4D1 bne .L37 - 341:./lib/fatfs/mmc.c **** xchg_spi(0xFF); - 372 .loc 1 341 0 - 373 0034 FF20 movs r0, #255 - 374 0036 FFF7FEFF bl xchg_spi - 375 .LVL48: - 342:./lib/fatfs/mmc.c **** resp = xchg_spi(0xFF); /* Receive a data response */ - 376 .loc 1 342 0 - 377 003a FF20 movs r0, #255 - 378 003c FFF7FEFF bl xchg_spi - 379 .LVL49: - 343:./lib/fatfs/mmc.c **** if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ - 380 .loc 1 343 0 - 381 0040 FF20 movs r0, #255 - 382 0042 FFF7FEFF bl xchg_spi - 383 .LVL50: - 344:./lib/fatfs/mmc.c **** return 0; - 384 .loc 1 344 0 - 385 0046 00F01F00 and r0, r0, #31 - 386 .LVL51: - 387 004a 0528 cmp r0, #5 - 388 004c 14BF ite ne - 389 004e 0023 movne r3, #0 - 390 0050 0123 moveq r3, #1 - 391 0052 00E0 b .L36 - 392 .LVL52: - 393 .L38: - 348:./lib/fatfs/mmc.c **** } - 394 .loc 1 348 0 - 395 0054 0123 movs r3, #1 - 396 .LVL53: - 397 .L36: - 349:./lib/fatfs/mmc.c **** #endif - 398 .loc 1 349 0 - 399 0056 1846 mov r0, r3 - 400 0058 38BD pop {r3, r4, r5, pc} - 401 .cfi_endproc - 402 .LFE39: - 404 005a 00BF .section .text.rcvr_datablock,"ax",%progbits - 405 .align 2 - 406 .thumb - 407 .thumb_func - 409 rcvr_datablock: - 410 .LFB38: - 292:./lib/fatfs/mmc.c **** BYTE token; - 411 .loc 1 292 0 - 412 .cfi_startproc - 413 @ args = 0, pretend = 0, frame = 0 - 414 @ frame_needed = 0, uses_anonymous_args = 0 - 415 .LVL54: - 416 0000 F8B5 push {r3, r4, r5, r6, r7, lr} - 417 .cfi_def_cfa_offset 24 - 418 .cfi_offset 3, -24 - 419 .cfi_offset 4, -20 - 420 .cfi_offset 5, -16 - 421 .cfi_offset 6, -12 - 422 .cfi_offset 7, -8 - 423 .cfi_offset 14, -4 - 424 0002 0446 mov r4, r0 - 425 0004 0D46 mov r5, r1 - 297:./lib/fatfs/mmc.c **** - 426 .loc 1 297 0 - 427 0006 FFF7FEFF bl TimerGet - 428 .LVL55: - 429 000a 00F16407 add r7, r0, #100 - 430 .LVL56: - 300:./lib/fatfs/mmc.c **** } while ((token == 0xFF) && (TimerGet() < timeOutTime)); - 431 .loc 1 300 0 - 432 000e FF26 movs r6, #255 - 433 .L43: - 300:./lib/fatfs/mmc.c **** } while ((token == 0xFF) && (TimerGet() < timeOutTime)); - 434 .loc 1 300 0 is_stmt 0 discriminator 2 - 435 0010 3046 mov r0, r6 - 436 0012 FFF7FEFF bl xchg_spi - 437 .LVL57: - 301:./lib/fatfs/mmc.c **** - 438 .loc 1 301 0 is_stmt 1 discriminator 2 - 439 0016 FF28 cmp r0, #255 - 440 0018 05D1 bne .L42 - 301:./lib/fatfs/mmc.c **** - 441 .loc 1 301 0 is_stmt 0 discriminator 1 - 442 001a FFF7FEFF bl TimerGet - 443 .LVL58: - 444 001e 8742 cmp r7, r0 - 445 0020 F6D8 bhi .L43 - 303:./lib/fatfs/mmc.c **** - 446 .loc 1 303 0 is_stmt 1 - 447 0022 0020 movs r0, #0 - 448 0024 F8BD pop {r3, r4, r5, r6, r7, pc} - 449 .LVL59: - 450 .L42: - 451 0026 FE28 cmp r0, #254 - 452 0028 16D1 bne .L46 - 453 002a 0234 adds r4, r4, #2 - 454 .LVL60: - 455 .LBB6: - 456 .LBB7: - 228:./lib/fatfs/mmc.c **** } - 457 .loc 1 228 0 - 458 002c FF26 movs r6, #255 - 459 .LVL61: - 460 .L45: - 228:./lib/fatfs/mmc.c **** } - 461 .loc 1 228 0 is_stmt 0 discriminator 1 - 462 002e 3046 mov r0, r6 - 463 0030 FFF7FEFF bl xchg_spi - 464 .LVL62: - 465 0034 04F8020C strb r0, [r4, #-2] - 466 .LVL63: - 467 .LBE7: - 468 .LBE6: - 469 .LBB8: - 470 .LBB9: - 471 0038 3046 mov r0, r6 - 472 003a FFF7FEFF bl xchg_spi - 473 .LVL64: - 474 003e 04F8010C strb r0, [r4, #-1] - 475 .LVL65: - 476 0042 0234 adds r4, r4, #2 - 477 .LVL66: - 478 .LBE9: - 479 .LBE8: - 308:./lib/fatfs/mmc.c **** xchg_spi(0xFF); /* Discard CRC */ - 480 .loc 1 308 0 is_stmt 1 discriminator 1 - 481 0044 023D subs r5, r5, #2 - 482 .LVL67: - 483 0046 F2D1 bne .L45 - 309:./lib/fatfs/mmc.c **** xchg_spi(0xFF); - 484 .loc 1 309 0 - 485 0048 FF20 movs r0, #255 - 486 004a FFF7FEFF bl xchg_spi - 487 .LVL68: - 310:./lib/fatfs/mmc.c **** - 488 .loc 1 310 0 - 489 004e FF20 movs r0, #255 - 490 0050 FFF7FEFF bl xchg_spi - 491 .LVL69: - 312:./lib/fatfs/mmc.c **** } - 492 .loc 1 312 0 - 493 0054 0120 movs r0, #1 - 494 0056 F8BD pop {r3, r4, r5, r6, r7, pc} - 495 .LVL70: - 496 .L46: - 303:./lib/fatfs/mmc.c **** - 497 .loc 1 303 0 - 498 0058 0020 movs r0, #0 - 499 .LVL71: - 313:./lib/fatfs/mmc.c **** - 500 .loc 1 313 0 - 501 005a F8BD pop {r3, r4, r5, r6, r7, pc} - 502 .cfi_endproc - 503 .LFE38: - 505 .section .text.disk_initialize,"ax",%progbits - 506 .align 2 - 507 .global disk_initialize - 508 .thumb - 509 .thumb_func - 511 disk_initialize: - 512 .LFB41: - 397:./lib/fatfs/mmc.c **** - 398:./lib/fatfs/mmc.c **** - 399:./lib/fatfs/mmc.c **** - 400:./lib/fatfs/mmc.c **** /*-------------------------------------------------------------------------- - 401:./lib/fatfs/mmc.c **** - 402:./lib/fatfs/mmc.c **** Public Functions - 403:./lib/fatfs/mmc.c **** - 404:./lib/fatfs/mmc.c **** ---------------------------------------------------------------------------*/ - 405:./lib/fatfs/mmc.c **** - 406:./lib/fatfs/mmc.c **** - 407:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 408:./lib/fatfs/mmc.c **** /* Initialize Disk Drive */ - 409:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 410:./lib/fatfs/mmc.c **** - 411:./lib/fatfs/mmc.c **** DSTATUS disk_initialize ( - 412:./lib/fatfs/mmc.c **** BYTE pdrv /* Physical drive nmuber (0) */ - 413:./lib/fatfs/mmc.c **** ) - 414:./lib/fatfs/mmc.c **** { - 513 .loc 1 414 0 - 514 .cfi_startproc - 515 @ args = 0, pretend = 0, frame = 32 - 516 @ frame_needed = 0, uses_anonymous_args = 0 - 517 .LVL72: - 415:./lib/fatfs/mmc.c **** BYTE n, cmd, ty, ocr[4]; - 416:./lib/fatfs/mmc.c **** ULONG timeOutTime; - 417:./lib/fatfs/mmc.c **** - 418:./lib/fatfs/mmc.c **** - 419:./lib/fatfs/mmc.c **** if (pdrv) return STA_NOINIT; /* Supports only single drive */ - 518 .loc 1 419 0 - 519 0000 0028 cmp r0, #0 - 520 0002 40F05A81 bne .L69 - 420:./lib/fatfs/mmc.c **** if (Stat & STA_NODISK) return Stat; /* No card in the socket */ - 521 .loc 1 420 0 - 522 0006 B24B ldr r3, .L84 - 523 0008 1B78 ldrb r3, [r3] @ zero_extendqisi2 - 524 000a 13F0020F tst r3, #2 - 525 000e 03D0 beq .L52 - 526 .loc 1 420 0 is_stmt 0 discriminator 1 - 527 0010 AF4B ldr r3, .L84 - 528 0012 1878 ldrb r0, [r3] @ zero_extendqisi2 - 529 .LVL73: - 530 0014 C0B2 uxtb r0, r0 - 421:./lib/fatfs/mmc.c **** - 422:./lib/fatfs/mmc.c **** power_on(); /* Force socket power on */ - 423:./lib/fatfs/mmc.c **** - 424:./lib/fatfs/mmc.c **** CS_LOW(); /* CS = L */ - 425:./lib/fatfs/mmc.c **** - 426:./lib/fatfs/mmc.c **** ty = 0; - 427:./lib/fatfs/mmc.c **** if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ - 428:./lib/fatfs/mmc.c **** timeOutTime = TimerGet() + 1000; /* Initialization timeout of 1000 msec */ - 429:./lib/fatfs/mmc.c **** - 430:./lib/fatfs/mmc.c **** if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */ - 431:./lib/fatfs/mmc.c **** for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF); /* Get trailing return value of R7 resp */ - 432:./lib/fatfs/mmc.c **** if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ - 433:./lib/fatfs/mmc.c **** while ((TimerGet() < timeOutTime) && send_cmd(ACMD41, 0x40000000)); /* Wait for leaving idle st - 434:./lib/fatfs/mmc.c **** if ((TimerGet() < timeOutTime) && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */ - 435:./lib/fatfs/mmc.c **** for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF); - 436:./lib/fatfs/mmc.c **** ty = (ocr[0] & 0x40) ? CT_SD2|CT_BLOCK : CT_SD2; /* SDv2 */ - 437:./lib/fatfs/mmc.c **** } - 438:./lib/fatfs/mmc.c **** } - 439:./lib/fatfs/mmc.c **** } else { /* SDv1 or MMCv3 */ - 440:./lib/fatfs/mmc.c **** if (send_cmd(ACMD41, 0) <= 1) { - 441:./lib/fatfs/mmc.c **** ty = CT_SD1; cmd = ACMD41; /* SDv1 */ - 442:./lib/fatfs/mmc.c **** } else { - 443:./lib/fatfs/mmc.c **** ty = CT_MMC; cmd = CMD1; /* MMCv3 */ - 444:./lib/fatfs/mmc.c **** } - 445:./lib/fatfs/mmc.c **** while ((TimerGet() < timeOutTime) && send_cmd(cmd, 0)); /* Wait for leaving idle state */ - 446:./lib/fatfs/mmc.c **** if (!(TimerGet() < timeOutTime) || send_cmd(CMD16, 512) != 0) /* Set read/write block length to - 447:./lib/fatfs/mmc.c **** ty = 0; - 448:./lib/fatfs/mmc.c **** } - 449:./lib/fatfs/mmc.c **** } - 450:./lib/fatfs/mmc.c **** CardType = ty; - 451:./lib/fatfs/mmc.c **** deselect(); - 452:./lib/fatfs/mmc.c **** - 453:./lib/fatfs/mmc.c **** if (ty) { /* Initialization succeded */ - 454:./lib/fatfs/mmc.c **** Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ - 455:./lib/fatfs/mmc.c **** FCLK_FAST(); - 456:./lib/fatfs/mmc.c **** } else { /* Initialization failed */ - 457:./lib/fatfs/mmc.c **** power_off(); - 458:./lib/fatfs/mmc.c **** } - 459:./lib/fatfs/mmc.c **** - 460:./lib/fatfs/mmc.c **** return Stat; - 461:./lib/fatfs/mmc.c **** } - 531 .loc 1 461 0 is_stmt 1 discriminator 1 - 532 0016 7047 bx lr - 533 .LVL74: - 534 .L52: - 414:./lib/fatfs/mmc.c **** BYTE n, cmd, ty, ocr[4]; - 535 .loc 1 414 0 - 536 0018 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} - 537 .cfi_def_cfa_offset 28 - 538 .cfi_offset 4, -28 - 539 .cfi_offset 5, -24 - 540 .cfi_offset 6, -20 - 541 .cfi_offset 7, -16 - 542 .cfi_offset 8, -12 - 543 .cfi_offset 9, -8 - 544 .cfi_offset 14, -4 - 545 001c 89B0 sub sp, sp, #36 - 546 .cfi_def_cfa_offset 64 - 547 .LBB18: - 548 .LBB19: - 131:./lib/fatfs/mmc.c **** /* Enable SPI clock, SPI2: APB1 */ - 549 .loc 1 131 0 - 550 001e 0820 movs r0, #8 - 551 .LVL75: - 552 0020 0121 movs r1, #1 - 553 0022 FFF7FEFF bl RCC_APB2PeriphClockCmd - 554 .LVL76: - 133:./lib/fatfs/mmc.c **** /* Configure I/O for Flash Chip select (PB12) */ - 555 .loc 1 133 0 - 556 0026 4FF48040 mov r0, #16384 - 557 002a 0121 movs r1, #1 - 558 002c FFF7FEFF bl RCC_APB1PeriphClockCmd - 559 .LVL77: - 135:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - 560 .loc 1 135 0 - 561 0030 4FF48057 mov r7, #4096 - 562 0034 ADF80070 strh r7, [sp] @ movhi - 136:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - 563 .loc 1 136 0 - 564 0038 4FF01009 mov r9, #16 - 565 003c 8DF80390 strb r9, [sp, #3] - 137:./lib/fatfs/mmc.c **** GPIO_Init(GPIOB, &GPIO_InitStructure); - 566 .loc 1 137 0 - 567 0040 0326 movs r6, #3 - 568 0042 8DF80260 strb r6, [sp, #2] - 138:./lib/fatfs/mmc.c **** - 569 .loc 1 138 0 - 570 0046 A34C ldr r4, .L84+4 - 571 0048 2046 mov r0, r4 - 572 004a 6946 mov r1, sp - 573 004c FFF7FEFF bl GPIO_Init - 574 .LVL78: - 141:./lib/fatfs/mmc.c **** - 575 .loc 1 141 0 - 576 0050 2046 mov r0, r4 - 577 0052 3946 mov r1, r7 - 578 0054 FFF7FEFF bl GPIO_SetBits - 579 .LVL79: - 144:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - 580 .loc 1 144 0 - 581 0058 4FF42043 mov r3, #40960 - 582 005c ADF80030 strh r3, [sp] @ movhi - 145:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - 583 .loc 1 145 0 - 584 0060 8DF80260 strb r6, [sp, #2] - 146:./lib/fatfs/mmc.c **** GPIO_Init(GPIOB, &GPIO_InitStructure); - 585 .loc 1 146 0 - 586 0064 1823 movs r3, #24 - 587 0066 8DF80330 strb r3, [sp, #3] - 147:./lib/fatfs/mmc.c **** /* Configure MISO (PB14) as Input with internal pull-up */ - 588 .loc 1 147 0 - 589 006a 2046 mov r0, r4 - 590 006c 6946 mov r1, sp - 591 006e FFF7FEFF bl GPIO_Init - 592 .LVL80: - 149:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - 593 .loc 1 149 0 - 594 0072 4FF48043 mov r3, #16384 - 595 0076 ADF80030 strh r3, [sp] @ movhi - 150:./lib/fatfs/mmc.c **** GPIO_Init(GPIOB, &GPIO_InitStructure); - 596 .loc 1 150 0 - 597 007a 4823 movs r3, #72 - 598 007c 8DF80330 strb r3, [sp, #3] - 151:./lib/fatfs/mmc.c **** - 599 .loc 1 151 0 - 600 0080 2046 mov r0, r4 - 601 0082 6946 mov r1, sp - 602 0084 FFF7FEFF bl GPIO_Init - 603 .LVL81: - 154:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - 604 .loc 1 154 0 - 605 0088 0025 movs r5, #0 - 606 008a ADF80850 strh r5, [sp, #8] @ movhi - 155:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - 607 .loc 1 155 0 - 608 008e 4FF48273 mov r3, #260 - 609 0092 ADF80A30 strh r3, [sp, #10] @ movhi - 156:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; - 610 .loc 1 156 0 - 611 0096 ADF80C50 strh r5, [sp, #12] @ movhi - 157:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; - 612 .loc 1 157 0 - 613 009a ADF80E50 strh r5, [sp, #14] @ movhi - 158:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - 614 .loc 1 158 0 - 615 009e ADF81050 strh r5, [sp, #16] @ movhi - 159:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256; // 72000kHz/256=281kHz < 400 - 616 .loc 1 159 0 - 617 00a2 4FF40073 mov r3, #512 - 618 00a6 ADF81230 strh r3, [sp, #18] @ movhi - 160:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - 619 .loc 1 160 0 - 620 00aa 3823 movs r3, #56 - 621 00ac ADF81430 strh r3, [sp, #20] @ movhi - 161:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_CRCPolynomial = 7; - 622 .loc 1 161 0 - 623 00b0 ADF81650 strh r5, [sp, #22] @ movhi - 162:./lib/fatfs/mmc.c **** - 624 .loc 1 162 0 - 625 00b4 0723 movs r3, #7 - 626 00b6 ADF81830 strh r3, [sp, #24] @ movhi - 164:./lib/fatfs/mmc.c **** SPI_CalculateCRC(SPI2, DISABLE); - 627 .loc 1 164 0 - 628 00ba DFF82082 ldr r8, .L84+12 - 629 00be 4046 mov r0, r8 - 630 00c0 02A9 add r1, sp, #8 - 631 00c2 FFF7FEFF bl SPI_Init - 632 .LVL82: - 165:./lib/fatfs/mmc.c **** SPI_Cmd(SPI2, ENABLE); - 633 .loc 1 165 0 - 634 00c6 4046 mov r0, r8 - 635 00c8 2946 mov r1, r5 - 636 00ca FFF7FEFF bl SPI_CalculateCRC - 637 .LVL83: - 166:./lib/fatfs/mmc.c **** - 638 .loc 1 166 0 - 639 00ce 4046 mov r0, r8 - 640 00d0 0121 movs r1, #1 - 641 00d2 FFF7FEFF bl SPI_Cmd - 642 .LVL84: - 643 .LBB20: - 644 .LBB21: - 82:./lib/fatfs/mmc.c **** - 645 .loc 1 82 0 - 646 00d6 2046 mov r0, r4 - 647 00d8 3946 mov r1, r7 - 648 00da FFF7FEFF bl GPIO_SetBits - 649 .LVL85: - 85:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - 650 .loc 1 85 0 - 651 00de 4FF40045 mov r5, #32768 - 652 00e2 ADF80450 strh r5, [sp, #4] @ movhi - 86:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - 653 .loc 1 86 0 - 654 00e6 8DF80660 strb r6, [sp, #6] - 87:./lib/fatfs/mmc.c **** GPIO_Init(GPIOB, &GPIO_InitStructure); - 655 .loc 1 87 0 - 656 00ea 8DF80790 strb r9, [sp, #7] - 88:./lib/fatfs/mmc.c **** GPIO_SetBits(GPIOB, GPIO_Pin_15); - 657 .loc 1 88 0 - 658 00ee 2046 mov r0, r4 - 659 00f0 01A9 add r1, sp, #4 - 660 00f2 FFF7FEFF bl GPIO_Init - 661 .LVL86: - 89:./lib/fatfs/mmc.c **** - 662 .loc 1 89 0 - 663 00f6 2046 mov r0, r4 - 664 00f8 2946 mov r1, r5 - 665 00fa FFF7FEFF bl GPIO_SetBits - 666 .LVL87: - 667 00fe 0A27 movs r7, #10 - 96:./lib/fatfs/mmc.c **** - 668 .loc 1 96 0 - 669 0100 0226 movs r6, #2 - 670 0102 4446 mov r4, r8 - 671 .LVL88: - 672 .L53: - 673 0104 2046 mov r0, r4 - 674 0106 3146 mov r1, r6 - 675 0108 FFF7FEFF bl SPI_I2S_GetFlagStatus - 676 .LVL89: - 677 010c 0028 cmp r0, #0 - 678 010e F9D0 beq .L53 - 99:./lib/fatfs/mmc.c **** - 679 .loc 1 99 0 - 680 0110 2046 mov r0, r4 - 681 0112 FF21 movs r1, #255 - 682 0114 FFF7FEFF bl SPI_I2S_SendData - 683 .LVL90: - 102:./lib/fatfs/mmc.c **** } - 684 .loc 1 102 0 - 685 0118 0125 movs r5, #1 - 686 .L54: - 687 011a 2046 mov r0, r4 - 688 011c 2946 mov r1, r5 - 689 011e FFF7FEFF bl SPI_I2S_GetFlagStatus - 690 .LVL91: - 691 0122 0028 cmp r0, #0 - 692 0124 F9D0 beq .L54 - 693 .LVL92: - 93:./lib/fatfs/mmc.c **** { - 694 .loc 1 93 0 - 695 0126 013F subs r7, r7, #1 - 696 .LVL93: - 697 0128 ECD1 bne .L53 - 106:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - 698 .loc 1 106 0 - 699 012a 4FF40043 mov r3, #32768 - 700 012e ADF80430 strh r3, [sp, #4] @ movhi - 107:./lib/fatfs/mmc.c **** GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - 701 .loc 1 107 0 - 702 0132 0323 movs r3, #3 - 703 0134 8DF80630 strb r3, [sp, #6] - 108:./lib/fatfs/mmc.c **** GPIO_Init(GPIOB, &GPIO_InitStructure); - 704 .loc 1 108 0 - 705 0138 1823 movs r3, #24 - 706 013a 8DF80730 strb r3, [sp, #7] - 109:./lib/fatfs/mmc.c **** } - 707 .loc 1 109 0 - 708 013e 654C ldr r4, .L84+4 - 709 0140 2046 mov r0, r4 - 710 0142 01A9 add r1, sp, #4 - 711 0144 FFF7FEFF bl GPIO_Init - 712 .LVL94: - 713 .LBE21: - 714 .LBE20: - 715 .LBE19: - 716 .LBE18: - 424:./lib/fatfs/mmc.c **** - 717 .loc 1 424 0 - 718 0148 2046 mov r0, r4 - 719 014a 4FF48051 mov r1, #4096 - 720 014e FFF7FEFF bl GPIO_ResetBits - 721 .LVL95: - 427:./lib/fatfs/mmc.c **** timeOutTime = TimerGet() + 1000; /* Initialization timeout of 1000 msec */ - 722 .loc 1 427 0 - 723 0152 0020 movs r0, #0 - 724 0154 0146 mov r1, r0 - 725 0156 FFF7FEFF bl send_cmd - 726 .LVL96: - 727 015a 0128 cmp r0, #1 - 728 015c 40F0AF80 bne .L56 - 428:./lib/fatfs/mmc.c **** - 729 .loc 1 428 0 - 730 0160 FFF7FEFF bl TimerGet - 731 .LVL97: - 732 0164 00F57A74 add r4, r0, #1000 - 733 .LVL98: - 430:./lib/fatfs/mmc.c **** for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF); /* Get trailing return value of R7 resp */ - 734 .loc 1 430 0 - 735 0168 0820 movs r0, #8 - 736 016a 4FF4D571 mov r1, #426 - 737 016e FFF7FEFF bl send_cmd - 738 .LVL99: - 739 0172 0128 cmp r0, #1 - 740 0174 43D1 bne .L57 - 741 0176 07AE add r6, sp, #28 - 742 0178 08AF add r7, sp, #32 - 743 .LVL100: - 744 017a 3546 mov r5, r6 - 431:./lib/fatfs/mmc.c **** if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ - 745 .loc 1 431 0 - 746 017c 4FF0FF08 mov r8, #255 - 747 .L58: - 748 .LVL101: - 431:./lib/fatfs/mmc.c **** if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ - 749 .loc 1 431 0 is_stmt 0 discriminator 3 - 750 0180 4046 mov r0, r8 - 751 0182 FFF7FEFF bl xchg_spi - 752 .LVL102: - 753 0186 05F8010B strb r0, [r5], #1 - 754 .LVL103: - 755 018a BD42 cmp r5, r7 - 756 018c F8D1 bne .L58 - 432:./lib/fatfs/mmc.c **** while ((TimerGet() < timeOutTime) && send_cmd(ACMD41, 0x40000000)); /* Wait for leaving idle st - 757 .loc 1 432 0 is_stmt 1 - 758 018e 9DF81E30 ldrb r3, [sp, #30] @ zero_extendqisi2 - 759 0192 012B cmp r3, #1 - 760 0194 40F09380 bne .L56 - 432:./lib/fatfs/mmc.c **** while ((TimerGet() < timeOutTime) && send_cmd(ACMD41, 0x40000000)); /* Wait for leaving idle st - 761 .loc 1 432 0 is_stmt 0 discriminator 1 - 762 0198 9DF81F30 ldrb r3, [sp, #31] @ zero_extendqisi2 - 763 019c AA2B cmp r3, #170 - 764 019e 40F08E80 bne .L56 - 433:./lib/fatfs/mmc.c **** if ((TimerGet() < timeOutTime) && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */ - 765 .loc 1 433 0 is_stmt 1 discriminator 2 - 766 01a2 4FF0A908 mov r8, #169 - 767 01a6 4FF08045 mov r5, #1073741824 - 768 .LVL104: - 769 .L73: - 770 01aa FFF7FEFF bl TimerGet - 771 .LVL105: - 772 01ae 8442 cmp r4, r0 - 773 01b0 05D9 bls .L59 - 433:./lib/fatfs/mmc.c **** if ((TimerGet() < timeOutTime) && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */ - 774 .loc 1 433 0 is_stmt 0 discriminator 1 - 775 01b2 4046 mov r0, r8 - 776 01b4 2946 mov r1, r5 - 777 01b6 FFF7FEFF bl send_cmd - 778 .LVL106: - 779 01ba 0028 cmp r0, #0 - 780 01bc F5D1 bne .L73 - 781 .L59: - 434:./lib/fatfs/mmc.c **** for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF); - 782 .loc 1 434 0 is_stmt 1 - 783 01be FFF7FEFF bl TimerGet - 784 .LVL107: - 785 01c2 8442 cmp r4, r0 - 786 01c4 7BD9 bls .L56 - 434:./lib/fatfs/mmc.c **** for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF); - 787 .loc 1 434 0 is_stmt 0 discriminator 1 - 788 01c6 3A20 movs r0, #58 - 789 01c8 0021 movs r1, #0 - 790 01ca FFF7FEFF bl send_cmd - 791 .LVL108: - 792 01ce 0028 cmp r0, #0 - 793 01d0 75D1 bne .L56 - 435:./lib/fatfs/mmc.c **** ty = (ocr[0] & 0x40) ? CT_SD2|CT_BLOCK : CT_SD2; /* SDv2 */ - 794 .loc 1 435 0 is_stmt 1 discriminator 3 - 795 01d2 FF24 movs r4, #255 - 796 .LVL109: - 797 .L72: - 798 01d4 2046 mov r0, r4 - 799 01d6 FFF7FEFF bl xchg_spi - 800 .LVL110: - 801 01da 06F8010B strb r0, [r6], #1 - 802 .LVL111: - 803 01de BE42 cmp r6, r7 - 804 01e0 F8D1 bne .L72 - 436:./lib/fatfs/mmc.c **** } - 805 .loc 1 436 0 - 806 01e2 9DF81C30 ldrb r3, [sp, #28] @ zero_extendqisi2 - 807 01e6 03F04003 and r3, r3, #64 - 808 01ea DBB2 uxtb r3, r3 - 809 01ec 002B cmp r3, #0 - 810 01ee 14BF ite ne - 811 01f0 0C22 movne r2, #12 - 812 01f2 0422 moveq r2, #4 - 813 .LVL112: - 450:./lib/fatfs/mmc.c **** deselect(); - 814 .loc 1 450 0 - 815 01f4 384B ldr r3, .L84+8 - 816 01f6 1A60 str r2, [r3] - 451:./lib/fatfs/mmc.c **** - 817 .loc 1 451 0 - 818 01f8 FFF7FEFF bl deselect - 819 .LVL113: - 820 01fc 24E0 b .L68 - 821 .LVL114: - 822 .L57: - 440:./lib/fatfs/mmc.c **** ty = CT_SD1; cmd = ACMD41; /* SDv1 */ - 823 .loc 1 440 0 - 824 01fe A920 movs r0, #169 - 825 0200 0021 movs r1, #0 - 826 0202 FFF7FEFF bl send_cmd - 827 .LVL115: - 828 0206 0128 cmp r0, #1 - 443:./lib/fatfs/mmc.c **** } - 829 .loc 1 443 0 - 830 0208 87BF ittee hi - 831 020a 0127 movhi r7, #1 - 832 .LVL116: - 833 020c 3D46 movhi r5, r7 - 441:./lib/fatfs/mmc.c **** } else { - 834 .loc 1 441 0 - 835 020e 0227 movls r7, #2 - 836 0210 A925 movls r5, #169 - 445:./lib/fatfs/mmc.c **** if (!(TimerGet() < timeOutTime) || send_cmd(CMD16, 512) != 0) /* Set read/write block length to - 837 .loc 1 445 0 - 838 0212 0026 movs r6, #0 - 839 .LVL117: - 840 .L65: - 445:./lib/fatfs/mmc.c **** if (!(TimerGet() < timeOutTime) || send_cmd(CMD16, 512) != 0) /* Set read/write block length to - 841 .loc 1 445 0 is_stmt 0 discriminator 2 - 842 0214 FFF7FEFF bl TimerGet - 843 .LVL118: - 844 0218 8442 cmp r4, r0 - 845 021a 05D9 bls .L64 - 445:./lib/fatfs/mmc.c **** if (!(TimerGet() < timeOutTime) || send_cmd(CMD16, 512) != 0) /* Set read/write block length to - 846 .loc 1 445 0 discriminator 1 - 847 021c 2846 mov r0, r5 - 848 021e 3146 mov r1, r6 - 849 0220 FFF7FEFF bl send_cmd - 850 .LVL119: - 851 0224 0028 cmp r0, #0 - 852 0226 F5D1 bne .L65 - 853 .L64: - 446:./lib/fatfs/mmc.c **** ty = 0; - 854 .loc 1 446 0 is_stmt 1 - 855 0228 FFF7FEFF bl TimerGet - 856 .LVL120: - 857 022c 8442 cmp r4, r0 - 858 022e 46D9 bls .L56 - 446:./lib/fatfs/mmc.c **** ty = 0; - 859 .loc 1 446 0 is_stmt 0 discriminator 1 - 860 0230 1020 movs r0, #16 - 861 0232 4FF40071 mov r1, #512 - 862 0236 FFF7FEFF bl send_cmd - 863 .LVL121: - 864 023a 0028 cmp r0, #0 - 865 023c 3FD1 bne .L56 - 866 .LVL122: - 450:./lib/fatfs/mmc.c **** deselect(); - 867 .loc 1 450 0 is_stmt 1 - 868 023e 264B ldr r3, .L84+8 - 869 0240 1F60 str r7, [r3] - 451:./lib/fatfs/mmc.c **** - 870 .loc 1 451 0 - 871 0242 FFF7FEFF bl deselect - 872 .LVL123: - 453:./lib/fatfs/mmc.c **** Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ - 873 .loc 1 453 0 - 874 0246 7FB3 cbz r7, .L66 - 875 .LVL124: - 876 .L68: - 454:./lib/fatfs/mmc.c **** FCLK_FAST(); - 877 .loc 1 454 0 - 878 0248 214A ldr r2, .L84 - 879 024a 1378 ldrb r3, [r2] @ zero_extendqisi2 - 880 024c 03F0FE03 and r3, r3, #254 - 881 0250 1370 strb r3, [r2] - 882 .LBB22: - 883 .LBB23: - 180:./lib/fatfs/mmc.c **** - 884 .loc 1 180 0 - 885 0252 224D ldr r5, .L84+12 - 886 0254 2846 mov r0, r5 - 887 0256 0021 movs r1, #0 - 888 0258 FFF7FEFF bl SPI_Cmd - 889 .LVL125: - 185:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - 890 .loc 1 185 0 - 891 025c 0024 movs r4, #0 - 892 025e ADF80840 strh r4, [sp, #8] @ movhi - 186:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - 893 .loc 1 186 0 - 894 0262 4FF48273 mov r3, #260 - 895 0266 ADF80A30 strh r3, [sp, #10] @ movhi - 187:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; - 896 .loc 1 187 0 - 897 026a ADF80C40 strh r4, [sp, #12] @ movhi - 188:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; - 898 .loc 1 188 0 - 899 026e ADF80E40 strh r4, [sp, #14] @ movhi - 189:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - 900 .loc 1 189 0 - 901 0272 ADF81040 strh r4, [sp, #16] @ movhi - 190:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; // 72MHz/4=18MHz < 20MHz - 902 .loc 1 190 0 - 903 0276 4FF40073 mov r3, #512 - 904 027a ADF81230 strh r3, [sp, #18] @ movhi - 191:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - 905 .loc 1 191 0 - 906 027e 0823 movs r3, #8 - 907 0280 ADF81430 strh r3, [sp, #20] @ movhi - 192:./lib/fatfs/mmc.c **** SPI_InitStructure.SPI_CRCPolynomial = 7; - 908 .loc 1 192 0 - 909 0284 ADF81640 strh r4, [sp, #22] @ movhi - 193:./lib/fatfs/mmc.c **** SPI_Init(SPI2, &SPI_InitStructure); - 910 .loc 1 193 0 - 911 0288 0723 movs r3, #7 - 912 028a ADF81830 strh r3, [sp, #24] @ movhi - 194:./lib/fatfs/mmc.c **** SPI_CalculateCRC(SPI2, DISABLE); - 913 .loc 1 194 0 - 914 028e 2846 mov r0, r5 - 915 0290 02A9 add r1, sp, #8 - 916 0292 FFF7FEFF bl SPI_Init - 917 .LVL126: - 195:./lib/fatfs/mmc.c **** - 918 .loc 1 195 0 - 919 0296 2846 mov r0, r5 - 920 0298 2146 mov r1, r4 - 921 029a FFF7FEFF bl SPI_CalculateCRC - 922 .LVL127: - 198:./lib/fatfs/mmc.c **** } - 923 .loc 1 198 0 - 924 029e 2846 mov r0, r5 - 925 02a0 0121 movs r1, #1 - 926 02a2 FFF7FEFF bl SPI_Cmd - 927 .LVL128: - 928 02a6 04E0 b .L67 - 929 .L66: - 930 .LVL129: - 931 .LBE23: - 932 .LBE22: - 933 .LBB24: - 934 .LBB25: - 204:./lib/fatfs/mmc.c **** } - 935 .loc 1 204 0 - 936 02a8 094A ldr r2, .L84 - 937 02aa 1378 ldrb r3, [r2] @ zero_extendqisi2 - 938 02ac 43F00103 orr r3, r3, #1 - 939 02b0 1370 strb r3, [r2] - 940 .LVL130: - 941 .L67: - 942 .LBE25: - 943 .LBE24: - 460:./lib/fatfs/mmc.c **** } - 944 .loc 1 460 0 - 945 02b2 074B ldr r3, .L84 - 946 02b4 1878 ldrb r0, [r3] @ zero_extendqisi2 - 947 02b6 C0B2 uxtb r0, r0 - 948 02b8 07E0 b .L81 - 949 .LVL131: - 950 .L69: - 951 .cfi_def_cfa_offset 0 - 952 .cfi_restore 4 - 953 .cfi_restore 5 - 954 .cfi_restore 6 - 955 .cfi_restore 7 - 956 .cfi_restore 8 - 957 .cfi_restore 9 - 958 .cfi_restore 14 - 419:./lib/fatfs/mmc.c **** if (Stat & STA_NODISK) return Stat; /* No card in the socket */ - 959 .loc 1 419 0 - 960 02ba 0120 movs r0, #1 - 961 .LVL132: - 962 02bc 7047 bx lr - 963 .L56: - 964 .cfi_def_cfa_offset 64 - 965 .cfi_offset 4, -28 - 966 .cfi_offset 5, -24 - 967 .cfi_offset 6, -20 - 968 .cfi_offset 7, -16 - 969 .cfi_offset 8, -12 - 970 .cfi_offset 9, -8 - 971 .cfi_offset 14, -4 - 972 .LVL133: - 450:./lib/fatfs/mmc.c **** deselect(); - 973 .loc 1 450 0 - 974 02be 0022 movs r2, #0 - 975 02c0 054B ldr r3, .L84+8 - 976 02c2 1A60 str r2, [r3] - 451:./lib/fatfs/mmc.c **** - 977 .loc 1 451 0 - 978 02c4 FFF7FEFF bl deselect - 979 .LVL134: - 980 02c8 EEE7 b .L66 - 981 .LVL135: - 982 .L81: - 983 .loc 1 461 0 - 984 02ca 09B0 add sp, sp, #36 - 985 .cfi_def_cfa_offset 28 - 986 @ sp needed - 987 02cc BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} - 988 .L85: - 989 .align 2 - 990 .L84: - 991 02d0 00000000 .word .LANCHOR0 - 992 02d4 000C0140 .word 1073810432 - 993 02d8 00000000 .word .LANCHOR1 - 994 02dc 00380040 .word 1073756160 - 995 .cfi_endproc - 996 .LFE41: - 998 .section .text.disk_status,"ax",%progbits - 999 .align 2 - 1000 .global disk_status - 1001 .thumb - 1002 .thumb_func - 1004 disk_status: - 1005 .LFB42: - 462:./lib/fatfs/mmc.c **** - 463:./lib/fatfs/mmc.c **** - 464:./lib/fatfs/mmc.c **** - 465:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 466:./lib/fatfs/mmc.c **** /* Get Disk Status */ - 467:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 468:./lib/fatfs/mmc.c **** - 469:./lib/fatfs/mmc.c **** DSTATUS disk_status ( - 470:./lib/fatfs/mmc.c **** BYTE pdrv /* Physical drive nmuber (0) */ - 471:./lib/fatfs/mmc.c **** ) - 472:./lib/fatfs/mmc.c **** { - 1006 .loc 1 472 0 - 1007 .cfi_startproc - 1008 @ args = 0, pretend = 0, frame = 0 - 1009 @ frame_needed = 0, uses_anonymous_args = 0 - 1010 @ link register save eliminated. - 1011 .LVL136: - 473:./lib/fatfs/mmc.c **** if (pdrv) return STA_NOINIT; /* Supports only single drive */ - 1012 .loc 1 473 0 - 1013 0000 18B9 cbnz r0, .L88 - 474:./lib/fatfs/mmc.c **** return Stat; - 1014 .loc 1 474 0 - 1015 0002 034B ldr r3, .L89 - 1016 0004 1878 ldrb r0, [r3] @ zero_extendqisi2 - 1017 .LVL137: - 1018 0006 C0B2 uxtb r0, r0 - 1019 0008 7047 bx lr - 1020 .LVL138: - 1021 .L88: - 473:./lib/fatfs/mmc.c **** if (pdrv) return STA_NOINIT; /* Supports only single drive */ - 1022 .loc 1 473 0 - 1023 000a 0120 movs r0, #1 - 1024 .LVL139: - 475:./lib/fatfs/mmc.c **** } - 1025 .loc 1 475 0 - 1026 000c 7047 bx lr - 1027 .L90: - 1028 000e 00BF .align 2 - 1029 .L89: - 1030 0010 00000000 .word .LANCHOR0 - 1031 .cfi_endproc - 1032 .LFE42: - 1034 .section .text.disk_read,"ax",%progbits - 1035 .align 2 - 1036 .global disk_read - 1037 .thumb - 1038 .thumb_func - 1040 disk_read: - 1041 .LFB43: - 476:./lib/fatfs/mmc.c **** - 477:./lib/fatfs/mmc.c **** - 478:./lib/fatfs/mmc.c **** - 479:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 480:./lib/fatfs/mmc.c **** /* Read Sector(s) */ - 481:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 482:./lib/fatfs/mmc.c **** - 483:./lib/fatfs/mmc.c **** DRESULT disk_read ( - 484:./lib/fatfs/mmc.c **** BYTE pdrv, /* Physical drive number (0) */ - 485:./lib/fatfs/mmc.c **** BYTE *buff, /* Pointer to the data buffer to store read data */ - 486:./lib/fatfs/mmc.c **** DWORD sector, /* Start sector number (LBA) */ - 487:./lib/fatfs/mmc.c **** BYTE count /* Sector count (1..255) */ - 488:./lib/fatfs/mmc.c **** ) - 489:./lib/fatfs/mmc.c **** { - 1042 .loc 1 489 0 - 1043 .cfi_startproc - 1044 @ args = 0, pretend = 0, frame = 0 - 1045 @ frame_needed = 0, uses_anonymous_args = 0 - 1046 .LVL140: - 490:./lib/fatfs/mmc.c **** if (pdrv || !count) return RES_PARERR; - 1047 .loc 1 490 0 - 1048 0000 0028 cmp r0, #0 - 1049 0002 3BD1 bne .L98 - 489:./lib/fatfs/mmc.c **** if (pdrv || !count) return RES_PARERR; - 1050 .loc 1 489 0 discriminator 2 - 1051 0004 70B5 push {r4, r5, r6, lr} - 1052 .cfi_def_cfa_offset 16 - 1053 .cfi_offset 4, -16 - 1054 .cfi_offset 5, -12 - 1055 .cfi_offset 6, -8 - 1056 .cfi_offset 14, -4 - 1057 0006 0D46 mov r5, r1 - 1058 0008 1C46 mov r4, r3 - 1059 .loc 1 490 0 discriminator 2 - 1060 000a 002B cmp r3, #0 - 1061 000c 38D0 beq .L99 - 491:./lib/fatfs/mmc.c **** if (Stat & STA_NOINIT) return RES_NOTRDY; - 1062 .loc 1 491 0 - 1063 000e 1E4B ldr r3, .L104 - 1064 .LVL141: - 1065 0010 1B78 ldrb r3, [r3] @ zero_extendqisi2 - 1066 0012 13F0010F tst r3, #1 - 1067 0016 35D1 bne .L100 - 492:./lib/fatfs/mmc.c **** - 493:./lib/fatfs/mmc.c **** if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ - 1068 .loc 1 493 0 - 1069 0018 1C4B ldr r3, .L104+4 - 1070 001a 1B68 ldr r3, [r3] - 1071 001c 13F0080F tst r3, #8 - 1072 0020 08BF it eq - 1073 0022 5202 lsleq r2, r2, #9 - 1074 .LVL142: - 494:./lib/fatfs/mmc.c **** - 495:./lib/fatfs/mmc.c **** if (count == 1) { /* Single block read */ - 1075 .loc 1 495 0 - 1076 0024 012C cmp r4, #1 - 1077 0026 0DD1 bne .L94 - 496:./lib/fatfs/mmc.c **** if ((send_cmd(CMD17, sector) == 0) /* READ_SINGLE_BLOCK */ - 1078 .loc 1 496 0 - 1079 0028 1120 movs r0, #17 - 1080 .LVL143: - 1081 002a 1146 mov r1, r2 - 1082 .LVL144: - 1083 002c FFF7FEFF bl send_cmd - 1084 .LVL145: - 1085 0030 F0B9 cbnz r0, .L95 - 497:./lib/fatfs/mmc.c **** && rcvr_datablock(buff, 512)) - 1086 .loc 1 497 0 - 1087 0032 2846 mov r0, r5 - 1088 0034 4FF40071 mov r1, #512 - 1089 0038 FFF7FEFF bl rcvr_datablock - 1090 .LVL146: - 1091 003c B0FA80F4 clz r4, r0 - 1092 0040 6409 lsrs r4, r4, #5 - 1093 0042 15E0 b .L95 - 1094 .LVL147: - 1095 .L94: - 498:./lib/fatfs/mmc.c **** count = 0; - 499:./lib/fatfs/mmc.c **** } - 500:./lib/fatfs/mmc.c **** else { /* Multiple block read */ - 501:./lib/fatfs/mmc.c **** if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ - 1096 .loc 1 501 0 - 1097 0044 1220 movs r0, #18 - 1098 .LVL148: - 1099 0046 1146 mov r1, r2 - 1100 .LVL149: - 1101 0048 FFF7FEFF bl send_cmd - 1102 .LVL150: - 1103 004c 80B9 cbnz r0, .L95 - 502:./lib/fatfs/mmc.c **** do { - 503:./lib/fatfs/mmc.c **** if (!rcvr_datablock(buff, 512)) break; - 1104 .loc 1 503 0 - 1105 004e 4FF40076 mov r6, #512 - 1106 .LVL151: - 1107 .L101: - 1108 0052 2846 mov r0, r5 - 1109 0054 3146 mov r1, r6 - 1110 0056 FFF7FEFF bl rcvr_datablock - 1111 .LVL152: - 1112 005a 28B1 cbz r0, .L96 - 504:./lib/fatfs/mmc.c **** buff += 512; - 1113 .loc 1 504 0 - 1114 005c 05F50075 add r5, r5, #512 - 1115 .LVL153: - 505:./lib/fatfs/mmc.c **** } while (--count); - 1116 .loc 1 505 0 - 1117 0060 601E subs r0, r4, #1 - 1118 .LVL154: - 1119 0062 10F0FF04 ands r4, r0, #255 - 1120 0066 F4D1 bne .L101 - 1121 .LVL155: - 1122 .L96: - 506:./lib/fatfs/mmc.c **** send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ - 1123 .loc 1 506 0 - 1124 0068 0C20 movs r0, #12 - 1125 006a 0021 movs r1, #0 - 1126 006c FFF7FEFF bl send_cmd - 1127 .LVL156: - 1128 .L95: - 507:./lib/fatfs/mmc.c **** } - 508:./lib/fatfs/mmc.c **** } - 509:./lib/fatfs/mmc.c **** deselect(); - 1129 .loc 1 509 0 - 1130 0070 FFF7FEFF bl deselect - 1131 .LVL157: - 510:./lib/fatfs/mmc.c **** - 511:./lib/fatfs/mmc.c **** return count ? RES_ERROR : RES_OK; - 1132 .loc 1 511 0 - 1133 0074 201C adds r0, r4, #0 - 1134 0076 18BF it ne - 1135 0078 0120 movne r0, #1 - 1136 007a 70BD pop {r4, r5, r6, pc} - 1137 .LVL158: - 1138 .L98: - 1139 .cfi_def_cfa_offset 0 - 1140 .cfi_restore 4 - 1141 .cfi_restore 5 - 1142 .cfi_restore 6 - 1143 .cfi_restore 14 - 490:./lib/fatfs/mmc.c **** if (Stat & STA_NOINIT) return RES_NOTRDY; - 1144 .loc 1 490 0 - 1145 007c 0420 movs r0, #4 - 1146 .LVL159: - 512:./lib/fatfs/mmc.c **** } - 1147 .loc 1 512 0 - 1148 007e 7047 bx lr - 1149 .LVL160: - 1150 .L99: - 1151 .cfi_def_cfa_offset 16 - 1152 .cfi_offset 4, -16 - 1153 .cfi_offset 5, -12 - 1154 .cfi_offset 6, -8 - 1155 .cfi_offset 14, -4 - 490:./lib/fatfs/mmc.c **** if (Stat & STA_NOINIT) return RES_NOTRDY; - 1156 .loc 1 490 0 - 1157 0080 0420 movs r0, #4 - 1158 .LVL161: - 1159 0082 70BD pop {r4, r5, r6, pc} - 1160 .LVL162: - 1161 .L100: - 491:./lib/fatfs/mmc.c **** - 1162 .loc 1 491 0 - 1163 0084 0320 movs r0, #3 - 1164 .LVL163: - 1165 .loc 1 512 0 - 1166 0086 70BD pop {r4, r5, r6, pc} - 1167 .L105: - 1168 .align 2 - 1169 .L104: - 1170 0088 00000000 .word .LANCHOR0 - 1171 008c 00000000 .word .LANCHOR1 - 1172 .cfi_endproc - 1173 .LFE43: - 1175 .section .text.disk_write,"ax",%progbits - 1176 .align 2 - 1177 .global disk_write - 1178 .thumb - 1179 .thumb_func - 1181 disk_write: - 1182 .LFB44: - 513:./lib/fatfs/mmc.c **** - 514:./lib/fatfs/mmc.c **** - 515:./lib/fatfs/mmc.c **** - 516:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 517:./lib/fatfs/mmc.c **** /* Write Sector(s) */ - 518:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 519:./lib/fatfs/mmc.c **** - 520:./lib/fatfs/mmc.c **** #if _USE_WRITE - 521:./lib/fatfs/mmc.c **** DRESULT disk_write ( - 522:./lib/fatfs/mmc.c **** BYTE pdrv, /* Physical drive nmuber (0) */ - 523:./lib/fatfs/mmc.c **** const BYTE *buff, /* Pointer to the data to be written */ - 524:./lib/fatfs/mmc.c **** DWORD sector, /* Start sector number (LBA) */ - 525:./lib/fatfs/mmc.c **** BYTE count /* Sector count (1..255) */ - 526:./lib/fatfs/mmc.c **** ) - 527:./lib/fatfs/mmc.c **** { - 1183 .loc 1 527 0 - 1184 .cfi_startproc - 1185 @ args = 0, pretend = 0, frame = 0 - 1186 @ frame_needed = 0, uses_anonymous_args = 0 - 1187 .LVL164: - 528:./lib/fatfs/mmc.c **** if (pdrv || !count) return RES_PARERR; - 1188 .loc 1 528 0 - 1189 0000 0028 cmp r0, #0 - 1190 0002 49D1 bne .L114 - 527:./lib/fatfs/mmc.c **** if (pdrv || !count) return RES_PARERR; - 1191 .loc 1 527 0 discriminator 2 - 1192 0004 70B5 push {r4, r5, r6, lr} - 1193 .cfi_def_cfa_offset 16 - 1194 .cfi_offset 4, -16 - 1195 .cfi_offset 5, -12 - 1196 .cfi_offset 6, -8 - 1197 .cfi_offset 14, -4 - 1198 0006 0E46 mov r6, r1 - 1199 0008 1546 mov r5, r2 - 1200 000a 1C46 mov r4, r3 - 1201 .loc 1 528 0 discriminator 2 - 1202 000c 002B cmp r3, #0 - 1203 000e 45D0 beq .L115 - 529:./lib/fatfs/mmc.c **** if (Stat & STA_NOINIT) return RES_NOTRDY; - 1204 .loc 1 529 0 - 1205 0010 254B ldr r3, .L121 - 1206 .LVL165: - 1207 0012 1B78 ldrb r3, [r3] @ zero_extendqisi2 - 1208 0014 13F0010F tst r3, #1 - 1209 0018 42D1 bne .L116 - 530:./lib/fatfs/mmc.c **** if (Stat & STA_PROTECT) return RES_WRPRT; - 1210 .loc 1 530 0 - 1211 001a 234B ldr r3, .L121 - 1212 001c 1B78 ldrb r3, [r3] @ zero_extendqisi2 - 1213 001e 13F0040F tst r3, #4 - 1214 0022 3FD1 bne .L117 - 531:./lib/fatfs/mmc.c **** - 532:./lib/fatfs/mmc.c **** if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ - 1215 .loc 1 532 0 - 1216 0024 214B ldr r3, .L121+4 - 1217 0026 1B68 ldr r3, [r3] - 1218 0028 13F0080F tst r3, #8 - 1219 002c 08BF it eq - 1220 002e 5502 lsleq r5, r2, #9 - 1221 .LVL166: - 533:./lib/fatfs/mmc.c **** - 534:./lib/fatfs/mmc.c **** if (count == 1) { /* Single block write */ - 1222 .loc 1 534 0 - 1223 0030 012C cmp r4, #1 - 1224 0032 0CD1 bne .L109 - 535:./lib/fatfs/mmc.c **** if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */ - 1225 .loc 1 535 0 - 1226 0034 1820 movs r0, #24 - 1227 .LVL167: - 1228 0036 2946 mov r1, r5 - 1229 .LVL168: - 1230 0038 FFF7FEFF bl send_cmd - 1231 .LVL169: - 1232 003c 30BB cbnz r0, .L110 - 536:./lib/fatfs/mmc.c **** && xmit_datablock(buff, 0xFE)) - 1233 .loc 1 536 0 - 1234 003e 3046 mov r0, r6 - 1235 0040 FE21 movs r1, #254 - 1236 0042 FFF7FEFF bl xmit_datablock - 1237 .LVL170: - 1238 0046 B0FA80F4 clz r4, r0 - 1239 004a 6409 lsrs r4, r4, #5 - 1240 004c 1EE0 b .L110 - 1241 .LVL171: - 1242 .L109: - 537:./lib/fatfs/mmc.c **** count = 0; - 538:./lib/fatfs/mmc.c **** } - 539:./lib/fatfs/mmc.c **** else { /* Multiple block write */ - 540:./lib/fatfs/mmc.c **** if (CardType & CT_SDC) send_cmd(ACMD23, count); - 1243 .loc 1 540 0 - 1244 004e 13F0060F tst r3, #6 - 1245 0052 03D0 beq .L111 - 1246 .loc 1 540 0 is_stmt 0 discriminator 1 - 1247 0054 9720 movs r0, #151 - 1248 .LVL172: - 1249 0056 2146 mov r1, r4 - 1250 .LVL173: - 1251 0058 FFF7FEFF bl send_cmd - 1252 .LVL174: - 1253 .L111: - 541:./lib/fatfs/mmc.c **** if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ - 1254 .loc 1 541 0 is_stmt 1 - 1255 005c 1920 movs r0, #25 - 1256 005e 2946 mov r1, r5 - 1257 0060 FFF7FEFF bl send_cmd - 1258 .LVL175: - 1259 0064 90B9 cbnz r0, .L110 - 542:./lib/fatfs/mmc.c **** do { - 543:./lib/fatfs/mmc.c **** if (!xmit_datablock(buff, 0xFC)) break; - 1260 .loc 1 543 0 - 1261 0066 FC25 movs r5, #252 - 1262 .LVL176: - 1263 .L118: - 1264 0068 3046 mov r0, r6 - 1265 006a 2946 mov r1, r5 - 1266 006c FFF7FEFF bl xmit_datablock - 1267 .LVL177: - 1268 0070 28B1 cbz r0, .L112 - 544:./lib/fatfs/mmc.c **** buff += 512; - 1269 .loc 1 544 0 - 1270 0072 06F50076 add r6, r6, #512 - 1271 .LVL178: - 545:./lib/fatfs/mmc.c **** } while (--count); - 1272 .loc 1 545 0 - 1273 0076 601E subs r0, r4, #1 - 1274 .LVL179: - 1275 0078 10F0FF04 ands r4, r0, #255 - 1276 007c F4D1 bne .L118 - 1277 .LVL180: - 1278 .L112: - 546:./lib/fatfs/mmc.c **** if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ - 1279 .loc 1 546 0 - 1280 007e 0020 movs r0, #0 - 1281 0080 FD21 movs r1, #253 - 1282 0082 FFF7FEFF bl xmit_datablock - 1283 .LVL181: - 1284 0086 0028 cmp r0, #0 - 547:./lib/fatfs/mmc.c **** count = 1; - 1285 .loc 1 547 0 - 1286 0088 08BF it eq - 1287 008a 0124 moveq r4, #1 - 1288 .LVL182: - 1289 .L110: - 548:./lib/fatfs/mmc.c **** } - 549:./lib/fatfs/mmc.c **** } - 550:./lib/fatfs/mmc.c **** deselect(); - 1290 .loc 1 550 0 - 1291 008c FFF7FEFF bl deselect - 1292 .LVL183: - 551:./lib/fatfs/mmc.c **** - 552:./lib/fatfs/mmc.c **** return count ? RES_ERROR : RES_OK; - 1293 .loc 1 552 0 - 1294 0090 201C adds r0, r4, #0 - 1295 0092 18BF it ne - 1296 0094 0120 movne r0, #1 - 1297 0096 70BD pop {r4, r5, r6, pc} - 1298 .LVL184: - 1299 .L114: - 1300 .cfi_def_cfa_offset 0 - 1301 .cfi_restore 4 - 1302 .cfi_restore 5 - 1303 .cfi_restore 6 - 1304 .cfi_restore 14 - 528:./lib/fatfs/mmc.c **** if (Stat & STA_NOINIT) return RES_NOTRDY; - 1305 .loc 1 528 0 - 1306 0098 0420 movs r0, #4 - 1307 .LVL185: - 553:./lib/fatfs/mmc.c **** } - 1308 .loc 1 553 0 - 1309 009a 7047 bx lr - 1310 .LVL186: - 1311 .L115: - 1312 .cfi_def_cfa_offset 16 - 1313 .cfi_offset 4, -16 - 1314 .cfi_offset 5, -12 - 1315 .cfi_offset 6, -8 - 1316 .cfi_offset 14, -4 - 528:./lib/fatfs/mmc.c **** if (Stat & STA_NOINIT) return RES_NOTRDY; - 1317 .loc 1 528 0 - 1318 009c 0420 movs r0, #4 - 1319 .LVL187: - 1320 009e 70BD pop {r4, r5, r6, pc} - 1321 .LVL188: - 1322 .L116: - 529:./lib/fatfs/mmc.c **** if (Stat & STA_PROTECT) return RES_WRPRT; - 1323 .loc 1 529 0 - 1324 00a0 0320 movs r0, #3 - 1325 .LVL189: - 1326 00a2 70BD pop {r4, r5, r6, pc} - 1327 .LVL190: - 1328 .L117: - 530:./lib/fatfs/mmc.c **** - 1329 .loc 1 530 0 - 1330 00a4 0220 movs r0, #2 - 1331 .LVL191: - 1332 .loc 1 553 0 - 1333 00a6 70BD pop {r4, r5, r6, pc} - 1334 .L122: - 1335 .align 2 - 1336 .L121: - 1337 00a8 00000000 .word .LANCHOR0 - 1338 00ac 00000000 .word .LANCHOR1 - 1339 .cfi_endproc - 1340 .LFE44: - 1342 .section .text.disk_ioctl,"ax",%progbits - 1343 .align 2 - 1344 .global disk_ioctl - 1345 .thumb - 1346 .thumb_func - 1348 disk_ioctl: - 1349 .LFB45: - 554:./lib/fatfs/mmc.c **** #endif - 555:./lib/fatfs/mmc.c **** - 556:./lib/fatfs/mmc.c **** - 557:./lib/fatfs/mmc.c **** - 558:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 559:./lib/fatfs/mmc.c **** /* Miscellaneous Functions */ - 560:./lib/fatfs/mmc.c **** /*-----------------------------------------------------------------------*/ - 561:./lib/fatfs/mmc.c **** - 562:./lib/fatfs/mmc.c **** #if _USE_IOCTL - 563:./lib/fatfs/mmc.c **** DRESULT disk_ioctl ( - 564:./lib/fatfs/mmc.c **** BYTE pdrv, /* Physical drive nmuber (0) */ - 565:./lib/fatfs/mmc.c **** BYTE cmd, /* Control code */ - 566:./lib/fatfs/mmc.c **** void *buff /* Buffer to send/receive data block */ - 567:./lib/fatfs/mmc.c **** ) - 568:./lib/fatfs/mmc.c **** { - 1350 .loc 1 568 0 - 1351 .cfi_startproc - 1352 @ args = 0, pretend = 0, frame = 16 - 1353 @ frame_needed = 0, uses_anonymous_args = 0 - 1354 .LVL192: - 569:./lib/fatfs/mmc.c **** DRESULT res; - 570:./lib/fatfs/mmc.c **** BYTE n, csd[16], *ptr = buff; - 571:./lib/fatfs/mmc.c **** DWORD csz; - 572:./lib/fatfs/mmc.c **** - 573:./lib/fatfs/mmc.c **** - 574:./lib/fatfs/mmc.c **** if (pdrv) return RES_PARERR; - 1355 .loc 1 574 0 - 1356 0000 0028 cmp r0, #0 - 1357 0002 40F02781 bne .L140 - 575:./lib/fatfs/mmc.c **** if (Stat & STA_NOINIT) return RES_NOTRDY; - 1358 .loc 1 575 0 - 1359 0006 964B ldr r3, .L158 - 1360 0008 1B78 ldrb r3, [r3] @ zero_extendqisi2 - 1361 000a 13F0010F tst r3, #1 - 1362 000e 40F02381 bne .L141 - 568:./lib/fatfs/mmc.c **** DRESULT res; - 1363 .loc 1 568 0 - 1364 0012 70B5 push {r4, r5, r6, lr} - 1365 .cfi_def_cfa_offset 16 - 1366 .cfi_offset 4, -16 - 1367 .cfi_offset 5, -12 - 1368 .cfi_offset 6, -8 - 1369 .cfi_offset 14, -4 - 1370 0014 84B0 sub sp, sp, #16 - 1371 .cfi_def_cfa_offset 32 - 1372 0016 1446 mov r4, r2 - 1373 .LVL193: - 576:./lib/fatfs/mmc.c **** - 577:./lib/fatfs/mmc.c **** res = RES_ERROR; - 578:./lib/fatfs/mmc.c **** switch (cmd) { - 1374 .loc 1 578 0 - 1375 0018 0E29 cmp r1, #14 - 1376 001a 00F20081 bhi .L142 - 1377 001e DFE811F0 tbh [pc, r1, lsl #1] - 1378 .L127: - 1379 0022 0F00 .2byte (.L126-.L127)/2 - 1380 0024 1500 .2byte (.L128-.L127)/2 - 1381 0026 FE00 .2byte (.L142-.L127)/2 - 1382 0028 5D00 .2byte (.L129-.L127)/2 - 1383 002a FE00 .2byte (.L142-.L127)/2 - 1384 002c FE00 .2byte (.L142-.L127)/2 - 1385 002e FE00 .2byte (.L142-.L127)/2 - 1386 0030 FE00 .2byte (.L142-.L127)/2 - 1387 0032 FE00 .2byte (.L142-.L127)/2 - 1388 0034 FE00 .2byte (.L142-.L127)/2 - 1389 0036 B800 .2byte (.L130-.L127)/2 - 1390 0038 BD00 .2byte (.L131-.L127)/2 - 1391 003a CB00 .2byte (.L132-.L127)/2 - 1392 003c D800 .2byte (.L133-.L127)/2 - 1393 003e E900 .2byte (.L134-.L127)/2 - 1394 .p2align 1 - 1395 .L126: - 579:./lib/fatfs/mmc.c **** case CTRL_SYNC : /* Flush write-back cache, Wait for end of internal process */ - 580:./lib/fatfs/mmc.c **** if (select()) res = RES_OK; - 1396 .loc 1 580 0 - 1397 0040 FFF7FEFF bl select - 1398 .LVL194: - 1399 0044 B0FA80F4 clz r4, r0 - 1400 .LVL195: - 1401 0048 6409 lsrs r4, r4, #5 - 1402 004a FFE0 b .L125 - 1403 .LVL196: - 1404 .L128: - 581:./lib/fatfs/mmc.c **** break; - 582:./lib/fatfs/mmc.c **** - 583:./lib/fatfs/mmc.c **** case GET_SECTOR_COUNT : /* Get number of sectors on the disk (WORD) */ - 584:./lib/fatfs/mmc.c **** if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { - 1405 .loc 1 584 0 - 1406 004c 0920 movs r0, #9 - 1407 .LVL197: - 1408 004e 0021 movs r1, #0 - 1409 .LVL198: - 1410 0050 FFF7FEFF bl send_cmd - 1411 .LVL199: - 1412 0054 0028 cmp r0, #0 - 1413 0056 40F0E480 bne .L143 - 1414 .loc 1 584 0 is_stmt 0 discriminator 1 - 1415 005a 6846 mov r0, sp - 1416 005c 1021 movs r1, #16 - 1417 005e FFF7FEFF bl rcvr_datablock - 1418 .LVL200: - 1419 0062 0028 cmp r0, #0 - 1420 0064 00F0DF80 beq .L144 - 585:./lib/fatfs/mmc.c **** if ((csd[0] >> 6) == 1) { /* SDv2? */ - 1421 .loc 1 585 0 is_stmt 1 - 1422 0068 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 - 1423 006c 9B09 lsrs r3, r3, #6 - 1424 006e 012B cmp r3, #1 - 1425 0070 10D1 bne .L135 - 1426 .LVL201: - 586:./lib/fatfs/mmc.c **** csz = csd[9] + ((WORD)csd[8] << 8) + ((DWORD)(csd[7] & 63) << 16) + 1; - 1427 .loc 1 586 0 - 1428 0072 9DF80730 ldrb r3, [sp, #7] @ zero_extendqisi2 - 1429 0076 03F03F03 and r3, r3, #63 - 1430 007a 1B04 lsls r3, r3, #16 - 1431 007c 591C adds r1, r3, #1 - 1432 007e 9DF80920 ldrb r2, [sp, #9] @ zero_extendqisi2 - 1433 0082 9DF80830 ldrb r3, [sp, #8] @ zero_extendqisi2 - 1434 .LVL202: - 1435 0086 02EB0323 add r3, r2, r3, lsl #8 - 1436 .LVL203: - 1437 008a 0B44 add r3, r3, r1 - 587:./lib/fatfs/mmc.c **** *(DWORD*)buff = csz << 10; - 1438 .loc 1 587 0 - 1439 008c 9B02 lsls r3, r3, #10 - 1440 008e 2360 str r3, [r4] - 588:./lib/fatfs/mmc.c **** } else { /* SDv1 or MMCv3 */ - 589:./lib/fatfs/mmc.c **** n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; - 590:./lib/fatfs/mmc.c **** csz = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; - 591:./lib/fatfs/mmc.c **** *(DWORD*)buff = csz << (n - 9); - 592:./lib/fatfs/mmc.c **** } - 593:./lib/fatfs/mmc.c **** res = RES_OK; - 1441 .loc 1 593 0 - 1442 0090 0024 movs r4, #0 - 1443 .LVL204: - 1444 0092 DBE0 b .L125 - 1445 .LVL205: - 1446 .L135: - 590:./lib/fatfs/mmc.c **** *(DWORD*)buff = csz << (n - 9); - 1447 .loc 1 590 0 - 1448 0094 9DF80820 ldrb r2, [sp, #8] @ zero_extendqisi2 - 1449 0098 9DF80730 ldrb r3, [sp, #7] @ zero_extendqisi2 - 1450 .LVL206: - 1451 009c 9B00 lsls r3, r3, #2 - 1452 .LVL207: - 1453 009e 03EB9213 add r3, r3, r2, lsr #6 - 1454 00a2 9DF80620 ldrb r2, [sp, #6] @ zero_extendqisi2 - 1455 00a6 02F00302 and r2, r2, #3 - 1456 00aa 03EB8223 add r3, r3, r2, lsl #10 - 1457 00ae 5A1C adds r2, r3, #1 - 589:./lib/fatfs/mmc.c **** csz = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; - 1458 .loc 1 589 0 - 1459 00b0 9DF80530 ldrb r3, [sp, #5] @ zero_extendqisi2 - 1460 00b4 03F00F03 and r3, r3, #15 - 1461 00b8 9DF80A10 ldrb r1, [sp, #10] @ zero_extendqisi2 - 1462 00bc 03EBD113 add r3, r3, r1, lsr #7 - 1463 00c0 0233 adds r3, r3, #2 - 1464 00c2 9DF80910 ldrb r1, [sp, #9] @ zero_extendqisi2 - 1465 00c6 01F00301 and r1, r1, #3 - 1466 00ca 03EB4103 add r3, r3, r1, lsl #1 - 591:./lib/fatfs/mmc.c **** } - 1467 .loc 1 591 0 - 1468 00ce DBB2 uxtb r3, r3 - 1469 00d0 093B subs r3, r3, #9 - 1470 00d2 02FA03F3 lsl r3, r2, r3 - 1471 00d6 2360 str r3, [r4] - 1472 .loc 1 593 0 - 1473 00d8 0024 movs r4, #0 - 1474 .LVL208: - 1475 00da B7E0 b .L125 - 1476 .LVL209: - 1477 .L129: - 594:./lib/fatfs/mmc.c **** } - 595:./lib/fatfs/mmc.c **** break; - 596:./lib/fatfs/mmc.c **** - 597:./lib/fatfs/mmc.c **** case GET_BLOCK_SIZE : /* Get erase block size in unit of sectors (DWORD) */ - 598:./lib/fatfs/mmc.c **** if (CardType & CT_SD2) { /* SDv2? */ - 1478 .loc 1 598 0 - 1479 00dc 614B ldr r3, .L158+4 - 1480 00de 1B68 ldr r3, [r3] - 1481 00e0 13F0040F tst r3, #4 - 1482 00e4 21D0 beq .L136 - 599:./lib/fatfs/mmc.c **** if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */ - 1483 .loc 1 599 0 - 1484 00e6 8D20 movs r0, #141 - 1485 .LVL210: - 1486 00e8 0021 movs r1, #0 - 1487 .LVL211: - 1488 00ea FFF7FEFF bl send_cmd - 1489 .LVL212: - 1490 00ee 0028 cmp r0, #0 - 1491 00f0 40F09B80 bne .L145 - 600:./lib/fatfs/mmc.c **** xchg_spi(0xFF); - 1492 .loc 1 600 0 - 1493 00f4 FF20 movs r0, #255 - 1494 00f6 FFF7FEFF bl xchg_spi - 1495 .LVL213: - 601:./lib/fatfs/mmc.c **** if (rcvr_datablock(csd, 16)) { /* Read partial block */ - 1496 .loc 1 601 0 - 1497 00fa 6846 mov r0, sp - 1498 00fc 1021 movs r1, #16 - 1499 00fe FFF7FEFF bl rcvr_datablock - 1500 .LVL214: - 1501 0102 0028 cmp r0, #0 - 1502 0104 00F09380 beq .L146 - 1503 0108 3025 movs r5, #48 - 602:./lib/fatfs/mmc.c **** for (n = 64 - 16; n; n--) xchg_spi(0xFF); /* Purge trailing data */ - 1504 .loc 1 602 0 - 1505 010a FF26 movs r6, #255 - 1506 .L137: - 1507 .LVL215: - 1508 .loc 1 602 0 is_stmt 0 discriminator 3 - 1509 010c 3046 mov r0, r6 - 1510 010e FFF7FEFF bl xchg_spi - 1511 .LVL216: - 1512 0112 6B1E subs r3, r5, #1 - 1513 0114 13F0FF05 ands r5, r3, #255 - 1514 .LVL217: - 1515 0118 F8D1 bne .L137 - 603:./lib/fatfs/mmc.c **** *(DWORD*)buff = 16UL << (csd[10] >> 4); - 1516 .loc 1 603 0 is_stmt 1 - 1517 011a 9DF80A20 ldrb r2, [sp, #10] @ zero_extendqisi2 - 1518 011e 1209 lsrs r2, r2, #4 - 1519 0120 1023 movs r3, #16 - 1520 0122 9340 lsls r3, r3, r2 - 1521 0124 2360 str r3, [r4] - 1522 .LVL218: - 604:./lib/fatfs/mmc.c **** res = RES_OK; - 1523 .loc 1 604 0 - 1524 0126 0024 movs r4, #0 - 1525 .LVL219: - 1526 0128 90E0 b .L125 - 1527 .LVL220: - 1528 .L136: - 605:./lib/fatfs/mmc.c **** } - 606:./lib/fatfs/mmc.c **** } - 607:./lib/fatfs/mmc.c **** } else { /* SDv1 or MMCv3 */ - 608:./lib/fatfs/mmc.c **** if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */ - 1529 .loc 1 608 0 - 1530 012a 0920 movs r0, #9 - 1531 .LVL221: - 1532 012c 0021 movs r1, #0 - 1533 .LVL222: - 1534 012e FFF7FEFF bl send_cmd - 1535 .LVL223: - 1536 0132 0028 cmp r0, #0 - 1537 0134 7DD1 bne .L147 - 1538 .loc 1 608 0 is_stmt 0 discriminator 1 - 1539 0136 6846 mov r0, sp - 1540 0138 1021 movs r1, #16 - 1541 013a FFF7FEFF bl rcvr_datablock - 1542 .LVL224: - 1543 013e 0028 cmp r0, #0 - 1544 0140 79D0 beq .L148 - 609:./lib/fatfs/mmc.c **** if (CardType & CT_SD1) { /* SDv1 */ - 1545 .loc 1 609 0 is_stmt 1 - 1546 0142 484B ldr r3, .L158+4 - 1547 0144 1B68 ldr r3, [r3] - 1548 0146 13F0020F tst r3, #2 - 1549 014a 11D0 beq .L138 - 610:./lib/fatfs/mmc.c **** *(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1550 .loc 1 610 0 - 1551 014c 9DF80A30 ldrb r3, [sp, #10] @ zero_extendqisi2 - 1552 0150 03F03F02 and r2, r3, #63 - 1553 0154 9DF80B30 ldrb r3, [sp, #11] @ zero_extendqisi2 - 1554 0158 DB09 lsrs r3, r3, #7 - 1555 015a 03EB4203 add r3, r3, r2, lsl #1 - 1556 015e 0133 adds r3, r3, #1 - 1557 0160 9DF80D20 ldrb r2, [sp, #13] @ zero_extendqisi2 - 1558 0164 9209 lsrs r2, r2, #6 - 1559 0166 013A subs r2, r2, #1 - 1560 0168 9340 lsls r3, r3, r2 - 1561 016a 2360 str r3, [r4] - 611:./lib/fatfs/mmc.c **** } else { /* MMCv3 */ - 612:./lib/fatfs/mmc.c **** *(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) - 613:./lib/fatfs/mmc.c **** } - 614:./lib/fatfs/mmc.c **** res = RES_OK; - 1562 .loc 1 614 0 - 1563 016c 0024 movs r4, #0 - 1564 .LVL225: - 1565 016e 6DE0 b .L125 - 1566 .LVL226: - 1567 .L138: - 612:./lib/fatfs/mmc.c **** } - 1568 .loc 1 612 0 - 1569 0170 9DF80B30 ldrb r3, [sp, #11] @ zero_extendqisi2 - 1570 0174 9DF80A10 ldrb r1, [sp, #10] @ zero_extendqisi2 - 1571 0178 C1F38401 ubfx r1, r1, #2, #5 - 1572 017c 03F00300 and r0, r3, #3 - 1573 0180 5A09 lsrs r2, r3, #5 - 1574 0182 02EBC002 add r2, r2, r0, lsl #3 - 1575 0186 531C adds r3, r2, #1 - 1576 0188 01FB0333 mla r3, r1, r3, r3 - 1577 018c 2360 str r3, [r4] - 1578 .loc 1 614 0 - 1579 018e 0024 movs r4, #0 - 1580 .LVL227: - 1581 0190 5CE0 b .L125 - 1582 .LVL228: - 1583 .L130: - 615:./lib/fatfs/mmc.c **** } - 616:./lib/fatfs/mmc.c **** } - 617:./lib/fatfs/mmc.c **** break; - 618:./lib/fatfs/mmc.c **** - 619:./lib/fatfs/mmc.c **** case MMC_GET_TYPE : /* Get card type flags (1 byte) */ - 620:./lib/fatfs/mmc.c **** *ptr = CardType; - 1584 .loc 1 620 0 - 1585 0192 344B ldr r3, .L158+4 - 1586 0194 1B68 ldr r3, [r3] - 1587 0196 1370 strb r3, [r2] - 1588 .LVL229: - 621:./lib/fatfs/mmc.c **** res = RES_OK; - 1589 .loc 1 621 0 - 1590 0198 0024 movs r4, #0 - 622:./lib/fatfs/mmc.c **** break; - 1591 .loc 1 622 0 - 1592 019a 57E0 b .L125 - 1593 .LVL230: - 1594 .L131: - 623:./lib/fatfs/mmc.c **** - 624:./lib/fatfs/mmc.c **** case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ - 625:./lib/fatfs/mmc.c **** if ((send_cmd(CMD9, 0) == 0) /* READ_CSD */ - 1595 .loc 1 625 0 - 1596 019c 0920 movs r0, #9 - 1597 .LVL231: - 1598 019e 0021 movs r1, #0 - 1599 .LVL232: - 1600 01a0 FFF7FEFF bl send_cmd - 1601 .LVL233: - 1602 01a4 0028 cmp r0, #0 - 1603 01a6 48D1 bne .L149 - 626:./lib/fatfs/mmc.c **** && rcvr_datablock(buff, 16)) - 1604 .loc 1 626 0 - 1605 01a8 2046 mov r0, r4 - 1606 01aa 1021 movs r1, #16 - 1607 01ac FFF7FEFF bl rcvr_datablock - 1608 .LVL234: - 580:./lib/fatfs/mmc.c **** break; - 1609 .loc 1 580 0 - 1610 01b0 B0FA80F4 clz r4, r0 - 1611 .LVL235: - 1612 01b4 6409 lsrs r4, r4, #5 - 1613 01b6 49E0 b .L125 - 1614 .LVL236: - 1615 .L132: - 627:./lib/fatfs/mmc.c **** res = RES_OK; - 628:./lib/fatfs/mmc.c **** break; - 629:./lib/fatfs/mmc.c **** - 630:./lib/fatfs/mmc.c **** case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ - 631:./lib/fatfs/mmc.c **** if ((send_cmd(CMD10, 0) == 0) /* READ_CID */ - 1616 .loc 1 631 0 - 1617 01b8 0A20 movs r0, #10 - 1618 .LVL237: - 1619 01ba 0021 movs r1, #0 - 1620 .LVL238: - 1621 01bc FFF7FEFF bl send_cmd - 1622 .LVL239: - 1623 01c0 E8BB cbnz r0, .L150 - 632:./lib/fatfs/mmc.c **** && rcvr_datablock(buff, 16)) - 1624 .loc 1 632 0 - 1625 01c2 2046 mov r0, r4 - 1626 01c4 1021 movs r1, #16 - 1627 01c6 FFF7FEFF bl rcvr_datablock - 1628 .LVL240: - 580:./lib/fatfs/mmc.c **** break; - 1629 .loc 1 580 0 - 1630 01ca B0FA80F4 clz r4, r0 - 1631 .LVL241: - 1632 01ce 6409 lsrs r4, r4, #5 - 1633 01d0 3CE0 b .L125 - 1634 .LVL242: - 1635 .L133: - 633:./lib/fatfs/mmc.c **** res = RES_OK; - 634:./lib/fatfs/mmc.c **** break; - 635:./lib/fatfs/mmc.c **** - 636:./lib/fatfs/mmc.c **** case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ - 637:./lib/fatfs/mmc.c **** if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ - 1636 .loc 1 637 0 - 1637 01d2 3A20 movs r0, #58 - 1638 .LVL243: - 1639 01d4 0021 movs r1, #0 - 1640 .LVL244: - 1641 01d6 FFF7FEFF bl send_cmd - 1642 .LVL245: - 1643 01da 90BB cbnz r0, .L151 - 1644 01dc 651E subs r5, r4, #1 - 1645 01de 0334 adds r4, r4, #3 - 1646 .LVL246: - 638:./lib/fatfs/mmc.c **** for (n = 0; n < 4; n++) - 639:./lib/fatfs/mmc.c **** *((BYTE*)buff+n) = xchg_spi(0xFF); - 1647 .loc 1 639 0 - 1648 01e0 FF26 movs r6, #255 - 1649 .L139: - 1650 .LVL247: - 1651 .loc 1 639 0 is_stmt 0 discriminator 3 - 1652 01e2 3046 mov r0, r6 - 1653 01e4 FFF7FEFF bl xchg_spi - 1654 .LVL248: - 1655 01e8 05F8010F strb r0, [r5, #1]! - 1656 .LVL249: - 638:./lib/fatfs/mmc.c **** for (n = 0; n < 4; n++) - 1657 .loc 1 638 0 is_stmt 1 discriminator 3 - 1658 01ec A542 cmp r5, r4 - 1659 01ee F8D1 bne .L139 - 640:./lib/fatfs/mmc.c **** res = RES_OK; - 1660 .loc 1 640 0 - 1661 01f0 0024 movs r4, #0 - 1662 .LVL250: - 1663 01f2 2BE0 b .L125 - 1664 .LVL251: - 1665 .L134: - 641:./lib/fatfs/mmc.c **** } - 642:./lib/fatfs/mmc.c **** break; - 643:./lib/fatfs/mmc.c **** - 644:./lib/fatfs/mmc.c **** case MMC_GET_SDSTAT : /* Receive SD status as a data block (64 bytes) */ - 645:./lib/fatfs/mmc.c **** if ((CardType & CT_SD2) && send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ - 1666 .loc 1 645 0 - 1667 01f4 1B4B ldr r3, .L158+4 - 1668 01f6 1B68 ldr r3, [r3] - 1669 01f8 13F0040F tst r3, #4 - 1670 01fc 23D0 beq .L152 - 1671 .loc 1 645 0 is_stmt 0 discriminator 1 - 1672 01fe 8D20 movs r0, #141 - 1673 .LVL252: - 1674 0200 0021 movs r1, #0 - 1675 .LVL253: - 1676 0202 FFF7FEFF bl send_cmd - 1677 .LVL254: - 1678 0206 00BB cbnz r0, .L153 - 646:./lib/fatfs/mmc.c **** xchg_spi(0xFF); - 1679 .loc 1 646 0 is_stmt 1 - 1680 0208 FF20 movs r0, #255 - 1681 020a FFF7FEFF bl xchg_spi - 1682 .LVL255: - 647:./lib/fatfs/mmc.c **** if (rcvr_datablock(buff, 64)) - 1683 .loc 1 647 0 - 1684 020e 2046 mov r0, r4 - 1685 0210 4021 movs r1, #64 - 1686 0212 FFF7FEFF bl rcvr_datablock - 1687 .LVL256: - 580:./lib/fatfs/mmc.c **** break; - 1688 .loc 1 580 0 - 1689 0216 B0FA80F4 clz r4, r0 - 1690 .LVL257: - 1691 021a 6409 lsrs r4, r4, #5 - 1692 021c 16E0 b .L125 - 1693 .LVL258: - 1694 .L142: - 648:./lib/fatfs/mmc.c **** res = RES_OK; - 649:./lib/fatfs/mmc.c **** } - 650:./lib/fatfs/mmc.c **** break; - 651:./lib/fatfs/mmc.c **** - 652:./lib/fatfs/mmc.c **** default: - 653:./lib/fatfs/mmc.c **** res = RES_PARERR; - 1695 .loc 1 653 0 - 1696 021e 0424 movs r4, #4 - 1697 0220 14E0 b .L125 - 1698 .LVL259: - 1699 .L143: - 577:./lib/fatfs/mmc.c **** switch (cmd) { - 1700 .loc 1 577 0 - 1701 0222 0124 movs r4, #1 - 1702 .LVL260: - 1703 0224 12E0 b .L125 - 1704 .LVL261: - 1705 .L144: - 1706 0226 0124 movs r4, #1 - 1707 .LVL262: - 1708 0228 10E0 b .L125 - 1709 .LVL263: - 1710 .L145: - 1711 022a 0124 movs r4, #1 - 1712 .LVL264: - 1713 022c 0EE0 b .L125 - 1714 .LVL265: - 1715 .L146: - 1716 022e 0124 movs r4, #1 - 1717 .LVL266: - 1718 0230 0CE0 b .L125 - 1719 .LVL267: - 1720 .L147: - 1721 0232 0124 movs r4, #1 - 1722 .LVL268: - 1723 0234 0AE0 b .L125 - 1724 .LVL269: - 1725 .L148: - 1726 0236 0124 movs r4, #1 - 1727 .LVL270: - 1728 0238 08E0 b .L125 - 1729 .LVL271: - 1730 .L149: - 1731 023a 0124 movs r4, #1 - 1732 .LVL272: - 1733 023c 06E0 b .L125 - 1734 .LVL273: - 1735 .L150: - 1736 023e 0124 movs r4, #1 - 1737 .LVL274: - 1738 0240 04E0 b .L125 - 1739 .LVL275: - 1740 .L151: - 1741 0242 0124 movs r4, #1 - 1742 .LVL276: - 1743 0244 02E0 b .L125 - 1744 .LVL277: - 1745 .L152: - 1746 0246 0124 movs r4, #1 - 1747 0248 00E0 b .L125 - 1748 .LVL278: - 1749 .L153: - 1750 024a 0124 movs r4, #1 - 1751 .LVL279: - 1752 .L125: - 654:./lib/fatfs/mmc.c **** } - 655:./lib/fatfs/mmc.c **** - 656:./lib/fatfs/mmc.c **** deselect(); - 1753 .loc 1 656 0 - 1754 024c FFF7FEFF bl deselect - 1755 .LVL280: - 657:./lib/fatfs/mmc.c **** - 658:./lib/fatfs/mmc.c **** return res; - 1756 .loc 1 658 0 - 1757 0250 2046 mov r0, r4 - 1758 0252 03E0 b .L124 - 1759 .LVL281: - 1760 .L140: - 1761 .cfi_def_cfa_offset 0 - 1762 .cfi_restore 4 - 1763 .cfi_restore 5 - 1764 .cfi_restore 6 - 1765 .cfi_restore 14 - 574:./lib/fatfs/mmc.c **** if (Stat & STA_NOINIT) return RES_NOTRDY; - 1766 .loc 1 574 0 - 1767 0254 0420 movs r0, #4 - 1768 .LVL282: - 1769 0256 7047 bx lr - 1770 .LVL283: - 1771 .L141: - 575:./lib/fatfs/mmc.c **** - 1772 .loc 1 575 0 - 1773 0258 0320 movs r0, #3 - 1774 .LVL284: - 1775 025a 7047 bx lr - 1776 .LVL285: - 1777 .L124: - 1778 .cfi_def_cfa_offset 32 - 1779 .cfi_offset 4, -16 - 1780 .cfi_offset 5, -12 - 1781 .cfi_offset 6, -8 - 1782 .cfi_offset 14, -4 - 659:./lib/fatfs/mmc.c **** } - 1783 .loc 1 659 0 - 1784 025c 04B0 add sp, sp, #16 - 1785 .cfi_def_cfa_offset 16 - 1786 @ sp needed - 1787 025e 70BD pop {r4, r5, r6, pc} - 1788 .LVL286: - 1789 .L159: - 1790 .align 2 - 1791 .L158: - 1792 0260 00000000 .word .LANCHOR0 - 1793 0264 00000000 .word .LANCHOR1 - 1794 .cfi_endproc - 1795 .LFE45: - 1797 .section .text.get_fattime,"ax",%progbits - 1798 .align 2 - 1799 .global get_fattime - 1800 .thumb - 1801 .thumb_func - 1803 get_fattime: - 1804 .LFB46: - 660:./lib/fatfs/mmc.c **** #endif - 661:./lib/fatfs/mmc.c **** - 662:./lib/fatfs/mmc.c **** - 663:./lib/fatfs/mmc.c **** /*---------------------------------------------------------*/ - 664:./lib/fatfs/mmc.c **** /* User Provided Timer Function for FatFs module */ - 665:./lib/fatfs/mmc.c **** /*---------------------------------------------------------*/ - 666:./lib/fatfs/mmc.c **** /* This is a real time clock service to be called from */ - 667:./lib/fatfs/mmc.c **** /* FatFs module. Any valid time must be returned even if */ - 668:./lib/fatfs/mmc.c **** /* the system does not support a real time clock. */ - 669:./lib/fatfs/mmc.c **** /* This is not required in read-only configuration. */ - 670:./lib/fatfs/mmc.c **** - 671:./lib/fatfs/mmc.c **** DWORD get_fattime (void) - 672:./lib/fatfs/mmc.c **** { - 1805 .loc 1 672 0 - 1806 .cfi_startproc - 1807 @ args = 0, pretend = 0, frame = 0 - 1808 @ frame_needed = 0, uses_anonymous_args = 0 - 1809 @ link register save eliminated. - 673:./lib/fatfs/mmc.c **** /* No RTC supprt. Return a fixed value 2013/5/10 0:00:00 */ - 674:./lib/fatfs/mmc.c **** return ((DWORD)(2013 - 1980) << 25) /* Y */ - 675:./lib/fatfs/mmc.c **** | ((DWORD)5 << 21) /* M */ - 676:./lib/fatfs/mmc.c **** | ((DWORD)10 << 16) /* D */ - 677:./lib/fatfs/mmc.c **** | ((DWORD)0 << 11) /* H */ - 678:./lib/fatfs/mmc.c **** | ((DWORD)0 << 5) /* M */ - 679:./lib/fatfs/mmc.c **** | ((DWORD)0 >> 1); /* S */ - 680:./lib/fatfs/mmc.c **** } - 1810 .loc 1 680 0 - 1811 0000 0048 ldr r0, .L161 - 1812 0002 7047 bx lr - 1813 .L162: - 1814 .align 2 - 1815 .L161: - 1816 0004 0000AA42 .word 1118437376 - 1817 .cfi_endproc - 1818 .LFE46: - 1820 .section .bss.CardType,"aw",%nobits - 1821 .align 2 - 1822 .set .LANCHOR1,. + 0 - 1825 CardType: - 1826 0000 00000000 .space 4 - 1827 .section .data.Stat,"aw",%progbits - 1828 .set .LANCHOR0,. + 0 - 1831 Stat: - 1832 0000 01 .byte 1 - 1833 .text - 1834 .Letext0: - 1835 .file 2 "../../../Source/third_party/fatfs/src/integer.h" - 1836 .file 3 "../../../Source/third_party/fatfs/src/diskio.h" - 1837 .file 4 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\mach - 1838 .file 5 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\stdi - 1839 .file 6 "./lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h" - 1840 .file 7 "./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h" - 1841 .file 8 "./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h" - 1842 .file 9 "../../../Source/ARMCM3_STM32/types.h" - 1843 .file 10 "./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h" - 1844 .file 11 "./lib/CMSIS/CM3/CoreSupport/core_cm3.h" - 1845 .file 12 "../../../Source/ARMCM3_STM32/timer.h" -DEFINED SYMBOLS - *ABS*:00000000 mmc.c -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:19 .text.xchg_spi:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:23 .text.xchg_spi:00000000 xchg_spi -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:64 .text.xchg_spi:00000024 $d -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:69 .text.wait_ready:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:73 .text.wait_ready:00000000 wait_ready -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:118 .text.deselect:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:122 .text.deselect:00000000 deselect -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:145 .text.deselect:00000014 $d -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:150 .text.select:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:154 .text.select:00000000 select -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:193 .text.select:00000028 $d -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:198 .text.send_cmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:202 .text.send_cmd:00000000 send_cmd -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:324 .text.xmit_datablock:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:328 .text.xmit_datablock:00000000 xmit_datablock -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:405 .text.rcvr_datablock:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:409 .text.rcvr_datablock:00000000 rcvr_datablock -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:506 .text.disk_initialize:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:511 .text.disk_initialize:00000000 disk_initialize -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:991 .text.disk_initialize:000002d0 $d -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:999 .text.disk_status:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1004 .text.disk_status:00000000 disk_status -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1030 .text.disk_status:00000010 $d -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1035 .text.disk_read:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1040 .text.disk_read:00000000 disk_read -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1170 .text.disk_read:00000088 $d -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1176 .text.disk_write:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1181 .text.disk_write:00000000 disk_write -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1337 .text.disk_write:000000a8 $d -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1343 .text.disk_ioctl:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1348 .text.disk_ioctl:00000000 disk_ioctl -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1379 .text.disk_ioctl:00000022 $d -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1394 .text.disk_ioctl:00000040 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1792 .text.disk_ioctl:00000260 $d -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1798 .text.get_fattime:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1803 .text.get_fattime:00000000 get_fattime -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1816 .text.get_fattime:00000004 $d -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1821 .bss.CardType:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1825 .bss.CardType:00000000 CardType -C:\Users\lwngim1\AppData\Local\Temp\cczeyUZQ.s:1831 .data.Stat:00000000 Stat - .debug_frame:00000010 $d - -UNDEFINED SYMBOLS -SPI_I2S_SendData -SPI_I2S_GetFlagStatus -SPI_I2S_ReceiveData -TimerGet -GPIO_SetBits -GPIO_ResetBits -RCC_APB2PeriphClockCmd -RCC_APB1PeriphClockCmd -GPIO_Init -SPI_Init -SPI_CalculateCRC -SPI_Cmd diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/nvm.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/nvm.lst deleted file mode 100644 index 2ff47247..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/nvm.lst +++ /dev/null @@ -1,375 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "nvm.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.NvmInit,"ax",%progbits - 19 .align 2 - 20 .global NvmInit - 21 .thumb - 22 .thumb_func - 24 NvmInit: - 25 .LFB0: - 26 .file 1 "../../../Source/ARMCM3_STM32/nvm.c" - 1:../../../Source/ARMCM3_STM32/nvm.c **** /************************************************************************************//** - 2:../../../Source/ARMCM3_STM32/nvm.c **** * \file Source\ARMCM3_STM32\nvm.c - 3:../../../Source/ARMCM3_STM32/nvm.c **** * \brief Bootloader non-volatile memory driver source file. - 4:../../../Source/ARMCM3_STM32/nvm.c **** * \ingroup Target_ARMCM3_STM32 - 5:../../../Source/ARMCM3_STM32/nvm.c **** * \internal - 6:../../../Source/ARMCM3_STM32/nvm.c **** *---------------------------------------------------------------------------------------- - 7:../../../Source/ARMCM3_STM32/nvm.c **** * C O P Y R I G H T - 8:../../../Source/ARMCM3_STM32/nvm.c **** *---------------------------------------------------------------------------------------- - 9:../../../Source/ARMCM3_STM32/nvm.c **** * Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved - 10:../../../Source/ARMCM3_STM32/nvm.c **** * - 11:../../../Source/ARMCM3_STM32/nvm.c **** *---------------------------------------------------------------------------------------- - 12:../../../Source/ARMCM3_STM32/nvm.c **** * L I C E N S E - 13:../../../Source/ARMCM3_STM32/nvm.c **** *---------------------------------------------------------------------------------------- - 14:../../../Source/ARMCM3_STM32/nvm.c **** * This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or - 15:../../../Source/ARMCM3_STM32/nvm.c **** * modify it under the terms of the GNU General Public License as published by the Free - 16:../../../Source/ARMCM3_STM32/nvm.c **** * Software Foundation, either version 3 of the License, or (at your option) any later - 17:../../../Source/ARMCM3_STM32/nvm.c **** * version. - 18:../../../Source/ARMCM3_STM32/nvm.c **** * - 19:../../../Source/ARMCM3_STM32/nvm.c **** * OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; - 20:../../../Source/ARMCM3_STM32/nvm.c **** * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - 21:../../../Source/ARMCM3_STM32/nvm.c **** * PURPOSE. See the GNU General Public License for more details. - 22:../../../Source/ARMCM3_STM32/nvm.c **** * - 23:../../../Source/ARMCM3_STM32/nvm.c **** * You should have received a copy of the GNU General Public License along with OpenBLT. - 24:../../../Source/ARMCM3_STM32/nvm.c **** * If not, see . - 25:../../../Source/ARMCM3_STM32/nvm.c **** * - 26:../../../Source/ARMCM3_STM32/nvm.c **** * A special exception to the GPL is included to allow you to distribute a combined work - 27:../../../Source/ARMCM3_STM32/nvm.c **** * that includes OpenBLT without being obliged to provide the source code for any - 28:../../../Source/ARMCM3_STM32/nvm.c **** * proprietary components. The exception text is included at the bottom of the license - 29:../../../Source/ARMCM3_STM32/nvm.c **** * file . - 30:../../../Source/ARMCM3_STM32/nvm.c **** * - 31:../../../Source/ARMCM3_STM32/nvm.c **** * \endinternal - 32:../../../Source/ARMCM3_STM32/nvm.c **** ****************************************************************************************/ - 33:../../../Source/ARMCM3_STM32/nvm.c **** - 34:../../../Source/ARMCM3_STM32/nvm.c **** /**************************************************************************************** - 35:../../../Source/ARMCM3_STM32/nvm.c **** * Include files - 36:../../../Source/ARMCM3_STM32/nvm.c **** ****************************************************************************************/ - 37:../../../Source/ARMCM3_STM32/nvm.c **** #include "boot.h" /* bootloader generic header */ - 38:../../../Source/ARMCM3_STM32/nvm.c **** - 39:../../../Source/ARMCM3_STM32/nvm.c **** - 40:../../../Source/ARMCM3_STM32/nvm.c **** /**************************************************************************************** - 41:../../../Source/ARMCM3_STM32/nvm.c **** * Hook functions - 42:../../../Source/ARMCM3_STM32/nvm.c **** ****************************************************************************************/ - 43:../../../Source/ARMCM3_STM32/nvm.c **** #if (BOOT_NVM_HOOKS_ENABLE > 0) - 44:../../../Source/ARMCM3_STM32/nvm.c **** extern void NvmInitHook(void); - 45:../../../Source/ARMCM3_STM32/nvm.c **** extern blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data); - 46:../../../Source/ARMCM3_STM32/nvm.c **** extern blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len); - 47:../../../Source/ARMCM3_STM32/nvm.c **** extern blt_bool NvmDoneHook(void); - 48:../../../Source/ARMCM3_STM32/nvm.c **** #endif - 49:../../../Source/ARMCM3_STM32/nvm.c **** - 50:../../../Source/ARMCM3_STM32/nvm.c **** #if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) - 51:../../../Source/ARMCM3_STM32/nvm.c **** extern blt_bool NvmWriteChecksumHook(void); - 52:../../../Source/ARMCM3_STM32/nvm.c **** extern blt_bool NvmVerifyChecksumHook(void); - 53:../../../Source/ARMCM3_STM32/nvm.c **** #endif - 54:../../../Source/ARMCM3_STM32/nvm.c **** - 55:../../../Source/ARMCM3_STM32/nvm.c **** - 56:../../../Source/ARMCM3_STM32/nvm.c **** - 57:../../../Source/ARMCM3_STM32/nvm.c **** /************************************************************************************//** - 58:../../../Source/ARMCM3_STM32/nvm.c **** ** \brief Initializes the NVM driver. - 59:../../../Source/ARMCM3_STM32/nvm.c **** ** \return none. - 60:../../../Source/ARMCM3_STM32/nvm.c **** ** - 61:../../../Source/ARMCM3_STM32/nvm.c **** ****************************************************************************************/ - 62:../../../Source/ARMCM3_STM32/nvm.c **** void NvmInit(void) - 63:../../../Source/ARMCM3_STM32/nvm.c **** { - 27 .loc 1 63 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 0000 08B5 push {r3, lr} - 32 .cfi_def_cfa_offset 8 - 33 .cfi_offset 3, -8 - 34 .cfi_offset 14, -4 - 64:../../../Source/ARMCM3_STM32/nvm.c **** #if (BOOT_NVM_HOOKS_ENABLE > 0) - 65:../../../Source/ARMCM3_STM32/nvm.c **** /* give the application a chance to initialize a driver for operating on NVM - 66:../../../Source/ARMCM3_STM32/nvm.c **** * that is not by default supported by this driver. - 67:../../../Source/ARMCM3_STM32/nvm.c **** */ - 68:../../../Source/ARMCM3_STM32/nvm.c **** NvmInitHook(); - 69:../../../Source/ARMCM3_STM32/nvm.c **** #endif - 70:../../../Source/ARMCM3_STM32/nvm.c **** - 71:../../../Source/ARMCM3_STM32/nvm.c **** /* init the internal driver */ - 72:../../../Source/ARMCM3_STM32/nvm.c **** FlashInit(); - 35 .loc 1 72 0 - 36 0002 FFF7FEFF bl FlashInit - 37 .LVL0: - 38 0006 08BD pop {r3, pc} - 39 .cfi_endproc - 40 .LFE0: - 42 .section .text.NvmWrite,"ax",%progbits - 43 .align 2 - 44 .global NvmWrite - 45 .thumb - 46 .thumb_func - 48 NvmWrite: - 49 .LFB1: - 73:../../../Source/ARMCM3_STM32/nvm.c **** } /*** end of NvmInit ***/ - 74:../../../Source/ARMCM3_STM32/nvm.c **** - 75:../../../Source/ARMCM3_STM32/nvm.c **** - 76:../../../Source/ARMCM3_STM32/nvm.c **** /************************************************************************************//** - 77:../../../Source/ARMCM3_STM32/nvm.c **** ** \brief Programs the non-volatile memory. - 78:../../../Source/ARMCM3_STM32/nvm.c **** ** \param addr Start address. - 79:../../../Source/ARMCM3_STM32/nvm.c **** ** \param len Length in bytes. - 80:../../../Source/ARMCM3_STM32/nvm.c **** ** \param data Pointer to the data buffer. - 81:../../../Source/ARMCM3_STM32/nvm.c **** ** \return BLT_TRUE if successful, BLT_FALSE otherwise. - 82:../../../Source/ARMCM3_STM32/nvm.c **** ** - 83:../../../Source/ARMCM3_STM32/nvm.c **** ****************************************************************************************/ - 84:../../../Source/ARMCM3_STM32/nvm.c **** blt_bool NvmWrite(blt_addr addr, blt_int32u len, blt_int8u *data) - 85:../../../Source/ARMCM3_STM32/nvm.c **** { - 50 .loc 1 85 0 - 51 .cfi_startproc - 52 @ args = 0, pretend = 0, frame = 0 - 53 @ frame_needed = 0, uses_anonymous_args = 0 - 54 .LVL1: - 55 0000 08B5 push {r3, lr} - 56 .cfi_def_cfa_offset 8 - 57 .cfi_offset 3, -8 - 58 .cfi_offset 14, -4 - 86:../../../Source/ARMCM3_STM32/nvm.c **** #if (BOOT_NVM_HOOKS_ENABLE > 0) - 87:../../../Source/ARMCM3_STM32/nvm.c **** blt_int8u result = BLT_NVM_NOT_IN_RANGE; - 88:../../../Source/ARMCM3_STM32/nvm.c **** #endif - 89:../../../Source/ARMCM3_STM32/nvm.c **** - 90:../../../Source/ARMCM3_STM32/nvm.c **** #if (BOOT_NVM_HOOKS_ENABLE > 0) - 91:../../../Source/ARMCM3_STM32/nvm.c **** /* give the application a chance to operate on memory that is not by default supported - 92:../../../Source/ARMCM3_STM32/nvm.c **** * by this driver. - 93:../../../Source/ARMCM3_STM32/nvm.c **** */ - 94:../../../Source/ARMCM3_STM32/nvm.c **** result = NvmWriteHook(addr, len, data); - 95:../../../Source/ARMCM3_STM32/nvm.c **** - 96:../../../Source/ARMCM3_STM32/nvm.c **** /* process the return code */ - 97:../../../Source/ARMCM3_STM32/nvm.c **** if (result == BLT_NVM_OKAY) - 98:../../../Source/ARMCM3_STM32/nvm.c **** { - 99:../../../Source/ARMCM3_STM32/nvm.c **** /* data was within range of the additionally supported memory and succesfully - 100:../../../Source/ARMCM3_STM32/nvm.c **** * programmed, so we are all done. - 101:../../../Source/ARMCM3_STM32/nvm.c **** */ - 102:../../../Source/ARMCM3_STM32/nvm.c **** return BLT_TRUE; - 103:../../../Source/ARMCM3_STM32/nvm.c **** } - 104:../../../Source/ARMCM3_STM32/nvm.c **** else if (result == BLT_NVM_ERROR) - 105:../../../Source/ARMCM3_STM32/nvm.c **** { - 106:../../../Source/ARMCM3_STM32/nvm.c **** /* data was within range of the additionally supported memory and attempted to be - 107:../../../Source/ARMCM3_STM32/nvm.c **** * programmed, but an error occurred, so we can't continue. - 108:../../../Source/ARMCM3_STM32/nvm.c **** */ - 109:../../../Source/ARMCM3_STM32/nvm.c **** return BLT_FALSE; - 110:../../../Source/ARMCM3_STM32/nvm.c **** } - 111:../../../Source/ARMCM3_STM32/nvm.c **** #endif - 112:../../../Source/ARMCM3_STM32/nvm.c **** - 113:../../../Source/ARMCM3_STM32/nvm.c **** /* still here so the internal driver should try and perform the program operation */ - 114:../../../Source/ARMCM3_STM32/nvm.c **** return FlashWrite(addr, len, data); - 59 .loc 1 114 0 - 60 0002 FFF7FEFF bl FlashWrite - 61 .LVL2: - 115:../../../Source/ARMCM3_STM32/nvm.c **** } /*** end of NvmWrite ***/ - 62 .loc 1 115 0 - 63 0006 08BD pop {r3, pc} - 64 .cfi_endproc - 65 .LFE1: - 67 .section .text.NvmErase,"ax",%progbits - 68 .align 2 - 69 .global NvmErase - 70 .thumb - 71 .thumb_func - 73 NvmErase: - 74 .LFB2: - 116:../../../Source/ARMCM3_STM32/nvm.c **** - 117:../../../Source/ARMCM3_STM32/nvm.c **** - 118:../../../Source/ARMCM3_STM32/nvm.c **** /************************************************************************************//** - 119:../../../Source/ARMCM3_STM32/nvm.c **** ** \brief Erases the non-volatile memory. - 120:../../../Source/ARMCM3_STM32/nvm.c **** ** \param addr Start address. - 121:../../../Source/ARMCM3_STM32/nvm.c **** ** \param len Length in bytes. - 122:../../../Source/ARMCM3_STM32/nvm.c **** ** \return BLT_TRUE if successful, BLT_FALSE otherwise. - 123:../../../Source/ARMCM3_STM32/nvm.c **** ** - 124:../../../Source/ARMCM3_STM32/nvm.c **** ****************************************************************************************/ - 125:../../../Source/ARMCM3_STM32/nvm.c **** blt_bool NvmErase(blt_addr addr, blt_int32u len) - 126:../../../Source/ARMCM3_STM32/nvm.c **** { - 75 .loc 1 126 0 - 76 .cfi_startproc - 77 @ args = 0, pretend = 0, frame = 0 - 78 @ frame_needed = 0, uses_anonymous_args = 0 - 79 .LVL3: - 80 0000 08B5 push {r3, lr} - 81 .cfi_def_cfa_offset 8 - 82 .cfi_offset 3, -8 - 83 .cfi_offset 14, -4 - 127:../../../Source/ARMCM3_STM32/nvm.c **** #if (BOOT_NVM_HOOKS_ENABLE > 0) - 128:../../../Source/ARMCM3_STM32/nvm.c **** blt_int8u result = BLT_NVM_NOT_IN_RANGE; - 129:../../../Source/ARMCM3_STM32/nvm.c **** #endif - 130:../../../Source/ARMCM3_STM32/nvm.c **** - 131:../../../Source/ARMCM3_STM32/nvm.c **** #if (BOOT_NVM_HOOKS_ENABLE > 0) - 132:../../../Source/ARMCM3_STM32/nvm.c **** /* give the application a chance to operate on memory that is not by default supported - 133:../../../Source/ARMCM3_STM32/nvm.c **** * by this driver. - 134:../../../Source/ARMCM3_STM32/nvm.c **** */ - 135:../../../Source/ARMCM3_STM32/nvm.c **** result = NvmEraseHook(addr, len); - 136:../../../Source/ARMCM3_STM32/nvm.c **** - 137:../../../Source/ARMCM3_STM32/nvm.c **** /* process the return code */ - 138:../../../Source/ARMCM3_STM32/nvm.c **** if (result == BLT_NVM_OKAY) - 139:../../../Source/ARMCM3_STM32/nvm.c **** { - 140:../../../Source/ARMCM3_STM32/nvm.c **** /* address was within range of the additionally supported memory and succesfully - 141:../../../Source/ARMCM3_STM32/nvm.c **** * erased, so we are all done. - 142:../../../Source/ARMCM3_STM32/nvm.c **** */ - 143:../../../Source/ARMCM3_STM32/nvm.c **** return BLT_TRUE; - 144:../../../Source/ARMCM3_STM32/nvm.c **** } - 145:../../../Source/ARMCM3_STM32/nvm.c **** else if (result == BLT_NVM_ERROR) - 146:../../../Source/ARMCM3_STM32/nvm.c **** { - 147:../../../Source/ARMCM3_STM32/nvm.c **** /* address was within range of the additionally supported memory and attempted to be - 148:../../../Source/ARMCM3_STM32/nvm.c **** * erased, but an error occurred, so we can't continue. - 149:../../../Source/ARMCM3_STM32/nvm.c **** */ - 150:../../../Source/ARMCM3_STM32/nvm.c **** return BLT_FALSE; - 151:../../../Source/ARMCM3_STM32/nvm.c **** } - 152:../../../Source/ARMCM3_STM32/nvm.c **** #endif - 153:../../../Source/ARMCM3_STM32/nvm.c **** - 154:../../../Source/ARMCM3_STM32/nvm.c **** /* still here so the internal driver should try and perform the erase operation */ - 155:../../../Source/ARMCM3_STM32/nvm.c **** return FlashErase(addr, len); - 84 .loc 1 155 0 - 85 0002 FFF7FEFF bl FlashErase - 86 .LVL4: - 156:../../../Source/ARMCM3_STM32/nvm.c **** } /*** end of NvmErase ***/ - 87 .loc 1 156 0 - 88 0006 08BD pop {r3, pc} - 89 .cfi_endproc - 90 .LFE2: - 92 .section .text.NvmVerifyChecksum,"ax",%progbits - 93 .align 2 - 94 .global NvmVerifyChecksum - 95 .thumb - 96 .thumb_func - 98 NvmVerifyChecksum: - 99 .LFB3: - 157:../../../Source/ARMCM3_STM32/nvm.c **** - 158:../../../Source/ARMCM3_STM32/nvm.c **** - 159:../../../Source/ARMCM3_STM32/nvm.c **** /************************************************************************************//** - 160:../../../Source/ARMCM3_STM32/nvm.c **** ** \brief Verifies the checksum, which indicates that a valid user program is - 161:../../../Source/ARMCM3_STM32/nvm.c **** ** present and can be started. - 162:../../../Source/ARMCM3_STM32/nvm.c **** ** \return BLT_TRUE if successful, BLT_FALSE otherwise. - 163:../../../Source/ARMCM3_STM32/nvm.c **** ** - 164:../../../Source/ARMCM3_STM32/nvm.c **** ****************************************************************************************/ - 165:../../../Source/ARMCM3_STM32/nvm.c **** blt_bool NvmVerifyChecksum(void) - 166:../../../Source/ARMCM3_STM32/nvm.c **** { - 100 .loc 1 166 0 - 101 .cfi_startproc - 102 @ args = 0, pretend = 0, frame = 0 - 103 @ frame_needed = 0, uses_anonymous_args = 0 - 104 0000 08B5 push {r3, lr} - 105 .cfi_def_cfa_offset 8 - 106 .cfi_offset 3, -8 - 107 .cfi_offset 14, -4 - 167:../../../Source/ARMCM3_STM32/nvm.c **** #if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) - 168:../../../Source/ARMCM3_STM32/nvm.c **** /* check checksum using the application specific method. */ - 169:../../../Source/ARMCM3_STM32/nvm.c **** return NvmVerifyChecksumHook(); - 170:../../../Source/ARMCM3_STM32/nvm.c **** #else - 171:../../../Source/ARMCM3_STM32/nvm.c **** /* check checksum using the interally supported method. */ - 172:../../../Source/ARMCM3_STM32/nvm.c **** return FlashVerifyChecksum(); - 108 .loc 1 172 0 - 109 0002 FFF7FEFF bl FlashVerifyChecksum - 110 .LVL5: - 173:../../../Source/ARMCM3_STM32/nvm.c **** #endif - 174:../../../Source/ARMCM3_STM32/nvm.c **** } /*** end of NvmVerifyChecksum ***/ - 111 .loc 1 174 0 - 112 0006 08BD pop {r3, pc} - 113 .cfi_endproc - 114 .LFE3: - 116 .section .text.NvmDone,"ax",%progbits - 117 .align 2 - 118 .global NvmDone - 119 .thumb - 120 .thumb_func - 122 NvmDone: - 123 .LFB4: - 175:../../../Source/ARMCM3_STM32/nvm.c **** - 176:../../../Source/ARMCM3_STM32/nvm.c **** - 177:../../../Source/ARMCM3_STM32/nvm.c **** /************************************************************************************//** - 178:../../../Source/ARMCM3_STM32/nvm.c **** ** \brief Once all erase and programming operations are completed, this - 179:../../../Source/ARMCM3_STM32/nvm.c **** ** function is called, so at the end of the programming session and - 180:../../../Source/ARMCM3_STM32/nvm.c **** ** right before a software reset is performed. It is used to calculate - 181:../../../Source/ARMCM3_STM32/nvm.c **** ** a checksum and program this into flash. This checksum is later used - 182:../../../Source/ARMCM3_STM32/nvm.c **** ** to determine if a valid user program is present in flash. - 183:../../../Source/ARMCM3_STM32/nvm.c **** ** \return BLT_TRUE if successful, BLT_FALSE otherwise. - 184:../../../Source/ARMCM3_STM32/nvm.c **** ** - 185:../../../Source/ARMCM3_STM32/nvm.c **** ****************************************************************************************/ - 186:../../../Source/ARMCM3_STM32/nvm.c **** blt_bool NvmDone(void) - 187:../../../Source/ARMCM3_STM32/nvm.c **** { - 124 .loc 1 187 0 - 125 .cfi_startproc - 126 @ args = 0, pretend = 0, frame = 0 - 127 @ frame_needed = 0, uses_anonymous_args = 0 - 128 0000 08B5 push {r3, lr} - 129 .cfi_def_cfa_offset 8 - 130 .cfi_offset 3, -8 - 131 .cfi_offset 14, -4 - 188:../../../Source/ARMCM3_STM32/nvm.c **** #if (BOOT_NVM_HOOKS_ENABLE > 0) - 189:../../../Source/ARMCM3_STM32/nvm.c **** /* give the application's NVM driver a chance to finish up */ - 190:../../../Source/ARMCM3_STM32/nvm.c **** if (NvmDoneHook() == BLT_FALSE) - 191:../../../Source/ARMCM3_STM32/nvm.c **** { - 192:../../../Source/ARMCM3_STM32/nvm.c **** /* error so no need to continue */ - 193:../../../Source/ARMCM3_STM32/nvm.c **** return BLT_FALSE; - 194:../../../Source/ARMCM3_STM32/nvm.c **** } - 195:../../../Source/ARMCM3_STM32/nvm.c **** #endif - 196:../../../Source/ARMCM3_STM32/nvm.c **** - 197:../../../Source/ARMCM3_STM32/nvm.c **** #if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) - 198:../../../Source/ARMCM3_STM32/nvm.c **** /* compute and write checksum, using the application specific method. */ - 199:../../../Source/ARMCM3_STM32/nvm.c **** if (NvmWriteChecksumHook() == BLT_FALSE) - 200:../../../Source/ARMCM3_STM32/nvm.c **** { - 201:../../../Source/ARMCM3_STM32/nvm.c **** return BLT_FALSE; - 202:../../../Source/ARMCM3_STM32/nvm.c **** } - 203:../../../Source/ARMCM3_STM32/nvm.c **** #else - 204:../../../Source/ARMCM3_STM32/nvm.c **** /* compute and write checksum, which is programmed by the internal driver. */ - 205:../../../Source/ARMCM3_STM32/nvm.c **** if (FlashWriteChecksum() == BLT_FALSE) - 132 .loc 1 205 0 - 133 0002 FFF7FEFF bl FlashWriteChecksum - 134 .LVL6: - 135 0006 0346 mov r3, r0 - 136 0008 10B1 cbz r0, .L10 - 206:../../../Source/ARMCM3_STM32/nvm.c **** { - 207:../../../Source/ARMCM3_STM32/nvm.c **** return BLT_FALSE; - 208:../../../Source/ARMCM3_STM32/nvm.c **** } - 209:../../../Source/ARMCM3_STM32/nvm.c **** #endif - 210:../../../Source/ARMCM3_STM32/nvm.c **** - 211:../../../Source/ARMCM3_STM32/nvm.c **** /* finish up internal driver operations */ - 212:../../../Source/ARMCM3_STM32/nvm.c **** return FlashDone(); - 137 .loc 1 212 0 - 138 000a FFF7FEFF bl FlashDone - 139 .LVL7: - 140 000e 0346 mov r3, r0 - 141 .L10: - 213:../../../Source/ARMCM3_STM32/nvm.c **** } /*** end of NvmDone ***/ - 142 .loc 1 213 0 - 143 0010 1846 mov r0, r3 - 144 0012 08BD pop {r3, pc} - 145 .cfi_endproc - 146 .LFE4: - 148 .text - 149 .Letext0: - 150 .file 2 "../../../Source/ARMCM3_STM32/types.h" - 151 .file 3 "../../../Source/ARMCM3_STM32/flash.h" -DEFINED SYMBOLS - *ABS*:00000000 nvm.c -C:\Users\lwngim1\AppData\Local\Temp\ccilMVOl.s:19 .text.NvmInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccilMVOl.s:24 .text.NvmInit:00000000 NvmInit -C:\Users\lwngim1\AppData\Local\Temp\ccilMVOl.s:43 .text.NvmWrite:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccilMVOl.s:48 .text.NvmWrite:00000000 NvmWrite -C:\Users\lwngim1\AppData\Local\Temp\ccilMVOl.s:68 .text.NvmErase:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccilMVOl.s:73 .text.NvmErase:00000000 NvmErase -C:\Users\lwngim1\AppData\Local\Temp\ccilMVOl.s:93 .text.NvmVerifyChecksum:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccilMVOl.s:98 .text.NvmVerifyChecksum:00000000 NvmVerifyChecksum -C:\Users\lwngim1\AppData\Local\Temp\ccilMVOl.s:117 .text.NvmDone:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccilMVOl.s:122 .text.NvmDone:00000000 NvmDone - .debug_frame:00000010 $d - -UNDEFINED SYMBOLS -FlashInit -FlashWrite -FlashErase -FlashVerifyChecksum -FlashWriteChecksum -FlashDone diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/stm32f10x_gpio.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/stm32f10x_gpio.lst deleted file mode 100644 index 29d89655..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/stm32f10x_gpio.lst +++ /dev/null @@ -1,1517 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "stm32f10x_gpio.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.GPIO_DeInit,"ax",%progbits - 19 .align 2 - 20 .global GPIO_DeInit - 21 .thumb - 22 .thumb_func - 24 GPIO_DeInit: - 25 .LFB29: - 26 .file 1 "./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c" - 1:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 2:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** ****************************************************************************** - 3:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @file stm32f10x_gpio.c - 4:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @author MCD Application Team - 5:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @version V3.5.0 - 6:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @date 11-March-2011 - 7:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief This file provides all the GPIO firmware functions. - 8:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** ****************************************************************************** - 9:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @attention - 10:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * - 11:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - 12:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - 13:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - 14:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - 15:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - 16:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - 17:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * - 18:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** *

© COPYRIGHT 2011 STMicroelectronics

- 19:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** ****************************************************************************** - 20:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 21:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 22:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Includes ------------------------------------------------------------------*/ - 23:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #include "stm32f10x_gpio.h" - 24:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #include "stm32f10x_rcc.h" - 25:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 26:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** @addtogroup STM32F10x_StdPeriph_Driver - 27:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @{ - 28:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 29:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 30:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** @defgroup GPIO - 31:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief GPIO driver modules - 32:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @{ - 33:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 34:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 35:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** @defgroup GPIO_Private_TypesDefinitions - 36:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @{ - 37:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 38:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 39:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 40:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @} - 41:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 42:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 43:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** @defgroup GPIO_Private_Defines - 44:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @{ - 45:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 46:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 47:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* ------------ RCC registers bit address in the alias region ----------------*/ - 48:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) - 49:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 50:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* --- EVENTCR Register -----*/ - 51:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 52:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Alias word address of EVOE bit */ - 53:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #define EVCR_OFFSET (AFIO_OFFSET + 0x00) - 54:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #define EVOE_BitNumber ((uint8_t)0x07) - 55:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) - 56:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 57:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 58:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* --- MAPR Register ---*/ - 59:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Alias word address of MII_RMII_SEL bit */ - 60:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #define MAPR_OFFSET (AFIO_OFFSET + 0x04) - 61:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #define MII_RMII_SEL_BitNumber ((u8)0x17) - 62:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber - 63:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 64:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 65:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) - 66:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #define LSB_MASK ((uint16_t)0xFFFF) - 67:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) - 68:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) - 69:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) - 70:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** #define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) - 71:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 72:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @} - 73:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 74:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 75:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** @defgroup GPIO_Private_Macros - 76:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @{ - 77:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 78:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 79:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 80:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @} - 81:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 82:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 83:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** @defgroup GPIO_Private_Variables - 84:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @{ - 85:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 86:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 87:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 88:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @} - 89:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 90:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 91:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** @defgroup GPIO_Private_FunctionPrototypes - 92:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @{ - 93:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 94:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 95:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 96:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @} - 97:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 98:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 99:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** @defgroup GPIO_Private_Functions - 100:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @{ - 101:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 102:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 103:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 104:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Deinitializes the GPIOx peripheral registers to their default reset values. - 105:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - 106:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 107:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 108:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_DeInit(GPIO_TypeDef* GPIOx) - 109:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 27 .loc 1 109 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 .LVL0: - 32 0000 08B5 push {r3, lr} - 33 .cfi_def_cfa_offset 8 - 34 .cfi_offset 3, -8 - 35 .cfi_offset 14, -4 - 110:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 111:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - 112:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 113:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (GPIOx == GPIOA) - 36 .loc 1 113 0 - 37 0002 2B4B ldr r3, .L10 - 38 0004 9842 cmp r0, r3 - 39 0006 08D1 bne .L2 - 114:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 115:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); - 40 .loc 1 115 0 - 41 0008 0420 movs r0, #4 - 42 .LVL1: - 43 000a 0121 movs r1, #1 - 44 000c FFF7FEFF bl RCC_APB2PeriphResetCmd - 45 .LVL2: - 116:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); - 46 .loc 1 116 0 - 47 0010 0420 movs r0, #4 - 48 0012 0021 movs r1, #0 - 49 0014 FFF7FEFF bl RCC_APB2PeriphResetCmd - 50 .LVL3: - 51 0018 08BD pop {r3, pc} - 52 .LVL4: - 53 .L2: - 117:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 118:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else if (GPIOx == GPIOB) - 54 .loc 1 118 0 - 55 001a 264B ldr r3, .L10+4 - 56 001c 9842 cmp r0, r3 - 57 001e 08D1 bne .L4 - 119:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 120:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); - 58 .loc 1 120 0 - 59 0020 0820 movs r0, #8 - 60 .LVL5: - 61 0022 0121 movs r1, #1 - 62 0024 FFF7FEFF bl RCC_APB2PeriphResetCmd - 63 .LVL6: - 121:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); - 64 .loc 1 121 0 - 65 0028 0820 movs r0, #8 - 66 002a 0021 movs r1, #0 - 67 002c FFF7FEFF bl RCC_APB2PeriphResetCmd - 68 .LVL7: - 69 0030 08BD pop {r3, pc} - 70 .LVL8: - 71 .L4: - 122:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 123:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else if (GPIOx == GPIOC) - 72 .loc 1 123 0 - 73 0032 214B ldr r3, .L10+8 - 74 0034 9842 cmp r0, r3 - 75 0036 08D1 bne .L5 - 124:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 125:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); - 76 .loc 1 125 0 - 77 0038 1020 movs r0, #16 - 78 .LVL9: - 79 003a 0121 movs r1, #1 - 80 003c FFF7FEFF bl RCC_APB2PeriphResetCmd - 81 .LVL10: - 126:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); - 82 .loc 1 126 0 - 83 0040 1020 movs r0, #16 - 84 0042 0021 movs r1, #0 - 85 0044 FFF7FEFF bl RCC_APB2PeriphResetCmd - 86 .LVL11: - 87 0048 08BD pop {r3, pc} - 88 .LVL12: - 89 .L5: - 127:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 128:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else if (GPIOx == GPIOD) - 90 .loc 1 128 0 - 91 004a 1C4B ldr r3, .L10+12 - 92 004c 9842 cmp r0, r3 - 93 004e 08D1 bne .L6 - 129:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 130:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); - 94 .loc 1 130 0 - 95 0050 2020 movs r0, #32 - 96 .LVL13: - 97 0052 0121 movs r1, #1 - 98 0054 FFF7FEFF bl RCC_APB2PeriphResetCmd - 99 .LVL14: - 131:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); - 100 .loc 1 131 0 - 101 0058 2020 movs r0, #32 - 102 005a 0021 movs r1, #0 - 103 005c FFF7FEFF bl RCC_APB2PeriphResetCmd - 104 .LVL15: - 105 0060 08BD pop {r3, pc} - 106 .LVL16: - 107 .L6: - 132:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 133:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else if (GPIOx == GPIOE) - 108 .loc 1 133 0 - 109 0062 174B ldr r3, .L10+16 - 110 0064 9842 cmp r0, r3 - 111 0066 08D1 bne .L7 - 134:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 135:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); - 112 .loc 1 135 0 - 113 0068 4020 movs r0, #64 - 114 .LVL17: - 115 006a 0121 movs r1, #1 - 116 006c FFF7FEFF bl RCC_APB2PeriphResetCmd - 117 .LVL18: - 136:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); - 118 .loc 1 136 0 - 119 0070 4020 movs r0, #64 - 120 0072 0021 movs r1, #0 - 121 0074 FFF7FEFF bl RCC_APB2PeriphResetCmd - 122 .LVL19: - 123 0078 08BD pop {r3, pc} - 124 .LVL20: - 125 .L7: - 137:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 138:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else if (GPIOx == GPIOF) - 126 .loc 1 138 0 - 127 007a 124B ldr r3, .L10+20 - 128 007c 9842 cmp r0, r3 - 129 007e 08D1 bne .L8 - 139:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 140:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); - 130 .loc 1 140 0 - 131 0080 8020 movs r0, #128 - 132 .LVL21: - 133 0082 0121 movs r1, #1 - 134 0084 FFF7FEFF bl RCC_APB2PeriphResetCmd - 135 .LVL22: - 141:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); - 136 .loc 1 141 0 - 137 0088 8020 movs r0, #128 - 138 008a 0021 movs r1, #0 - 139 008c FFF7FEFF bl RCC_APB2PeriphResetCmd - 140 .LVL23: - 141 0090 08BD pop {r3, pc} - 142 .LVL24: - 143 .L8: - 142:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 143:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else - 144:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 145:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (GPIOx == GPIOG) - 144 .loc 1 145 0 - 145 0092 0D4B ldr r3, .L10+24 - 146 0094 9842 cmp r0, r3 - 147 0096 09D1 bne .L1 - 146:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 147:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); - 148 .loc 1 147 0 - 149 0098 4FF48070 mov r0, #256 - 150 .LVL25: - 151 009c 0121 movs r1, #1 - 152 009e FFF7FEFF bl RCC_APB2PeriphResetCmd - 153 .LVL26: - 148:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); - 154 .loc 1 148 0 - 155 00a2 4FF48070 mov r0, #256 - 156 00a6 0021 movs r1, #0 - 157 00a8 FFF7FEFF bl RCC_APB2PeriphResetCmd - 158 .LVL27: - 159 .L1: - 160 00ac 08BD pop {r3, pc} - 161 .L11: - 162 00ae 00BF .align 2 - 163 .L10: - 164 00b0 00080140 .word 1073809408 - 165 00b4 000C0140 .word 1073810432 - 166 00b8 00100140 .word 1073811456 - 167 00bc 00140140 .word 1073812480 - 168 00c0 00180140 .word 1073813504 - 169 00c4 001C0140 .word 1073814528 - 170 00c8 00200140 .word 1073815552 - 171 .cfi_endproc - 172 .LFE29: - 174 .section .text.GPIO_AFIODeInit,"ax",%progbits - 175 .align 2 - 176 .global GPIO_AFIODeInit - 177 .thumb - 178 .thumb_func - 180 GPIO_AFIODeInit: - 181 .LFB30: - 149:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 150:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 151:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 152:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 153:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 154:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Deinitializes the Alternate Functions (remap, event control - 155:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * and EXTI configuration) registers to their default reset values. - 156:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param None - 157:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 158:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 159:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_AFIODeInit(void) - 160:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 182 .loc 1 160 0 - 183 .cfi_startproc - 184 @ args = 0, pretend = 0, frame = 0 - 185 @ frame_needed = 0, uses_anonymous_args = 0 - 186 0000 08B5 push {r3, lr} - 187 .cfi_def_cfa_offset 8 - 188 .cfi_offset 3, -8 - 189 .cfi_offset 14, -4 - 161:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); - 190 .loc 1 161 0 - 191 0002 0120 movs r0, #1 - 192 0004 0146 mov r1, r0 - 193 0006 FFF7FEFF bl RCC_APB2PeriphResetCmd - 194 .LVL28: - 162:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); - 195 .loc 1 162 0 - 196 000a 0120 movs r0, #1 - 197 000c 0021 movs r1, #0 - 198 000e FFF7FEFF bl RCC_APB2PeriphResetCmd - 199 .LVL29: - 200 0012 08BD pop {r3, pc} - 201 .cfi_endproc - 202 .LFE30: - 204 .section .text.GPIO_Init,"ax",%progbits - 205 .align 2 - 206 .global GPIO_Init - 207 .thumb - 208 .thumb_func - 210 GPIO_Init: - 211 .LFB31: - 163:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 164:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 165:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 166:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Initializes the GPIOx peripheral according to the specified - 167:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * parameters in the GPIO_InitStruct. - 168:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - 169:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that - 170:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * contains the configuration information for the specified GPIO peripheral. - 171:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 172:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 173:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) - 174:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 212 .loc 1 174 0 - 213 .cfi_startproc - 214 @ args = 0, pretend = 0, frame = 0 - 215 @ frame_needed = 0, uses_anonymous_args = 0 - 216 .LVL30: - 217 0000 F0B5 push {r4, r5, r6, r7, lr} - 218 .cfi_def_cfa_offset 20 - 219 .cfi_offset 4, -20 - 220 .cfi_offset 5, -16 - 221 .cfi_offset 6, -12 - 222 .cfi_offset 7, -8 - 223 .cfi_offset 14, -4 - 224 .LVL31: - 175:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - 176:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** uint32_t tmpreg = 0x00, pinmask = 0x00; - 177:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 178:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - 179:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - 180:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - 181:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 182:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /*---------------------------- GPIO Mode Configuration -----------------------*/ - 183:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - 225 .loc 1 183 0 - 226 0002 CB78 ldrb r3, [r1, #3] @ zero_extendqisi2 - 227 0004 03F00F06 and r6, r3, #15 - 228 .LVL32: - 184:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - 229 .loc 1 184 0 - 230 0008 13F0100F tst r3, #16 - 185:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 186:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 187:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - 188:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Output mode */ - 189:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - 231 .loc 1 189 0 - 232 000c 1CBF itt ne - 233 000e 8B78 ldrbne r3, [r1, #2] @ zero_extendqisi2 - 234 0010 1E43 orrne r6, r6, r3 - 235 .LVL33: - 190:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 191:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /*---------------------------- GPIO CRL Configuration ------------------------*/ - 192:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Configure the eight low port pins */ - 193:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) - 236 .loc 1 193 0 - 237 0012 0B78 ldrb r3, [r1] @ zero_extendqisi2 - 238 0014 F3B1 cbz r3, .L17 - 194:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 195:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg = GPIOx->CRL; - 239 .loc 1 195 0 - 240 0016 0568 ldr r5, [r0] - 241 .LVL34: - 196:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** for (pinpos = 0x00; pinpos < 0x08; pinpos++) - 242 .loc 1 196 0 - 243 0018 0022 movs r2, #0 - 197:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 198:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** pos = ((uint32_t)0x01) << pinpos; - 244 .loc 1 198 0 - 245 001a 0127 movs r7, #1 - 199:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Get the port pins position */ - 200:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - 201:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (currentpin == pos) - 202:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 203:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** pos = pinpos << 2; - 204:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Clear the corresponding low control register bits */ - 205:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** pinmask = ((uint32_t)0x0F) << pos; - 246 .loc 1 205 0 - 247 001c 4FF00F0E mov lr, #15 - 248 .LVL35: - 249 .L20: - 198:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Get the port pins position */ - 250 .loc 1 198 0 - 251 0020 07FA02F3 lsl r3, r7, r2 - 200:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (currentpin == pos) - 252 .loc 1 200 0 - 253 0024 0C88 ldrh r4, [r1] - 254 0026 1C40 ands r4, r4, r3 - 255 .LVL36: - 201:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 256 .loc 1 201 0 - 257 0028 9C42 cmp r4, r3 - 258 002a 0FD1 bne .L18 - 259 .LVL37: - 203:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Clear the corresponding low control register bits */ - 260 .loc 1 203 0 - 261 002c 9300 lsls r3, r2, #2 - 262 .LVL38: - 263 .loc 1 205 0 - 264 002e 0EFA03FC lsl ip, lr, r3 - 206:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg &= ~pinmask; - 265 .loc 1 206 0 - 266 0032 25EA0C05 bic r5, r5, ip - 267 .LVL39: - 207:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Write the mode configuration in the corresponding bits */ - 208:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg |= (currentmode << pos); - 268 .loc 1 208 0 - 269 0036 06FA03F3 lsl r3, r6, r3 - 270 .LVL40: - 271 003a 1D43 orrs r5, r5, r3 - 272 .LVL41: - 209:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Reset the corresponding ODR bit */ - 210:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - 273 .loc 1 210 0 - 274 003c CB78 ldrb r3, [r1, #3] @ zero_extendqisi2 - 275 003e 282B cmp r3, #40 - 276 0040 01D1 bne .L19 - 211:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 212:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->BRR = (((uint32_t)0x01) << pinpos); - 277 .loc 1 212 0 - 278 0042 4461 str r4, [r0, #20] - 279 0044 02E0 b .L18 - 280 .L19: - 213:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 214:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else - 215:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 216:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Set the corresponding ODR bit */ - 217:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - 281 .loc 1 217 0 - 282 0046 482B cmp r3, #72 - 218:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 219:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->BSRR = (((uint32_t)0x01) << pinpos); - 283 .loc 1 219 0 - 284 0048 08BF it eq - 285 004a 0461 streq r4, [r0, #16] - 286 .LVL42: - 287 .L18: - 196:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 288 .loc 1 196 0 discriminator 2 - 289 004c 0132 adds r2, r2, #1 - 290 .LVL43: - 291 004e 082A cmp r2, #8 - 292 0050 E6D1 bne .L20 - 220:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 221:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 222:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 223:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 224:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->CRL = tmpreg; - 293 .loc 1 224 0 - 294 0052 0560 str r5, [r0] - 295 .LVL44: - 296 .L17: - 225:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 226:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /*---------------------------- GPIO CRH Configuration ------------------------*/ - 227:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Configure the eight high port pins */ - 228:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (GPIO_InitStruct->GPIO_Pin > 0x00FF) - 297 .loc 1 228 0 - 298 0054 0B88 ldrh r3, [r1] - 299 0056 FF2B cmp r3, #255 - 300 0058 21D9 bls .L14 - 229:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 230:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg = GPIOx->CRH; - 301 .loc 1 230 0 - 302 005a 4568 ldr r5, [r0, #4] - 303 .LVL45: - 231:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** for (pinpos = 0x00; pinpos < 0x08; pinpos++) - 304 .loc 1 231 0 - 305 005c 0023 movs r3, #0 - 232:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 233:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** pos = (((uint32_t)0x01) << (pinpos + 0x08)); - 306 .loc 1 233 0 - 307 005e 0127 movs r7, #1 - 234:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Get the port pins position */ - 235:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - 236:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (currentpin == pos) - 237:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 238:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** pos = pinpos << 2; - 239:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Clear the corresponding high control register bits */ - 240:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** pinmask = ((uint32_t)0x0F) << pos; - 308 .loc 1 240 0 - 309 0060 4FF00F0C mov ip, #15 - 310 .LVL46: - 311 .L24: - 312 0064 03F10802 add r2, r3, #8 - 233:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Get the port pins position */ - 313 .loc 1 233 0 - 314 0068 07FA02F4 lsl r4, r7, r2 - 315 .LVL47: - 235:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (currentpin == pos) - 316 .loc 1 235 0 - 317 006c 0A88 ldrh r2, [r1] - 318 006e 2240 ands r2, r2, r4 - 319 .LVL48: - 236:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 320 .loc 1 236 0 - 321 0070 A242 cmp r2, r4 - 322 0072 10D1 bne .L22 - 323 .LVL49: - 238:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Clear the corresponding high control register bits */ - 324 .loc 1 238 0 - 325 0074 4FEA830E lsl lr, r3, #2 - 326 .LVL50: - 327 .loc 1 240 0 - 328 0078 0CFA0EF4 lsl r4, ip, lr - 241:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg &= ~pinmask; - 329 .loc 1 241 0 - 330 007c 25EA0405 bic r5, r5, r4 - 331 .LVL51: - 242:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Write the mode configuration in the corresponding bits */ - 243:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg |= (currentmode << pos); - 332 .loc 1 243 0 - 333 0080 06FA0EF4 lsl r4, r6, lr - 334 0084 2543 orrs r5, r5, r4 - 335 .LVL52: - 244:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Reset the corresponding ODR bit */ - 245:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - 336 .loc 1 245 0 - 337 0086 CC78 ldrb r4, [r1, #3] @ zero_extendqisi2 - 338 0088 282C cmp r4, #40 - 246:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 247:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); - 339 .loc 1 247 0 - 340 008a 08BF it eq - 341 008c 4261 streq r2, [r0, #20] - 248:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 249:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Set the corresponding ODR bit */ - 250:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - 342 .loc 1 250 0 - 343 008e CC78 ldrb r4, [r1, #3] @ zero_extendqisi2 - 344 0090 482C cmp r4, #72 - 251:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 252:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); - 345 .loc 1 252 0 - 346 0092 08BF it eq - 347 0094 0261 streq r2, [r0, #16] - 348 .LVL53: - 349 .L22: - 231:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 350 .loc 1 231 0 discriminator 2 - 351 0096 0133 adds r3, r3, #1 - 352 .LVL54: - 353 0098 082B cmp r3, #8 - 354 009a E3D1 bne .L24 - 253:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 254:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 255:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 256:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->CRH = tmpreg; - 355 .loc 1 256 0 - 356 009c 4560 str r5, [r0, #4] - 357 .LVL55: - 358 .L14: - 359 009e F0BD pop {r4, r5, r6, r7, pc} - 360 .cfi_endproc - 361 .LFE31: - 363 .section .text.GPIO_StructInit,"ax",%progbits - 364 .align 2 - 365 .global GPIO_StructInit - 366 .thumb - 367 .thumb_func - 369 GPIO_StructInit: - 370 .LFB32: - 257:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 258:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 259:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 260:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 261:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Fills each GPIO_InitStruct member with its default value. - 262:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will - 263:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * be initialized. - 264:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 265:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 266:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) - 267:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 371 .loc 1 267 0 - 372 .cfi_startproc - 373 @ args = 0, pretend = 0, frame = 0 - 374 @ frame_needed = 0, uses_anonymous_args = 0 - 375 @ link register save eliminated. - 376 .LVL56: - 268:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Reset GPIO init structure parameters values */ - 269:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - 377 .loc 1 269 0 - 378 0000 4FF6FF73 movw r3, #65535 - 379 0004 0380 strh r3, [r0] @ movhi - 270:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - 380 .loc 1 270 0 - 381 0006 0223 movs r3, #2 - 382 0008 8370 strb r3, [r0, #2] - 271:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; - 383 .loc 1 271 0 - 384 000a 0423 movs r3, #4 - 385 000c C370 strb r3, [r0, #3] - 386 000e 7047 bx lr - 387 .cfi_endproc - 388 .LFE32: - 390 .section .text.GPIO_ReadInputDataBit,"ax",%progbits - 391 .align 2 - 392 .global GPIO_ReadInputDataBit - 393 .thumb - 394 .thumb_func - 396 GPIO_ReadInputDataBit: - 397 .LFB33: - 272:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 273:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 274:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 275:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Reads the specified input port pin. - 276:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - 277:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_Pin: specifies the port bit to read. - 278:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be GPIO_Pin_x where x can be (0..15). - 279:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval The input port pin value. - 280:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 281:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) - 282:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 398 .loc 1 282 0 - 399 .cfi_startproc - 400 @ args = 0, pretend = 0, frame = 0 - 401 @ frame_needed = 0, uses_anonymous_args = 0 - 402 @ link register save eliminated. - 403 .LVL57: - 283:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** uint8_t bitstatus = 0x00; - 284:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 285:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 286:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - 287:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - 288:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 289:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - 404 .loc 1 289 0 - 405 0000 8368 ldr r3, [r0, #8] - 406 .LVL58: - 407 0002 1942 tst r1, r3 - 290:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 291:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** bitstatus = (uint8_t)Bit_SET; - 292:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 293:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else - 294:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 295:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** bitstatus = (uint8_t)Bit_RESET; - 296:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 297:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** return bitstatus; - 298:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 408 .loc 1 298 0 - 409 0004 14BF ite ne - 410 0006 0120 movne r0, #1 - 411 .LVL59: - 412 0008 0020 moveq r0, #0 - 413 000a 7047 bx lr - 414 .cfi_endproc - 415 .LFE33: - 417 .section .text.GPIO_ReadInputData,"ax",%progbits - 418 .align 2 - 419 .global GPIO_ReadInputData - 420 .thumb - 421 .thumb_func - 423 GPIO_ReadInputData: - 424 .LFB34: - 299:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 300:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 301:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Reads the specified GPIO input data port. - 302:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - 303:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval GPIO input data port value. - 304:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 305:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) - 306:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 425 .loc 1 306 0 - 426 .cfi_startproc - 427 @ args = 0, pretend = 0, frame = 0 - 428 @ frame_needed = 0, uses_anonymous_args = 0 - 429 @ link register save eliminated. - 430 .LVL60: - 307:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 308:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - 309:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 310:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** return ((uint16_t)GPIOx->IDR); - 431 .loc 1 310 0 - 432 0000 8068 ldr r0, [r0, #8] - 433 .LVL61: - 311:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 434 .loc 1 311 0 - 435 0002 80B2 uxth r0, r0 - 436 0004 7047 bx lr - 437 .cfi_endproc - 438 .LFE34: - 440 0006 00BF .section .text.GPIO_ReadOutputDataBit,"ax",%progbits - 441 .align 2 - 442 .global GPIO_ReadOutputDataBit - 443 .thumb - 444 .thumb_func - 446 GPIO_ReadOutputDataBit: - 447 .LFB35: - 312:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 313:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 314:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Reads the specified output data port bit. - 315:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - 316:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_Pin: specifies the port bit to read. - 317:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be GPIO_Pin_x where x can be (0..15). - 318:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval The output port pin value. - 319:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 320:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) - 321:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 448 .loc 1 321 0 - 449 .cfi_startproc - 450 @ args = 0, pretend = 0, frame = 0 - 451 @ frame_needed = 0, uses_anonymous_args = 0 - 452 @ link register save eliminated. - 453 .LVL62: - 322:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** uint8_t bitstatus = 0x00; - 323:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 324:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - 325:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - 326:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 327:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - 454 .loc 1 327 0 - 455 0000 C368 ldr r3, [r0, #12] - 456 .LVL63: - 457 0002 1942 tst r1, r3 - 328:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 329:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** bitstatus = (uint8_t)Bit_SET; - 330:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 331:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else - 332:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 333:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** bitstatus = (uint8_t)Bit_RESET; - 334:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 335:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** return bitstatus; - 336:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 458 .loc 1 336 0 - 459 0004 14BF ite ne - 460 0006 0120 movne r0, #1 - 461 .LVL64: - 462 0008 0020 moveq r0, #0 - 463 000a 7047 bx lr - 464 .cfi_endproc - 465 .LFE35: - 467 .section .text.GPIO_ReadOutputData,"ax",%progbits - 468 .align 2 - 469 .global GPIO_ReadOutputData - 470 .thumb - 471 .thumb_func - 473 GPIO_ReadOutputData: - 474 .LFB36: - 337:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 338:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 339:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Reads the specified GPIO output data port. - 340:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - 341:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval GPIO output data port value. - 342:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 343:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) - 344:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 475 .loc 1 344 0 - 476 .cfi_startproc - 477 @ args = 0, pretend = 0, frame = 0 - 478 @ frame_needed = 0, uses_anonymous_args = 0 - 479 @ link register save eliminated. - 480 .LVL65: - 345:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 346:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - 347:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 348:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** return ((uint16_t)GPIOx->ODR); - 481 .loc 1 348 0 - 482 0000 C068 ldr r0, [r0, #12] - 483 .LVL66: - 349:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 484 .loc 1 349 0 - 485 0002 80B2 uxth r0, r0 - 486 0004 7047 bx lr - 487 .cfi_endproc - 488 .LFE36: - 490 0006 00BF .section .text.GPIO_SetBits,"ax",%progbits - 491 .align 2 - 492 .global GPIO_SetBits - 493 .thumb - 494 .thumb_func - 496 GPIO_SetBits: - 497 .LFB37: - 350:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 351:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 352:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Sets the selected data port bits. - 353:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - 354:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_Pin: specifies the port bits to be written. - 355:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - 356:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 357:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 358:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) - 359:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 498 .loc 1 359 0 - 499 .cfi_startproc - 500 @ args = 0, pretend = 0, frame = 0 - 501 @ frame_needed = 0, uses_anonymous_args = 0 - 502 @ link register save eliminated. - 503 .LVL67: - 360:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 361:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - 362:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); - 363:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 364:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->BSRR = GPIO_Pin; - 504 .loc 1 364 0 - 505 0000 0161 str r1, [r0, #16] - 506 0002 7047 bx lr - 507 .cfi_endproc - 508 .LFE37: - 510 .section .text.GPIO_ResetBits,"ax",%progbits - 511 .align 2 - 512 .global GPIO_ResetBits - 513 .thumb - 514 .thumb_func - 516 GPIO_ResetBits: - 517 .LFB38: - 365:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 366:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 367:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 368:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Clears the selected data port bits. - 369:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - 370:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_Pin: specifies the port bits to be written. - 371:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - 372:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 373:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 374:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) - 375:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 518 .loc 1 375 0 - 519 .cfi_startproc - 520 @ args = 0, pretend = 0, frame = 0 - 521 @ frame_needed = 0, uses_anonymous_args = 0 - 522 @ link register save eliminated. - 523 .LVL68: - 376:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 377:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - 378:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); - 379:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 380:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->BRR = GPIO_Pin; - 524 .loc 1 380 0 - 525 0000 4161 str r1, [r0, #20] - 526 0002 7047 bx lr - 527 .cfi_endproc - 528 .LFE38: - 530 .section .text.GPIO_WriteBit,"ax",%progbits - 531 .align 2 - 532 .global GPIO_WriteBit - 533 .thumb - 534 .thumb_func - 536 GPIO_WriteBit: - 537 .LFB39: - 381:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 382:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 383:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 384:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Sets or clears the selected data port bit. - 385:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - 386:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_Pin: specifies the port bit to be written. - 387:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be one of GPIO_Pin_x where x can be (0..15). - 388:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param BitVal: specifies the value to be written to the selected bit. - 389:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be one of the BitAction enum values: - 390:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg Bit_RESET: to clear the port pin - 391:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg Bit_SET: to set the port pin - 392:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 393:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 394:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) - 395:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 538 .loc 1 395 0 - 539 .cfi_startproc - 540 @ args = 0, pretend = 0, frame = 0 - 541 @ frame_needed = 0, uses_anonymous_args = 0 - 542 @ link register save eliminated. - 543 .LVL69: - 396:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 397:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - 398:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - 399:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_BIT_ACTION(BitVal)); - 400:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 401:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (BitVal != Bit_RESET) - 544 .loc 1 401 0 - 545 0000 0AB1 cbz r2, .L36 - 402:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 403:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->BSRR = GPIO_Pin; - 546 .loc 1 403 0 - 547 0002 0161 str r1, [r0, #16] - 548 0004 7047 bx lr - 549 .L36: - 404:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 405:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else - 406:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 407:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->BRR = GPIO_Pin; - 550 .loc 1 407 0 - 551 0006 4161 str r1, [r0, #20] - 552 0008 7047 bx lr - 553 .cfi_endproc - 554 .LFE39: - 556 000a 00BF .section .text.GPIO_Write,"ax",%progbits - 557 .align 2 - 558 .global GPIO_Write - 559 .thumb - 560 .thumb_func - 562 GPIO_Write: - 563 .LFB40: - 408:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 409:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 410:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 411:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 412:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Writes data to the specified GPIO data port. - 413:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - 414:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param PortVal: specifies the value to be written to the port output data register. - 415:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 416:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 417:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) - 418:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 564 .loc 1 418 0 - 565 .cfi_startproc - 566 @ args = 0, pretend = 0, frame = 0 - 567 @ frame_needed = 0, uses_anonymous_args = 0 - 568 @ link register save eliminated. - 569 .LVL70: - 419:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 420:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - 421:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 422:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->ODR = PortVal; - 570 .loc 1 422 0 - 571 0000 C160 str r1, [r0, #12] - 572 0002 7047 bx lr - 573 .cfi_endproc - 574 .LFE40: - 576 .section .text.GPIO_PinLockConfig,"ax",%progbits - 577 .align 2 - 578 .global GPIO_PinLockConfig - 579 .thumb - 580 .thumb_func - 582 GPIO_PinLockConfig: - 583 .LFB41: - 423:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 424:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 425:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 426:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Locks GPIO Pins configuration registers. - 427:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - 428:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_Pin: specifies the port bit to be written. - 429:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - 430:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 431:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 432:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) - 433:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 584 .loc 1 433 0 - 585 .cfi_startproc - 586 @ args = 0, pretend = 0, frame = 0 - 587 @ frame_needed = 0, uses_anonymous_args = 0 - 588 @ link register save eliminated. - 589 .LVL71: - 434:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** uint32_t tmp = 0x00010000; - 435:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 436:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 437:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - 438:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); - 439:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 440:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmp |= GPIO_Pin; - 590 .loc 1 440 0 - 591 0000 41F48033 orr r3, r1, #65536 - 592 .LVL72: - 441:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Set LCKK bit */ - 442:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->LCKR = tmp; - 593 .loc 1 442 0 - 594 0004 8361 str r3, [r0, #24] - 443:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Reset LCKK bit */ - 444:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->LCKR = GPIO_Pin; - 595 .loc 1 444 0 - 596 0006 8161 str r1, [r0, #24] - 445:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Set LCKK bit */ - 446:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** GPIOx->LCKR = tmp; - 597 .loc 1 446 0 - 598 0008 8361 str r3, [r0, #24] - 447:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Read LCKK bit*/ - 448:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmp = GPIOx->LCKR; - 599 .loc 1 448 0 - 600 000a 8369 ldr r3, [r0, #24] - 601 .LVL73: - 449:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Read LCKK bit*/ - 450:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmp = GPIOx->LCKR; - 602 .loc 1 450 0 - 603 000c 8369 ldr r3, [r0, #24] - 604 000e 7047 bx lr - 605 .cfi_endproc - 606 .LFE41: - 608 .section .text.GPIO_EventOutputConfig,"ax",%progbits - 609 .align 2 - 610 .global GPIO_EventOutputConfig - 611 .thumb - 612 .thumb_func - 614 GPIO_EventOutputConfig: - 615 .LFB42: - 451:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 452:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 453:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 454:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Selects the GPIO pin used as Event output. - 455:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_PortSource: selects the GPIO port to be used as source - 456:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * for Event output. - 457:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). - 458:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_PinSource: specifies the pin for the Event output. - 459:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be GPIO_PinSourcex where x can be (0..15). - 460:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 461:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 462:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) - 463:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 616 .loc 1 463 0 - 617 .cfi_startproc - 618 @ args = 0, pretend = 0, frame = 0 - 619 @ frame_needed = 0, uses_anonymous_args = 0 - 620 @ link register save eliminated. - 621 .LVL74: - 464:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** uint32_t tmpreg = 0x00; - 465:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 466:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); - 467:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - 468:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 469:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg = AFIO->EVCR; - 622 .loc 1 469 0 - 623 0000 054A ldr r2, .L41 - 624 0002 1368 ldr r3, [r2] - 625 .LVL75: - 470:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Clear the PORT[6:4] and PIN[3:0] bits */ - 471:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg &= EVCR_PORTPINCONFIG_MASK; - 626 .loc 1 471 0 - 627 0004 23F07F03 bic r3, r3, #127 - 628 .LVL76: - 629 0008 1B04 lsls r3, r3, #16 - 630 000a 1B0C lsrs r3, r3, #16 - 631 000c 1943 orrs r1, r1, r3 - 632 .LVL77: - 472:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg |= (uint32_t)GPIO_PortSource << 0x04; - 473:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg |= GPIO_PinSource; - 633 .loc 1 473 0 - 634 000e 41EA0010 orr r0, r1, r0, lsl #4 - 635 .LVL78: - 474:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** AFIO->EVCR = tmpreg; - 636 .loc 1 474 0 - 637 0012 1060 str r0, [r2] - 638 0014 7047 bx lr - 639 .L42: - 640 0016 00BF .align 2 - 641 .L41: - 642 0018 00000140 .word 1073807360 - 643 .cfi_endproc - 644 .LFE42: - 646 .section .text.GPIO_EventOutputCmd,"ax",%progbits - 647 .align 2 - 648 .global GPIO_EventOutputCmd - 649 .thumb - 650 .thumb_func - 652 GPIO_EventOutputCmd: - 653 .LFB43: - 475:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 476:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 477:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 478:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Enables or disables the Event Output. - 479:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param NewState: new state of the Event output. - 480:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be: ENABLE or DISABLE. - 481:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 482:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 483:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_EventOutputCmd(FunctionalState NewState) - 484:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 654 .loc 1 484 0 - 655 .cfi_startproc - 656 @ args = 0, pretend = 0, frame = 0 - 657 @ frame_needed = 0, uses_anonymous_args = 0 - 658 @ link register save eliminated. - 659 .LVL79: - 485:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 486:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 487:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 488:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; - 660 .loc 1 488 0 - 661 0000 014B ldr r3, .L44 - 662 0002 1860 str r0, [r3] - 663 0004 7047 bx lr - 664 .L45: - 665 0006 00BF .align 2 - 666 .L44: - 667 0008 1C002042 .word 1109393436 - 668 .cfi_endproc - 669 .LFE43: - 671 .section .text.GPIO_PinRemapConfig,"ax",%progbits - 672 .align 2 - 673 .global GPIO_PinRemapConfig - 674 .thumb - 675 .thumb_func - 677 GPIO_PinRemapConfig: - 678 .LFB44: - 489:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 490:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 491:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 492:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Changes the mapping of the specified pin. - 493:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_Remap: selects the pin to remap. - 494:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be one of the following values: - 495:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping - 496:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping - 497:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping - 498:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping - 499:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping - 500:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping - 501:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping - 502:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping - 503:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping - 504:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping - 505:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping - 506:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping - 507:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping - 508:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping - 509:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping - 510:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping - 511:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping - 512:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibra - 513:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping - 514:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping - 515:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping - 516:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping - 517:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices) - 518:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices) - 519:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST - 520:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled - 521:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP) - 522:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectiv - 523:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * When the SPI3/I2S3 is remapped using this function, the - 524:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST. - 525:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) conn - 526:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * to TIM2 Internal Trigger 1 for calibration (only for Con - 527:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 I - 528:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * Ethernet PTP output. When Reset TIM2 ITR1 is connected t - 529:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivi - 530:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line de - 531:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line de - 532:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line de - 533:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devi - 534:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices) - 535:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density dev - 536:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density de - 537:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density de - 538:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density - 539:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density - 540:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High dens - 541:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High - 542:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density - 543:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trig - 544:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * only for High density Value line devices) - 545:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param NewState: new state of the port pin remapping. - 546:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be: ENABLE or DISABLE. - 547:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 548:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 549:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) - 550:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 679 .loc 1 550 0 - 680 .cfi_startproc - 681 @ args = 0, pretend = 0, frame = 0 - 682 @ frame_needed = 0, uses_anonymous_args = 0 - 683 @ link register save eliminated. - 684 .LVL80: - 685 0000 30B4 push {r4, r5} - 686 .cfi_def_cfa_offset 8 - 687 .cfi_offset 4, -8 - 688 .cfi_offset 5, -4 - 689 .LVL81: - 551:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; - 552:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 553:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 554:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_REMAP(GPIO_Remap)); - 555:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 556:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 557:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if((GPIO_Remap & 0x80000000) == 0x80000000) - 690 .loc 1 557 0 - 691 0002 0028 cmp r0, #0 - 558:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 559:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg = AFIO->MAPR2; - 692 .loc 1 559 0 - 693 0004 184B ldr r3, .L56 - 694 0006 B4BF ite lt - 695 0008 DB69 ldrlt r3, [r3, #28] - 696 .LVL82: - 560:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 561:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else - 562:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 563:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg = AFIO->MAPR; - 697 .loc 1 563 0 - 698 000a 5B68 ldrge r3, [r3, #4] - 699 .LVL83: - 564:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 565:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 566:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - 567:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmp = GPIO_Remap & LSB_MASK; - 700 .loc 1 567 0 - 701 000c 82B2 uxth r2, r0 - 702 .LVL84: - 568:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 569:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR - 703 .loc 1 569 0 - 704 000e 00F44014 and r4, r0, #3145728 - 705 0012 B4F5401F cmp r4, #3145728 - 706 0016 07D1 bne .L49 - 570:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 571:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg &= DBGAFR_SWJCFG_MASK; - 707 .loc 1 571 0 - 708 0018 23F07063 bic r3, r3, #251658240 - 709 .LVL85: - 572:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** AFIO->MAPR &= DBGAFR_SWJCFG_MASK; - 710 .loc 1 572 0 - 711 001c 124D ldr r5, .L56 - 712 001e 6C68 ldr r4, [r5, #4] - 713 0020 24F07064 bic r4, r4, #251658240 - 714 0024 6C60 str r4, [r5, #4] - 715 0026 13E0 b .L50 - 716 .L49: - 573:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 574:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) - 717 .loc 1 574 0 - 718 0028 10F4801F tst r0, #1048576 - 719 002c 08D0 beq .L51 - 720 .LVL86: - 566:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmp = GPIO_Remap & LSB_MASK; - 721 .loc 1 566 0 - 722 002e C0F30345 ubfx r5, r0, #16, #4 - 575:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 576:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmp1 = ((uint32_t)0x03) << tmpmask; - 723 .loc 1 576 0 - 724 0032 0324 movs r4, #3 - 725 0034 AC40 lsls r4, r4, r5 - 577:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg &= ~tmp1; - 726 .loc 1 577 0 - 727 0036 23EA0403 bic r3, r3, r4 - 728 .LVL87: - 578:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg |= ~DBGAFR_SWJCFG_MASK; - 729 .loc 1 578 0 - 730 003a 43F07063 orr r3, r3, #251658240 - 731 .LVL88: - 732 003e 07E0 b .L50 - 733 .LVL89: - 734 .L51: - 579:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 580:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else - 581:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 582:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); - 735 .loc 1 582 0 - 736 0040 440D lsrs r4, r0, #21 - 737 0042 2401 lsls r4, r4, #4 - 738 0044 02FA04F4 lsl r4, r2, r4 - 739 0048 23EA0403 bic r3, r3, r4 - 740 .LVL90: - 583:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg |= ~DBGAFR_SWJCFG_MASK; - 741 .loc 1 583 0 - 742 004c 43F07063 orr r3, r3, #251658240 - 743 .LVL91: - 744 .L50: - 584:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 585:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 586:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if (NewState != DISABLE) - 745 .loc 1 586 0 - 746 0050 19B1 cbz r1, .L52 - 587:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 588:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); - 747 .loc 1 588 0 - 748 0052 410D lsrs r1, r0, #21 - 749 .LVL92: - 750 0054 0901 lsls r1, r1, #4 - 751 0056 8A40 lsls r2, r2, r1 - 752 .LVL93: - 753 0058 1343 orrs r3, r3, r2 - 754 .LVL94: - 755 .L52: - 589:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 590:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 591:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** if((GPIO_Remap & 0x80000000) == 0x80000000) - 756 .loc 1 591 0 - 757 005a 0028 cmp r0, #0 - 592:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 593:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** AFIO->MAPR2 = tmpreg; - 758 .loc 1 593 0 - 759 005c 024A ldr r2, .L56 - 760 005e B4BF ite lt - 761 0060 D361 strlt r3, [r2, #28] - 594:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 595:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** else - 596:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 597:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** AFIO->MAPR = tmpreg; - 762 .loc 1 597 0 - 763 0062 5360 strge r3, [r2, #4] - 598:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 599:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 764 .loc 1 599 0 - 765 0064 30BC pop {r4, r5} - 766 .cfi_restore 5 - 767 .cfi_restore 4 - 768 .cfi_def_cfa_offset 0 - 769 0066 7047 bx lr - 770 .L57: - 771 .align 2 - 772 .L56: - 773 0068 00000140 .word 1073807360 - 774 .cfi_endproc - 775 .LFE44: - 777 .section .text.GPIO_EXTILineConfig,"ax",%progbits - 778 .align 2 - 779 .global GPIO_EXTILineConfig - 780 .thumb - 781 .thumb_func - 783 GPIO_EXTILineConfig: - 784 .LFB45: - 600:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 601:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 602:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Selects the GPIO pin used as EXTI Line. - 603:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. - 604:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). - 605:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_PinSource: specifies the EXTI line to be configured. - 606:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be GPIO_PinSourcex where x can be (0..15). - 607:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 608:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 609:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) - 610:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 785 .loc 1 610 0 - 786 .cfi_startproc - 787 @ args = 0, pretend = 0, frame = 0 - 788 @ frame_needed = 0, uses_anonymous_args = 0 - 789 @ link register save eliminated. - 790 .LVL95: - 791 0000 10B4 push {r4} - 792 .cfi_def_cfa_offset 4 - 793 .cfi_offset 4, -4 - 794 .LVL96: - 611:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** uint32_t tmp = 0x00; - 612:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Check the parameters */ - 613:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); - 614:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - 615:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 616:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); - 795 .loc 1 616 0 - 796 0002 01F00303 and r3, r1, #3 - 797 0006 9B00 lsls r3, r3, #2 - 798 .LVL97: - 799 0008 01F0FC01 and r1, r1, #252 - 800 .LVL98: - 801 000c 01F18041 add r1, r1, #1073741824 - 802 0010 01F58031 add r1, r1, #65536 - 617:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; - 803 .loc 1 617 0 - 804 0014 8C68 ldr r4, [r1, #8] - 616:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; - 805 .loc 1 616 0 - 806 0016 0F22 movs r2, #15 - 807 0018 9A40 lsls r2, r2, r3 - 808 .LVL99: - 809 .loc 1 617 0 - 810 001a 24EA0202 bic r2, r4, r2 - 811 .LVL100: - 812 001e 8A60 str r2, [r1, #8] - 618:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & - 813 .loc 1 618 0 - 814 0020 8A68 ldr r2, [r1, #8] - 815 0022 9840 lsls r0, r0, r3 - 816 .LVL101: - 817 0024 0243 orrs r2, r2, r0 - 818 0026 8A60 str r2, [r1, #8] - 619:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** } - 819 .loc 1 619 0 - 820 0028 5DF8044B ldr r4, [sp], #4 - 821 .cfi_restore 4 - 822 .cfi_def_cfa_offset 0 - 823 002c 7047 bx lr - 824 .cfi_endproc - 825 .LFE45: - 827 002e 00BF .section .text.GPIO_ETH_MediaInterfaceConfig,"ax",%progbits - 828 .align 2 - 829 .global GPIO_ETH_MediaInterfaceConfig - 830 .thumb - 831 .thumb_func - 833 GPIO_ETH_MediaInterfaceConfig: - 834 .LFB46: - 620:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 621:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /** - 622:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @brief Selects the Ethernet media interface. - 623:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @note This function applies only to STM32 Connectivity line devices. - 624:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. - 625:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * This parameter can be one of the following values: - 626:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_ETH_MediaInterface_MII: MII mode - 627:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @arg GPIO_ETH_MediaInterface_RMII: RMII mode - 628:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** * @retval None - 629:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** */ - 630:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) - 631:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** { - 835 .loc 1 631 0 - 836 .cfi_startproc - 837 @ args = 0, pretend = 0, frame = 0 - 838 @ frame_needed = 0, uses_anonymous_args = 0 - 839 @ link register save eliminated. - 840 .LVL102: - 632:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); - 633:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** - 634:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** /* Configure MII_RMII selection bit */ - 635:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c **** *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; - 841 .loc 1 635 0 - 842 0000 014B ldr r3, .L61 - 843 0002 1860 str r0, [r3] - 844 0004 7047 bx lr - 845 .L62: - 846 0006 00BF .align 2 - 847 .L61: - 848 0008 DC002042 .word 1109393628 - 849 .cfi_endproc - 850 .LFE46: - 852 .text - 853 .Letext0: - 854 .file 2 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\mach - 855 .file 3 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\stdi - 856 .file 4 "./lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h" - 857 .file 5 "./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h" - 858 .file 6 "./lib/CMSIS/CM3/CoreSupport/core_cm3.h" - 859 .file 7 "./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h" -DEFINED SYMBOLS - *ABS*:00000000 stm32f10x_gpio.c -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:19 .text.GPIO_DeInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:24 .text.GPIO_DeInit:00000000 GPIO_DeInit -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:164 .text.GPIO_DeInit:000000b0 $d -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:175 .text.GPIO_AFIODeInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:180 .text.GPIO_AFIODeInit:00000000 GPIO_AFIODeInit -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:205 .text.GPIO_Init:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:210 .text.GPIO_Init:00000000 GPIO_Init -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:364 .text.GPIO_StructInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:369 .text.GPIO_StructInit:00000000 GPIO_StructInit -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:391 .text.GPIO_ReadInputDataBit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:396 .text.GPIO_ReadInputDataBit:00000000 GPIO_ReadInputDataBit -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:418 .text.GPIO_ReadInputData:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:423 .text.GPIO_ReadInputData:00000000 GPIO_ReadInputData -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:441 .text.GPIO_ReadOutputDataBit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:446 .text.GPIO_ReadOutputDataBit:00000000 GPIO_ReadOutputDataBit -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:468 .text.GPIO_ReadOutputData:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:473 .text.GPIO_ReadOutputData:00000000 GPIO_ReadOutputData -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:491 .text.GPIO_SetBits:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:496 .text.GPIO_SetBits:00000000 GPIO_SetBits -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:511 .text.GPIO_ResetBits:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:516 .text.GPIO_ResetBits:00000000 GPIO_ResetBits -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:531 .text.GPIO_WriteBit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:536 .text.GPIO_WriteBit:00000000 GPIO_WriteBit -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:557 .text.GPIO_Write:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:562 .text.GPIO_Write:00000000 GPIO_Write -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:577 .text.GPIO_PinLockConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:582 .text.GPIO_PinLockConfig:00000000 GPIO_PinLockConfig -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:609 .text.GPIO_EventOutputConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:614 .text.GPIO_EventOutputConfig:00000000 GPIO_EventOutputConfig -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:642 .text.GPIO_EventOutputConfig:00000018 $d -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:647 .text.GPIO_EventOutputCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:652 .text.GPIO_EventOutputCmd:00000000 GPIO_EventOutputCmd -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:667 .text.GPIO_EventOutputCmd:00000008 $d -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:672 .text.GPIO_PinRemapConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:677 .text.GPIO_PinRemapConfig:00000000 GPIO_PinRemapConfig -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:773 .text.GPIO_PinRemapConfig:00000068 $d -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:778 .text.GPIO_EXTILineConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:783 .text.GPIO_EXTILineConfig:00000000 GPIO_EXTILineConfig -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:828 .text.GPIO_ETH_MediaInterfaceConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:833 .text.GPIO_ETH_MediaInterfaceConfig:00000000 GPIO_ETH_MediaInterfaceConfig -C:\Users\lwngim1\AppData\Local\Temp\ccMcewvx.s:848 .text.GPIO_ETH_MediaInterfaceConfig:00000008 $d - .debug_frame:00000010 $d - -UNDEFINED SYMBOLS -RCC_APB2PeriphResetCmd diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/stm32f10x_rcc.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/stm32f10x_rcc.lst deleted file mode 100644 index a92f5022..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/stm32f10x_rcc.lst +++ /dev/null @@ -1,2796 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "stm32f10x_rcc.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.RCC_DeInit,"ax",%progbits - 19 .align 2 - 20 .global RCC_DeInit - 21 .thumb - 22 .thumb_func - 24 RCC_DeInit: - 25 .LFB29: - 26 .file 1 "./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c" - 1:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 2:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** ****************************************************************************** - 3:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @file stm32f10x_rcc.c - 4:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @author MCD Application Team - 5:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @version V3.5.0 - 6:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @date 11-March-2011 - 7:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief This file provides all the RCC firmware functions. - 8:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** ****************************************************************************** - 9:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @attention - 10:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - 11:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - 12:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - 13:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - 14:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - 15:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - 16:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - 17:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - 18:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *

© COPYRIGHT 2011 STMicroelectronics

- 19:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** ****************************************************************************** - 20:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 21:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 22:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Includes ------------------------------------------------------------------*/ - 23:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #include "stm32f10x_rcc.h" - 24:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 25:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** @addtogroup STM32F10x_StdPeriph_Driver - 26:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @{ - 27:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 28:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 29:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** @defgroup RCC - 30:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief RCC driver modules - 31:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @{ - 32:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 33:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 34:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** @defgroup RCC_Private_TypesDefinitions - 35:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @{ - 36:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 37:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 38:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 39:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @} - 40:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 41:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 42:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** @defgroup RCC_Private_Defines - 43:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @{ - 44:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 45:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 46:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* ------------ RCC registers bit address in the alias region ----------- */ - 47:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - 48:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 49:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* --- CR Register ---*/ - 50:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 51:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Alias word address of HSION bit */ - 52:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CR_OFFSET (RCC_OFFSET + 0x00) - 53:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define HSION_BitNumber 0x00 - 54:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) - 55:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 56:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Alias word address of PLLON bit */ - 57:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define PLLON_BitNumber 0x18 - 58:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) - 59:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 60:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #ifdef STM32F10X_CL - 61:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Alias word address of PLL2ON bit */ - 62:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define PLL2ON_BitNumber 0x1A - 63:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) - 64:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 65:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Alias word address of PLL3ON bit */ - 66:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define PLL3ON_BitNumber 0x1C - 67:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) - 68:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif /* STM32F10X_CL */ - 69:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 70:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Alias word address of CSSON bit */ - 71:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CSSON_BitNumber 0x13 - 72:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) - 73:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 74:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* --- CFGR Register ---*/ - 75:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 76:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Alias word address of USBPRE bit */ - 77:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_OFFSET (RCC_OFFSET + 0x04) - 78:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 79:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #ifndef STM32F10X_CL - 80:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define USBPRE_BitNumber 0x16 - 81:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) - 82:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #else - 83:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define OTGFSPRE_BitNumber 0x16 - 84:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) - 85:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif /* STM32F10X_CL */ - 86:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 87:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* --- BDCR Register ---*/ - 88:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 89:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Alias word address of RTCEN bit */ - 90:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define BDCR_OFFSET (RCC_OFFSET + 0x20) - 91:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define RTCEN_BitNumber 0x0F - 92:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) - 93:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 94:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Alias word address of BDRST bit */ - 95:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define BDRST_BitNumber 0x10 - 96:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) - 97:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 98:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* --- CSR Register ---*/ - 99:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 100:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Alias word address of LSION bit */ - 101:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CSR_OFFSET (RCC_OFFSET + 0x24) - 102:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define LSION_BitNumber 0x00 - 103:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) - 104:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 105:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #ifdef STM32F10X_CL - 106:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* --- CFGR2 Register ---*/ - 107:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 108:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Alias word address of I2S2SRC bit */ - 109:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) - 110:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define I2S2SRC_BitNumber 0x11 - 111:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) - 112:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 113:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Alias word address of I2S3SRC bit */ - 114:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define I2S3SRC_BitNumber 0x12 - 115:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) - 116:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif /* STM32F10X_CL */ - 117:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 118:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* ---------------------- RCC registers bit mask ------------------------ */ - 119:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 120:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* CR register bit mask */ - 121:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) - 122:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CR_HSEBYP_Set ((uint32_t)0x00040000) - 123:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) - 124:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CR_HSEON_Set ((uint32_t)0x00010000) - 125:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - 126:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 127:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* CFGR register bit mask */ - 128:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined - 129:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) - 130:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #else - 131:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) - 132:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif /* STM32F10X_CL */ - 133:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 134:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) - 135:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) - 136:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) - 137:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_SWS_Mask ((uint32_t)0x0000000C) - 138:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) - 139:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) - 140:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) - 141:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) - 142:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) - 143:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) - 144:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) - 145:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) - 146:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) - 147:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 148:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* CSR register bit mask */ - 149:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CSR_RMVF_Set ((uint32_t)0x01000000) - 150:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 151:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined - 152:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* CFGR2 register bit mask */ - 153:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) - 154:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) - 155:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif - 156:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #ifdef STM32F10X_CL - 157:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) - 158:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) - 159:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) - 160:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif /* STM32F10X_CL */ - 161:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 162:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* RCC Flag Mask */ - 163:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define FLAG_Mask ((uint8_t)0x1F) - 164:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 165:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* CIR register byte 2 (Bits[15:8]) base address */ - 166:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) - 167:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 168:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* CIR register byte 3 (Bits[23:16]) base address */ - 169:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - 170:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 171:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* CFGR register byte 4 (Bits[31:24]) base address */ - 172:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) - 173:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 174:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* BDCR register base address */ - 175:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - 176:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 177:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 178:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @} - 179:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 180:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 181:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** @defgroup RCC_Private_Macros - 182:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @{ - 183:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 184:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 185:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 186:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @} - 187:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 188:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 189:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** @defgroup RCC_Private_Variables - 190:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @{ - 191:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 192:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 193:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - 194:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; - 195:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 196:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 197:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @} - 198:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 199:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 200:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** @defgroup RCC_Private_FunctionPrototypes - 201:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @{ - 202:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 203:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 204:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 205:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @} - 206:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 207:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 208:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** @defgroup RCC_Private_Functions - 209:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @{ - 210:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 211:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 212:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 213:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Resets the RCC clock configuration to the default reset state. - 214:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param None - 215:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 216:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 217:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_DeInit(void) - 218:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 27 .loc 1 218 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 @ link register save eliminated. - 219:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set HSION bit */ - 220:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CR |= (uint32_t)0x00000001; - 32 .loc 1 220 0 - 33 0000 0D4B ldr r3, .L2 - 34 0002 1A68 ldr r2, [r3] - 35 0004 42F00102 orr r2, r2, #1 - 36 0008 1A60 str r2, [r3] - 221:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 222:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ - 223:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #ifndef STM32F10X_CL - 224:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR &= (uint32_t)0xF8FF0000; - 37 .loc 1 224 0 - 38 000a 5968 ldr r1, [r3, #4] - 39 000c 0B4A ldr r2, .L2+4 - 40 000e 0A40 ands r2, r2, r1 - 41 0010 5A60 str r2, [r3, #4] - 225:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #else - 226:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR &= (uint32_t)0xF0FF0000; - 227:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif /* STM32F10X_CL */ - 228:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 229:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Reset HSEON, CSSON and PLLON bits */ - 230:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CR &= (uint32_t)0xFEF6FFFF; - 42 .loc 1 230 0 - 43 0012 1A68 ldr r2, [r3] - 44 0014 22F08472 bic r2, r2, #17301504 - 45 0018 22F48032 bic r2, r2, #65536 - 46 001c 1A60 str r2, [r3] - 231:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 232:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Reset HSEBYP bit */ - 233:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CR &= (uint32_t)0xFFFBFFFF; - 47 .loc 1 233 0 - 48 001e 1A68 ldr r2, [r3] - 49 0020 22F48022 bic r2, r2, #262144 - 50 0024 1A60 str r2, [r3] - 234:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 235:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - 236:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR &= (uint32_t)0xFF80FFFF; - 51 .loc 1 236 0 - 52 0026 5A68 ldr r2, [r3, #4] - 53 0028 22F4FE02 bic r2, r2, #8323072 - 54 002c 5A60 str r2, [r3, #4] - 237:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 238:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #ifdef STM32F10X_CL - 239:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Reset PLL2ON and PLL3ON bits */ - 240:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CR &= (uint32_t)0xEBFFFFFF; - 241:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 242:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Disable all interrupts and clear pending bits */ - 243:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CIR = 0x00FF0000; - 244:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 245:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Reset CFGR2 register */ - 246:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR2 = 0x00000000; - 247:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - 248:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Disable all interrupts and clear pending bits */ - 249:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CIR = 0x009F0000; - 250:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 251:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Reset CFGR2 register */ - 252:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR2 = 0x00000000; - 253:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #else - 254:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Disable all interrupts and clear pending bits */ - 255:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CIR = 0x009F0000; - 55 .loc 1 255 0 - 56 002e 4FF41F02 mov r2, #10420224 - 57 0032 9A60 str r2, [r3, #8] - 58 0034 7047 bx lr - 59 .L3: - 60 0036 00BF .align 2 - 61 .L2: - 62 0038 00100240 .word 1073876992 - 63 003c 0000FFF8 .word -117506048 - 64 .cfi_endproc - 65 .LFE29: - 67 .section .text.RCC_HSEConfig,"ax",%progbits - 68 .align 2 - 69 .global RCC_HSEConfig - 70 .thumb - 71 .thumb_func - 73 RCC_HSEConfig: - 74 .LFB30: - 256:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif /* STM32F10X_CL */ - 257:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 258:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 259:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 260:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 261:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the External High Speed oscillator (HSE). - 262:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note HSE can not be stopped if it is used directly or through the PLL as system clock. - 263:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_HSE: specifies the new state of the HSE. - 264:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be one of the following values: - 265:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_HSE_OFF: HSE oscillator OFF - 266:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_HSE_ON: HSE oscillator ON - 267:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - 268:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 269:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 270:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_HSEConfig(uint32_t RCC_HSE) - 271:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 75 .loc 1 271 0 - 76 .cfi_startproc - 77 @ args = 0, pretend = 0, frame = 0 - 78 @ frame_needed = 0, uses_anonymous_args = 0 - 79 @ link register save eliminated. - 80 .LVL0: - 272:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 273:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_HSE(RCC_HSE)); - 274:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - 275:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Reset HSEON bit */ - 276:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CR &= CR_HSEON_Reset; - 81 .loc 1 276 0 - 82 0000 0D4B ldr r3, .L8 - 83 0002 1A68 ldr r2, [r3] - 84 0004 22F48032 bic r2, r2, #65536 - 85 0008 1A60 str r2, [r3] - 277:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Reset HSEBYP bit */ - 278:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CR &= CR_HSEBYP_Reset; - 86 .loc 1 278 0 - 87 000a 1A68 ldr r2, [r3] - 88 000c 22F48022 bic r2, r2, #262144 - 89 0010 1A60 str r2, [r3] - 279:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ - 280:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** switch(RCC_HSE) - 90 .loc 1 280 0 - 91 0012 B0F5803F cmp r0, #65536 - 92 0016 03D0 beq .L6 - 93 0018 B0F5802F cmp r0, #262144 - 94 001c 06D0 beq .L7 - 95 001e 7047 bx lr - 96 .L6: - 281:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 282:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** case RCC_HSE_ON: - 283:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set HSEON bit */ - 284:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CR |= CR_HSEON_Set; - 97 .loc 1 284 0 - 98 0020 054A ldr r2, .L8 - 99 0022 1368 ldr r3, [r2] - 100 0024 43F48033 orr r3, r3, #65536 - 101 0028 1360 str r3, [r2] - 285:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** break; - 102 .loc 1 285 0 - 103 002a 7047 bx lr - 104 .L7: - 286:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 287:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** case RCC_HSE_Bypass: - 288:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set HSEBYP and HSEON bits */ - 289:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; - 105 .loc 1 289 0 - 106 002c 024A ldr r2, .L8 - 107 002e 1368 ldr r3, [r2] - 108 0030 43F4A023 orr r3, r3, #327680 - 109 0034 1360 str r3, [r2] - 110 0036 7047 bx lr - 111 .L9: - 112 .align 2 - 113 .L8: - 114 0038 00100240 .word 1073876992 - 115 .cfi_endproc - 116 .LFE30: - 118 .section .text.RCC_AdjustHSICalibrationValue,"ax",%progbits - 119 .align 2 - 120 .global RCC_AdjustHSICalibrationValue - 121 .thumb - 122 .thumb_func - 124 RCC_AdjustHSICalibrationValue: - 125 .LFB32: - 290:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** break; - 291:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 292:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** default: - 293:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** break; - 294:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 295:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 296:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 297:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 298:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Waits for HSE start-up. - 299:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param None - 300:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval An ErrorStatus enumuration value: - 301:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - SUCCESS: HSE oscillator is stable and ready to use - 302:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - ERROR: HSE oscillator not yet ready - 303:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 304:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** ErrorStatus RCC_WaitForHSEStartUp(void) - 305:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 306:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** __IO uint32_t StartUpCounter = 0; - 307:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** ErrorStatus status = ERROR; - 308:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** FlagStatus HSEStatus = RESET; - 309:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 310:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Wait till HSE is ready and if Time out is reached exit */ - 311:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** do - 312:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 313:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - 314:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** StartUpCounter++; - 315:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - 316:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 317:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - 318:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 319:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** status = SUCCESS; - 320:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 321:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else - 322:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 323:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** status = ERROR; - 324:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 325:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** return (status); - 326:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 327:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 328:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 329:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - 330:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param HSICalibrationValue: specifies the calibration trimming value. - 331:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter must be a number between 0 and 0x1F. - 332:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 333:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 334:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) - 335:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 126 .loc 1 335 0 - 127 .cfi_startproc - 128 @ args = 0, pretend = 0, frame = 0 - 129 @ frame_needed = 0, uses_anonymous_args = 0 - 130 @ link register save eliminated. - 131 .LVL1: - 336:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t tmpreg = 0; - 337:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 338:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - 339:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg = RCC->CR; - 132 .loc 1 339 0 - 133 0000 034A ldr r2, .L11 - 134 0002 1368 ldr r3, [r2] - 135 .LVL2: - 340:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Clear HSITRIM[4:0] bits */ - 341:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg &= CR_HSITRIM_Mask; - 136 .loc 1 341 0 - 137 0004 23F0F803 bic r3, r3, #248 - 138 .LVL3: - 342:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - 343:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg |= (uint32_t)HSICalibrationValue << 3; - 139 .loc 1 343 0 - 140 0008 43EAC000 orr r0, r3, r0, lsl #3 - 141 .LVL4: - 344:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Store the new value */ - 345:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CR = tmpreg; - 142 .loc 1 345 0 - 143 000c 1060 str r0, [r2] - 144 000e 7047 bx lr - 145 .L12: - 146 .align 2 - 147 .L11: - 148 0010 00100240 .word 1073876992 - 149 .cfi_endproc - 150 .LFE32: - 152 .section .text.RCC_HSICmd,"ax",%progbits - 153 .align 2 - 154 .global RCC_HSICmd - 155 .thumb - 156 .thumb_func - 158 RCC_HSICmd: - 159 .LFB33: - 346:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 347:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 348:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 349:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Enables or disables the Internal High Speed oscillator (HSI). - 350:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note HSI can not be stopped if it is used directly or through the PLL as system clock. - 351:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. - 352:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 353:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 354:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_HSICmd(FunctionalState NewState) - 355:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 160 .loc 1 355 0 - 161 .cfi_startproc - 162 @ args = 0, pretend = 0, frame = 0 - 163 @ frame_needed = 0, uses_anonymous_args = 0 - 164 @ link register save eliminated. - 165 .LVL5: - 356:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 357:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 358:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; - 166 .loc 1 358 0 - 167 0000 014B ldr r3, .L14 - 168 0002 1860 str r0, [r3] - 169 0004 7047 bx lr - 170 .L15: - 171 0006 00BF .align 2 - 172 .L14: - 173 0008 00004242 .word 1111621632 - 174 .cfi_endproc - 175 .LFE33: - 177 .section .text.RCC_PLLConfig,"ax",%progbits - 178 .align 2 - 179 .global RCC_PLLConfig - 180 .thumb - 181 .thumb_func - 183 RCC_PLLConfig: - 184 .LFB34: - 359:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 360:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 361:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 362:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the PLL clock source and multiplication factor. - 363:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note This function must be used only when the PLL is disabled. - 364:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_PLLSource: specifies the PLL entry clock source. - 365:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, - 366:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * this parameter can be one of the following values: - 367:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - 368:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry - 369:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b other_STM32_devices, this parameter can be one of the following values: - 370:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - 371:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry - 372:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry - 373:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_PLLMul: specifies the PLL multiplication factor. - 374:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_ - 375:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] - 376:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 377:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 378:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) - 379:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 185 .loc 1 379 0 - 186 .cfi_startproc - 187 @ args = 0, pretend = 0, frame = 0 - 188 @ frame_needed = 0, uses_anonymous_args = 0 - 189 @ link register save eliminated. - 190 .LVL6: - 380:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t tmpreg = 0; - 381:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 382:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 383:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - 384:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); - 385:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 386:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR; - 191 .loc 1 386 0 - 192 0000 034A ldr r2, .L17 - 193 0002 5368 ldr r3, [r2, #4] - 194 .LVL7: - 387:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - 388:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg &= CFGR_PLL_Mask; - 195 .loc 1 388 0 - 196 0004 23F47C13 bic r3, r3, #4128768 - 197 .LVL8: - 198 0008 1943 orrs r1, r1, r3 - 199 .LVL9: - 389:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set the PLL configuration bits */ - 390:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg |= RCC_PLLSource | RCC_PLLMul; - 200 .loc 1 390 0 - 201 000a 0843 orrs r0, r0, r1 - 202 .LVL10: - 391:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Store the new value */ - 392:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR = tmpreg; - 203 .loc 1 392 0 - 204 000c 5060 str r0, [r2, #4] - 205 000e 7047 bx lr - 206 .L18: - 207 .align 2 - 208 .L17: - 209 0010 00100240 .word 1073876992 - 210 .cfi_endproc - 211 .LFE34: - 213 .section .text.RCC_PLLCmd,"ax",%progbits - 214 .align 2 - 215 .global RCC_PLLCmd - 216 .thumb - 217 .thumb_func - 219 RCC_PLLCmd: - 220 .LFB35: - 393:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 394:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 395:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 396:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Enables or disables the PLL. - 397:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note The PLL can not be disabled if it is used as system clock. - 398:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. - 399:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 400:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 401:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_PLLCmd(FunctionalState NewState) - 402:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 221 .loc 1 402 0 - 222 .cfi_startproc - 223 @ args = 0, pretend = 0, frame = 0 - 224 @ frame_needed = 0, uses_anonymous_args = 0 - 225 @ link register save eliminated. - 226 .LVL11: - 403:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 404:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 405:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 406:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; - 227 .loc 1 406 0 - 228 0000 014B ldr r3, .L20 - 229 0002 1860 str r0, [r3] - 230 0004 7047 bx lr - 231 .L21: - 232 0006 00BF .align 2 - 233 .L20: - 234 0008 60004242 .word 1111621728 - 235 .cfi_endproc - 236 .LFE35: - 238 .section .text.RCC_SYSCLKConfig,"ax",%progbits - 239 .align 2 - 240 .global RCC_SYSCLKConfig - 241 .thumb - 242 .thumb_func - 244 RCC_SYSCLKConfig: - 245 .LFB36: - 407:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 408:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 409:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined - 410:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 411:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the PREDIV1 division factor. - 412:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note - 413:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - This function must be used only when the PLL is disabled. - 414:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - This function applies only to STM32 Connectivity line and Value line - 415:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * devices. - 416:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. - 417:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be one of the following values: - 418:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock - 419:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock - 420:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note - 421:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE - 422:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. - 423:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be RCC_PREDIV1_Divx where x:[1,16] - 424:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 425:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 426:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) - 427:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 428:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t tmpreg = 0; - 429:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 430:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 431:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); - 432:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); - 433:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 434:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR2; - 435:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ - 436:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); - 437:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set the PREDIV1 clock source and division factor */ - 438:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; - 439:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Store the new value */ - 440:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR2 = tmpreg; - 441:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 442:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif - 443:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 444:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #ifdef STM32F10X_CL - 445:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 446:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the PREDIV2 division factor. - 447:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note - 448:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - This function must be used only when both PLL2 and PLL3 are disabled. - 449:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - This function applies only to STM32 Connectivity line devices. - 450:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. - 451:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be RCC_PREDIV2_Divx where x:[1,16] - 452:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 453:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 454:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) - 455:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 456:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t tmpreg = 0; - 457:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 458:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 459:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); - 460:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 461:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR2; - 462:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Clear PREDIV2[3:0] bits */ - 463:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg &= ~CFGR2_PREDIV2; - 464:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set the PREDIV2 division factor */ - 465:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg |= RCC_PREDIV2_Div; - 466:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Store the new value */ - 467:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR2 = tmpreg; - 468:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 469:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 470:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 471:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the PLL2 multiplication factor. - 472:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note - 473:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - This function must be used only when the PLL2 is disabled. - 474:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - This function applies only to STM32 Connectivity line devices. - 475:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. - 476:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} - 477:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 478:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 479:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_PLL2Config(uint32_t RCC_PLL2Mul) - 480:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 481:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t tmpreg = 0; - 482:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 483:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 484:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); - 485:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 486:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR2; - 487:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Clear PLL2Mul[3:0] bits */ - 488:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg &= ~CFGR2_PLL2MUL; - 489:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set the PLL2 configuration bits */ - 490:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg |= RCC_PLL2Mul; - 491:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Store the new value */ - 492:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR2 = tmpreg; - 493:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 494:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 495:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 496:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 497:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Enables or disables the PLL2. - 498:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note - 499:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - The PLL2 can not be disabled if it is used indirectly as system clock - 500:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * (i.e. it is used as PLL clock entry that is used as System clock). - 501:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - This function applies only to STM32 Connectivity line devices. - 502:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. - 503:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 504:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 505:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_PLL2Cmd(FunctionalState NewState) - 506:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 507:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 508:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 509:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 510:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; - 511:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 512:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 513:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 514:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 515:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the PLL3 multiplication factor. - 516:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note - 517:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - This function must be used only when the PLL3 is disabled. - 518:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - This function applies only to STM32 Connectivity line devices. - 519:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. - 520:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} - 521:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 522:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 523:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_PLL3Config(uint32_t RCC_PLL3Mul) - 524:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 525:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t tmpreg = 0; - 526:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 527:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 528:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); - 529:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 530:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR2; - 531:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Clear PLL3Mul[3:0] bits */ - 532:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg &= ~CFGR2_PLL3MUL; - 533:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set the PLL3 configuration bits */ - 534:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg |= RCC_PLL3Mul; - 535:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Store the new value */ - 536:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR2 = tmpreg; - 537:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 538:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 539:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 540:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 541:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Enables or disables the PLL3. - 542:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note This function applies only to STM32 Connectivity line devices. - 543:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. - 544:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 545:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 546:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_PLL3Cmd(FunctionalState NewState) - 547:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 548:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 549:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 550:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 551:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; - 552:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 553:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif /* STM32F10X_CL */ - 554:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 555:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 556:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the system clock (SYSCLK). - 557:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - 558:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be one of the following values: - 559:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock - 560:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock - 561:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock - 562:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 563:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 564:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) - 565:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 246 .loc 1 565 0 - 247 .cfi_startproc - 248 @ args = 0, pretend = 0, frame = 0 - 249 @ frame_needed = 0, uses_anonymous_args = 0 - 250 @ link register save eliminated. - 251 .LVL12: - 566:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t tmpreg = 0; - 567:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 568:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - 569:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR; - 252 .loc 1 569 0 - 253 0000 034A ldr r2, .L23 - 254 0002 5368 ldr r3, [r2, #4] - 255 .LVL13: - 570:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Clear SW[1:0] bits */ - 571:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg &= CFGR_SW_Mask; - 256 .loc 1 571 0 - 257 0004 23F00303 bic r3, r3, #3 - 258 .LVL14: - 572:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - 573:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg |= RCC_SYSCLKSource; - 259 .loc 1 573 0 - 260 0008 1843 orrs r0, r0, r3 - 261 .LVL15: - 574:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Store the new value */ - 575:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR = tmpreg; - 262 .loc 1 575 0 - 263 000a 5060 str r0, [r2, #4] - 264 000c 7047 bx lr - 265 .L24: - 266 000e 00BF .align 2 - 267 .L23: - 268 0010 00100240 .word 1073876992 - 269 .cfi_endproc - 270 .LFE36: - 272 .section .text.RCC_GetSYSCLKSource,"ax",%progbits - 273 .align 2 - 274 .global RCC_GetSYSCLKSource - 275 .thumb - 276 .thumb_func - 278 RCC_GetSYSCLKSource: - 279 .LFB37: - 576:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 577:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 578:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 579:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Returns the clock source used as system clock. - 580:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param None - 581:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval The clock source used as system clock. The returned value can - 582:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * be one of the following: - 583:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - 0x00: HSI used as system clock - 584:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - 0x04: HSE used as system clock - 585:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - 0x08: PLL used as system clock - 586:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 587:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint8_t RCC_GetSYSCLKSource(void) - 588:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 280 .loc 1 588 0 - 281 .cfi_startproc - 282 @ args = 0, pretend = 0, frame = 0 - 283 @ frame_needed = 0, uses_anonymous_args = 0 - 284 @ link register save eliminated. - 589:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); - 285 .loc 1 589 0 - 286 0000 024B ldr r3, .L26 - 287 0002 5868 ldr r0, [r3, #4] - 590:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 288 .loc 1 590 0 - 289 0004 00F00C00 and r0, r0, #12 - 290 0008 7047 bx lr - 291 .L27: - 292 000a 00BF .align 2 - 293 .L26: - 294 000c 00100240 .word 1073876992 - 295 .cfi_endproc - 296 .LFE37: - 298 .section .text.RCC_HCLKConfig,"ax",%progbits - 299 .align 2 - 300 .global RCC_HCLKConfig - 301 .thumb - 302 .thumb_func - 304 RCC_HCLKConfig: - 305 .LFB38: - 591:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 592:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 593:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the AHB clock (HCLK). - 594:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - 595:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * the system clock (SYSCLK). - 596:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be one of the following values: - 597:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - 598:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - 599:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - 600:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - 601:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - 602:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - 603:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - 604:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - 605:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - 606:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 607:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 608:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_HCLKConfig(uint32_t RCC_SYSCLK) - 609:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 306 .loc 1 609 0 - 307 .cfi_startproc - 308 @ args = 0, pretend = 0, frame = 0 - 309 @ frame_needed = 0, uses_anonymous_args = 0 - 310 @ link register save eliminated. - 311 .LVL16: - 610:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t tmpreg = 0; - 611:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 612:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - 613:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR; - 312 .loc 1 613 0 - 313 0000 034A ldr r2, .L29 - 314 0002 5368 ldr r3, [r2, #4] - 315 .LVL17: - 614:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Clear HPRE[3:0] bits */ - 615:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg &= CFGR_HPRE_Reset_Mask; - 316 .loc 1 615 0 - 317 0004 23F0F003 bic r3, r3, #240 - 318 .LVL18: - 616:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - 617:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg |= RCC_SYSCLK; - 319 .loc 1 617 0 - 320 0008 1843 orrs r0, r0, r3 - 321 .LVL19: - 618:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Store the new value */ - 619:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR = tmpreg; - 322 .loc 1 619 0 - 323 000a 5060 str r0, [r2, #4] - 324 000c 7047 bx lr - 325 .L30: - 326 000e 00BF .align 2 - 327 .L29: - 328 0010 00100240 .word 1073876992 - 329 .cfi_endproc - 330 .LFE38: - 332 .section .text.RCC_PCLK1Config,"ax",%progbits - 333 .align 2 - 334 .global RCC_PCLK1Config - 335 .thumb - 336 .thumb_func - 338 RCC_PCLK1Config: - 339 .LFB39: - 620:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 621:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 622:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 623:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the Low Speed APB clock (PCLK1). - 624:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - 625:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * the AHB clock (HCLK). - 626:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be one of the following values: - 627:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_HCLK_Div1: APB1 clock = HCLK - 628:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - 629:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - 630:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - 631:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - 632:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 633:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 634:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_PCLK1Config(uint32_t RCC_HCLK) - 635:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 340 .loc 1 635 0 - 341 .cfi_startproc - 342 @ args = 0, pretend = 0, frame = 0 - 343 @ frame_needed = 0, uses_anonymous_args = 0 - 344 @ link register save eliminated. - 345 .LVL20: - 636:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t tmpreg = 0; - 637:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 638:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_PCLK(RCC_HCLK)); - 639:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR; - 346 .loc 1 639 0 - 347 0000 034A ldr r2, .L32 - 348 0002 5368 ldr r3, [r2, #4] - 349 .LVL21: - 640:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Clear PPRE1[2:0] bits */ - 641:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg &= CFGR_PPRE1_Reset_Mask; - 350 .loc 1 641 0 - 351 0004 23F4E063 bic r3, r3, #1792 - 352 .LVL22: - 642:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - 643:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg |= RCC_HCLK; - 353 .loc 1 643 0 - 354 0008 1843 orrs r0, r0, r3 - 355 .LVL23: - 644:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Store the new value */ - 645:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR = tmpreg; - 356 .loc 1 645 0 - 357 000a 5060 str r0, [r2, #4] - 358 000c 7047 bx lr - 359 .L33: - 360 000e 00BF .align 2 - 361 .L32: - 362 0010 00100240 .word 1073876992 - 363 .cfi_endproc - 364 .LFE39: - 366 .section .text.RCC_PCLK2Config,"ax",%progbits - 367 .align 2 - 368 .global RCC_PCLK2Config - 369 .thumb - 370 .thumb_func - 372 RCC_PCLK2Config: - 373 .LFB40: - 646:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 647:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 648:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 649:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the High Speed APB clock (PCLK2). - 650:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - 651:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * the AHB clock (HCLK). - 652:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be one of the following values: - 653:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_HCLK_Div1: APB2 clock = HCLK - 654:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - 655:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - 656:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - 657:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - 658:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 659:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 660:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_PCLK2Config(uint32_t RCC_HCLK) - 661:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 374 .loc 1 661 0 - 375 .cfi_startproc - 376 @ args = 0, pretend = 0, frame = 0 - 377 @ frame_needed = 0, uses_anonymous_args = 0 - 378 @ link register save eliminated. - 379 .LVL24: - 662:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t tmpreg = 0; - 663:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 664:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_PCLK(RCC_HCLK)); - 665:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR; - 380 .loc 1 665 0 - 381 0000 034A ldr r2, .L35 - 382 0002 5368 ldr r3, [r2, #4] - 383 .LVL25: - 666:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Clear PPRE2[2:0] bits */ - 667:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg &= CFGR_PPRE2_Reset_Mask; - 384 .loc 1 667 0 - 385 0004 23F46053 bic r3, r3, #14336 - 386 .LVL26: - 668:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - 669:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg |= RCC_HCLK << 3; - 387 .loc 1 669 0 - 388 0008 43EAC000 orr r0, r3, r0, lsl #3 - 389 .LVL27: - 670:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Store the new value */ - 671:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR = tmpreg; - 390 .loc 1 671 0 - 391 000c 5060 str r0, [r2, #4] - 392 000e 7047 bx lr - 393 .L36: - 394 .align 2 - 395 .L35: - 396 0010 00100240 .word 1073876992 - 397 .cfi_endproc - 398 .LFE40: - 400 .section .text.RCC_ITConfig,"ax",%progbits - 401 .align 2 - 402 .global RCC_ITConfig - 403 .thumb - 404 .thumb_func - 406 RCC_ITConfig: - 407 .LFB41: - 672:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 673:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 674:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 675:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Enables or disables the specified RCC interrupts. - 676:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - 677:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - 678:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b STM32_Connectivity_line_devices, this parameter can be any combination - 679:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * of the following values - 680:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_LSIRDY: LSI ready interrupt - 681:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_LSERDY: LSE ready interrupt - 682:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_HSIRDY: HSI ready interrupt - 683:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_HSERDY: HSE ready interrupt - 684:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_PLLRDY: PLL ready interrupt - 685:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - 686:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - 687:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - 688:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b other_STM32_devices, this parameter can be any combination of the - 689:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * following values - 690:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_LSIRDY: LSI ready interrupt - 691:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_LSERDY: LSE ready interrupt - 692:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_HSIRDY: HSI ready interrupt - 693:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_HSERDY: HSE ready interrupt - 694:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_PLLRDY: PLL ready interrupt - 695:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - 696:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the specified RCC interrupts. - 697:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE. - 698:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 699:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 700:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) - 701:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 408 .loc 1 701 0 - 409 .cfi_startproc - 410 @ args = 0, pretend = 0, frame = 0 - 411 @ frame_needed = 0, uses_anonymous_args = 0 - 412 @ link register save eliminated. - 413 .LVL28: - 702:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 703:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_IT(RCC_IT)); - 704:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 705:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if (NewState != DISABLE) - 414 .loc 1 705 0 - 415 0000 21B1 cbz r1, .L38 - 706:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 707:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ - 708:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - 416 .loc 1 708 0 - 417 0002 054B ldr r3, .L40 - 418 0004 1A78 ldrb r2, [r3] @ zero_extendqisi2 - 419 0006 1043 orrs r0, r0, r2 - 420 .LVL29: - 421 0008 1870 strb r0, [r3] - 422 000a 7047 bx lr - 423 .LVL30: - 424 .L38: - 709:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 710:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else - 711:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 712:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ - 713:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - 425 .loc 1 713 0 - 426 000c 024A ldr r2, .L40 - 427 000e 1378 ldrb r3, [r2] @ zero_extendqisi2 - 428 0010 23EA0000 bic r0, r3, r0 - 429 .LVL31: - 430 0014 1070 strb r0, [r2] - 431 0016 7047 bx lr - 432 .L41: - 433 .align 2 - 434 .L40: - 435 0018 09100240 .word 1073877001 - 436 .cfi_endproc - 437 .LFE41: - 439 .section .text.RCC_USBCLKConfig,"ax",%progbits - 440 .align 2 - 441 .global RCC_USBCLKConfig - 442 .thumb - 443 .thumb_func - 445 RCC_USBCLKConfig: - 446 .LFB42: - 714:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 715:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 716:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 717:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #ifndef STM32F10X_CL - 718:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 719:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the USB clock (USBCLK). - 720:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_USBCLKSource: specifies the USB clock source. This clock is - 721:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * derived from the PLL output. - 722:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be one of the following values: - 723:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB - 724:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * clock source - 725:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source - 726:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 727:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 728:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) - 729:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 447 .loc 1 729 0 - 448 .cfi_startproc - 449 @ args = 0, pretend = 0, frame = 0 - 450 @ frame_needed = 0, uses_anonymous_args = 0 - 451 @ link register save eliminated. - 452 .LVL32: - 730:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 731:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); - 732:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 733:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; - 453 .loc 1 733 0 - 454 0000 014B ldr r3, .L43 - 455 0002 1860 str r0, [r3] - 456 0004 7047 bx lr - 457 .L44: - 458 0006 00BF .align 2 - 459 .L43: - 460 0008 D8004242 .word 1111621848 - 461 .cfi_endproc - 462 .LFE42: - 464 .section .text.RCC_ADCCLKConfig,"ax",%progbits - 465 .align 2 - 466 .global RCC_ADCCLKConfig - 467 .thumb - 468 .thumb_func - 470 RCC_ADCCLKConfig: - 471 .LFB43: - 734:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 735:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #else - 736:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 737:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the USB OTG FS clock (OTGFSCLK). - 738:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This function applies only to STM32 Connectivity line devices. - 739:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. - 740:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This clock is derived from the PLL output. - 741:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be one of the following values: - 742:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clo - 743:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clo - 744:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 745:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 746:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) - 747:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 748:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 749:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); - 750:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 751:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; - 752:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 753:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif /* STM32F10X_CL */ - 754:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 755:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 756:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the ADC clock (ADCCLK). - 757:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from - 758:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * the APB2 clock (PCLK2). - 759:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be one of the following values: - 760:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 - 761:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 - 762:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 - 763:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 - 764:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 765:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 766:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) - 767:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 472 .loc 1 767 0 - 473 .cfi_startproc - 474 @ args = 0, pretend = 0, frame = 0 - 475 @ frame_needed = 0, uses_anonymous_args = 0 - 476 @ link register save eliminated. - 477 .LVL33: - 768:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t tmpreg = 0; - 769:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 770:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); - 771:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR; - 478 .loc 1 771 0 - 479 0000 034A ldr r2, .L46 - 480 0002 5368 ldr r3, [r2, #4] - 481 .LVL34: - 772:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Clear ADCPRE[1:0] bits */ - 773:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg &= CFGR_ADCPRE_Reset_Mask; - 482 .loc 1 773 0 - 483 0004 23F44043 bic r3, r3, #49152 - 484 .LVL35: - 774:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ - 775:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmpreg |= RCC_PCLK2; - 485 .loc 1 775 0 - 486 0008 1843 orrs r0, r0, r3 - 487 .LVL36: - 776:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Store the new value */ - 777:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CFGR = tmpreg; - 488 .loc 1 777 0 - 489 000a 5060 str r0, [r2, #4] - 490 000c 7047 bx lr - 491 .L47: - 492 000e 00BF .align 2 - 493 .L46: - 494 0010 00100240 .word 1073876992 - 495 .cfi_endproc - 496 .LFE43: - 498 .section .text.RCC_LSEConfig,"ax",%progbits - 499 .align 2 - 500 .global RCC_LSEConfig - 501 .thumb - 502 .thumb_func - 504 RCC_LSEConfig: - 505 .LFB44: - 778:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 779:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 780:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #ifdef STM32F10X_CL - 781:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 782:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the I2S2 clock source(I2S2CLK). - 783:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note - 784:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - This function must be called before enabling I2S2 APB clock. - 785:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - This function applies only to STM32 Connectivity line devices. - 786:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. - 787:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be one of the following values: - 788:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry - 789:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry - 790:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 791:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 792:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) - 793:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 794:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 795:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); - 796:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 797:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; - 798:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 799:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 800:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 801:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the I2S3 clock source(I2S2CLK). - 802:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note - 803:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - This function must be called before enabling I2S3 APB clock. - 804:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * - This function applies only to STM32 Connectivity line devices. - 805:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. - 806:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be one of the following values: - 807:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry - 808:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry - 809:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 810:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 811:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) - 812:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 813:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 814:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); - 815:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 816:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; - 817:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 818:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif /* STM32F10X_CL */ - 819:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 820:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 821:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the External Low Speed oscillator (LSE). - 822:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_LSE: specifies the new state of the LSE. - 823:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be one of the following values: - 824:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_LSE_OFF: LSE oscillator OFF - 825:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_LSE_ON: LSE oscillator ON - 826:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - 827:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 828:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 829:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_LSEConfig(uint8_t RCC_LSE) - 830:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 506 .loc 1 830 0 - 507 .cfi_startproc - 508 @ args = 0, pretend = 0, frame = 0 - 509 @ frame_needed = 0, uses_anonymous_args = 0 - 510 @ link register save eliminated. - 511 .LVL37: - 831:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 832:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_LSE(RCC_LSE)); - 833:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - 834:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Reset LSEON bit */ - 835:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - 512 .loc 1 835 0 - 513 0000 084B ldr r3, .L52 - 514 0002 0022 movs r2, #0 - 515 0004 1A70 strb r2, [r3] - 836:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Reset LSEBYP bit */ - 837:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - 516 .loc 1 837 0 - 517 0006 1A70 strb r2, [r3] - 838:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - 839:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** switch(RCC_LSE) - 518 .loc 1 839 0 - 519 0008 0128 cmp r0, #1 - 520 000a 02D0 beq .L50 - 521 000c 0428 cmp r0, #4 - 522 000e 04D0 beq .L51 - 523 0010 7047 bx lr - 524 .L50: - 840:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 841:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** case RCC_LSE_ON: - 842:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set LSEON bit */ - 843:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - 525 .loc 1 843 0 - 526 0012 0122 movs r2, #1 - 527 0014 034B ldr r3, .L52 - 528 0016 1A70 strb r2, [r3] - 844:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** break; - 529 .loc 1 844 0 - 530 0018 7047 bx lr - 531 .L51: - 845:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 846:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** case RCC_LSE_Bypass: - 847:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set LSEBYP and LSEON bits */ - 848:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - 532 .loc 1 848 0 - 533 001a 0522 movs r2, #5 - 534 001c 014B ldr r3, .L52 - 535 001e 1A70 strb r2, [r3] - 536 0020 7047 bx lr - 537 .L53: - 538 0022 00BF .align 2 - 539 .L52: - 540 0024 20100240 .word 1073877024 - 541 .cfi_endproc - 542 .LFE44: - 544 .section .text.RCC_LSICmd,"ax",%progbits - 545 .align 2 - 546 .global RCC_LSICmd - 547 .thumb - 548 .thumb_func - 550 RCC_LSICmd: - 551 .LFB45: - 849:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** break; - 850:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 851:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** default: - 852:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** break; - 853:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 854:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 855:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 856:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 857:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Enables or disables the Internal Low Speed oscillator (LSI). - 858:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note LSI can not be disabled if the IWDG is running. - 859:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. - 860:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 861:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 862:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_LSICmd(FunctionalState NewState) - 863:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 552 .loc 1 863 0 - 553 .cfi_startproc - 554 @ args = 0, pretend = 0, frame = 0 - 555 @ frame_needed = 0, uses_anonymous_args = 0 - 556 @ link register save eliminated. - 557 .LVL38: - 864:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 865:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 866:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; - 558 .loc 1 866 0 - 559 0000 014B ldr r3, .L55 - 560 0002 1860 str r0, [r3] - 561 0004 7047 bx lr - 562 .L56: - 563 0006 00BF .align 2 - 564 .L55: - 565 0008 80044242 .word 1111622784 - 566 .cfi_endproc - 567 .LFE45: - 569 .section .text.RCC_RTCCLKConfig,"ax",%progbits - 570 .align 2 - 571 .global RCC_RTCCLKConfig - 572 .thumb - 573 .thumb_func - 575 RCC_RTCCLKConfig: - 576 .LFB46: - 867:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 868:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 869:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 870:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Configures the RTC clock (RTCCLK). - 871:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset. - 872:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_RTCCLKSource: specifies the RTC clock source. - 873:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be one of the following values: - 874:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - 875:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - 876:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock - 877:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 878:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 879:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) - 880:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 577 .loc 1 880 0 - 578 .cfi_startproc - 579 @ args = 0, pretend = 0, frame = 0 - 580 @ frame_needed = 0, uses_anonymous_args = 0 - 581 @ link register save eliminated. - 582 .LVL39: - 881:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 882:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - 883:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Select the RTC clock source */ - 884:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->BDCR |= RCC_RTCCLKSource; - 583 .loc 1 884 0 - 584 0000 024A ldr r2, .L58 - 585 0002 136A ldr r3, [r2, #32] - 586 0004 1843 orrs r0, r0, r3 - 587 .LVL40: - 588 0006 1062 str r0, [r2, #32] - 589 0008 7047 bx lr - 590 .L59: - 591 000a 00BF .align 2 - 592 .L58: - 593 000c 00100240 .word 1073876992 - 594 .cfi_endproc - 595 .LFE46: - 597 .section .text.RCC_RTCCLKCmd,"ax",%progbits - 598 .align 2 - 599 .global RCC_RTCCLKCmd - 600 .thumb - 601 .thumb_func - 603 RCC_RTCCLKCmd: - 604 .LFB47: - 885:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 886:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 887:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 888:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Enables or disables the RTC clock. - 889:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKCo - 890:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - 891:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 892:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 893:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_RTCCLKCmd(FunctionalState NewState) - 894:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 605 .loc 1 894 0 - 606 .cfi_startproc - 607 @ args = 0, pretend = 0, frame = 0 - 608 @ frame_needed = 0, uses_anonymous_args = 0 - 609 @ link register save eliminated. - 610 .LVL41: - 895:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ - 896:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 897:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; - 611 .loc 1 897 0 - 612 0000 014B ldr r3, .L61 - 613 0002 1860 str r0, [r3] - 614 0004 7047 bx lr - 615 .L62: - 616 0006 00BF .align 2 - 617 .L61: - 618 0008 3C044242 .word 1111622716 - 619 .cfi_endproc - 620 .LFE47: - 622 .section .text.RCC_GetClocksFreq,"ax",%progbits - 623 .align 2 - 624 .global RCC_GetClocksFreq - 625 .thumb - 626 .thumb_func - 628 RCC_GetClocksFreq: - 629 .LFB48: - 898:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 899:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 900:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** - 901:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Returns the frequencies of different on chip clocks. - 902:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - 903:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * the clocks frequencies. - 904:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note The result of this function could be not correct when using - 905:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * fractional value for HSE crystal. - 906:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None - 907:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ - 908:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) - 909:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 630 .loc 1 909 0 - 631 .cfi_startproc - 632 @ args = 0, pretend = 0, frame = 0 - 633 @ frame_needed = 0, uses_anonymous_args = 0 - 634 @ link register save eliminated. - 635 .LVL42: - 636 0000 10B4 push {r4} - 637 .cfi_def_cfa_offset 4 - 638 .cfi_offset 4, -4 - 639 .LVL43: - 910:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; - 911:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 912:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #ifdef STM32F10X_CL - 913:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; - 914:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif /* STM32F10X_CL */ - 915:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 916:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - 917:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t prediv1factor = 0; - 918:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif - 919:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 920:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Get SYSCLK source -------------------------------------------------------*/ - 921:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmp = RCC->CFGR & CFGR_SWS_Mask; - 640 .loc 1 921 0 - 641 0002 274B ldr r3, .L73 - 642 0004 5B68 ldr r3, [r3, #4] - 643 .LVL44: - 644 0006 03F00C03 and r3, r3, #12 - 645 .LVL45: - 922:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 923:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** switch (tmp) - 646 .loc 1 923 0 - 647 000a 042B cmp r3, #4 - 648 000c 05D0 beq .L65 - 649 000e 082B cmp r3, #8 - 650 0010 06D0 beq .L66 - 651 0012 F3B9 cbnz r3, .L71 - 924:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 925:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** case 0x00: /* HSI used as system clock */ - 926:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - 652 .loc 1 926 0 - 653 0014 234B ldr r3, .L73+4 - 654 .LVL46: - 655 0016 0360 str r3, [r0] - 927:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** break; - 656 .loc 1 927 0 - 657 0018 1DE0 b .L68 - 658 .LVL47: - 659 .L65: - 928:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** case 0x04: /* HSE used as system clock */ - 929:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - 660 .loc 1 929 0 - 661 001a 224B ldr r3, .L73+4 - 662 .LVL48: - 663 001c 0360 str r3, [r0] - 930:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** break; - 664 .loc 1 930 0 - 665 001e 1AE0 b .L68 - 666 .LVL49: - 667 .L66: - 931:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** case 0x08: /* PLL used as system clock */ - 932:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 933:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Get PLL clock source and multiplication factor ----------------------*/ - 934:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** pllmull = RCC->CFGR & CFGR_PLLMull_Mask; - 668 .loc 1 934 0 - 669 0020 1F4A ldr r2, .L73 - 670 0022 5368 ldr r3, [r2, #4] - 671 .LVL50: - 935:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; - 672 .loc 1 935 0 - 673 0024 5268 ldr r2, [r2, #4] - 674 .LVL51: - 936:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 937:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #ifndef STM32F10X_CL - 938:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** pllmull = ( pllmull >> 18) + 2; - 675 .loc 1 938 0 - 676 0026 C3F38343 ubfx r3, r3, #18, #4 - 677 .LVL52: - 678 002a 0233 adds r3, r3, #2 - 679 .LVL53: - 939:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 940:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if (pllsource == 0x00) - 680 .loc 1 940 0 - 681 002c 12F4803F tst r2, #65536 - 682 0030 04D1 bne .L69 - 941:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - 942:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; - 683 .loc 1 942 0 - 684 0032 1D4A ldr r2, .L73+8 - 685 .LVL54: - 686 0034 02FB03F3 mul r3, r2, r3 - 687 .LVL55: - 688 0038 0360 str r3, [r0] - 689 003a 0CE0 b .L68 - 690 .LVL56: - 691 .L69: - 943:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 944:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else - 945:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 946:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - 947:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; - 948:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ - 949:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; - 950:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #else - 951:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* HSE selected as PLL clock entry */ - 952:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) - 692 .loc 1 952 0 - 693 003c 184A ldr r2, .L73 - 694 .LVL57: - 695 003e 5268 ldr r2, [r2, #4] - 696 0040 12F4003F tst r2, #131072 - 953:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** {/* HSE oscillator clock divided by 2 */ - 954:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; - 697 .loc 1 954 0 - 698 0044 14BF ite ne - 699 0046 184A ldrne r2, .L73+8 - 955:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 956:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else - 957:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 958:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; - 700 .loc 1 958 0 - 701 0048 164A ldreq r2, .L73+4 - 702 004a 02FB03F3 mul r3, r2, r3 - 703 .LVL58: - 704 004e 0360 str r3, [r0] - 705 0050 01E0 b .L68 - 706 .LVL59: - 707 .L71: - 959:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 960:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif - 961:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 962:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #else - 963:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** pllmull = pllmull >> 18; - 964:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 965:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if (pllmull != 0x0D) - 966:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 967:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** pllmull += 2; - 968:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 969:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else - 970:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { /* PLL multiplication factor = PLL input clock * 6.5 */ - 971:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** pllmull = 13 / 2; - 972:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 973:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 974:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if (pllsource == 0x00) - 975:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - 976:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; - 977:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 978:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else - 979:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** {/* PREDIV1 selected as PLL clock entry */ - 980:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 981:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Get PREDIV1 clock source and division factor */ - 982:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; - 983:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; - 984:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 985:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if (prediv1source == 0) - 986:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { /* HSE oscillator clock selected as PREDIV1 clock entry */ - 987:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; - 988:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 989:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else - 990:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** {/* PLL2 clock selected as PREDIV1 clock entry */ - 991:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 992:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Get PREDIV2 division factor and PLL2 multiplication factor */ - 993:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; - 994:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; - 995:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) - 996:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 997:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 998:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif /* STM32F10X_CL */ - 999:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** break; -1000:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1001:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** default: -1002:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - 708 .loc 1 1002 0 - 709 0052 144B ldr r3, .L73+4 - 710 .LVL60: - 711 0054 0360 str r3, [r0] - 712 .LVL61: - 713 .L68: -1003:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** break; -1004:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1005:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1006:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ -1007:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Get HCLK prescaler */ -1008:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; - 714 .loc 1 1008 0 - 715 0056 124A ldr r2, .L73 - 716 0058 5368 ldr r3, [r2, #4] - 717 .LVL62: -1009:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmp = tmp >> 4; - 718 .loc 1 1009 0 - 719 005a C3F30313 ubfx r3, r3, #4, #4 - 720 .LVL63: -1010:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** presc = APBAHBPrescTable[tmp]; - 721 .loc 1 1010 0 - 722 005e 134C ldr r4, .L73+12 - 723 0060 E15C ldrb r1, [r4, r3] @ zero_extendqisi2 - 724 0062 C9B2 uxtb r1, r1 - 725 .LVL64: -1011:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* HCLK clock frequency */ -1012:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - 726 .loc 1 1012 0 - 727 0064 0368 ldr r3, [r0] - 728 .LVL65: - 729 0066 CB40 lsrs r3, r3, r1 - 730 0068 4360 str r3, [r0, #4] -1013:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Get PCLK1 prescaler */ -1014:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; - 731 .loc 1 1014 0 - 732 006a 5168 ldr r1, [r2, #4] - 733 .LVL66: -1015:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmp = tmp >> 8; - 734 .loc 1 1015 0 - 735 006c C1F30221 ubfx r1, r1, #8, #3 - 736 .LVL67: -1016:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** presc = APBAHBPrescTable[tmp]; - 737 .loc 1 1016 0 - 738 0070 615C ldrb r1, [r4, r1] @ zero_extendqisi2 - 739 .LVL68: - 740 0072 C9B2 uxtb r1, r1 - 741 .LVL69: -1017:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* PCLK1 clock frequency */ -1018:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - 742 .loc 1 1018 0 - 743 0074 23FA01F1 lsr r1, r3, r1 - 744 .LVL70: - 745 0078 8160 str r1, [r0, #8] -1019:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Get PCLK2 prescaler */ -1020:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; - 746 .loc 1 1020 0 - 747 007a 5168 ldr r1, [r2, #4] - 748 .LVL71: -1021:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmp = tmp >> 11; - 749 .loc 1 1021 0 - 750 007c C1F3C221 ubfx r1, r1, #11, #3 - 751 .LVL72: -1022:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** presc = APBAHBPrescTable[tmp]; - 752 .loc 1 1022 0 - 753 0080 615C ldrb r1, [r4, r1] @ zero_extendqisi2 - 754 .LVL73: - 755 0082 C9B2 uxtb r1, r1 - 756 .LVL74: -1023:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* PCLK2 clock frequency */ -1024:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - 757 .loc 1 1024 0 - 758 0084 CB40 lsrs r3, r3, r1 - 759 0086 C360 str r3, [r0, #12] -1025:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Get ADCCLK prescaler */ -1026:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; - 760 .loc 1 1026 0 - 761 0088 5268 ldr r2, [r2, #4] - 762 .LVL75: -1027:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmp = tmp >> 14; - 763 .loc 1 1027 0 - 764 008a C2F38132 ubfx r2, r2, #14, #2 - 765 .LVL76: -1028:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** presc = ADCPrescTable[tmp]; - 766 .loc 1 1028 0 - 767 008e 0849 ldr r1, .L73+16 - 768 .LVL77: - 769 0090 8A5C ldrb r2, [r1, r2] @ zero_extendqisi2 - 770 .LVL78: - 771 0092 D2B2 uxtb r2, r2 - 772 .LVL79: -1029:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* ADCCLK clock frequency */ -1030:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; - 773 .loc 1 1030 0 - 774 0094 B3FBF2F3 udiv r3, r3, r2 - 775 0098 0361 str r3, [r0, #16] -1031:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 776 .loc 1 1031 0 - 777 009a 5DF8044B ldr r4, [sp], #4 - 778 .cfi_restore 4 - 779 .cfi_def_cfa_offset 0 - 780 009e 7047 bx lr - 781 .L74: - 782 .align 2 - 783 .L73: - 784 00a0 00100240 .word 1073876992 - 785 00a4 00127A00 .word 8000000 - 786 00a8 00093D00 .word 4000000 - 787 00ac 00000000 .word .LANCHOR0 - 788 00b0 00000000 .word .LANCHOR1 - 789 .cfi_endproc - 790 .LFE48: - 792 .section .text.RCC_AHBPeriphClockCmd,"ax",%progbits - 793 .align 2 - 794 .global RCC_AHBPeriphClockCmd - 795 .thumb - 796 .thumb_func - 798 RCC_AHBPeriphClockCmd: - 799 .LFB49: -1032:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1033:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** -1034:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Enables or disables the AHB peripheral clock. -1035:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. -1036:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1037:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b STM32_Connectivity_line_devices, this parameter can be any combination -1038:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * of the following values: -1039:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_DMA1 -1040:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_DMA2 -1041:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_SRAM -1042:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_FLITF -1043:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_CRC -1044:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_OTG_FS -1045:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_ETH_MAC -1046:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_ETH_MAC_Tx -1047:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_ETH_MAC_Rx -1048:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1049:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b other_STM32_devices, this parameter can be any combination of the -1050:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * following values: -1051:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_DMA1 -1052:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_DMA2 -1053:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_SRAM -1054:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_FLITF -1055:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_CRC -1056:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_FSMC -1057:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_SDIO -1058:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1059:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note SRAM and FLITF clock can be disabled only during sleep mode. -1060:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the specified peripheral clock. -1061:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE. -1062:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None -1063:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ -1064:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -1065:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 800 .loc 1 1065 0 - 801 .cfi_startproc - 802 @ args = 0, pretend = 0, frame = 0 - 803 @ frame_needed = 0, uses_anonymous_args = 0 - 804 @ link register save eliminated. - 805 .LVL80: -1066:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ -1067:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); -1068:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); -1069:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1070:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if (NewState != DISABLE) - 806 .loc 1 1070 0 - 807 0000 21B1 cbz r1, .L76 -1071:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1072:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->AHBENR |= RCC_AHBPeriph; - 808 .loc 1 1072 0 - 809 0002 054A ldr r2, .L78 - 810 0004 5369 ldr r3, [r2, #20] - 811 0006 1843 orrs r0, r0, r3 - 812 .LVL81: - 813 0008 5061 str r0, [r2, #20] - 814 000a 7047 bx lr - 815 .LVL82: - 816 .L76: -1073:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1074:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else -1075:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1076:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->AHBENR &= ~RCC_AHBPeriph; - 817 .loc 1 1076 0 - 818 000c 024A ldr r2, .L78 - 819 000e 5369 ldr r3, [r2, #20] - 820 0010 23EA0000 bic r0, r3, r0 - 821 .LVL83: - 822 0014 5061 str r0, [r2, #20] - 823 0016 7047 bx lr - 824 .L79: - 825 .align 2 - 826 .L78: - 827 0018 00100240 .word 1073876992 - 828 .cfi_endproc - 829 .LFE49: - 831 .section .text.RCC_APB2PeriphClockCmd,"ax",%progbits - 832 .align 2 - 833 .global RCC_APB2PeriphClockCmd - 834 .thumb - 835 .thumb_func - 837 RCC_APB2PeriphClockCmd: - 838 .LFB50: -1077:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1078:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1079:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1080:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** -1081:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Enables or disables the High Speed APB (APB2) peripheral clock. -1082:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. -1083:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be any combination of the following values: -1084:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, -1085:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, -1086:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, -1087:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, -1088:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, -1089:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, -1090:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 -1091:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the specified peripheral clock. -1092:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE. -1093:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None -1094:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ -1095:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -1096:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 839 .loc 1 1096 0 - 840 .cfi_startproc - 841 @ args = 0, pretend = 0, frame = 0 - 842 @ frame_needed = 0, uses_anonymous_args = 0 - 843 @ link register save eliminated. - 844 .LVL84: -1097:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ -1098:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); -1099:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); -1100:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if (NewState != DISABLE) - 845 .loc 1 1100 0 - 846 0000 21B1 cbz r1, .L81 -1101:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1102:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->APB2ENR |= RCC_APB2Periph; - 847 .loc 1 1102 0 - 848 0002 054A ldr r2, .L83 - 849 0004 9369 ldr r3, [r2, #24] - 850 0006 1843 orrs r0, r0, r3 - 851 .LVL85: - 852 0008 9061 str r0, [r2, #24] - 853 000a 7047 bx lr - 854 .LVL86: - 855 .L81: -1103:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1104:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else -1105:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1106:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->APB2ENR &= ~RCC_APB2Periph; - 856 .loc 1 1106 0 - 857 000c 024A ldr r2, .L83 - 858 000e 9369 ldr r3, [r2, #24] - 859 0010 23EA0000 bic r0, r3, r0 - 860 .LVL87: - 861 0014 9061 str r0, [r2, #24] - 862 0016 7047 bx lr - 863 .L84: - 864 .align 2 - 865 .L83: - 866 0018 00100240 .word 1073876992 - 867 .cfi_endproc - 868 .LFE50: - 870 .section .text.RCC_APB1PeriphClockCmd,"ax",%progbits - 871 .align 2 - 872 .global RCC_APB1PeriphClockCmd - 873 .thumb - 874 .thumb_func - 876 RCC_APB1PeriphClockCmd: - 877 .LFB51: -1107:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1108:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1109:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1110:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** -1111:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. -1112:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. -1113:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be any combination of the following values: -1114:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, -1115:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, -1116:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, -1117:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, -1118:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, -1119:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, -1120:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, -1121:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 -1122:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the specified peripheral clock. -1123:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE. -1124:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None -1125:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ -1126:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -1127:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 878 .loc 1 1127 0 - 879 .cfi_startproc - 880 @ args = 0, pretend = 0, frame = 0 - 881 @ frame_needed = 0, uses_anonymous_args = 0 - 882 @ link register save eliminated. - 883 .LVL88: -1128:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ -1129:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); -1130:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); -1131:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if (NewState != DISABLE) - 884 .loc 1 1131 0 - 885 0000 21B1 cbz r1, .L86 -1132:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1133:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->APB1ENR |= RCC_APB1Periph; - 886 .loc 1 1133 0 - 887 0002 054A ldr r2, .L88 - 888 0004 D369 ldr r3, [r2, #28] - 889 0006 1843 orrs r0, r0, r3 - 890 .LVL89: - 891 0008 D061 str r0, [r2, #28] - 892 000a 7047 bx lr - 893 .LVL90: - 894 .L86: -1134:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1135:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else -1136:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1137:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->APB1ENR &= ~RCC_APB1Periph; - 895 .loc 1 1137 0 - 896 000c 024A ldr r2, .L88 - 897 000e D369 ldr r3, [r2, #28] - 898 0010 23EA0000 bic r0, r3, r0 - 899 .LVL91: - 900 0014 D061 str r0, [r2, #28] - 901 0016 7047 bx lr - 902 .L89: - 903 .align 2 - 904 .L88: - 905 0018 00100240 .word 1073876992 - 906 .cfi_endproc - 907 .LFE51: - 909 .section .text.RCC_APB2PeriphResetCmd,"ax",%progbits - 910 .align 2 - 911 .global RCC_APB2PeriphResetCmd - 912 .thumb - 913 .thumb_func - 915 RCC_APB2PeriphResetCmd: - 916 .LFB52: -1138:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1139:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1140:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1141:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #ifdef STM32F10X_CL -1142:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** -1143:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Forces or releases AHB peripheral reset. -1144:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note This function applies only to STM32 Connectivity line devices. -1145:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. -1146:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be any combination of the following values: -1147:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_OTG_FS -1148:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_AHBPeriph_ETH_MAC -1149:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the specified peripheral reset. -1150:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE. -1151:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None -1152:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ -1153:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -1154:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1155:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ -1156:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); -1157:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); -1158:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1159:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if (NewState != DISABLE) -1160:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1161:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->AHBRSTR |= RCC_AHBPeriph; -1162:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1163:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else -1164:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1165:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->AHBRSTR &= ~RCC_AHBPeriph; -1166:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1167:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1168:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** #endif /* STM32F10X_CL */ -1169:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1170:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** -1171:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Forces or releases High Speed APB (APB2) peripheral reset. -1172:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. -1173:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be any combination of the following values: -1174:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, -1175:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, -1176:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, -1177:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, -1178:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, -1179:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, -1180:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 -1181:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the specified peripheral reset. -1182:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE. -1183:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None -1184:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ -1185:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -1186:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 917 .loc 1 1186 0 - 918 .cfi_startproc - 919 @ args = 0, pretend = 0, frame = 0 - 920 @ frame_needed = 0, uses_anonymous_args = 0 - 921 @ link register save eliminated. - 922 .LVL92: -1187:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ -1188:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); -1189:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); -1190:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if (NewState != DISABLE) - 923 .loc 1 1190 0 - 924 0000 21B1 cbz r1, .L91 -1191:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1192:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->APB2RSTR |= RCC_APB2Periph; - 925 .loc 1 1192 0 - 926 0002 054A ldr r2, .L93 - 927 0004 D368 ldr r3, [r2, #12] - 928 0006 1843 orrs r0, r0, r3 - 929 .LVL93: - 930 0008 D060 str r0, [r2, #12] - 931 000a 7047 bx lr - 932 .LVL94: - 933 .L91: -1193:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1194:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else -1195:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1196:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->APB2RSTR &= ~RCC_APB2Periph; - 934 .loc 1 1196 0 - 935 000c 024A ldr r2, .L93 - 936 000e D368 ldr r3, [r2, #12] - 937 0010 23EA0000 bic r0, r3, r0 - 938 .LVL95: - 939 0014 D060 str r0, [r2, #12] - 940 0016 7047 bx lr - 941 .L94: - 942 .align 2 - 943 .L93: - 944 0018 00100240 .word 1073876992 - 945 .cfi_endproc - 946 .LFE52: - 948 .section .text.RCC_APB1PeriphResetCmd,"ax",%progbits - 949 .align 2 - 950 .global RCC_APB1PeriphResetCmd - 951 .thumb - 952 .thumb_func - 954 RCC_APB1PeriphResetCmd: - 955 .LFB53: -1197:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1198:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1199:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1200:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** -1201:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Forces or releases Low Speed APB (APB1) peripheral reset. -1202:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. -1203:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be any combination of the following values: -1204:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, -1205:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, -1206:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, -1207:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, -1208:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, -1209:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, -1210:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, -1211:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 -1212:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the specified peripheral clock. -1213:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE. -1214:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None -1215:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ -1216:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -1217:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 956 .loc 1 1217 0 - 957 .cfi_startproc - 958 @ args = 0, pretend = 0, frame = 0 - 959 @ frame_needed = 0, uses_anonymous_args = 0 - 960 @ link register save eliminated. - 961 .LVL96: -1218:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ -1219:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); -1220:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); -1221:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if (NewState != DISABLE) - 962 .loc 1 1221 0 - 963 0000 21B1 cbz r1, .L96 -1222:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1223:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->APB1RSTR |= RCC_APB1Periph; - 964 .loc 1 1223 0 - 965 0002 054A ldr r2, .L98 - 966 0004 1369 ldr r3, [r2, #16] - 967 0006 1843 orrs r0, r0, r3 - 968 .LVL97: - 969 0008 1061 str r0, [r2, #16] - 970 000a 7047 bx lr - 971 .LVL98: - 972 .L96: -1224:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1225:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else -1226:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1227:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->APB1RSTR &= ~RCC_APB1Periph; - 973 .loc 1 1227 0 - 974 000c 024A ldr r2, .L98 - 975 000e 1369 ldr r3, [r2, #16] - 976 0010 23EA0000 bic r0, r3, r0 - 977 .LVL99: - 978 0014 1061 str r0, [r2, #16] - 979 0016 7047 bx lr - 980 .L99: - 981 .align 2 - 982 .L98: - 983 0018 00100240 .word 1073876992 - 984 .cfi_endproc - 985 .LFE53: - 987 .section .text.RCC_BackupResetCmd,"ax",%progbits - 988 .align 2 - 989 .global RCC_BackupResetCmd - 990 .thumb - 991 .thumb_func - 993 RCC_BackupResetCmd: - 994 .LFB54: -1228:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1229:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1230:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1231:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** -1232:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Forces or releases the Backup domain reset. -1233:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the Backup domain reset. -1234:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE. -1235:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None -1236:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ -1237:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_BackupResetCmd(FunctionalState NewState) -1238:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 995 .loc 1 1238 0 - 996 .cfi_startproc - 997 @ args = 0, pretend = 0, frame = 0 - 998 @ frame_needed = 0, uses_anonymous_args = 0 - 999 @ link register save eliminated. - 1000 .LVL100: -1239:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ -1240:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); -1241:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; - 1001 .loc 1 1241 0 - 1002 0000 014B ldr r3, .L101 - 1003 0002 1860 str r0, [r3] - 1004 0004 7047 bx lr - 1005 .L102: - 1006 0006 00BF .align 2 - 1007 .L101: - 1008 0008 40044242 .word 1111622720 - 1009 .cfi_endproc - 1010 .LFE54: - 1012 .section .text.RCC_ClockSecuritySystemCmd,"ax",%progbits - 1013 .align 2 - 1014 .global RCC_ClockSecuritySystemCmd - 1015 .thumb - 1016 .thumb_func - 1018 RCC_ClockSecuritySystemCmd: - 1019 .LFB55: -1242:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1243:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1244:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** -1245:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Enables or disables the Clock Security System. -1246:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param NewState: new state of the Clock Security System.. -1247:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE. -1248:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None -1249:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ -1250:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -1251:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 1020 .loc 1 1251 0 - 1021 .cfi_startproc - 1022 @ args = 0, pretend = 0, frame = 0 - 1023 @ frame_needed = 0, uses_anonymous_args = 0 - 1024 @ link register save eliminated. - 1025 .LVL101: -1252:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ -1253:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); -1254:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; - 1026 .loc 1 1254 0 - 1027 0000 014B ldr r3, .L104 - 1028 0002 1860 str r0, [r3] - 1029 0004 7047 bx lr - 1030 .L105: - 1031 0006 00BF .align 2 - 1032 .L104: - 1033 0008 4C004242 .word 1111621708 - 1034 .cfi_endproc - 1035 .LFE55: - 1037 .section .text.RCC_MCOConfig,"ax",%progbits - 1038 .align 2 - 1039 .global RCC_MCOConfig - 1040 .thumb - 1041 .thumb_func - 1043 RCC_MCOConfig: - 1044 .LFB56: -1255:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1256:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1257:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** -1258:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Selects the clock source to output on MCO pin. -1259:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_MCO: specifies the clock source to output. -1260:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1261:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b STM32_Connectivity_line_devices, this parameter can be one of the -1262:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * following values: -1263:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_NoClock: No clock selected -1264:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_SYSCLK: System clock selected -1265:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_HSI: HSI oscillator clock selected -1266:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_HSE: HSE oscillator clock selected -1267:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected -1268:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_PLL2CLK: PLL2 clock selected -1269:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected -1270:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected -1271:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_PLL3CLK: PLL3 clock selected -1272:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1273:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b other_STM32_devices, this parameter can be one of the following values: -1274:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_NoClock: No clock selected -1275:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_SYSCLK: System clock selected -1276:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_HSI: HSI oscillator clock selected -1277:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_HSE: HSE oscillator clock selected -1278:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected -1279:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1280:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None -1281:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ -1282:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_MCOConfig(uint8_t RCC_MCO) -1283:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 1045 .loc 1 1283 0 - 1046 .cfi_startproc - 1047 @ args = 0, pretend = 0, frame = 0 - 1048 @ frame_needed = 0, uses_anonymous_args = 0 - 1049 @ link register save eliminated. - 1050 .LVL102: -1284:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ -1285:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_MCO(RCC_MCO)); -1286:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1287:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Perform Byte access to MCO bits to select the MCO source */ -1288:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; - 1051 .loc 1 1288 0 - 1052 0000 014B ldr r3, .L107 - 1053 0002 1870 strb r0, [r3] - 1054 0004 7047 bx lr - 1055 .L108: - 1056 0006 00BF .align 2 - 1057 .L107: - 1058 0008 07100240 .word 1073876999 - 1059 .cfi_endproc - 1060 .LFE56: - 1062 .section .text.RCC_GetFlagStatus,"ax",%progbits - 1063 .align 2 - 1064 .global RCC_GetFlagStatus - 1065 .thumb - 1066 .thumb_func - 1068 RCC_GetFlagStatus: - 1069 .LFB57: -1289:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1290:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1291:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** -1292:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Checks whether the specified RCC flag is set or not. -1293:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_FLAG: specifies the flag to check. -1294:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1295:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b STM32_Connectivity_line_devices, this parameter can be one of the -1296:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * following values: -1297:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready -1298:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready -1299:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_PLLRDY: PLL clock ready -1300:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready -1301:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready -1302:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready -1303:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready -1304:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_PINRST: Pin reset -1305:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_PORRST: POR/PDR reset -1306:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_SFTRST: Software reset -1307:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset -1308:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_WWDGRST: Window Watchdog reset -1309:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_LPWRRST: Low Power reset -1310:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1311:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b other_STM32_devices, this parameter can be one of the following values: -1312:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready -1313:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready -1314:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_PLLRDY: PLL clock ready -1315:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready -1316:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready -1317:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_PINRST: Pin reset -1318:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_PORRST: POR/PDR reset -1319:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_SFTRST: Software reset -1320:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset -1321:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_WWDGRST: Window Watchdog reset -1322:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_FLAG_LPWRRST: Low Power reset -1323:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1324:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval The new state of RCC_FLAG (SET or RESET). -1325:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ -1326:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -1327:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 1070 .loc 1 1327 0 - 1071 .cfi_startproc - 1072 @ args = 0, pretend = 0, frame = 0 - 1073 @ frame_needed = 0, uses_anonymous_args = 0 - 1074 @ link register save eliminated. - 1075 .LVL103: -1328:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t tmp = 0; -1329:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** uint32_t statusreg = 0; -1330:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** FlagStatus bitstatus = RESET; -1331:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ -1332:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_FLAG(RCC_FLAG)); -1333:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1334:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Get the RCC register index */ -1335:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmp = RCC_FLAG >> 5; - 1076 .loc 1 1335 0 - 1077 0000 4309 lsrs r3, r0, #5 - 1078 .LVL104: -1336:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if (tmp == 1) /* The flag to check is in CR register */ - 1079 .loc 1 1336 0 - 1080 0002 012B cmp r3, #1 - 1081 0004 02D1 bne .L110 -1337:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1338:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** statusreg = RCC->CR; - 1082 .loc 1 1338 0 - 1083 0006 074B ldr r3, .L113 - 1084 .LVL105: - 1085 0008 1A68 ldr r2, [r3] - 1086 .LVL106: - 1087 000a 04E0 b .L111 - 1088 .LVL107: - 1089 .L110: -1339:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1340:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else if (tmp == 2) /* The flag to check is in BDCR register */ - 1090 .loc 1 1340 0 - 1091 000c 022B cmp r3, #2 -1341:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1342:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** statusreg = RCC->BDCR; - 1092 .loc 1 1342 0 - 1093 000e 054B ldr r3, .L113 - 1094 .LVL108: - 1095 0010 0CBF ite eq - 1096 0012 1A6A ldreq r2, [r3, #32] - 1097 .LVL109: -1343:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1344:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else /* The flag to check is in CSR register */ -1345:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1346:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** statusreg = RCC->CSR; - 1098 .loc 1 1346 0 - 1099 0014 5A6A ldrne r2, [r3, #36] - 1100 .LVL110: - 1101 .L111: -1347:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1348:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1349:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Get the flag position */ -1350:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** tmp = RCC_FLAG & FLAG_Mask; -1351:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - 1102 .loc 1 1351 0 - 1103 0016 00F01F03 and r3, r0, #31 - 1104 001a 22FA03F0 lsr r0, r2, r3 - 1105 .LVL111: -1352:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1353:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** bitstatus = SET; -1354:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1355:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else -1356:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1357:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** bitstatus = RESET; -1358:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1359:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1360:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Return the flag status */ -1361:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** return bitstatus; -1362:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 1106 .loc 1 1362 0 - 1107 001e 00F00100 and r0, r0, #1 - 1108 0022 7047 bx lr - 1109 .L114: - 1110 .align 2 - 1111 .L113: - 1112 0024 00100240 .word 1073876992 - 1113 .cfi_endproc - 1114 .LFE57: - 1116 .section .text.RCC_WaitForHSEStartUp,"ax",%progbits - 1117 .align 2 - 1118 .global RCC_WaitForHSEStartUp - 1119 .thumb - 1120 .thumb_func - 1122 RCC_WaitForHSEStartUp: - 1123 .LFB31: - 305:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** __IO uint32_t StartUpCounter = 0; - 1124 .loc 1 305 0 - 1125 .cfi_startproc - 1126 @ args = 0, pretend = 0, frame = 8 - 1127 @ frame_needed = 0, uses_anonymous_args = 0 - 1128 0000 10B5 push {r4, lr} - 1129 .cfi_def_cfa_offset 8 - 1130 .cfi_offset 4, -8 - 1131 .cfi_offset 14, -4 - 1132 0002 82B0 sub sp, sp, #8 - 1133 .cfi_def_cfa_offset 16 - 306:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** ErrorStatus status = ERROR; - 1134 .loc 1 306 0 - 1135 0004 0023 movs r3, #0 - 1136 0006 0193 str r3, [sp, #4] - 1137 .LVL112: - 313:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** StartUpCounter++; - 1138 .loc 1 313 0 - 1139 0008 3124 movs r4, #49 - 1140 .LVL113: - 1141 .L117: - 313:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** StartUpCounter++; - 1142 .loc 1 313 0 is_stmt 0 discriminator 2 - 1143 000a 2046 mov r0, r4 - 1144 000c FFF7FEFF bl RCC_GetFlagStatus - 1145 .LVL114: - 314:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - 1146 .loc 1 314 0 is_stmt 1 discriminator 2 - 1147 0010 019B ldr r3, [sp, #4] - 1148 0012 0133 adds r3, r3, #1 - 1149 0014 0193 str r3, [sp, #4] - 315:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 1150 .loc 1 315 0 discriminator 2 - 1151 0016 019B ldr r3, [sp, #4] - 1152 0018 B3F5A06F cmp r3, #1280 - 1153 001c 01D0 beq .L116 - 315:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 1154 .loc 1 315 0 is_stmt 0 discriminator 1 - 1155 001e 0028 cmp r0, #0 - 1156 0020 F3D0 beq .L117 - 1157 .L116: - 317:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 1158 .loc 1 317 0 is_stmt 1 - 1159 0022 3120 movs r0, #49 - 1160 .LVL115: - 1161 0024 FFF7FEFF bl RCC_GetFlagStatus - 1162 .LVL116: - 326:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** - 1163 .loc 1 326 0 - 1164 0028 0030 adds r0, r0, #0 - 1165 .LVL117: - 1166 002a 18BF it ne - 1167 002c 0120 movne r0, #1 - 1168 002e 02B0 add sp, sp, #8 - 1169 .cfi_def_cfa_offset 8 - 1170 @ sp needed - 1171 0030 10BD pop {r4, pc} - 1172 .cfi_endproc - 1173 .LFE31: - 1175 0032 00BF .section .text.RCC_ClearFlag,"ax",%progbits - 1176 .align 2 - 1177 .global RCC_ClearFlag - 1178 .thumb - 1179 .thumb_func - 1181 RCC_ClearFlag: - 1182 .LFB58: -1363:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1364:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** -1365:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Clears the RCC reset flags. -1366:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, -1367:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST -1368:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param None -1369:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None -1370:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ -1371:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_ClearFlag(void) -1372:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 1183 .loc 1 1372 0 - 1184 .cfi_startproc - 1185 @ args = 0, pretend = 0, frame = 0 - 1186 @ frame_needed = 0, uses_anonymous_args = 0 - 1187 @ link register save eliminated. -1373:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Set RMVF bit to clear the reset flags */ -1374:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** RCC->CSR |= CSR_RMVF_Set; - 1188 .loc 1 1374 0 - 1189 0000 024A ldr r2, .L121 - 1190 0002 536A ldr r3, [r2, #36] - 1191 0004 43F08073 orr r3, r3, #16777216 - 1192 0008 5362 str r3, [r2, #36] - 1193 000a 7047 bx lr - 1194 .L122: - 1195 .align 2 - 1196 .L121: - 1197 000c 00100240 .word 1073876992 - 1198 .cfi_endproc - 1199 .LFE58: - 1201 .section .text.RCC_GetITStatus,"ax",%progbits - 1202 .align 2 - 1203 .global RCC_GetITStatus - 1204 .thumb - 1205 .thumb_func - 1207 RCC_GetITStatus: - 1208 .LFB59: -1375:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1376:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1377:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** -1378:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Checks whether the specified RCC interrupt has occurred or not. -1379:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_IT: specifies the RCC interrupt source to check. -1380:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1381:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b STM32_Connectivity_line_devices, this parameter can be one of the -1382:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * following values: -1383:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_LSIRDY: LSI ready interrupt -1384:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_LSERDY: LSE ready interrupt -1385:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_HSIRDY: HSI ready interrupt -1386:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_HSERDY: HSE ready interrupt -1387:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_PLLRDY: PLL ready interrupt -1388:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt -1389:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt -1390:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_CSS: Clock Security System interrupt -1391:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1392:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b other_STM32_devices, this parameter can be one of the following values: -1393:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_LSIRDY: LSI ready interrupt -1394:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_LSERDY: LSE ready interrupt -1395:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_HSIRDY: HSI ready interrupt -1396:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_HSERDY: HSE ready interrupt -1397:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_PLLRDY: PLL ready interrupt -1398:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_CSS: Clock Security System interrupt -1399:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1400:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval The new state of RCC_IT (SET or RESET). -1401:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ -1402:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** ITStatus RCC_GetITStatus(uint8_t RCC_IT) -1403:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 1209 .loc 1 1403 0 - 1210 .cfi_startproc - 1211 @ args = 0, pretend = 0, frame = 0 - 1212 @ frame_needed = 0, uses_anonymous_args = 0 - 1213 @ link register save eliminated. - 1214 .LVL118: -1404:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** ITStatus bitstatus = RESET; -1405:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ -1406:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_GET_IT(RCC_IT)); -1407:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1408:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the status of the specified RCC interrupt */ -1409:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - 1215 .loc 1 1409 0 - 1216 0000 034B ldr r3, .L124 - 1217 0002 9B68 ldr r3, [r3, #8] - 1218 .LVL119: - 1219 0004 1842 tst r0, r3 -1410:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1411:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** bitstatus = SET; -1412:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1413:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** else -1414:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { -1415:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** bitstatus = RESET; -1416:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } -1417:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1418:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Return the RCC_IT status */ -1419:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** return bitstatus; -1420:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** } - 1220 .loc 1 1420 0 - 1221 0006 14BF ite ne - 1222 0008 0120 movne r0, #1 - 1223 .LVL120: - 1224 000a 0020 moveq r0, #0 - 1225 000c 7047 bx lr - 1226 .L125: - 1227 000e 00BF .align 2 - 1228 .L124: - 1229 0010 00100240 .word 1073876992 - 1230 .cfi_endproc - 1231 .LFE59: - 1233 .section .text.RCC_ClearITPendingBit,"ax",%progbits - 1234 .align 2 - 1235 .global RCC_ClearITPendingBit - 1236 .thumb - 1237 .thumb_func - 1239 RCC_ClearITPendingBit: - 1240 .LFB60: -1421:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1422:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /** -1423:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @brief Clears the RCC's interrupt pending bits. -1424:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @param RCC_IT: specifies the interrupt pending bit to clear. -1425:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1426:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b STM32_Connectivity_line_devices, this parameter can be any combination -1427:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * of the following values: -1428:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_LSIRDY: LSI ready interrupt -1429:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_LSERDY: LSE ready interrupt -1430:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_HSIRDY: HSI ready interrupt -1431:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_HSERDY: HSE ready interrupt -1432:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_PLLRDY: PLL ready interrupt -1433:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt -1434:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt -1435:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_CSS: Clock Security System interrupt -1436:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1437:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * For @b other_STM32_devices, this parameter can be any combination of the -1438:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * following values: -1439:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_LSIRDY: LSI ready interrupt -1440:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_LSERDY: LSE ready interrupt -1441:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_HSIRDY: HSI ready interrupt -1442:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_HSERDY: HSE ready interrupt -1443:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_PLLRDY: PLL ready interrupt -1444:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * -1445:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @arg RCC_IT_CSS: Clock Security System interrupt -1446:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** * @retval None -1447:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** */ -1448:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** void RCC_ClearITPendingBit(uint8_t RCC_IT) -1449:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** { - 1241 .loc 1 1449 0 - 1242 .cfi_startproc - 1243 @ args = 0, pretend = 0, frame = 0 - 1244 @ frame_needed = 0, uses_anonymous_args = 0 - 1245 @ link register save eliminated. - 1246 .LVL121: -1450:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Check the parameters */ -1451:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** assert_param(IS_RCC_CLEAR_IT(RCC_IT)); -1452:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** -1453:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt -1454:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** pending bits */ -1455:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c **** *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; - 1247 .loc 1 1455 0 - 1248 0000 014B ldr r3, .L127 - 1249 0002 1870 strb r0, [r3] - 1250 0004 7047 bx lr - 1251 .L128: - 1252 0006 00BF .align 2 - 1253 .L127: - 1254 0008 0A100240 .word 1073877002 - 1255 .cfi_endproc - 1256 .LFE60: - 1258 .section .data.ADCPrescTable,"aw",%progbits - 1259 .align 2 - 1260 .set .LANCHOR1,. + 0 - 1263 ADCPrescTable: - 1264 0000 02 .byte 2 - 1265 0001 04 .byte 4 - 1266 0002 06 .byte 6 - 1267 0003 08 .byte 8 - 1268 .section .data.APBAHBPrescTable,"aw",%progbits - 1269 .align 2 - 1270 .set .LANCHOR0,. + 0 - 1273 APBAHBPrescTable: - 1274 0000 00 .byte 0 - 1275 0001 00 .byte 0 - 1276 0002 00 .byte 0 - 1277 0003 00 .byte 0 - 1278 0004 01 .byte 1 - 1279 0005 02 .byte 2 - 1280 0006 03 .byte 3 - 1281 0007 04 .byte 4 - 1282 0008 01 .byte 1 - 1283 0009 02 .byte 2 - 1284 000a 03 .byte 3 - 1285 000b 04 .byte 4 - 1286 000c 06 .byte 6 - 1287 000d 07 .byte 7 - 1288 000e 08 .byte 8 - 1289 000f 09 .byte 9 - 1290 .text - 1291 .Letext0: - 1292 .file 2 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\mach - 1293 .file 3 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\stdi - 1294 .file 4 "./lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h" - 1295 .file 5 "./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h" - 1296 .file 6 "./lib/CMSIS/CM3/CoreSupport/core_cm3.h" -DEFINED SYMBOLS - *ABS*:00000000 stm32f10x_rcc.c -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:19 .text.RCC_DeInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:24 .text.RCC_DeInit:00000000 RCC_DeInit -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:62 .text.RCC_DeInit:00000038 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:68 .text.RCC_HSEConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:73 .text.RCC_HSEConfig:00000000 RCC_HSEConfig -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:114 .text.RCC_HSEConfig:00000038 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:119 .text.RCC_AdjustHSICalibrationValue:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:124 .text.RCC_AdjustHSICalibrationValue:00000000 RCC_AdjustHSICalibrationValue -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:148 .text.RCC_AdjustHSICalibrationValue:00000010 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:153 .text.RCC_HSICmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:158 .text.RCC_HSICmd:00000000 RCC_HSICmd -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:173 .text.RCC_HSICmd:00000008 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:178 .text.RCC_PLLConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:183 .text.RCC_PLLConfig:00000000 RCC_PLLConfig -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:209 .text.RCC_PLLConfig:00000010 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:214 .text.RCC_PLLCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:219 .text.RCC_PLLCmd:00000000 RCC_PLLCmd -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:234 .text.RCC_PLLCmd:00000008 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:239 .text.RCC_SYSCLKConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:244 .text.RCC_SYSCLKConfig:00000000 RCC_SYSCLKConfig -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:268 .text.RCC_SYSCLKConfig:00000010 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:273 .text.RCC_GetSYSCLKSource:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:278 .text.RCC_GetSYSCLKSource:00000000 RCC_GetSYSCLKSource -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:294 .text.RCC_GetSYSCLKSource:0000000c $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:299 .text.RCC_HCLKConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:304 .text.RCC_HCLKConfig:00000000 RCC_HCLKConfig -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:328 .text.RCC_HCLKConfig:00000010 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:333 .text.RCC_PCLK1Config:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:338 .text.RCC_PCLK1Config:00000000 RCC_PCLK1Config -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:362 .text.RCC_PCLK1Config:00000010 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:367 .text.RCC_PCLK2Config:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:372 .text.RCC_PCLK2Config:00000000 RCC_PCLK2Config -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:396 .text.RCC_PCLK2Config:00000010 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:401 .text.RCC_ITConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:406 .text.RCC_ITConfig:00000000 RCC_ITConfig -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:435 .text.RCC_ITConfig:00000018 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:440 .text.RCC_USBCLKConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:445 .text.RCC_USBCLKConfig:00000000 RCC_USBCLKConfig -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:460 .text.RCC_USBCLKConfig:00000008 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:465 .text.RCC_ADCCLKConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:470 .text.RCC_ADCCLKConfig:00000000 RCC_ADCCLKConfig -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:494 .text.RCC_ADCCLKConfig:00000010 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:499 .text.RCC_LSEConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:504 .text.RCC_LSEConfig:00000000 RCC_LSEConfig -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:540 .text.RCC_LSEConfig:00000024 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:545 .text.RCC_LSICmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:550 .text.RCC_LSICmd:00000000 RCC_LSICmd -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:565 .text.RCC_LSICmd:00000008 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:570 .text.RCC_RTCCLKConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:575 .text.RCC_RTCCLKConfig:00000000 RCC_RTCCLKConfig -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:593 .text.RCC_RTCCLKConfig:0000000c $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:598 .text.RCC_RTCCLKCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:603 .text.RCC_RTCCLKCmd:00000000 RCC_RTCCLKCmd -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:618 .text.RCC_RTCCLKCmd:00000008 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:623 .text.RCC_GetClocksFreq:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:628 .text.RCC_GetClocksFreq:00000000 RCC_GetClocksFreq -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:784 .text.RCC_GetClocksFreq:000000a0 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:793 .text.RCC_AHBPeriphClockCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:798 .text.RCC_AHBPeriphClockCmd:00000000 RCC_AHBPeriphClockCmd -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:827 .text.RCC_AHBPeriphClockCmd:00000018 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:832 .text.RCC_APB2PeriphClockCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:837 .text.RCC_APB2PeriphClockCmd:00000000 RCC_APB2PeriphClockCmd -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:866 .text.RCC_APB2PeriphClockCmd:00000018 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:871 .text.RCC_APB1PeriphClockCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:876 .text.RCC_APB1PeriphClockCmd:00000000 RCC_APB1PeriphClockCmd -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:905 .text.RCC_APB1PeriphClockCmd:00000018 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:910 .text.RCC_APB2PeriphResetCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:915 .text.RCC_APB2PeriphResetCmd:00000000 RCC_APB2PeriphResetCmd -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:944 .text.RCC_APB2PeriphResetCmd:00000018 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:949 .text.RCC_APB1PeriphResetCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:954 .text.RCC_APB1PeriphResetCmd:00000000 RCC_APB1PeriphResetCmd -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:983 .text.RCC_APB1PeriphResetCmd:00000018 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:988 .text.RCC_BackupResetCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:993 .text.RCC_BackupResetCmd:00000000 RCC_BackupResetCmd -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1008 .text.RCC_BackupResetCmd:00000008 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1013 .text.RCC_ClockSecuritySystemCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1018 .text.RCC_ClockSecuritySystemCmd:00000000 RCC_ClockSecuritySystemCmd -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1033 .text.RCC_ClockSecuritySystemCmd:00000008 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1038 .text.RCC_MCOConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1043 .text.RCC_MCOConfig:00000000 RCC_MCOConfig -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1058 .text.RCC_MCOConfig:00000008 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1063 .text.RCC_GetFlagStatus:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1068 .text.RCC_GetFlagStatus:00000000 RCC_GetFlagStatus -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1112 .text.RCC_GetFlagStatus:00000024 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1117 .text.RCC_WaitForHSEStartUp:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1122 .text.RCC_WaitForHSEStartUp:00000000 RCC_WaitForHSEStartUp -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1176 .text.RCC_ClearFlag:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1181 .text.RCC_ClearFlag:00000000 RCC_ClearFlag -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1197 .text.RCC_ClearFlag:0000000c $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1202 .text.RCC_GetITStatus:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1207 .text.RCC_GetITStatus:00000000 RCC_GetITStatus -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1229 .text.RCC_GetITStatus:00000010 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1234 .text.RCC_ClearITPendingBit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1239 .text.RCC_ClearITPendingBit:00000000 RCC_ClearITPendingBit -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1254 .text.RCC_ClearITPendingBit:00000008 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1259 .data.ADCPrescTable:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1263 .data.ADCPrescTable:00000000 ADCPrescTable -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1269 .data.APBAHBPrescTable:00000000 $d -C:\Users\lwngim1\AppData\Local\Temp\cckU7y8M.s:1273 .data.APBAHBPrescTable:00000000 APBAHBPrescTable - .debug_frame:00000010 $d - -NO UNDEFINED SYMBOLS diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/stm32f10x_spi.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/stm32f10x_spi.lst deleted file mode 100644 index f1e3df3a..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/stm32f10x_spi.lst +++ /dev/null @@ -1,1862 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "stm32f10x_spi.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.SPI_I2S_DeInit,"ax",%progbits - 19 .align 2 - 20 .global SPI_I2S_DeInit - 21 .thumb - 22 .thumb_func - 24 SPI_I2S_DeInit: - 25 .LFB29: - 26 .file 1 "./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c" - 1:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 2:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** ****************************************************************************** - 3:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @file stm32f10x_spi.c - 4:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @author MCD Application Team - 5:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @version V3.5.0 - 6:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @date 11-March-2011 - 7:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief This file provides all the SPI firmware functions. - 8:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** ****************************************************************************** - 9:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @attention - 10:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 11:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - 12:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - 13:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - 14:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - 15:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - 16:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - 17:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 18:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** *

© COPYRIGHT 2011 STMicroelectronics

- 19:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** ****************************************************************************** - 20:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 21:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 22:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Includes ------------------------------------------------------------------*/ - 23:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #include "stm32f10x_spi.h" - 24:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #include "stm32f10x_rcc.h" - 25:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 26:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** @addtogroup STM32F10x_StdPeriph_Driver - 27:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @{ - 28:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 29:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 30:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** @defgroup SPI - 31:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief SPI driver modules - 32:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @{ - 33:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 34:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 35:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** @defgroup SPI_Private_TypesDefinitions - 36:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @{ - 37:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 38:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 39:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 40:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @} - 41:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 42:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 43:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 44:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** @defgroup SPI_Private_Defines - 45:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @{ - 46:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 47:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 48:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* SPI SPE mask */ - 49:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define CR1_SPE_Set ((uint16_t)0x0040) - 50:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define CR1_SPE_Reset ((uint16_t)0xFFBF) - 51:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 52:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* I2S I2SE mask */ - 53:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define I2SCFGR_I2SE_Set ((uint16_t)0x0400) - 54:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) - 55:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 56:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* SPI CRCNext mask */ - 57:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define CR1_CRCNext_Set ((uint16_t)0x1000) - 58:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 59:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* SPI CRCEN mask */ - 60:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define CR1_CRCEN_Set ((uint16_t)0x2000) - 61:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define CR1_CRCEN_Reset ((uint16_t)0xDFFF) - 62:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 63:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* SPI SSOE mask */ - 64:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define CR2_SSOE_Set ((uint16_t)0x0004) - 65:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define CR2_SSOE_Reset ((uint16_t)0xFFFB) - 66:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 67:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* SPI registers Masks */ - 68:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define CR1_CLEAR_Mask ((uint16_t)0x3040) - 69:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) - 70:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 71:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* SPI or I2S mode selection masks */ - 72:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define SPI_Mode_Select ((uint16_t)0xF7FF) - 73:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define I2S_Mode_Select ((uint16_t)0x0800) - 74:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 75:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* I2S clock source selection masks */ - 76:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) - 77:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) - 78:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define I2S_MUL_MASK ((uint32_t)(0x0000F000)) - 79:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #define I2S_DIV_MASK ((uint32_t)(0x000000F0)) - 80:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 81:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 82:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @} - 83:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 84:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 85:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** @defgroup SPI_Private_Macros - 86:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @{ - 87:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 88:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 89:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 90:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @} - 91:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 92:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 93:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** @defgroup SPI_Private_Variables - 94:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @{ - 95:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 96:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 97:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 98:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @} - 99:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 100:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 101:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** @defgroup SPI_Private_FunctionPrototypes - 102:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @{ - 103:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 104:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 105:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 106:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @} - 107:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 108:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 109:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** @defgroup SPI_Private_Functions - 110:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @{ - 111:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 112:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 113:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 114:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Deinitializes the SPIx peripheral registers to their default - 115:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * reset values (Affects also the I2Ss). - 116:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - 117:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 118:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 119:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_I2S_DeInit(SPI_TypeDef* SPIx) - 120:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 27 .loc 1 120 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 .LVL0: - 32 0000 08B5 push {r3, lr} - 33 .cfi_def_cfa_offset 8 - 34 .cfi_offset 3, -8 - 35 .cfi_offset 14, -4 - 121:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 122:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 123:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 124:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if (SPIx == SPI1) - 36 .loc 1 124 0 - 37 0002 154B ldr r3, .L6 - 38 0004 9842 cmp r0, r3 - 39 0006 0AD1 bne .L2 - 125:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 126:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Enable SPI1 reset state */ - 127:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - 40 .loc 1 127 0 - 41 0008 4FF48050 mov r0, #4096 - 42 .LVL1: - 43 000c 0121 movs r1, #1 - 44 000e FFF7FEFF bl RCC_APB2PeriphResetCmd - 45 .LVL2: - 128:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Release SPI1 from reset state */ - 129:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - 46 .loc 1 129 0 - 47 0012 4FF48050 mov r0, #4096 - 48 0016 0021 movs r1, #0 - 49 0018 FFF7FEFF bl RCC_APB2PeriphResetCmd - 50 .LVL3: - 51 001c 08BD pop {r3, pc} - 52 .LVL4: - 53 .L2: - 130:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 131:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else if (SPIx == SPI2) - 54 .loc 1 131 0 - 55 001e 0F4B ldr r3, .L6+4 - 56 0020 9842 cmp r0, r3 - 57 0022 0AD1 bne .L4 - 132:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 133:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Enable SPI2 reset state */ - 134:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - 58 .loc 1 134 0 - 59 0024 4FF48040 mov r0, #16384 - 60 .LVL5: - 61 0028 0121 movs r1, #1 - 62 002a FFF7FEFF bl RCC_APB1PeriphResetCmd - 63 .LVL6: - 135:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Release SPI2 from reset state */ - 136:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - 64 .loc 1 136 0 - 65 002e 4FF48040 mov r0, #16384 - 66 0032 0021 movs r1, #0 - 67 0034 FFF7FEFF bl RCC_APB1PeriphResetCmd - 68 .LVL7: - 69 0038 08BD pop {r3, pc} - 70 .LVL8: - 71 .L4: - 137:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 138:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 139:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 140:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if (SPIx == SPI3) - 72 .loc 1 140 0 - 73 003a 094B ldr r3, .L6+8 - 74 003c 9842 cmp r0, r3 - 75 003e 09D1 bne .L1 - 141:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 142:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Enable SPI3 reset state */ - 143:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - 76 .loc 1 143 0 - 77 0040 4FF40040 mov r0, #32768 - 78 .LVL9: - 79 0044 0121 movs r1, #1 - 80 0046 FFF7FEFF bl RCC_APB1PeriphResetCmd - 81 .LVL10: - 144:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Release SPI3 from reset state */ - 145:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - 82 .loc 1 145 0 - 83 004a 4FF40040 mov r0, #32768 - 84 004e 0021 movs r1, #0 - 85 0050 FFF7FEFF bl RCC_APB1PeriphResetCmd - 86 .LVL11: - 87 .L1: - 88 0054 08BD pop {r3, pc} - 89 .L7: - 90 0056 00BF .align 2 - 91 .L6: - 92 0058 00300140 .word 1073819648 - 93 005c 00380040 .word 1073756160 - 94 0060 003C0040 .word 1073757184 - 95 .cfi_endproc - 96 .LFE29: - 98 .section .text.SPI_Init,"ax",%progbits - 99 .align 2 - 100 .global SPI_Init - 101 .thumb - 102 .thumb_func - 104 SPI_Init: - 105 .LFB30: - 146:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 147:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 148:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 149:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 150:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 151:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Initializes the SPIx peripheral according to the specified - 152:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * parameters in the SPI_InitStruct. - 153:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - 154:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - 155:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * contains the configuration information for the specified SPI peripheral. - 156:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 157:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 158:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) - 159:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 106 .loc 1 159 0 - 107 .cfi_startproc - 108 @ args = 0, pretend = 0, frame = 0 - 109 @ frame_needed = 0, uses_anonymous_args = 0 - 110 @ link register save eliminated. - 111 .LVL12: - 112 0000 10B4 push {r4} - 113 .cfi_def_cfa_offset 4 - 114 .cfi_offset 4, -4 - 115 .LVL13: - 160:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** uint16_t tmpreg = 0; - 161:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 162:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* check the parameters */ - 163:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 164:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 165:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the SPI parameters */ - 166:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - 167:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - 168:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - 169:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - 170:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - 171:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - 172:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - 173:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - 174:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - 175:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 176:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /*---------------------------- SPIx CR1 Configuration ------------------------*/ - 177:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the SPIx CR1 value */ - 178:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** tmpreg = SPIx->CR1; - 116 .loc 1 178 0 - 117 0002 0388 ldrh r3, [r0] - 118 .LVL14: - 179:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - 180:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** tmpreg &= CR1_CLEAR_Mask; - 119 .loc 1 180 0 - 120 0004 03F44154 and r4, r3, #12352 - 121 .LVL15: - 181:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - 182:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** master/salve mode, CPOL and CPHA */ - 183:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - 184:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - 185:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Set LSBFirst bit according to SPI_FirstBit value */ - 186:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Set BR bits according to SPI_BaudRatePrescaler value */ - 187:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Set CPOL bit according to SPI_CPOL value */ - 188:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Set CPHA bit according to SPI_CPHA value */ - 189:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - 122 .loc 1 189 0 - 123 0008 4A88 ldrh r2, [r1, #2] - 124 000a 0B88 ldrh r3, [r1] - 125 000c 1343 orrs r3, r3, r2 - 126 000e 8A88 ldrh r2, [r1, #4] - 127 0010 1343 orrs r3, r3, r2 - 128 0012 CA88 ldrh r2, [r1, #6] - 129 0014 1343 orrs r3, r3, r2 - 130 0016 0A89 ldrh r2, [r1, #8] - 131 0018 1343 orrs r3, r3, r2 - 132 001a 4A89 ldrh r2, [r1, #10] - 133 001c 1343 orrs r3, r3, r2 - 134 001e 8A89 ldrh r2, [r1, #12] - 135 0020 1343 orrs r3, r3, r2 - 136 0022 CA89 ldrh r2, [r1, #14] - 137 0024 1343 orrs r3, r3, r2 - 138 0026 2343 orrs r3, r3, r4 - 139 0028 9BB2 uxth r3, r3 - 140 .LVL16: - 190:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - 191:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - 192:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - 193:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Write to SPIx CR1 */ - 194:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR1 = tmpreg; - 141 .loc 1 194 0 - 142 002a 0380 strh r3, [r0] @ movhi - 195:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 196:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - 197:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->I2SCFGR &= SPI_Mode_Select; - 143 .loc 1 197 0 - 144 002c 838B ldrh r3, [r0, #28] - 145 .LVL17: - 146 002e 23F40063 bic r3, r3, #2048 - 147 0032 1B04 lsls r3, r3, #16 - 148 0034 1B0C lsrs r3, r3, #16 - 149 0036 8383 strh r3, [r0, #28] @ movhi - 150 .LVL18: - 198:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 199:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - 200:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Write to SPIx CRCPOLY */ - 201:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; - 151 .loc 1 201 0 - 152 0038 0B8A ldrh r3, [r1, #16] - 153 003a 0382 strh r3, [r0, #16] @ movhi - 202:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 154 .loc 1 202 0 - 155 003c 5DF8044B ldr r4, [sp], #4 - 156 .cfi_restore 4 - 157 .cfi_def_cfa_offset 0 - 158 0040 7047 bx lr - 159 .cfi_endproc - 160 .LFE30: - 162 0042 00BF .section .text.I2S_Init,"ax",%progbits - 163 .align 2 - 164 .global I2S_Init - 165 .thumb - 166 .thumb_func - 168 I2S_Init: - 169 .LFB31: - 203:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 204:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 205:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Initializes the SPIx peripheral according to the specified - 206:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * parameters in the I2S_InitStruct. - 207:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be 2 or 3 to select the SPI peripheral - 208:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * (configured in I2S mode). - 209:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - 210:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * contains the configuration information for the specified SPI peripheral - 211:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * configured in I2S mode. - 212:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @note - 213:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * The function calculates the optimal prescaler needed to obtain the most - 214:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * accurate audio frequency (depending on the I2S clock source, the PLL values - 215:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * and the product configuration). But in case the prescaler value is greater - 216:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * than 511, the default value (0x02) will be configured instead. * - 217:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 218:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 219:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) - 220:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 170 .loc 1 220 0 - 171 .cfi_startproc - 172 @ args = 0, pretend = 0, frame = 24 - 173 @ frame_needed = 0, uses_anonymous_args = 0 - 174 .LVL19: - 175 0000 F0B5 push {r4, r5, r6, r7, lr} - 176 .cfi_def_cfa_offset 20 - 177 .cfi_offset 4, -20 - 178 .cfi_offset 5, -16 - 179 .cfi_offset 6, -12 - 180 .cfi_offset 7, -8 - 181 .cfi_offset 14, -4 - 182 0002 87B0 sub sp, sp, #28 - 183 .cfi_def_cfa_offset 48 - 184 0004 0546 mov r5, r0 - 185 0006 0C46 mov r4, r1 - 186 .LVL20: - 221:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - 222:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** uint32_t tmp = 0; - 223:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** RCC_ClocksTypeDef RCC_Clocks; - 224:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** uint32_t sourceclock = 0; - 225:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 226:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the I2S parameters */ - 227:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_23_PERIPH(SPIx)); - 228:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - 229:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - 230:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - 231:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - 232:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - 233:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - 234:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 235:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - 236:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - 237:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; - 187 .loc 1 237 0 - 188 0008 838B ldrh r3, [r0, #28] - 189 000a 9BB2 uxth r3, r3 - 190 000c 23F47B63 bic r3, r3, #4016 - 191 0010 23F00F03 bic r3, r3, #15 - 192 0014 9BB2 uxth r3, r3 - 193 0016 8383 strh r3, [r0, #28] @ movhi - 238:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->I2SPR = 0x0002; - 194 .loc 1 238 0 - 195 0018 0223 movs r3, #2 - 196 001a 0384 strh r3, [r0, #32] @ movhi - 239:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 240:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the I2SCFGR register value */ - 241:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** tmpreg = SPIx->I2SCFGR; - 197 .loc 1 241 0 - 198 001c 868B ldrh r6, [r0, #28] - 199 001e B6B2 uxth r6, r6 - 200 .LVL21: - 242:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 243:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - 244:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - 201 .loc 1 244 0 - 202 0020 8B68 ldr r3, [r1, #8] - 203 0022 022B cmp r3, #2 - 204 0024 26D0 beq .L15 - 245:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 246:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** i2sodd = (uint16_t)0; - 247:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** i2sdiv = (uint16_t)2; - 248:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 249:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* If the requested audio frequency is not the default, compute the prescaler */ - 250:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 251:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 252:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the frame length (For the Prescaler computing) */ - 253:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - 205 .loc 1 253 0 - 206 0026 8B88 ldrh r3, [r1, #4] - 254:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 255:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Packet length is 16 bits */ - 256:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** packetlength = 1; - 257:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 258:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 259:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 260:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Packet length is 32 bits */ - 261:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** packetlength = 2; - 207 .loc 1 261 0 - 208 0028 002B cmp r3, #0 - 209 002a 0CBF ite eq - 210 002c 0127 moveq r7, #1 - 211 002e 0227 movne r7, #2 - 212 .LVL22: - 262:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 263:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 264:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the I2S clock source mask depending on the peripheral number */ - 265:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if(((uint32_t)SPIx) == SPI2_BASE) - 266:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 267:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* The mask is relative to I2S2 */ - 268:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** tmp = I2S2_CLOCK_SRC; - 269:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 270:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 271:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 272:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* The mask is relative to I2S3 */ - 273:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** tmp = I2S3_CLOCK_SRC; - 274:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 275:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 276:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the I2S clock source configuration depending on the Device: - 277:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** Only Connectivity line devices have the PLL3 VCO clock */ - 278:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #ifdef STM32F10X_CL - 279:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if((RCC->CFGR2 & tmp) != 0) - 280:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 281:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the configuration bits of RCC PLL3 multiplier */ - 282:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12); - 283:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 284:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the value of the PLL3 multiplier */ - 285:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if((tmp > 5) && (tmp < 15)) - 286:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 287:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Multiplier is between 8 and 14 (value 15 is forbidden) */ - 288:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** tmp += 2; - 289:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 290:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 291:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 292:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if (tmp == 15) - 293:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 294:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Multiplier is 20 */ - 295:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** tmp = 20; - 296:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 297:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 298:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the PREDIV2 value */ - 299:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); - 300:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 301:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */ - 302:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); - 303:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 304:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 305:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 306:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* I2S Clock source is System clock: Get System Clock frequency */ - 307:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** RCC_GetClocksFreq(&RCC_Clocks); - 308:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 309:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the source clock value: based on System Clock value */ - 310:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** sourceclock = RCC_Clocks.SYSCLK_Frequency; - 311:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 312:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #else /* STM32F10X_HD */ - 313:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* I2S Clock source is System clock: Get System Clock frequency */ - 314:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** RCC_GetClocksFreq(&RCC_Clocks); - 213 .loc 1 314 0 - 214 0030 01A8 add r0, sp, #4 - 215 .LVL23: - 216 0032 FFF7FEFF bl RCC_GetClocksFreq - 217 .LVL24: - 315:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 316:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the source clock value: based on System Clock value */ - 317:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** sourceclock = RCC_Clocks.SYSCLK_Frequency; - 218 .loc 1 317 0 - 219 0036 019A ldr r2, [sp, #4] - 220 .LVL25: - 318:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** #endif /* STM32F10X_CL */ - 319:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 320:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Compute the Real divider depending on the MCLK output state with a floating point */ - 321:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - 221 .loc 1 321 0 - 222 0038 E388 ldrh r3, [r4, #6] - 223 003a B3F5007F cmp r3, #512 - 322:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 323:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* MCLK output is enabled */ - 324:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - 224 .loc 1 324 0 - 225 003e 0EBF itee eq - 226 0040 130A lsreq r3, r2, #8 - 325:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 326:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 327:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 328:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* MCLK output is disabled */ - 329:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq - 227 .loc 1 329 0 - 228 0042 7B01 lslne r3, r7, #5 - 229 0044 B2FBF3F3 udivne r3, r2, r3 - 230 0048 03EB8303 add r3, r3, r3, lsl #2 - 231 004c 5B00 lsls r3, r3, #1 - 232 004e A268 ldr r2, [r4, #8] - 233 .LVL26: - 234 0050 B3FBF2F3 udiv r3, r3, r2 - 235 0054 0533 adds r3, r3, #5 - 236 0056 9BB2 uxth r3, r3 - 237 .LVL27: - 330:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 331:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 332:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Remove the floating point */ - 333:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** tmp = tmp / 10; - 238 .loc 1 333 0 - 239 0058 124A ldr r2, .L19 - 240 005a A2FB0323 umull r2, r3, r2, r3 - 241 .LVL28: - 242 005e DB08 lsrs r3, r3, #3 - 243 .LVL29: - 334:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 335:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parity of the divider */ - 336:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - 337:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 338:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Compute the i2sdiv prescaler */ - 339:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - 244 .loc 1 339 0 - 245 0060 03F00102 and r2, r3, #1 - 246 0064 5B08 lsrs r3, r3, #1 - 247 .LVL30: - 340:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 341:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - 342:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** i2sodd = (uint16_t) (i2sodd << 8); - 343:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 344:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 345:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Test if the divider is 1 or 0 or greater than 0xFF */ - 346:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - 248 .loc 1 346 0 - 249 0066 991E subs r1, r3, #2 - 250 0068 89B2 uxth r1, r1 - 251 006a FD29 cmp r1, #253 - 252 .LVL31: - 253 006c 05D8 bhi .L17 - 342:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 254 .loc 1 342 0 - 255 006e 1202 lsls r2, r2, #8 - 256 .LVL32: - 257 0070 92B2 uxth r2, r2 - 258 0072 04E0 b .L11 - 259 .LVL33: - 260 .L15: - 246:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** i2sdiv = (uint16_t)2; - 261 .loc 1 246 0 - 262 0074 0022 movs r2, #0 - 247:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 263 .loc 1 247 0 - 264 0076 0223 movs r3, #2 - 265 0078 01E0 b .L11 - 266 .LVL34: - 267 .L17: - 347:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 348:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Set the default values */ - 349:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** i2sdiv = 2; - 350:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** i2sodd = 0; - 268 .loc 1 350 0 - 269 007a 0022 movs r2, #0 - 270 .LVL35: - 349:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** i2sodd = 0; - 271 .loc 1 349 0 - 272 007c 0223 movs r3, #2 - 273 .LVL36: - 274 .L11: - 275 007e 1343 orrs r3, r3, r2 - 276 .LVL37: - 351:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 352:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 353:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Write to SPIx I2SPR register the computed value */ - 354:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - 277 .loc 1 354 0 - 278 0080 E288 ldrh r2, [r4, #6] - 279 .LVL38: - 280 0082 1343 orrs r3, r3, r2 - 281 0084 2B84 strh r3, [r5, #32] @ movhi - 282 0086 2388 ldrh r3, [r4] - 283 0088 1E43 orrs r6, r6, r3 - 284 .LVL39: - 285 008a 46F40066 orr r6, r6, #2048 - 286 008e 6388 ldrh r3, [r4, #2] - 287 0090 3343 orrs r3, r3, r6 - 288 0092 A288 ldrh r2, [r4, #4] - 289 0094 1343 orrs r3, r3, r2 - 355:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 356:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Configure the I2S with the SPI_InitStruct values */ - 357:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - 290 .loc 1 357 0 - 291 0096 A289 ldrh r2, [r4, #12] - 292 0098 1343 orrs r3, r3, r2 - 293 009a 9BB2 uxth r3, r3 - 294 .LVL40: - 358:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataForm - 359:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** (uint16_t)I2S_InitStruct->I2S_CPOL)))); - 360:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 361:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Write to SPIx I2SCFGR */ - 362:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->I2SCFGR = tmpreg; - 295 .loc 1 362 0 - 296 009c AB83 strh r3, [r5, #28] @ movhi - 363:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 297 .loc 1 363 0 - 298 009e 07B0 add sp, sp, #28 - 299 .cfi_def_cfa_offset 20 - 300 @ sp needed - 301 00a0 F0BD pop {r4, r5, r6, r7, pc} - 302 .LVL41: - 303 .L20: - 304 00a2 00BF .align 2 - 305 .L19: - 306 00a4 CDCCCCCC .word -858993459 - 307 .cfi_endproc - 308 .LFE31: - 310 .section .text.SPI_StructInit,"ax",%progbits - 311 .align 2 - 312 .global SPI_StructInit - 313 .thumb - 314 .thumb_func - 316 SPI_StructInit: - 317 .LFB32: - 364:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 365:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 366:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Fills each SPI_InitStruct member with its default value. - 367:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. - 368:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 369:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 370:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) - 371:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 318 .loc 1 371 0 - 319 .cfi_startproc - 320 @ args = 0, pretend = 0, frame = 0 - 321 @ frame_needed = 0, uses_anonymous_args = 0 - 322 @ link register save eliminated. - 323 .LVL42: - 372:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /*--------------- Reset SPI init structure parameters values -----------------*/ - 373:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Initialize the SPI_Direction member */ - 374:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - 324 .loc 1 374 0 - 325 0000 0023 movs r3, #0 - 326 0002 0380 strh r3, [r0] @ movhi - 375:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* initialize the SPI_Mode member */ - 376:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - 327 .loc 1 376 0 - 328 0004 4380 strh r3, [r0, #2] @ movhi - 377:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* initialize the SPI_DataSize member */ - 378:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - 329 .loc 1 378 0 - 330 0006 8380 strh r3, [r0, #4] @ movhi - 379:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Initialize the SPI_CPOL member */ - 380:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - 331 .loc 1 380 0 - 332 0008 C380 strh r3, [r0, #6] @ movhi - 381:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Initialize the SPI_CPHA member */ - 382:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - 333 .loc 1 382 0 - 334 000a 0381 strh r3, [r0, #8] @ movhi - 383:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Initialize the SPI_NSS member */ - 384:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - 335 .loc 1 384 0 - 336 000c 4381 strh r3, [r0, #10] @ movhi - 385:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Initialize the SPI_BaudRatePrescaler member */ - 386:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - 337 .loc 1 386 0 - 338 000e 8381 strh r3, [r0, #12] @ movhi - 387:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Initialize the SPI_FirstBit member */ - 388:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - 339 .loc 1 388 0 - 340 0010 C381 strh r3, [r0, #14] @ movhi - 389:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Initialize the SPI_CRCPolynomial member */ - 390:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPI_InitStruct->SPI_CRCPolynomial = 7; - 341 .loc 1 390 0 - 342 0012 0723 movs r3, #7 - 343 0014 0382 strh r3, [r0, #16] @ movhi - 344 0016 7047 bx lr - 345 .cfi_endproc - 346 .LFE32: - 348 .section .text.I2S_StructInit,"ax",%progbits - 349 .align 2 - 350 .global I2S_StructInit - 351 .thumb - 352 .thumb_func - 354 I2S_StructInit: - 355 .LFB33: - 391:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 392:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 393:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 394:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Fills each I2S_InitStruct member with its default value. - 395:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. - 396:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 397:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 398:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) - 399:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 356 .loc 1 399 0 - 357 .cfi_startproc - 358 @ args = 0, pretend = 0, frame = 0 - 359 @ frame_needed = 0, uses_anonymous_args = 0 - 360 @ link register save eliminated. - 361 .LVL43: - 400:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /*--------------- Reset I2S init structure parameters values -----------------*/ - 401:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Initialize the I2S_Mode member */ - 402:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - 362 .loc 1 402 0 - 363 0000 0023 movs r3, #0 - 364 0002 0380 strh r3, [r0] @ movhi - 403:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 404:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Initialize the I2S_Standard member */ - 405:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - 365 .loc 1 405 0 - 366 0004 4380 strh r3, [r0, #2] @ movhi - 406:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 407:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Initialize the I2S_DataFormat member */ - 408:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - 367 .loc 1 408 0 - 368 0006 8380 strh r3, [r0, #4] @ movhi - 409:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 410:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Initialize the I2S_MCLKOutput member */ - 411:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - 369 .loc 1 411 0 - 370 0008 C380 strh r3, [r0, #6] @ movhi - 412:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 413:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Initialize the I2S_AudioFreq member */ - 414:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - 371 .loc 1 414 0 - 372 000a 0222 movs r2, #2 - 373 000c 8260 str r2, [r0, #8] - 415:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 416:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Initialize the I2S_CPOL member */ - 417:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; - 374 .loc 1 417 0 - 375 000e 8381 strh r3, [r0, #12] @ movhi - 376 0010 7047 bx lr - 377 .cfi_endproc - 378 .LFE33: - 380 0012 00BF .section .text.SPI_Cmd,"ax",%progbits - 381 .align 2 - 382 .global SPI_Cmd - 383 .thumb - 384 .thumb_func - 386 SPI_Cmd: - 387 .LFB34: - 418:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 419:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 420:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 421:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Enables or disables the specified SPI peripheral. - 422:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - 423:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param NewState: new state of the SPIx peripheral. - 424:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be: ENABLE or DISABLE. - 425:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 426:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 427:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) - 428:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 388 .loc 1 428 0 - 389 .cfi_startproc - 390 @ args = 0, pretend = 0, frame = 0 - 391 @ frame_needed = 0, uses_anonymous_args = 0 - 392 @ link register save eliminated. - 393 .LVL44: - 429:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 430:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 431:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 432:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if (NewState != DISABLE) - 394 .loc 1 432 0 - 395 0000 29B1 cbz r1, .L24 - 433:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 434:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Enable the selected SPI peripheral */ - 435:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR1 |= CR1_SPE_Set; - 396 .loc 1 435 0 - 397 0002 0388 ldrh r3, [r0] - 398 0004 9BB2 uxth r3, r3 - 399 0006 43F04003 orr r3, r3, #64 - 400 000a 0380 strh r3, [r0] @ movhi - 401 000c 7047 bx lr - 402 .L24: - 436:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 437:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 438:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 439:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Disable the selected SPI peripheral */ - 440:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR1 &= CR1_SPE_Reset; - 403 .loc 1 440 0 - 404 000e 0388 ldrh r3, [r0] - 405 0010 23F04003 bic r3, r3, #64 - 406 0014 1B04 lsls r3, r3, #16 - 407 0016 1B0C lsrs r3, r3, #16 - 408 0018 0380 strh r3, [r0] @ movhi - 409 001a 7047 bx lr - 410 .cfi_endproc - 411 .LFE34: - 413 .section .text.I2S_Cmd,"ax",%progbits - 414 .align 2 - 415 .global I2S_Cmd - 416 .thumb - 417 .thumb_func - 419 I2S_Cmd: - 420 .LFB35: - 441:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 442:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 443:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 444:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 445:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Enables or disables the specified SPI peripheral (in I2S mode). - 446:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. - 447:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param NewState: new state of the SPIx peripheral. - 448:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be: ENABLE or DISABLE. - 449:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 450:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 451:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) - 452:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 421 .loc 1 452 0 - 422 .cfi_startproc - 423 @ args = 0, pretend = 0, frame = 0 - 424 @ frame_needed = 0, uses_anonymous_args = 0 - 425 @ link register save eliminated. - 426 .LVL45: - 453:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 454:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_23_PERIPH(SPIx)); - 455:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 456:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if (NewState != DISABLE) - 427 .loc 1 456 0 - 428 0000 29B1 cbz r1, .L27 - 457:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 458:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Enable the selected SPI peripheral (in I2S mode) */ - 459:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; - 429 .loc 1 459 0 - 430 0002 838B ldrh r3, [r0, #28] - 431 0004 9BB2 uxth r3, r3 - 432 0006 43F48063 orr r3, r3, #1024 - 433 000a 8383 strh r3, [r0, #28] @ movhi - 434 000c 7047 bx lr - 435 .L27: - 460:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 461:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 462:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 463:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Disable the selected SPI peripheral (in I2S mode) */ - 464:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; - 436 .loc 1 464 0 - 437 000e 838B ldrh r3, [r0, #28] - 438 0010 23F48063 bic r3, r3, #1024 - 439 0014 1B04 lsls r3, r3, #16 - 440 0016 1B0C lsrs r3, r3, #16 - 441 0018 8383 strh r3, [r0, #28] @ movhi - 442 001a 7047 bx lr - 443 .cfi_endproc - 444 .LFE35: - 446 .section .text.SPI_I2S_ITConfig,"ax",%progbits - 447 .align 2 - 448 .global SPI_I2S_ITConfig - 449 .thumb - 450 .thumb_func - 452 SPI_I2S_ITConfig: - 453 .LFB36: - 465:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 466:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 467:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 468:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 469:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Enables or disables the specified SPI/I2S interrupts. - 470:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be - 471:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 1, 2 or 3 in SPI mode - 472:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 2 or 3 in I2S mode - 473:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. - 474:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be one of the following values: - 475:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - 476:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - 477:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_I2S_IT_ERR: Error interrupt mask - 478:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param NewState: new state of the specified SPI/I2S interrupt. - 479:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be: ENABLE or DISABLE. - 480:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 481:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 482:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) - 483:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 454 .loc 1 483 0 - 455 .cfi_startproc - 456 @ args = 0, pretend = 0, frame = 0 - 457 @ frame_needed = 0, uses_anonymous_args = 0 - 458 @ link register save eliminated. - 459 .LVL46: - 484:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** uint16_t itpos = 0, itmask = 0 ; - 485:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 486:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 487:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 488:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - 489:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 490:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the SPI/I2S IT index */ - 491:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** itpos = SPI_I2S_IT >> 4; - 492:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 493:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Set the IT mask */ - 494:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** itmask = (uint16_t)1 << (uint16_t)itpos; - 460 .loc 1 494 0 - 461 0000 0909 lsrs r1, r1, #4 - 462 .LVL47: - 463 0002 0123 movs r3, #1 - 464 0004 8B40 lsls r3, r3, r1 - 465 0006 9BB2 uxth r3, r3 - 466 .LVL48: - 495:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 496:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if (NewState != DISABLE) - 467 .loc 1 496 0 - 468 0008 22B1 cbz r2, .L30 - 497:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 498:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Enable the selected SPI/I2S interrupt */ - 499:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR2 |= itmask; - 469 .loc 1 499 0 - 470 000a 8288 ldrh r2, [r0, #4] - 471 .LVL49: - 472 000c 92B2 uxth r2, r2 - 473 000e 1343 orrs r3, r3, r2 - 474 .LVL50: - 475 0010 8380 strh r3, [r0, #4] @ movhi - 476 0012 7047 bx lr - 477 .LVL51: - 478 .L30: - 500:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 501:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 502:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 503:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Disable the selected SPI/I2S interrupt */ - 504:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR2 &= (uint16_t)~itmask; - 479 .loc 1 504 0 - 480 0014 8288 ldrh r2, [r0, #4] - 481 .LVL52: - 482 0016 92B2 uxth r2, r2 - 483 0018 22EA0303 bic r3, r2, r3 - 484 .LVL53: - 485 001c 8380 strh r3, [r0, #4] @ movhi - 486 001e 7047 bx lr - 487 .cfi_endproc - 488 .LFE36: - 490 .section .text.SPI_I2S_DMACmd,"ax",%progbits - 491 .align 2 - 492 .global SPI_I2S_DMACmd - 493 .thumb - 494 .thumb_func - 496 SPI_I2S_DMACmd: - 497 .LFB37: - 505:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 506:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 507:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 508:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 509:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Enables or disables the SPIx/I2Sx DMA interface. - 510:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be - 511:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 1, 2 or 3 in SPI mode - 512:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 2 or 3 in I2S mode - 513:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. - 514:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be any combination of the following values: - 515:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - 516:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - 517:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param NewState: new state of the selected SPI/I2S DMA transfer request. - 518:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be: ENABLE or DISABLE. - 519:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 520:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 521:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) - 522:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 498 .loc 1 522 0 - 499 .cfi_startproc - 500 @ args = 0, pretend = 0, frame = 0 - 501 @ frame_needed = 0, uses_anonymous_args = 0 - 502 @ link register save eliminated. - 503 .LVL54: - 523:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 524:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 525:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 526:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - 527:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if (NewState != DISABLE) - 504 .loc 1 527 0 - 505 0000 22B1 cbz r2, .L33 - 528:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 529:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Enable the selected SPI/I2S DMA requests */ - 530:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR2 |= SPI_I2S_DMAReq; - 506 .loc 1 530 0 - 507 0002 8388 ldrh r3, [r0, #4] - 508 0004 9BB2 uxth r3, r3 - 509 0006 1943 orrs r1, r1, r3 - 510 .LVL55: - 511 0008 8180 strh r1, [r0, #4] @ movhi - 512 000a 7047 bx lr - 513 .LVL56: - 514 .L33: - 531:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 532:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 533:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 534:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Disable the selected SPI/I2S DMA requests */ - 535:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - 515 .loc 1 535 0 - 516 000c 8388 ldrh r3, [r0, #4] - 517 000e 9BB2 uxth r3, r3 - 518 0010 23EA0101 bic r1, r3, r1 - 519 .LVL57: - 520 0014 8180 strh r1, [r0, #4] @ movhi - 521 0016 7047 bx lr - 522 .cfi_endproc - 523 .LFE37: - 525 .section .text.SPI_I2S_SendData,"ax",%progbits - 526 .align 2 - 527 .global SPI_I2S_SendData - 528 .thumb - 529 .thumb_func - 531 SPI_I2S_SendData: - 532 .LFB38: - 536:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 537:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 538:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 539:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 540:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Transmits a Data through the SPIx/I2Sx peripheral. - 541:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be - 542:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 1, 2 or 3 in SPI mode - 543:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 2 or 3 in I2S mode - 544:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param Data : Data to be transmitted. - 545:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 546:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 547:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) - 548:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 533 .loc 1 548 0 - 534 .cfi_startproc - 535 @ args = 0, pretend = 0, frame = 0 - 536 @ frame_needed = 0, uses_anonymous_args = 0 - 537 @ link register save eliminated. - 538 .LVL58: - 549:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 550:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 551:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 552:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Write in the DR register the data to be sent */ - 553:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->DR = Data; - 539 .loc 1 553 0 - 540 0000 8181 strh r1, [r0, #12] @ movhi - 541 0002 7047 bx lr - 542 .cfi_endproc - 543 .LFE38: - 545 .section .text.SPI_I2S_ReceiveData,"ax",%progbits - 546 .align 2 - 547 .global SPI_I2S_ReceiveData - 548 .thumb - 549 .thumb_func - 551 SPI_I2S_ReceiveData: - 552 .LFB39: - 554:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 555:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 556:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 557:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - 558:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be - 559:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 1, 2 or 3 in SPI mode - 560:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 2 or 3 in I2S mode - 561:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval The value of the received data. - 562:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 563:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) - 564:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 553 .loc 1 564 0 - 554 .cfi_startproc - 555 @ args = 0, pretend = 0, frame = 0 - 556 @ frame_needed = 0, uses_anonymous_args = 0 - 557 @ link register save eliminated. - 558 .LVL59: - 565:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 566:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 567:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 568:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Return the data in the DR register */ - 569:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** return SPIx->DR; - 559 .loc 1 569 0 - 560 0000 8089 ldrh r0, [r0, #12] - 561 .LVL60: - 570:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 562 .loc 1 570 0 - 563 0002 80B2 uxth r0, r0 - 564 0004 7047 bx lr - 565 .cfi_endproc - 566 .LFE39: - 568 0006 00BF .section .text.SPI_NSSInternalSoftwareConfig,"ax",%progbits - 569 .align 2 - 570 .global SPI_NSSInternalSoftwareConfig - 571 .thumb - 572 .thumb_func - 574 SPI_NSSInternalSoftwareConfig: - 575 .LFB40: - 571:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 572:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 573:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Configures internally by software the NSS pin for the selected SPI. - 574:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - 575:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - 576:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be one of the following values: - 577:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - 578:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - 579:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 580:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 581:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) - 582:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 576 .loc 1 582 0 - 577 .cfi_startproc - 578 @ args = 0, pretend = 0, frame = 0 - 579 @ frame_needed = 0, uses_anonymous_args = 0 - 580 @ link register save eliminated. - 581 .LVL61: - 583:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 584:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 585:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - 586:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - 582 .loc 1 586 0 - 583 0000 4FF6FF63 movw r3, #65279 - 584 0004 9942 cmp r1, r3 - 585 0006 05D0 beq .L38 - 587:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 588:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Set NSS pin internally by software */ - 589:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR1 |= SPI_NSSInternalSoft_Set; - 586 .loc 1 589 0 - 587 0008 0388 ldrh r3, [r0] - 588 000a 9BB2 uxth r3, r3 - 589 000c 43F48073 orr r3, r3, #256 - 590 0010 0380 strh r3, [r0] @ movhi - 591 0012 7047 bx lr - 592 .L38: - 590:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 591:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 592:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 593:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Reset NSS pin internally by software */ - 594:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - 593 .loc 1 594 0 - 594 0014 0388 ldrh r3, [r0] - 595 0016 23F48073 bic r3, r3, #256 - 596 001a 1B04 lsls r3, r3, #16 - 597 001c 1B0C lsrs r3, r3, #16 - 598 001e 0380 strh r3, [r0] @ movhi - 599 0020 7047 bx lr - 600 .cfi_endproc - 601 .LFE40: - 603 0022 00BF .section .text.SPI_SSOutputCmd,"ax",%progbits - 604 .align 2 - 605 .global SPI_SSOutputCmd - 606 .thumb - 607 .thumb_func - 609 SPI_SSOutputCmd: - 610 .LFB41: - 595:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 596:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 597:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 598:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 599:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Enables or disables the SS output for the selected SPI. - 600:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - 601:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param NewState: new state of the SPIx SS output. - 602:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be: ENABLE or DISABLE. - 603:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 604:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 605:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) - 606:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 611 .loc 1 606 0 - 612 .cfi_startproc - 613 @ args = 0, pretend = 0, frame = 0 - 614 @ frame_needed = 0, uses_anonymous_args = 0 - 615 @ link register save eliminated. - 616 .LVL62: - 607:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 608:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 609:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 610:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if (NewState != DISABLE) - 617 .loc 1 610 0 - 618 0000 29B1 cbz r1, .L41 - 611:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 612:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Enable the selected SPI SS output */ - 613:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR2 |= CR2_SSOE_Set; - 619 .loc 1 613 0 - 620 0002 8388 ldrh r3, [r0, #4] - 621 0004 9BB2 uxth r3, r3 - 622 0006 43F00403 orr r3, r3, #4 - 623 000a 8380 strh r3, [r0, #4] @ movhi - 624 000c 7047 bx lr - 625 .L41: - 614:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 615:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 616:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 617:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Disable the selected SPI SS output */ - 618:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR2 &= CR2_SSOE_Reset; - 626 .loc 1 618 0 - 627 000e 8388 ldrh r3, [r0, #4] - 628 0010 23F00403 bic r3, r3, #4 - 629 0014 1B04 lsls r3, r3, #16 - 630 0016 1B0C lsrs r3, r3, #16 - 631 0018 8380 strh r3, [r0, #4] @ movhi - 632 001a 7047 bx lr - 633 .cfi_endproc - 634 .LFE41: - 636 .section .text.SPI_DataSizeConfig,"ax",%progbits - 637 .align 2 - 638 .global SPI_DataSizeConfig - 639 .thumb - 640 .thumb_func - 642 SPI_DataSizeConfig: - 643 .LFB42: - 619:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 620:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 621:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 622:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 623:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Configures the data size for the selected SPI. - 624:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - 625:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPI_DataSize: specifies the SPI data size. - 626:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be one of the following values: - 627:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_DataSize_16b: Set data frame format to 16bit - 628:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_DataSize_8b: Set data frame format to 8bit - 629:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 630:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 631:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) - 632:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 644 .loc 1 632 0 - 645 .cfi_startproc - 646 @ args = 0, pretend = 0, frame = 0 - 647 @ frame_needed = 0, uses_anonymous_args = 0 - 648 @ link register save eliminated. - 649 .LVL63: - 633:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 634:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 635:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - 636:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Clear DFF bit */ - 637:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - 650 .loc 1 637 0 - 651 0000 0388 ldrh r3, [r0] - 652 0002 23F40063 bic r3, r3, #2048 - 653 0006 1B04 lsls r3, r3, #16 - 654 0008 1B0C lsrs r3, r3, #16 - 655 000a 0380 strh r3, [r0] @ movhi - 638:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Set new DFF bit value */ - 639:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR1 |= SPI_DataSize; - 656 .loc 1 639 0 - 657 000c 0388 ldrh r3, [r0] - 658 000e 9BB2 uxth r3, r3 - 659 0010 1943 orrs r1, r1, r3 - 660 .LVL64: - 661 0012 0180 strh r1, [r0] @ movhi - 662 0014 7047 bx lr - 663 .cfi_endproc - 664 .LFE42: - 666 0016 00BF .section .text.SPI_TransmitCRC,"ax",%progbits - 667 .align 2 - 668 .global SPI_TransmitCRC - 669 .thumb - 670 .thumb_func - 672 SPI_TransmitCRC: - 673 .LFB43: - 640:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 641:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 642:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 643:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Transmit the SPIx CRC value. - 644:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - 645:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 646:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 647:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_TransmitCRC(SPI_TypeDef* SPIx) - 648:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 674 .loc 1 648 0 - 675 .cfi_startproc - 676 @ args = 0, pretend = 0, frame = 0 - 677 @ frame_needed = 0, uses_anonymous_args = 0 - 678 @ link register save eliminated. - 679 .LVL65: - 649:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 650:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 651:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 652:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Enable the selected SPI CRC transmission */ - 653:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR1 |= CR1_CRCNext_Set; - 680 .loc 1 653 0 - 681 0000 0388 ldrh r3, [r0] - 682 0002 9BB2 uxth r3, r3 - 683 0004 43F48053 orr r3, r3, #4096 - 684 0008 0380 strh r3, [r0] @ movhi - 685 000a 7047 bx lr - 686 .cfi_endproc - 687 .LFE43: - 689 .section .text.SPI_CalculateCRC,"ax",%progbits - 690 .align 2 - 691 .global SPI_CalculateCRC - 692 .thumb - 693 .thumb_func - 695 SPI_CalculateCRC: - 696 .LFB44: - 654:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 655:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 656:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 657:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Enables or disables the CRC value calculation of the transferred bytes. - 658:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - 659:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param NewState: new state of the SPIx CRC value calculation. - 660:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be: ENABLE or DISABLE. - 661:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 662:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 663:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) - 664:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 697 .loc 1 664 0 - 698 .cfi_startproc - 699 @ args = 0, pretend = 0, frame = 0 - 700 @ frame_needed = 0, uses_anonymous_args = 0 - 701 @ link register save eliminated. - 702 .LVL66: - 665:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 666:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 667:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 668:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if (NewState != DISABLE) - 703 .loc 1 668 0 - 704 0000 29B1 cbz r1, .L46 - 669:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 670:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Enable the selected SPI CRC calculation */ - 671:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR1 |= CR1_CRCEN_Set; - 705 .loc 1 671 0 - 706 0002 0388 ldrh r3, [r0] - 707 0004 9BB2 uxth r3, r3 - 708 0006 43F40053 orr r3, r3, #8192 - 709 000a 0380 strh r3, [r0] @ movhi - 710 000c 7047 bx lr - 711 .L46: - 672:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 673:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 674:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 675:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Disable the selected SPI CRC calculation */ - 676:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR1 &= CR1_CRCEN_Reset; - 712 .loc 1 676 0 - 713 000e 0388 ldrh r3, [r0] - 714 0010 23F40053 bic r3, r3, #8192 - 715 0014 1B04 lsls r3, r3, #16 - 716 0016 1B0C lsrs r3, r3, #16 - 717 0018 0380 strh r3, [r0] @ movhi - 718 001a 7047 bx lr - 719 .cfi_endproc - 720 .LFE44: - 722 .section .text.SPI_GetCRC,"ax",%progbits - 723 .align 2 - 724 .global SPI_GetCRC - 725 .thumb - 726 .thumb_func - 728 SPI_GetCRC: - 729 .LFB45: - 677:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 678:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 679:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 680:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 681:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Returns the transmit or the receive CRC register value for the specified SPI. - 682:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - 683:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPI_CRC: specifies the CRC register to be read. - 684:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be one of the following values: - 685:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_CRC_Tx: Selects Tx CRC register - 686:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_CRC_Rx: Selects Rx CRC register - 687:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval The selected CRC register value.. - 688:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 689:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) - 690:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 730 .loc 1 690 0 - 731 .cfi_startproc - 732 @ args = 0, pretend = 0, frame = 0 - 733 @ frame_needed = 0, uses_anonymous_args = 0 - 734 @ link register save eliminated. - 735 .LVL67: - 691:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** uint16_t crcreg = 0; - 692:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 693:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 694:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_CRC(SPI_CRC)); - 695:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if (SPI_CRC != SPI_CRC_Rx) - 736 .loc 1 695 0 - 737 0000 0129 cmp r1, #1 - 696:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 697:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the Tx CRC register */ - 698:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** crcreg = SPIx->TXCRCR; - 738 .loc 1 698 0 - 739 0002 14BF ite ne - 740 0004 008B ldrhne r0, [r0, #24] - 741 .LVL68: - 699:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 700:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 701:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 702:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the Rx CRC register */ - 703:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** crcreg = SPIx->RXCRCR; - 742 .loc 1 703 0 - 743 0006 808A ldrheq r0, [r0, #20] - 744 0008 80B2 uxth r0, r0 - 745 .LVL69: - 704:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 705:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Return the selected CRC register */ - 706:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** return crcreg; - 707:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 746 .loc 1 707 0 - 747 000a 7047 bx lr - 748 .cfi_endproc - 749 .LFE45: - 751 .section .text.SPI_GetCRCPolynomial,"ax",%progbits - 752 .align 2 - 753 .global SPI_GetCRCPolynomial - 754 .thumb - 755 .thumb_func - 757 SPI_GetCRCPolynomial: - 758 .LFB46: - 708:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 709:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 710:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Returns the CRC Polynomial register value for the specified SPI. - 711:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - 712:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval The CRC Polynomial register value. - 713:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 714:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) - 715:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 759 .loc 1 715 0 - 760 .cfi_startproc - 761 @ args = 0, pretend = 0, frame = 0 - 762 @ frame_needed = 0, uses_anonymous_args = 0 - 763 @ link register save eliminated. - 764 .LVL70: - 716:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 717:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 718:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 719:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Return the CRC polynomial register */ - 720:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** return SPIx->CRCPR; - 765 .loc 1 720 0 - 766 0000 008A ldrh r0, [r0, #16] - 767 .LVL71: - 721:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 768 .loc 1 721 0 - 769 0002 80B2 uxth r0, r0 - 770 0004 7047 bx lr - 771 .cfi_endproc - 772 .LFE46: - 774 0006 00BF .section .text.SPI_BiDirectionalLineConfig,"ax",%progbits - 775 .align 2 - 776 .global SPI_BiDirectionalLineConfig - 777 .thumb - 778 .thumb_func - 780 SPI_BiDirectionalLineConfig: - 781 .LFB47: - 722:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 723:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 724:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. - 725:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - 726:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. - 727:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be one of the following values: - 728:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_Direction_Tx: Selects Tx transmission direction - 729:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_Direction_Rx: Selects Rx receive direction - 730:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 731:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 732:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) - 733:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 782 .loc 1 733 0 - 783 .cfi_startproc - 784 @ args = 0, pretend = 0, frame = 0 - 785 @ frame_needed = 0, uses_anonymous_args = 0 - 786 @ link register save eliminated. - 787 .LVL72: - 734:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 735:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 736:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_DIRECTION(SPI_Direction)); - 737:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if (SPI_Direction == SPI_Direction_Tx) - 788 .loc 1 737 0 - 789 0000 B1F5804F cmp r1, #16384 - 790 0004 05D1 bne .L53 - 738:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 739:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Set the Tx only mode */ - 740:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR1 |= SPI_Direction_Tx; - 791 .loc 1 740 0 - 792 0006 0388 ldrh r3, [r0] - 793 0008 9BB2 uxth r3, r3 - 794 000a 43F48043 orr r3, r3, #16384 - 795 000e 0380 strh r3, [r0] @ movhi - 796 0010 7047 bx lr - 797 .L53: - 741:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 742:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 743:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 744:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Set the Rx only mode */ - 745:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->CR1 &= SPI_Direction_Rx; - 798 .loc 1 745 0 - 799 0012 0388 ldrh r3, [r0] - 800 0014 23F48043 bic r3, r3, #16384 - 801 0018 1B04 lsls r3, r3, #16 - 802 001a 1B0C lsrs r3, r3, #16 - 803 001c 0380 strh r3, [r0] @ movhi - 804 001e 7047 bx lr - 805 .cfi_endproc - 806 .LFE47: - 808 .section .text.SPI_I2S_GetFlagStatus,"ax",%progbits - 809 .align 2 - 810 .global SPI_I2S_GetFlagStatus - 811 .thumb - 812 .thumb_func - 814 SPI_I2S_GetFlagStatus: - 815 .LFB48: - 746:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 747:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 748:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 749:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 750:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Checks whether the specified SPI/I2S flag is set or not. - 751:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be - 752:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 1, 2 or 3 in SPI mode - 753:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 2 or 3 in I2S mode - 754:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. - 755:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be one of the following values: - 756:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - 757:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - 758:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_I2S_FLAG_BSY: Busy flag. - 759:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_I2S_FLAG_OVR: Overrun flag. - 760:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_FLAG_MODF: Mode Fault flag. - 761:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_FLAG_CRCERR: CRC Error flag. - 762:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg I2S_FLAG_UDR: Underrun Error flag. - 763:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg I2S_FLAG_CHSIDE: Channel Side flag. - 764:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval The new state of SPI_I2S_FLAG (SET or RESET). - 765:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 766:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) - 767:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 816 .loc 1 767 0 - 817 .cfi_startproc - 818 @ args = 0, pretend = 0, frame = 0 - 819 @ frame_needed = 0, uses_anonymous_args = 0 - 820 @ link register save eliminated. - 821 .LVL73: - 768:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** FlagStatus bitstatus = RESET; - 769:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 770:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 771:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - 772:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the status of the specified SPI/I2S flag */ - 773:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - 822 .loc 1 773 0 - 823 0000 0389 ldrh r3, [r0, #8] - 824 .LVL74: - 825 0002 1942 tst r1, r3 - 774:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 775:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* SPI_I2S_FLAG is set */ - 776:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** bitstatus = SET; - 777:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 778:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 779:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 780:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* SPI_I2S_FLAG is reset */ - 781:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** bitstatus = RESET; - 782:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 783:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Return the SPI_I2S_FLAG status */ - 784:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** return bitstatus; - 785:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 826 .loc 1 785 0 - 827 0004 14BF ite ne - 828 0006 0120 movne r0, #1 - 829 .LVL75: - 830 0008 0020 moveq r0, #0 - 831 000a 7047 bx lr - 832 .cfi_endproc - 833 .LFE48: - 835 .section .text.SPI_I2S_ClearFlag,"ax",%progbits - 836 .align 2 - 837 .global SPI_I2S_ClearFlag - 838 .thumb - 839 .thumb_func - 841 SPI_I2S_ClearFlag: - 842 .LFB49: - 786:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 787:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 788:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Clears the SPIx CRC Error (CRCERR) flag. - 789:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be - 790:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 1, 2 or 3 in SPI mode - 791:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - 792:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This function clears only CRCERR flag. - 793:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @note - 794:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - OVR (OverRun error) flag is cleared by software sequence: a read - 795:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - 796:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - 797:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - UDR (UnderRun error) flag is cleared by a read operation to - 798:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * SPI_SR register (SPI_I2S_GetFlagStatus()). - 799:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - 800:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - 801:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - 802:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 803:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 804:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) - 805:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 843 .loc 1 805 0 - 844 .cfi_startproc - 845 @ args = 0, pretend = 0, frame = 0 - 846 @ frame_needed = 0, uses_anonymous_args = 0 - 847 @ link register save eliminated. - 848 .LVL76: - 806:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 807:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 808:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - 809:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 810:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Clear the selected SPI CRC Error (CRCERR) flag */ - 811:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->SR = (uint16_t)~SPI_I2S_FLAG; - 849 .loc 1 811 0 - 850 0000 C943 mvns r1, r1 - 851 .LVL77: - 852 0002 89B2 uxth r1, r1 - 853 0004 0181 strh r1, [r0, #8] @ movhi - 854 0006 7047 bx lr - 855 .cfi_endproc - 856 .LFE49: - 858 .section .text.SPI_I2S_GetITStatus,"ax",%progbits - 859 .align 2 - 860 .global SPI_I2S_GetITStatus - 861 .thumb - 862 .thumb_func - 864 SPI_I2S_GetITStatus: - 865 .LFB50: - 812:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 813:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 814:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 815:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. - 816:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be - 817:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 1, 2 or 3 in SPI mode - 818:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 2 or 3 in I2S mode - 819:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. - 820:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This parameter can be one of the following values: - 821:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - 822:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - 823:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_I2S_IT_OVR: Overrun interrupt. - 824:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_IT_MODF: Mode Fault interrupt. - 825:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg SPI_IT_CRCERR: CRC Error interrupt. - 826:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @arg I2S_IT_UDR: Underrun Error interrupt. - 827:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval The new state of SPI_I2S_IT (SET or RESET). - 828:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 829:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) - 830:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 866 .loc 1 830 0 - 867 .cfi_startproc - 868 @ args = 0, pretend = 0, frame = 0 - 869 @ frame_needed = 0, uses_anonymous_args = 0 - 870 @ link register save eliminated. - 871 .LVL78: - 872 0000 10B4 push {r4} - 873 .cfi_def_cfa_offset 4 - 874 .cfi_offset 4, -4 - 875 .LVL79: - 831:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** ITStatus bitstatus = RESET; - 832:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** uint16_t itpos = 0, itmask = 0, enablestatus = 0; - 833:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 834:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 835:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 836:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - 837:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 838:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the SPI/I2S IT index */ - 839:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** itpos = 0x01 << (SPI_I2S_IT & 0x0F); - 840:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 841:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the SPI/I2S IT mask */ - 842:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** itmask = SPI_I2S_IT >> 4; - 843:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 844:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Set the IT mask */ - 845:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** itmask = 0x01 << itmask; - 846:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 847:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the SPI_I2S_IT enable bit status */ - 848:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** enablestatus = (SPIx->CR2 & itmask) ; - 876 .loc 1 848 0 - 877 0002 8388 ldrh r3, [r0, #4] - 878 0004 9CB2 uxth r4, r3 - 879 .LVL80: - 849:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 850:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the status of the specified SPI/I2S interrupt */ - 851:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - 880 .loc 1 851 0 - 881 0006 0289 ldrh r2, [r0, #8] - 882 0008 92B2 uxth r2, r2 - 839:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 883 .loc 1 839 0 - 884 000a 01F00F00 and r0, r1, #15 - 885 .LVL81: - 886 000e 0123 movs r3, #1 - 887 0010 8340 lsls r3, r3, r0 - 888 .loc 1 851 0 - 889 0012 1A42 tst r2, r3 - 890 0014 07D0 beq .L59 - 845:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 891 .loc 1 845 0 discriminator 1 - 892 0016 0909 lsrs r1, r1, #4 - 893 .LVL82: - 894 0018 0123 movs r3, #1 - 895 001a 8B40 lsls r3, r3, r1 - 896 .loc 1 851 0 discriminator 1 - 897 001c 1C42 tst r4, r3 - 852:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 853:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* SPI_I2S_IT is set */ - 854:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** bitstatus = SET; - 898 .loc 1 854 0 discriminator 1 - 899 001e 14BF ite ne - 900 0020 0120 movne r0, #1 - 901 0022 0020 moveq r0, #0 - 902 0024 00E0 b .L58 - 903 .LVL83: - 904 .L59: - 855:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 856:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** else - 857:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 858:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* SPI_I2S_IT is reset */ - 859:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** bitstatus = RESET; - 905 .loc 1 859 0 - 906 0026 0020 movs r0, #0 - 907 .LVL84: - 908 .L58: - 860:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 861:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Return the SPI_I2S_IT status */ - 862:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** return bitstatus; - 863:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** } - 909 .loc 1 863 0 - 910 0028 5DF8044B ldr r4, [sp], #4 - 911 .cfi_restore 4 - 912 .cfi_def_cfa_offset 0 - 913 .LVL85: - 914 002c 7047 bx lr - 915 .cfi_endproc - 916 .LFE50: - 918 002e 00BF .section .text.SPI_I2S_ClearITPendingBit,"ax",%progbits - 919 .align 2 - 920 .global SPI_I2S_ClearITPendingBit - 921 .thumb - 922 .thumb_func - 924 SPI_I2S_ClearITPendingBit: - 925 .LFB51: - 864:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 865:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /** - 866:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - 867:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPIx: where x can be - 868:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - 1, 2 or 3 in SPI mode - 869:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - 870:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * This function clears only CRCERR interrupt pending bit. - 871:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @note - 872:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - OVR (OverRun Error) interrupt pending bit is cleared by software - 873:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - 874:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - 875:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - UDR (UnderRun Error) interrupt pending bit is cleared by a read - 876:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * operation to SPI_SR register (SPI_I2S_GetITStatus()). - 877:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - 878:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - 879:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - 880:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * the SPI). - 881:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** * @retval None - 882:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** */ - 883:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) - 884:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** { - 926 .loc 1 884 0 - 927 .cfi_startproc - 928 @ args = 0, pretend = 0, frame = 0 - 929 @ frame_needed = 0, uses_anonymous_args = 0 - 930 @ link register save eliminated. - 931 .LVL86: - 885:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** uint16_t itpos = 0; - 886:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Check the parameters */ - 887:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_ALL_PERIPH(SPIx)); - 888:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - 889:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 890:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Get the SPI IT index */ - 891:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** itpos = 0x01 << (SPI_I2S_IT & 0x0F); - 932 .loc 1 891 0 - 933 0000 01F00F01 and r1, r1, #15 - 934 .LVL87: - 935 0004 0123 movs r3, #1 - 936 0006 8B40 lsls r3, r3, r1 - 892:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** - 893:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - 894:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c **** SPIx->SR = (uint16_t)~itpos; - 937 .loc 1 894 0 - 938 0008 DB43 mvns r3, r3 - 939 000a 9BB2 uxth r3, r3 - 940 000c 0381 strh r3, [r0, #8] @ movhi - 941 000e 7047 bx lr - 942 .cfi_endproc - 943 .LFE51: - 945 .text - 946 .Letext0: - 947 .file 2 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\mach - 948 .file 3 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\stdi - 949 .file 4 "./lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h" - 950 .file 5 "./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h" - 951 .file 6 "./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h" - 952 .file 7 "./lib/CMSIS/CM3/CoreSupport/core_cm3.h" -DEFINED SYMBOLS - *ABS*:00000000 stm32f10x_spi.c -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:19 .text.SPI_I2S_DeInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:24 .text.SPI_I2S_DeInit:00000000 SPI_I2S_DeInit -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:92 .text.SPI_I2S_DeInit:00000058 $d -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:99 .text.SPI_Init:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:104 .text.SPI_Init:00000000 SPI_Init -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:163 .text.I2S_Init:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:168 .text.I2S_Init:00000000 I2S_Init -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:306 .text.I2S_Init:000000a4 $d -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:311 .text.SPI_StructInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:316 .text.SPI_StructInit:00000000 SPI_StructInit -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:349 .text.I2S_StructInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:354 .text.I2S_StructInit:00000000 I2S_StructInit -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:381 .text.SPI_Cmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:386 .text.SPI_Cmd:00000000 SPI_Cmd -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:414 .text.I2S_Cmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:419 .text.I2S_Cmd:00000000 I2S_Cmd -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:447 .text.SPI_I2S_ITConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:452 .text.SPI_I2S_ITConfig:00000000 SPI_I2S_ITConfig -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:491 .text.SPI_I2S_DMACmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:496 .text.SPI_I2S_DMACmd:00000000 SPI_I2S_DMACmd -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:526 .text.SPI_I2S_SendData:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:531 .text.SPI_I2S_SendData:00000000 SPI_I2S_SendData -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:546 .text.SPI_I2S_ReceiveData:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:551 .text.SPI_I2S_ReceiveData:00000000 SPI_I2S_ReceiveData -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:569 .text.SPI_NSSInternalSoftwareConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:574 .text.SPI_NSSInternalSoftwareConfig:00000000 SPI_NSSInternalSoftwareConfig -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:604 .text.SPI_SSOutputCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:609 .text.SPI_SSOutputCmd:00000000 SPI_SSOutputCmd -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:637 .text.SPI_DataSizeConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:642 .text.SPI_DataSizeConfig:00000000 SPI_DataSizeConfig -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:667 .text.SPI_TransmitCRC:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:672 .text.SPI_TransmitCRC:00000000 SPI_TransmitCRC -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:690 .text.SPI_CalculateCRC:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:695 .text.SPI_CalculateCRC:00000000 SPI_CalculateCRC -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:723 .text.SPI_GetCRC:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:728 .text.SPI_GetCRC:00000000 SPI_GetCRC -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:752 .text.SPI_GetCRCPolynomial:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:757 .text.SPI_GetCRCPolynomial:00000000 SPI_GetCRCPolynomial -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:775 .text.SPI_BiDirectionalLineConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:780 .text.SPI_BiDirectionalLineConfig:00000000 SPI_BiDirectionalLineConfig -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:809 .text.SPI_I2S_GetFlagStatus:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:814 .text.SPI_I2S_GetFlagStatus:00000000 SPI_I2S_GetFlagStatus -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:836 .text.SPI_I2S_ClearFlag:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:841 .text.SPI_I2S_ClearFlag:00000000 SPI_I2S_ClearFlag -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:859 .text.SPI_I2S_GetITStatus:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:864 .text.SPI_I2S_GetITStatus:00000000 SPI_I2S_GetITStatus -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:919 .text.SPI_I2S_ClearITPendingBit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccKxFG03.s:924 .text.SPI_I2S_ClearITPendingBit:00000000 SPI_I2S_ClearITPendingBit - .debug_frame:00000010 $d - -UNDEFINED SYMBOLS -RCC_APB2PeriphResetCmd -RCC_APB1PeriphResetCmd -RCC_GetClocksFreq diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/stm32f10x_usart.lst b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/stm32f10x_usart.lst deleted file mode 100644 index 19dfb93b..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Boot/obj/stm32f10x_usart.lst +++ /dev/null @@ -1,2276 +0,0 @@ - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 1 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "stm32f10x_usart.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.USART_DeInit,"ax",%progbits - 19 .align 2 - 20 .global USART_DeInit - 21 .thumb - 22 .thumb_func - 24 USART_DeInit: - 25 .LFB29: - 26 .file 1 "./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c" - 1:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 2:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** ****************************************************************************** - 3:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @file stm32f10x_usart.c - 4:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @author MCD Application Team - 5:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @version V3.5.0 - 6:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @date 11-March-2011 - 7:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief This file provides all the USART firmware functions. - 8:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** ****************************************************************************** - 9:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @attention - 10:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * - 11:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - 12:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - 13:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - 14:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - 15:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - 16:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - 17:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * - 18:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** *

© COPYRIGHT 2011 STMicroelectronics

- 19:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** ****************************************************************************** - 20:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 21:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 22:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Includes ------------------------------------------------------------------*/ - 23:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #include "stm32f10x_usart.h" - 24:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #include "stm32f10x_rcc.h" - 25:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 26:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** @addtogroup STM32F10x_StdPeriph_Driver - 27:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @{ - 28:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 29:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 30:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** @defgroup USART - 31:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief USART driver modules - 32:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @{ - 33:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 34:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 35:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** @defgroup USART_Private_TypesDefinitions - 36:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @{ - 37:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 38:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 39:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 40:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @} - 41:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 42:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 43:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** @defgroup USART_Private_Defines - 44:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @{ - 45:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 46:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 47:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */ - 48:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */ - 49:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 50:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ - 51:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 52:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ - 53:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ - 54:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */ - 55:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */ - 56:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */ - 57:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 58:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ - 59:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ - 60:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 61:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ - 62:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */ - 63:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */ - 64:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 65:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */ - 66:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ - 67:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 68:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ - 69:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ - 70:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 71:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ - 72:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ - 73:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 74:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ - 75:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */ - 76:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 77:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ - 78:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ - 79:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ - 80:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ - 81:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ - 82:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 83:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* USART OverSampling-8 Mask */ - 84:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */ - 85:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */ - 86:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 87:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* USART One Bit Sampling Mask */ - 88:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */ - 89:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** #define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */ - 90:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 91:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 92:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @} - 93:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 94:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 95:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** @defgroup USART_Private_Macros - 96:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @{ - 97:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 98:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 99:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 100:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @} - 101:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 102:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 103:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** @defgroup USART_Private_Variables - 104:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @{ - 105:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 106:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 107:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 108:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @} - 109:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 110:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 111:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** @defgroup USART_Private_FunctionPrototypes - 112:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @{ - 113:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 114:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 115:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 116:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @} - 117:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 118:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 119:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** @defgroup USART_Private_Functions - 120:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @{ - 121:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 122:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 123:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 124:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Deinitializes the USARTx peripheral registers to their default reset values. - 125:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 126:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 127:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 128:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 129:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 130:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_DeInit(USART_TypeDef* USARTx) - 131:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 27 .loc 1 131 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 .LVL0: - 32 0000 08B5 push {r3, lr} - 33 .cfi_def_cfa_offset 8 - 34 .cfi_offset 3, -8 - 35 .cfi_offset 14, -4 - 132:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 133:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 134:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 135:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (USARTx == USART1) - 36 .loc 1 135 0 - 37 0002 234B ldr r3, .L8 - 38 0004 9842 cmp r0, r3 - 39 0006 0AD1 bne .L2 - 136:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 137:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - 40 .loc 1 137 0 - 41 0008 4FF48040 mov r0, #16384 - 42 .LVL1: - 43 000c 0121 movs r1, #1 - 44 000e FFF7FEFF bl RCC_APB2PeriphResetCmd - 45 .LVL2: - 138:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - 46 .loc 1 138 0 - 47 0012 4FF48040 mov r0, #16384 - 48 0016 0021 movs r1, #0 - 49 0018 FFF7FEFF bl RCC_APB2PeriphResetCmd - 50 .LVL3: - 51 001c 08BD pop {r3, pc} - 52 .LVL4: - 53 .L2: - 139:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 140:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else if (USARTx == USART2) - 54 .loc 1 140 0 - 55 001e 1D4B ldr r3, .L8+4 - 56 0020 9842 cmp r0, r3 - 57 0022 0AD1 bne .L4 - 141:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 142:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - 58 .loc 1 142 0 - 59 0024 4FF40030 mov r0, #131072 - 60 .LVL5: - 61 0028 0121 movs r1, #1 - 62 002a FFF7FEFF bl RCC_APB1PeriphResetCmd - 63 .LVL6: - 143:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - 64 .loc 1 143 0 - 65 002e 4FF40030 mov r0, #131072 - 66 0032 0021 movs r1, #0 - 67 0034 FFF7FEFF bl RCC_APB1PeriphResetCmd - 68 .LVL7: - 69 0038 08BD pop {r3, pc} - 70 .LVL8: - 71 .L4: - 144:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 145:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else if (USARTx == USART3) - 72 .loc 1 145 0 - 73 003a 174B ldr r3, .L8+8 - 74 003c 9842 cmp r0, r3 - 75 003e 0AD1 bne .L5 - 146:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 147:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - 76 .loc 1 147 0 - 77 0040 4FF48020 mov r0, #262144 - 78 .LVL9: - 79 0044 0121 movs r1, #1 - 80 0046 FFF7FEFF bl RCC_APB1PeriphResetCmd - 81 .LVL10: - 148:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - 82 .loc 1 148 0 - 83 004a 4FF48020 mov r0, #262144 - 84 004e 0021 movs r1, #0 - 85 0050 FFF7FEFF bl RCC_APB1PeriphResetCmd - 86 .LVL11: - 87 0054 08BD pop {r3, pc} - 88 .LVL12: - 89 .L5: - 149:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 150:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else if (USARTx == UART4) - 90 .loc 1 150 0 - 91 0056 114B ldr r3, .L8+12 - 92 0058 9842 cmp r0, r3 - 93 005a 0AD1 bne .L6 - 151:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 152:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - 94 .loc 1 152 0 - 95 005c 4FF40020 mov r0, #524288 - 96 .LVL13: - 97 0060 0121 movs r1, #1 - 98 0062 FFF7FEFF bl RCC_APB1PeriphResetCmd - 99 .LVL14: - 153:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - 100 .loc 1 153 0 - 101 0066 4FF40020 mov r0, #524288 - 102 006a 0021 movs r1, #0 - 103 006c FFF7FEFF bl RCC_APB1PeriphResetCmd - 104 .LVL15: - 105 0070 08BD pop {r3, pc} - 106 .LVL16: - 107 .L6: - 154:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 155:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 156:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 157:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (USARTx == UART5) - 108 .loc 1 157 0 - 109 0072 0B4B ldr r3, .L8+16 - 110 0074 9842 cmp r0, r3 - 111 0076 09D1 bne .L1 - 158:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 159:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - 112 .loc 1 159 0 - 113 0078 4FF48010 mov r0, #1048576 - 114 .LVL17: - 115 007c 0121 movs r1, #1 - 116 007e FFF7FEFF bl RCC_APB1PeriphResetCmd - 117 .LVL18: - 160:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - 118 .loc 1 160 0 - 119 0082 4FF48010 mov r0, #1048576 - 120 0086 0021 movs r1, #0 - 121 0088 FFF7FEFF bl RCC_APB1PeriphResetCmd - 122 .LVL19: - 123 .L1: - 124 008c 08BD pop {r3, pc} - 125 .L9: - 126 008e 00BF .align 2 - 127 .L8: - 128 0090 00380140 .word 1073821696 - 129 0094 00440040 .word 1073759232 - 130 0098 00480040 .word 1073760256 - 131 009c 004C0040 .word 1073761280 - 132 00a0 00500040 .word 1073762304 - 133 .cfi_endproc - 134 .LFE29: - 136 .section .text.USART_Init,"ax",%progbits - 137 .align 2 - 138 .global USART_Init - 139 .thumb - 140 .thumb_func - 142 USART_Init: - 143 .LFB30: - 161:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 162:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 163:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 164:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 165:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 166:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Initializes the USARTx peripheral according to the specified - 167:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * parameters in the USART_InitStruct . - 168:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 169:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 170:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 171:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - 172:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * that contains the configuration information for the specified USART - 173:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * peripheral. - 174:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 175:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 176:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) - 177:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 144 .loc 1 177 0 - 145 .cfi_startproc - 146 @ args = 0, pretend = 0, frame = 24 - 147 @ frame_needed = 0, uses_anonymous_args = 0 - 148 .LVL20: - 149 0000 30B5 push {r4, r5, lr} - 150 .cfi_def_cfa_offset 12 - 151 .cfi_offset 4, -12 - 152 .cfi_offset 5, -8 - 153 .cfi_offset 14, -4 - 154 0002 87B0 sub sp, sp, #28 - 155 .cfi_def_cfa_offset 40 - 156 0004 0446 mov r4, r0 - 157 0006 0D46 mov r5, r1 - 158 .LVL21: - 178:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** uint32_t tmpreg = 0x00, apbclock = 0x00; - 179:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** uint32_t integerdivider = 0x00; - 180:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** uint32_t fractionaldivider = 0x00; - 181:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** uint32_t usartxbase = 0; - 182:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** RCC_ClocksTypeDef RCC_ClocksStatus; - 183:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 184:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 185:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - 186:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - 187:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - 188:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - 189:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - 190:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - 191:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* The hardware flow control is available only for USART1, USART2 and USART3 */ - 192:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - 193:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 194:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_123_PERIPH(USARTx)); - 195:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 196:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 197:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** usartxbase = (uint32_t)USARTx; - 198:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 199:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /*---------------------------- USART CR2 Configuration -----------------------*/ - 200:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg = USARTx->CR2; - 159 .loc 1 200 0 - 160 0008 038A ldrh r3, [r0, #16] - 161 000a 9BB2 uxth r3, r3 - 162 .LVL22: - 201:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Clear STOP[13:12] bits */ - 202:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg &= CR2_STOP_CLEAR_Mask; - 163 .loc 1 202 0 - 164 000c 23F44053 bic r3, r3, #12288 - 165 .LVL23: - 203:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ - 204:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Set STOP[13:12] bits according to USART_StopBits value */ - 205:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - 166 .loc 1 205 0 - 167 0010 CA88 ldrh r2, [r1, #6] - 168 0012 1343 orrs r3, r3, r2 - 169 .LVL24: - 206:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 207:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Write to USART CR2 */ - 208:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR2 = (uint16_t)tmpreg; - 170 .loc 1 208 0 - 171 0014 0382 strh r3, [r0, #16] @ movhi - 209:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 210:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /*---------------------------- USART CR1 Configuration -----------------------*/ - 211:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg = USARTx->CR1; - 172 .loc 1 211 0 - 173 0016 8289 ldrh r2, [r0, #12] - 174 0018 92B2 uxth r2, r2 - 175 .LVL25: - 212:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Clear M, PCE, PS, TE and RE bits */ - 213:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg &= CR1_CLEAR_Mask; - 214:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Configure the USART Word Length, Parity and mode ----------------------- */ - 215:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Set the M bits according to USART_WordLength value */ - 216:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Set PCE and PS bits according to USART_Parity value */ - 217:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Set TE and RE bits according to USART_Mode value */ - 218:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - 176 .loc 1 218 0 - 177 001a 0989 ldrh r1, [r1, #8] - 178 .LVL26: - 179 001c AB88 ldrh r3, [r5, #4] - 180 001e 0B43 orrs r3, r3, r1 - 181 0020 6989 ldrh r1, [r5, #10] - 182 0022 0B43 orrs r3, r3, r1 - 213:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Configure the USART Word Length, Parity and mode ----------------------- */ - 183 .loc 1 213 0 - 184 0024 22F4B052 bic r2, r2, #5632 - 185 .LVL27: - 186 0028 22F00C02 bic r2, r2, #12 - 187 .loc 1 218 0 - 188 002c 1343 orrs r3, r3, r2 - 189 002e 9BB2 uxth r3, r3 - 190 .LVL28: - 219:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USART_InitStruct->USART_Mode; - 220:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Write to USART CR1 */ - 221:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR1 = (uint16_t)tmpreg; - 191 .loc 1 221 0 - 192 0030 8381 strh r3, [r0, #12] @ movhi - 222:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 223:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /*---------------------------- USART CR3 Configuration -----------------------*/ - 224:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg = USARTx->CR3; - 193 .loc 1 224 0 - 194 0032 838A ldrh r3, [r0, #20] - 195 .LVL29: - 196 0034 9BB2 uxth r3, r3 - 197 .LVL30: - 225:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Clear CTSE and RTSE bits */ - 226:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg &= CR3_CLEAR_Mask; - 198 .loc 1 226 0 - 199 0036 23F44073 bic r3, r3, #768 - 200 .LVL31: - 227:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Configure the USART HFC -------------------------------------------------*/ - 228:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - 229:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - 201 .loc 1 229 0 - 202 003a AA89 ldrh r2, [r5, #12] - 203 003c 1343 orrs r3, r3, r2 - 204 .LVL32: - 230:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Write to USART CR3 */ - 231:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 = (uint16_t)tmpreg; - 205 .loc 1 231 0 - 206 003e 8382 strh r3, [r0, #20] @ movhi - 232:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 233:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /*---------------------------- USART BRR Configuration -----------------------*/ - 234:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Configure the USART Baud Rate -------------------------------------------*/ - 235:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** RCC_GetClocksFreq(&RCC_ClocksStatus); - 207 .loc 1 235 0 - 208 0040 01A8 add r0, sp, #4 - 209 .LVL33: - 210 0042 FFF7FEFF bl RCC_GetClocksFreq - 211 .LVL34: - 236:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (usartxbase == USART1_BASE) - 212 .loc 1 236 0 - 213 0046 1A4B ldr r3, .L18 - 214 0048 9C42 cmp r4, r3 - 237:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 238:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** apbclock = RCC_ClocksStatus.PCLK2_Frequency; - 215 .loc 1 238 0 - 216 004a 0CBF ite eq - 217 004c 049B ldreq r3, [sp, #16] - 218 .LVL35: - 239:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 240:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 241:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 242:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** apbclock = RCC_ClocksStatus.PCLK1_Frequency; - 219 .loc 1 242 0 - 220 004e 039B ldrne r3, [sp, #12] - 221 .LVL36: - 243:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 244:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 245:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Determine the integer part */ - 246:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if ((USARTx->CR1 & CR1_OVER8_Set) != 0) - 222 .loc 1 246 0 - 223 0050 A289 ldrh r2, [r4, #12] - 224 0052 12B2 sxth r2, r2 - 225 0054 002A cmp r2, #0 - 247:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 248:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Integer part computing in case Oversampling mode is 8 Samples */ - 249:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - 226 .loc 1 249 0 - 227 0056 03EB8303 add r3, r3, r3, lsl #2 - 228 .LVL37: - 229 005a 03EB8303 add r3, r3, r3, lsl #2 - 230 005e 2968 ldr r1, [r5] - 231 0060 B4BF ite lt - 232 0062 4900 lsllt r1, r1, #1 - 250:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 251:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - 252:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 253:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Integer part computing in case Oversampling mode is 16 Samples */ - 254:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - 233 .loc 1 254 0 - 234 0064 8900 lslge r1, r1, #2 - 235 0066 B3FBF1F1 udiv r1, r3, r1 - 236 .LVL38: - 255:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 256:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg = (integerdivider / 100) << 4; - 237 .loc 1 256 0 - 238 006a 124B ldr r3, .L18+4 - 239 006c A3FB0123 umull r2, r3, r3, r1 - 240 0070 5809 lsrs r0, r3, #5 - 241 .LVL39: - 257:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 258:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Determine the fractional part */ - 259:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - 242 .loc 1 259 0 - 243 0072 0501 lsls r5, r0, #4 - 244 .LVL40: - 245 0074 6423 movs r3, #100 - 246 0076 00FB1313 mls r3, r0, r3, r1 - 247 .LVL41: - 260:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 261:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Implement the fractional part in the register */ - 262:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if ((USARTx->CR1 & CR1_OVER8_Set) != 0) - 248 .loc 1 262 0 - 249 007a A289 ldrh r2, [r4, #12] - 250 007c 12B2 sxth r2, r2 - 251 007e 002A cmp r2, #0 - 252 0080 09DA bge .L15 - 263:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 264:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - 253 .loc 1 264 0 - 254 0082 D900 lsls r1, r3, #3 - 255 .LVL42: - 256 0084 3231 adds r1, r1, #50 - 257 0086 0B4A ldr r2, .L18+4 - 258 0088 A2FB0131 umull r3, r1, r2, r1 - 259 .LVL43: - 260 008c C1F34212 ubfx r2, r1, #5, #3 - 261 0090 42EA0503 orr r3, r2, r5 - 262 .LVL44: - 263 0094 07E0 b .L16 - 264 .LVL45: - 265 .L15: - 265:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 266:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - 267:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 268:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - 266 .loc 1 268 0 - 267 0096 1B01 lsls r3, r3, #4 - 268 .LVL46: - 269 0098 3233 adds r3, r3, #50 - 270 009a 064A ldr r2, .L18+4 - 271 009c A2FB0323 umull r2, r3, r2, r3 - 272 00a0 C3F34313 ubfx r3, r3, #5, #4 - 273 00a4 2B43 orrs r3, r3, r5 - 274 .LVL47: - 275 .L16: - 269:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 270:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 271:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Write to USART BRR */ - 272:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->BRR = (uint16_t)tmpreg; - 276 .loc 1 272 0 - 277 00a6 9BB2 uxth r3, r3 - 278 .LVL48: - 279 00a8 2381 strh r3, [r4, #8] @ movhi - 273:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 280 .loc 1 273 0 - 281 00aa 07B0 add sp, sp, #28 - 282 .cfi_def_cfa_offset 12 - 283 @ sp needed - 284 00ac 30BD pop {r4, r5, pc} - 285 .LVL49: - 286 .L19: - 287 00ae 00BF .align 2 - 288 .L18: - 289 00b0 00380140 .word 1073821696 - 290 00b4 1F85EB51 .word 1374389535 - 291 .cfi_endproc - 292 .LFE30: - 294 .section .text.USART_StructInit,"ax",%progbits - 295 .align 2 - 296 .global USART_StructInit - 297 .thumb - 298 .thumb_func - 300 USART_StructInit: - 301 .LFB31: - 274:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 275:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 276:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Fills each USART_InitStruct member with its default value. - 277:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - 278:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * which will be initialized. - 279:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 280:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 281:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_StructInit(USART_InitTypeDef* USART_InitStruct) - 282:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 302 .loc 1 282 0 - 303 .cfi_startproc - 304 @ args = 0, pretend = 0, frame = 0 - 305 @ frame_needed = 0, uses_anonymous_args = 0 - 306 @ link register save eliminated. - 307 .LVL50: - 283:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* USART_InitStruct members default value */ - 284:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USART_InitStruct->USART_BaudRate = 9600; - 308 .loc 1 284 0 - 309 0000 4FF41653 mov r3, #9600 - 310 0004 0360 str r3, [r0] - 285:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USART_InitStruct->USART_WordLength = USART_WordLength_8b; - 311 .loc 1 285 0 - 312 0006 0023 movs r3, #0 - 313 0008 8380 strh r3, [r0, #4] @ movhi - 286:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USART_InitStruct->USART_StopBits = USART_StopBits_1; - 314 .loc 1 286 0 - 315 000a C380 strh r3, [r0, #6] @ movhi - 287:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USART_InitStruct->USART_Parity = USART_Parity_No ; - 316 .loc 1 287 0 - 317 000c 0381 strh r3, [r0, #8] @ movhi - 288:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - 318 .loc 1 288 0 - 319 000e 0C22 movs r2, #12 - 320 0010 4281 strh r2, [r0, #10] @ movhi - 289:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; - 321 .loc 1 289 0 - 322 0012 8381 strh r3, [r0, #12] @ movhi - 323 0014 7047 bx lr - 324 .cfi_endproc - 325 .LFE31: - 327 0016 00BF .section .text.USART_ClockInit,"ax",%progbits - 328 .align 2 - 329 .global USART_ClockInit - 330 .thumb - 331 .thumb_func - 333 USART_ClockInit: - 334 .LFB32: - 290:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 291:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 292:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 293:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Initializes the USARTx peripheral Clock according to the - 294:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * specified parameters in the USART_ClockInitStruct . - 295:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. - 296:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - 297:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * structure that contains the configuration information for the specified - 298:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART peripheral. - 299:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. - 300:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 301:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 302:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) - 303:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 335 .loc 1 303 0 - 336 .cfi_startproc - 337 @ args = 0, pretend = 0, frame = 0 - 338 @ frame_needed = 0, uses_anonymous_args = 0 - 339 @ link register save eliminated. - 340 .LVL51: - 341 0000 10B4 push {r4} - 342 .cfi_def_cfa_offset 4 - 343 .cfi_offset 4, -4 - 344 .LVL52: - 304:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** uint32_t tmpreg = 0x00; - 305:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 306:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_123_PERIPH(USARTx)); - 307:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - 308:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - 309:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - 310:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); - 311:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 312:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /*---------------------------- USART CR2 Configuration -----------------------*/ - 313:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg = USARTx->CR2; - 345 .loc 1 313 0 - 346 0002 028A ldrh r2, [r0, #16] - 347 0004 92B2 uxth r2, r2 - 348 .LVL53: - 314:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - 315:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg &= CR2_CLOCK_CLEAR_Mask; - 316:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - 317:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Set CLKEN bit according to USART_Clock value */ - 318:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Set CPOL bit according to USART_CPOL value */ - 319:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Set CPHA bit according to USART_CPHA value */ - 320:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Set LBCL bit according to USART_LastBit value */ - 321:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - 322:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - 349 .loc 1 322 0 - 350 0006 4C88 ldrh r4, [r1, #2] - 351 0008 0B88 ldrh r3, [r1] - 352 000a 2343 orrs r3, r3, r4 - 353 000c 8C88 ldrh r4, [r1, #4] - 354 000e 2343 orrs r3, r3, r4 - 355 0010 C988 ldrh r1, [r1, #6] - 356 .LVL54: - 357 0012 0B43 orrs r3, r3, r1 - 315:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - 358 .loc 1 315 0 - 359 0014 22F47062 bic r2, r2, #3840 - 360 .LVL55: - 321:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - 361 .loc 1 321 0 - 362 0018 1343 orrs r3, r3, r2 - 363 001a 9BB2 uxth r3, r3 - 364 .LVL56: - 323:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Write to USART CR2 */ - 324:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR2 = (uint16_t)tmpreg; - 365 .loc 1 324 0 - 366 001c 0382 strh r3, [r0, #16] @ movhi - 325:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 367 .loc 1 325 0 - 368 001e 5DF8044B ldr r4, [sp], #4 - 369 .cfi_restore 4 - 370 .cfi_def_cfa_offset 0 - 371 0022 7047 bx lr - 372 .cfi_endproc - 373 .LFE32: - 375 .section .text.USART_ClockStructInit,"ax",%progbits - 376 .align 2 - 377 .global USART_ClockStructInit - 378 .thumb - 379 .thumb_func - 381 USART_ClockStructInit: - 382 .LFB33: - 326:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 327:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 328:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Fills each USART_ClockInitStruct member with its default value. - 329:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - 330:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * structure which will be initialized. - 331:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 332:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 333:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) - 334:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 383 .loc 1 334 0 - 384 .cfi_startproc - 385 @ args = 0, pretend = 0, frame = 0 - 386 @ frame_needed = 0, uses_anonymous_args = 0 - 387 @ link register save eliminated. - 388 .LVL57: - 335:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* USART_ClockInitStruct members default value */ - 336:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - 389 .loc 1 336 0 - 390 0000 0023 movs r3, #0 - 391 0002 0380 strh r3, [r0] @ movhi - 337:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - 392 .loc 1 337 0 - 393 0004 4380 strh r3, [r0, #2] @ movhi - 338:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - 394 .loc 1 338 0 - 395 0006 8380 strh r3, [r0, #4] @ movhi - 339:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; - 396 .loc 1 339 0 - 397 0008 C380 strh r3, [r0, #6] @ movhi - 398 000a 7047 bx lr - 399 .cfi_endproc - 400 .LFE33: - 402 .section .text.USART_Cmd,"ax",%progbits - 403 .align 2 - 404 .global USART_Cmd - 405 .thumb - 406 .thumb_func - 408 USART_Cmd: - 409 .LFB34: - 340:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 341:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 342:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 343:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Enables or disables the specified USART peripheral. - 344:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 345:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 346:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 347:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param NewState: new state of the USARTx peripheral. - 348:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be: ENABLE or DISABLE. - 349:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 350:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 351:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) - 352:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 410 .loc 1 352 0 - 411 .cfi_startproc - 412 @ args = 0, pretend = 0, frame = 0 - 413 @ frame_needed = 0, uses_anonymous_args = 0 - 414 @ link register save eliminated. - 415 .LVL58: - 353:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 354:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 355:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 356:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 357:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (NewState != DISABLE) - 416 .loc 1 357 0 - 417 0000 29B1 cbz r1, .L25 - 358:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 359:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Enable the selected USART by setting the UE bit in the CR1 register */ - 360:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR1 |= CR1_UE_Set; - 418 .loc 1 360 0 - 419 0002 8389 ldrh r3, [r0, #12] - 420 0004 9BB2 uxth r3, r3 - 421 0006 43F40053 orr r3, r3, #8192 - 422 000a 8381 strh r3, [r0, #12] @ movhi - 423 000c 7047 bx lr - 424 .L25: - 361:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 362:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 363:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 364:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Disable the selected USART by clearing the UE bit in the CR1 register */ - 365:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR1 &= CR1_UE_Reset; - 425 .loc 1 365 0 - 426 000e 8389 ldrh r3, [r0, #12] - 427 0010 23F40053 bic r3, r3, #8192 - 428 0014 1B04 lsls r3, r3, #16 - 429 0016 1B0C lsrs r3, r3, #16 - 430 0018 8381 strh r3, [r0, #12] @ movhi - 431 001a 7047 bx lr - 432 .cfi_endproc - 433 .LFE34: - 435 .section .text.USART_ITConfig,"ax",%progbits - 436 .align 2 - 437 .global USART_ITConfig - 438 .thumb - 439 .thumb_func - 441 USART_ITConfig: - 442 .LFB35: - 366:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 367:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 368:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 369:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 370:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Enables or disables the specified USART interrupts. - 371:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 372:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 373:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 374:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - 375:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 376:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - 377:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_LBD: LIN Break detection interrupt - 378:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_TXE: Transmit Data Register empty interrupt - 379:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_TC: Transmission complete interrupt - 380:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_RXNE: Receive Data register not empty interrupt - 381:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_IDLE: Idle line detection interrupt - 382:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_PE: Parity Error interrupt - 383:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - 384:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param NewState: new state of the specified USARTx interrupts. - 385:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be: ENABLE or DISABLE. - 386:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 387:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 388:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) - 389:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 443 .loc 1 389 0 - 444 .cfi_startproc - 445 @ args = 0, pretend = 0, frame = 0 - 446 @ frame_needed = 0, uses_anonymous_args = 0 - 447 @ link register save eliminated. - 448 .LVL59: - 449 0000 10B4 push {r4} - 450 .cfi_def_cfa_offset 4 - 451 .cfi_offset 4, -4 - 452 .LVL60: - 390:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - 391:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** uint32_t usartxbase = 0x00; - 392:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 393:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 394:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_CONFIG_IT(USART_IT)); - 395:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 396:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* The CTS interrupt is not available for UART4 and UART5 */ - 397:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (USART_IT == USART_IT_CTS) - 398:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 399:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_123_PERIPH(USARTx)); - 400:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 401:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 402:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** usartxbase = (uint32_t)USARTx; - 403:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 404:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Get the USART register index */ - 405:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** usartreg = (((uint8_t)USART_IT) >> 0x05); - 453 .loc 1 405 0 - 454 0002 C1F34214 ubfx r4, r1, #5, #3 - 455 .LVL61: - 406:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 407:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Get the interrupt position */ - 408:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** itpos = USART_IT & IT_Mask; - 409:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** itmask = (((uint32_t)0x01) << itpos); - 456 .loc 1 409 0 - 457 0006 01F01F01 and r1, r1, #31 - 458 .LVL62: - 459 000a 0123 movs r3, #1 - 460 000c 8B40 lsls r3, r3, r1 - 461 .LVL63: - 410:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 411:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (usartreg == 0x01) /* The IT is in CR1 register */ - 462 .loc 1 411 0 - 463 000e 012C cmp r4, #1 - 464 0010 01D1 bne .L28 - 412:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 413:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** usartxbase += 0x0C; - 465 .loc 1 413 0 - 466 0012 0C30 adds r0, r0, #12 - 467 .LVL64: - 468 0014 03E0 b .L29 - 469 .LVL65: - 470 .L28: - 414:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 415:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else if (usartreg == 0x02) /* The IT is in CR2 register */ - 471 .loc 1 415 0 - 472 0016 022C cmp r4, #2 - 416:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 417:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** usartxbase += 0x10; - 473 .loc 1 417 0 - 474 0018 0CBF ite eq - 475 001a 1030 addeq r0, r0, #16 - 476 .LVL66: - 418:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 419:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else /* The IT is in CR3 register */ - 420:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 421:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** usartxbase += 0x14; - 477 .loc 1 421 0 - 478 001c 1430 addne r0, r0, #20 - 479 .LVL67: - 480 .L29: - 422:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 423:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (NewState != DISABLE) - 481 .loc 1 423 0 - 482 001e 1AB1 cbz r2, .L31 - 424:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 425:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** *(__IO uint32_t*)usartxbase |= itmask; - 483 .loc 1 425 0 - 484 0020 0268 ldr r2, [r0] - 485 .LVL68: - 486 0022 1343 orrs r3, r3, r2 - 487 .LVL69: - 488 0024 0360 str r3, [r0] - 489 0026 03E0 b .L27 - 490 .LVL70: - 491 .L31: - 426:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 427:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 428:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 429:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** *(__IO uint32_t*)usartxbase &= ~itmask; - 492 .loc 1 429 0 - 493 0028 0268 ldr r2, [r0] - 494 .LVL71: - 495 002a 22EA0303 bic r3, r2, r3 - 496 .LVL72: - 497 002e 0360 str r3, [r0] - 498 .L27: - 430:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 431:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 499 .loc 1 431 0 - 500 0030 5DF8044B ldr r4, [sp], #4 - 501 .cfi_restore 4 - 502 .cfi_def_cfa_offset 0 - 503 .LVL73: - 504 0034 7047 bx lr - 505 .cfi_endproc - 506 .LFE35: - 508 0036 00BF .section .text.USART_DMACmd,"ax",%progbits - 509 .align 2 - 510 .global USART_DMACmd - 511 .thumb - 512 .thumb_func - 514 USART_DMACmd: - 515 .LFB36: - 432:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 433:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 434:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Enables or disables the USART’s DMA interface. - 435:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 436:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 437:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 438:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_DMAReq: specifies the DMA request. - 439:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be any combination of the following values: - 440:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_DMAReq_Tx: USART DMA transmit request - 441:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_DMAReq_Rx: USART DMA receive request - 442:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param NewState: new state of the DMA Request sources. - 443:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be: ENABLE or DISABLE. - 444:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @note The DMA mode is not available for UART5 except in the STM32 - 445:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * High density value line devices(STM32F10X_HD_VL). - 446:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 447:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 448:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) - 449:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 516 .loc 1 449 0 - 517 .cfi_startproc - 518 @ args = 0, pretend = 0, frame = 0 - 519 @ frame_needed = 0, uses_anonymous_args = 0 - 520 @ link register save eliminated. - 521 .LVL74: - 450:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 451:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 452:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_DMAREQ(USART_DMAReq)); - 453:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 454:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (NewState != DISABLE) - 522 .loc 1 454 0 - 523 0000 22B1 cbz r2, .L35 - 455:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 456:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Enable the DMA transfer for selected requests by setting the DMAT and/or - 457:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** DMAR bits in the USART CR3 register */ - 458:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 |= USART_DMAReq; - 524 .loc 1 458 0 - 525 0002 838A ldrh r3, [r0, #20] - 526 0004 9BB2 uxth r3, r3 - 527 0006 1943 orrs r1, r1, r3 - 528 .LVL75: - 529 0008 8182 strh r1, [r0, #20] @ movhi - 530 000a 7047 bx lr - 531 .LVL76: - 532 .L35: - 459:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 460:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 461:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 462:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - 463:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** DMAR bits in the USART CR3 register */ - 464:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 &= (uint16_t)~USART_DMAReq; - 533 .loc 1 464 0 - 534 000c 838A ldrh r3, [r0, #20] - 535 000e 9BB2 uxth r3, r3 - 536 0010 23EA0101 bic r1, r3, r1 - 537 .LVL77: - 538 0014 8182 strh r1, [r0, #20] @ movhi - 539 0016 7047 bx lr - 540 .cfi_endproc - 541 .LFE36: - 543 .section .text.USART_SetAddress,"ax",%progbits - 544 .align 2 - 545 .global USART_SetAddress - 546 .thumb - 547 .thumb_func - 549 USART_SetAddress: - 550 .LFB37: - 465:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 466:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 467:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 468:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 469:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Sets the address of the USART node. - 470:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 471:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 472:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 473:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_Address: Indicates the address of the USART node. - 474:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 475:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 476:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) - 477:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 551 .loc 1 477 0 - 552 .cfi_startproc - 553 @ args = 0, pretend = 0, frame = 0 - 554 @ frame_needed = 0, uses_anonymous_args = 0 - 555 @ link register save eliminated. - 556 .LVL78: - 478:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 479:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 480:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ADDRESS(USART_Address)); - 481:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 482:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Clear the USART address */ - 483:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR2 &= CR2_Address_Mask; - 557 .loc 1 483 0 - 558 0000 038A ldrh r3, [r0, #16] - 559 0002 23F00F03 bic r3, r3, #15 - 560 0006 1B04 lsls r3, r3, #16 - 561 0008 1B0C lsrs r3, r3, #16 - 562 000a 0382 strh r3, [r0, #16] @ movhi - 484:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Set the USART address node */ - 485:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR2 |= USART_Address; - 563 .loc 1 485 0 - 564 000c 038A ldrh r3, [r0, #16] - 565 000e 9BB2 uxth r3, r3 - 566 0010 1943 orrs r1, r1, r3 - 567 .LVL79: - 568 0012 0182 strh r1, [r0, #16] @ movhi - 569 0014 7047 bx lr - 570 .cfi_endproc - 571 .LFE37: - 573 0016 00BF .section .text.USART_WakeUpConfig,"ax",%progbits - 574 .align 2 - 575 .global USART_WakeUpConfig - 576 .thumb - 577 .thumb_func - 579 USART_WakeUpConfig: - 580 .LFB38: - 486:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 487:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 488:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 489:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Selects the USART WakeUp method. - 490:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 491:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 492:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 493:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_WakeUp: specifies the USART wakeup method. - 494:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 495:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - 496:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - 497:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 498:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 499:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) - 500:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 581 .loc 1 500 0 - 582 .cfi_startproc - 583 @ args = 0, pretend = 0, frame = 0 - 584 @ frame_needed = 0, uses_anonymous_args = 0 - 585 @ link register save eliminated. - 586 .LVL80: - 501:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 502:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 503:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_WAKEUP(USART_WakeUp)); - 504:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 505:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR1 &= CR1_WAKE_Mask; - 587 .loc 1 505 0 - 588 0000 8389 ldrh r3, [r0, #12] - 589 0002 23F40063 bic r3, r3, #2048 - 590 0006 1B04 lsls r3, r3, #16 - 591 0008 1B0C lsrs r3, r3, #16 - 592 000a 8381 strh r3, [r0, #12] @ movhi - 506:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR1 |= USART_WakeUp; - 593 .loc 1 506 0 - 594 000c 8389 ldrh r3, [r0, #12] - 595 000e 9BB2 uxth r3, r3 - 596 0010 1943 orrs r1, r1, r3 - 597 .LVL81: - 598 0012 8181 strh r1, [r0, #12] @ movhi - 599 0014 7047 bx lr - 600 .cfi_endproc - 601 .LFE38: - 603 0016 00BF .section .text.USART_ReceiverWakeUpCmd,"ax",%progbits - 604 .align 2 - 605 .global USART_ReceiverWakeUpCmd - 606 .thumb - 607 .thumb_func - 609 USART_ReceiverWakeUpCmd: - 610 .LFB39: - 507:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 508:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 509:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 510:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Determines if the USART is in mute mode or not. - 511:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 512:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 513:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 514:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param NewState: new state of the USART mute mode. - 515:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be: ENABLE or DISABLE. - 516:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 517:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 518:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) - 519:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 611 .loc 1 519 0 - 612 .cfi_startproc - 613 @ args = 0, pretend = 0, frame = 0 - 614 @ frame_needed = 0, uses_anonymous_args = 0 - 615 @ link register save eliminated. - 616 .LVL82: - 520:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 521:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 522:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 523:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 524:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (NewState != DISABLE) - 617 .loc 1 524 0 - 618 0000 29B1 cbz r1, .L40 - 525:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 526:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - 527:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR1 |= CR1_RWU_Set; - 619 .loc 1 527 0 - 620 0002 8389 ldrh r3, [r0, #12] - 621 0004 9BB2 uxth r3, r3 - 622 0006 43F00203 orr r3, r3, #2 - 623 000a 8381 strh r3, [r0, #12] @ movhi - 624 000c 7047 bx lr - 625 .L40: - 528:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 529:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 530:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 531:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - 532:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR1 &= CR1_RWU_Reset; - 626 .loc 1 532 0 - 627 000e 8389 ldrh r3, [r0, #12] - 628 0010 23F00203 bic r3, r3, #2 - 629 0014 1B04 lsls r3, r3, #16 - 630 0016 1B0C lsrs r3, r3, #16 - 631 0018 8381 strh r3, [r0, #12] @ movhi - 632 001a 7047 bx lr - 633 .cfi_endproc - 634 .LFE39: - 636 .section .text.USART_LINBreakDetectLengthConfig,"ax",%progbits - 637 .align 2 - 638 .global USART_LINBreakDetectLengthConfig - 639 .thumb - 640 .thumb_func - 642 USART_LINBreakDetectLengthConfig: - 643 .LFB40: - 533:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 534:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 535:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 536:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 537:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Sets the USART LIN Break detection length. - 538:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 539:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 540:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 541:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - 542:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 543:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - 544:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - 545:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 546:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 547:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) - 548:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 644 .loc 1 548 0 - 645 .cfi_startproc - 646 @ args = 0, pretend = 0, frame = 0 - 647 @ frame_needed = 0, uses_anonymous_args = 0 - 648 @ link register save eliminated. - 649 .LVL83: - 549:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 550:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 551:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - 552:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 553:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR2 &= CR2_LBDL_Mask; - 650 .loc 1 553 0 - 651 0000 038A ldrh r3, [r0, #16] - 652 0002 23F02003 bic r3, r3, #32 - 653 0006 1B04 lsls r3, r3, #16 - 654 0008 1B0C lsrs r3, r3, #16 - 655 000a 0382 strh r3, [r0, #16] @ movhi - 554:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR2 |= USART_LINBreakDetectLength; - 656 .loc 1 554 0 - 657 000c 038A ldrh r3, [r0, #16] - 658 000e 9BB2 uxth r3, r3 - 659 0010 1943 orrs r1, r1, r3 - 660 .LVL84: - 661 0012 0182 strh r1, [r0, #16] @ movhi - 662 0014 7047 bx lr - 663 .cfi_endproc - 664 .LFE40: - 666 0016 00BF .section .text.USART_LINCmd,"ax",%progbits - 667 .align 2 - 668 .global USART_LINCmd - 669 .thumb - 670 .thumb_func - 672 USART_LINCmd: - 673 .LFB41: - 555:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 556:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 557:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 558:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Enables or disables the USART’s LIN mode. - 559:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 560:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 561:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 562:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param NewState: new state of the USART LIN mode. - 563:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be: ENABLE or DISABLE. - 564:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 565:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 566:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) - 567:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 674 .loc 1 567 0 - 675 .cfi_startproc - 676 @ args = 0, pretend = 0, frame = 0 - 677 @ frame_needed = 0, uses_anonymous_args = 0 - 678 @ link register save eliminated. - 679 .LVL85: - 568:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 569:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 570:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 571:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 572:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (NewState != DISABLE) - 680 .loc 1 572 0 - 681 0000 29B1 cbz r1, .L44 - 573:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 574:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - 575:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR2 |= CR2_LINEN_Set; - 682 .loc 1 575 0 - 683 0002 038A ldrh r3, [r0, #16] - 684 0004 9BB2 uxth r3, r3 - 685 0006 43F48043 orr r3, r3, #16384 - 686 000a 0382 strh r3, [r0, #16] @ movhi - 687 000c 7047 bx lr - 688 .L44: - 576:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 577:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 578:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 579:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - 580:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR2 &= CR2_LINEN_Reset; - 689 .loc 1 580 0 - 690 000e 038A ldrh r3, [r0, #16] - 691 0010 23F48043 bic r3, r3, #16384 - 692 0014 1B04 lsls r3, r3, #16 - 693 0016 1B0C lsrs r3, r3, #16 - 694 0018 0382 strh r3, [r0, #16] @ movhi - 695 001a 7047 bx lr - 696 .cfi_endproc - 697 .LFE41: - 699 .section .text.USART_SendData,"ax",%progbits - 700 .align 2 - 701 .global USART_SendData - 702 .thumb - 703 .thumb_func - 705 USART_SendData: - 706 .LFB42: - 581:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 582:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 583:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 584:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 585:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Transmits single data through the USARTx peripheral. - 586:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 587:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 588:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 589:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param Data: the data to transmit. - 590:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 591:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 592:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) - 593:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 707 .loc 1 593 0 - 708 .cfi_startproc - 709 @ args = 0, pretend = 0, frame = 0 - 710 @ frame_needed = 0, uses_anonymous_args = 0 - 711 @ link register save eliminated. - 712 .LVL86: - 594:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 595:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 596:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_DATA(Data)); - 597:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 598:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Transmit Data */ - 599:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->DR = (Data & (uint16_t)0x01FF); - 713 .loc 1 599 0 - 714 0000 C1F30801 ubfx r1, r1, #0, #9 - 715 .LVL87: - 716 0004 8180 strh r1, [r0, #4] @ movhi - 717 0006 7047 bx lr - 718 .cfi_endproc - 719 .LFE42: - 721 .section .text.USART_ReceiveData,"ax",%progbits - 722 .align 2 - 723 .global USART_ReceiveData - 724 .thumb - 725 .thumb_func - 727 USART_ReceiveData: - 728 .LFB43: - 600:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 601:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 602:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 603:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Returns the most recent received data by the USARTx peripheral. - 604:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 605:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 606:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 607:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval The received data. - 608:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 609:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** uint16_t USART_ReceiveData(USART_TypeDef* USARTx) - 610:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 729 .loc 1 610 0 - 730 .cfi_startproc - 731 @ args = 0, pretend = 0, frame = 0 - 732 @ frame_needed = 0, uses_anonymous_args = 0 - 733 @ link register save eliminated. - 734 .LVL88: - 611:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 612:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 613:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 614:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Receive Data */ - 615:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); - 735 .loc 1 615 0 - 736 0000 8088 ldrh r0, [r0, #4] - 737 .LVL89: - 616:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 738 .loc 1 616 0 - 739 0002 C0F30800 ubfx r0, r0, #0, #9 - 740 0006 7047 bx lr - 741 .cfi_endproc - 742 .LFE43: - 744 .section .text.USART_SendBreak,"ax",%progbits - 745 .align 2 - 746 .global USART_SendBreak - 747 .thumb - 748 .thumb_func - 750 USART_SendBreak: - 751 .LFB44: - 617:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 618:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 619:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Transmits break characters. - 620:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 621:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 622:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 623:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 624:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 625:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_SendBreak(USART_TypeDef* USARTx) - 626:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 752 .loc 1 626 0 - 753 .cfi_startproc - 754 @ args = 0, pretend = 0, frame = 0 - 755 @ frame_needed = 0, uses_anonymous_args = 0 - 756 @ link register save eliminated. - 757 .LVL90: - 627:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 628:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 629:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 630:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Send break characters */ - 631:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR1 |= CR1_SBK_Set; - 758 .loc 1 631 0 - 759 0000 8389 ldrh r3, [r0, #12] - 760 0002 9BB2 uxth r3, r3 - 761 0004 43F00103 orr r3, r3, #1 - 762 0008 8381 strh r3, [r0, #12] @ movhi - 763 000a 7047 bx lr - 764 .cfi_endproc - 765 .LFE44: - 767 .section .text.USART_SetGuardTime,"ax",%progbits - 768 .align 2 - 769 .global USART_SetGuardTime - 770 .thumb - 771 .thumb_func - 773 USART_SetGuardTime: - 774 .LFB45: - 632:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 633:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 634:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 635:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Sets the specified USART guard time. - 636:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - 637:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_GuardTime: specifies the guard time. - 638:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @note The guard time bits are not available for UART4 and UART5. - 639:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 640:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 641:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) - 642:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 775 .loc 1 642 0 - 776 .cfi_startproc - 777 @ args = 0, pretend = 0, frame = 0 - 778 @ frame_needed = 0, uses_anonymous_args = 0 - 779 @ link register save eliminated. - 780 .LVL91: - 643:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 644:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_123_PERIPH(USARTx)); - 645:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 646:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Clear the USART Guard time */ - 647:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->GTPR &= GTPR_LSB_Mask; - 781 .loc 1 647 0 - 782 0000 038B ldrh r3, [r0, #24] - 783 0002 DBB2 uxtb r3, r3 - 784 0004 0383 strh r3, [r0, #24] @ movhi - 648:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Set the USART guard time */ - 649:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); - 785 .loc 1 649 0 - 786 0006 038B ldrh r3, [r0, #24] - 787 0008 9BB2 uxth r3, r3 - 788 000a 43EA0121 orr r1, r3, r1, lsl #8 - 789 .LVL92: - 790 000e 0183 strh r1, [r0, #24] @ movhi - 791 0010 7047 bx lr - 792 .cfi_endproc - 793 .LFE45: - 795 0012 00BF .section .text.USART_SetPrescaler,"ax",%progbits - 796 .align 2 - 797 .global USART_SetPrescaler - 798 .thumb - 799 .thumb_func - 801 USART_SetPrescaler: - 802 .LFB46: - 650:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 651:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 652:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 653:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Sets the system clock prescaler. - 654:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 655:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 656:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 657:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_Prescaler: specifies the prescaler clock. - 658:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @note The function is used for IrDA mode with UART4 and UART5. - 659:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 660:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 661:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) - 662:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 803 .loc 1 662 0 - 804 .cfi_startproc - 805 @ args = 0, pretend = 0, frame = 0 - 806 @ frame_needed = 0, uses_anonymous_args = 0 - 807 @ link register save eliminated. - 808 .LVL93: - 663:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 664:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 665:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 666:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Clear the USART prescaler */ - 667:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->GTPR &= GTPR_MSB_Mask; - 809 .loc 1 667 0 - 810 0000 038B ldrh r3, [r0, #24] - 811 0002 03F47F43 and r3, r3, #65280 - 812 0006 0383 strh r3, [r0, #24] @ movhi - 668:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Set the USART prescaler */ - 669:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->GTPR |= USART_Prescaler; - 813 .loc 1 669 0 - 814 0008 038B ldrh r3, [r0, #24] - 815 000a 9BB2 uxth r3, r3 - 816 000c 1943 orrs r1, r1, r3 - 817 .LVL94: - 818 000e 0183 strh r1, [r0, #24] @ movhi - 819 0010 7047 bx lr - 820 .cfi_endproc - 821 .LFE46: - 823 0012 00BF .section .text.USART_SmartCardCmd,"ax",%progbits - 824 .align 2 - 825 .global USART_SmartCardCmd - 826 .thumb - 827 .thumb_func - 829 USART_SmartCardCmd: - 830 .LFB47: - 670:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 671:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 672:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 673:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Enables or disables the USART’s Smart Card mode. - 674:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - 675:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param NewState: new state of the Smart Card mode. - 676:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be: ENABLE or DISABLE. - 677:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @note The Smart Card mode is not available for UART4 and UART5. - 678:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 679:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 680:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) - 681:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 831 .loc 1 681 0 - 832 .cfi_startproc - 833 @ args = 0, pretend = 0, frame = 0 - 834 @ frame_needed = 0, uses_anonymous_args = 0 - 835 @ link register save eliminated. - 836 .LVL95: - 682:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 683:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_123_PERIPH(USARTx)); - 684:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 685:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (NewState != DISABLE) - 837 .loc 1 685 0 - 838 0000 29B1 cbz r1, .L52 - 686:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 687:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - 688:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 |= CR3_SCEN_Set; - 839 .loc 1 688 0 - 840 0002 838A ldrh r3, [r0, #20] - 841 0004 9BB2 uxth r3, r3 - 842 0006 43F02003 orr r3, r3, #32 - 843 000a 8382 strh r3, [r0, #20] @ movhi - 844 000c 7047 bx lr - 845 .L52: - 689:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 690:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 691:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 692:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - 693:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 &= CR3_SCEN_Reset; - 846 .loc 1 693 0 - 847 000e 838A ldrh r3, [r0, #20] - 848 0010 23F02003 bic r3, r3, #32 - 849 0014 1B04 lsls r3, r3, #16 - 850 0016 1B0C lsrs r3, r3, #16 - 851 0018 8382 strh r3, [r0, #20] @ movhi - 852 001a 7047 bx lr - 853 .cfi_endproc - 854 .LFE47: - 856 .section .text.USART_SmartCardNACKCmd,"ax",%progbits - 857 .align 2 - 858 .global USART_SmartCardNACKCmd - 859 .thumb - 860 .thumb_func - 862 USART_SmartCardNACKCmd: - 863 .LFB48: - 694:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 695:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 696:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 697:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 698:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Enables or disables NACK transmission. - 699:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - 700:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param NewState: new state of the NACK transmission. - 701:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be: ENABLE or DISABLE. - 702:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @note The Smart Card mode is not available for UART4 and UART5. - 703:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 704:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 705:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) - 706:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 864 .loc 1 706 0 - 865 .cfi_startproc - 866 @ args = 0, pretend = 0, frame = 0 - 867 @ frame_needed = 0, uses_anonymous_args = 0 - 868 @ link register save eliminated. - 869 .LVL96: - 707:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 708:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_123_PERIPH(USARTx)); - 709:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 710:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (NewState != DISABLE) - 870 .loc 1 710 0 - 871 0000 29B1 cbz r1, .L55 - 711:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 712:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - 713:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 |= CR3_NACK_Set; - 872 .loc 1 713 0 - 873 0002 838A ldrh r3, [r0, #20] - 874 0004 9BB2 uxth r3, r3 - 875 0006 43F01003 orr r3, r3, #16 - 876 000a 8382 strh r3, [r0, #20] @ movhi - 877 000c 7047 bx lr - 878 .L55: - 714:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 715:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 716:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 717:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - 718:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 &= CR3_NACK_Reset; - 879 .loc 1 718 0 - 880 000e 838A ldrh r3, [r0, #20] - 881 0010 23F01003 bic r3, r3, #16 - 882 0014 1B04 lsls r3, r3, #16 - 883 0016 1B0C lsrs r3, r3, #16 - 884 0018 8382 strh r3, [r0, #20] @ movhi - 885 001a 7047 bx lr - 886 .cfi_endproc - 887 .LFE48: - 889 .section .text.USART_HalfDuplexCmd,"ax",%progbits - 890 .align 2 - 891 .global USART_HalfDuplexCmd - 892 .thumb - 893 .thumb_func - 895 USART_HalfDuplexCmd: - 896 .LFB49: - 719:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 720:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 721:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 722:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 723:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Enables or disables the USART’s Half Duplex communication. - 724:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 725:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 726:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 727:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param NewState: new state of the USART Communication. - 728:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be: ENABLE or DISABLE. - 729:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 730:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 731:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) - 732:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 897 .loc 1 732 0 - 898 .cfi_startproc - 899 @ args = 0, pretend = 0, frame = 0 - 900 @ frame_needed = 0, uses_anonymous_args = 0 - 901 @ link register save eliminated. - 902 .LVL97: - 733:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 734:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 735:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 736:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 737:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (NewState != DISABLE) - 903 .loc 1 737 0 - 904 0000 29B1 cbz r1, .L58 - 738:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 739:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - 740:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 |= CR3_HDSEL_Set; - 905 .loc 1 740 0 - 906 0002 838A ldrh r3, [r0, #20] - 907 0004 9BB2 uxth r3, r3 - 908 0006 43F00803 orr r3, r3, #8 - 909 000a 8382 strh r3, [r0, #20] @ movhi - 910 000c 7047 bx lr - 911 .L58: - 741:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 742:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 743:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 744:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - 745:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 &= CR3_HDSEL_Reset; - 912 .loc 1 745 0 - 913 000e 838A ldrh r3, [r0, #20] - 914 0010 23F00803 bic r3, r3, #8 - 915 0014 1B04 lsls r3, r3, #16 - 916 0016 1B0C lsrs r3, r3, #16 - 917 0018 8382 strh r3, [r0, #20] @ movhi - 918 001a 7047 bx lr - 919 .cfi_endproc - 920 .LFE49: - 922 .section .text.USART_OverSampling8Cmd,"ax",%progbits - 923 .align 2 - 924 .global USART_OverSampling8Cmd - 925 .thumb - 926 .thumb_func - 928 USART_OverSampling8Cmd: - 929 .LFB50: - 746:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 747:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 748:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 749:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 750:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 751:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Enables or disables the USART's 8x oversampling mode. - 752:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 753:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 754:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 755:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param NewState: new state of the USART one bit sampling method. - 756:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be: ENABLE or DISABLE. - 757:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @note - 758:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This function has to be called before calling USART_Init() - 759:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * function in order to have correct baudrate Divider value. - 760:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 761:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 762:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) - 763:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 930 .loc 1 763 0 - 931 .cfi_startproc - 932 @ args = 0, pretend = 0, frame = 0 - 933 @ frame_needed = 0, uses_anonymous_args = 0 - 934 @ link register save eliminated. - 935 .LVL98: - 764:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 765:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 766:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 767:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 768:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (NewState != DISABLE) - 936 .loc 1 768 0 - 937 0000 39B1 cbz r1, .L61 - 769:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 770:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - 771:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR1 |= CR1_OVER8_Set; - 938 .loc 1 771 0 - 939 0002 8389 ldrh r3, [r0, #12] - 940 0004 6FEA4343 mvn r3, r3, lsl #17 - 941 0008 6FEA5343 mvn r3, r3, lsr #17 - 942 000c 9BB2 uxth r3, r3 - 943 000e 8381 strh r3, [r0, #12] @ movhi - 944 0010 7047 bx lr - 945 .L61: - 772:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 773:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 774:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 775:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - 776:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR1 &= CR1_OVER8_Reset; - 946 .loc 1 776 0 - 947 0012 8389 ldrh r3, [r0, #12] - 948 0014 C3F30E03 ubfx r3, r3, #0, #15 - 949 0018 8381 strh r3, [r0, #12] @ movhi - 950 001a 7047 bx lr - 951 .cfi_endproc - 952 .LFE50: - 954 .section .text.USART_OneBitMethodCmd,"ax",%progbits - 955 .align 2 - 956 .global USART_OneBitMethodCmd - 957 .thumb - 958 .thumb_func - 960 USART_OneBitMethodCmd: - 961 .LFB51: - 777:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 778:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 779:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 780:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 781:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Enables or disables the USART's one bit sampling method. - 782:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 783:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 784:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 785:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param NewState: new state of the USART one bit sampling method. - 786:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be: ENABLE or DISABLE. - 787:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 788:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 789:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) - 790:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 962 .loc 1 790 0 - 963 .cfi_startproc - 964 @ args = 0, pretend = 0, frame = 0 - 965 @ frame_needed = 0, uses_anonymous_args = 0 - 966 @ link register save eliminated. - 967 .LVL99: - 791:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 792:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 793:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 794:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 795:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (NewState != DISABLE) - 968 .loc 1 795 0 - 969 0000 29B1 cbz r1, .L64 - 796:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 797:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - 798:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 |= CR3_ONEBITE_Set; - 970 .loc 1 798 0 - 971 0002 838A ldrh r3, [r0, #20] - 972 0004 9BB2 uxth r3, r3 - 973 0006 43F40063 orr r3, r3, #2048 - 974 000a 8382 strh r3, [r0, #20] @ movhi - 975 000c 7047 bx lr - 976 .L64: - 799:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 800:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 801:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 802:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ - 803:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 &= CR3_ONEBITE_Reset; - 977 .loc 1 803 0 - 978 000e 838A ldrh r3, [r0, #20] - 979 0010 23F40063 bic r3, r3, #2048 - 980 0014 1B04 lsls r3, r3, #16 - 981 0016 1B0C lsrs r3, r3, #16 - 982 0018 8382 strh r3, [r0, #20] @ movhi - 983 001a 7047 bx lr - 984 .cfi_endproc - 985 .LFE51: - 987 .section .text.USART_IrDAConfig,"ax",%progbits - 988 .align 2 - 989 .global USART_IrDAConfig - 990 .thumb - 991 .thumb_func - 993 USART_IrDAConfig: - 994 .LFB52: - 804:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 805:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 806:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 807:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 808:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Configures the USART's IrDA interface. - 809:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 810:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 811:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 812:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_IrDAMode: specifies the IrDA mode. - 813:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 814:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IrDAMode_LowPower - 815:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IrDAMode_Normal - 816:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 817:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 818:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) - 819:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 995 .loc 1 819 0 - 996 .cfi_startproc - 997 @ args = 0, pretend = 0, frame = 0 - 998 @ frame_needed = 0, uses_anonymous_args = 0 - 999 @ link register save eliminated. - 1000 .LVL100: - 820:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 821:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 822:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - 823:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 824:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 &= CR3_IRLP_Mask; - 1001 .loc 1 824 0 - 1002 0000 838A ldrh r3, [r0, #20] - 1003 0002 23F00403 bic r3, r3, #4 - 1004 0006 1B04 lsls r3, r3, #16 - 1005 0008 1B0C lsrs r3, r3, #16 - 1006 000a 8382 strh r3, [r0, #20] @ movhi - 825:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 |= USART_IrDAMode; - 1007 .loc 1 825 0 - 1008 000c 838A ldrh r3, [r0, #20] - 1009 000e 9BB2 uxth r3, r3 - 1010 0010 1943 orrs r1, r1, r3 - 1011 .LVL101: - 1012 0012 8182 strh r1, [r0, #20] @ movhi - 1013 0014 7047 bx lr - 1014 .cfi_endproc - 1015 .LFE52: - 1017 0016 00BF .section .text.USART_IrDACmd,"ax",%progbits - 1018 .align 2 - 1019 .global USART_IrDACmd - 1020 .thumb - 1021 .thumb_func - 1023 USART_IrDACmd: - 1024 .LFB53: - 826:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 827:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 828:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 829:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Enables or disables the USART's IrDA interface. - 830:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 831:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 832:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 833:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param NewState: new state of the IrDA mode. - 834:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be: ENABLE or DISABLE. - 835:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 836:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 837:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) - 838:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 1025 .loc 1 838 0 - 1026 .cfi_startproc - 1027 @ args = 0, pretend = 0, frame = 0 - 1028 @ frame_needed = 0, uses_anonymous_args = 0 - 1029 @ link register save eliminated. - 1030 .LVL102: - 839:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 840:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 841:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_FUNCTIONAL_STATE(NewState)); - 842:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 843:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (NewState != DISABLE) - 1031 .loc 1 843 0 - 1032 0000 29B1 cbz r1, .L68 - 844:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 845:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - 846:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 |= CR3_IREN_Set; - 1033 .loc 1 846 0 - 1034 0002 838A ldrh r3, [r0, #20] - 1035 0004 9BB2 uxth r3, r3 - 1036 0006 43F00203 orr r3, r3, #2 - 1037 000a 8382 strh r3, [r0, #20] @ movhi - 1038 000c 7047 bx lr - 1039 .L68: - 847:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 848:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 849:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 850:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - 851:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->CR3 &= CR3_IREN_Reset; - 1040 .loc 1 851 0 - 1041 000e 838A ldrh r3, [r0, #20] - 1042 0010 23F00203 bic r3, r3, #2 - 1043 0014 1B04 lsls r3, r3, #16 - 1044 0016 1B0C lsrs r3, r3, #16 - 1045 0018 8382 strh r3, [r0, #20] @ movhi - 1046 001a 7047 bx lr - 1047 .cfi_endproc - 1048 .LFE53: - 1050 .section .text.USART_GetFlagStatus,"ax",%progbits - 1051 .align 2 - 1052 .global USART_GetFlagStatus - 1053 .thumb - 1054 .thumb_func - 1056 USART_GetFlagStatus: - 1057 .LFB54: - 852:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 853:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 854:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 855:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 856:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Checks whether the specified USART flag is set or not. - 857:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 858:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 859:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 860:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_FLAG: specifies the flag to check. - 861:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 862:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - 863:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_LBD: LIN Break detection flag - 864:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_TXE: Transmit data register empty flag - 865:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_TC: Transmission Complete flag - 866:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_RXNE: Receive data register not empty flag - 867:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_IDLE: Idle Line detection flag - 868:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_ORE: OverRun Error flag - 869:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_NE: Noise Error flag - 870:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_FE: Framing Error flag - 871:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_PE: Parity Error flag - 872:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval The new state of USART_FLAG (SET or RESET). - 873:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 874:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) - 875:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 1058 .loc 1 875 0 - 1059 .cfi_startproc - 1060 @ args = 0, pretend = 0, frame = 0 - 1061 @ frame_needed = 0, uses_anonymous_args = 0 - 1062 @ link register save eliminated. - 1063 .LVL103: - 876:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** FlagStatus bitstatus = RESET; - 877:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 878:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 879:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_FLAG(USART_FLAG)); - 880:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* The CTS flag is not available for UART4 and UART5 */ - 881:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (USART_FLAG == USART_FLAG_CTS) - 882:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 883:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_123_PERIPH(USARTx)); - 884:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 885:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 886:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) - 1064 .loc 1 886 0 - 1065 0000 0388 ldrh r3, [r0] - 1066 .LVL104: - 1067 0002 1942 tst r1, r3 - 887:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 888:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** bitstatus = SET; - 889:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 890:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 891:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 892:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** bitstatus = RESET; - 893:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 894:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** return bitstatus; - 895:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 1068 .loc 1 895 0 - 1069 0004 14BF ite ne - 1070 0006 0120 movne r0, #1 - 1071 .LVL105: - 1072 0008 0020 moveq r0, #0 - 1073 000a 7047 bx lr - 1074 .cfi_endproc - 1075 .LFE54: - 1077 .section .text.USART_ClearFlag,"ax",%progbits - 1078 .align 2 - 1079 .global USART_ClearFlag - 1080 .thumb - 1081 .thumb_func - 1083 USART_ClearFlag: - 1084 .LFB55: - 896:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 897:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 898:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Clears the USARTx's pending flags. - 899:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 900:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 901:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 902:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_FLAG: specifies the flag to clear. - 903:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be any combination of the following values: - 904:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - 905:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_LBD: LIN Break detection flag. - 906:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_TC: Transmission Complete flag. - 907:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_FLAG_RXNE: Receive data register not empty flag. - 908:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * - 909:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @note - 910:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - 911:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * error) and IDLE (Idle line detected) flags are cleared by software - 912:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) - 913:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * followed by a read operation to USART_DR register (USART_ReceiveData()). - 914:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * - RXNE flag can be also cleared by a read to the USART_DR register - 915:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * (USART_ReceiveData()). - 916:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * - TC flag can be also cleared by software sequence: a read operation to - 917:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART_SR register (USART_GetFlagStatus()) followed by a write operation - 918:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * to USART_DR register (USART_SendData()). - 919:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * - TXE flag is cleared only by a write to the USART_DR register - 920:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * (USART_SendData()). - 921:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None - 922:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 923:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) - 924:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 1085 .loc 1 924 0 - 1086 .cfi_startproc - 1087 @ args = 0, pretend = 0, frame = 0 - 1088 @ frame_needed = 0, uses_anonymous_args = 0 - 1089 @ link register save eliminated. - 1090 .LVL106: - 925:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 926:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 927:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - 928:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* The CTS flag is not available for UART4 and UART5 */ - 929:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) - 930:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 931:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_123_PERIPH(USARTx)); - 932:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 933:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 934:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->SR = (uint16_t)~USART_FLAG; - 1091 .loc 1 934 0 - 1092 0000 C943 mvns r1, r1 - 1093 .LVL107: - 1094 0002 89B2 uxth r1, r1 - 1095 0004 0180 strh r1, [r0] @ movhi - 1096 0006 7047 bx lr - 1097 .cfi_endproc - 1098 .LFE55: - 1100 .section .text.USART_GetITStatus,"ax",%progbits - 1101 .align 2 - 1102 .global USART_GetITStatus - 1103 .thumb - 1104 .thumb_func - 1106 USART_GetITStatus: - 1107 .LFB56: - 935:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 936:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 937:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** - 938:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Checks whether the specified USART interrupt has occurred or not. - 939:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. - 940:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 941:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. - 942:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_IT: specifies the USART interrupt source to check. - 943:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: - 944:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - 945:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_LBD: LIN Break detection interrupt - 946:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_TXE: Tansmit Data Register empty interrupt - 947:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_TC: Transmission complete interrupt - 948:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_RXNE: Receive Data register not empty interrupt - 949:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_IDLE: Idle line detection interrupt - 950:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_ORE: OverRun Error interrupt - 951:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_NE: Noise Error interrupt - 952:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_FE: Framing Error interrupt - 953:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_PE: Parity Error interrupt - 954:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval The new state of USART_IT (SET or RESET). - 955:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ - 956:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) - 957:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 1108 .loc 1 957 0 - 1109 .cfi_startproc - 1110 @ args = 0, pretend = 0, frame = 0 - 1111 @ frame_needed = 0, uses_anonymous_args = 0 - 1112 @ link register save eliminated. - 1113 .LVL108: - 1114 0000 10B4 push {r4} - 1115 .cfi_def_cfa_offset 4 - 1116 .cfi_offset 4, -4 - 1117 .LVL109: - 958:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - 959:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** ITStatus bitstatus = RESET; - 960:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ - 961:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); - 962:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_GET_IT(USART_IT)); - 963:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* The CTS interrupt is not available for UART4 and UART5 */ - 964:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (USART_IT == USART_IT_CTS) - 965:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 966:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_123_PERIPH(USARTx)); - 967:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 968:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 969:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Get the USART register index */ - 970:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** usartreg = (((uint8_t)USART_IT) >> 0x05); - 1118 .loc 1 970 0 - 1119 0002 C1F34212 ubfx r2, r1, #5, #3 - 1120 .LVL110: - 971:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Get the interrupt position */ - 972:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** itmask = USART_IT & IT_Mask; - 973:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** itmask = (uint32_t)0x01 << itmask; - 1121 .loc 1 973 0 - 1122 0006 01F01F04 and r4, r1, #31 - 1123 000a 0123 movs r3, #1 - 1124 000c A340 lsls r3, r3, r4 - 1125 .LVL111: - 974:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 975:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (usartreg == 0x01) /* The IT is in CR1 register */ - 1126 .loc 1 975 0 - 1127 000e 012A cmp r2, #1 - 1128 0010 03D1 bne .L73 - 976:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 977:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** itmask &= USARTx->CR1; - 1129 .loc 1 977 0 - 1130 0012 8289 ldrh r2, [r0, #12] - 1131 .LVL112: - 1132 0014 92B2 uxth r2, r2 - 1133 0016 1340 ands r3, r3, r2 - 1134 .LVL113: - 1135 0018 05E0 b .L74 - 1136 .LVL114: - 1137 .L73: - 978:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 979:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else if (usartreg == 0x02) /* The IT is in CR2 register */ - 1138 .loc 1 979 0 - 1139 001a 022A cmp r2, #2 - 980:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 981:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** itmask &= USARTx->CR2; - 1140 .loc 1 981 0 - 1141 001c 0CBF ite eq - 1142 001e 028A ldrheq r2, [r0, #16] - 1143 .LVL115: - 982:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 983:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else /* The IT is in CR3 register */ - 984:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 985:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** itmask &= USARTx->CR3; - 1144 .loc 1 985 0 - 1145 0020 828A ldrhne r2, [r0, #20] - 1146 0022 92B2 uxth r2, r2 - 1147 0024 1340 ands r3, r3, r2 - 1148 .LVL116: - 1149 .L74: - 986:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 987:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** - 988:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** bitpos = USART_IT >> 0x08; - 989:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** bitpos = (uint32_t)0x01 << bitpos; - 990:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** bitpos &= USARTx->SR; - 1150 .loc 1 990 0 - 1151 0026 0288 ldrh r2, [r0] - 1152 0028 92B2 uxth r2, r2 - 1153 .LVL117: - 991:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - 1154 .loc 1 991 0 - 1155 002a 3BB1 cbz r3, .L77 - 989:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** bitpos &= USARTx->SR; - 1156 .loc 1 989 0 discriminator 1 - 1157 002c 090A lsrs r1, r1, #8 - 1158 .LVL118: - 1159 002e 0123 movs r3, #1 - 1160 .LVL119: - 1161 0030 8B40 lsls r3, r3, r1 - 1162 .loc 1 991 0 discriminator 1 - 1163 0032 1342 tst r3, r2 - 992:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 993:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** bitstatus = SET; - 1164 .loc 1 993 0 discriminator 1 - 1165 0034 14BF ite ne - 1166 0036 0120 movne r0, #1 - 1167 .LVL120: - 1168 0038 0020 moveq r0, #0 - 1169 003a 00E0 b .L76 - 1170 .LVL121: - 1171 .L77: - 994:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 995:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** else - 996:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 997:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** bitstatus = RESET; - 1172 .loc 1 997 0 - 1173 003c 0020 movs r0, #0 - 1174 .LVL122: - 1175 .L76: - 998:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 999:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** -1000:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** return bitstatus; -1001:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } - 1176 .loc 1 1001 0 - 1177 003e 5DF8044B ldr r4, [sp], #4 - 1178 .cfi_restore 4 - 1179 .cfi_def_cfa_offset 0 - 1180 0042 7047 bx lr - 1181 .cfi_endproc - 1182 .LFE56: - 1184 .section .text.USART_ClearITPendingBit,"ax",%progbits - 1185 .align 2 - 1186 .global USART_ClearITPendingBit - 1187 .thumb - 1188 .thumb_func - 1190 USART_ClearITPendingBit: - 1191 .LFB57: -1002:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** -1003:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /** -1004:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @brief Clears the USARTx's interrupt pending bits. -1005:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USARTx: Select the USART or the UART peripheral. -1006:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: -1007:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * USART1, USART2, USART3, UART4 or UART5. -1008:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @param USART_IT: specifies the interrupt pending bit to clear. -1009:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * This parameter can be one of the following values: -1010:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) -1011:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_LBD: LIN Break detection interrupt -1012:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_TC: Transmission complete interrupt. -1013:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @arg USART_IT_RXNE: Receive Data register not empty interrupt. -1014:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * -1015:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @note -1016:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun -1017:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * error) and IDLE (Idle line detected) pending bits are cleared by -1018:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * software sequence: a read operation to USART_SR register -1019:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * (USART_GetITStatus()) followed by a read operation to USART_DR register -1020:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * (USART_ReceiveData()). -1021:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * - RXNE pending bit can be also cleared by a read to the USART_DR register -1022:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * (USART_ReceiveData()). -1023:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * - TC pending bit can be also cleared by software sequence: a read -1024:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * operation to USART_SR register (USART_GetITStatus()) followed by a write -1025:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * operation to USART_DR register (USART_SendData()). -1026:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * - TXE pending bit is cleared only by a write to the USART_DR register -1027:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * (USART_SendData()). -1028:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** * @retval None -1029:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** */ -1030:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) -1031:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { - 1192 .loc 1 1031 0 - 1193 .cfi_startproc - 1194 @ args = 0, pretend = 0, frame = 0 - 1195 @ frame_needed = 0, uses_anonymous_args = 0 - 1196 @ link register save eliminated. - 1197 .LVL123: -1032:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** uint16_t bitpos = 0x00, itmask = 0x00; -1033:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* Check the parameters */ -1034:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_ALL_PERIPH(USARTx)); -1035:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_CLEAR_IT(USART_IT)); -1036:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** /* The CTS interrupt is not available for UART4 and UART5 */ -1037:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** if (USART_IT == USART_IT_CTS) -1038:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** { -1039:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** assert_param(IS_USART_123_PERIPH(USARTx)); -1040:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** } -1041:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** -1042:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** bitpos = USART_IT >> 0x08; -1043:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - 1198 .loc 1 1043 0 - 1199 0000 090A lsrs r1, r1, #8 - 1200 .LVL124: - 1201 0002 0123 movs r3, #1 - 1202 0004 8B40 lsls r3, r3, r1 -1044:./lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c **** USARTx->SR = (uint16_t)~itmask; - 1203 .loc 1 1044 0 - 1204 0006 DB43 mvns r3, r3 - 1205 0008 9BB2 uxth r3, r3 - 1206 000a 0380 strh r3, [r0] @ movhi - 1207 000c 7047 bx lr - 1208 .cfi_endproc - 1209 .LFE57: - 1211 000e 00BF .text - 1212 .Letext0: - 1213 .file 2 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\mach - 1214 .file 3 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\stdi - 1215 .file 4 "./lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h" - 1216 .file 5 "./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h" - 1217 .file 6 "./lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h" - 1218 .file 7 "./lib/CMSIS/CM3/CoreSupport/core_cm3.h" -DEFINED SYMBOLS - *ABS*:00000000 stm32f10x_usart.c -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:19 .text.USART_DeInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:24 .text.USART_DeInit:00000000 USART_DeInit -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:128 .text.USART_DeInit:00000090 $d -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:137 .text.USART_Init:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:142 .text.USART_Init:00000000 USART_Init -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:289 .text.USART_Init:000000b0 $d -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:295 .text.USART_StructInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:300 .text.USART_StructInit:00000000 USART_StructInit -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:328 .text.USART_ClockInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:333 .text.USART_ClockInit:00000000 USART_ClockInit -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:376 .text.USART_ClockStructInit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:381 .text.USART_ClockStructInit:00000000 USART_ClockStructInit -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:403 .text.USART_Cmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:408 .text.USART_Cmd:00000000 USART_Cmd -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:436 .text.USART_ITConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:441 .text.USART_ITConfig:00000000 USART_ITConfig -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:509 .text.USART_DMACmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:514 .text.USART_DMACmd:00000000 USART_DMACmd -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:544 .text.USART_SetAddress:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:549 .text.USART_SetAddress:00000000 USART_SetAddress -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:574 .text.USART_WakeUpConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:579 .text.USART_WakeUpConfig:00000000 USART_WakeUpConfig -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:604 .text.USART_ReceiverWakeUpCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:609 .text.USART_ReceiverWakeUpCmd:00000000 USART_ReceiverWakeUpCmd -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:637 .text.USART_LINBreakDetectLengthConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:642 .text.USART_LINBreakDetectLengthConfig:00000000 USART_LINBreakDetectLengthConfig -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:667 .text.USART_LINCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:672 .text.USART_LINCmd:00000000 USART_LINCmd -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:700 .text.USART_SendData:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:705 .text.USART_SendData:00000000 USART_SendData -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:722 .text.USART_ReceiveData:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:727 .text.USART_ReceiveData:00000000 USART_ReceiveData -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:745 .text.USART_SendBreak:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:750 .text.USART_SendBreak:00000000 USART_SendBreak -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:768 .text.USART_SetGuardTime:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:773 .text.USART_SetGuardTime:00000000 USART_SetGuardTime -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:796 .text.USART_SetPrescaler:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:801 .text.USART_SetPrescaler:00000000 USART_SetPrescaler -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:824 .text.USART_SmartCardCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:829 .text.USART_SmartCardCmd:00000000 USART_SmartCardCmd -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:857 .text.USART_SmartCardNACKCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:862 .text.USART_SmartCardNACKCmd:00000000 USART_SmartCardNACKCmd -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:890 .text.USART_HalfDuplexCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:895 .text.USART_HalfDuplexCmd:00000000 USART_HalfDuplexCmd -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:923 .text.USART_OverSampling8Cmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:928 .text.USART_OverSampling8Cmd:00000000 USART_OverSampling8Cmd -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:955 .text.USART_OneBitMethodCmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:960 .text.USART_OneBitMethodCmd:00000000 USART_OneBitMethodCmd -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:988 .text.USART_IrDAConfig:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:993 .text.USART_IrDAConfig:00000000 USART_IrDAConfig -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:1018 .text.USART_IrDACmd:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:1023 .text.USART_IrDACmd:00000000 USART_IrDACmd -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:1051 .text.USART_GetFlagStatus:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:1056 .text.USART_GetFlagStatus:00000000 USART_GetFlagStatus -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:1078 .text.USART_ClearFlag:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:1083 .text.USART_ClearFlag:00000000 USART_ClearFlag -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:1101 .text.USART_GetITStatus:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:1106 .text.USART_GetITStatus:00000000 USART_GetITStatus -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:1185 .text.USART_ClearITPendingBit:00000000 $t -C:\Users\lwngim1\AppData\Local\Temp\ccZauMuc.s:1190 .text.USART_ClearITPendingBit:00000000 USART_ClearITPendingBit - .debug_frame:00000010 $d - -UNDEFINED SYMBOLS -RCC_APB2PeriphResetCmd -RCC_APB1PeriphResetCmd -RCC_GetClocksFreq diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.map b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.map deleted file mode 100644 index 8ce00267..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.map +++ /dev/null @@ -1,110 +0,0 @@ - -bin/demoprog_nucleo_stm32f103rb.elf: file format elf32-littlearm -bin/demoprog_nucleo_stm32f103rb.elf -architecture: arm, flags 0x00000112: -EXEC_P, HAS_SYMS, D_PAGED -start address 0x08006000 - -Program Header: - LOAD off 0x00000000 vaddr 0x08000000 paddr 0x08000000 align 2**15 - filesz 0x0000678c memsz 0x0000678c flags r-x - LOAD off 0x00008000 vaddr 0x20000000 paddr 0x0800678c align 2**15 - filesz 0x00000014 memsz 0x00000168 flags rw- -private flags = 5000202: [Version5 EABI] [soft-float ABI] [has entry point] - -Sections: -Idx Name Size VMA LMA File off Algn - 0 .text 0000078c 08006000 08006000 00006000 2**2 - CONTENTS, ALLOC, LOAD, READONLY, CODE - 1 .data 00000014 20000000 0800678c 00008000 2**2 - CONTENTS, ALLOC, LOAD, DATA - 2 .bss 00000154 20000014 080067a0 00008014 2**2 - ALLOC - 3 .debug_info 000030e6 00000000 00000000 00008014 2**0 - CONTENTS, READONLY, DEBUGGING - 4 .debug_abbrev 00000e0d 00000000 00000000 0000b0fa 2**0 - CONTENTS, READONLY, DEBUGGING - 5 .debug_loc 0000148a 00000000 00000000 0000bf07 2**0 - CONTENTS, READONLY, DEBUGGING - 6 .debug_aranges 000003f8 00000000 00000000 0000d391 2**0 - CONTENTS, READONLY, DEBUGGING - 7 .debug_ranges 00000358 00000000 00000000 0000d789 2**0 - CONTENTS, READONLY, DEBUGGING - 8 .debug_line 000015bd 00000000 00000000 0000dae1 2**0 - CONTENTS, READONLY, DEBUGGING - 9 .debug_str 00001424 00000000 00000000 0000f09e 2**0 - CONTENTS, READONLY, DEBUGGING - 10 .comment 00000070 00000000 00000000 000104c2 2**0 - CONTENTS, READONLY - 11 .ARM.attributes 00000033 00000000 00000000 00010532 2**0 - CONTENTS, READONLY - 12 .debug_frame 00000790 00000000 00000000 00010568 2**2 - CONTENTS, READONLY, DEBUGGING -SYMBOL TABLE: -08006000 l d .text 00000000 .text -20000000 l d .data 00000000 .data -20000014 l d .bss 00000000 .bss -00000000 l d .debug_info 00000000 .debug_info -00000000 l d .debug_abbrev 00000000 .debug_abbrev -00000000 l d .debug_loc 00000000 .debug_loc -00000000 l d .debug_aranges 00000000 .debug_aranges -00000000 l d .debug_ranges 00000000 .debug_ranges -00000000 l d .debug_line 00000000 .debug_line -00000000 l d .debug_str 00000000 .debug_str -00000000 l d .comment 00000000 .comment -00000000 l d .ARM.attributes 00000000 .ARM.attributes -00000000 l d .debug_frame 00000000 .debug_frame -00000000 l df *ABS* 00000000 vectors.c -00000000 l df *ABS* 00000000 boot.c -08006154 l F .text 0000001c NVIC_SystemReset -08006170 l F .text 0000002c UartReceiveByte -20000014 l O .bss 00000041 xcpCtoReqPacket.6487 -20000058 l O .bss 00000001 xcpCtoRxLength.6488 -20000059 l O .bss 00000001 xcpCtoRxInProgress.6489 -00000000 l df *ABS* 00000000 cstart.c -080062da l F .text 00000000 zero_loop -00000000 l df *ABS* 00000000 irq.c -00000000 l df *ABS* 00000000 led.c -2000005c l O .bss 00000004 timer_counter_last.6472 -20000060 l O .bss 00000001 led_toggle_state.6471 -00000000 l df *ABS* 00000000 main.c -00000000 l df *ABS* 00000000 timer.c -20000064 l O .bss 00000004 millisecond_counter -00000000 l df *ABS* 00000000 stm32f10x_gpio.c -00000000 l df *ABS* 00000000 stm32f10x_rcc.c -20000000 l O .data 00000004 ADCPrescTable -20000004 l O .data 00000010 APBAHBPrescTable -00000000 l df *ABS* 00000000 stm32f10x_usart.c -00000000 l df *ABS* 00000000 -00000100 l *ABS* 00000000 __STACKSIZE__ -080062a8 g F .text 00000054 reset_handler -08006308 g F .text 00000004 IrqInterruptEnable -08006780 g F .text 0000000c USART_GetFlagStatus -0800678c g .text 00000000 _etext -080064f8 g F .text 00000010 TimerISRHandler -08006778 g F .text 00000008 USART_ReceiveData -08006668 g F .text 0000001c RCC_APB2PeriphClockCmd -0800650c g F .text 000000a0 GPIO_Init -0800675c g F .text 0000001c USART_Cmd -08006684 g F .text 0000001c RCC_APB1PeriphClockCmd -20000068 g .bss 00000000 _ebss -08006508 g F .text 00000002 UnusedISR -0800630c g F .text 00000038 LedInit -080065ac g F .text 00000004 GPIO_SetBits -080065b4 g F .text 000000b4 RCC_GetClocksFreq -080066a0 g F .text 000000bc USART_Init -20000014 g .bss 00000000 _bss -080065b0 g F .text 00000004 GPIO_ResetBits -0800639c g F .text 00000124 main -0800619c g F .text 00000098 BootComInit -20000000 g .data 00000000 _data -08006344 g F .text 00000058 LedToggle -20000168 g .bss 00000000 _estack -20000014 g .data 00000000 _edata -08006000 g O .text 00000154 _vectab -08006234 g F .text 00000074 BootComCheckActivationRequest -20000068 g .bss 00000000 _stack -080064ec g F .text 0000000c TimerGet -080064c0 g F .text 0000002c TimerInit - - diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.srec b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.srec deleted file mode 100644 index b7c996de..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.srec +++ /dev/null @@ -1,125 +0,0 @@ -S027000062696E2F64656D6F70726F675F6E75636C656F5F73746D33326631303372622E737265636D -S3150800600068010020A96200080965000809650008FA -S31508006010096500080965000809650008096500089A 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--git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/boot.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/boot.c deleted file mode 100644 index eed20162..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/boot.c +++ /dev/null @@ -1,397 +0,0 @@ -/************************************************************************************//** -* \file Demo\ARMCM3_STM32_Olimex_STM32P103_GCC\Prog\boot.c -* \brief Demo program bootloader interface source file. -* \ingroup Prog_ARMCM3_STM32_Olimex_STM32P103_GCC -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or -* modify it under the terms of the GNU General Public License as published by the Free -* Software Foundation, either version 3 of the License, or (at your option) any later -* version. -* -* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; -* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -* PURPOSE. See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along with OpenBLT. -* If not, see . -* -* A special exception to the GPL is included to allow you to distribute a combined work -* that includes OpenBLT without being obliged to provide the source code for any -* proprietary components. The exception text is included at the bottom of the license -* file . -* -* \endinternal -****************************************************************************************/ - -/**************************************************************************************** -* Include files -****************************************************************************************/ -#include "header.h" /* generic header */ - - -/**************************************************************************************** -* Function prototypes -****************************************************************************************/ -#if (BOOT_COM_UART_ENABLE > 0) -static void BootComUartInit(void); -static void BootComUartCheckActivationRequest(void); -#endif -#if (BOOT_COM_CAN_ENABLE > 0) -static void BootComCanInit(void); -static void BootComCanCheckActivationRequest(void); -#endif - -/************************************************************************************//** -** \brief Initializes the communication interface. -** \return none. -** -****************************************************************************************/ -void BootComInit(void) -{ -#if (BOOT_COM_UART_ENABLE > 0) - BootComUartInit(); -#endif -#if (BOOT_COM_CAN_ENABLE > 0) - BootComCanInit(); -#endif -} /*** end of BootComInit ***/ - - -/************************************************************************************//** -** \brief Receives the CONNECT request from the host, which indicates that the -** bootloader should be activated and, if so, activates it. -** \return none. -** -****************************************************************************************/ -void BootComCheckActivationRequest(void) -{ -#if (BOOT_COM_UART_ENABLE > 0) - BootComUartCheckActivationRequest(); -#endif -#if (BOOT_COM_CAN_ENABLE > 0) - BootComCanCheckActivationRequest(); -#endif -} /*** end of BootComCheckActivationRequest ***/ - - -/************************************************************************************//** -** \brief Bootloader activation function. -** \return none. -** -****************************************************************************************/ -void BootActivate(void) -{ - /* perform software reset to activate the bootoader again */ - NVIC_SystemReset(); -} /*** end of BootActivate ***/ - - -#if (BOOT_COM_UART_ENABLE > 0) -/**************************************************************************************** -* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E -****************************************************************************************/ - -/**************************************************************************************** -* Function prototypes -****************************************************************************************/ -static unsigned char UartReceiveByte(unsigned char *data); - - -/************************************************************************************//** -** \brief Initializes the UART communication interface. -** \return none. -** -****************************************************************************************/ -static void BootComUartInit(void) -{ - GPIO_InitTypeDef GPIO_InitStruct; - USART_InitTypeDef USART_InitStruct; - - /* enable UART peripheral clock */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); - /* enable GPIO peripheral clock for transmitter and receiver pins */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE); - /* configure USART Tx as alternate function push-pull */ - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2; - GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStruct); - /* Configure USART Rx as alternate function input floating */ - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_3; - GPIO_Init(GPIOA, &GPIO_InitStruct); - /* configure UART communcation parameters */ - USART_InitStruct.USART_BaudRate = BOOT_COM_UART_BAUDRATE; - USART_InitStruct.USART_WordLength = USART_WordLength_8b; - USART_InitStruct.USART_StopBits = USART_StopBits_1; - USART_InitStruct.USART_Parity = USART_Parity_No; - USART_InitStruct.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStruct.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(USART2, &USART_InitStruct); - /* enable UART */ - USART_Cmd(USART2, ENABLE); -} /*** end of BootComUartInit ***/ - - -/************************************************************************************//** -** \brief Receives the CONNECT request from the host, which indicates that the -** bootloader should be activated and, if so, activates it. -** \return none. -** -****************************************************************************************/ -static void BootComUartCheckActivationRequest(void) -{ - static unsigned char xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1]; - static unsigned char xcpCtoRxLength; - static unsigned char xcpCtoRxInProgress = 0; - - /* start of cto packet received? */ - if (xcpCtoRxInProgress == 0) - { - /* store the message length when received */ - if (UartReceiveByte(&xcpCtoReqPacket[0]) == 1) - { - /* indicate that a cto packet is being received */ - xcpCtoRxInProgress = 1; - - /* reset packet data count */ - xcpCtoRxLength = 0; - } - } - else - { - /* store the next packet byte */ - if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1) - { - /* increment the packet data count */ - xcpCtoRxLength++; - - /* check to see if the entire packet was received */ - if (xcpCtoRxLength == xcpCtoReqPacket[0]) - { - /* done with cto packet reception */ - xcpCtoRxInProgress = 0; - - /* check if this was an XCP CONNECT command */ - if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00)) - { - /* connection request received so start the bootloader */ - BootActivate(); - } - } - } - } -} /*** end of BootComUartCheckActivationRequest ***/ - - -/************************************************************************************//** -** \brief Receives a communication interface byte if one is present. -** \param data Pointer to byte where the data is to be stored. -** \return 1 if a byte was received, 0 otherwise. -** -****************************************************************************************/ -static unsigned char UartReceiveByte(unsigned char *data) -{ - /* check flag to see if a byte was received */ - if (USART_GetFlagStatus(USART2, USART_FLAG_RXNE) == SET) - { - /* retrieve and store the newly received byte */ - *data = (unsigned char)USART_ReceiveData(USART2); - /* all done */ - return 1; - } - /* still here to no new byte received */ - return 0; -} /*** end of UartReceiveByte ***/ -#endif /* BOOT_COM_UART_ENABLE > 0 */ - - -#if (BOOT_COM_CAN_ENABLE > 0) -/**************************************************************************************** -* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E -****************************************************************************************/ - -/**************************************************************************************** -* Type definitions -****************************************************************************************/ -/** \brief Structure type for grouping CAN bus timing related information. */ -typedef struct t_can_bus_timing -{ - unsigned char tseg1; /**< CAN time segment 1 */ - unsigned char tseg2; /**< CAN time segment 2 */ -} tCanBusTiming; - - -/**************************************************************************************** -* Local constant declarations -****************************************************************************************/ -/** \brief CAN bittiming table for dynamically calculating the bittiming settings. - * \details According to the CAN protocol 1 bit-time can be made up of between 8..25 - * time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC - * always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) * - * 100%. This array contains possible and valid time quanta configurations with - * a sample point between 68..78%. - */ -static const tCanBusTiming canTiming[] = -{ /* TQ | TSEG1 | TSEG2 | SP */ - /* ------------------------- */ - { 5, 2 }, /* 8 | 5 | 2 | 75% */ - { 6, 2 }, /* 9 | 6 | 2 | 78% */ - { 6, 3 }, /* 10 | 6 | 3 | 70% */ - { 7, 3 }, /* 11 | 7 | 3 | 73% */ - { 8, 3 }, /* 12 | 8 | 3 | 75% */ - { 9, 3 }, /* 13 | 9 | 3 | 77% */ - { 9, 4 }, /* 14 | 9 | 4 | 71% */ - { 10, 4 }, /* 15 | 10 | 4 | 73% */ - { 11, 4 }, /* 16 | 11 | 4 | 75% */ - { 12, 4 }, /* 17 | 12 | 4 | 76% */ - { 12, 5 }, /* 18 | 12 | 5 | 72% */ - { 13, 5 }, /* 19 | 13 | 5 | 74% */ - { 14, 5 }, /* 20 | 14 | 5 | 75% */ - { 15, 5 }, /* 21 | 15 | 5 | 76% */ - { 15, 6 }, /* 22 | 15 | 6 | 73% */ - { 16, 6 }, /* 23 | 16 | 6 | 74% */ - { 16, 7 }, /* 24 | 16 | 7 | 71% */ - { 16, 8 } /* 25 | 16 | 8 | 68% */ -}; - - -/************************************************************************************//** -** \brief Search algorithm to match the desired baudrate to a possible bus -** timing configuration. -** \param baud The desired baudrate in kbps. Valid values are 10..1000. -** \param prescaler Pointer to where the value for the prescaler will be stored. -** \param tseg1 Pointer to where the value for TSEG2 will be stored. -** \param tseg2 Pointer to where the value for TSEG2 will be stored. -** \return 1 if the CAN bustiming register values were found, 0 otherwise. -** -****************************************************************************************/ -static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned short *prescaler, - unsigned char *tseg1, unsigned char *tseg2) -{ - unsigned char cnt; - - /* loop through all possible time quanta configurations to find a match */ - for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++) - { - if (((BOOT_CPU_SYSTEM_SPEED_KHZ/2) % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0) - { - /* compute the prescaler that goes with this TQ configuration */ - *prescaler = (BOOT_CPU_SYSTEM_SPEED_KHZ/2)/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1)); - - /* make sure the prescaler is valid */ - if ( (*prescaler > 0) && (*prescaler <= 1024) ) - { - /* store the bustiming configuration */ - *tseg1 = canTiming[cnt].tseg1; - *tseg2 = canTiming[cnt].tseg2; - /* found a good bus timing configuration */ - return 1; - } - } - } - /* could not find a good bus timing configuration */ - return 0; -} /*** end of CanGetSpeedConfig ***/ - - -/************************************************************************************//** -** \brief Initializes the CAN communication interface. -** \return none. -** -****************************************************************************************/ -static void BootComCanInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - CAN_InitTypeDef CAN_InitStructure; - CAN_FilterInitTypeDef CAN_FilterInitStructure; - unsigned short prescaler; - unsigned char tseg1, tseg2; - - /* GPIO clock enable */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); - /* Configure CAN pin: RX */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOB, &GPIO_InitStructure); - /* Configure CAN pin: TX */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOB, &GPIO_InitStructure); - /* Remap CAN1 pins to PortB */ - GPIO_PinRemapConfig(GPIO_Remap1_CAN1 , ENABLE); - /* CAN1 Periph clock enable */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); - /* CAN register init */ - CAN_DeInit(CAN1); - CAN_StructInit(&CAN_InitStructure); - /* obtain the bittiming configuration for this baudrate */ - CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &tseg1, &tseg2); - /* CAN controller init */ - CAN_InitStructure.CAN_TTCM = DISABLE; - CAN_InitStructure.CAN_ABOM = DISABLE; - CAN_InitStructure.CAN_AWUM = DISABLE; - CAN_InitStructure.CAN_NART = DISABLE; - CAN_InitStructure.CAN_RFLM = DISABLE; - CAN_InitStructure.CAN_TXFP = DISABLE; - CAN_InitStructure.CAN_Mode = CAN_Mode_Normal; - /* CAN Baudrate init */ - CAN_InitStructure.CAN_SJW = CAN_SJW_1tq; - CAN_InitStructure.CAN_BS1 = tseg1 - 1; - CAN_InitStructure.CAN_BS2 = tseg2 - 1; - CAN_InitStructure.CAN_Prescaler = prescaler; - CAN_Init(CAN1, &CAN_InitStructure); - /* CAN filter init - receive all messages */ - CAN_FilterInitStructure.CAN_FilterNumber = 0; - CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask; - CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit; - CAN_FilterInitStructure.CAN_FilterIdHigh = 0x0000; - CAN_FilterInitStructure.CAN_FilterIdLow = 0x0000; - CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0x0000; - CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0x0000; - CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 0; - CAN_FilterInitStructure.CAN_FilterActivation = ENABLE; - CAN_FilterInit(&CAN_FilterInitStructure); -} /*** end of BootCanComInit ***/ - - -/************************************************************************************//** -** \brief Receives the CONNECT request from the host, which indicates that the -** bootloader should be activated and, if so, activates it. -** \return none. -** -****************************************************************************************/ -static void BootComCanCheckActivationRequest(void) -{ - CanRxMsg RxMessage; - - /* check if a new message was received */ - if (CAN_MessagePending(CAN1, CAN_FIFO0) > 0) - { - /* receive the message */ - CAN_Receive(CAN1, CAN_FIFO0, &RxMessage); - if (RxMessage.StdId == BOOT_COM_CAN_RX_MSG_ID) - { - /* check if this was an XCP CONNECT command */ - if ((RxMessage.Data[0] == 0xff) && (RxMessage.Data[1] == 0x00)) - { - /* connection request received so start the bootloader */ - BootActivate(); - } - } - } -} /*** end of BootCanComCheckActivationRequest ***/ -#endif /* BOOT_COM_CAN_ENABLE > 0 */ - - -/*********************************** end of boot.c *************************************/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/boot.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/boot.h deleted file mode 100644 index 984da284..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/boot.h +++ /dev/null @@ -1,45 +0,0 @@ -/************************************************************************************//** -* \file Demo\ARMCM3_STM32_Olimex_STM32P103_GCC\Prog\boot.h -* \brief Demo program bootloader interface header file. -* \ingroup Prog_ARMCM3_STM32_Olimex_STM32P103_GCC -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or -* modify it under the terms of the GNU General Public License as published by the Free -* Software Foundation, either version 3 of the License, or (at your option) any later -* version. -* -* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; -* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -* PURPOSE. See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along with OpenBLT. -* If not, see . -* -* A special exception to the GPL is included to allow you to distribute a combined work -* that includes OpenBLT without being obliged to provide the source code for any -* proprietary components. The exception text is included at the bottom of the license -* file . -* -* \endinternal -****************************************************************************************/ -#ifndef BOOT_H -#define BOOT_H - -/**************************************************************************************** -* Function prototypes -****************************************************************************************/ -void BootComInit(void); -void BootComCheckActivationRequest(void); -void BootActivate(void); - - -#endif /* BOOT_H */ -/*********************************** end of boot.h *************************************/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/cmd/clean.bat b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/cmd/clean.bat deleted file mode 100644 index da685acd..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/cmd/clean.bat +++ /dev/null @@ -1,3 +0,0 @@ -@echo off -call env.bat -make --directory=../ clean diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/cmd/env.bat b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/cmd/env.bat deleted file mode 100644 index e6db8838..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/cmd/env.bat +++ /dev/null @@ -1,5 +0,0 @@ -@echo off -set PATH=c:\Program Files\GNU ARM Eclipse\OpenOCD\0.9.0-201505190955\bin\;%PATH% -set PATH=c:\Program Files (x86)\GNU ARM Eclipse\Build Tools\2.4-201503242026\bin;%PATH% -set PATH=c:\Program Files (x86)\GNU Tools ARM Embedded\4.9 2015q1\bin;%PATH% -set PATH=c:\Program Files (x86)\GNU Tools ARM Embedded\4.9 2015q1\arm-none-eabi\bin;%PATH% \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/cstart.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/cstart.c deleted file mode 100644 index 7050a0c6..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/cstart.c +++ /dev/null @@ -1,94 +0,0 @@ -/************************************************************************************//** -* \file Demo\ARMCM3_STM32_Olimex_STM32P103_GCC\Prog\cstart.c -* \brief Demo program C startup source file. -* \ingroup Prog_ARMCM3_STM32_Olimex_STM32P103_GCC -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or -* modify it under the terms of the GNU General Public License as published by the Free -* Software Foundation, either version 3 of the License, or (at your option) any later -* version. -* -* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; -* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -* PURPOSE. See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along with OpenBLT. -* If not, see . -* -* A special exception to the GPL is included to allow you to distribute a combined work -* that includes OpenBLT without being obliged to provide the source code for any -* proprietary components. The exception text is included at the bottom of the license -* file . -* -* \endinternal -****************************************************************************************/ - -/**************************************************************************************** -* Include files -****************************************************************************************/ -#include "header.h" /* generic header */ - - -/**************************************************************************************** -* External function protoypes -****************************************************************************************/ -extern int main(void); - - -/**************************************************************************************** -* External data declarations -****************************************************************************************/ -/* these externals are declared by the linker */ -extern unsigned long _etext; -extern unsigned long _data; -extern unsigned long _edata; -extern unsigned long _bss; -extern unsigned long _ebss; -extern unsigned long _estack; - - -/************************************************************************************//** -** \brief Reset interrupt service routine. Configures the stack, initializes -** RAM and jumps to function main. -** \return none. -** -****************************************************************************************/ -void reset_handler(void) -{ - unsigned long *pSrc, *pDest; - - /* initialize stack pointer */ - __asm(" ldr r1, =_estack\n" - " mov sp, r1"); - /* copy the data segment initializers from flash to SRAM */ - pSrc = &_etext; - for(pDest = &_data; pDest < &_edata; ) - { - *pDest++ = *pSrc++; - } - /* zero fill the bss segment. this is done with inline assembly since this will - * clear the value of pDest if it is not kept in a register. - */ - __asm(" ldr r0, =_bss\n" - " ldr r1, =_ebss\n" - " mov r2, #0\n" - " .thumb_func\n" - "zero_loop:\n" - " cmp r0, r1\n" - " it lt\n" - " strlt r2, [r0], #4\n" - " blt zero_loop"); - /* start the software application by calling its entry point */ - main(); -} /*** end of reset_handler ***/ - - -/************************************ end of cstart.c **********************************/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/header.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/header.h deleted file mode 100644 index 77fb001b..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/header.h +++ /dev/null @@ -1,49 +0,0 @@ -/************************************************************************************//** -* \file Demo\ARMCM3_STM32_Olimex_STM32P103_GCC\Prog\header.h -* \brief Generic header file. -* \ingroup Prog_ARMCM3_STM32_Olimex_STM32P103_GCC -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or -* modify it under the terms of the GNU General Public License as published by the Free -* Software Foundation, either version 3 of the License, or (at your option) any later -* version. -* -* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; -* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -* PURPOSE. See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along with OpenBLT. -* If not, see . -* -* A special exception to the GPL is included to allow you to distribute a combined work -* that includes OpenBLT without being obliged to provide the source code for any -* proprietary components. The exception text is included at the bottom of the license -* file . -* -* \endinternal -****************************************************************************************/ -#ifndef HEADER_H -#define HEADER_H - -/**************************************************************************************** -* Include files -****************************************************************************************/ -#include "../Boot/blt_conf.h" /* bootloader configuration */ -#include "stm32f10x.h" /* STM32 register definitions */ -#include "stm32f10x_conf.h" /* STM32 peripheral drivers */ -#include "boot.h" /* bootloader interface driver */ -#include "irq.h" /* IRQ driver */ -#include "led.h" /* LED driver */ -#include "timer.h" /* Timer driver */ - - -#endif /* HEADER_H */ -/*********************************** end of header.h ***********************************/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/ide/DemoProg.project b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/ide/DemoProg.project deleted file mode 100644 index eb281d2c..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/ide/DemoProg.project +++ /dev/null @@ -1,170 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - break main -continue - - - - - - - make clean - make - - - - None - $(WorkspacePath)/.. - - - - - - - - - - - - - - - - - - - - - - - make clean - make - - - - None - $(WorkspacePath) - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/ide/DemoProg.workspace b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/ide/DemoProg.workspace deleted file mode 100644 index 4060139b..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/ide/DemoProg.workspace +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/ide/readme.txt b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/ide/readme.txt deleted file mode 100644 index 8a340a19..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/ide/readme.txt +++ /dev/null @@ -1,4 +0,0 @@ -Integrated Development Environment ----------------------------------- -Codelite was used as the editor during the development of this software program. This directory contains the Codelite -workspace and project files. Codelite is a cross platform open source C/C++ IDE, available at http://www.codelite.org/. \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/irq.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/irq.c deleted file mode 100644 index 70609148..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/irq.c +++ /dev/null @@ -1,94 +0,0 @@ -/************************************************************************************//** -* \file Demo\ARMCM3_STM32_Olimex_STM32P103_GCC\Prog\irq.c -* \brief IRQ driver source file. -* \ingroup Prog_ARMCM3_STM32_Olimex_STM32P103_GCC -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or -* modify it under the terms of the GNU General Public License as published by the Free -* Software Foundation, either version 3 of the License, or (at your option) any later -* version. -* -* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; -* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -* PURPOSE. See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along with OpenBLT. -* If not, see . -* -* A special exception to the GPL is included to allow you to distribute a combined work -* that includes OpenBLT without being obliged to provide the source code for any -* proprietary components. The exception text is included at the bottom of the license -* file . -* -* \endinternal -****************************************************************************************/ - -/**************************************************************************************** -* Include files -****************************************************************************************/ -#include "header.h" /* generic header */ - - -/**************************************************************************************** -* Local data definitions -****************************************************************************************/ -/** \brief Interrupt nesting counter. Used for global interrupt en/disable. */ -static unsigned char interruptNesting = 0; - - -/************************************************************************************//** -** \brief Enables the generation IRQ interrupts. Typically called once during -** software startup after completion of the initialization. -** \return none. -** -****************************************************************************************/ -void IrqInterruptEnable(void) -{ - __enable_irq(); -} /*** end of IrqInterruptEnable ***/ - - -/************************************************************************************//** -** \brief Disables the generation IRQ interrupts and stores information on -** whether or not the interrupts were already disabled before explicitly -** disabling them with this function. Normally used as a pair together -** with IrqInterruptRestore during a critical section. -** \return none. -** -****************************************************************************************/ -void IrqInterruptDisable(void) -{ - if (interruptNesting == 0) - { - __disable_irq(); - } - interruptNesting++; -} /*** end of IrqInterruptDisable ***/ - - -/************************************************************************************//** -** \brief Restore the generation IRQ interrupts to the setting it had prior to -** calling IrqInterruptDisable. Normally used as a pair together with -** IrqInterruptDisable during a critical section. -** \return none. -** -****************************************************************************************/ -void IrqInterruptRestore(void) -{ - interruptNesting--; - if (interruptNesting == 0) - { - __enable_irq(); - } -} /*** end of IrqInterruptRestore ***/ - - -/*********************************** end of irq.c **************************************/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/led.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/led.h deleted file mode 100644 index 8dfb365c..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/led.h +++ /dev/null @@ -1,44 +0,0 @@ -/************************************************************************************//** -* \file Demo\ARMCM3_STM32_Olimex_STM32P103_GCC\Prog\led.h -* \brief LED driver header file. -* \ingroup Prog_ARMCM3_STM32_Olimex_STM32P103_GCC -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or -* modify it under the terms of the GNU General Public License as published by the Free -* Software Foundation, either version 3 of the License, or (at your option) any later -* version. -* -* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; -* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -* PURPOSE. See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along with OpenBLT. -* If not, see . -* -* A special exception to the GPL is included to allow you to distribute a combined work -* that includes OpenBLT without being obliged to provide the source code for any -* proprietary components. The exception text is included at the bottom of the license -* file . -* -* \endinternal -****************************************************************************************/ -#ifndef LED_H -#define LED_H - -/**************************************************************************************** -* Function prototypes -****************************************************************************************/ -void LedInit(void); -void LedToggle(void); - - -#endif /* LED_H */ -/*********************************** end of led.h **************************************/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c deleted file mode 100644 index 0e8c3c43..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.c +++ /dev/null @@ -1,784 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) __attribute__( ( naked ) ); -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n\t" - "BX lr \n\t" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) __attribute__( ( naked ) ); -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n\t" - "BX lr \n\t" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h deleted file mode 100644 index 2b6b51a7..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/CMSIS/CM3/CoreSupport/core_cm3.h +++ /dev/null @@ -1,1818 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CM3_CORE_H__ -#define __CM3_CORE_H__ - -/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - Error 10: \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' - * . - * - Error 530: \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized - * . - * - Error 550: \n - * __regBasePri = (basePri & 0x1ff); \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed - * . - * - Error 754: \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced - * . - * - Error 750: \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced - * . - * - Error 528: \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced - * . - * - Error 751: \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register - @{ -*/ - - -/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM3_NVIC */ - - -/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM3_SCB */ - - -/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM3_SysTick */ - - -/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM - memory mapped structure for Instrumentation Trace Macrocell (ITM) - @{ - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_CM3_ITM */ - - -/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type - memory mapped structure for Interrupt Type - @{ - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ -/*@}*/ /* end of group CMSIS_CM3_InterruptType */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU - memory mapped structure for Memory Protection Unit (MPU) - @{ - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@}*/ /* end of group CMSIS_CM3_MPU */ -#endif - - -/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - -/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ -/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ -static __INLINE void __WFI() { __ASM ("wfi"); } -static __INLINE void __WFE() { __ASM ("wfe"); } -static __INLINE void __SEV() { __ASM ("sev"); } -static __INLINE void __CLREX() { __ASM ("clrex"); } - -/* intrinsic void __ISB(void) */ -/* intrinsic void __DSB(void) */ -/* intrinsic void __DMB(void) */ -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } - -static __INLINE void __NOP() { __ASM volatile ("nop"); } -static __INLINE void __WFI() { __ASM volatile ("wfi"); } -static __INLINE void __WFE() { __ASM volatile ("wfe"); } -static __INLINE void __SEV() { __ASM volatile ("sev"); } -static __INLINE void __ISB() { __ASM volatile ("isb"); } -static __INLINE void __DSB() { __ASM volatile ("dsb"); } -static __INLINE void __DMB() { __ASM volatile ("dmb"); } -static __INLINE void __CLREX() { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - -/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param PriorityGroup is priority grouping field - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @return priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn The number of the interrupt for read active bit - * @return 1 = interrupt active, 0 = interrupt not active - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param PriorityGroup The used priority group - * @param PreemptPriority The preemptive priority value (starting from 0) - * @param SubPriority The sub priority value (starting from 0) - * @return The encoded priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param Priority The priority for the interrupt - * @param PriorityGroup The used priority group - * @param pPreemptPriority The preemptive priority value (starting from 0) - * @param pSubPriority The sub priority value (starting from 0) - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ - - - -/* ##################################### Debug In/Output function ########################################### */ - -/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface - Core Debug Interface containing: - - Core Debug Receive / Transmit Functions - - Core Debug Defines - - Core Debug Variables -*/ -/*@{*/ - -extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** - * @brief Outputs a character via the ITM channel 0 - * - * @param ch character to output - * @return character to output - * - * The function outputs a character via the ITM channel 0. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** - * @brief Inputs a character via variable ITM_RxBuffer - * - * @return received character, -1 = no character received - * - * The function inputs a character via variable ITM_RxBuffer. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE int ITM_ReceiveChar (void) { - int ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - * @brief Check if a character via variable ITM_RxBuffer is available - * - * @return 1 = character available, 0 = no character available - * - * The function checks variable ITM_RxBuffer whether a character is available or not. - * The function returns '1' if a character is available and '0' if no character is available. - */ -static __INLINE int ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_definitions */ - -#endif /* __CM3_CORE_H__ */ - -/*lint -restore */ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h deleted file mode 100644 index af0c7c9a..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h +++ /dev/null @@ -1,8336 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F10x Connectivity line, - * High density, High density value line, Medium density, - * Medium density Value line, Low density, Low density Value line - * and XL-density devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x - * @{ - */ - -#ifndef __STM32F10x_H -#define __STM32F10x_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) - /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ - /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ - /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ - /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ - /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ - /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ - /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ - /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ -#endif -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - - - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 16 and 32 Kbytes. - - Low-density value line devices are STM32F100xx microcontrollers where the Flash - memory density ranges between 16 and 32 Kbytes. - - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 64 and 128 Kbytes. - - Medium-density value line devices are STM32F100xx microcontrollers where the - Flash memory density ranges between 64 and 128 Kbytes. - - High-density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 256 and 512 Kbytes. - - High-density value line devices are STM32F100xx microcontrollers where the - Flash memory density ranges between 256 and 512 Kbytes. - - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 512 and 1024 Kbytes. - - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. - */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) - #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" -#endif - -#if !defined USE_STDPERIPH_DRIVER -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined HSE_VALUE - #ifdef STM32F10X_CL - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - #else - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ - #endif /* STM32F10X_CL */ -#endif /* HSE_VALUE */ - - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ - -#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ - -/** - * @brief STM32F10x Standard Peripheral Library version number - */ -#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F10X_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#ifdef STM32F10X_XL - #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ -#else - #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ -#endif /* STM32F10X_XL */ -#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @brief STM32F10x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - -#ifdef STM32F10X_LD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_LD */ - -#ifdef STM32F10X_LD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_LD_VL */ - -#ifdef STM32F10X_MD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_MD */ - -#ifdef STM32F10X_MD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_MD_VL */ - -#ifdef STM32F10X_HD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ - TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_HD */ - -#ifdef STM32F10X_HD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ - TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ - TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ - DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is - mapped at position 60 only if the MISC_REMAP bit in - the AFIO_MAPR2 register is set) */ -#endif /* STM32F10X_HD_VL */ - -#ifdef STM32F10X_XL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_XL */ - -#ifdef STM32F10X_CL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ -#endif /* STM32F10X_CL */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32f10x.h" -#include - -/** @addtogroup Exported_types - * @{ - */ - -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT -#define HSE_Value HSE_VALUE -#define HSI_Value HSI_VALUE -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; -} ADC_TypeDef; - -/** - * @brief Backup Registers - */ - -typedef struct -{ - uint32_t RESERVED0; - __IO uint16_t DR1; - uint16_t RESERVED1; - __IO uint16_t DR2; - uint16_t RESERVED2; - __IO uint16_t DR3; - uint16_t RESERVED3; - __IO uint16_t DR4; - uint16_t RESERVED4; - __IO uint16_t DR5; - uint16_t RESERVED5; - __IO uint16_t DR6; - uint16_t RESERVED6; - __IO uint16_t DR7; - uint16_t RESERVED7; - __IO uint16_t DR8; - uint16_t RESERVED8; - __IO uint16_t DR9; - uint16_t RESERVED9; - __IO uint16_t DR10; - uint16_t RESERVED10; - __IO uint16_t RTCCR; - uint16_t RESERVED11; - __IO uint16_t CR; - uint16_t RESERVED12; - __IO uint16_t CSR; - uint16_t RESERVED13[5]; - __IO uint16_t DR11; - uint16_t RESERVED14; - __IO uint16_t DR12; - uint16_t RESERVED15; - __IO uint16_t DR13; - uint16_t RESERVED16; - __IO uint16_t DR14; - uint16_t RESERVED17; - __IO uint16_t DR15; - uint16_t RESERVED18; - __IO uint16_t DR16; - uint16_t RESERVED19; - __IO uint16_t DR17; - uint16_t RESERVED20; - __IO uint16_t DR18; - uint16_t RESERVED21; - __IO uint16_t DR19; - uint16_t RESERVED22; - __IO uint16_t DR20; - uint16_t RESERVED23; - __IO uint16_t DR21; - uint16_t RESERVED24; - __IO uint16_t DR22; - uint16_t RESERVED25; - __IO uint16_t DR23; - uint16_t RESERVED26; - __IO uint16_t DR24; - uint16_t RESERVED27; - __IO uint16_t DR25; - uint16_t RESERVED28; - __IO uint16_t DR26; - uint16_t RESERVED29; - __IO uint16_t DR27; - uint16_t RESERVED30; - __IO uint16_t DR28; - uint16_t RESERVED31; - __IO uint16_t DR29; - uint16_t RESERVED32; - __IO uint16_t DR30; - uint16_t RESERVED33; - __IO uint16_t DR31; - uint16_t RESERVED34; - __IO uint16_t DR32; - uint16_t RESERVED35; - __IO uint16_t DR33; - uint16_t RESERVED36; - __IO uint16_t DR34; - uint16_t RESERVED37; - __IO uint16_t DR35; - uint16_t RESERVED38; - __IO uint16_t DR36; - uint16_t RESERVED39; - __IO uint16_t DR37; - uint16_t RESERVED40; - __IO uint16_t DR38; - uint16_t RESERVED41; - __IO uint16_t DR39; - uint16_t RESERVED42; - __IO uint16_t DR40; - uint16_t RESERVED43; - __IO uint16_t DR41; - uint16_t RESERVED44; - __IO uint16_t DR42; - uint16_t RESERVED45; -} BKP_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; - __IO uint32_t TDTR; - __IO uint32_t TDLR; - __IO uint32_t TDHR; -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; - __IO uint32_t RDTR; - __IO uint32_t RDLR; - __IO uint32_t RDHR; -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; - __IO uint32_t MSR; - __IO uint32_t TSR; - __IO uint32_t RF0R; - __IO uint32_t RF1R; - __IO uint32_t IER; - __IO uint32_t ESR; - __IO uint32_t BTR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FMR; - __IO uint32_t FM1R; - uint32_t RESERVED2; - __IO uint32_t FS1R; - uint32_t RESERVED3; - __IO uint32_t FFA1R; - uint32_t RESERVED4; - __IO uint32_t FA1R; - uint32_t RESERVED5[8]; -#ifndef STM32F10X_CL - CAN_FilterRegister_TypeDef sFilterRegister[14]; -#else - CAN_FilterRegister_TypeDef sFilterRegister[28]; -#endif /* STM32F10X_CL */ -} CAN_TypeDef; - -/** - * @brief Consumer Electronics Control (CEC) - */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t OAR; - __IO uint32_t PRES; - __IO uint32_t ESR; - __IO uint32_t CSR; - __IO uint32_t TXD; - __IO uint32_t RXD; -} CEC_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; - __IO uint8_t IDR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CR; -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t SWTRIGR; - __IO uint32_t DHR12R1; - __IO uint32_t DHR12L1; - __IO uint32_t DHR8R1; - __IO uint32_t DHR12R2; - __IO uint32_t DHR12L2; - __IO uint32_t DHR8R2; - __IO uint32_t DHR12RD; - __IO uint32_t DHR12LD; - __IO uint32_t DHR8RD; - __IO uint32_t DOR1; - __IO uint32_t DOR2; -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - __IO uint32_t SR; -#endif -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; - __IO uint32_t CR; -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; - __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t IFCR; -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - uint32_t RESERVED8[567]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - uint32_t RESERVED9[9]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; - __IO uint32_t EMR; - __IO uint32_t RTSR; - __IO uint32_t FTSR; - __IO uint32_t SWIER; - __IO uint32_t PR; -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; - __IO uint32_t KEYR; - __IO uint32_t OPTKEYR; - __IO uint32_t SR; - __IO uint32_t CR; - __IO uint32_t AR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WRPR; -#ifdef STM32F10X_XL - uint32_t RESERVED1[8]; - __IO uint32_t KEYR2; - uint32_t RESERVED2; - __IO uint32_t SR2; - __IO uint32_t CR2; - __IO uint32_t AR2; -#endif /* STM32F10X_XL */ -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ - -typedef struct -{ - __IO uint16_t RDP; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRP0; - __IO uint16_t WRP1; - __IO uint16_t WRP2; - __IO uint16_t WRP3; -} OB_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; - __IO uint32_t SR2; - __IO uint32_t PMEM2; - __IO uint32_t PATT2; - uint32_t RESERVED0; - __IO uint32_t ECCR2; -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; - __IO uint32_t SR3; - __IO uint32_t PMEM3; - __IO uint32_t PATT3; - uint32_t RESERVED0; - __IO uint32_t ECCR3; -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; - __IO uint32_t SR4; - __IO uint32_t PMEM4; - __IO uint32_t PATT4; - __IO uint32_t PIO4; -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t CRL; - __IO uint32_t CRH; - __IO uint32_t IDR; - __IO uint32_t ODR; - __IO uint32_t BSRR; - __IO uint32_t BRR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/** - * @brief Alternate Function I/O - */ - -typedef struct -{ - __IO uint32_t EVCR; - __IO uint32_t MAPR; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t MAPR2; -} AFIO_TypeDef; -/** - * @brief Inter Integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t OAR1; - uint16_t RESERVED2; - __IO uint16_t OAR2; - uint16_t RESERVED3; - __IO uint16_t DR; - uint16_t RESERVED4; - __IO uint16_t SR1; - uint16_t RESERVED5; - __IO uint16_t SR2; - uint16_t RESERVED6; - __IO uint16_t CCR; - uint16_t RESERVED7; - __IO uint16_t TRISE; - uint16_t RESERVED8; -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; - __IO uint32_t PR; - __IO uint32_t RLR; - __IO uint32_t SR; -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFGR; - __IO uint32_t CIR; - __IO uint32_t APB2RSTR; - __IO uint32_t APB1RSTR; - __IO uint32_t AHBENR; - __IO uint32_t APB2ENR; - __IO uint32_t APB1ENR; - __IO uint32_t BDCR; - __IO uint32_t CSR; - -#ifdef STM32F10X_CL - __IO uint32_t AHBRSTR; - __IO uint32_t CFGR2; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - uint32_t RESERVED0; - __IO uint32_t CFGR2; -#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint16_t CRH; - uint16_t RESERVED0; - __IO uint16_t CRL; - uint16_t RESERVED1; - __IO uint16_t PRLH; - uint16_t RESERVED2; - __IO uint16_t PRLL; - uint16_t RESERVED3; - __IO uint16_t DIVH; - uint16_t RESERVED4; - __IO uint16_t DIVL; - uint16_t RESERVED5; - __IO uint16_t CNTH; - uint16_t RESERVED6; - __IO uint16_t CNTL; - uint16_t RESERVED7; - __IO uint16_t ALRH; - uint16_t RESERVED8; - __IO uint16_t ALRL; - uint16_t RESERVED9; -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLKCR; - __IO uint32_t ARG; - __IO uint32_t CMD; - __I uint32_t RESPCMD; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __I uint32_t RESP4; - __IO uint32_t DTIMER; - __IO uint32_t DLEN; - __IO uint32_t DCTRL; - __I uint32_t DCOUNT; - __I uint32_t STA; - __IO uint32_t ICR; - __IO uint32_t MASK; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SR; - uint16_t RESERVED2; - __IO uint16_t DR; - uint16_t RESERVED3; - __IO uint16_t CRCPR; - uint16_t RESERVED4; - __IO uint16_t RXCRCR; - uint16_t RESERVED5; - __IO uint16_t TXCRCR; - uint16_t RESERVED6; - __IO uint16_t I2SCFGR; - uint16_t RESERVED7; - __IO uint16_t I2SPR; - uint16_t RESERVED8; -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SMCR; - uint16_t RESERVED2; - __IO uint16_t DIER; - uint16_t RESERVED3; - __IO uint16_t SR; - uint16_t RESERVED4; - __IO uint16_t EGR; - uint16_t RESERVED5; - __IO uint16_t CCMR1; - uint16_t RESERVED6; - __IO uint16_t CCMR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ARR; - uint16_t RESERVED11; - __IO uint16_t RCR; - uint16_t RESERVED12; - __IO uint16_t CCR1; - uint16_t RESERVED13; - __IO uint16_t CCR2; - uint16_t RESERVED14; - __IO uint16_t CCR3; - uint16_t RESERVED15; - __IO uint16_t CCR4; - uint16_t RESERVED16; - __IO uint16_t BDTR; - uint16_t RESERVED17; - __IO uint16_t DCR; - uint16_t RESERVED18; - __IO uint16_t DMAR; - uint16_t RESERVED19; -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; - uint16_t RESERVED0; - __IO uint16_t DR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CR1; - uint16_t RESERVED3; - __IO uint16_t CR2; - uint16_t RESERVED4; - __IO uint16_t CR3; - uint16_t RESERVED5; - __IO uint16_t GTPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFR; - __IO uint32_t SR; -} WWDG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define CEC_BASE (APB1PERIPH_BASE + 0x7800) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) -#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) -#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) - -#define SDIO_BASE (PERIPH_BASE + 0x18000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ - -#define ETH_BASE (AHBPERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define BKP ((BKP_TypeDef *) BKP_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define CEC ((CEC_TypeDef *) CEC_BASE) -#define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* CRC calculation unit */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ - - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ - -/*!< PVD level configuration */ -#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ -#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ -#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ -#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ -#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ -#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ -#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ -#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ - -#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ - - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ - -/******************************************************************************/ -/* */ -/* Backup registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR11 register *******************/ -#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR12 register *******************/ -#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR13 register *******************/ -#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR14 register *******************/ -#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR15 register *******************/ -#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR16 register *******************/ -#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR17 register *******************/ -#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_DR18 register ********************/ -#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR19 register *******************/ -#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR20 register *******************/ -#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR21 register *******************/ -#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR22 register *******************/ -#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR23 register *******************/ -#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR24 register *******************/ -#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR25 register *******************/ -#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR26 register *******************/ -#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR27 register *******************/ -#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR28 register *******************/ -#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR29 register *******************/ -#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR30 register *******************/ -#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR31 register *******************/ -#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR32 register *******************/ -#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR33 register *******************/ -#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR34 register *******************/ -#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR35 register *******************/ -#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR36 register *******************/ -#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR37 register *******************/ -#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR38 register *******************/ -#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR39 register *******************/ -#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR40 register *******************/ -#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR41 register *******************/ -#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR42 register *******************/ -#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ -#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ -#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ -#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ - -/******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ -#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ -#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ -#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ -#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ -#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ - -#ifdef STM32F10X_CL - #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ - #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ - #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ - #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ -#endif /* STM32F10X_CL */ - -/******************* Bit definition for RCC_CFGR register *******************/ -/*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ - -/*!< ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ - -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ - -#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ - -/*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ - -#ifdef STM32F10X_CL - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ - #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ - - #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ - #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ - #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ - #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#else - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#endif /* STM32F10X_CL */ - -/*!<****************** Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ - -#ifdef STM32F10X_CL - #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ - #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ - #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ - #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ - #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ - #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ -#endif /* STM32F10X_CL */ - -/***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ -#endif - -#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ -#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ -#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ - #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ - #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ - #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ - #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ -#endif /* STM32F10X_XL */ - -/***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ -#endif - -#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ - #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ - #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ - #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ - #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ - #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ - #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ - #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ - #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ - #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ - #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ - #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ - #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ -#endif - -#ifdef STM32F10X_CL - #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ - #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ - #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ -#endif /* STM32F10X_XL */ - -/****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ -#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) - #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ - #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ -#endif - -#ifdef STM32F10X_CL - #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ - #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ - #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ - #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ -#endif /* STM32F10X_CL */ - -/****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ -#endif - -#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ -#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ -#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ - #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ - #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ - #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ - #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ -#endif - -/***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ -#endif - -#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ - #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ - #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ - #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) - #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) - #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ - #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ - #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ - #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ -#endif - -#ifdef STM32F10X_HD_VL - #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ - #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ - #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ - #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ - #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ - #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ - #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ -#endif /* STM32F10X_HD_VL */ - -#ifdef STM32F10X_CL - #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ - #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ - #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ -#endif /* STM32F10X_XL */ - -/******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ - -#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ -#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ - -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ - -#ifdef STM32F10X_CL -/******************* Bit definition for RCC_AHBRSTR register ****************/ - #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ - #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ - -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ - -/*!< PREDIV2 configuration */ - #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ - #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ - #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ - -/*!< PLL2MUL configuration */ - #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ - #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ - #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ - #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ - #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ - #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ - #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ - #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ - #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ - #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ - #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ - -/*!< PLL3MUL configuration */ - #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ - #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ - #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ - #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ - #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ - #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ - #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ - #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ - #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ - #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ - #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ - - #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ - #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ -#endif - -/******************************************************************************/ -/* */ -/* General Purpose and Alternate Function I/O */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/*!<****************** Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ -#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ -#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ -#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ -#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ -#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ -#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ -#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ -#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ -#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ -#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ -#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ -#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ -#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ -#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ -#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ - -/******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ -#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ -#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ -#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ -#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ -#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ -#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ -#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ -#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ -#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ -#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ -#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ -#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ -#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ -#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ -#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ -#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ -#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ -#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ -#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ -#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ -#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ -#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ -#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ -#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ -#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ -#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ -#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ -#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ -#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ -#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ - -#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ -#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ -#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ -#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ -#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ -#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ -#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ -#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ -#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ -#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ -#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ -#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ -#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ -#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ -#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ -#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ -#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ -#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ -#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ -#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ -#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ -#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ -#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ -#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ -#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ -#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ -#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ -#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ -#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ -#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ -#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ -#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ - -/*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ - -#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ -#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ -#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ -#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ - -/*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ -#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ -#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ -#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ -#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ - -#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ - -/****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ - -#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -/* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -/*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -/*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ - -/*!< CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ - -/*!< SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ - -#ifdef STM32F10X_CL -/*!< ETH_REMAP configuration */ - #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ - -/*!< CAN2_REMAP configuration */ - #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ - -/*!< MII_RMII_SEL configuration */ - #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ - -/*!< SPI3_REMAP configuration */ - #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ - -/*!< TIM2ITR1_IREMAP configuration */ - #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ - -/*!< PTP_PPS_REMAP configuration */ - #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ -#endif - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ - -/*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ - -/*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ - -/*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ - -/*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ - -/*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ - -/* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ - -/*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ - -/*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ - -/*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ - -/*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ - -/*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ - -/*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ - -/* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ - -/* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ - -/*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ - -/*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ -#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ -#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ -#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ -#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ -#endif - -#ifdef STM32F10X_HD_VL -#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ -#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ -#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ -#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ -#endif - -#ifdef STM32F10X_XL -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ -#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ -#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ -#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ -#endif - -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ -#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ -#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ - -/******************************************************************************/ -/* */ -/* DMA Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CCR1 register *******************/ -#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ -#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ -#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR2 register *******************/ -#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR3 register *******************/ -#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/*!<****************** Bit definition for DMA_CCR4 register *******************/ -#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/****************** Bit definition for DMA_CCR5 register *******************/ -#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ - -/******************* Bit definition for DMA_CCR6 register *******************/ -#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR7 register *******************/ -#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ - -/****************** Bit definition for DMA_CNDTR1 register ******************/ -#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR2 register ******************/ -#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR3 register ******************/ -#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR4 register ******************/ -#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR5 register ******************/ -#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR6 register ******************/ -#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR7 register ******************/ -#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CPAR1 register *******************/ -#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR2 register *******************/ -#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR3 register *******************/ -#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR4 register *******************/ -#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR5 register *******************/ -#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR6 register *******************/ -#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR7 register *******************/ -#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CMAR1 register *******************/ -#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR2 register *******************/ -#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR3 register *******************/ -#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - - -/****************** Bit definition for DMA_CMAR4 register *******************/ -#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR5 register *******************/ -#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR6 register *******************/ -#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR7 register *******************/ -#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ -#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ -#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ -#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ -#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ - -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ -#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ - - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ -#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ -#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ -#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ -#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ - -#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ - -#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ -#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ -#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ -#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ - -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ - -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ - -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ -#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ - -#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ -#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ -#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ -#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ - -#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ -#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ -#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ - -#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ - -/***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12R2 register ******************/ -#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L2 register ******************/ -#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R2 register ******************/ -#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12RD register ******************/ -#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ -#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12LD register ******************/ -#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ -#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8RD register ******************/ -#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ -#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ - -/******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ - -/******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ - -/******************** Bit definition for DAC_SR register ********************/ -#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ - -/******************************************************************************/ -/* */ -/* CEC */ -/* */ -/******************************************************************************/ -/******************** Bit definition for CEC_CFGR register ******************/ -#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ -#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ -#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ -#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ - -/******************** Bit definition for CEC_OAR register ******************/ -#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ -#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ - -/******************** Bit definition for CEC_PRES register ******************/ -#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ - -/******************** Bit definition for CEC_ESR register ******************/ -#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ -#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ -#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ -#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ -#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ -#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ -#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ - -/******************** Bit definition for CEC_CSR register ******************/ -#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ -#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ -#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ -#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ -#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ -#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ -#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ -#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ - -/******************** Bit definition for CEC_TXD register ******************/ -#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ - -/******************** Bit definition for CEC_RXD register ******************/ -#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ - -/******************************************************************************/ -/* */ -/* TIM */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ -#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ -#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ -#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ -#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ - -#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ - -#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ - -#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ -#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -/******************* Bit definition for TIM_CR2 register ********************/ -#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ -#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ -#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ - -#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ -#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ -#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ -#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ -#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ -#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIM_SMCR register *******************/ -#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ - -#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ -#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ - -#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ -#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ -#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ -#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ - -#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ -#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ - -/******************* Bit definition for TIM_DIER register *******************/ -#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ -#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ -#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ -#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ -#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ -#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ -#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ -#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ -#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ -#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ -#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ -#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ - -/******************** Bit definition for TIM_SR register ********************/ -#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ -#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ -#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ -#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ -#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ -#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ -#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ -#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ -#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ -#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ -#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ -#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIM_EGR register ********************/ -#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ -#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ -#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ -#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ -#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ -#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ -#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ -#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ - -/****************** Bit definition for TIM_CCMR1 register *******************/ -#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ - -#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ -#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ - -#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ - -#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ -#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ - -#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ - -#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ -#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ - -#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ -#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ - -/****************** Bit definition for TIM_CCMR2 register *******************/ -#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ - -#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ -#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ - -#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ - -#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ -#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ - -#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ - -#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ -#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ - -#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ -#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ -#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ -#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ -#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ -#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ -#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ -#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ -#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ -#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ -#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ -#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ -#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ -#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ -#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ -#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ - -/******************* Bit definition for TIM_ARR register ********************/ -#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ - -/******************* Bit definition for TIM_RCR register ********************/ -#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ - -/******************* Bit definition for TIM_CCR1 register *******************/ -#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ - -/******************* Bit definition for TIM_CCR2 register *******************/ -#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ - -/******************* Bit definition for TIM_CCR3 register *******************/ -#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ - -/******************* Bit definition for TIM_CCR4 register *******************/ -#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ - -#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ -#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ -#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ -#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ -#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ -#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ -#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ - -/******************* Bit definition for TIM_DCR register ********************/ -#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ -#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ - -#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ -#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ -#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ -#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ - -/******************* Bit definition for TIM_DMAR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ - -/******************************************************************************/ -/* */ -/* Real-Time Clock */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for RTC_CRH register ********************/ -#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ -#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ -#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ - -/******************* Bit definition for RTC_CRL register ********************/ -#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ -#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ -#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ -#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ -#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ -#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ - -/******************* Bit definition for RTC_PRLH register *******************/ -#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ - -/******************* Bit definition for RTC_PRLL register *******************/ -#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ - -/******************* Bit definition for RTC_DIVH register *******************/ -#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ - -/******************* Bit definition for RTC_DIVL register *******************/ -#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ - -/******************* Bit definition for RTC_CNTH register *******************/ -#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ - -/******************* Bit definition for RTC_CNTL register *******************/ -#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ - -/******************* Bit definition for RTC_ALRH register *******************/ -#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ - -/******************* Bit definition for RTC_ALRL register *******************/ -#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ - -/******************************************************************************/ -/* */ -/* Independent WATCHDOG */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ - -/******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ - -/******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ - -/******************************************************************************/ -/* */ -/* Window WATCHDOG */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CR register ********************/ -#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ -#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ -#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ -#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ -#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ -#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ -#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ - -#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ - -/******************* Bit definition for WWDG_CFR register *******************/ -#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ -#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ - -#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ -#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ - -#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_SR register ********************/ -#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Flexible Static Memory Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for FSMC_BCR1 register *******************/ -#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR2 register *******************/ -#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR3 register *******************/ -#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ -#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR4 register *******************/ -#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BTR1 register ******************/ -#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BTR2 register *******************/ -#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/******************* Bit definition for FSMC_BTR3 register *******************/ -#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BTR4 register *******************/ -#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR1 register ******************/ -#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR2 register ******************/ -#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ -#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR3 register ******************/ -#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR4 register ******************/ -#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_PCR2 register *******************/ -#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ -#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/****************** Bit definition for FSMC_PCR3 register *******************/ -#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/****************** Bit definition for FSMC_PCR4 register *******************/ -#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/******************* Bit definition for FSMC_SR2 register *******************/ -#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/******************* Bit definition for FSMC_SR3 register *******************/ -#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/******************* Bit definition for FSMC_SR4 register *******************/ -#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/****************** Bit definition for FSMC_PMEM2 register ******************/ -#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ -#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ -#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ -#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ -#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PMEM3 register ******************/ -#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ -#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ -#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ -#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ -#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PMEM4 register ******************/ -#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ -#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ -#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ -#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ -#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT2 register ******************/ -#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ -#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ -#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ -#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ -#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT3 register ******************/ -#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ -#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ -#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ -#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ -#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT4 register ******************/ -#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ -#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ -#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ -#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ -#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PIO4 register *******************/ -#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ -#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ -#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ -#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ -#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_ECCR2 register ******************/ -#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ - -/****************** Bit definition for FSMC_ECCR3 register ******************/ -#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ - -/******************************************************************************/ -/* */ -/* SD host Interface */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for SDIO_POWER register ******************/ -#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ -#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ - -/****************** Bit definition for SDIO_CLKCR register ******************/ -#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ -#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ -#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ -#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ - -#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ -#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ -#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ - -#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ - -/******************* Bit definition for SDIO_ARG register *******************/ -#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ - -/******************* Bit definition for SDIO_CMD register *******************/ -#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ - -#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ -#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ -#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ - -#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ -#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ -#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ -#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ -#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ -#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ -#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ - -/***************** Bit definition for SDIO_RESPCMD register *****************/ -#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ - -/****************** Bit definition for SDIO_RESP0 register ******************/ -#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP1 register ******************/ -#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP2 register ******************/ -#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP3 register ******************/ -#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP4 register ******************/ -#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_DTIMER register *****************/ -#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ - -/****************** Bit definition for SDIO_DLEN register *******************/ -#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ - -/****************** Bit definition for SDIO_DCTRL register ******************/ -#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ -#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ -#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ -#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ - -#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ -#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ -#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ -#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ -#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ - -/****************** Bit definition for SDIO_DCOUNT register *****************/ -#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ - -/****************** Bit definition for SDIO_STA register ********************/ -#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ -#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ -#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ -#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ -#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ -#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ -#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ -#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ -#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ -#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ -#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ -#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ -#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ -#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ -#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ -#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ -#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ -#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ -#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ -#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ -#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ -#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ -#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ -#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ - -/******************* Bit definition for SDIO_ICR register *******************/ -#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ -#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ -#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ -#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ -#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ -#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ -#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ -#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ -#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ -#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ -#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ - -/****************** Bit definition for SDIO_MASK register *******************/ -#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ -#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ -#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ -#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ -#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ -#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ -#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ -#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ -#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ -#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ -#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ -#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ -#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ -#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ -#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ -#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ -#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ -#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ -#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ -#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ -#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ -#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ - -/***************** Bit definition for SDIO_FIFOCNT register *****************/ -#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ - -/****************** Bit definition for SDIO_FIFO register *******************/ -#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ - -/******************************************************************************/ -/* */ -/* USB Device FS */ -/* */ -/******************************************************************************/ - -/*!< Endpoint-specific registers */ -/******************* Bit definition for USB_EP0R register *******************/ -#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP1R register *******************/ -#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP2R register *******************/ -#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP3R register *******************/ -#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP4R register *******************/ -#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP5R register *******************/ -#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP6R register *******************/ -#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP7R register *******************/ -#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/*!< Common registers */ -/******************* Bit definition for USB_CNTR register *******************/ -#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ -#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ -#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ -#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ -#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ -#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ -#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ -#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ -#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ -#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ -#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ -#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ -#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ - -/******************* Bit definition for USB_ISTR register *******************/ -#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ -#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ -#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ -#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ -#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ -#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ -#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ -#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ -#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ -#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ - -/******************* Bit definition for USB_FNR register ********************/ -#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ -#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ -#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ -#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ -#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ - -/****************** Bit definition for USB_DADDR register *******************/ -#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ -#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ -#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ -#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ -#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ -#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ -#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ -#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ - -#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ - -/****************** Bit definition for USB_BTABLE register ******************/ -#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ - -/*!< Buffer descriptor table */ -/***************** Bit definition for USB_ADDR0_TX register *****************/ -#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ - -/***************** Bit definition for USB_ADDR1_TX register *****************/ -#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ - -/***************** Bit definition for USB_ADDR2_TX register *****************/ -#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ - -/***************** Bit definition for USB_ADDR3_TX register *****************/ -#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ - -/***************** Bit definition for USB_ADDR4_TX register *****************/ -#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ - -/***************** Bit definition for USB_ADDR5_TX register *****************/ -#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ - -/***************** Bit definition for USB_ADDR6_TX register *****************/ -#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ - -/***************** Bit definition for USB_ADDR7_TX register *****************/ -#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_COUNT0_TX register ****************/ -#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ - -/***************** Bit definition for USB_COUNT1_TX register ****************/ -#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ - -/***************** Bit definition for USB_COUNT2_TX register ****************/ -#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ - -/***************** Bit definition for USB_COUNT3_TX register ****************/ -#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ - -/***************** Bit definition for USB_COUNT4_TX register ****************/ -#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ - -/***************** Bit definition for USB_COUNT5_TX register ****************/ -#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ - -/***************** Bit definition for USB_COUNT6_TX register ****************/ -#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ - -/***************** Bit definition for USB_COUNT7_TX register ****************/ -#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ - -/*----------------------------------------------------------------------------*/ - -/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ -#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ - -/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ -#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ - -/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ -#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ - -/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ -#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ - -/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ -#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ - -/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ -#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ - -/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ -#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ - -/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ -#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ - -/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ -#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ - -/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ -#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ - -/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ -#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ - -/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ -#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ - -/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ -#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ - -/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ -#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ - -/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ -#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ - -/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ -#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_ADDR0_RX register *****************/ -#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ - -/***************** Bit definition for USB_ADDR1_RX register *****************/ -#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ - -/***************** Bit definition for USB_ADDR2_RX register *****************/ -#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ - -/***************** Bit definition for USB_ADDR3_RX register *****************/ -#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ - -/***************** Bit definition for USB_ADDR4_RX register *****************/ -#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ - -/***************** Bit definition for USB_ADDR5_RX register *****************/ -#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ - -/***************** Bit definition for USB_ADDR6_RX register *****************/ -#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ - -/***************** Bit definition for USB_ADDR7_RX register *****************/ -#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_COUNT0_RX register ****************/ -#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT1_RX register ****************/ -#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT2_RX register ****************/ -#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT3_RX register ****************/ -#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT4_RX register ****************/ -#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT5_RX register ****************/ -#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT6_RX register ****************/ -#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT7_RX register ****************/ -#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/*----------------------------------------------------------------------------*/ - -/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ -#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ -#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ -#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ -#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ -#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ -#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ -#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ -#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ -#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ -#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ -#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ -#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ -#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ -#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ -#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ -#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/******************************************************************************/ -/* */ -/* Controller Area Network */ -/* */ -/******************************************************************************/ - -/*!< CAN control and status registers */ -/******************* Bit definition for CAN_MCR register ********************/ -#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ -#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ -#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ -#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ -#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ -#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ -#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ -#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ -#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ - -/******************* Bit definition for CAN_MSR register ********************/ -#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ -#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ -#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ -#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ -#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ -#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ -#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ -#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ -#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ - -/******************* Bit definition for CAN_TSR register ********************/ -#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ -#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ -#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ -#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ -#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ -#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ -#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ -#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ -#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ -#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ -#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ -#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ -#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ -#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ -#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ -#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ - -#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ -#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ -#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ -#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ - -#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ -#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ - -/******************* Bit definition for CAN_RF0R register *******************/ -#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ -#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ -#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ -#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ - -/******************* Bit definition for CAN_RF1R register *******************/ -#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ -#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ -#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ -#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ - -/******************** Bit definition for CAN_IER register *******************/ -#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ -#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ -#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ -#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ -#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ -#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ -#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ -#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ -#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ -#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ - -/******************** Bit definition for CAN_ESR register *******************/ -#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ -#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ -#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ - -#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ -#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - -#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ -#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ - -/******************* Bit definition for CAN_BTR register ********************/ -#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ -#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ -#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ -#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ -#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ -#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ - -/*!< Mailbox registers */ -/****************** Bit definition for CAN_TI0R register ********************/ -#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/****************** Bit definition for CAN_TDT0R register *******************/ -#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/****************** Bit definition for CAN_TDL0R register *******************/ -#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/****************** Bit definition for CAN_TDH0R register *******************/ -#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_TI1R register *******************/ -#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT1R register ******************/ -#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_TDL1R register ******************/ -#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_TDH1R register ******************/ -#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_TI2R register *******************/ -#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ -#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT2R register ******************/ -#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_TDL2R register ******************/ -#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_TDH2R register ******************/ -#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_RI0R register *******************/ -#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT0R register ******************/ -#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ -#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_RDL0R register ******************/ -#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_RDH0R register ******************/ -#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_RI1R register *******************/ -#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ -#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT1R register ******************/ -#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ -#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_RDL1R register ******************/ -#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_RDH1R register ******************/ -#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/*!< CAN filter registers */ -/******************* Bit definition for CAN_FMR register ********************/ -#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ - -/******************* Bit definition for CAN_FM1R register *******************/ -#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ -#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ -#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ -#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ -#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ -#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ -#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ -#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ -#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ -#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ -#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ -#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ -#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ -#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ -#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ - -/******************* Bit definition for CAN_FS1R register *******************/ -#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ -#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ -#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ -#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ -#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ -#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ -#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ -#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ -#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ -#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ -#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ -#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ -#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ -#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ -#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ - -/****************** Bit definition for CAN_FFA1R register *******************/ -#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ -#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ -#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ -#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ -#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ -#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ -#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ -#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ -#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ -#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ -#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ -#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ -#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ -#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ -#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ - -/******************* Bit definition for CAN_FA1R register *******************/ -#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ -#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ -#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ -#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ -#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ -#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ -#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ -#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ -#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ -#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ -#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ -#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ -#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ -#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ -#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ - -/******************* Bit definition for CAN_F0R1 register *******************/ -#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F1R1 register *******************/ -#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F2R1 register *******************/ -#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F3R1 register *******************/ -#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F4R1 register *******************/ -#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F5R1 register *******************/ -#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F6R1 register *******************/ -#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F7R1 register *******************/ -#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F8R1 register *******************/ -#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F9R1 register *******************/ -#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F10R1 register ******************/ -#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F11R1 register ******************/ -#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F12R1 register ******************/ -#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F13R1 register ******************/ -#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F0R2 register *******************/ -#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F1R2 register *******************/ -#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F2R2 register *******************/ -#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F3R2 register *******************/ -#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F4R2 register *******************/ -#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F5R2 register *******************/ -#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F6R2 register *******************/ -#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F7R2 register *******************/ -#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F8R2 register *******************/ -#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F9R2 register *******************/ -#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F10R2 register ******************/ -#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F11R2 register ******************/ -#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F12R2 register ******************/ -#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F13R2 register ******************/ -#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************************************************************************/ -/* */ -/* Serial Peripheral Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ -#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ -#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ - -#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ -#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ -#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ - -#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ -#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ -#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ -#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ -#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ -#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ -#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ -#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ -#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ -#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ -#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ -#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ -#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ -#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ -#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ -#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ - -/******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ - -/******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ - -/****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ - -/****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ - -/****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ - -#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ -#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ - -/****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ -#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ - -/******************************************************************************/ -/* */ -/* Inter-integrated Circuit Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CR1 register ********************/ -#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ -#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ -#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ -#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ -#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ -#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ -#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ -#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ -#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ -#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ -#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ -#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ -#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ -#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ - -/******************* Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ - -#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ -#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ -#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ -#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ -#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ - -/******************* Bit definition for I2C_OAR1 register *******************/ -#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ -#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ - -#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ -#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ -#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ - -#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OAR2 register *******************/ -#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ -#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ - -/******************** Bit definition for I2C_DR register ********************/ -#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ - -/******************* Bit definition for I2C_SR1 register ********************/ -#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ -#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ -#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ -#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ -#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ -#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ -#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ -#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ -#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ -#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ -#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ -#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ -#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ -#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ - -/******************* Bit definition for I2C_SR2 register ********************/ -#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ -#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ -#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ -#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ -#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ -#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ -#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ -#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ - -/******************* Bit definition for I2C_CCR register ********************/ -#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ -#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ - -/****************** Bit definition for I2C_TRISE register *******************/ -#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ - -/******************************************************************************/ -/* */ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for USART_SR register *******************/ -#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ -#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ -#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ -#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ -#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ -#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ -#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ -#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ -#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ -#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ - -/******************* Bit definition for USART_DR register *******************/ -#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ - -/****************** Bit definition for USART_CR1 register *******************/ -#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ -#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ -#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ -#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ -#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ -#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ -#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ -#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ -#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ -#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ -#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ -#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ -#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ - -/****************** Bit definition for USART_CR2 register *******************/ -#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ -#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ -#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ -#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ -#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ -#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ - -#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ -#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ - -/****************** Bit definition for USART_CR3 register *******************/ -#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ -#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ -#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ -#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ -#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ -#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ -#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ -#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ -#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ -#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ -#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ -#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ - -/****************** Bit definition for USART_GTPR register ******************/ -#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ -#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ - -#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ - -/******************************************************************************/ -/* */ -/* Debug MCU */ -/* */ -/******************************************************************************/ - -/**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ - -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ -#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ -#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ -#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ -#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ -#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ -#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ -#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ -#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ -#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ - -/****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ -#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ - -#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ -#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ -#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ - -/******************************************************************************/ -/* */ -/* FLASH and Option Bytes Registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ -#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ -#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ -#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ - -#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ -#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ - -/***************** Bit definition for FLASH_OPTKEYR register ****************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ - -/****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ -#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ -#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ -#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ - -/******************* Bit definition for FLASH_CR register *******************/ -#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ -#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ -#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ -#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ -#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ -#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ -#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ -#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ -#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ -#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ - -/******************* Bit definition for FLASH_AR register *******************/ -#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ - -#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ -#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ -#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ - -/****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for FLASH_RDP register *******************/ -#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ -#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ - -/****************** Bit definition for FLASH_WRP0 register ******************/ -#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP1 register ******************/ -#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP2 register ******************/ -#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP3 register ******************/ -#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -#ifdef STM32F10X_CL -/******************************************************************************/ -/* Ethernet MAC Registers bits definitions */ -/******************************************************************************/ -/* Bit definition for Ethernet MAC Control Register register */ -#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ -#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ -#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ - #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ - #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ - #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ - #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ - #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ - #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ - #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ - #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ -#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ -#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ -#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ -#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ -#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ -#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ -#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ -#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ -#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling - a transmission attempt during retries after a collision: 0 =< r <2^k */ - #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ - #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ - #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ - #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ -#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ -#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ -#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ - -/* Bit definition for Ethernet MAC Frame Filter Register */ -#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ -#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ -#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ -#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ -#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ - #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ - #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ - #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ -#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ -#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ -#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ -#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ -#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ -#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ - -/* Bit definition for Ethernet MAC Hash Table High Register */ -#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ - -/* Bit definition for Ethernet MAC Hash Table Low Register */ -#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ - -/* Bit definition for Ethernet MAC MII Address Register */ -#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ -#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ -#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ - #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ - #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ - #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ -#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ -#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ - -/* Bit definition for Ethernet MAC MII Data Register */ -#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ - -/* Bit definition for Ethernet MAC Flow Control Register */ -#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ -#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ -#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ - #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ - #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ - #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ - #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ -#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ -#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ -#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ -#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ - -/* Bit definition for Ethernet MAC VLAN Tag Register */ -#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ -#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ - -/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ -#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ -/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. - Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ -/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask - Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask - Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask - Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask - Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - - RSVD - Filter1 Command - RSVD - Filter0 Command - Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset - Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 - Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ - -/* Bit definition for Ethernet MAC PMT Control and Status Register */ -#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ -#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ -#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ -#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ -#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ -#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ - -/* Bit definition for Ethernet MAC Status Register */ -#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ -#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ -#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ -#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ -#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ - -/* Bit definition for Ethernet MAC Interrupt Mask Register */ -#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ -#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ - -/* Bit definition for Ethernet MAC Address0 High Register */ -#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ - -/* Bit definition for Ethernet MAC Address0 Low Register */ -#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ - -/* Bit definition for Ethernet MAC Address1 High Register */ -#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ - #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ -#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address1 Low Register */ -#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ - -/* Bit definition for Ethernet MAC Address2 High Register */ -#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ - #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address2 Low Register */ -#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ - -/* Bit definition for Ethernet MAC Address3 High Register */ -#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ - #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ - -/* Bit definition for Ethernet MAC Address3 Low Register */ -#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ - -/******************************************************************************/ -/* Ethernet MMC Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet MMC Contol Register */ -#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ -#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ -#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ -#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ - -/* Bit definition for Ethernet MMC Receive Interrupt Register */ -#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Register */ -#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ -#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ -#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ -#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ -#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ -#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ - -/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ -#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ - -/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ -#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ - -/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ -#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ - -/******************************************************************************/ -/* Ethernet PTP Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet PTP Time Stamp Contol Register */ -#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ -#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ -#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ -#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ -#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ -#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ - -/* Bit definition for Ethernet PTP Sub-Second Increment Register */ -#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ - -/* Bit definition for Ethernet PTP Time Stamp High Register */ -#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ - -/* Bit definition for Ethernet PTP Time Stamp Low Register */ -#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ -#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp High Update Register */ -#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ -#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ -#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Addend Register */ -#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ - -/* Bit definition for Ethernet PTP Target Time High Register */ -#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ - -/* Bit definition for Ethernet PTP Target Time Low Register */ -#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ - -/******************************************************************************/ -/* Ethernet DMA Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet DMA Bus Mode Register */ -#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ -#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ -#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ -#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ - #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ - #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ - #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ - #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ -#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ -#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ -#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ - #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ - #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ - #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ - #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ -#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ -#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ -#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ - -/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ -#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ - -/* Bit definition for Ethernet DMA Receive Poll Demand Register */ -#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ - -/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ -#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ - -/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ -#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ - -/* Bit definition for Ethernet DMA Status Register */ -#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ -#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ -#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ -#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ - /* combination with EBS[2:0] for GetFlagStatus function */ - #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ - #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ - #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ - #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ - #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ - #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ - #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ - #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ - #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ -#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ - #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ - #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ - #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ - #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ - #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ - #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ -#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ -#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ -#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ -#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ -#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ -#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ -#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ -#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ -#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ -#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ -#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ -#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ -#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ -#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ -#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ - -/* Bit definition for Ethernet DMA Operation Mode Register */ -#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ -#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ -#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ -#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ -#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ -#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ - #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ - #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ - #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ - #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ - #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ - #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ - #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ - #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ -#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ -#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ -#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ -#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ - #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ - #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ - #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ - #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ -#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ -#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ - -/* Bit definition for Ethernet DMA Interrupt Enable Register */ -#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ -#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ -#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ -#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ -#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ -#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ -#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ -#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ -#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ -#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ -#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ -#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ -#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ -#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ -#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ - -/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ -#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ -#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ -#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ -#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ - -/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ -#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ -#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ -#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ -#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ -#endif /* STM32F10X_CL */ - -/** - * @} - */ - - /** - * @} - */ - -#ifdef USE_STDPERIPH_DRIVER - #include "stm32f10x_conf.h" -#endif - -/** @addtogroup Exported_macro - * @{ - */ - -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_H */ - -/** - * @} - */ - - /** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/Release_Notes.html b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/Release_Notes.html deleted file mode 100644 index 633e42e3..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/Release_Notes.html +++ /dev/null @@ -1,342 +0,0 @@ - - - - - - - - - - - - -Release Notes for STM32F10x Standard Peripherals Library Drivers - - - - - -
-


-

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Back to Release page
-

Release -Notes for STM32F10x Standard Peripherals Library Drivers -(StdPeriph_Driver)

-

Copyright 2011 STMicroelectronics

-

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-

 

- - - - - - -
-

Contents

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    -
  1. STM32F10x Standard Peripherals Library -Drivers update History
    2. -
  2. License
    3. -
- - -

STM32F10x Standard -Peripherals Library Drivers  update History


-

V3.5.0 / 11-March-2011

-

Main -Changes

- -
    -
  • stm32f10x_can.h/.c files:
    • -
      -
    • Add 5 new functions
      • -
        -
      • 3 -new functions controlling the counter errors: CAN_GetLastErrorCode(), -CAN_GetReceiveErrorCounter() and CAN_GetLSBTransmitErrorCounter().
        • -
      -
        -
      • 1 new function to select the CAN operating mode: CAN_OperatingModeRequest().
        • -
      -
        -
      • 1 new function to support CAN TT mode: CAN_TTComModeCmd().
        -
        • -
      -
    • CAN_TransmitStatus() function updated to support all CAN transmit intermediate states
      -
      • -
    -
  • stm32f10x_i2c.h/.c files:
    • -
      -
    • Add 1 new function:
      • -
        -
      • I2C_NACKPositionConfig(): -This function configures the same bit (POS) as I2C_PECPositionConfig() -but is intended to be used in I2C mode while I2C_PECPositionConfig() is -intended to used in SMBUS mode.
        • -
      -
    -
  • stm32f10x_tim.h/.c files:
    • -
      -
    • Change the TIM_DMABurstLength_xBytes definitions to TIM_DMABurstLength_xTansfers
      -
      • -
    - - -
- -

3.4.0 -- 10/15/2010

- -
    -
  1. General
    2. -
- -
    -
  • Add support for STM32F10x High-density value line devices.
    • -
- -
    -
  1. STM32F10x_StdPeriph_Driver
    2. -
- - -
    - -
  • stm32f10x_bkp.h/.c
    • -
      -
    • Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file.
      • -
    -
  • stm32f10x_can.h/.c
    • -
      -
    • Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.
      -
      • -
    • Update the wording of some defines and Asserts macro.
      -
      • -
    • CAN_GetFlagStatus() -and CAN_ClearFlag() functions: updated to support new flags (were not -supported in previous version). These flags are:  CAN_FLAG_RQCP0, -CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1, -CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0,   CAN_FLAG_FOV0, -CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC.
      -
      • -
    • CAN_GetITStatus() -function: add a check of the interrupt enable bit before getting the -status of corresponding interrupt pending bit.
      -
      • -
    • CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit.
      -
      • -
    -
  • stm32f10x_crc.h/.c
    • -
      -
    • Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.
      • -
    -
  • stm32f10x_dac.h/.c
    • -
      -
    • Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file.
      • -
    -
  • stm32f10x_dbgmcu.h/.c
    • -
      -
    • Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file.
      • -
    -
  • stm32f10x_dma.h/.c
    • -
      -
    • Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.
      • -
    • Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"
      -
      • -
    -
  • stm32f10x_flash.h/.c
    • -
      -
    • FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.
      • -
    -
  • stm32f10x_fsmc.h/.c
    • -
      -
    • Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.
      • -
    -
  • stm32f10x_gpio.h/.c
    • -
      -
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.
      • -
    -
  • stm32f10x_pwr.h/.c
    • -
      -
    • Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.
      • -
    -
  • stm32f10x_rtc.h/.c
    • -
      -
    • Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.
      • -
    -
  • stm32f10x_spi.h/.c
    • -
      -
    • Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".
      • -
    -
  • stm32f10x_tim.h/.c
    • -
    • Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".
    - -
- -

3.3.0 -- 04/16/2010

- -
  1. General
-
  • Add support for STM32F10x XL-density devices.
  • I2C driver: events description and management enhancement.
-
  1. STM32F10x_StdPeriph_Driver
-
  • stm32f10x_dbgmcu.h/.c
    • DBGMCU_Config() function: add new values DBGMCU_TIMx_STOP (x: 9..14) for DBGMCU_Periph parameter.
  • stm32f10x_flash.h/.c: -updated to support Bank2 of XL-density devices (up to 1MByte of Flash -memory). For more details, refer to the description provided within -stm32f10x_flash.c file.
  • stm32f10x_gpio.h/.c
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for FSMC_NADV pin and TIM9..11,13,14.
  • stm32f10x_i2c.h/.c: I2C events description and management enhancement.
    • I2C_CheckEvent() -function: updated to check whether the last event contains the -I2C_EVENT  (instead of check whether the last event is equal to -I2C_EVENT)
    • Add -detailed description of I2C events and how to manage them using the -functions provided by this driver. For more information, refer to -stm32f10x_i2c.h and stm32f10x_i2c.c files.
  • stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration
  • stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.
  • stm32f10x_sdio.h: 
    • SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter
      change
        -#define -SDIO_ReadWaitMode_CLK               -  ((uint32_t)0x00000000)
        #define -SDIO_ReadWaitMode_DATA2             -((uint32_t)0x00000001)
      by
        #define -SDIO_ReadWaitMode_CLK               -  ((uint32_t)0x00000001)
        #define -SDIO_ReadWaitMode_DATA2             -((uint32_t)0x00000000)
-

3.2.0 -- 03/01/2010

-
    -
  1. General
    2. -
-
    - -
  • Add support -for STM32 Low-density Value line (STM32F100x4/6) and -Medium-density Value line (STM32F100x8/B) devices.
    • -
  • Almost -peripherals drivers were updated to support Value -line devices features
    • -
  • Drivers limitations fix and enhancements.
    • - -
-
    -
  1. STM32F10x_StdPeriph_Driver
    2. -
-
    -
  • Add new -firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c
    • -
  • Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.
    • -
  • RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.
    • -
  • GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: GPIO_Remap_TIM1_DMA, GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.
    • -
  • USART -driver: add support for Oversampling by 8 mode and onebit method. 2 -functions has been added: USART_OverSampling8Cmd() and -USART_OneBitMethodCmd().
    -
    • -
  • DAC -driver: add new functions handling the DAC under run feature: -DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus() -and DAC_ClearITPendingBit().
    • -
  • DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.
    -
    • -
  • FLASH -driver: the FLASH_EraseOptionBytes() function updated. This is now just -erasing the option bytes without modifying the RDP status either -enabled or disabled.
    • -
  • PWR -driver: the PWR_EnterSTOPMode() function updated. When woken up from -STOP mode, this function resets again the SLEEPDEEP bit in the -Cortex-M3 System Control register to allow Sleep mode entering.
    • - - -
-

License

-

The -enclosed firmware and all the related documentation are not covered by -a License Agreement, if you need such License you can contact your -local STMicroelectronics office.

-

THE -PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO -SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR -ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY -CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY -CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH -THEIR PRODUCTS.

-

 

-
-
-

For -complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers -visit www.st.com/STM32

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/misc.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/misc.h deleted file mode 100644 index 7d401ca9..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/misc.h +++ /dev/null @@ -1,220 +0,0 @@ -/** - ****************************************************************************** - * @file misc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/** @defgroup MISC_Exported_Types - * @{ - */ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be a value of @ref IRQn_Type - (For the complete STM32 Devices IRQ Channels list, please - refer to stm32f10x.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup NVIC_Priority_Table - * @{ - */ - -/** -@code - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - ============================================================================================================================ - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ============================================================================================================================ - NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ============================================================================================================================ -@endcode -*/ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @} - */ - -/** @defgroup SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Functions - * @{ - */ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h deleted file mode 100644 index d1b2653a..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h +++ /dev/null @@ -1,483 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_adc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_ADC_H -#define __STM32F10x_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Exported_Types - * @{ - */ - -/** - * @brief ADC Init structure definition - */ - -typedef struct -{ - uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or - dual mode. - This parameter can be a value of @ref ADC_mode */ - - FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in - Scan (multichannels) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ -}ADC_InitTypeDef; -/** - * @} - */ - -/** @defgroup ADC_Exported_Constants - * @{ - */ - -#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3)) - -#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC3)) - -/** @defgroup ADC_mode - * @{ - */ - -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) -#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) -#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) -#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) -#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) -#define ADC_Mode_RegSimult ((uint32_t)0x00060000) -#define ADC_Mode_FastInterl ((uint32_t)0x00070000) -#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) -#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) - -#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ - ((MODE) == ADC_Mode_RegInjecSimult) || \ - ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ - ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ - ((MODE) == ADC_Mode_InjecSimult) || \ - ((MODE) == ADC_Mode_RegSimult) || \ - ((MODE) == ADC_Mode_FastInterl) || \ - ((MODE) == ADC_Mode_SlowInterl) || \ - ((MODE) == ADC_Mode_AlterTrig)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion - * @{ - */ - -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ - -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ - -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ - -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_None) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) -/** - * @} - */ - -/** @defgroup ADC_data_align - * @{ - */ - -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - -/** @defgroup ADC_channels - * @{ - */ - -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) - -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) -/** - * @} - */ - -/** @defgroup ADC_sampling_time - * @{ - */ - -#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) -#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) -#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) -#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) -#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) -#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) -#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) -#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ - ((TIME) == ADC_SampleTime_7Cycles5) || \ - ((TIME) == ADC_SampleTime_13Cycles5) || \ - ((TIME) == ADC_SampleTime_28Cycles5) || \ - ((TIME) == ADC_SampleTime_41Cycles5) || \ - ((TIME) == ADC_SampleTime_55Cycles5) || \ - ((TIME) == ADC_SampleTime_71Cycles5) || \ - ((TIME) == ADC_SampleTime_239Cycles5)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion - * @{ - */ - -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ - -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ - -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ - -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) -/** - * @} - */ - -/** @defgroup ADC_injected_channel_selection - * @{ - */ - -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4)) -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ - -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition - * @{ - */ - -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) - -#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) - -#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ - ((IT) == ADC_IT_JEOC)) -/** - * @} - */ - -/** @defgroup ADC_flags_definition - * @{ - */ - -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ - ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ - ((FLAG) == ADC_FLAG_STRT)) -/** - * @} - */ - -/** @defgroup ADC_thresholds - * @{ - */ - -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_offset - * @{ - */ - -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_length - * @{ - */ - -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) - -/** - * @} - */ - -/** @defgroup ADC_injected_rank - * @{ - */ - -#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) - -/** - * @} - */ - - -/** @defgroup ADC_regular_length - * @{ - */ - -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) -/** - * @} - */ - -/** @defgroup ADC_regular_rank - * @{ - */ - -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) - -/** - * @} - */ - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ - -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions - * @{ - */ - -void ADC_DeInit(ADC_TypeDef* ADCx); -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -void ADC_ResetCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_StartCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetDualModeConversionValue(void); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h deleted file mode 100644 index b620753e..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_bkp.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the BKP firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_BKP_H -#define __STM32F10x_BKP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup BKP - * @{ - */ - -/** @defgroup BKP_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Constants - * @{ - */ - -/** @defgroup Tamper_Pin_active_level - * @{ - */ - -#define BKP_TamperPinLevel_High ((uint16_t)0x0000) -#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) -#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ - ((LEVEL) == BKP_TamperPinLevel_Low)) -/** - * @} - */ - -/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin - * @{ - */ - -#define BKP_RTCOutputSource_None ((uint16_t)0x0000) -#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) -#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) -#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) -#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ - ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ - ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ - ((SOURCE) == BKP_RTCOutputSource_Second)) -/** - * @} - */ - -/** @defgroup Data_Backup_Register - * @{ - */ - -#define BKP_DR1 ((uint16_t)0x0004) -#define BKP_DR2 ((uint16_t)0x0008) -#define BKP_DR3 ((uint16_t)0x000C) -#define BKP_DR4 ((uint16_t)0x0010) -#define BKP_DR5 ((uint16_t)0x0014) -#define BKP_DR6 ((uint16_t)0x0018) -#define BKP_DR7 ((uint16_t)0x001C) -#define BKP_DR8 ((uint16_t)0x0020) -#define BKP_DR9 ((uint16_t)0x0024) -#define BKP_DR10 ((uint16_t)0x0028) -#define BKP_DR11 ((uint16_t)0x0040) -#define BKP_DR12 ((uint16_t)0x0044) -#define BKP_DR13 ((uint16_t)0x0048) -#define BKP_DR14 ((uint16_t)0x004C) -#define BKP_DR15 ((uint16_t)0x0050) -#define BKP_DR16 ((uint16_t)0x0054) -#define BKP_DR17 ((uint16_t)0x0058) -#define BKP_DR18 ((uint16_t)0x005C) -#define BKP_DR19 ((uint16_t)0x0060) -#define BKP_DR20 ((uint16_t)0x0064) -#define BKP_DR21 ((uint16_t)0x0068) -#define BKP_DR22 ((uint16_t)0x006C) -#define BKP_DR23 ((uint16_t)0x0070) -#define BKP_DR24 ((uint16_t)0x0074) -#define BKP_DR25 ((uint16_t)0x0078) -#define BKP_DR26 ((uint16_t)0x007C) -#define BKP_DR27 ((uint16_t)0x0080) -#define BKP_DR28 ((uint16_t)0x0084) -#define BKP_DR29 ((uint16_t)0x0088) -#define BKP_DR30 ((uint16_t)0x008C) -#define BKP_DR31 ((uint16_t)0x0090) -#define BKP_DR32 ((uint16_t)0x0094) -#define BKP_DR33 ((uint16_t)0x0098) -#define BKP_DR34 ((uint16_t)0x009C) -#define BKP_DR35 ((uint16_t)0x00A0) -#define BKP_DR36 ((uint16_t)0x00A4) -#define BKP_DR37 ((uint16_t)0x00A8) -#define BKP_DR38 ((uint16_t)0x00AC) -#define BKP_DR39 ((uint16_t)0x00B0) -#define BKP_DR40 ((uint16_t)0x00B4) -#define BKP_DR41 ((uint16_t)0x00B8) -#define BKP_DR42 ((uint16_t)0x00BC) - -#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ - ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ - ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ - ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ - ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ - ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ - ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ - ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ - ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ - ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ - ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ - ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ - ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ - ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) - -#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Functions - * @{ - */ - -void BKP_DeInit(void); -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); -void BKP_TamperPinCmd(FunctionalState NewState); -void BKP_ITConfig(FunctionalState NewState); -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); -FlagStatus BKP_GetFlagStatus(void); -void BKP_ClearFlag(void); -ITStatus BKP_GetITStatus(void); -void BKP_ClearITPendingBit(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_BKP_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h deleted file mode 100644 index 648f747c..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h +++ /dev/null @@ -1,697 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_can.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the CAN firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CAN_H -#define __STM32F10x_CAN_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/** @defgroup CAN_Exported_Types - * @{ - */ - -#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ - ((PERIPH) == CAN2)) - -/** - * @brief CAN init structure definition - */ - -typedef struct -{ - uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. - It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of - @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of - @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit - Segment 2. - This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered - communication mode. This parameter can be set - either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off - management. This parameter can be set either - to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or - DISABLE. */ - - FunctionalState CAN_NART; /*!< Enable or disable the no-automatic - retransmission mode. This parameter can be - set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE - or DISABLE. */ - - FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE - or DISABLE. */ -} CAN_InitTypeDef; - -/** - * @brief CAN filter init structure definition - */ - -typedef struct -{ - uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/** - * @brief CAN Tx message structure definition - */ - -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be - transmitted. This parameter can be a value between - 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ -} CanTxMsg; - -/** - * @brief CAN Rx message structure definition - */ - -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t FMI; /*!< Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanRxMsg; - -/** - * @} - */ - -/** @defgroup CAN_Exported_Constants - * @{ - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ - -#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ - -/** - * @} - */ - -/** @defgroup CAN_Mode - * @{ - */ - -#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ - ((MODE) == CAN_Mode_LoopBack)|| \ - ((MODE) == CAN_Mode_Silent) || \ - ((MODE) == CAN_Mode_Silent_LoopBack)) -/** - * @} - */ - - -/** - * @defgroup CAN_Operating_Mode - * @{ - */ -#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ -#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ -#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ - - -#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ - ((MODE) == CAN_OperatingMode_Normal)|| \ - ((MODE) == CAN_OperatingMode_Sleep)) -/** - * @} - */ - -/** - * @defgroup CAN_Mode_Status - * @{ - */ - -#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ -#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ - - -/** - * @} - */ - -/** @defgroup CAN_synchronisation_jump_width - * @{ - */ - -#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ - ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 - * @{ - */ - -#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 - * @{ - */ - -#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) - -/** - * @} - */ - -/** @defgroup CAN_clock_prescaler - * @{ - */ - -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) - -/** - * @} - */ - -/** @defgroup CAN_filter_number - * @{ - */ -#ifndef STM32F10X_CL - #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) -#else - #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup CAN_filter_mode - * @{ - */ - -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ - -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ - ((MODE) == CAN_FilterMode_IdList)) -/** - * @} - */ - -/** @defgroup CAN_filter_scale - * @{ - */ - -#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ - -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ - ((SCALE) == CAN_FilterScale_32bit)) - -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO - * @{ - */ - -#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ - ((FIFO) == CAN_FilterFIFO1)) -/** - * @} - */ - -/** @defgroup Start_bank_filter_for_slave_CAN - * @{ - */ -#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) -/** - * @} - */ - -/** @defgroup CAN_Tx - * @{ - */ - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - -/** - * @} - */ - -/** @defgroup CAN_identifier_type - * @{ - */ - -#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ - ((IDTYPE) == CAN_Id_Extended)) -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request - * @{ - */ - -#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) - -/** - * @} - */ - -/** @defgroup CAN_transmit_constants - * @{ - */ - -#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ -#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ - -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number_constants - * @{ - */ - -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) - -/** - * @} - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ - -#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ -#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ - -/** - * @} - */ - -/** @defgroup CAN_wake_up_constants - * @{ - */ - -#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ -#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ - -/** - * @} - */ - -/** - * @defgroup CAN_Error_Code_constants - * @{ - */ - -#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ -#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ -#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ -#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ -#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ -#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ -#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ -#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ - - -/** - * @} - */ - -/** @defgroup CAN_flags - * @{ - */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ - -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ - -/* Receive Flags */ -#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ -#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ -#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ -/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ - -/* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ -#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ - -#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ - ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ - ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ - ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_SLAK )) - -#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ - ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) -/** - * @} - */ - - -/** @defgroup CAN_interrupts - * @{ - */ - - - -#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ - -/* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ -#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ - -/* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ -#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ -#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ -#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ -#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ - -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME - - -#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -/** - * @} - */ - -/** @defgroup CAN_Legacy - * @{ - */ -#define CANINITFAILED CAN_InitStatus_Failed -#define CANINITOK CAN_InitStatus_Success -#define CAN_FilterFIFO0 CAN_Filter_FIFO0 -#define CAN_FilterFIFO1 CAN_Filter_FIFO1 -#define CAN_ID_STD CAN_Id_Standard -#define CAN_ID_EXT CAN_Id_Extended -#define CAN_RTR_DATA CAN_RTR_Data -#define CAN_RTR_REMOTE CAN_RTR_Remote -#define CANTXFAILE CAN_TxStatus_Failed -#define CANTXOK CAN_TxStatus_Ok -#define CANTXPENDING CAN_TxStatus_Pending -#define CAN_NO_MB CAN_TxStatus_NoMailBox -#define CANSLEEPFAILED CAN_Sleep_Failed -#define CANSLEEPOK CAN_Sleep_Ok -#define CANWAKEUPFAILED CAN_WakeUp_Failed -#define CANWAKEUPOK CAN_WakeUp_Ok - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup CAN_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions - * @{ - */ -/* Function used to set the CAN configuration to the default reset state *****/ -void CAN_DeInit(CAN_TypeDef* CANx); - -/* Initialization and Configuration functions *********************************/ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); - -/* Transmit functions *********************************************************/ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); - -/* Receive functions **********************************************************/ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); - - -/* Operation modes functions **************************************************/ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); -uint8_t CAN_Sleep(CAN_TypeDef* CANx); -uint8_t CAN_WakeUp(CAN_TypeDef* CANx); - -/* Error management functions *************************************************/ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); - -/* Interrupts and flags management functions **********************************/ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CAN_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h deleted file mode 100644 index a3f8fc78..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h +++ /dev/null @@ -1,210 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_cec.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the CEC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CEC_H -#define __STM32F10x_CEC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CEC - * @{ - */ - - -/** @defgroup CEC_Exported_Types - * @{ - */ - -/** - * @brief CEC Init structure definition - */ -typedef struct -{ - uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. - This parameter can be a value of @ref CEC_BitTiming_Mode */ - uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. - This parameter can be a value of @ref CEC_BitPeriod_Mode */ -}CEC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup CEC_Exported_Constants - * @{ - */ - -/** @defgroup CEC_BitTiming_Mode - * @{ - */ -#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ -#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ - -#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ - ((MODE) == CEC_BitTimingErrFreeMode)) -/** - * @} - */ - -/** @defgroup CEC_BitPeriod_Mode - * @{ - */ -#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ -#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ - -#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ - ((MODE) == CEC_BitPeriodFlexibleMode)) -/** - * @} - */ - - -/** @defgroup CEC_interrupts_definition - * @{ - */ -#define CEC_IT_TERR CEC_CSR_TERR -#define CEC_IT_TBTRF CEC_CSR_TBTRF -#define CEC_IT_RERR CEC_CSR_RERR -#define CEC_IT_RBTF CEC_CSR_RBTF -#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ - ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) -/** - * @} - */ - - -/** @defgroup CEC_Own_Address - * @{ - */ -#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) -/** - * @} - */ - -/** @defgroup CEC_Prescaler - * @{ - */ -#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) - -/** - * @} - */ - -/** @defgroup CEC_flags_definition - * @{ - */ - -/** - * @brief ESR register flags - */ -#define CEC_FLAG_BTE ((uint32_t)0x10010000) -#define CEC_FLAG_BPE ((uint32_t)0x10020000) -#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) -#define CEC_FLAG_SBE ((uint32_t)0x10080000) -#define CEC_FLAG_ACKE ((uint32_t)0x10100000) -#define CEC_FLAG_LINE ((uint32_t)0x10200000) -#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) - -/** - * @brief CSR register flags - */ -#define CEC_FLAG_TEOM ((uint32_t)0x00000002) -#define CEC_FLAG_TERR ((uint32_t)0x00000004) -#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) -#define CEC_FLAG_RSOM ((uint32_t)0x00000010) -#define CEC_FLAG_REOM ((uint32_t)0x00000020) -#define CEC_FLAG_RERR ((uint32_t)0x00000040) -#define CEC_FLAG_RBTF ((uint32_t)0x00000080) - -#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) - -#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ - ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ - ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ - ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ - ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ - ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ - ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup CEC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CEC_Exported_Functions - * @{ - */ -void CEC_DeInit(void); -void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); -void CEC_Cmd(FunctionalState NewState); -void CEC_ITConfig(FunctionalState NewState); -void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); -void CEC_SetPrescaler(uint16_t CEC_Prescaler); -void CEC_SendDataByte(uint8_t Data); -uint8_t CEC_ReceiveDataByte(void); -void CEC_StartOfMessage(void); -void CEC_EndOfMessageCmd(FunctionalState NewState); -FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); -void CEC_ClearFlag(uint32_t CEC_FLAG); -ITStatus CEC_GetITStatus(uint8_t CEC_IT); -void CEC_ClearITPendingBit(uint16_t CEC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CEC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h deleted file mode 100644 index 658a51ce..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_crc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CRC_H -#define __STM32F10x_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/** @defgroup CRC_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Functions - * @{ - */ - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CRC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h deleted file mode 100644 index 71061641..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h +++ /dev/null @@ -1,317 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dac.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DAC_H -#define __STM32F10x_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/** @defgroup DAC_Exported_Types - * @{ - */ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel - only in High-density devices*/ -#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel - only in Connectivity line, Medium-density and Low-density Value Line devices */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel - only in Medium-density and Low-density Value Line devices*/ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignment - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/** @defgroup DAC_interrupts_definition - * @{ - */ - -#define DAC_IT_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ -#endif - -/** - * @} - */ - -/** @defgroup DAC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions - * @{ - */ - -void DAC_DeInit(void); -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -#endif -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_DAC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h deleted file mode 100644 index 1e6a68ac..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dbgmcu.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the DBGMCU - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DBGMCU_H -#define __STM32F10x_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DBGMCU - * @{ - */ - -/** @defgroup DBGMCU_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ - -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) -#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) -#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) -#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) -#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) -#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) -#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) -#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) -#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) -#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) -#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) -#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) -#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) -#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) - -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Functions - * @{ - */ - -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_DBGMCU_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h deleted file mode 100644 index a1ab7d03..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h +++ /dev/null @@ -1,184 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_exti.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the EXTI firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_EXTI_H -#define __STM32F10x_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/** @defgroup EXTI_Exported_Types - * @{ - */ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS - Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ - -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) - - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions - * @{ - */ - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_EXTI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h deleted file mode 100644 index f46d4e87..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h +++ /dev/null @@ -1,426 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_flash.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_FLASH_H -#define __STM32F10x_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @defgroup FLASH_Exported_Types - * @{ - */ - -/** - * @brief FLASH Status - */ - -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT -}FLASH_Status; - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ - -#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2)) -/** - * @} - */ - -/** @defgroup Half_Cycle_Enable_Disable - * @{ - */ - -#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ -#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ -#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ - ((STATE) == FLASH_HalfCycleAccess_Disable)) -/** - * @} - */ - -/** @defgroup Prefetch_Buffer_Enable_Disable - * @{ - */ - -#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ -#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ -#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ - ((STATE) == FLASH_PrefetchBuffer_Disable)) -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ - -/* Values to be used with STM32 Low and Medium density devices */ -#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ -#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ -#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ -#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ -#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ -#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ -#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ -#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ - -/* Values to be used with STM32 Medium-density devices */ -#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ -#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ -#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ -#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ -#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ -#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ -#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ -#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ -#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ -#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ -#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ -#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ -#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ -#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ -#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ -#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ -#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ -#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ -#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ -#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ -#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ -#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ -#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ -#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ - -/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ -#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 0 to 1 */ -#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 2 to 3 */ -#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 4 to 5 */ -#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 6 to 7 */ -#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 8 to 9 */ -#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 10 to 11 */ -#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 12 to 13 */ -#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 14 to 15 */ -#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 16 to 17 */ -#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 18 to 19 */ -#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 20 to 21 */ -#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 22 to 23 */ -#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 24 to 25 */ -#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 26 to 27 */ -#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 28 to 29 */ -#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 30 to 31 */ -#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 32 to 33 */ -#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 34 to 35 */ -#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 36 to 37 */ -#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 38 to 39 */ -#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 40 to 41 */ -#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 42 to 43 */ -#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 44 to 45 */ -#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 46 to 47 */ -#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 48 to 49 */ -#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 50 to 51 */ -#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 52 to 53 */ -#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 54 to 55 */ -#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 56 to 57 */ -#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 58 to 59 */ -#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 60 to 61 */ -#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ -#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ -#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ - -#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ - -#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) - -#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) - -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_IWatchdog - * @{ - */ - -#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STOP - * @{ - */ - -#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STDBY - * @{ - */ - -#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) - -#ifdef STM32F10X_XL -/** - * @} - */ -/** @defgroup FLASH_Boot - * @{ - */ -#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position - and this parameter is selected the device will boot from Bank1(Default) */ -#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position - and this parameter is selected the device will boot from Bank 2 or Bank 1, - depending on the activation of the bank */ -#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) -#endif -/** - * @} - */ -/** @defgroup FLASH_Interrupts - * @{ - */ -#ifdef STM32F10X_XL -#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ -#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ - -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ - -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) -#else -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ - -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) -#endif - -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ -#ifdef STM32F10X_XL -#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ -#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ -#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ -#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ - -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ - ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_OPTERR)|| \ - ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) -#else -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ - ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_OPTERR)) -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions - * @{ - */ - -/*------------ Functions used for all STM32F10x devices -----*/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); -uint32_t FLASH_GetUserOptionByte(void); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -FlagStatus FLASH_GetPrefetchBufferStatus(void); -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); - -/*------------ New function used for all STM32F10x devices -----*/ -void FLASH_UnlockBank1(void); -void FLASH_LockBank1(void); -FLASH_Status FLASH_EraseAllBank1Pages(void); -FLASH_Status FLASH_GetBank1Status(void); -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); - -#ifdef STM32F10X_XL -/*---- New Functions used only with STM32F10x_XL density devices -----*/ -void FLASH_UnlockBank2(void); -void FLASH_LockBank2(void); -FLASH_Status FLASH_EraseAllBank2Pages(void); -FLASH_Status FLASH_GetBank2Status(void); -FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); -FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_FLASH_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h deleted file mode 100644 index ee707e74..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h +++ /dev/null @@ -1,733 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_fsmc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the FSMC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_FSMC_H -#define __STM32F10x_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FSMC - * @{ - */ - -/** @defgroup FSMC_Exported_Types - * @{ - */ - -/** - * @brief Timing parameters For NOR/SRAM Banks - */ - -typedef struct -{ - uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 0xF. - @note: It is not used with synchronous NOR Flash memories. */ - - uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 0 and 0xF. - @note: It is not used with synchronous NOR Flash memories.*/ - - uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 0 and 0xFF. - @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 0xF. - @note: It is only used for multiplexed NOR Flash memories. */ - - uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 0xF. - @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The value of this parameter depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 0xF in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ -}FSMC_NORSRAMTimingInitTypeDef; - -/** - * @brief FSMC NOR/SRAM Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the databus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_Data_Width */ - - uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ - - uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ - - uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ -}FSMC_NORSRAMInitTypeDef; - -/** - * @brief Timing parameters For FSMC NAND and PCCARD Banks - */ - -typedef struct -{ - uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 0xFF.*/ - - uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command deassertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - databus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ -}FSMC_NAND_PCCARDTimingInitTypeDef; - -/** - * @brief FSMC NAND Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_Data_Width */ - - uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ - - uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ -}FSMC_NANDInitTypeDef; - -/** - * @brief FSMC PCCARD Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ -}FSMC_PCCARDInitTypeDef; - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Constants - * @{ - */ - -/** @defgroup FSMC_NORSRAM_Bank - * @{ - */ -#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) -#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) -#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) -#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup FSMC_NAND_Bank - * @{ - */ -#define FSMC_Bank2_NAND ((uint32_t)0x00000010) -#define FSMC_Bank3_NAND ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup FSMC_PCCARD_Bank - * @{ - */ -#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) -/** - * @} - */ - -#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ - ((BANK) == FSMC_Bank1_NORSRAM2) || \ - ((BANK) == FSMC_Bank1_NORSRAM3) || \ - ((BANK) == FSMC_Bank1_NORSRAM4)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND)) - -#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -/** @defgroup NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FSMC_Data_Address_Bus_Multiplexing - * @{ - */ - -#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) -#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ - ((MUX) == FSMC_DataAddressMux_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Memory_Type - * @{ - */ - -#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) -#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ - ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ - ((MEMORY) == FSMC_MemoryType_NOR)) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Width - * @{ - */ - -#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) -#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ - ((WIDTH) == FSMC_MemoryDataWidth_16b)) - -/** - * @} - */ - -/** @defgroup FSMC_Burst_Access_Mode - * @{ - */ - -#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) -#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ - ((STATE) == FSMC_BurstAccessMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_AsynchronousWait - * @{ - */ -#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) -#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) -#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ - ((STATE) == FSMC_AsynchronousWait_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal_Polarity - * @{ - */ - -#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) -#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ - ((POLARITY) == FSMC_WaitSignalPolarity_High)) - -/** - * @} - */ - -/** @defgroup FSMC_Wrap_Mode - * @{ - */ - -#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) -#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ - ((MODE) == FSMC_WrapMode_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Timing - * @{ - */ - -#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ - ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) - -/** - * @} - */ - -/** @defgroup FSMC_Write_Operation - * @{ - */ - -#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) -#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ - ((OPERATION) == FSMC_WriteOperation_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal - * @{ - */ - -#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) -#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ - ((SIGNAL) == FSMC_WaitSignal_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Extended_Mode - * @{ - */ - -#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ - ((MODE) == FSMC_ExtendedMode_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Write_Burst - * @{ - */ - -#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) -#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ - ((BURST) == FSMC_WriteBurst_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time - * @{ - */ - -#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time - * @{ - */ - -#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Setup_Time - * @{ - */ - -#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) - -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration - * @{ - */ - -#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_CLK_Division - * @{ - */ - -#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Latency - * @{ - */ - -#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Access_Mode - * @{ - */ - -#define FSMC_AccessMode_A ((uint32_t)0x00000000) -#define FSMC_AccessMode_B ((uint32_t)0x10000000) -#define FSMC_AccessMode_C ((uint32_t)0x20000000) -#define FSMC_AccessMode_D ((uint32_t)0x30000000) -#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ - ((MODE) == FSMC_AccessMode_B) || \ - ((MODE) == FSMC_AccessMode_C) || \ - ((MODE) == FSMC_AccessMode_D)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup FSMC_Wait_feature - * @{ - */ - -#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ - ((FEATURE) == FSMC_Waitfeature_Enable)) - -/** - * @} - */ - - -/** @defgroup FSMC_ECC - * @{ - */ - -#define FSMC_ECC_Disable ((uint32_t)0x00000000) -#define FSMC_ECC_Enable ((uint32_t)0x00000040) -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ - ((STATE) == FSMC_ECC_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_ECC_Page_Size - * @{ - */ - -#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_8192Bytes)) - -/** - * @} - */ - -/** @defgroup FSMC_TCLR_Setup_Time - * @{ - */ - -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_TAR_Setup_Time - * @{ - */ - -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Setup_Time - * @{ - */ - -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Setup_Time - * @{ - */ - -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Hold_Setup_Time - * @{ - */ - -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_HiZ_Setup_Time - * @{ - */ - -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Interrupt_sources - * @{ - */ - -#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FSMC_IT_Level ((uint32_t)0x00000010) -#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) -#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ - ((IT) == FSMC_IT_Level) || \ - ((IT) == FSMC_IT_FallingEdge)) -/** - * @} - */ - -/** @defgroup FSMC_Flags - * @{ - */ - -#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FSMC_FLAG_Level ((uint32_t)0x00000002) -#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ - ((FLAG) == FSMC_FLAG_Level) || \ - ((FLAG) == FSMC_FLAG_FallingEdge) || \ - ((FLAG) == FSMC_FLAG_FEMPT)) - -#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Functions - * @{ - */ - -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); -void FSMC_NANDDeInit(uint32_t FSMC_Bank); -void FSMC_PCCARDDeInit(void); -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_PCCARDCmd(FunctionalState NewState); -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); -uint32_t FSMC_GetECC(uint32_t FSMC_Bank); -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_FSMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h deleted file mode 100644 index b8aa49a2..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h +++ /dev/null @@ -1,385 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_gpio.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the GPIO - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_GPIO_H -#define __STM32F10x_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/** @defgroup GPIO_Exported_Types - * @{ - */ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF) || \ - ((PERIPH) == GPIOG)) - -/** - * @brief Output Maximum frequency selection - */ - -typedef enum -{ - GPIO_Speed_10MHz = 1, - GPIO_Speed_2MHz, - GPIO_Speed_50MHz -}GPIOSpeed_TypeDef; -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ - ((SPEED) == GPIO_Speed_50MHz)) - -/** - * @brief Configuration Mode enumeration - */ - -typedef enum -{ GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 -}GPIOMode_TypeDef; - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ - ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ - ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ - ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) - -/** - * @brief GPIO Init structure definition - */ - -typedef struct -{ - uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -}GPIO_InitTypeDef; - - -/** - * @brief Bit_SET and Bit_RESET enumeration - */ - -typedef enum -{ Bit_RESET = 0, - Bit_SET -}BitAction; - -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ - -#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ - -#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) - -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) - -/** - * @} - */ - -/** @defgroup GPIO_Remap_define - * @{ - */ - -#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ -#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ -#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ -#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ -#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ -#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ -#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ -#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ -#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ -#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ -#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ -#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ -#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ -#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ -#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ -#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected - to TIM2 Internal Trigger 1 for calibration - (only for Connectivity line devices) */ -#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ - -#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ - -#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ -#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ -#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ - -#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ -#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ -#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, - only for High density Value line devices) */ - -#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ - ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ - ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ - ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ - ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ - ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ - ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ - ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ - ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ - ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ - ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ - ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ - ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ - ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ - ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ - ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ - ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ - ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ - ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ - ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ - ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \ - ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) - -/** - * @} - */ - -/** @defgroup GPIO_Port_Sources - * @{ - */ - -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOB ((uint8_t)0x01) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) -#define GPIO_PortSourceGPIOD ((uint8_t)0x03) -#define GPIO_PortSourceGPIOE ((uint8_t)0x04) -#define GPIO_PortSourceGPIOF ((uint8_t)0x05) -#define GPIO_PortSourceGPIOG ((uint8_t)0x06) -#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOE)) - -#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOG)) - -/** - * @} - */ - -/** @defgroup GPIO_Pin_sources - * @{ - */ - -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) - -/** - * @} - */ - -/** @defgroup Ethernet_Media_Interface - * @{ - */ -#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) -#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) - -#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ - ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) - -/** - * @} - */ -/** - * @} - */ - -/** @defgroup GPIO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions - * @{ - */ - -void GPIO_DeInit(GPIO_TypeDef* GPIOx); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_EventOutputCmd(FunctionalState NewState); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_GPIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h deleted file mode 100644 index 2d42e5ce..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h +++ /dev/null @@ -1,684 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_i2c.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_I2C_H -#define __STM32F10x_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Exported_Types - * @{ - */ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/** - * @} - */ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2)) -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode - * @{ - */ - -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ - ((CYCLE) == I2C_DutyCycle_2)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) -#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ - ((STATE) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_DR ((uint8_t)0x10) -#define I2C_Register_SR1 ((uint8_t)0x14) -#define I2C_Register_SR2 ((uint8_t)0x18) -#define I2C_Register_CCR ((uint8_t)0x1C) -#define I2C_Register_TRISE ((uint8_t)0x20) -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_DR) || \ - ((REGISTER) == I2C_Register_SR1) || \ - ((REGISTER) == I2C_Register_SR2) || \ - ((REGISTER) == I2C_Register_CCR) || \ - ((REGISTER) == I2C_Register_TRISE)) -/** - * @} - */ - -/** @defgroup I2C_SMBus_alert_pin_level - * @{ - */ - -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) -#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ - ((ALERT) == I2C_SMBusAlert_High)) -/** - * @} - */ - -/** @defgroup I2C_PEC_position - * @{ - */ - -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ - ((POSITION) == I2C_PECPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_NCAK_position - * @{ - */ - -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ - ((POSITION) == I2C_NACKPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ - ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ - ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ - ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -/** - * @brief SR2 register flags - */ - -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/** - * @brief SR1 register flags - */ - -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ - ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ - ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ - ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ - ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ - ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ - ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ - ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_SB)) -/** - * @} - */ - -/** @defgroup I2C_Events - * @{ - */ - -/*======================================== - - I2C Master Events (Events grouped in order of communication) - ==========================================*/ -/** - * @brief Communication start - * - * After sending the START condition (I2C_GenerateSTART() function) the master - * has to wait for this event. It means that the Start condition has been correctly - * released on the I2C bus (the bus is free, no other devices is communicating). - * - */ -/* --EV5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/** - * @brief Address Acknowledge - * - * After checking on EV5 (start condition correctly released on the bus), the - * master sends the address of the slave(s) with which it will communicate - * (I2C_Send7bitAddress() function, it also determines the direction of the communication: - * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will - * be set: - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (just after generating the START - * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() - * function). Then master should wait on EV9. It means that the 10-bit addressing - * header has been correctly sent on the bus. Then master should send the second part of - * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master - * should wait for event EV6. - * - */ - -/* --EV6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* --EV9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/** - * @brief Communication events - * - * If a communication is established (START condition generated and slave address - * acknowledged) then the master has to check on one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EV7 then to read - * the data received from the slave (I2C_ReceiveData() function). - * - * 2) Master Transmitter mode: The master has to send data (I2C_SendData() - * function) then to wait on event EV8 or EV8_2. - * These two events are similar: - * - EV8 means that the data has been written in the data register and is - * being shifted out. - * - EV8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EV8 is sufficient for the application. - * Using EV8_2 leads to a slower communication but ensure more reliable test. - * EV8_2 is also more suitable than EV8 for testing on the last data transmission - * (before Stop condition generation). - * - * @note In case the user software does not guarantee that this event EV7 is - * managed before the current byte end of transfer, then user may check on EV7 - * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Master RECEIVER mode -----------------------------*/ -/* --EV7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master TRANSMITTER mode --------------------------*/ -/* --EV8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* --EV8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - - -/*======================================== - - I2C Slave Events (Events grouped in order of communication) - ==========================================*/ - -/** - * @brief Communication start events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a Start condition on the bus (generated by master - * device) followed by the peripheral address. The peripheral generates an ACK - * condition on the bus (if the acknowledge feature is enabled through function - * I2C_AcknowledgeConfig()) and the events listed above are set : - * - * 1) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * 2) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * 3) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* --EV1 (all the events below are variants of EV1) */ -/* 1) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* 2) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* 3) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/** - * @brief Communication events - * - * Wait on one of these events when EV1 has already been checked and: - * - * - Slave RECEIVER mode: - * - EV2: When the application is expecting a data byte to be received. - * - EV4: When the application is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EV3: When a byte has been transmitted by the slave and the application is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be - * used when the user software doesn't guarantee the EV3 is managed before the - * current byte end of transfer. - * - EV3_2: When the master sends a NACK in order to tell slave that data transmission - * shall end (before sending the STOP condition). In this case slave has to stop sending - * data bytes and expect a Stop condition on the bus. - * - * @note In case the user software does not guarantee that the event EV2 is - * managed before the current byte end of transfer, then user may check on EV2 - * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Slave RECEIVER mode --------------------------*/ -/* --EV2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* --EV4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave TRANSMITTER mode -----------------------*/ -/* --EV3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* --EV3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -/*=========================== End of Events Description ==========================================*/ - -#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ - ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ - ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) -/** - * @} - */ - -/** @defgroup I2C_clock_speed - * @{ - */ - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions - * @{ - */ - -void I2C_DeInit(I2C_TypeDef* I2Cx); -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); - -/** - * @brief - **************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * depending on the application requirements and constraints: - * - * - * 1) Basic state monitoring: - * Using I2C_CheckEvent() function: - * It compares the status registers (SR1 and SR2) content to a given event - * (can be the combination of one or more flags). - * It returns SUCCESS if the current status includes the given flags - * and returns ERROR if one or more flags are missing in the current status. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (RM0008). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs (ie. error flags are set besides to the monitored flags), - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * hold or corrupted real state. - * In this case, it is advised to use error interrupts to monitor the error - * events and handle them in the interrupt IRQ handler. - * - * @note - * For error management, it is advised to use the following functions: - * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() - * in order to determine which error occurred. - * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - * and/or I2C_GenerateStop() in order to clear the error flag and source, - * and return to correct communication status. - * - * - * 2) Advanced state monitoring: - * Using the function I2C_GetLastEvent() which returns the image of both status - * registers in a single word (uint32_t) (Status Register 2 value is shifted left - * by 16 bits and concatenated to Status Register 1). - * - When to use: - * - This function is suitable for the same applications above but it allows to - * overcome the limitations of I2C_GetFlagStatus() function (see below). - * The returned value could be compared to events already defined in the - * library (stm32f10x_i2c.h) or to custom values defined by user. - * - This function is suitable when multiple flags are monitored at the same time. - * - At the opposite of I2C_CheckEvent() function, this function allows user to - * choose when an event is accepted (when all events flags are set and no - * other flags are set or just when the needed flags are set like - * I2C_CheckEvent() function). - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * 3) Flag-based state monitoring: - * Using the function I2C_GetFlagStatus() which simply returns the status of - * one single flag (ie. I2C_FLAG_RXNE ...). - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed (most I2C events - * are monitored through multiple flags). - * - Limitations: - * - When calling this function, the Status register is accessed. Some flags are - * cleared when the status register is accessed. So checking the status - * of one Flag, may clear other ones. - * - Function may need to be called twice or more in order to monitor one - * single event. - * - */ - -/** - * - * 1) Basic state monitoring - ******************************************************************************* - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/** - * - * 2) Advanced state monitoring - ******************************************************************************* - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/** - * - * 3) Flag-based state monitoring - ******************************************************************************* - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -/** - * - ******************************************************************************* - */ - -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_I2C_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h deleted file mode 100644 index 76e6ce91..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_pwr.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_PWR_H -#define __STM32F10x_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/** @defgroup PWR_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PVD_detection_level - * @{ - */ - -#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) -#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) -#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) -#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) -#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) -#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) -#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) -#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ - ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ - ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ - ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) -/** - * @} - */ - -/** @defgroup Regulator_state_is_STOP_mode - * @{ - */ - -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower ((uint32_t)0x00000001) -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) -/** - * @} - */ - -/** @defgroup STOP_mode_entry - * @{ - */ - -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ - -#define PWR_FLAG_WU ((uint32_t)0x00000001) -#define PWR_FLAG_SB ((uint32_t)0x00000002) -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions - * @{ - */ - -void PWR_DeInit(void); -void PWR_BackupAccessCmd(FunctionalState NewState); -void PWR_PVDCmd(FunctionalState NewState); -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_WakeUpPinCmd(FunctionalState NewState); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_PWR_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h deleted file mode 100644 index b3b7d821..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h +++ /dev/null @@ -1,727 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rcc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the RCC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_RCC_H -#define __STM32F10x_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/** @defgroup RCC_Exported_Types - * @{ - */ - -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ - uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/** - * @} - */ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup HSE_configuration - * @{ - */ - -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00010000) -#define RCC_HSE_Bypass ((uint32_t)0x00040000) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) - -/** - * @} - */ - -/** @defgroup PLL_entry_clock_source - * @{ - */ - -#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) - #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) - #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) - #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div2)) -#else - #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) - #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_PREDIV1)) -#endif /* STM32F10X_CL */ - -/** - * @} - */ - -/** @defgroup PLL_multiplication_factor - * @{ - */ -#ifndef STM32F10X_CL - #define RCC_PLLMul_2 ((uint32_t)0x00000000) - #define RCC_PLLMul_3 ((uint32_t)0x00040000) - #define RCC_PLLMul_4 ((uint32_t)0x00080000) - #define RCC_PLLMul_5 ((uint32_t)0x000C0000) - #define RCC_PLLMul_6 ((uint32_t)0x00100000) - #define RCC_PLLMul_7 ((uint32_t)0x00140000) - #define RCC_PLLMul_8 ((uint32_t)0x00180000) - #define RCC_PLLMul_9 ((uint32_t)0x001C0000) - #define RCC_PLLMul_10 ((uint32_t)0x00200000) - #define RCC_PLLMul_11 ((uint32_t)0x00240000) - #define RCC_PLLMul_12 ((uint32_t)0x00280000) - #define RCC_PLLMul_13 ((uint32_t)0x002C0000) - #define RCC_PLLMul_14 ((uint32_t)0x00300000) - #define RCC_PLLMul_15 ((uint32_t)0x00340000) - #define RCC_PLLMul_16 ((uint32_t)0x00380000) - #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ - ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ - ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ - ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ - ((MUL) == RCC_PLLMul_16)) - -#else - #define RCC_PLLMul_4 ((uint32_t)0x00080000) - #define RCC_PLLMul_5 ((uint32_t)0x000C0000) - #define RCC_PLLMul_6 ((uint32_t)0x00100000) - #define RCC_PLLMul_7 ((uint32_t)0x00140000) - #define RCC_PLLMul_8 ((uint32_t)0x00180000) - #define RCC_PLLMul_9 ((uint32_t)0x001C0000) - #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) - - #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_6_5)) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup PREDIV1_division_factor - * @{ - */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) - #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) - #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) - #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) - #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) - #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) - #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) - #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) - #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) - #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) - #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) - #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) - #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) - #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) - #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) - #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) - #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) - - #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ - ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ - ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ - ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ - ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ - ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ - ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ - ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) -#endif -/** - * @} - */ - - -/** @defgroup PREDIV1_clock_source - * @{ - */ -#ifdef STM32F10X_CL -/* PREDIV1 clock source (for STM32 connectivity line devices) */ - #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) - #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) - - #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ - ((SOURCE) == RCC_PREDIV1_Source_PLL2)) -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/* PREDIV1 clock source (for STM32 Value line devices) */ - #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) - - #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) -#endif -/** - * @} - */ - -#ifdef STM32F10X_CL -/** @defgroup PREDIV2_division_factor - * @{ - */ - - #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) - #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) - #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) - #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) - #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) - #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) - #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) - #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) - #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) - #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) - #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) - #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) - #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) - #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) - #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) - #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) - - #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ - ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ - ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ - ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ - ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ - ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ - ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ - ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) -/** - * @} - */ - - -/** @defgroup PLL2_multiplication_factor - * @{ - */ - - #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) - #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) - #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) - #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) - #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) - #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) - #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) - #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) - #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) - - #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ - ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ - ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ - ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ - ((MUL) == RCC_PLL2Mul_20)) -/** - * @} - */ - - -/** @defgroup PLL3_multiplication_factor - * @{ - */ - - #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) - #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) - #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) - #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) - #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) - #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) - #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) - #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) - #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) - - #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ - ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ - ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ - ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ - ((MUL) == RCC_PLL3Mul_20)) -/** - * @} - */ - -#endif /* STM32F10X_CL */ - - -/** @defgroup System_clock_source - * @{ - */ - -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup AHB_clock_source - * @{ - */ - -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup APB1_APB2_clock_source - * @{ - */ - -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00000400) -#define RCC_HCLK_Div4 ((uint32_t)0x00000500) -#define RCC_HCLK_Div8 ((uint32_t)0x00000600) -#define RCC_HCLK_Div16 ((uint32_t)0x00000700) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt_source - * @{ - */ - -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) - -#ifndef STM32F10X_CL - #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) - #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) - #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) -#else - #define RCC_IT_PLL2RDY ((uint8_t)0x20) - #define RCC_IT_PLL3RDY ((uint8_t)0x40) - #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) - #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) - #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) -#endif /* STM32F10X_CL */ - - -/** - * @} - */ - -#ifndef STM32F10X_CL -/** @defgroup USB_Device_clock_source - * @{ - */ - - #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) - #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) - - #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ - ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) -/** - * @} - */ -#else -/** @defgroup USB_OTG_FS_clock_source - * @{ - */ - #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) - #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) - - #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ - ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) -/** - * @} - */ -#endif /* STM32F10X_CL */ - - -#ifdef STM32F10X_CL -/** @defgroup I2S2_clock_source - * @{ - */ - #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) - #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) - - #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ - ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) -/** - * @} - */ - -/** @defgroup I2S3_clock_source - * @{ - */ - #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) - #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) - - #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ - ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) -/** - * @} - */ -#endif /* STM32F10X_CL */ - - -/** @defgroup ADC_clock_source - * @{ - */ - -#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) -#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) -#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) -#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) -#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ - ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) -/** - * @} - */ - -/** @defgroup LSE_configuration - * @{ - */ - -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RTC_clock_source - * @{ - */ - -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) -/** - * @} - */ - -/** @defgroup AHB_peripheral - * @{ - */ - -#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) -#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) -#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) -#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) - -#ifndef STM32F10X_CL - #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) - #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) - #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) -#else - #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) - #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) - #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) - #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) - - #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) - #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup APB2_peripheral - * @{ - */ - -#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) -#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) -#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) -#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) -#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) -#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) -#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) -#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) -#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup APB1_peripheral - * @{ - */ - -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) -#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) -#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_USB ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) - -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup Clock_source_to_output_on_MCO_pin - * @{ - */ - -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) -#define RCC_MCO_HSE ((uint8_t)0x06) -#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) - -#ifndef STM32F10X_CL - #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ - ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ - ((MCO) == RCC_MCO_PLLCLK_Div2)) -#else - #define RCC_MCO_PLL2CLK ((uint8_t)0x08) - #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) - #define RCC_MCO_XT1 ((uint8_t)0x0A) - #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) - - #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ - ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ - ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ - ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ - ((MCO) == RCC_MCO_PLL3CLK)) -#endif /* STM32F10X_CL */ - -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ - -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -#ifndef STM32F10X_CL - #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ - ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ - ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ - ((FLAG) == RCC_FLAG_LPWRRST)) -#else - #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) - #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) - #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ - ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ - ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ - ((FLAG) == RCC_FLAG_LPWRRST)) -#endif /* STM32F10X_CL */ - -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RCC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions - * @{ - */ - -void RCC_DeInit(void); -void RCC_HSEConfig(uint32_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) - void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); -#endif - -#ifdef STM32F10X_CL - void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); - void RCC_PLL2Config(uint32_t RCC_PLL2Mul); - void RCC_PLL2Cmd(FunctionalState NewState); - void RCC_PLL3Config(uint32_t RCC_PLL3Mul); - void RCC_PLL3Cmd(FunctionalState NewState); -#endif /* STM32F10X_CL */ - -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); - -#ifndef STM32F10X_CL - void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); -#else - void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); -#endif /* STM32F10X_CL */ - -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); - -#ifdef STM32F10X_CL - void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); - void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); -#endif /* STM32F10X_CL */ - -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -#ifdef STM32F10X_CL -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -#endif /* STM32F10X_CL */ - -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCO); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_RCC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h deleted file mode 100644 index 214a5893..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rtc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_RTC_H -#define __STM32F10x_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/** @defgroup RTC_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - -/** @defgroup RTC_interrupts_define - * @{ - */ - -#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ -#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ -#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ -#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ - ((IT) == RTC_IT_SEC)) -/** - * @} - */ - -/** @defgroup RTC_interrupts_flags - * @{ - */ - -#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ -#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ -#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ -#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ -#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ -#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ - ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ - ((FLAG) == RTC_FLAG_SEC)) -#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions - * @{ - */ - -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); -void RTC_EnterConfigMode(void); -void RTC_ExitConfigMode(void); -uint32_t RTC_GetCounter(void); -void RTC_SetCounter(uint32_t CounterValue); -void RTC_SetPrescaler(uint32_t PrescalerValue); -void RTC_SetAlarm(uint32_t AlarmValue); -uint32_t RTC_GetDivider(void); -void RTC_WaitForLastTask(void); -void RTC_WaitForSynchro(void); -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); -void RTC_ClearFlag(uint16_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint16_t RTC_IT); -void RTC_ClearITPendingBit(uint16_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_RTC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h deleted file mode 100644 index 40cfdedc..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h +++ /dev/null @@ -1,531 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_sdio.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the SDIO firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_SDIO_H -#define __STM32F10x_SDIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SDIO - * @{ - */ - -/** @defgroup SDIO_Exported_Types - * @{ - */ - -typedef struct -{ - uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDIO_Clock_Edge */ - - uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDIO_Clock_Bypass */ - - uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDIO_Clock_Power_Save */ - - uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. - This parameter can be a value of @ref SDIO_Bus_Wide */ - - uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ - - uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. - This parameter can be a value between 0x00 and 0xFF. */ - -} SDIO_InitTypeDef; - -typedef struct -{ - uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register */ - - uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ - - uint32_t SDIO_Response; /*!< Specifies the SDIO response type. - This parameter can be a value of @ref SDIO_Response_Type */ - - uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. - This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ - - uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_CPSM_State */ -} SDIO_CmdInitTypeDef; - -typedef struct -{ - uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ - - uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ - - uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDIO_Data_Block_Size */ - - uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDIO_Transfer_Direction */ - - uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDIO_Transfer_Type */ - - uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_DPSM_State */ -} SDIO_DataInitTypeDef; - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Constants - * @{ - */ - -/** @defgroup SDIO_Clock_Edge - * @{ - */ - -#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) -#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) -#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ - ((EDGE) == SDIO_ClockEdge_Falling)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Bypass - * @{ - */ - -#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) -#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ - ((BYPASS) == SDIO_ClockBypass_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Power_Save - * @{ - */ - -#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) -#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) -#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ - ((SAVE) == SDIO_ClockPowerSave_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Bus_Wide - * @{ - */ - -#define SDIO_BusWide_1b ((uint32_t)0x00000000) -#define SDIO_BusWide_4b ((uint32_t)0x00000800) -#define SDIO_BusWide_8b ((uint32_t)0x00001000) -#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ - ((WIDE) == SDIO_BusWide_8b)) - -/** - * @} - */ - -/** @defgroup SDIO_Hardware_Flow_Control - * @{ - */ - -#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) -#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) -#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ - ((CONTROL) == SDIO_HardwareFlowControl_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Power_State - * @{ - */ - -#define SDIO_PowerState_OFF ((uint32_t)0x00000000) -#define SDIO_PowerState_ON ((uint32_t)0x00000003) -#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) -/** - * @} - */ - - -/** @defgroup SDIO_Interrupt_sources - * @{ - */ - -#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) -#define SDIO_IT_CMDREND ((uint32_t)0x00000040) -#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_IT_DATAEND ((uint32_t)0x00000100) -#define SDIO_IT_STBITERR ((uint32_t)0x00000200) -#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) -#define SDIO_IT_CMDACT ((uint32_t)0x00000800) -#define SDIO_IT_TXACT ((uint32_t)0x00001000) -#define SDIO_IT_RXACT ((uint32_t)0x00002000) -#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) -#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) -#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) -#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup SDIO_Command_Index - * @{ - */ - -#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) -/** - * @} - */ - -/** @defgroup SDIO_Response_Type - * @{ - */ - -#define SDIO_Response_No ((uint32_t)0x00000000) -#define SDIO_Response_Short ((uint32_t)0x00000040) -#define SDIO_Response_Long ((uint32_t)0x000000C0) -#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ - ((RESPONSE) == SDIO_Response_Short) || \ - ((RESPONSE) == SDIO_Response_Long)) -/** - * @} - */ - -/** @defgroup SDIO_Wait_Interrupt_State - * @{ - */ - -#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ -#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ -#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ -#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ - ((WAIT) == SDIO_Wait_Pend)) -/** - * @} - */ - -/** @defgroup SDIO_CPSM_State - * @{ - */ - -#define SDIO_CPSM_Disable ((uint32_t)0x00000000) -#define SDIO_CPSM_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Response_Registers - * @{ - */ - -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) -#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ - ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) -/** - * @} - */ - -/** @defgroup SDIO_Data_Length - * @{ - */ - -#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) -/** - * @} - */ - -/** @defgroup SDIO_Data_Block_Size - * @{ - */ - -#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) -#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) -#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) -#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) -#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) -#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) -#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) -#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) -#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) -#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) -#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) -#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) -#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) -#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) -#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) -#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ - ((SIZE) == SDIO_DataBlockSize_2b) || \ - ((SIZE) == SDIO_DataBlockSize_4b) || \ - ((SIZE) == SDIO_DataBlockSize_8b) || \ - ((SIZE) == SDIO_DataBlockSize_16b) || \ - ((SIZE) == SDIO_DataBlockSize_32b) || \ - ((SIZE) == SDIO_DataBlockSize_64b) || \ - ((SIZE) == SDIO_DataBlockSize_128b) || \ - ((SIZE) == SDIO_DataBlockSize_256b) || \ - ((SIZE) == SDIO_DataBlockSize_512b) || \ - ((SIZE) == SDIO_DataBlockSize_1024b) || \ - ((SIZE) == SDIO_DataBlockSize_2048b) || \ - ((SIZE) == SDIO_DataBlockSize_4096b) || \ - ((SIZE) == SDIO_DataBlockSize_8192b) || \ - ((SIZE) == SDIO_DataBlockSize_16384b)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Direction - * @{ - */ - -#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) -#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) -#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ - ((DIR) == SDIO_TransferDir_ToSDIO)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Type - * @{ - */ - -#define SDIO_TransferMode_Block ((uint32_t)0x00000000) -#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) -#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ - ((MODE) == SDIO_TransferMode_Block)) -/** - * @} - */ - -/** @defgroup SDIO_DPSM_State - * @{ - */ - -#define SDIO_DPSM_Disable ((uint32_t)0x00000000) -#define SDIO_DPSM_Enable ((uint32_t)0x00000001) -#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Flags - * @{ - */ - -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) -#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) -#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) -#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) -#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_TXUNDERR) || \ - ((FLAG) == SDIO_FLAG_RXOVERR) || \ - ((FLAG) == SDIO_FLAG_CMDREND) || \ - ((FLAG) == SDIO_FLAG_CMDSENT) || \ - ((FLAG) == SDIO_FLAG_DATAEND) || \ - ((FLAG) == SDIO_FLAG_STBITERR) || \ - ((FLAG) == SDIO_FLAG_DBCKEND) || \ - ((FLAG) == SDIO_FLAG_CMDACT) || \ - ((FLAG) == SDIO_FLAG_TXACT) || \ - ((FLAG) == SDIO_FLAG_RXACT) || \ - ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOF) || \ - ((FLAG) == SDIO_FLAG_RXFIFOF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOE) || \ - ((FLAG) == SDIO_FLAG_TXDAVL) || \ - ((FLAG) == SDIO_FLAG_RXDAVL) || \ - ((FLAG) == SDIO_FLAG_SDIOIT) || \ - ((FLAG) == SDIO_FLAG_CEATAEND)) - -#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) - -#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ - ((IT) == SDIO_IT_DCRCFAIL) || \ - ((IT) == SDIO_IT_CTIMEOUT) || \ - ((IT) == SDIO_IT_DTIMEOUT) || \ - ((IT) == SDIO_IT_TXUNDERR) || \ - ((IT) == SDIO_IT_RXOVERR) || \ - ((IT) == SDIO_IT_CMDREND) || \ - ((IT) == SDIO_IT_CMDSENT) || \ - ((IT) == SDIO_IT_DATAEND) || \ - ((IT) == SDIO_IT_STBITERR) || \ - ((IT) == SDIO_IT_DBCKEND) || \ - ((IT) == SDIO_IT_CMDACT) || \ - ((IT) == SDIO_IT_TXACT) || \ - ((IT) == SDIO_IT_RXACT) || \ - ((IT) == SDIO_IT_TXFIFOHE) || \ - ((IT) == SDIO_IT_RXFIFOHF) || \ - ((IT) == SDIO_IT_TXFIFOF) || \ - ((IT) == SDIO_IT_RXFIFOF) || \ - ((IT) == SDIO_IT_TXFIFOE) || \ - ((IT) == SDIO_IT_RXFIFOE) || \ - ((IT) == SDIO_IT_TXDAVL) || \ - ((IT) == SDIO_IT_RXDAVL) || \ - ((IT) == SDIO_IT_SDIOIT) || \ - ((IT) == SDIO_IT_CEATAEND)) - -#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup SDIO_Read_Wait_Mode - * @{ - */ - -#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) -#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) -#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ - ((MODE) == SDIO_ReadWaitMode_DATA2)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Functions - * @{ - */ - -void SDIO_DeInit(void); -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ClockCmd(FunctionalState NewState); -void SDIO_SetPowerState(uint32_t SDIO_PowerState); -uint32_t SDIO_GetPowerState(void); -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); -void SDIO_DMACmd(FunctionalState NewState); -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); -uint8_t SDIO_GetCommandResponse(void); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -uint32_t SDIO_GetDataCounter(void); -uint32_t SDIO_ReadData(void); -void SDIO_WriteData(uint32_t Data); -uint32_t SDIO_GetFIFOCount(void); -void SDIO_StartSDIOReadWait(FunctionalState NewState); -void SDIO_StopSDIOReadWait(FunctionalState NewState); -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -void SDIO_SetSDIOOperation(FunctionalState NewState); -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); -void SDIO_CommandCompletionCmd(FunctionalState NewState); -void SDIO_CEATAITCmd(FunctionalState NewState); -void SDIO_SendCEATACmd(FunctionalState NewState); -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); -void SDIO_ClearFlag(uint32_t SDIO_FLAG); -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); -void SDIO_ClearITPendingBit(uint32_t SDIO_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_SDIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h deleted file mode 100644 index 6056c4c6..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h +++ /dev/null @@ -1,487 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_spi.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the SPI firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_SPI_H -#define __STM32F10x_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Exported_Types - * @{ - */ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/** - * @} - */ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx) || \ - ((MODE) == I2S_Mode_MasterRx) ) -/** - * @} - */ - -/** @defgroup I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) -#define I2S_IT_UDR ((uint8_t)0x53) -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ - ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SPI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions - * @{ - */ - -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_SPI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h deleted file mode 100644 index 61ae249a..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h +++ /dev/null @@ -1,412 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_usart.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_USART_H -#define __STM32F10x_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/** @defgroup USART_Exported_Types - * @{ - */ - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - - uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/** - * @} - */ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4) || \ - ((PERIPH) == UART5)) - -#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3)) - -#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4)) -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_0_5) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) -#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @{ - */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) -#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) - -#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) -#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\ - ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ - || ((USART_FLAG) != USART_FLAG_CTS)) -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) -#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup USART_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Exported_Functions - * @{ - */ - -void USART_DeInit(USART_TypeDef* USARTx); -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); -void USART_SendBreak(USART_TypeDef* USARTx); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_USART_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.c deleted file mode 100644 index ec9165f7..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/misc.c +++ /dev/null @@ -1,225 +0,0 @@ -/** - ****************************************************************************** - * @file misc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "misc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/** @defgroup MISC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_Defines - * @{ - */ - -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) -/** - * @} - */ - -/** @defgroup MISC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM - * @arg NVIC_VectTab_FLASH - * @param Offset: Vector Table base offset field. This value must be a multiple - * of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND - * @arg NVIC_LP_SLEEPDEEP - * @arg NVIC_LP_SLEEPONEXIT - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c deleted file mode 100644 index 916a096d..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c +++ /dev/null @@ -1,1307 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_adc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the ADC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_adc.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/** @defgroup ADC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Defines - * @{ - */ - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CR1_DISCEN_Set ((uint32_t)0x00000800) -#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) - -/* ADC JAUTO mask */ -#define CR1_JAUTO_Set ((uint32_t)0x00000400) -#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) - -/* CR1 register Mask */ -#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) - -/* ADC ADON mask */ -#define CR2_ADON_Set ((uint32_t)0x00000001) -#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CR2_DMA_Set ((uint32_t)0x00000100) -#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF) - -/* ADC RSTCAL mask */ -#define CR2_RSTCAL_Set ((uint32_t)0x00000008) - -/* ADC CAL mask */ -#define CR2_CAL_Set ((uint32_t)0x00000004) - -/* ADC SWSTART mask */ -#define CR2_SWSTART_Set ((uint32_t)0x00400000) - -/* ADC EXTTRIG mask */ -#define CR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTART mask */ -#define CR2_JSWSTART_Set ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) - -/* ADC TSPD mask */ -#define CR2_TSVREFE_Set ((uint32_t)0x00800000) -#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) - -/* CR2 register Mask */ -#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) - -/* ADC SQx mask */ -#define SQR3_SQ_Set ((uint32_t)0x0000001F) -#define SQR2_SQ_Set ((uint32_t)0x0000001F) -#define SQR1_SQ_Set ((uint32_t)0x0000001F) - -/* SQR1 register Mask */ -#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define JSQR_JSQ_Set ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define JSQR_JL_Set ((uint32_t)0x00300000) -#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_Set ((uint32_t)0x00000007) -#define SMPR2_SMP_Set ((uint32_t)0x00000007) - -/* ADC JDRx registers offset */ -#define JDR_Offset ((uint8_t)0x28) - -/* ADC1 DR register base address */ -#define DR_ADDRESS ((uint32_t)0x4001244C) - -/** - * @} - */ - -/** @defgroup ADC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_DeInit(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - if (ADCx == ADC1) - { - /* Enable ADC1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - /* Release ADC1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); - } - else if (ADCx == ADC2) - { - /* Enable ADC2 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); - /* Release ADC2 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); - } - else - { - if (ADCx == ADC3) - { - /* Enable ADC3 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); - /* Release ADC3 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); - } - } -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); - - /*---------------------------- ADCx CR1 Configuration -----------------*/ - /* Get the ADCx CR1 value */ - tmpreg1 = ADCx->CR1; - /* Clear DUALMOD and SCAN bits */ - tmpreg1 &= CR1_CLEAR_Mask; - /* Configure ADCx: Dual mode and scan conversion mode */ - /* Set DUALMOD bits according to ADC_Mode value */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); - /* Write to ADCx CR1 */ - ADCx->CR1 = tmpreg1; - - /*---------------------------- ADCx CR2 Configuration -----------------*/ - /* Get the ADCx CR2 value */ - tmpreg1 = ADCx->CR2; - /* Clear CONT, ALIGN and EXTSEL bits */ - tmpreg1 &= CR2_CLEAR_Mask; - /* Configure ADCx: external trigger event and continuous conversion mode */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - /* Write to ADCx CR2 */ - ADCx->CR2 = tmpreg1; - - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - /* Clear L bits */ - tmpreg1 &= SQR1_CLEAR_Mask; - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfChannel value */ - tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); - tmpreg1 |= (uint32_t)tmpreg2 << 20; - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Reset ADC init structure parameters values */ - /* Initialize the ADC_Mode member */ - ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; - /* initialize the ADC_ScanConvMode member */ - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - /* Initialize the ADC_NbrOfChannel member */ - ADC_InitStruct->ADC_NbrOfChannel = 1; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ADON bit to wake up the ADC from power down mode */ - ADCx->CR2 |= CR2_ADON_Set; - } - else - { - /* Disable the selected ADC peripheral */ - ADCx->CR2 &= CR2_ADON_Reset; - } -} - -/** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1 or 3 to select the ADC peripheral. - * Note: ADC2 hasn't a DMA capability. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_DMA_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CR2 |= CR2_DMA_Set; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CR2 &= CR2_DMA_Reset; - } -} - -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)ADC_IT; - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->CR1 |= itmask; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->CR1 &= (~(uint32_t)itmask); - } -} - -/** - * @brief Resets the selected ADC calibration registers. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_ResetCalibration(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Resets the selected ADC calibration registers */ - ADCx->CR2 |= CR2_RSTCAL_Set; -} - -/** - * @brief Gets the selected ADC reset calibration registers status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC reset calibration registers (SET or RESET). - */ -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of RSTCAL bit */ - if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) - { - /* RSTCAL bit is set */ - bitstatus = SET; - } - else - { - /* RSTCAL bit is reset */ - bitstatus = RESET; - } - /* Return the RSTCAL bit status */ - return bitstatus; -} - -/** - * @brief Starts the selected ADC calibration process. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_StartCalibration(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Enable the selected ADC calibration process */ - ADCx->CR2 |= CR2_CAL_Set; -} - -/** - * @brief Gets the selected ADC calibration status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC calibration (SET or RESET). - */ -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of CAL bit */ - if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) - { - /* CAL bit is set: calibration on going */ - bitstatus = SET; - } - else - { - /* CAL bit is reset: end of calibration */ - bitstatus = RESET; - } - /* Return the CAL bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC software start conversion . - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC software start conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion on external event and start the selected - ADC conversion */ - ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; - } - else - { - /* Disable the selected ADC conversion on external event and stop the selected - ADC conversion */ - ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; - } -} - -/** - * @brief Gets the selected ADC Software start conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) - { - /* SWSTART bit is set */ - bitstatus = SET; - } - else - { - /* SWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the SWSTART bit status */ - return bitstatus; -} - -/** - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Number: specifies the discontinuous mode regular channel - * count value. This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - /* Get the old register value */ - tmpreg1 = ADCx->CR1; - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= CR1_DISCNUM_Reset; - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - /* Store the new register value */ - ADCx->CR1 = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on regular group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CR1 |= CR1_DISCEN_Set; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CR1 &= CR1_DISCEN_Reset; - } -} - -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_REGULAR_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* For Rank 1 to 6 */ - if (Rank < 7) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - /* Calculate the mask to clear */ - tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - /* For Rank 7 to 12 */ - else if (Rank < 13) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - /* Calculate the mask to clear */ - tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - /* For Rank 13 to 16 */ - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - /* Calculate the mask to clear */ - tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } -} - -/** - * @brief Enables or disables the ADCx conversion through external trigger. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC external trigger start of conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion on external event */ - ADCx->CR2 |= CR2_EXTTRIG_Set; - } - else - { - /* Disable the selected ADC conversion on external event */ - ADCx->CR2 &= CR2_EXTTRIG_Reset; - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. - * @retval The Data conversion value. - */ -uint32_t ADC_GetDualModeConversionValue(void) -{ - /* Return the dual mode conversion value */ - return (*(__IO uint32_t *) DR_ADDRESS); -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC auto injected conversion - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CR1 |= CR1_JAUTO_Set; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CR1 &= CR1_JAUTO_Reset; - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on injected group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CR1 |= CR1_JDISCEN_Set; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CR1 &= CR1_JDISCEN_Reset; - } -} - -/** - * @brief Configures the ADCx external trigger for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) - * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) - * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 - * capture compare4 event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not - * by external trigger (for ADC1, ADC2 and ADC3) - * @retval None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external event selection for injected group */ - tmpreg &= CR2_JEXTSEL_Reset; - /* Set the external event selection for injected group */ - tmpreg |= ADC_ExternalTrigInjecConv; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Enables or disables the ADCx injected channels conversion through - * external trigger - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC external trigger start of - * injected conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC external event selection for injected group */ - ADCx->CR2 |= CR2_JEXTTRIG_Set; - } - else - { - /* Disable the selected ADC external event selection for injected group */ - ADCx->CR2 &= CR2_JEXTTRIG_Reset; - } -} - -/** - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC software start injected conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion for injected group on external event and start the selected - ADC injected conversion */ - ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; - } - else - { - /* Disable the selected ADC conversion on external event for injected group and stop the selected - ADC injected conversion */ - ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; - } -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of JSWSTART bit */ - if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) - { - /* JSWSTART bit is set */ - bitstatus = SET; - } - else - { - /* JSWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JSWSTART bit status */ - return bitstatus; -} - -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_INJECTED_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* Rank configuration */ - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Get JL value: Number = JL+1 */ - tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; - /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Clear the old JSQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Set the JSQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Configures the sequencer length for injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_LENGTH(Length)); - - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Clear the old injected sequnence lenght JL bits */ - tmpreg1 &= JSQR_JL_Reset; - /* Set the injected sequnence lenght JL bits */ - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Set the injected channels conversion value offset - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the ADC injected channel to set its offset. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @param Offset: the offset value for the selected ADC injected channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_OFFSET(Offset)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - /* Set the selected injected channel data offset */ - *(__IO uint32_t *) tmp = (uint32_t)Offset; -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the converted ADC injected channel. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + JDR_Offset; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -/** - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear AWDEN, AWDENJ and AWDSGL bits */ - tmpreg &= CR1_AWDMode_Reset; - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - /* Set the ADCx high threshold */ - ADCx->HTR = HighThreshold; - /* Set the ADCx low threshold */ - ADCx->LTR = LowThreshold; -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear the Analog watchdog channel select bits */ - tmpreg &= CR1_AWDCH_Reset; - /* Set the Analog watchdog channel */ - tmpreg |= ADC_Channel; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Enables or disables the temperature sensor and Vrefint channel. - * @param NewState: new state of the temperature sensor. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the temperature sensor and Vrefint channel*/ - ADC1->CR2 |= CR2_TSVREFE_Set; - } - else - { - /* Disable the temperature sensor and Vrefint channel*/ - ADC1->CR2 &= CR2_TSVREFE_Reset; - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - /* Check the status of the specified ADC flag */ - if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - /* Clear the selected ADC flags */ - ADCx->SR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = ADC_IT >> 8; - /* Get the ADC_IT enable bit status */ - enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; - /* Check the status of the specified ADC interrupt */ - if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's interrupt pending bits. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)(ADC_IT >> 8); - /* Clear the selected ADC interrupt pending bits */ - ADCx->SR = ~(uint32_t)itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c deleted file mode 100644 index 3004b9ef..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c +++ /dev/null @@ -1,308 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_bkp.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the BKP firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_bkp.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup BKP - * @brief BKP driver modules - * @{ - */ - -/** @defgroup BKP_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Defines - * @{ - */ - -/* ------------ BKP registers bit address in the alias region --------------- */ -#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) - -/* --- CR Register ----*/ - -/* Alias word address of TPAL bit */ -#define CR_OFFSET (BKP_OFFSET + 0x30) -#define TPAL_BitNumber 0x01 -#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) - -/* Alias word address of TPE bit */ -#define TPE_BitNumber 0x00 -#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of TPIE bit */ -#define CSR_OFFSET (BKP_OFFSET + 0x34) -#define TPIE_BitNumber 0x02 -#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) - -/* Alias word address of TIF bit */ -#define TIF_BitNumber 0x09 -#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) - -/* Alias word address of TEF bit */ -#define TEF_BitNumber 0x08 -#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) - -/* ---------------------- BKP registers bit mask ------------------------ */ - -/* RTCCR register bit mask */ -#define RTCCR_CAL_MASK ((uint16_t)0xFF80) -#define RTCCR_MASK ((uint16_t)0xFC7F) - -/** - * @} - */ - - -/** @defgroup BKP_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the BKP peripheral registers to their default reset values. - * @param None - * @retval None - */ -void BKP_DeInit(void) -{ - RCC_BackupResetCmd(ENABLE); - RCC_BackupResetCmd(DISABLE); -} - -/** - * @brief Configures the Tamper Pin active level. - * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. - * This parameter can be one of the following values: - * @arg BKP_TamperPinLevel_High: Tamper pin active on high level - * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level - * @retval None - */ -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) -{ - /* Check the parameters */ - assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); - *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; -} - -/** - * @brief Enables or disables the Tamper Pin activation. - * @param NewState: new state of the Tamper Pin activation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void BKP_TamperPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Tamper Pin Interrupt. - * @param NewState: new state of the Tamper Pin Interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void BKP_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; -} - -/** - * @brief Select the RTC output source to output on the Tamper pin. - * @param BKP_RTCOutputSource: specifies the RTC output source. - * This parameter can be one of the following values: - * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. - * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency - * divided by 64 on the Tamper pin. - * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on - * the Tamper pin. - * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on - * the Tamper pin. - * @retval None - */ -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) -{ - uint16_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); - tmpreg = BKP->RTCCR; - /* Clear CCO, ASOE and ASOS bits */ - tmpreg &= RTCCR_MASK; - - /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ - tmpreg |= BKP_RTCOutputSource; - /* Store the new value */ - BKP->RTCCR = tmpreg; -} - -/** - * @brief Sets RTC Clock Calibration value. - * @param CalibrationValue: specifies the RTC Clock Calibration value. - * This parameter must be a number between 0 and 0x7F. - * @retval None - */ -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) -{ - uint16_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); - tmpreg = BKP->RTCCR; - /* Clear CAL[6:0] bits */ - tmpreg &= RTCCR_CAL_MASK; - /* Set CAL[6:0] bits according to CalibrationValue value */ - tmpreg |= CalibrationValue; - /* Store the new value */ - BKP->RTCCR = tmpreg; -} - -/** - * @brief Writes user data to the specified Data Backup Register. - * @param BKP_DR: specifies the Data Backup Register. - * This parameter can be BKP_DRx where x:[1, 42] - * @param Data: data to write - * @retval None - */ -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_BKP_DR(BKP_DR)); - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Reads data from the specified Data Backup Register. - * @param BKP_DR: specifies the Data Backup Register. - * This parameter can be BKP_DRx where x:[1, 42] - * @retval The content of the specified Data Backup Register - */ -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_BKP_DR(BKP_DR)); - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Checks whether the Tamper Pin Event flag is set or not. - * @param None - * @retval The new state of the Tamper Pin Event flag (SET or RESET). - */ -FlagStatus BKP_GetFlagStatus(void) -{ - return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); -} - -/** - * @brief Clears Tamper Pin Event pending flag. - * @param None - * @retval None - */ -void BKP_ClearFlag(void) -{ - /* Set CTE bit to clear Tamper Pin Event flag */ - BKP->CSR |= BKP_CSR_CTE; -} - -/** - * @brief Checks whether the Tamper Pin Interrupt has occurred or not. - * @param None - * @retval The new state of the Tamper Pin Interrupt (SET or RESET). - */ -ITStatus BKP_GetITStatus(void) -{ - return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); -} - -/** - * @brief Clears Tamper Pin Interrupt pending bit. - * @param None - * @retval None - */ -void BKP_ClearITPendingBit(void) -{ - /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ - BKP->CSR |= BKP_CSR_CTI; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c deleted file mode 100644 index 607d6924..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c +++ /dev/null @@ -1,1415 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_can.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the CAN firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_can.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CAN - * @brief CAN driver modules - * @{ - */ - -/** @defgroup CAN_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_Defines - * @{ - */ - -/* CAN Master Control Register bits */ - -#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ - -/* CAN Filter Master Register bits */ -#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) - - - -/* Flags in TSR register */ -#define CAN_FLAGS_TSR ((uint32_t)0x08000000) -/* Flags in RF1R register */ -#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) -/* Flags in RF0R register */ -#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) -/* Flags in MSR register */ -#define CAN_FLAGS_MSR ((uint32_t)0x01000000) -/* Flags in ESR register */ -#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - - - -#define CAN_MODE_MASK ((uint32_t) 0x00000003) -/** - * @} - */ - -/** @defgroup CAN_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_FunctionPrototypes - * @{ - */ - -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - -/** - * @} - */ - -/** @defgroup CAN_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the CAN peripheral registers to their default reset values. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval None. - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - if (CANx == CAN1) - { - /* Enable CAN1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); - /* Release CAN1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); - } - else - { - /* Enable CAN2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); - /* Release CAN2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); - } -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param CANx: where x can be 1 or 2 to to select the CAN - * peripheral. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that - * contains the configuration information for the - * CAN peripheral. - * @retval Constant indicates initialization succeed which will be - * CAN_InitStatus_Failed or CAN_InitStatus_Success. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - uint32_t wait_ack = 0x00000000; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); - assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); - assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); - assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); - assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); - assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); - - /* Exit from sleep mode */ - CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - - /* Request initialisation */ - CANx->MCR |= CAN_MCR_INRQ ; - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* Check acknowledge */ - if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - /* Set the time triggered communication mode */ - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->MCR |= CAN_MCR_TTCM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->MCR |= CAN_MCR_ABOM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->MCR |= CAN_MCR_AWUM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->MCR |= CAN_MCR_NART; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->MCR |= CAN_MCR_RFLM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->MCR |= CAN_MCR_TXFP; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ - ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ - ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - - /* Request leave initialisation */ - CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Wait the acknowledge */ - wait_ack = 0; - - while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success ; - } - } - - /* At this step, return the status of initialization */ - return InitStatus; -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_FilterInitStruct. - * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef - * structure that contains the configuration - * information. - * @retval None. - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; - - /* Filter Scale */ - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filter_number_bit_pos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - /* Filter Mode */ - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter activation */ - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FA1R |= filter_number_bit_pos; - } - - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Fills each CAN_InitStruct member with its default value. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which - * will be initialized. - * @retval None. - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - /* Reset CAN init structure parameters values */ - - /* Initialize the time triggered communication mode */ - CAN_InitStruct->CAN_TTCM = DISABLE; - - /* Initialize the automatic bus-off management */ - CAN_InitStruct->CAN_ABOM = DISABLE; - - /* Initialize the automatic wake-up mode */ - CAN_InitStruct->CAN_AWUM = DISABLE; - - /* Initialize the no automatic retransmission */ - CAN_InitStruct->CAN_NART = DISABLE; - - /* Initialize the receive FIFO locked mode */ - CAN_InitStruct->CAN_RFLM = DISABLE; - - /* Initialize the transmit FIFO priority */ - CAN_InitStruct->CAN_TXFP = DISABLE; - - /* Initialize the CAN_Mode member */ - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - - /* Initialize the CAN_SJW member */ - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - - /* Initialize the CAN_BS1 member */ - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - - /* Initialize the CAN_BS2 member */ - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - - /* Initialize the CAN_Prescaler member */ - CAN_InitStruct->CAN_Prescaler = 1; -} - -/** - * @brief Select the start bank filter for slave CAN. - * @note This function applies only to STM32 Connectivity line devices. - * @param CAN_BankNumber: Select the start slave bank filter from 1..27. - * @retval None. - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - - /* Enter Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Select the start slave bank */ - CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; - - /* Leave Initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Enables or disables the DBG Freeze for CAN. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: new state of the CAN peripheral. This parameter can - * be: ENABLE or DISABLE. - * @retval None. - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Debug Freeze */ - CANx->MCR |= MCR_DBF; - } - else - { - /* Disable Debug Freeze */ - CANx->MCR &= ~MCR_DBF; - } -} - - -/** - * @brief Enables or disabes the CAN Time TriggerOperation communication mode. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState : Mode new state , can be one of @ref FunctionalState. - * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last - * two data bytes of the 8-byte message: TIME[7:0] in data byte 6 - * and TIME[15:8] in data byte 7 - * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be - * sent over the CAN bus. - * @retval None - */ -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TTCM mode */ - CANx->MCR |= CAN_MCR_TTCM; - - /* Set TGT bits */ - CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); - } - else - { - /* Disable the TTCM mode */ - CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); - - /* Reset TGT bits */ - CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); - } -} -/** - * @brief Initiates the transmission of a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TxMessage: pointer to a structure which contains CAN Id, CAN - * DLC and CAN data. - * @retval The number of the mailbox that is used for transmission - * or CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); - assert_param(IS_CAN_RTR(TxMessage->RTR)); - assert_param(IS_CAN_DLC(TxMessage->DLC)); - - /* Select one empty transmit mailbox */ - if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if (transmit_mailbox != CAN_TxStatus_NoMailBox) - { - /* Set up the Id */ - CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_Id_Standard) - { - assert_param(IS_CAN_STDID(TxMessage->StdId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ - TxMessage->RTR); - } - else - { - assert_param(IS_CAN_EXTID(TxMessage->ExtId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->IDE | \ - TxMessage->RTR); - } - - /* Set up the DLC */ - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; - - /* Set up the data field */ - CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - /* Request transmission */ - CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; - } - return transmit_mailbox; -} - -/** - * @brief Checks the transmission of a message. - * @param CANx: where x can be 1 or 2 to to select the - * CAN peripheral. - * @param TransmitMailbox: the number of the mailbox that is used for - * transmission. - * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed - * in an other case. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); - - switch (TransmitMailbox) - { - case (CAN_TXMAILBOX_0): - state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); - break; - case (CAN_TXMAILBOX_1): - state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); - break; - case (CAN_TXMAILBOX_2): - state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); - break; - default: - state = CAN_TxStatus_Failed; - break; - } - switch (state) - { - /* transmit pending */ - case (0x0): state = CAN_TxStatus_Pending; - break; - /* transmit failed */ - case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; - break; - /* transmit succeeded */ - case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; - break; - default: state = CAN_TxStatus_Failed; - break; - } - return (uint8_t) state; -} - -/** - * @brief Cancels a transmit request. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param Mailbox: Mailbox number. - * @retval None. - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); - /* abort transmission */ - switch (Mailbox) - { - case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; - break; - case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; - break; - case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; - break; - default: - break; - } -} - - -/** - * @brief Receives a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: pointer to a structure receive message which contains - * CAN Id, CAN DLC, CAN datas and FMI number. - * @retval None. - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Get the Id */ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; - if (RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Releases the specified FIFO. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. - * @retval None. - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Returns the number of pending messages. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval NbMessage : which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - return message_pending; -} - - -/** - * @brief Select the CAN Operation mode. - * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one - * of @ref CAN_OperatingMode_TypeDef enumeration. - * @retval status of the requested mode which can be - * - CAN_ModeStatus_Failed CAN failed entering the specific mode - * - CAN_ModeStatus_Success CAN Succeed entering the specific mode - - */ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) -{ - uint8_t status = CAN_ModeStatus_Failed; - - /* Timeout for INAK or also for SLAK bits*/ - uint32_t timeout = INAK_TIMEOUT; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); - - if (CAN_OperatingMode == CAN_OperatingMode_Initialization) - { - /* Request initialisation */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Normal) - { - /* Request leave initialisation and sleep mode and enter Normal mode */ - CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != 0) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) - { - /* Request Sleep mode */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else - { - status = CAN_ModeStatus_Failed; - } - - return (uint8_t) status; -} - -/** - * @brief Enters the low power mode. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an - * other case. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CAN_Sleep_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Request Sleep mode */ - CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) - { - /* Sleep mode not entered */ - sleepstatus = CAN_Sleep_Ok; - } - /* return sleep mode status */ - return (uint8_t)sleepstatus; -} - -/** - * @brief Wakes the CAN up. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval status: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an - * other case. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CAN_WakeUp_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Wake up request */ - CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Sleep mode status */ - while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) - { - /* wake up done : Sleep mode exited */ - wakeupstatus = CAN_WakeUp_Ok; - } - /* return wakeup status */ - return (uint8_t)wakeupstatus; -} - - -/** - * @brief Returns the CANx's last error code (LEC). - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CAN_ErrorCode: specifies the Error code : - * - CAN_ERRORCODE_NoErr No Error - * - CAN_ERRORCODE_StuffErr Stuff Error - * - CAN_ERRORCODE_FormErr Form Error - * - CAN_ERRORCODE_ACKErr Acknowledgment Error - * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error - * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error - * - CAN_ERRORCODE_CRCErr CRC Error - * - CAN_ERRORCODE_SoftwareSetErr Software Set Error - */ - -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) -{ - uint8_t errorcode=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the error code*/ - errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); - - /* Return the error code*/ - return errorcode; -} -/** - * @brief Returns the CANx Receive Error Counter (REC). - * @note In case of an error during reception, this counter is incremented - * by 1 or by 8 depending on the error condition as defined by the CAN - * standard. After every successful reception, the counter is - * decremented by 1 or reset to 120 if its value was higher than 128. - * When the counter value exceeds 127, the CAN controller enters the - * error passive state. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the Receive Error Counter*/ - counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); - - /* Return the Receive Error Counter*/ - return counter; -} - - -/** - * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval LSB of the 9-bit CAN Transmit Error Counter. - */ -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); - - /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - return counter; -} - - -/** - * @brief Enables or disables the specified CANx interrupts. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. - * This parameter can be: - * - CAN_IT_TME, - * - CAN_IT_FMP0, - * - CAN_IT_FF0, - * - CAN_IT_FOV0, - * - CAN_IT_FMP1, - * - CAN_IT_FF1, - * - CAN_IT_FOV1, - * - CAN_IT_EWG, - * - CAN_IT_EPV, - * - CAN_IT_LEC, - * - CAN_IT_ERR, - * - CAN_IT_WKU or - * - CAN_IT_SLK. - * @param NewState: new state of the CAN interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CANx interrupt */ - CANx->IER |= CAN_IT; - } - else - { - /* Disable the selected CANx interrupt */ - CANx->IER &= ~CAN_IT; - } -} -/** - * @brief Checks whether the specified CAN flag is set or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to check. - * This parameter can be one of the following flags: - * - CAN_FLAG_EWG - * - CAN_FLAG_EPV - * - CAN_FLAG_BOF - * - CAN_FLAG_RQCP0 - * - CAN_FLAG_RQCP1 - * - CAN_FLAG_RQCP2 - * - CAN_FLAG_FMP1 - * - CAN_FLAG_FF1 - * - CAN_FLAG_FOV1 - * - CAN_FLAG_FMP0 - * - CAN_FLAG_FF0 - * - CAN_FLAG_FOV0 - * - CAN_FLAG_WKU - * - CAN_FLAG_SLAK - * - CAN_FLAG_LEC - * @retval The new state of CAN_FLAG (SET or RESET). - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); - - - if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ - { - /* Check the status of the specified CAN flag */ - if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - /* Return the CAN_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CAN's pending flags. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to clear. - * This parameter can be one of the following flags: - * - CAN_FLAG_RQCP0 - * - CAN_FLAG_RQCP1 - * - CAN_FLAG_RQCP2 - * - CAN_FLAG_FF1 - * - CAN_FLAG_FOV1 - * - CAN_FLAG_FF0 - * - CAN_FLAG_FOV0 - * - CAN_FLAG_WKU - * - CAN_FLAG_SLAK - * - CAN_FLAG_LEC - * @retval None. - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - uint32_t flagtmp=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); - - if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ - { - /* Clear the selected CAN flags */ - CANx->ESR = (uint32_t)RESET; - } - else /* MSR or TSR or RF0R or RF1R */ - { - flagtmp = CAN_FLAG & 0x000FFFFF; - - if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF0R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF1R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) - { - /* Transmit Flags */ - CANx->TSR = (uint32_t)(flagtmp); - } - else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ - { - /* Operating mode Flags */ - CANx->MSR = (uint32_t)(flagtmp); - } - } -} - -/** - * @brief Checks whether the specified CANx interrupt has occurred or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt source to check. - * This parameter can be one of the following flags: - * - CAN_IT_TME - * - CAN_IT_FMP0 - * - CAN_IT_FF0 - * - CAN_IT_FOV0 - * - CAN_IT_FMP1 - * - CAN_IT_FF1 - * - CAN_IT_FOV1 - * - CAN_IT_WKU - * - CAN_IT_SLK - * - CAN_IT_EWG - * - CAN_IT_EPV - * - CAN_IT_BOF - * - CAN_IT_LEC - * - CAN_IT_ERR - * @retval The current state of CAN_IT (SET or RESET). - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus itstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - - /* check the enable interrupt bit */ - if((CANx->IER & CAN_IT) != RESET) - { - /* in case the Interrupt is enabled, .... */ - switch (CAN_IT) - { - case CAN_IT_TME: - /* Check CAN_TSR_RQCPx bits */ - itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); - break; - case CAN_IT_FMP0: - /* Check CAN_RF0R_FMP0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); - break; - case CAN_IT_FF0: - /* Check CAN_RF0R_FULL0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); - break; - case CAN_IT_FOV0: - /* Check CAN_RF0R_FOVR0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); - break; - case CAN_IT_FMP1: - /* Check CAN_RF1R_FMP1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); - break; - case CAN_IT_FF1: - /* Check CAN_RF1R_FULL1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); - break; - case CAN_IT_FOV1: - /* Check CAN_RF1R_FOVR1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); - break; - case CAN_IT_WKU: - /* Check CAN_MSR_WKUI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); - break; - case CAN_IT_SLK: - /* Check CAN_MSR_SLAKI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); - break; - case CAN_IT_EWG: - /* Check CAN_ESR_EWGF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); - break; - case CAN_IT_EPV: - /* Check CAN_ESR_EPVF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); - break; - case CAN_IT_BOF: - /* Check CAN_ESR_BOFF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); - break; - case CAN_IT_LEC: - /* Check CAN_ESR_LEC bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); - break; - case CAN_IT_ERR: - /* Check CAN_MSR_ERRI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); - break; - default : - /* in case of error, return RESET */ - itstatus = RESET; - break; - } - } - else - { - /* in case the Interrupt is not enabled, return RESET */ - itstatus = RESET; - } - - /* Return the CAN_IT status */ - return itstatus; -} - -/** - * @brief Clears the CANx's interrupt pending bits. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the interrupt pending bit to clear. - * - CAN_IT_TME - * - CAN_IT_FF0 - * - CAN_IT_FOV0 - * - CAN_IT_FF1 - * - CAN_IT_FOV1 - * - CAN_IT_WKU - * - CAN_IT_SLK - * - CAN_IT_EWG - * - CAN_IT_EPV - * - CAN_IT_BOF - * - CAN_IT_LEC - * - CAN_IT_ERR - * @retval None. - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_IT(CAN_IT)); - - switch (CAN_IT) - { - case CAN_IT_TME: - /* Clear CAN_TSR_RQCPx (rc_w1)*/ - CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; - break; - case CAN_IT_FF0: - /* Clear CAN_RF0R_FULL0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FULL0; - break; - case CAN_IT_FOV0: - /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FOVR0; - break; - case CAN_IT_FF1: - /* Clear CAN_RF1R_FULL1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FULL1; - break; - case CAN_IT_FOV1: - /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FOVR1; - break; - case CAN_IT_WKU: - /* Clear CAN_MSR_WKUI (rc_w1)*/ - CANx->MSR = CAN_MSR_WKUI; - break; - case CAN_IT_SLK: - /* Clear CAN_MSR_SLAKI (rc_w1)*/ - CANx->MSR = CAN_MSR_SLAKI; - break; - case CAN_IT_EWG: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* Note : the corresponding Flag is cleared by hardware depending - of the CAN Bus status*/ - break; - case CAN_IT_EPV: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* Note : the corresponding Flag is cleared by hardware depending - of the CAN Bus status*/ - break; - case CAN_IT_BOF: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* Note : the corresponding Flag is cleared by hardware depending - of the CAN Bus status*/ - break; - case CAN_IT_LEC: - /* Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - break; - case CAN_IT_ERR: - /*Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending - of the CAN Bus status*/ - break; - default : - break; - } -} - -/** - * @brief Checks whether the CAN interrupt has occurred or not. - * @param CAN_Reg: specifies the CAN interrupt register to check. - * @param It_Bit: specifies the interrupt source bit to check. - * @retval The new state of the CAN Interrupt (SET or RESET). - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - /* CAN_IT is set */ - pendingbitstatus = SET; - } - else - { - /* CAN_IT is reset */ - pendingbitstatus = RESET; - } - return pendingbitstatus; -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c deleted file mode 100644 index 08b501a0..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c +++ /dev/null @@ -1,433 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_cec.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the CEC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_cec.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CEC - * @brief CEC driver modules - * @{ - */ - -/** @defgroup CEC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Defines - * @{ - */ - -/* ------------ CEC registers bit address in the alias region ----------- */ -#define CEC_OFFSET (CEC_BASE - PERIPH_BASE) - -/* --- CFGR Register ---*/ - -/* Alias word address of PE bit */ -#define CFGR_OFFSET (CEC_OFFSET + 0x00) -#define PE_BitNumber 0x00 -#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) - -/* Alias word address of IE bit */ -#define IE_BitNumber 0x01 -#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of TSOM bit */ -#define CSR_OFFSET (CEC_OFFSET + 0x10) -#define TSOM_BitNumber 0x00 -#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) - -/* Alias word address of TEOM bit */ -#define TEOM_BitNumber 0x01 -#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) - -#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Macros - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the CEC peripheral registers to their default reset - * values. - * @param None - * @retval None - */ -void CEC_DeInit(void) -{ - /* Enable CEC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); - /* Release CEC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); -} - - -/** - * @brief Initializes the CEC peripheral according to the specified - * parameters in the CEC_InitStruct. - * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that - * contains the configuration information for the specified - * CEC peripheral. - * @retval None - */ -void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); - assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); - - /*---------------------------- CEC CFGR Configuration -----------------*/ - /* Get the CEC CFGR value */ - tmpreg = CEC->CFGR; - - /* Clear BTEM and BPEM bits */ - tmpreg &= CFGR_CLEAR_Mask; - - /* Configure CEC: Bit Timing Error and Bit Period Error */ - tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); - - /* Write to CEC CFGR register*/ - CEC->CFGR = tmpreg; - -} - -/** - * @brief Enables or disables the specified CEC peripheral. - * @param NewState: new state of the CEC peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; - - if(NewState == DISABLE) - { - /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ - while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) - { - } - } -} - -/** - * @brief Enables or disables the CEC interrupt. - * @param NewState: new state of the CEC interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; -} - -/** - * @brief Defines the Own Address of the CEC device. - * @param CEC_OwnAddress: The CEC own address - * @retval None - */ -void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) -{ - /* Check the parameters */ - assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); - - /* Set the CEC own address */ - CEC->OAR = CEC_OwnAddress; -} - -/** - * @brief Sets the CEC prescaler value. - * @param CEC_Prescaler: CEC prescaler new value - * @retval None - */ -void CEC_SetPrescaler(uint16_t CEC_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); - - /* Set the Prescaler value*/ - CEC->PRES = CEC_Prescaler; -} - -/** - * @brief Transmits single data through the CEC peripheral. - * @param Data: the data to transmit. - * @retval None - */ -void CEC_SendDataByte(uint8_t Data) -{ - /* Transmit Data */ - CEC->TXD = Data ; -} - - -/** - * @brief Returns the most recent received data by the CEC peripheral. - * @param None - * @retval The received data. - */ -uint8_t CEC_ReceiveDataByte(void) -{ - /* Receive Data */ - return (uint8_t)(CEC->RXD); -} - -/** - * @brief Starts a new message. - * @param None - * @retval None - */ -void CEC_StartOfMessage(void) -{ - /* Starts of new message */ - *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; -} - -/** - * @brief Transmits message with or without an EOM bit. - * @param NewState: new state of the CEC Tx End Of Message. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_EndOfMessageCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* The data byte will be transmitted with or without an EOM bit*/ - *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; -} - -/** - * @brief Gets the CEC flag status - * @param CEC_FLAG: specifies the CEC flag to check. - * This parameter can be one of the following values: - * @arg CEC_FLAG_BTE: Bit Timing Error - * @arg CEC_FLAG_BPE: Bit Period Error - * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error - * @arg CEC_FLAG_SBE: Start Bit Error - * @arg CEC_FLAG_ACKE: Block Acknowledge Error - * @arg CEC_FLAG_LINE: Line Error - * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error - * @arg CEC_FLAG_TEOM: Tx End Of Message - * @arg CEC_FLAG_TERR: Tx Error - * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished - * @arg CEC_FLAG_RSOM: Rx Start Of Message - * @arg CEC_FLAG_REOM: Rx End Of Message - * @arg CEC_FLAG_RERR: Rx Error - * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished - * @retval The new state of CEC_FLAG (SET or RESET) - */ -FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t cecreg = 0, cecbase = 0; - - /* Check the parameters */ - assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); - - /* Get the CEC peripheral base address */ - cecbase = (uint32_t)(CEC_BASE); - - /* Read flag register index */ - cecreg = CEC_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - CEC_FLAG &= FLAG_Mask; - - if(cecreg != 0) - { - /* Flag in CEC ESR Register */ - CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); - - /* Get the CEC ESR register address */ - cecbase += 0xC; - } - else - { - /* Get the CEC CSR register address */ - cecbase += 0x10; - } - - if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) - { - /* CEC_FLAG is set */ - bitstatus = SET; - } - else - { - /* CEC_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the CEC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CEC's pending flags. - * @param CEC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg CEC_FLAG_TERR: Tx Error - * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished - * @arg CEC_FLAG_RSOM: Rx Start Of Message - * @arg CEC_FLAG_REOM: Rx End Of Message - * @arg CEC_FLAG_RERR: Rx Error - * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished - * @retval None - */ -void CEC_ClearFlag(uint32_t CEC_FLAG) -{ - uint32_t tmp = 0x0; - - /* Check the parameters */ - assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); - - tmp = CEC->CSR & 0x2; - - /* Clear the selected CEC flags */ - CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); -} - -/** - * @brief Checks whether the specified CEC interrupt has occurred or not. - * @param CEC_IT: specifies the CEC interrupt source to check. - * This parameter can be one of the following values: - * @arg CEC_IT_TERR: Tx Error - * @arg CEC_IT_TBTF: Tx Block Transfer Finished - * @arg CEC_IT_RERR: Rx Error - * @arg CEC_IT_RBTF: Rx Block Transfer Finished - * @retval The new state of CEC_IT (SET or RESET). - */ -ITStatus CEC_GetITStatus(uint8_t CEC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_CEC_GET_IT(CEC_IT)); - - /* Get the CEC IT enable bit status */ - enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; - - /* Check the status of the specified CEC interrupt */ - if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) - { - /* CEC_IT is set */ - bitstatus = SET; - } - else - { - /* CEC_IT is reset */ - bitstatus = RESET; - } - /* Return the CEC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the CEC's interrupt pending bits. - * @param CEC_IT: specifies the CEC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg CEC_IT_TERR: Tx Error - * @arg CEC_IT_TBTF: Tx Block Transfer Finished - * @arg CEC_IT_RERR: Rx Error - * @arg CEC_IT_RBTF: Rx Block Transfer Finished - * @retval None - */ -void CEC_ClearITPendingBit(uint16_t CEC_IT) -{ - uint32_t tmp = 0x0; - - /* Check the parameters */ - assert_param(IS_CEC_GET_IT(CEC_IT)); - - tmp = CEC->CSR & 0x2; - - /* Clear the selected CEC interrupt pending bits */ - CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c deleted file mode 100644 index 025b8e28..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c +++ /dev/null @@ -1,571 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dac.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the DAC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dac.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/** @defgroup DAC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Defines - * @{ - */ - -/* CR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) -#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) -/** - * @} - */ - -/** @defgroup DAC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified - * parameters in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that - * contains the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, wave generation, - mask/amplitude for wave generation */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= (DAC_CR_EN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel); - } -} -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DAC->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} -#endif - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software - * triggers. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_SET ; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_RESET; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: Specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignment for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel - * DAC. - * @param DAC_Align: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data - * holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data - * holding register. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DAC_Channel: thee selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be only of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channelx's pending flags. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @retval None - */ -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DAC->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channelx's interrupt pending bits. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @retval None - */ -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DAC->SR = (DAC_IT << DAC_Channel); -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c deleted file mode 100644 index d34307b0..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c +++ /dev/null @@ -1,162 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dbgmcu.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the DBGMCU firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dbgmcu.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DBGMCU - * @brief DBGMCU driver modules - * @{ - */ - -/** @defgroup DBGMCU_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Defines - * @{ - */ - -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Functions - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); -} - -/** - * @brief Configures the specified peripheral and low power mode behavior - * when the MCU under Debug mode. - * @param DBGMCU_Periph: specifies the peripheral and low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted - * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted - * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted - * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted - * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted - * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted - * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted - * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted - * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted - * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted - * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted - * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted - * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted - * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted - * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted - * @param NewState: new state of the specified peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c deleted file mode 100644 index 0c86f901..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c +++ /dev/null @@ -1,714 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dma.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the DMA firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dma.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/** @defgroup DMA_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup DMA_Private_Defines - * @{ - */ - - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) -#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) -#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) -#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) -#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) -#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) -#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) - -/* DMA2 Channelx interrupt pending bit masks */ -#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) -#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) -#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) -#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) -#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) - -/* DMA2 FLAG mask */ -#define FLAG_Mask ((uint32_t)0x10000000) - -/* DMA registers Masks */ -#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) - -/** - * @} - */ - -/** @defgroup DMA_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the DMAy Channelx registers to their default reset - * values. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @retval None - */ -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); - - /* Reset DMAy Channelx control register */ - DMAy_Channelx->CCR = 0; - - /* Reset DMAy Channelx remaining bytes register */ - DMAy_Channelx->CNDTR = 0; - - /* Reset DMAy Channelx peripheral address register */ - DMAy_Channelx->CPAR = 0; - - /* Reset DMAy Channelx memory address register */ - DMAy_Channelx->CMAR = 0; - - if (DMAy_Channelx == DMA1_Channel1) - { - /* Reset interrupt pending bits for DMA1 Channel1 */ - DMA1->IFCR |= DMA1_Channel1_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel2) - { - /* Reset interrupt pending bits for DMA1 Channel2 */ - DMA1->IFCR |= DMA1_Channel2_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel3) - { - /* Reset interrupt pending bits for DMA1 Channel3 */ - DMA1->IFCR |= DMA1_Channel3_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel4) - { - /* Reset interrupt pending bits for DMA1 Channel4 */ - DMA1->IFCR |= DMA1_Channel4_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel5) - { - /* Reset interrupt pending bits for DMA1 Channel5 */ - DMA1->IFCR |= DMA1_Channel5_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel6) - { - /* Reset interrupt pending bits for DMA1 Channel6 */ - DMA1->IFCR |= DMA1_Channel6_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel7) - { - /* Reset interrupt pending bits for DMA1 Channel7 */ - DMA1->IFCR |= DMA1_Channel7_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel1) - { - /* Reset interrupt pending bits for DMA2 Channel1 */ - DMA2->IFCR |= DMA2_Channel1_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel2) - { - /* Reset interrupt pending bits for DMA2 Channel2 */ - DMA2->IFCR |= DMA2_Channel2_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel3) - { - /* Reset interrupt pending bits for DMA2 Channel3 */ - DMA2->IFCR |= DMA2_Channel3_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel4) - { - /* Reset interrupt pending bits for DMA2 Channel4 */ - DMA2->IFCR |= DMA2_Channel4_IT_Mask; - } - else - { - if (DMAy_Channelx == DMA2_Channel5) - { - /* Reset interrupt pending bits for DMA2 Channel5 */ - DMA2->IFCR |= DMA2_Channel5_IT_Mask; - } - } -} - -/** - * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that - * contains the configuration information for the specified DMA Channel. - * @retval None - */ -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); - -/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ - /* Get the DMAy_Channelx CCR value */ - tmpreg = DMAy_Channelx->CCR; - /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= CCR_CLEAR_Mask; - /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ - /* Set DIR bit according to DMA_DIR value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set PL bits according to DMA_Priority value */ - /* Set the MEM2MEM bit according to DMA_M2M value */ - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - /* Write to DMAy Channelx CCR */ - DMAy_Channelx->CCR = tmpreg; - -/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; - -/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ - /* Write to DMAy Channelx CPAR */ - DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - -/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ - /* Write to DMAy Channelx CMAR */ - DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ -/*-------------- Reset DMA init structure parameters values ------------------*/ - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - /* Initialize the DMA_MemoryBaseAddr member */ - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - /* Initialize the DMA_M2M member */ - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/** - * @brief Enables or disables the specified DMAy Channelx. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param NewState: new state of the DMAy Channelx. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Channelx */ - DMAy_Channelx->CCR |= DMA_CCR1_EN; - } - else - { - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); - } -} - -/** - * @brief Enables or disables the specified DMAy Channelx interrupts. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DMA_IT: specifies the DMA interrupts sources to be enabled - * or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DMA interrupts */ - DMAy_Channelx->CCR |= DMA_IT; - } - else - { - /* Disable the selected DMA interrupts */ - DMAy_Channelx->CCR &= ~DMA_IT; - } -} - -/** - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DataNumber: The number of data units in the current DMAy Channelx - * transfer. - * @note This function can only be used when the DMAy_Channelx is disabled. - * @retval None. - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - -/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DataNumber; -} - -/** - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @retval The number of remaining data units in the current DMAy Channelx - * transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - /* Return the number of remaining data units for DMAy Channelx */ - return ((uint16_t)(DMAy_Channelx->CNDTR)); -} - -/** - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * @param DMAy_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * @retval The new state of DMAy_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); - - /* Calculate the used DMAy */ - if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR ; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR ; - } - - /* Check the status of the specified DMAy flag */ - if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) - { - /* DMAy_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMAy_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMAy_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's pending flags. - * @param DMAy_FLAG: specifies the flag to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * @retval None - */ -void DMA_ClearFlag(uint32_t DMAy_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); - - /* Calculate the used DMAy */ - if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMAy flags */ - DMA2->IFCR = DMAy_FLAG; - } - else - { - /* Clear the selected DMAy flags */ - DMA1->IFCR = DMAy_FLAG; - } -} - -/** - * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. - * @param DMAy_IT: specifies the DMAy interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. - * @retval The new state of DMAy_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMAy_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_IT(DMAy_IT)); - - /* Calculate the used DMA */ - if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR; - } - - /* Check the status of the specified DMAy interrupt */ - if ((tmpreg & DMAy_IT) != (uint32_t)RESET) - { - /* DMAy_IT is set */ - bitstatus = SET; - } - else - { - /* DMAy_IT is reset */ - bitstatus = RESET; - } - /* Return the DMA_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's interrupt pending bits. - * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. - * @retval None - */ -void DMA_ClearITPendingBit(uint32_t DMAy_IT) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); - - /* Calculate the used DMAy */ - if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMAy interrupt pending bits */ - DMA2->IFCR = DMAy_IT; - } - else - { - /* Clear the selected DMAy interrupt pending bits */ - DMA1->IFCR = DMAy_IT; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c deleted file mode 100644 index ab734627..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c +++ /dev/null @@ -1,269 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_exti.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the EXTI firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_exti.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/** @defgroup EXTI_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Defines - * @{ - */ - -#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x00000000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x000FFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected external interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt. - * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be: - * @arg EXTI_Linex: External interrupt line x where x(0..19) - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be: - * @arg EXTI_Linex: External interrupt line x where x(0..19) - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - enablestatus = EXTI->IMR & EXTI_Line; - if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c deleted file mode 100644 index f6c7bf17..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c +++ /dev/null @@ -1,1684 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_flash.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the FLASH firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_flash.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/** @defgroup FLASH_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Defines - * @{ - */ - -/* Flash Access Control Register bits */ -#define ACR_LATENCY_Mask ((uint32_t)0x00000038) -#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) -#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) - -/* Flash Access Control Register bits */ -#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) - -/* Flash Control Register bits */ -#define CR_PG_Set ((uint32_t)0x00000001) -#define CR_PG_Reset ((uint32_t)0x00001FFE) -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0x00001FFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0x00001FFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0x00001FDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) - -/* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) -#define OB_USER_BFB2 ((uint16_t)0x0008) - -/* FLASH Keys */ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) - -/* FLASH BANK address */ -#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) - -/* Delay definition */ -#define EraseTimeout ((uint32_t)0x000B0000) -#define ProgramTimeout ((uint32_t)0x00002000) -/** - * @} - */ - -/** @defgroup FLASH_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** -@code - - This driver provides functions to configure and program the Flash memory of all STM32F10x devices, - including the latest STM32F10x_XL density devices. - - STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability: - - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each) - - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each) - While other STM32F10x devices features only one bank with memory up to 512 Kbytes. - - In version V3.3.0, some functions were updated and new ones were added to support - STM32F10x_XL devices. Thus some functions manages all devices, while other are - dedicated for XL devices only. - - The table below presents the list of available functions depending on the used STM32F10x devices. - - *************************************************** - * Legacy functions used for all STM32F10x devices * - *************************************************** - +----------------------------------------------------------------------------------------------------------------------------------+ - | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | - | | devices | devices | | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_SetLatency | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_HalfCycleAccessCmd | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_PrefetchBufferCmd | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. | - | | | | - For other devices: unlock Bank1 and it is equivalent | - | | | | to FLASH_UnlockBank1 function. | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. | - | | | | - For other devices: lock Bank1 and it is equivalent | - | | | | to FLASH_LockBank1 function. | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 | - | | | | - For other devices: erase a page in Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 | - | | | | - For other devices: erase all pages in Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_EraseOptionBytes | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ProgramOptionByteData | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_EnableWriteProtection | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ReadOutProtection | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_UserOptionByteConfig | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetUserOptionByte | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts| - | | | | - For other devices: enable Bank1's interrupts | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status| - | | | | - For other devices: return Bank1's flag status | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag | - | | | | - For other devices: clear Bank1's flag | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) | - | | | | equivalent to FLASH_GetBank1Status function | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) | - | | | | equivalent to: FLASH_WaitForLastBank1Operation function | - +----------------------------------------------------------------------------------------------------------------------------------+ - - ************************************************************************************************************************ - * New functions used for all STM32F10x devices to manage Bank1: * - * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 * - * - For other devices, these functions are optional (covered by functions listed above) * - ************************************************************************************************************************ - +----------------------------------------------------------------------------------------------------------------------------------+ - | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | - | | devices | devices | | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation | - +----------------------------------------------------------------------------------------------------------------------------------+ - - ***************************************************************************** - * New Functions used only with STM32F10x_XL density devices to manage Bank2 * - ***************************************************************************** - +----------------------------------------------------------------------------------------------------------------------------------+ - | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | - | | devices | devices | | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_LockBank2 | Yes | No | - Lock Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 | - +----------------------------------------------------------------------------------------------------------------------------------+ -@endcode -*/ - - -/** - * @brief Sets the code latency value. - * @note This function can be used for all STM32F10x devices. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @arg FLASH_Latency_2: FLASH Two Latency cycles - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Read the ACR register */ - tmpreg = FLASH->ACR; - - /* Sets the Latency value */ - tmpreg &= ACR_LATENCY_Mask; - tmpreg |= FLASH_Latency; - - /* Write the ACR register */ - FLASH->ACR = tmpreg; -} - -/** - * @brief Enables or disables the Half cycle flash access. - * @note This function can be used for all STM32F10x devices. - * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. - * This parameter can be one of the following values: - * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable - * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable - * @retval None - */ -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) -{ - /* Check the parameters */ - assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); - - /* Enable or disable the Half cycle access */ - FLASH->ACR &= ACR_HLFCYA_Mask; - FLASH->ACR |= FLASH_HalfCycleAccess; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @note This function can be used for all STM32F10x devices. - * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. - * This parameter can be one of the following values: - * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable - * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable - * @retval None - */ -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) -{ - /* Check the parameters */ - assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); - - /* Enable or disable the Prefetch Buffer */ - FLASH->ACR &= ACR_PRFTBE_Mask; - FLASH->ACR |= FLASH_PrefetchBuffer; -} - -/** - * @brief Unlocks the FLASH Program Erase Controller. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2. - * - For all other devices it unlocks Bank1 and it is equivalent - * to FLASH_UnlockBank1 function.. - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - -#ifdef STM32F10X_XL - /* Authorize the FPEC of Bank2 Access */ - FLASH->KEYR2 = FLASH_KEY1; - FLASH->KEYR2 = FLASH_KEY2; -#endif /* STM32F10X_XL */ -} -/** - * @brief Unlocks the FLASH Bank1 Program Erase Controller. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function unlocks Bank1. - * - For all other devices it unlocks Bank1 and it is - * equivalent to FLASH_Unlock function. - * @param None - * @retval None - */ -void FLASH_UnlockBank1(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -#ifdef STM32F10X_XL -/** - * @brief Unlocks the FLASH Bank2 Program Erase Controller. - * @note This function can be used only for STM32F10X_XL density devices. - * @param None - * @retval None - */ -void FLASH_UnlockBank2(void) -{ - /* Authorize the FPEC of Bank2 Access */ - FLASH->KEYR2 = FLASH_KEY1; - FLASH->KEYR2 = FLASH_KEY2; - -} -#endif /* STM32F10X_XL */ - -/** - * @brief Locks the FLASH Program Erase Controller. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function Locks Bank1 and Bank2. - * - For all other devices it Locks Bank1 and it is equivalent - * to FLASH_LockBank1 function. - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ - FLASH->CR |= CR_LOCK_Set; - -#ifdef STM32F10X_XL - /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ - FLASH->CR2 |= CR_LOCK_Set; -#endif /* STM32F10X_XL */ -} - -/** - * @brief Locks the FLASH Bank1 Program Erase Controller. - * @note this function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function Locks Bank1. - * - For all other devices it Locks Bank1 and it is equivalent - * to FLASH_Lock function. - * @param None - * @retval None - */ -void FLASH_LockBank1(void) -{ - /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ - FLASH->CR |= CR_LOCK_Set; -} - -#ifdef STM32F10X_XL -/** - * @brief Locks the FLASH Bank2 Program Erase Controller. - * @note This function can be used only for STM32F10X_XL density devices. - * @param None - * @retval None - */ -void FLASH_LockBank2(void) -{ - /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ - FLASH->CR2 |= CR_LOCK_Set; -} -#endif /* STM32F10X_XL */ - -/** - * @brief Erases a specified FLASH page. - * @note This function can be used for all STM32F10x devices. - * @param Page_Address: The page address to be erased. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Page_Address)); - -#ifdef STM32F10X_XL - if(Page_Address < FLASH_BANK1_END_ADDRESS) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR|= CR_PER_Set; - FLASH->AR = Page_Address; - FLASH->CR|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - /* Disable the PER Bit */ - FLASH->CR &= CR_PER_Reset; - } - } - else - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR2|= CR_PER_Set; - FLASH->AR2 = Page_Address; - FLASH->CR2|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - - /* Disable the PER Bit */ - FLASH->CR2 &= CR_PER_Reset; - } - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR|= CR_PER_Set; - FLASH->AR = Page_Address; - FLASH->CR|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - /* Disable the PER Bit */ - FLASH->CR &= CR_PER_Reset; - } -#endif /* STM32F10X_XL */ - - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH pages. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - -#ifdef STM32F10X_XL - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR2 |= CR_MER_Set; - FLASH->CR2 |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR2 &= CR_MER_Reset; - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } -#endif /* STM32F10X_XL */ - - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all Bank1 FLASH pages. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function erases all Bank1 pages. - * - For all other devices it erases all Bank1 pages and it is equivalent - * to FLASH_EraseAllPages function. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllBank1Pages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } - /* Return the Erase Status */ - return status; -} - -#ifdef STM32F10X_XL -/** - * @brief Erases all Bank2 FLASH pages. - * @note This function can be used only for STM32F10x_XL density devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllBank2Pages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR2 |= CR_MER_Set; - FLASH->CR2 |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR2 &= CR_MER_Reset; - } - /* Return the Erase Status */ - return status; -} -#endif /* STM32F10X_XL */ - -/** - * @brief Erases the FLASH option bytes. - * @note This functions erases all option bytes except the Read protection (RDP). - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseOptionBytes(void) -{ - uint16_t rdptmp = RDP_Key; - - FLASH_Status status = FLASH_COMPLETE; - - /* Get the actual read protection Option Byte value */ - if(FLASH_GetReadOutProtectionStatus() != RESET) - { - rdptmp = 0x00; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* if the previous operation is completed, proceed to erase the option bytes */ - FLASH->CR |= CR_OPTER_Set; - FLASH->CR |= CR_STRT_Set; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - /* Restore the last read protection Option Byte value */ - OB->RDP = (uint16_t)rdptmp; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - } - /* Return the erase status */ - return status; -} - -/** - * @brief Programs a word at a specified address. - * @note This function can be used for all STM32F10x devices. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - -#ifdef STM32F10X_XL - if(Address < FLASH_BANK1_END_ADDRESS - 2) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - } - else if(Address == (FLASH_BANK1_END_ADDRESS - 1)) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - FLASH->CR2 |= CR_PG_Set; - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } - else - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR2 |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } -#endif /* STM32F10X_XL */ - - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified address. - * @note This function can be used for all STM32F10x devices. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - -#ifdef STM32F10X_XL - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(Address < FLASH_BANK1_END_ADDRESS) - { - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - else - { - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR2 |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } -#endif /* STM32F10X_XL */ - - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified Option Byte Data address. - * @note This function can be used for all STM32F10x devices. - * @param Address: specifies the address to be programmed. - * This parameter can be 0x1FFFF804 or 0x1FFFF806. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_OB_DATA_ADDRESS(Address)); - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - /* Enables the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte Data Program Status */ - return status; -} - -/** - * @brief Write protects the desired pages - * @note This function can be used for all STM32F10x devices. - * @param FLASH_Pages: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 - * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 - * and FLASH_WRProt_Pages124to127 - * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255 - * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 - * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511 - * @arg FLASH_WRProt_AllPages - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) -{ - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; - - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); - - FLASH_Pages = (uint32_t)(~FLASH_Pages); - WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); - WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); - WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); - WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Authorizes the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - FLASH->CR |= CR_OPTPG_Set; - if(WRP0_Data != 0xFF) - { - OB->WRP0 = WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) - { - OB->WRP1 = WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) - { - OB->WRP2 = WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) - { - OB->WRP3 = WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the write protection operation Status */ - return status; -} - -/** - * @brief Enables or disables the read out protection. - * @note If the user has already programmed the other option bytes before calling - * this function, he must re-program them since this function erases all option bytes. - * @note This function can be used for all STM32F10x devices. - * @param Newstate: new state of the ReadOut Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* Authorizes the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - FLASH->CR |= CR_OPTER_Set; - FLASH->CR |= CR_STRT_Set; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - if(NewState != DISABLE) - { - OB->RDP = 0x00; - } - else - { - OB->RDP = RDP_Key; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - /* Disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - } - } - } - /* Return the protection operation Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @note This function can be used for all STM32F10x devices. - * @param OB_IWDG: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - - OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte program Status */ - return status; -} - -#ifdef STM32F10X_XL -/** - * @brief Configures to boot from Bank1 or Bank2. - * @note This function can be used only for STM32F10x_XL density devices. - * @param FLASH_BOOT: select the FLASH Bank to boot from. - * This parameter can be one of the following values: - * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash - * position and this parameter is selected the device will boot from Bank1(Default). - * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash - * position and this parameter is selected the device will boot from Bank2 or Bank1, - * depending on the activation of the bank. The active banks are checked in - * the following order: Bank2, followed by Bank1. - * The active bank is recognized by the value programmed at the base address - * of the respective bank (corresponding to the initial stack pointer value - * in the interrupt vector table). - * For more information, please refer to AN2606 from www.st.com. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT) -{ - FLASH_Status status = FLASH_COMPLETE; - assert_param(IS_FLASH_BOOT(FLASH_BOOT)); - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - - if(FLASH_BOOT == FLASH_BOOT_Bank1) - { - OB->USER |= OB_USER_BFB2; - } - else - { - OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2)); - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte program Status */ - return status; -} -#endif /* STM32F10X_XL */ - -/** - * @brief Returns the FLASH User Option Bytes values. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint32_t FLASH_GetUserOptionByte(void) -{ - /* Return the User Option Byte */ - return (uint32_t)(FLASH->OBR >> 2); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes Register value. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval The FLASH Write Protection Option Bytes Register value - */ -uint32_t FLASH_GetWriteProtectionOptionByte(void) -{ - /* Return the Flash write protection Register value */ - return (uint32_t)(FLASH->WRPR); -} - -/** - * @brief Checks whether the FLASH Read Out Protection Status is set or not. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetReadOutProtectionStatus(void) -{ - FlagStatus readoutstatus = RESET; - if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - readoutstatus = SET; - } - else - { - readoutstatus = RESET; - } - return readoutstatus; -} - -/** - * @brief Checks whether the FLASH Prefetch Buffer status is set or not. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH Prefetch Buffer Status (SET or RESET). - */ -FlagStatus FLASH_GetPrefetchBufferStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts - for Bank1 and Bank2. - * - For other devices it enables or disables the specified FLASH interrupts for Bank1. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_ERROR: FLASH Error Interrupt - * @arg FLASH_IT_EOP: FLASH end of operation Interrupt - * @param NewState: new state of the specified Flash interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ -#ifdef STM32F10X_XL - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if((FLASH_IT & 0x80000000) != 0x0) - { - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF); - } - else - { - /* Disable the interrupt sources */ - FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF); - } - } - else - { - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } - } -#else - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -#endif /* STM32F10X_XL */ -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices, this function checks whether the specified - * Bank1 or Bank2 flag is set or not. - * - For other devices, it checks whether the specified Bank1 flag is - * set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_BSY: FLASH Busy flag - * @arg FLASH_FLAG_PGERR: FLASH Program error flag - * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - -#ifdef STM32F10X_XL - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH_FLAG & 0x80000000) != 0x0) - { - if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - } -#else - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } -#endif /* STM32F10X_XL */ - - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH's pending flags. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices, this function clears Bank1 or Bank2’s pending flags - * - For other devices, it clears Bank1’s pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_PGERR: FLASH Program error flag - * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ -#ifdef STM32F10X_XL - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; - - if((FLASH_FLAG & 0x80000000) != 0x0) - { - /* Clear the flags */ - FLASH->SR2 = FLASH_FLAG; - } - else - { - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; - } - -#else - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -#endif /* STM32F10X_XL */ -} - -/** - * @brief Returns the FLASH Status. - * @note This function can be used for all STM32F10x devices, it is equivalent - * to FLASH_GetBank1Status function. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_PGERR) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} - -/** - * @brief Returns the FLASH Bank1 Status. - * @note This function can be used for all STM32F10x devices, it is equivalent - * to FLASH_GetStatus function. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetBank1Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} - -#ifdef STM32F10X_XL -/** - * @brief Returns the FLASH Bank2 Status. - * @note This function can be used for STM32F10x_XL density devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetBank2Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} -#endif /* STM32F10X_XL */ -/** - * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. - * @note This function can be used for all STM32F10x devices, - * it is equivalent to FLASH_WaitForLastBank1Operation. - * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation - * to complete or a TIMEOUT to occur. - * - For all other devices it waits for a Flash operation to complete - * or a TIMEOUT to occur. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetBank1Status(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -/** - * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. - * @note This function can be used for all STM32F10x devices, - * it is equivalent to FLASH_WaitForLastOperation. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetBank1Status(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -#ifdef STM32F10X_XL -/** - * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur. - * @note This function can be used only for STM32F10x_XL density devices. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetBank2Status(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00)) - { - status = FLASH_GetBank2Status(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} -#endif /* STM32F10X_XL */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c deleted file mode 100644 index c75137ca..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c +++ /dev/null @@ -1,866 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_fsmc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the FSMC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_fsmc.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup FSMC - * @brief FSMC driver modules - * @{ - */ - -/** @defgroup FSMC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup FSMC_Private_Defines - * @{ - */ - -/* --------------------- FSMC registers bit mask ---------------------------- */ - -/* FSMC BCRx Mask */ -#define BCR_MBKEN_Set ((uint32_t)0x00000001) -#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_Set ((uint32_t)0x00000040) - -/* FSMC PCRx Mask */ -#define PCR_PBKEN_Set ((uint32_t)0x00000004) -#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_Set ((uint32_t)0x00000040) -#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) -#define PCR_MemoryType_NAND ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup FSMC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default - * reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @retval None - */ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - - /* FSMC_Bank1_NORSRAM1 */ - if(FSMC_Bank == FSMC_Bank1_NORSRAM1) - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; - } - /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ - else - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; - } - FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; - FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval None - */ -void FSMC_NANDDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Set the FSMC_Bank2 registers to their reset values */ - FSMC_Bank2->PCR2 = 0x00000018; - FSMC_Bank2->SR2 = 0x00000040; - FSMC_Bank2->PMEM2 = 0xFCFCFCFC; - FSMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FSMC_Bank3_NAND */ - else - { - /* Set the FSMC_Bank3 registers to their reset values */ - FSMC_Bank3->PCR3 = 0x00000018; - FSMC_Bank3->SR3 = 0x00000040; - FSMC_Bank3->PMEM3 = 0xFCFCFCFC; - FSMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FSMC_PCCARDDeInit(void) -{ - /* Set the FSMC_Bank4 registers to their reset values */ - FSMC_Bank4->PCR4 = 0x00000018; - FSMC_Bank4->SR4 = 0x00000000; - FSMC_Bank4->PMEM4 = 0xFCFCFCFC; - FSMC_Bank4->PATT4 = 0xFCFCFCFC; - FSMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. - * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef - * structure that contains the configuration information for - * the FSMC NOR/SRAM specified Banks. - * @retval None - */ -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); - assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); - assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); - assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); - assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); - assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); - assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); - assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); - - /* Bank1 NOR/SRAM control register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | - FSMC_NORSRAMInitStruct->FSMC_MemoryType | - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | - FSMC_NORSRAMInitStruct->FSMC_WrapMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | - FSMC_NORSRAMInitStruct->FSMC_WriteOperation | - FSMC_NORSRAMInitStruct->FSMC_WaitSignal | - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | - FSMC_NORSRAMInitStruct->FSMC_WriteBurst; - - if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) - { - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; - } - - /* Bank1 NOR/SRAM timing register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; - - - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ - if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) - { - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; - } - else - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; - } -} - -/** - * @brief Initializes the FSMC NAND Banks according to the specified - * parameters in the FSMC_NANDInitStruct. - * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef - * structure that contains the configuration information for the FSMC - * NAND specified Banks. - * @retval None - */ -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); - assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); - assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); - assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); - assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); - assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); - assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ - tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | - PCR_MemoryType_NAND | - FSMC_NANDInitStruct->FSMC_MemoryDataWidth | - FSMC_NANDInitStruct->FSMC_ECC | - FSMC_NANDInitStruct->FSMC_ECCPageSize | - (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| - (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); - - /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ - tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ - tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* FSMC_Bank2_NAND registers configuration */ - FSMC_Bank2->PCR2 = tmppcr; - FSMC_Bank2->PMEM2 = tmppmem; - FSMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FSMC_Bank3_NAND registers configuration */ - FSMC_Bank3->PCR3 = tmppcr; - FSMC_Bank3->PMEM3 = tmppmem; - FSMC_Bank3->PATT3 = tmppatt; - } -} - -/** - * @brief Initializes the FSMC PCCARD Bank according to the specified - * parameters in the FSMC_PCCARDInitStruct. - * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef - * structure that contains the configuration information for the FSMC - * PCCARD Bank. - * @retval None - */ -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); - assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ - FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | - FSMC_MemoryDataWidth_16b | - (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | - (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); - - /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ - FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ - FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ - FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); -} - -/** - * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. - * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; - FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; -} - -/** - * @brief Fills each FSMC_NANDInitStruct member with its default value. - * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; - FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; - FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Fills each FSMC_PCCARDInitStruct member with its default value. - * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; - } -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; - } - else - { - FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; - } - else - { - FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; - } - } -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; - } -} - -/** - * @brief Enables or disables the FSMC NAND ECC feature. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; - } - else - { - FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; - } - else - { - FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FSMC_GetECC(uint32_t FSMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FSMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FSMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} - -/** - * @brief Enables or disables the specified FSMC interrupts. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @param NewState: new state of the specified FSMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) -{ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 |= FSMC_IT; - } - } - else - { - /* Disable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - - FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FSMC flag is set or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. - * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. - * @retval The new state of FSMC_FLAG (SET or RESET). - */ -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - /* Get the flag status */ - if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FSMC's pending flags. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. - * @retval None - */ -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~FSMC_FLAG; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~FSMC_FLAG; - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~FSMC_FLAG; - } -} - -/** - * @brief Checks whether the specified FSMC interrupt has occurred or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval The new state of FSMC_IT (SET or RESET). - */ -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - itstatus = tmpsr & FSMC_IT; - - itenable = tmpsr & (FSMC_IT >> 3); - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FSMC's interrupt pending bits. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval None - */ -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c deleted file mode 100644 index 88967268..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c +++ /dev/null @@ -1,1331 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_i2c.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the I2C firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_i2c.h" -#include "stm32f10x_rcc.h" - - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/** @defgroup I2C_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Defines - * @{ - */ - -/* I2C SPE mask */ -#define CR1_PE_Set ((uint16_t)0x0001) -#define CR1_PE_Reset ((uint16_t)0xFFFE) - -/* I2C START mask */ -#define CR1_START_Set ((uint16_t)0x0100) -#define CR1_START_Reset ((uint16_t)0xFEFF) - -/* I2C STOP mask */ -#define CR1_STOP_Set ((uint16_t)0x0200) -#define CR1_STOP_Reset ((uint16_t)0xFDFF) - -/* I2C ACK mask */ -#define CR1_ACK_Set ((uint16_t)0x0400) -#define CR1_ACK_Reset ((uint16_t)0xFBFF) - -/* I2C ENGC mask */ -#define CR1_ENGC_Set ((uint16_t)0x0040) -#define CR1_ENGC_Reset ((uint16_t)0xFFBF) - -/* I2C SWRST mask */ -#define CR1_SWRST_Set ((uint16_t)0x8000) -#define CR1_SWRST_Reset ((uint16_t)0x7FFF) - -/* I2C PEC mask */ -#define CR1_PEC_Set ((uint16_t)0x1000) -#define CR1_PEC_Reset ((uint16_t)0xEFFF) - -/* I2C ENPEC mask */ -#define CR1_ENPEC_Set ((uint16_t)0x0020) -#define CR1_ENPEC_Reset ((uint16_t)0xFFDF) - -/* I2C ENARP mask */ -#define CR1_ENARP_Set ((uint16_t)0x0010) -#define CR1_ENARP_Reset ((uint16_t)0xFFEF) - -/* I2C NOSTRETCH mask */ -#define CR1_NOSTRETCH_Set ((uint16_t)0x0080) -#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) - -/* I2C registers Masks */ -#define CR1_CLEAR_Mask ((uint16_t)0xFBF5) - -/* I2C DMAEN mask */ -#define CR2_DMAEN_Set ((uint16_t)0x0800) -#define CR2_DMAEN_Reset ((uint16_t)0xF7FF) - -/* I2C LAST mask */ -#define CR2_LAST_Set ((uint16_t)0x1000) -#define CR2_LAST_Reset ((uint16_t)0xEFFF) - -/* I2C FREQ mask */ -#define CR2_FREQ_Reset ((uint16_t)0xFFC0) - -/* I2C ADD0 mask */ -#define OAR1_ADD0_Set ((uint16_t)0x0001) -#define OAR1_ADD0_Reset ((uint16_t)0xFFFE) - -/* I2C ENDUAL mask */ -#define OAR2_ENDUAL_Set ((uint16_t)0x0001) -#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE) - -/* I2C ADD2 mask */ -#define OAR2_ADD2_Reset ((uint16_t)0xFF01) - -/* I2C F/S mask */ -#define CCR_FS_Set ((uint16_t)0x8000) - -/* I2C CCR mask */ -#define CCR_CCR_Set ((uint16_t)0x0FFF) - -/* I2C FLAG mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) - -/* I2C Interrupt Enable mask */ -#define ITEN_Mask ((uint32_t)0x07000000) - -/** - * @} - */ - -/** @defgroup I2C_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the I2Cx peripheral registers to their default reset values. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval None - */ -void I2C_DeInit(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - if (I2Cx == I2C1) - { - /* Enable I2C1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); - /* Release I2C1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); - } - else - { - /* Enable I2C2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); - /* Release I2C2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); - } -} - -/** - * @brief Initializes the I2Cx peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified I2C peripheral. - * @retval None - */ -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) -{ - uint16_t tmpreg = 0, freqrange = 0; - uint16_t result = 0x04; - uint32_t pclk1 = 8000000; - RCC_ClocksTypeDef rcc_clocks; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - -/*---------------------------- I2Cx CR2 Configuration ------------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear frequency FREQ[5:0] bits */ - tmpreg &= CR2_FREQ_Reset; - /* Get pclk1 frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - /* Set frequency bits depending on pclk1 value */ - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; - -/*---------------------------- I2Cx CCR Configuration ------------------------*/ - /* Disable the selected I2C peripheral to configure TRISE */ - I2Cx->CR1 &= CR1_PE_Reset; - /* Reset tmpreg value */ - /* Clear F/S, DUTY and CCR[11:0] bits */ - tmpreg = 0; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - /* Standard mode speed calculate */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - /* Test if CCR value is under 0x4*/ - if (result < 0x04) - { - /* Set minimum allowed value */ - result = 0x04; - } - /* Set speed value for standard mode */ - tmpreg |= result; - /* Set Maximum Rise Time for standard mode */ - I2Cx->TRISE = freqrange + 1; - } - /* Configure speed in fast mode */ - else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ - { - if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - /* Fast mode speed calculate: Tlow/Thigh = 2 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ - { - /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - /* Set DUTY bit */ - result |= I2C_DutyCycle_16_9; - } - - /* Test if CCR value is under 0x1*/ - if ((result & CCR_CCR_Set) == 0) - { - /* Set minimum allowed value */ - result |= (uint16_t)0x0001; - } - /* Set speed value and set F/S bit for fast mode */ - tmpreg |= (uint16_t)(result | CCR_FS_Set); - /* Set Maximum Rise Time for fast mode */ - I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - /* Write to I2Cx CCR */ - I2Cx->CCR = tmpreg; - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= CR1_PE_Set; - -/*---------------------------- I2Cx CR1 Configuration ------------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear ACK, SMBTYPE and SMBUS bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure I2Cx: mode and acknowledgement */ - /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ - /* Set ACK bit according to I2C_Ack value */ - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - -/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ - /* Set I2Cx Own Address1 and acknowledged address */ - I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ -/*---------------- Reset I2C init structure parameters values ----------------*/ - /* initialize the I2C_ClockSpeed member */ - I2C_InitStruct->I2C_ClockSpeed = 5000; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_DutyCycle member */ - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= CR1_PE_Set; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= CR1_PE_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C DMA requests. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR2 |= CR2_DMAEN_Set; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR2 &= CR2_DMAEN_Reset; - } -} - -/** - * @brief Specifies if the next DMA transfer will be the last one. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Next DMA transfer is the last transfer */ - I2Cx->CR2 |= CR2_LAST_Set; - } - else - { - /* Next DMA transfer is not the last transfer */ - I2Cx->CR2 &= CR2_LAST_Reset; - } -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR1 |= CR1_START_Set; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR1 &= CR1_START_Reset; - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR1 |= CR1_STOP_Set; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR1 &= CR1_STOP_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C acknowledge feature. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C Acknowledgement. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the acknowledgement */ - I2Cx->CR1 |= CR1_ACK_Set; - } - else - { - /* Disable the acknowledgement */ - I2Cx->CR1 &= CR1_ACK_Reset; - } -} - -/** - * @brief Configures the specified I2C own address2. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the 7bit I2C own address2. - * @retval None. - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx Own address2 bit [7:1] */ - tmpreg &= OAR2_ADD2_Reset; - - /* Set I2Cx Own address2 */ - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the specified I2C dual addressing mode. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C dual addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable dual addressing mode */ - I2Cx->OAR2 |= OAR2_ENDUAL_Set; - } - else - { - /* Disable dual addressing mode */ - I2Cx->OAR2 &= OAR2_ENDUAL_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C general call feature. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C General call. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable generall call */ - I2Cx->CR1 |= CR1_ENGC_Set; - } - else - { - /* Disable generall call */ - I2Cx->CR1 &= CR1_ENGC_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_BUF: Buffer interrupt mask - * @arg I2C_IT_EVT: Event interrupt mask - * @arg I2C_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR2 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR2 &= (uint16_t)~I2C_IT; - } -} - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Write in the DR register the data to be sent */ - I2Cx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the data in the DR register */ - return (uint8_t)I2Cx->DR; -} - -/** - * @brief Transmits the address byte to select the slave device. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address which will be transmitted - * @param I2C_Direction: specifies whether the I2C device will be a - * Transmitter or a Receiver. This parameter can be one of the following values - * @arg I2C_Direction_Transmitter: Transmitter mode - * @arg I2C_Direction_Receiver: Receiver mode - * @retval None. - */ -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction != I2C_Direction_Transmitter) - { - /* Set the address bit0 for read */ - Address |= OAR1_ADD0_Set; - } - else - { - /* Reset the address bit0 for write */ - Address &= OAR1_ADD0_Reset; - } - /* Send the address */ - I2Cx->DR = Address; -} - -/** - * @brief Reads the specified I2C register and returns its value. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_DR: DR register. - * @arg I2C_Register_SR1: SR1 register. - * @arg I2C_Register_SR2: SR2 register. - * @arg I2C_Register_CCR: CCR register. - * @arg I2C_Register_TRISE: TRISE register. - * @retval The value of the read register. - */ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t) I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Peripheral under reset */ - I2Cx->CR1 |= CR1_SWRST_Set; - } - else - { - /* Peripheral not under reset */ - I2Cx->CR1 &= CR1_SWRST_Reset; - } -} - -/** - * @brief Selects the specified I2C NACK position in master receiver mode. - * This function is useful in I2C Master Receiver mode when the number - * of data to be received is equal to 2. In this case, this function - * should be called (with parameter I2C_NACKPosition_Next) before data - * reception starts,as described in the 2-byte reception procedure - * recommended in Reference Manual in Section: Master receiver. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_NACKPosition: specifies the NACK position. - * This parameter can be one of the following values: - * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last - * received byte. - * @arg I2C_NACKPosition_Current: indicates that current byte is the last - * received byte. - * - * @note This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * - * @retval None - */ -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); - - /* Check the input parameter */ - if (I2C_NACKPosition == I2C_NACKPosition_Next) - { - /* Next byte in shift register is the last received byte */ - I2Cx->CR1 |= I2C_NACKPosition_Next; - } - else - { - /* Current byte in shift register is the last received byte */ - I2Cx->CR1 &= I2C_NACKPosition_Current; - } -} - -/** - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_SMBusAlert: specifies SMBAlert pin level. - * This parameter can be one of the following values: - * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low - * @arg I2C_SMBusAlert_High: SMBAlert pin driven high - * @retval None - */ -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); - if (I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - /* Drive the SMBusAlert pin Low */ - I2Cx->CR1 |= I2C_SMBusAlert_Low; - } - else - { - /* Drive the SMBusAlert pin High */ - I2Cx->CR1 &= I2C_SMBusAlert_High; - } -} - -/** - * @brief Enables or disables the specified I2C PEC transfer. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C PEC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC transmission */ - I2Cx->CR1 |= CR1_PEC_Set; - } - else - { - /* Disable the selected I2C PEC transmission */ - I2Cx->CR1 &= CR1_PEC_Reset; - } -} - -/** - * @brief Selects the specified I2C PEC position. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_PECPosition: specifies the PEC position. - * This parameter can be one of the following values: - * @arg I2C_PECPosition_Next: indicates that the next byte is PEC - * @arg I2C_PECPosition_Current: indicates that current byte is PEC - * - * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() - * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() - * is intended to used in I2C mode. - * - * @retval None - */ -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); - if (I2C_PECPosition == I2C_PECPosition_Next) - { - /* Next byte in shift register is PEC */ - I2Cx->CR1 |= I2C_PECPosition_Next; - } - else - { - /* Current byte in shift register is PEC */ - I2Cx->CR1 &= I2C_PECPosition_Current; - } -} - -/** - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC calculation */ - I2Cx->CR1 |= CR1_ENPEC_Set; - } - else - { - /* Disable the selected I2C PEC calculation */ - I2Cx->CR1 &= CR1_ENPEC_Reset; - } -} - -/** - * @brief Returns the PEC value for the specified I2C. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the selected I2C PEC value */ - return ((I2Cx->SR2) >> 8); -} - -/** - * @brief Enables or disables the specified I2C ARP. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx ARP. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C ARP */ - I2Cx->CR1 |= CR1_ENARP_Set; - } - else - { - /* Disable the selected I2C ARP */ - I2Cx->CR1 &= CR1_ENARP_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C Clock stretching. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState == DISABLE) - { - /* Enable the selected I2C Clock stretching */ - I2Cx->CR1 |= CR1_NOSTRETCH_Set; - } - else - { - /* Disable the selected I2C Clock stretching */ - I2Cx->CR1 &= CR1_NOSTRETCH_Reset; - } -} - -/** - * @brief Selects the specified I2C fast mode duty cycle. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_DutyCycle: specifies the fast mode duty cycle. - * This parameter can be one of the following values: - * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 - * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 - * @retval None - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); - if (I2C_DutyCycle != I2C_DutyCycle_16_9) - { - /* I2C fast mode Tlow/Thigh=2 */ - I2Cx->CCR &= I2C_DutyCycle_2; - } - else - { - /* I2C fast mode Tlow/Thigh=16/9 */ - I2Cx->CCR |= I2C_DutyCycle_16_9; - } -} - - - -/** - * @brief - **************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * depending on the application requirements and constraints: - * - * - * 1) Basic state monitoring: - * Using I2C_CheckEvent() function: - * It compares the status registers (SR1 and SR2) content to a given event - * (can be the combination of one or more flags). - * It returns SUCCESS if the current status includes the given flags - * and returns ERROR if one or more flags are missing in the current status. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (RM0008). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs (ie. error flags are set besides to the monitored flags), - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * hold or corrupted real state. - * In this case, it is advised to use error interrupts to monitor the error - * events and handle them in the interrupt IRQ handler. - * - * @note - * For error management, it is advised to use the following functions: - * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() - * in order to determine which error occured. - * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - * and/or I2C_GenerateStop() in order to clear the error flag and source, - * and return to correct communication status. - * - * - * 2) Advanced state monitoring: - * Using the function I2C_GetLastEvent() which returns the image of both status - * registers in a single word (uint32_t) (Status Register 2 value is shifted left - * by 16 bits and concatenated to Status Register 1). - * - When to use: - * - This function is suitable for the same applications above but it allows to - * overcome the mentioned limitation of I2C_GetFlagStatus() function. - * The returned value could be compared to events already defined in the - * library (stm32f10x_i2c.h) or to custom values defined by user. - * - This function is suitable when multiple flags are monitored at the same time. - * - At the opposite of I2C_CheckEvent() function, this function allows user to - * choose when an event is accepted (when all events flags are set and no - * other flags are set or just when the needed flags are set like - * I2C_CheckEvent() function). - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * 3) Flag-based state monitoring: - * Using the function I2C_GetFlagStatus() which simply returns the status of - * one single flag (ie. I2C_FLAG_RXNE ...). - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed (most I2C events - * are monitored through multiple flags). - * - Limitations: - * - When calling this function, the Status register is accessed. Some flags are - * cleared when the status register is accessed. So checking the status - * of one Flag, may clear other ones. - * - Function may need to be called twice or more in order to monitor one - * single event. - * - * For detailed description of Events, please refer to section I2C_Events in - * stm32f10x_i2c.h file. - * - */ - -/** - * - * 1) Basic state monitoring - ******************************************************************************* - */ - -/** - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_EVENT: specifies the event to be checked. - * This parameter can be one of the following values: - * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2 - * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3 - * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 - * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 - * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 - * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 - * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 - * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 - * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 - * - * @note: For detailed description of Events, please refer to section - * I2C_Events in stm32f10x_i2c.h file. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Last event is equal to the I2C_EVENT - * - ERROR: Last event is different from the I2C_EVENT - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_EVENT(I2C_EVENT)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_Mask; - - /* Check whether the last event contains the I2C_EVENT */ - if ((lastevent & I2C_EVENT) == I2C_EVENT) - { - /* SUCCESS: last event is equal to I2C_EVENT */ - status = SUCCESS; - } - else - { - /* ERROR: last event is different from I2C_EVENT */ - status = ERROR; - } - /* Return status */ - return status; -} - -/** - * - * 2) Advanced state monitoring - ******************************************************************************* - */ - -/** - * @brief Returns the last I2Cx Event. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * - * @note: For detailed description of Events, please refer to section - * I2C_Events in stm32f10x_i2c.h file. - * - * @retval The last event - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_Mask; - - /* Return status */ - return lastevent; -} - -/** - * - * 3) Flag-based state monitoring - ******************************************************************************* - */ - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) - * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) - * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) - * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) - * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag - * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) - * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDA" - * @arg I2C_FLAG_SB: Start bit flag (Master mode) - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the I2Cx peripheral base address */ - i2cxbase = (uint32_t)I2Cx; - - /* Read flag register index */ - i2creg = I2C_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - I2C_FLAG &= FLAG_Mask; - - if(i2creg != 0) - { - /* Get the I2Cx SR1 register address */ - i2cxbase += 0x14; - } - else - { - /* Flag in I2Cx SR2 Register */ - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - /* Get the I2Cx SR2 register address */ - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the I2C_FLAG status */ - return bitstatus; -} - - - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * - * @note - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR - * register (I2C_SendData()). - * @retval None - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - /* Get the I2C flag position */ - flagpos = I2C_FLAG & FLAG_Mask; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert flag - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_IT_PECERR: PEC error in reception flag - * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure flag - * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_IT_BERR: Bus error flag - * @arg I2C_IT_TXE: Data register empty flag (Transmitter) - * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag - * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) - * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_IT_BTF: Byte transfer finished flag - * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_IT_SB: Start bit flag (Master mode) - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ; - - /* Get bit[23:0] of the flag */ - I2C_IT &= FLAG_Mask; - - /* Check the status of the specified I2C flag */ - if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx’s interrupt pending bits. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert interrupt - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt - * @arg I2C_IT_PECERR: PEC error in reception interrupt - * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure interrupt - * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) - * @arg I2C_IT_BERR: Bus error interrupt - * - * @note - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DR register (I2C_SendData()). - * @retval None - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - /* Get the I2C flag position */ - flagpos = I2C_IT & FLAG_Mask; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c deleted file mode 100644 index 9d3b0e85..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c +++ /dev/null @@ -1,190 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_iwdg.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the IWDG firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_iwdg.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/** @defgroup IWDG_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Defines - * @{ - */ - -/* ---------------------- IWDG registers bit mask ----------------------------*/ - -/* KR register bit mask */ -#define KR_KEY_Reload ((uint16_t)0xAAAA) -#define KR_KEY_Enable ((uint16_t)0xCCCC) - -/** - * @} - */ - -/** @defgroup IWDG_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_Reload; -} - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_Enable; -} - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c deleted file mode 100644 index 147bf0f8..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c +++ /dev/null @@ -1,307 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_pwr.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the PWR firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_pwr.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/** @defgroup PWR_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Defines - * @{ - */ - -/* --------- PWR registers bit address in the alias region ---------- */ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of DBP bit */ -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BitNumber 0x04 -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of EWUP bit */ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -#define EWUP_BitNumber 0x08 -#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) - - -/** - * @} - */ - -/** @defgroup PWR_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the RTC and backup registers. - * @param NewState: new state of the access to the RTC and backup registers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V - * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V - * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V - * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V - * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V - * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V - * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V - * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - tmpreg = PWR->CR; - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_MASK; - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; -} - -/** - * @brief Enters STOP mode. - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: STOP mode with regulator ON - * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDS bits */ - tmpreg &= CR_DS_MASK; - /* Set LPDS bit according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - /* Store the new value */ - PWR->CR = tmpreg; - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); -} - -/** - * @brief Enters STANDBY mode. - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Clear Wake-up flag */ - PWR->CR |= PWR_CR_CWUF; - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP; -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM ) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @arg PWR_FLAG_PVDO: PVD Output - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - - PWR->CR |= PWR_FLAG << 2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c deleted file mode 100644 index 4b2ec1f1..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c +++ /dev/null @@ -1,1470 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rcc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the RCC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/** @defgroup RCC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Defines - * @{ - */ - -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) - -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) - -#ifdef STM32F10X_CL - /* Alias word address of PLL2ON bit */ - #define PLL2ON_BitNumber 0x1A - #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) - - /* Alias word address of PLL3ON bit */ - #define PLL3ON_BitNumber 0x1C - #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) - -/* --- CFGR Register ---*/ - -/* Alias word address of USBPRE bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x04) - -#ifndef STM32F10X_CL - #define USBPRE_BitNumber 0x16 - #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) -#else - #define OTGFSPRE_BitNumber 0x16 - #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* --- BDCR Register ---*/ - -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x20) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) - -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x24) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) - -#ifdef STM32F10X_CL -/* --- CFGR2 Register ---*/ - - /* Alias word address of I2S2SRC bit */ - #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) - #define I2S2SRC_BitNumber 0x11 - #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) - - /* Alias word address of I2S3SRC bit */ - #define I2S3SRC_BitNumber 0x12 - #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* ---------------------- RCC registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CR_HSEBYP_Set ((uint32_t)0x00040000) -#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CR_HSEON_Set ((uint32_t)0x00010000) -#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -/* CFGR register bit mask */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) - #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) -#else - #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) -#endif /* STM32F10X_CL */ - -#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) -#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) -#define CFGR_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) -#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) -#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) -#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) -#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) -#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) - -/* CSR register bit mask */ -#define CSR_RMVF_Set ((uint32_t)0x01000000) - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) -/* CFGR2 register bit mask */ - #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) - #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) -#endif -#ifdef STM32F10X_CL - #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) - #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) - #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) -#endif /* STM32F10X_CL */ - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CFGR register byte 4 (Bits[31:24]) base address */ -#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) - -/* BDCR register base address */ -#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - -/** - * @} - */ - -/** @defgroup RCC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Variables - * @{ - */ - -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; - -/** - * @} - */ - -/** @defgroup RCC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#ifndef STM32F10X_CL - RCC->CFGR &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR &= (uint32_t)0xF0FF0000; -#endif /* STM32F10X_CL */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - -#ifdef STM32F10X_CL - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#endif /* STM32F10X_CL */ - -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note HSE can not be stopped if it is used directly or through the PLL as system clock. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: HSE oscillator OFF - * @arg RCC_HSE_ON: HSE oscillator ON - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - /* Reset HSEON bit */ - RCC->CR &= CR_HSEON_Reset; - /* Reset HSEBYP bit */ - RCC->CR &= CR_HSEBYP_Reset; - /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ - switch(RCC_HSE) - { - case RCC_HSE_ON: - /* Set HSEON bit */ - RCC->CR |= CR_HSEON_Set; - break; - - case RCC_HSE_Bypass: - /* Set HSEBYP and HSEON bits */ - RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; - break; - - default: - break; - } -} - -/** - * @brief Waits for HSE start-up. - * @param None - * @retval An ErrorStatus enumuration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - ErrorStatus status = ERROR; - FlagStatus HSEStatus = RESET; - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @param HSICalibrationValue: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - tmpreg = RCC->CR; - /* Clear HSITRIM[4:0] bits */ - tmpreg &= CR_HSITRIM_Mask; - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note HSI can not be stopped if it is used directly or through the PLL as system clock. - * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLL clock source and multiplication factor. - * @note This function must be used only when the PLL is disabled. - * @param RCC_PLLSource: specifies the PLL entry clock source. - * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, - * this parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry - * @param RCC_PLLMul: specifies the PLL multiplication factor. - * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} - * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); - - tmpreg = RCC->CFGR; - /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - tmpreg &= CFGR_PLL_Mask; - /* Set the PLL configuration bits */ - tmpreg |= RCC_PLLSource | RCC_PLLMul; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Enables or disables the PLL. - * @note The PLL can not be disabled if it is used as system clock. - * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) -/** - * @brief Configures the PREDIV1 division factor. - * @note - * - This function must be used only when the PLL is disabled. - * - This function applies only to STM32 Connectivity line and Value line - * devices. - * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. - * This parameter can be one of the following values: - * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock - * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock - * @note - * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE - * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. - * This parameter can be RCC_PREDIV1_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); - assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ - tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); - /* Set the PREDIV1 clock source and division factor */ - tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} -#endif - -#ifdef STM32F10X_CL -/** - * @brief Configures the PREDIV2 division factor. - * @note - * - This function must be used only when both PLL2 and PLL3 are disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. - * This parameter can be RCC_PREDIV2_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV2[3:0] bits */ - tmpreg &= ~CFGR2_PREDIV2; - /* Set the PREDIV2 division factor */ - tmpreg |= RCC_PREDIV2_Div; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - -/** - * @brief Configures the PLL2 multiplication factor. - * @note - * - This function must be used only when the PLL2 is disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. - * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL2Config(uint32_t RCC_PLL2Mul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); - - tmpreg = RCC->CFGR2; - /* Clear PLL2Mul[3:0] bits */ - tmpreg &= ~CFGR2_PLL2MUL; - /* Set the PLL2 configuration bits */ - tmpreg |= RCC_PLL2Mul; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - - -/** - * @brief Enables or disables the PLL2. - * @note - * - The PLL2 can not be disabled if it is used indirectly as system clock - * (i.e. it is used as PLL clock entry that is used as System clock). - * - This function applies only to STM32 Connectivity line devices. - * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL2Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; -} - - -/** - * @brief Configures the PLL3 multiplication factor. - * @note - * - This function must be used only when the PLL3 is disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. - * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL3Config(uint32_t RCC_PLL3Mul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); - - tmpreg = RCC->CFGR2; - /* Clear PLL3Mul[3:0] bits */ - tmpreg &= ~CFGR2_PLL3MUL; - /* Set the PLL3 configuration bits */ - tmpreg |= RCC_PLL3Mul; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - - -/** - * @brief Enables or disables the PLL3. - * @note This function applies only to STM32 Connectivity line devices. - * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL3Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the system clock (SYSCLK). - * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - tmpreg = RCC->CFGR; - /* Clear SW[1:0] bits */ - tmpreg &= CFGR_SW_Mask; - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can - * be one of the following: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - tmpreg = RCC->CFGR; - /* Clear HPRE[3:0] bits */ - tmpreg &= CFGR_HPRE_Reset_Mask; - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - tmpreg = RCC->CFGR; - /* Clear PPRE1[2:0] bits */ - tmpreg &= CFGR_PPRE1_Reset_Mask; - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - tmpreg = RCC->CFGR; - /* Clear PPRE2[2:0] bits */ - tmpreg &= CFGR_PPRE2_Reset_Mask; - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Enables or disables the specified RCC interrupts. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -#ifndef STM32F10X_CL -/** - * @brief Configures the USB clock (USBCLK). - * @param RCC_USBCLKSource: specifies the USB clock source. This clock is - * derived from the PLL output. - * This parameter can be one of the following values: - * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB - * clock source - * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source - * @retval None - */ -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); - - *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; -} -#else -/** - * @brief Configures the USB OTG FS clock (OTGFSCLK). - * This function applies only to STM32 Connectivity line devices. - * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. - * This clock is derived from the PLL output. - * This parameter can be one of the following values: - * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source - * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source - * @retval None - */ -void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); - - *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the ADC clock (ADCCLK). - * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from - * the APB2 clock (PCLK2). - * This parameter can be one of the following values: - * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 - * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 - * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 - * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 - * @retval None - */ -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); - tmpreg = RCC->CFGR; - /* Clear ADCPRE[1:0] bits */ - tmpreg &= CFGR_ADCPRE_Reset_Mask; - /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ - tmpreg |= RCC_PCLK2; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -#ifdef STM32F10X_CL -/** - * @brief Configures the I2S2 clock source(I2S2CLK). - * @note - * - This function must be called before enabling I2S2 APB clock. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry - * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry - * @retval None - */ -void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); - - *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; -} - -/** - * @brief Configures the I2S3 clock source(I2S2CLK). - * @note - * - This function must be called before enabling I2S3 APB clock. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry - * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry - * @retval None - */ -void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); - - *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: LSE oscillator OFF - * @arg RCC_LSE_ON: LSE oscillator ON - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - /* Reset LSEBYP bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - switch(RCC_LSE) - { - case RCC_LSE_ON: - /* Set LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - break; - - case RCC_LSE_Bypass: - /* Set LSEBYP and LSEON bits */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - - default: - break; - } -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset. - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - /* Select the RTC clock source */ - RCC->BDCR |= RCC_RTCCLKSource; -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Returns the frequencies of different on chip clocks. - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * @note The result of this function could be not correct when using - * fractional value for HSE crystal. - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; - -#ifdef STM32F10X_CL - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - uint32_t prediv1factor = 0; -#endif - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & CFGR_SWS_Mask; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & CFGR_PLLMull_Mask; - pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; - -#ifndef STM32F10X_CL - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; - } - else - { - #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; - #else - /* HSE selected as PLL clock entry */ - if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; - } - else - { - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; - } - #endif - } -#else - pllmull = pllmull >> 18; - - if (pllmull != 0x0D) - { - pllmull += 2; - } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; - } - - if (pllsource == 0x00) - {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; - - if (prediv1source == 0) - { /* HSE oscillator clock selected as PREDIV1 clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; - RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; - } - } -#endif /* STM32F10X_CL */ - break; - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - - /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ - /* Get HCLK prescaler */ - tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; - tmp = tmp >> 11; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - /* Get ADCCLK prescaler */ - tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; - tmp = tmp >> 14; - presc = ADCPrescTable[tmp]; - /* ADCCLK clock frequency */ - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; -} - -/** - * @brief Enables or disables the AHB peripheral clock. - * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values: - * @arg RCC_AHBPeriph_DMA1 - * @arg RCC_AHBPeriph_DMA2 - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_FLITF - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_OTG_FS - * @arg RCC_AHBPeriph_ETH_MAC - * @arg RCC_AHBPeriph_ETH_MAC_Tx - * @arg RCC_AHBPeriph_ETH_MAC_Rx - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values: - * @arg RCC_AHBPeriph_DMA1 - * @arg RCC_AHBPeriph_DMA2 - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_FLITF - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_FSMC - * @arg RCC_AHBPeriph_SDIO - * - * @note SRAM and FLITF clock can be disabled only during sleep mode. - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBENR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, - * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, - * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, - * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, - * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, - * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, - * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, - * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, - * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, - * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, - * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, - * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, - * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -#ifdef STM32F10X_CL -/** - * @brief Forces or releases AHB peripheral reset. - * @note This function applies only to STM32 Connectivity line devices. - * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_OTG_FS - * @arg RCC_AHBPeriph_ETH_MAC - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBRSTR |= RCC_AHBPeriph; - } - else - { - RCC->AHBRSTR &= ~RCC_AHBPeriph; - } -} -#endif /* STM32F10X_CL */ - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, - * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, - * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, - * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, - * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, - * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, - * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, - * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, - * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, - * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, - * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, - * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, - * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases the Backup domain reset. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @param NewState: new state of the Clock Security System.. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO pin. - * @param RCC_MCO: specifies the clock source to output. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_MCO_NoClock: No clock selected - * @arg RCC_MCO_SYSCLK: System clock selected - * @arg RCC_MCO_HSI: HSI oscillator clock selected - * @arg RCC_MCO_HSE: HSE oscillator clock selected - * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected - * @arg RCC_MCO_PLL2CLK: PLL2 clock selected - * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected - * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected - * @arg RCC_MCO_PLL3CLK: PLL3 clock selected - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_MCO_NoClock: No clock selected - * @arg RCC_MCO_SYSCLK: System clock selected - * @arg RCC_MCO_HSI: HSI oscillator clock selected - * @arg RCC_MCO_HSE: HSE oscillator clock selected - * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected - * - * @retval None - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCO)); - - /* Perform Byte access to MCO bits to select the MCO source */ - *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready - * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 2) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_Mask; - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= CSR_RMVF_Set; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c deleted file mode 100644 index f798d2bd..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c +++ /dev/null @@ -1,339 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rtc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the RTC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_rtc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/** @defgroup RTC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup RTC_Private_Defines - * @{ - */ -#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ -#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RTC->CRH |= RTC_IT; - } - else - { - RTC->CRH &= (uint16_t)~RTC_IT; - } -} - -/** - * @brief Enters the RTC configuration mode. - * @param None - * @retval None - */ -void RTC_EnterConfigMode(void) -{ - /* Set the CNF flag to enter in the Configuration Mode */ - RTC->CRL |= RTC_CRL_CNF; -} - -/** - * @brief Exits from the RTC configuration mode. - * @param None - * @retval None - */ -void RTC_ExitConfigMode(void) -{ - /* Reset the CNF flag to exit from the Configuration Mode */ - RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); -} - -/** - * @brief Gets the RTC counter value. - * @param None - * @retval RTC counter value. - */ -uint32_t RTC_GetCounter(void) -{ - uint16_t tmp = 0; - tmp = RTC->CNTL; - return (((uint32_t)RTC->CNTH << 16 ) | tmp) ; -} - -/** - * @brief Sets the RTC counter value. - * @param CounterValue: RTC counter new value. - * @retval None - */ -void RTC_SetCounter(uint32_t CounterValue) -{ - RTC_EnterConfigMode(); - /* Set RTC COUNTER MSB word */ - RTC->CNTH = CounterValue >> 16; - /* Set RTC COUNTER LSB word */ - RTC->CNTL = (CounterValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/** - * @brief Sets the RTC prescaler value. - * @param PrescalerValue: RTC prescaler new value. - * @retval None - */ -void RTC_SetPrescaler(uint32_t PrescalerValue) -{ - /* Check the parameters */ - assert_param(IS_RTC_PRESCALER(PrescalerValue)); - - RTC_EnterConfigMode(); - /* Set RTC PRESCALER MSB word */ - RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16; - /* Set RTC PRESCALER LSB word */ - RTC->PRLL = (PrescalerValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/** - * @brief Sets the RTC alarm value. - * @param AlarmValue: RTC alarm new value. - * @retval None - */ -void RTC_SetAlarm(uint32_t AlarmValue) -{ - RTC_EnterConfigMode(); - /* Set the ALARM MSB word */ - RTC->ALRH = AlarmValue >> 16; - /* Set the ALARM LSB word */ - RTC->ALRL = (AlarmValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/** - * @brief Gets the RTC divider value. - * @param None - * @retval RTC Divider value. - */ -uint32_t RTC_GetDivider(void) -{ - uint32_t tmp = 0x00; - tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; - tmp |= RTC->DIVL; - return tmp; -} - -/** - * @brief Waits until last write operation on RTC registers has finished. - * @note This function must be called before any write to RTC registers. - * @param None - * @retval None - */ -void RTC_WaitForLastTask(void) -{ - /* Loop until RTOFF flag is set */ - while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) - { - } -} - -/** - * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) - * are synchronized with RTC APB clock. - * @note This function must be called before any read operation after an APB reset - * or an APB clock stop. - * @param None - * @retval None - */ -void RTC_WaitForSynchro(void) -{ - /* Clear RSF flag */ - RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; - /* Loop until RSF flag is set */ - while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) - { - } -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one the following values: - * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_OW: Overflow flag - * @arg RTC_FLAG_ALR: Alarm flag - * @arg RTC_FLAG_SEC: Second flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's pending flags. - * @param RTC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after - * an APB reset or an APB Clock stop. - * @arg RTC_FLAG_OW: Overflow flag - * @arg RTC_FLAG_ALR: Alarm flag - * @arg RTC_FLAG_SEC: Second flag - * @retval None - */ -void RTC_ClearFlag(uint16_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the corresponding RTC flag */ - RTC->CRL &= (uint16_t)~RTC_FLAG; -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupts sources to check. - * This parameter can be one of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @retval The new state of the RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint16_t RTC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - bitstatus = (ITStatus)(RTC->CRL & RTC_IT); - if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's interrupt pending bits. - * @param RTC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint16_t RTC_IT) -{ - /* Check the parameters */ - assert_param(IS_RTC_IT(RTC_IT)); - - /* Clear the corresponding RTC pending bit */ - RTC->CRL &= (uint16_t)~RTC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c deleted file mode 100644 index d1870cef..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c +++ /dev/null @@ -1,799 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_sdio.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the SDIO firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_sdio.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup SDIO - * @brief SDIO driver modules - * @{ - */ - -/** @defgroup SDIO_Private_TypesDefinitions - * @{ - */ - -/* ------------ SDIO registers bit address in the alias region ----------- */ -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* --- CLKCR Register ---*/ - -/* Alias word address of CLKEN bit */ -#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) -#define CLKEN_BitNumber 0x08 -#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) - -/* --- CMD Register ---*/ - -/* Alias word address of SDIOSUSPEND bit */ -#define CMD_OFFSET (SDIO_OFFSET + 0x0C) -#define SDIOSUSPEND_BitNumber 0x0B -#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) - -/* Alias word address of ENCMDCOMPL bit */ -#define ENCMDCOMPL_BitNumber 0x0C -#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) - -/* Alias word address of NIEN bit */ -#define NIEN_BitNumber 0x0D -#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) - -/* Alias word address of ATACMD bit */ -#define ATACMD_BitNumber 0x0E -#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) - -/* --- DCTRL Register ---*/ - -/* Alias word address of DMAEN bit */ -#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) -#define DMAEN_BitNumber 0x03 -#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) - -/* Alias word address of RWSTART bit */ -#define RWSTART_BitNumber 0x08 -#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) - -/* Alias word address of RWSTOP bit */ -#define RWSTOP_BitNumber 0x09 -#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) - -/* Alias word address of RWMOD bit */ -#define RWMOD_BitNumber 0x0A -#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) - -/* Alias word address of SDIOEN bit */ -#define SDIOEN_BitNumber 0x0B -#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) - -/* ---------------------- SDIO registers bit mask ------------------------ */ - -/* --- CLKCR Register ---*/ - -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) - -/* --- PWRCTRL Register ---*/ - -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - -/* --- DCTRL Register ---*/ - -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) - -/* --- CMD Register ---*/ - -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/** - * @} - */ - -/** @defgroup SDIO_Private_Defines - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the SDIO peripheral registers to their default reset values. - * @param None - * @retval None - */ -void SDIO_DeInit(void) -{ - SDIO->POWER = 0x00000000; - SDIO->CLKCR = 0x00000000; - SDIO->ARG = 0x00000000; - SDIO->CMD = 0x00000000; - SDIO->DTIMER = 0x00000000; - SDIO->DLEN = 0x00000000; - SDIO->DCTRL = 0x00000000; - SDIO->ICR = 0x00C007FF; - SDIO->MASK = 0x00000000; -} - -/** - * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. - * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. - * @retval None - */ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); - assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); - assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); - assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); - assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); - -/*---------------------------- SDIO CLKCR Configuration ------------------------*/ - /* Get the SDIO CLKCR value */ - tmpreg = SDIO->CLKCR; - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - tmpreg &= CLKCR_CLEAR_MASK; - - /* Set CLKDIV bits according to SDIO_ClockDiv value */ - /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ - /* Set BYPASS bit according to SDIO_ClockBypass value */ - /* Set WIDBUS bits according to SDIO_BusWide value */ - /* Set NEGEDGE bits according to SDIO_ClockEdge value */ - /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ - tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | - SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | - SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); - - /* Write to SDIO CLKCR */ - SDIO->CLKCR = tmpreg; -} - -/** - * @brief Fills each SDIO_InitStruct member with its default value. - * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) -{ - /* SDIO_InitStruct members default value */ - SDIO_InitStruct->SDIO_ClockDiv = 0x00; - SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; -} - -/** - * @brief Enables or disables the SDIO Clock. - * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ClockCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; -} - -/** - * @brief Sets the power status of the controller. - * @param SDIO_PowerState: new state of the Power state. - * This parameter can be one of the following values: - * @arg SDIO_PowerState_OFF - * @arg SDIO_PowerState_ON - * @retval None - */ -void SDIO_SetPowerState(uint32_t SDIO_PowerState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); - - SDIO->POWER &= PWR_PWRCTRL_MASK; - SDIO->POWER |= SDIO_PowerState; -} - -/** - * @brief Gets the power status of the controller. - * @param None - * @retval Power status of the controller. The returned value can - * be one of the following: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPowerState(void) -{ - return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); -} - -/** - * @brief Enables or disables the SDIO interrupts. - * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @param NewState: new state of the specified SDIO interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_IT(SDIO_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SDIO interrupts */ - SDIO->MASK |= SDIO_IT; - } - else - { - /* Disable the SDIO interrupts */ - SDIO->MASK &= ~SDIO_IT; - } -} - -/** - * @brief Enables or disables the SDIO DMA request. - * @param NewState: new state of the selected SDIO DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; -} - -/** - * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. - * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); - assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); - assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); - assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); - -/*---------------------------- SDIO ARG Configuration ------------------------*/ - /* Set the SDIO Argument value */ - SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; - -/*---------------------------- SDIO CMD Configuration ------------------------*/ - /* Get the SDIO CMD value */ - tmpreg = SDIO->CMD; - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ - tmpreg &= CMD_CLEAR_MASK; - /* Set CMDINDEX bits according to SDIO_CmdIndex value */ - /* Set WAITRESP bits according to SDIO_Response value */ - /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ - /* Set CPSMEN bits according to SDIO_CPSM value */ - tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response - | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; - - /* Write to SDIO CMD */ - SDIO->CMD = tmpreg; -} - -/** - * @brief Fills each SDIO_CmdInitStruct member with its default value. - * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. - * @retval None - */ -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) -{ - /* SDIO_CmdInitStruct members default value */ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -/** - * @brief Returns command index of last command for which response received. - * @param None - * @retval Returns the command index of the last command response received. - */ -uint8_t SDIO_GetCommandResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/** - * @brief Returns response received from the card for the last command. - * @param SDIO_RESP: Specifies the SDIO response register. - * This parameter can be one of the following values: - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_RESP(SDIO_RESP)); - - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @brief Initializes the SDIO data path according to the specified - * parameters in the SDIO_DataInitStruct. - * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that - * contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); - assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); - assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); - assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); - assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); - -/*---------------------------- SDIO DTIMER Configuration ---------------------*/ - /* Set the SDIO Data TimeOut value */ - SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; - -/*---------------------------- SDIO DLEN Configuration -----------------------*/ - /* Set the SDIO DataLength value */ - SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; - -/*---------------------------- SDIO DCTRL Configuration ----------------------*/ - /* Get the SDIO DCTRL value */ - tmpreg = SDIO->DCTRL; - /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ - tmpreg &= DCTRL_CLEAR_MASK; - /* Set DEN bit according to SDIO_DPSM value */ - /* Set DTMODE bit according to SDIO_TransferMode value */ - /* Set DTDIR bit according to SDIO_TransferDir value */ - /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ - tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir - | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - - /* Write to SDIO DCTRL */ - SDIO->DCTRL = tmpreg; -} - -/** - * @brief Fills each SDIO_DataInitStruct member with its default value. - * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - /* SDIO_DataInitStruct members default value */ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param None - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(void) -{ - return SDIO->DCOUNT; -} - -/** - * @brief Read one data word from Rx FIFO. - * @param None - * @retval Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/** - * @brief Write one data word to Tx FIFO. - * @param Data: 32-bit data word to write. - * @retval None - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/** - * @brief Returns the number of words left to be written to or read from FIFO. - * @param None - * @retval Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/** - * @brief Starts the SD I/O Read Wait operation. - * @param NewState: new state of the Start SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StartSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; -} - -/** - * @brief Stops the SD I/O Read Wait operation. - * @param NewState: new state of the Stop SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StopSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; -} - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parameter can be: - * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 - * @retval None - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; -} - -/** - * @brief Enables or disables the SD I/O Mode Operation. - * @param NewState: new state of SDIO specific operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SetSDIOOperation(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the SD I/O Mode suspend command sending. - * @param NewState: new state of the SD I/O Mode suspend command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the command completion signal. - * @param NewState: new state of command completion signal. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CommandCompletionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the CE-ATA interrupt. - * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CEATAITCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); -} - -/** - * @brief Sends CE-ATA command (CMD61). - * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendCEATACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; -} - -/** - * @brief Checks whether the specified SDIO flag is set or not. - * @param SDIO_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide - * bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_FLAG(SDIO_FLAG)); - - if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's pending flags. - * @param SDIO_FLAG: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide - * bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearFlag(uint32_t SDIO_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); - - SDIO->ICR = SDIO_FLAG; -} - -/** - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param SDIO_IT: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_IT (SET or RESET). - */ -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_GET_IT(SDIO_IT)); - if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's interrupt pending bits. - * @param SDIO_IT: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearITPendingBit(uint32_t SDIO_IT) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); - - SDIO->ICR = SDIO_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c deleted file mode 100644 index 81c8484e..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/Prog/lib/stdperiphlib/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c +++ /dev/null @@ -1,2890 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_tim.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the TIM firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_tim.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/** @defgroup TIM_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Defines - * @{ - */ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_Mask ((uint16_t)0x00FF) -#define CCMR_Offset ((uint16_t)0x0018) -#define CCER_CCE_Set ((uint16_t)0x0001) -#define CCER_CCNE_Set ((uint16_t)0x0004) - -/** - * @} - */ - -/** @defgroup TIM_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_FunctionPrototypes - * @{ - */ - -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -/** - * @} - */ - -/** @defgroup TIM_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @retval None - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if (TIMx == TIM5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - else if (TIMx == TIM8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); - } - else if (TIMx == TIM9) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); - } - else if (TIMx == TIM10) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); - } - else if (TIMx == TIM11) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); - } - else if (TIMx == TIM12) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); - } - else if (TIMx == TIM13) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); - } - else if (TIMx == TIM14) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); - } - else if (TIMx == TIM15) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); - } - else if (TIMx == TIM16) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); - } - else - { - if (TIMx == TIM17) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); - } - } -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef - * structure that contains the configuration information for the - * specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| - (TIMx == TIM4) || (TIMx == TIM5)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if((TIMx != TIM6) && (TIMx != TIM7)) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler and the Repetition counter - values immediately */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| - (TIMx == TIM16)|| (TIMx == TIM17)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); - - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); - - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Output Compare IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - } - else - { - assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity)); - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* TI3 Configuration */ - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* TI4 Configuration */ - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Configures the: Break feature, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable). - * @param TIMx: where x can be 1 or 8 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); - } -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= TIM_BDTR_MOE; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); - } -} - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can only generate an update interrupt. - * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, - * TIM_IT_CC2 or TIM_IT_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * @note - * - TIM6 and TIM7 can only generate an update event. - * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Configures the TIMx's DMA interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select - * the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, - * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, - * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, - * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, - * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, - * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, - * TIM_DMABase_DCR. - * @param TIM_DMABurstLength: DMA Burst length. - * This parameter can be one value between: - * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMx's DMA Requests. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 - * to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST9_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 - * to select the TIM peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ITRSource: Trigger source. - * This parameter can be one of the following values: - * @param TIM_TS_ITR0: Internal Trigger 0 - * @param TIM_TS_ITR1: Internal Trigger 1 - * @param TIM_TS_ITR2: Internal Trigger 2 - * @param TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter : specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - tmpsmcr |= TIM_TS_ETRF; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - tmpsmcr = TIMx->SMCR; - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_Mask; - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - tmpcr1 = TIMx->CR1; - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - tmpsmcr |= TIM_EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); - } -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= TIM_CR2_CCUS; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select - * the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); - } -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 - * to select the TIMx peripheral - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= TIM_CR2_CCPC; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); - } -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC1NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); - tmpccer |= TIM_OCNPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC2NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC3NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_Set << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = CCER_CCNE_Set << TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint16_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. - * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_Offset; - - tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. - * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); - } -} - -/** - * @brief Enables or disables the TIMx's Hall sensor interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); - } -} - -/** - * @brief Selects the TIMx's One Pulse Mode. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This paramter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs (TRGO). - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST7_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes - * the counter and triggers an update of the registers. - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO). - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select - * the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @retval Capture Compare 2 Register value. - */ -uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @retval Counter Register value. - */ -uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * @note - * - TIM6 and TIM7 can have only one update flag. - * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, - * TIM_FLAG_CC2 or TIM_FLAG_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. - * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * @note - * - TIM6 and TIM7 can have only one update flag. - * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, - * TIM_FLAG_CC2 or TIM_FLAG_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. - * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can generate only an update interrupt. - * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, - * TIM_IT_CC2 or TIM_IT_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can generate only an update interrupt. - * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, - * TIM_IT_CC2 or TIM_IT_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - } - else - { - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - } - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - } - else - { - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E); - } - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - } - else - { - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E); - } - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - } - else - { - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E); - } - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/demo.dox b/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/demo.dox deleted file mode 100644 index f7ba606e..00000000 --- a/Target/Demo/ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC/demo.dox +++ /dev/null @@ -1,8 +0,0 @@ -/** -\defgroup ARMCM3_STM32_Nucleo_STM32F103RB_GNU_ARM_GCC Demo for Nucleo-F103RB -\brief Preconfigured programs for the Nucleo-F103RB and the GNU ARM GCC compiler. -\details Refer to http://feaser.com/openblt/doku.php?id=manual:demos - for detailed getting started instructions. -*/ - -