From 6b48314b853341f5e6b6683bc4bdb6d49ceef86e Mon Sep 17 00:00:00 2001 From: Frank Voorburg Date: Thu, 17 Aug 2017 09:48:18 +0000 Subject: [PATCH] Refs #363. Updated GCC Makefiles in the STM32F1 demo programs. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@348 5dc33758-31d5-4daf-9ae8-b24bf3d40d73 --- .../Boot/bin/openblt_nucleo_stm32f103rb.elf | Bin 342878 -> 465664 bytes .../Boot/bin/openblt_nucleo_stm32f103rb.map | 566 +- .../Boot/bin/openblt_nucleo_stm32f103rb.srec | 575 +- .../Boot/cmd/build.bat | 2 - .../Boot/cmd/clean.bat | 2 - .../Boot/cmd/debug.bat | 2 - .../Boot/cmd/debug.cfg | 11 - .../Boot/cmd/flash.bat | 2 - .../Boot/cmd/flash.cfg | 13 - .../Boot/ide/DemoBoot.project | 318 - .../Boot/ide/DemoBoot.workspace | 12 - .../Boot/ide/readme.txt | 4 - .../Boot/lib/newlib/_exit.c | 38 + .../Boot/makefile | 6 +- .../Prog/bin/demoprog_nucleo_stm32f103rb.elf | Bin 455213 -> 504116 bytes .../Prog/bin/demoprog_nucleo_stm32f103rb.map | 438 +- .../Prog/bin/demoprog_nucleo_stm32f103rb.srec | 293 +- .../Prog/cmd/build.bat | 2 - .../Prog/cmd/clean.bat | 2 - .../Prog/ide/DemoProg.project | 168 - .../Prog/ide/DemoProg.workspace | 12 - .../Prog/ide/readme.txt | 4 - .../Prog/lib/newlib/_exit.c | 38 + .../Prog/makefile | 6 +- .../Boot/bin/openblt_olimex_stm32h103.elf | Bin 427294 -> 508456 bytes .../Boot/bin/openblt_olimex_stm32h103.map | 806 +- .../Boot/bin/openblt_olimex_stm32h103.srec | 1332 +- .../Boot/cmd/build.bat | 2 - .../Boot/cmd/clean.bat | 2 - .../Boot/cmd/debug.bat | 1 - .../Boot/cmd/debug.cfg | 15 - .../Boot/cmd/flash.bat | 1 - .../Boot/cmd/flash.cfg | 21 - .../Boot/ide/DemoBoot.project | 181 - .../Boot/ide/DemoBoot.workspace | 12 - .../Boot/ide/readme.txt | 4 - .../Boot/lib/newlib/_exit.c | 38 + .../Boot/makefile | 6 +- .../Prog/bin/demoprog_olimex_stm32h103.elf | Bin 437724 -> 486664 bytes .../Prog/bin/demoprog_olimex_stm32h103.map | 398 +- .../Prog/bin/demoprog_olimex_stm32h103.srec | 181 +- .../Prog/cmd/build.bat | 2 - .../Prog/cmd/clean.bat | 2 - .../Prog/ide/DemoProg.project | 165 - .../Prog/ide/DemoProg.workspace | 12 - .../Prog/ide/readme.txt | 4 - .../Prog/lib/newlib/_exit.c | 38 + .../Prog/makefile | 6 +- .../Boot/bin/openblt_olimex_stm32p103.elf | Bin 523184 -> 597084 bytes .../Boot/bin/openblt_olimex_stm32p103.map | 842 +- .../Boot/bin/openblt_olimex_stm32p103.srec | 2568 +- .../Boot/cmd/build.bat | 2 - .../Boot/cmd/clean.bat | 2 - .../Boot/cmd/debug.bat | 1 - .../Boot/cmd/debug.cfg | 15 - .../Boot/cmd/flash.bat | 1 - .../Boot/cmd/flash.cfg | 21 - .../Boot/ide/DemoBoot.project | 288 - .../Boot/ide/DemoBoot.workspace | 12 - .../Boot/ide/readme.txt | 4 - .../Boot/lib/newlib/_exit.c | 38 + .../Boot/makefile | 6 +- .../Prog/bin/demoprog_olimex_stm32p103.elf | Bin 471701 -> 521004 bytes .../Prog/bin/demoprog_olimex_stm32p103.map | 464 +- .../Prog/bin/demoprog_olimex_stm32p103.srec | 473 +- .../Prog/cmd/build.bat | 2 - .../Prog/cmd/clean.bat | 2 - .../Prog/ide/DemoProg.project | 168 - .../Prog/ide/DemoProg.workspace | 12 - .../Prog/ide/readme.txt | 4 - .../Prog/lib/newlib/_exit.c | 38 + .../Prog/makefile | 6 +- .../Boot/bin/openblt_olimexino_stm32.elf | Bin 785124 -> 788508 bytes .../Boot/bin/openblt_olimexino_stm32.map | 6991 +---- .../Boot/bin/openblt_olimexino_stm32.srec | 3015 +- .../Boot/cfg/STM32F103xx.svd | 24923 ---------------- .../Boot/ide/olimexino.depend | 474 - .../Boot/ide/olimexino.ebp | 515 - .../Boot/ide/olimexino.elay | 64 - .../Boot/lib/newlib/_exit.c | 38 + .../Boot/makefile | 178 + .../Boot/{cfg => }/stm32f103rb_flash.ld | 0 .../Prog/bin/demoprog_olimexino_stm32.elf | Bin 484388 -> 501216 bytes .../Prog/bin/demoprog_olimexino_stm32.map | 3975 +-- .../Prog/bin/demoprog_olimexino_stm32.srec | 157 +- .../Prog/cfg/STM32F103xx.svd | 24923 ---------------- .../Prog/ide/olimexino.depend | 564 - .../Prog/ide/olimexino.ebp | 291 - .../Prog/ide/olimexino.elay | 34 - .../Prog/lib/newlib/_exit.c | 38 + .../Prog/makefile | 164 + .../Prog/{cfg => }/stm32f103rb_flash.ld | 0 92 files changed, 7489 insertions(+), 69567 deletions(-) delete mode 100644 Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/cmd/build.bat delete mode 100644 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Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/ide/olimexino.depend delete mode 100644 Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/ide/olimexino.ebp delete mode 100644 Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/ide/olimexino.elay create mode 100644 Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/lib/newlib/_exit.c create mode 100644 Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/makefile rename Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/{cfg => }/stm32f103rb_flash.ld (100%) diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/bin/openblt_nucleo_stm32f103rb.elf b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/bin/openblt_nucleo_stm32f103rb.elf index 94f1c004d9654b7ab7fcfde3cda9b967e6f34729..7889f79c305e0685679ca3b61fb5570187e229de 100644 GIT binary patch delta 107140 zcmbrn2Vhi1yFPyAoIRV(wrsW$AmApU1c8uH6cGr75K2N73q`5Hpa_vBBD$gXW`H1q zB2Bu0geF~3=|PYV2I+_pYC_%L^PJtq@_Ebu{`1|LciuYnoq1=@;yrucnYA`@vd6o= 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zzU`niW^%cyD{#ol6RMasKP*eq{R8Cv>HgvJ?R0;ZDA(ufzfbpHBd=@a?=Vccj8{Fk zTmJTYP.elf to start the debug session -### - -init -reset init -halt - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/cmd/flash.bat b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/cmd/flash.bat deleted file mode 100644 index 4f1858d6..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/cmd/flash.bat +++ /dev/null @@ -1,2 +0,0 @@ -call env.bat -openocd.exe -f interface/stlink-v2-1.cfg -f target/stm32f1x_stlink.cfg -f flash.cfg \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/cmd/flash.cfg b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/cmd/flash.cfg deleted file mode 100644 index 1217715f..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/cmd/flash.cfg +++ /dev/null @@ -1,13 +0,0 @@ -### -# Description: mass erases and flashes the binary with OpenOCD -### - -init -reset init -halt -stm32f1x mass_erase 0 -flash write_image ..\\bin\\openblt_demoprog_nucleo_stm32f103rb.elf -#flash write_image erase ..\\bin\\openblt_demoprog_nucleo_stm32f103rb.elf -shutdown - - diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/ide/DemoBoot.project b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/ide/DemoBoot.project deleted file mode 100644 index cec59fdf..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/ide/DemoBoot.project +++ /dev/null @@ -1,318 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - break main -continue - - - - - - - mingw32-make clean - mingw32-make - - - - None - $(WorkspacePath)/.. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - make clean - make - - - - None - $(WorkspacePath) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/ide/DemoBoot.workspace b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/ide/DemoBoot.workspace deleted file mode 100644 index 7957a1d7..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/ide/DemoBoot.workspace +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/ide/readme.txt b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/ide/readme.txt deleted file mode 100644 index 8a340a19..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/ide/readme.txt +++ /dev/null @@ -1,4 +0,0 @@ -Integrated Development Environment ----------------------------------- -Codelite was used as the editor during the development of this software program. This directory contains the Codelite -workspace and project files. Codelite is a cross platform open source C/C++ IDE, available at http://www.codelite.org/. \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/lib/newlib/_exit.c b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/lib/newlib/_exit.c new file mode 100644 index 00000000..4ae9532c --- /dev/null +++ b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/lib/newlib/_exit.c @@ -0,0 +1,38 @@ +// ---------------------------------------------------------------------------- + +#include + +// ---------------------------------------------------------------------------- + +// Forward declaration + +void +_exit(int code); + +// ---------------------------------------------------------------------------- + +// We just enter an infinite loop, to be used as landmark when halting +// the debugger. +// +// It can be redefined in the application, if more functionality +// is required. + +void +__attribute__((weak)) +_exit(int code __attribute__((unused))) +{ + // TODO: write on trace + while (1) + ; +} + +// ---------------------------------------------------------------------------- + +void +__attribute__((weak,noreturn)) +abort(void) +{ + _exit(1); +} + +// ---------------------------------------------------------------------------- diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/makefile b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/makefile index 09c85de3..6c73816b 100644 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/makefile +++ b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Boot/makefile @@ -34,7 +34,7 @@ PROJ_NAME=openblt_nucleo_stm32f103rb #|--------------------------------------------------------------------------------------| #| Configure tool path | #|--------------------------------------------------------------------------------------| -TOOL_PATH= +TOOL_PATH=/opt/gcc-arm-none-eabi-5_4-2016q3/bin/ #|--------------------------------------------------------------------------------------| @@ -64,7 +64,7 @@ PROJ_FILES += $(wildcard ../../../Source/ARMCM3_STM32F1/GCC/*.h) #|--------------------------------------------------------------------------------------| #| Toolchain binaries | #|--------------------------------------------------------------------------------------| -RM = cs-rm +RM = rm CC = $(TOOL_PATH)arm-none-eabi-gcc LN = $(TOOL_PATH)arm-none-eabi-gcc OC = $(TOOL_PATH)arm-none-eabi-objcopy @@ -107,7 +107,7 @@ AFLAGS = $(CFLAGS) LFLAGS = $(STDFLAGS) $(OPTFLAGS) LFLAGS += -Wl,--defsym=__HEAP_SIZE=$(HEAP_SIZE) -Wl,--defsym=__STACK_SIZE=$(STACK_SIZE) LFLAGS += -Wl,-script="stm32f103rb_flash.ld" -Wl,-Map=$(BIN_PATH)/$(PROJ_NAME).map -LFLAGS += -Wl,--gc-sections $(LIB_PATH) +LFLAGS += -specs=nano.specs -Wl,--gc-sections $(LIB_PATH) OFLAGS = -O srec ODFLAGS = -x SZFLAGS = -B -d diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.elf b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.elf index 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b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.map index 2e440dfc..0e2275af 100644 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.map +++ b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.map @@ -1,206 +1,232 @@ - -bin/demoprog_nucleo_stm32f103rb.elf: file format elf32-littlearm -bin/demoprog_nucleo_stm32f103rb.elf -architecture: arm, flags 0x00000112: -EXEC_P, HAS_SYMS, D_PAGED -start address 0x08002000 - -Program Header: - LOAD off 0x00000000 vaddr 0x08000000 paddr 0x08000000 align 2**15 - filesz 0x0000295c memsz 0x0000295c flags r-x - LOAD off 0x00008000 vaddr 0x20000000 paddr 0x0800295c align 2**15 - filesz 0x0000001c memsz 0x00000090 flags rw- -private flags = 5000202: [Version5 EABI] [soft-float ABI] [has entry point] - -Sections: -Idx Name Size VMA LMA File off Algn - 0 .text 0000095c 08002000 08002000 00002000 2**2 - CONTENTS, ALLOC, LOAD, READONLY, CODE - 1 .data 0000001c 20000000 0800295c 00008000 2**2 - CONTENTS, ALLOC, LOAD, DATA - 2 .bss 00000074 2000001c 08002978 0000801c 2**2 - ALLOC - 3 .heap 00000800 20000090 20000090 00008020 2**3 - CONTENTS, READONLY - 4 .stack_dummy 00000800 20000090 20000090 00008820 2**3 - CONTENTS, READONLY - 5 .ARM.attributes 00000027 00000000 00000000 00009020 2**0 - CONTENTS, READONLY - 6 .comment 00000030 00000000 00000000 00009047 2**0 - CONTENTS, READONLY - 7 .debug_line 00002bc9 00000000 00000000 00009077 2**0 - CONTENTS, READONLY, DEBUGGING - 8 .debug_info 00002f85 00000000 00000000 0000bc40 2**0 - CONTENTS, READONLY, DEBUGGING - 9 .debug_abbrev 00000c5e 00000000 00000000 0000ebc5 2**0 - CONTENTS, READONLY, DEBUGGING - 10 .debug_aranges 000003b8 00000000 00000000 0000f828 2**3 - CONTENTS, READONLY, DEBUGGING - 11 .debug_loc 000011cb 00000000 00000000 0000fbe0 2**0 - CONTENTS, READONLY, DEBUGGING - 12 .debug_ranges 00000328 00000000 00000000 00010dab 2**0 - CONTENTS, READONLY, DEBUGGING - 13 .debug_macro 0000d653 00000000 00000000 000110d3 2**0 - CONTENTS, READONLY, DEBUGGING - 14 .debug_str 0004e8a4 00000000 00000000 0001e726 2**0 - CONTENTS, READONLY, DEBUGGING - 15 .debug_frame 0000071c 00000000 00000000 0006cfcc 2**2 - CONTENTS, READONLY, DEBUGGING -SYMBOL TABLE: -08002000 l d .text 00000000 .text -20000000 l d .data 00000000 .data -2000001c l d .bss 00000000 .bss -20000090 l d .heap 00000000 .heap -20000090 l d .stack_dummy 00000000 .stack_dummy -00000000 l d .ARM.attributes 00000000 .ARM.attributes -00000000 l d .comment 00000000 .comment -00000000 l d .debug_line 00000000 .debug_line -00000000 l d .debug_info 00000000 .debug_info -00000000 l d .debug_abbrev 00000000 .debug_abbrev -00000000 l d .debug_aranges 00000000 .debug_aranges -00000000 l d .debug_loc 00000000 .debug_loc -00000000 l d .debug_ranges 00000000 .debug_ranges -00000000 l d .debug_macro 00000000 .debug_macro -00000000 l d .debug_str 00000000 .debug_str -00000000 l d .debug_frame 00000000 .debug_frame -00000000 l df *ABS* 00000000 obj/startup_stm32f10x_md.o -00000800 l *ABS* 00000000 Stack_Size -00000800 l *ABS* 00000000 Heap_Size -080021c2 l .text 00000000 .flash_to_ram_loop -080021f4 l .text 00000000 .fill_zero_bss -080021f0 l .text 00000000 .loop_zero_bss -00000000 l df *ABS* 00000000 crtstuff.c -08002958 l O .text 00000000 __EH_FRAME_BEGIN__ -080020f0 l F .text 00000000 deregister_tm_clones -08002118 l F .text 00000000 register_tm_clones -08002148 l F .text 00000000 __do_global_dtors_aux -2000001c l .bss 00000000 completed.7922 -20000018 l O .data 00000000 __do_global_dtors_aux_fini_array_entry -08002178 l F .text 00000000 frame_dummy -20000020 l .bss 00000000 object.7927 -20000014 l O .data 00000000 __frame_dummy_init_array_entry -00000000 l df *ABS* 00000000 boot.c -08002270 l F .text 00000086 BootComUartInit -080022f8 l F .text 0000002c UartReceiveByte -0800234c l F .text 000000d8 BootComUartCheckActivationRequest -20000038 l O .bss 00000041 xcpCtoReqPacket.6441 -2000007c l O .bss 00000001 xcpCtoRxLength.6442 -2000007d l O .bss 00000001 xcpCtoRxInProgress.6443 -20000080 l O .bss 00000004 xcpCtoRxStartTime.6444 -00000000 l df *ABS* 00000000 led.c -20000084 l O .bss 00000004 timer_counter_last.6426 -20000088 l O .bss 00000001 led_toggle_state.6425 -00000000 l df *ABS* 00000000 stm32f10x_gpio.c -00000000 l df *ABS* 00000000 stm32f10x_rcc.c -20000000 l O .data 00000004 ADCPrescTable -20000004 l O .data 00000010 APBAHBPrescTable -00000000 l df *ABS* 00000000 stm32f10x_usart.c -00000000 l df *ABS* 00000000 main.c -080027b0 l F .text 00000122 Init -00000000 l df *ABS* 00000000 timer.c -2000008c l O .bss 00000004 millisecond_counter -00000000 l df *ABS* 00000000 c:/users/frank voorburg/mentorgraphics/sourcery_codebench_lite_for_arm_eabi/bin/../lib/gcc/arm-none-eabi/4.8.1/thumb2/crti.o -00000000 l df *ABS* 00000000 c:/users/frank voorburg/mentorgraphics/sourcery_codebench_lite_for_arm_eabi/bin/../lib/gcc/arm-none-eabi/4.8.1/thumb2/crtn.o -00000000 l df *ABS* 00000000 crtstuff.c -08002958 l O .text 00000000 __FRAME_END__ -00000000 l df *ABS* 00000000 -00000800 l *ABS* 00000000 __HEAP_SIZE -0800295c l .text 00000000 __exidx_end -0800295c l .text 00000000 __exidx_start -00000800 l *ABS* 00000000 __STACK_SIZE -08002222 w F .text 00000002 EXTI2_IRQHandler -20000090 g .heap 00000800 __HeapBase -0800220a w F .text 00000002 DebugMon_Handler -20000000 g .data 00000000 __data_start__ -08002248 w F .text 00000002 TIM1_CC_IRQHandler -08002200 w F .text 00000002 HardFault_Handler -08002930 g F .text 00000010 SysTick_Handler -08002214 w F .text 00000002 PVD_IRQHandler -0800220c w F .text 00000002 PendSV_Handler -080021fe w F .text 00000002 NMI_Handler -08002224 w F .text 00000002 EXTI3_IRQHandler -0800295c g .text 00000000 __etext -080027a4 g F .text 0000000c USART_GetFlagStatus -2000001c g O .data 00000000 .hidden __TMC_END__ -0800221e w F .text 00000002 EXTI0_IRQHandler -08002254 w F .text 00000002 I2C2_EV_IRQHandler -0800279c g F .text 00000008 USART_ReceiveData -08002206 w F .text 00000002 UsageFault_Handler -08002668 g F .text 00000024 RCC_APB2PeriphClockCmd -08002236 w F .text 00000002 ADC1_2_IRQHandler -080024c8 g F .text 000000aa GPIO_Init -20000890 g .heap 00000000 __HeapLimit -2000001c g .bss 00000000 __bss_start__ -08002258 w F .text 00000002 SPI1_IRQHandler -08002780 g F .text 0000001c USART_Cmd -08002216 w F .text 00000002 TAMPER_IRQHandler -0800268c g F .text 00000024 RCC_APB1PeriphClockCmd -0800222e w F .text 00000002 DMA1_Channel4_IRQHandler -08002940 g F .text 00000000 _init -0800232c g F .text 0000001e BootActivate -08002260 w F .text 00000002 USART3_IRQHandler -08002218 w F .text 00000002 RTC_IRQHandler -08002234 w F .text 00000002 DMA1_Channel7_IRQHandler -080021b8 g F .text 00000030 Reset_Handler -0800223c w F .text 00000002 CAN1_RX1_IRQHandler -0800242c g F .text 00000032 LedInit -08002574 g F .text 00000004 GPIO_SetBits -0800224e w F .text 00000002 TIM4_IRQHandler -00000000 w *UND* 00000000 __deregister_frame_info -20000090 g .heap 00000000 end -08002250 w F .text 00000002 I2C1_EV_IRQHandler -2000001c g .data 00000000 __data_end__ -00000000 w *UND* 00000000 _ITM_registerTMCloneTable -0800257c g F .text 000000ea RCC_GetClocksFreq -08002232 w F .text 00000002 DMA1_Channel6_IRQHandler -080026b0 g F .text 000000d0 USART_Init -20000090 g .bss 00000000 __bss_end__ -0800224c w F .text 00000002 TIM3_IRQHandler -0800221c w F .text 00000002 RCC_IRQHandler -08002246 w F .text 00000002 TIM1_TRG_COM_IRQHandler -08002228 w F .text 00000002 DMA1_Channel1_IRQHandler -08002210 w F .text 00000002 Default_Handler -080021e8 w F .text 00000016 _start -08002262 w F .text 00000002 EXTI15_10_IRQHandler -08002578 g F .text 00000004 GPIO_ResetBits -08002240 w F .text 00000002 EXTI9_5_IRQHandler -00000000 w *UND* 00000000 _ITM_deregisterTMCloneTable -0800225a w F .text 00000002 SPI2_IRQHandler -08002202 w F .text 00000002 MemManage_Handler -08002000 g .text 000000f0 __isr_vector -080028d4 g F .text 00000014 main -08002208 w F .text 00000002 SVC_Handler -20000090 g .heap 00000000 __end__ -08002230 w F .text 00000002 DMA1_Channel5_IRQHandler -08002226 w F .text 00000002 EXTI4_IRQHandler -080028e8 g F .text 0000000c TimerSet -0800223a w F .text 00000002 USB_LP_CAN1_RX0_IRQHandler -08002324 g F .text 00000008 BootComInit -0800294c g F .text 00000000 _fini -08002238 w F .text 00000002 USB_HP_CAN1_TX_IRQHandler -0800222c w F .text 00000002 DMA1_Channel3_IRQHandler -20005000 g *ABS* 00000000 __StackTop -08002244 w F .text 00000002 TIM1_UP_IRQHandler -08002212 w F .text 00000002 WWDG_IRQHandler -08002460 g F .text 00000068 LedToggle -0800224a w F .text 00000002 TIM2_IRQHandler -08002242 w F .text 00000002 TIM1_BRK_IRQHandler -08002220 w F .text 00000002 EXTI1_IRQHandler -08002264 w F .text 00000002 RTCAlarm_IRQHandler -20004800 g *ABS* 00000800 __StackLimit -0800225e w F .text 00000002 USART2_IRQHandler -08002256 w F .text 00000002 I2C2_ER_IRQHandler -0800222a w F .text 00000002 DMA1_Channel2_IRQHandler -08002424 g F .text 00000008 BootComCheckActivationRequest -0800223e w F .text 00000002 CAN1_SCE_IRQHandler -0800221a w F .text 00000002 FLASH_IRQHandler -08002204 w F .text 00000002 BusFault_Handler -0800225c w F .text 00000002 USART1_IRQHandler -08002252 w F .text 00000002 I2C1_ER_IRQHandler -08002924 g F .text 0000000c TimerGet -00000000 w *UND* 00000000 _Jv_RegisterClasses -080028f4 g F .text 00000030 TimerInit -00000000 w *UND* 00000000 __register_frame_info -08002266 w F .text 00000002 USBWakeUp_IRQHandler - - + +bin/demoprog_nucleo_stm32f103rb.elf: file format elf32-littlearm +bin/demoprog_nucleo_stm32f103rb.elf +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x08002000 + +Program Header: +0x70000001 off 0x00002900 vaddr 0x08002900 paddr 0x08002900 align 2**2 + filesz 0x00000008 memsz 0x00000008 flags r-- + LOAD off 0x00000000 vaddr 0x08000000 paddr 0x08000000 align 2**16 + filesz 0x00002908 memsz 0x00002908 flags r-x + LOAD off 0x00010000 vaddr 0x20000000 paddr 0x08002908 align 2**16 + filesz 0x0000007c memsz 0x000000ec flags rw- +private flags = 5000200: [Version5 EABI] [soft-float ABI] + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00000900 08002000 08002000 00002000 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .ARM.exidx 00000008 08002900 08002900 00002900 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .data 0000007c 20000000 08002908 00010000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 3 .bss 00000070 2000007c 08002984 0001007c 2**2 + ALLOC + 4 .heap 00000800 200000f0 200000f0 00010080 2**3 + CONTENTS, READONLY + 5 .stack_dummy 00000800 200000f0 200000f0 00010880 2**3 + CONTENTS, READONLY + 6 .ARM.attributes 00000029 00000000 00000000 00011080 2**0 + CONTENTS, READONLY + 7 .comment 0000006e 00000000 00000000 000110a9 2**0 + CONTENTS, READONLY + 8 .debug_line 000029d7 00000000 00000000 00011117 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_info 000030d5 00000000 00000000 00013aee 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 00000cd1 00000000 00000000 00016bc3 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_aranges 000003e0 00000000 00000000 00017898 2**3 + CONTENTS, READONLY, DEBUGGING + 12 .debug_loc 000013ab 00000000 00000000 00017c78 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_ranges 00000340 00000000 00000000 00019023 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_macro 0000e187 00000000 00000000 00019363 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_str 000514c6 00000000 00000000 000274ea 2**0 + CONTENTS, READONLY, DEBUGGING + 16 .debug_frame 000007f0 00000000 00000000 000789b0 2**2 + CONTENTS, READONLY, DEBUGGING +SYMBOL TABLE: +08002000 l d .text 00000000 .text +08002900 l d .ARM.exidx 00000000 .ARM.exidx +20000000 l d .data 00000000 .data +2000007c l d .bss 00000000 .bss +200000f0 l d .heap 00000000 .heap +200000f0 l d .stack_dummy 00000000 .stack_dummy +00000000 l d .ARM.attributes 00000000 .ARM.attributes +00000000 l d .comment 00000000 .comment +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l d .debug_ranges 00000000 .debug_ranges +00000000 l d .debug_macro 00000000 .debug_macro +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l df *ABS* 00000000 obj/startup_stm32f10x_md.o +00000800 l *ABS* 00000000 Stack_Size +00000800 l *ABS* 00000000 Heap_Size +080021ca l .text 00000000 .flash_to_ram_loop +080021fc l .text 00000000 .fill_zero_bss +080021f8 l .text 00000000 .loop_zero_bss +00000000 l df *ABS* 00000000 crtstuff.c +080028fc l O .text 00000000 __EH_FRAME_BEGIN__ +080020f0 l F .text 00000000 __do_global_dtors_aux +2000007c l .bss 00000000 completed.8603 +20000078 l O .data 00000000 __do_global_dtors_aux_fini_array_entry +08002114 l F .text 00000000 frame_dummy +20000080 l .bss 00000000 object.8608 +20000074 l O .data 00000000 __frame_dummy_init_array_entry +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m/crt0.o +00000000 l df *ABS* 00000000 boot.c +08002278 l F .text 00000080 BootComUartInit +080022f8 l F .text 00000024 UartReceiveByte +08002340 l F .text 00000094 BootComUartCheckActivationRequest +20000098 l O .bss 00000004 xcpCtoRxStartTime.6570 +2000009c l O .bss 00000041 xcpCtoReqPacket.6567 +200000dd l O .bss 00000001 xcpCtoRxLength.6568 +200000de l O .bss 00000001 xcpCtoRxInProgress.6569 +00000000 l df *ABS* 00000000 main.c +080023dc l F .text 00000104 Init +00000000 l df *ABS* 00000000 led.c +200000e0 l O .bss 00000004 timer_counter_last.6552 +200000e4 l O .bss 00000001 led_toggle_state.6551 +00000000 l df *ABS* 00000000 timer.c +200000e8 l O .bss 00000004 millisecond_counter +00000000 l df *ABS* 00000000 stm32f10x_rcc.c +20000000 l O .data 00000004 ADCPrescTable +20000004 l O .data 00000010 APBAHBPrescTable +00000000 l df *ABS* 00000000 stm32f10x_usart.c +00000000 l df *ABS* 00000000 stm32f10x_gpio.c +00000000 l df *ABS* 00000000 _exit.c +00000000 l df *ABS* 00000000 exit.c +00000000 l df *ABS* 00000000 init.c +00000000 l df *ABS* 00000000 memset.c +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crti.o +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o +00000000 l df *ABS* 00000000 impure.c +20000014 l O .data 00000060 impure_data +00000000 l df *ABS* 00000000 crtstuff.c +080028fc l O .text 00000000 __FRAME_END__ +00000000 l df *ABS* 00000000 +20000078 l .data 00000000 __init_array_end +20000074 l .data 00000000 __preinit_array_end +20000074 l .data 00000000 __init_array_start +20000074 l .data 00000000 __preinit_array_start +0800222a w F .text 00000002 EXTI2_IRQHandler +200000f0 g .heap 00000800 __HeapBase +08002212 w F .text 00000002 DebugMon_Handler +00000800 g *ABS* 00000000 __HEAP_SIZE +20000000 g .data 00000000 __data_start__ +08002250 w F .text 00000002 TIM1_CC_IRQHandler +08002208 w F .text 00000002 HardFault_Handler +080025b4 g F .text 00000010 SysTick_Handler +0800221c w F .text 00000002 PVD_IRQHandler +08002214 w F .text 00000002 PendSV_Handler +08002206 w F .text 00000002 NMI_Handler +08002908 g .ARM.exidx 00000000 __exidx_end +0800222c w F .text 00000002 EXTI3_IRQHandler +08002908 g .ARM.exidx 00000000 __etext +080027a4 g F .text 0000000e USART_GetFlagStatus +08002226 w F .text 00000002 EXTI0_IRQHandler +0800225c w F .text 00000002 I2C2_EV_IRQHandler +0800279c g F .text 00000008 USART_ReceiveData +0800220e w F .text 00000002 UsageFault_Handler +08002680 g F .text 0000001c RCC_APB2PeriphClockCmd +0800223e w F .text 00000002 ADC1_2_IRQHandler +080027b4 g F .text 0000009a GPIO_Init +200008f0 g .heap 00000000 __HeapLimit +2000007c g .bss 00000000 __bss_start__ +08002260 w F .text 00000002 SPI1_IRQHandler +08002780 g F .text 0000001c USART_Cmd +0800221e w F .text 00000002 TAMPER_IRQHandler +0800269c g F .text 0000001c RCC_APB1PeriphClockCmd +08002900 g .text 00000000 __exidx_start +080028f8 g O .text 00000004 _global_impure_ptr +08002884 g F .text 0000004c __libc_init_array +08002236 w F .text 00000002 DMA1_Channel4_IRQHandler +0800214c g F .text 00000000 _mainCRTStartup +080028e0 g F .text 00000000 _init +08002324 g F .text 0000001c BootActivate +08002268 w F .text 00000002 USART3_IRQHandler +00000000 w *UND* 00000000 __libc_fini_array +08002220 w F .text 00000002 RTC_IRQHandler +0800223c w F .text 00000002 DMA1_Channel7_IRQHandler +080021c0 g F .text 00000030 Reset_Handler +08002244 w F .text 00000002 CAN1_RX1_IRQHandler +080024f4 g F .text 00000030 LedInit +08002850 g F .text 00000004 GPIO_SetBits +08002256 w F .text 00000002 TIM4_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stderr +00000000 w *UND* 00000000 __deregister_frame_info +200000f0 g .heap 00000000 end +08002258 w F .text 00000002 I2C1_EV_IRQHandler +2000007c g .data 00000000 __data_end__ +080025c4 g F .text 000000bc RCC_GetClocksFreq +0800223a w F .text 00000002 DMA1_Channel6_IRQHandler +080026b8 g F .text 000000c8 USART_Init +200000ec g .bss 00000000 __bss_end__ +00000800 g *ABS* 00000000 __STACK_SIZE +08002254 w F .text 00000002 TIM3_IRQHandler +08002224 w F .text 00000002 RCC_IRQHandler +0800224e w F .text 00000002 TIM1_TRG_COM_IRQHandler +00000000 w *UND* 00000000 __call_exitprocs +08002230 w F .text 00000002 DMA1_Channel1_IRQHandler +08002218 w F .text 00000002 Default_Handler +0800214c g F .text 00000000 _start +0800226a w F .text 00000002 EXTI15_10_IRQHandler +00000000 w *UND* 00000000 software_init_hook +08002854 g F .text 00000004 GPIO_ResetBits +08002248 w F .text 00000002 EXTI9_5_IRQHandler +08002262 w F .text 00000002 SPI2_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stdin +080028d0 g F .text 00000010 memset +0800220a w F .text 00000002 MemManage_Handler +08002000 g .text 000000f0 __isr_vector +080024e0 g F .text 00000014 main +08002210 w F .text 00000002 SVC_Handler +00000000 w *UND* 00000000 hardware_init_hook +200000f0 g .heap 00000000 __end__ +08002238 w F .text 00000002 DMA1_Channel5_IRQHandler +0800222e w F .text 00000002 EXTI4_IRQHandler +08002570 g F .text 0000000c TimerSet +08002242 w F .text 00000002 USB_LP_CAN1_RX0_IRQHandler +0800231c g F .text 00000008 BootComInit +080028ec g F .text 00000000 _fini +08002240 w F .text 00000002 USB_HP_CAN1_TX_IRQHandler +00000000 w *UND* 00000000 atexit +08002234 w F .text 00000002 DMA1_Channel3_IRQHandler +20005000 g .bss 00000000 __StackTop +0800224c w F .text 00000002 TIM1_UP_IRQHandler +0800221a w F .text 00000002 WWDG_IRQHandler +08002524 g F .text 0000004c LedToggle +08002252 w F .text 00000002 TIM2_IRQHandler +0800224a w F .text 00000002 TIM1_BRK_IRQHandler +20005000 g *ABS* 00000000 __stack +08002228 w F .text 00000002 EXTI1_IRQHandler +0800226c w F .text 00000002 RTCAlarm_IRQHandler +20004800 g *ABS* 00000800 __StackLimit +08002266 w F .text 00000002 USART2_IRQHandler +0800285c g F .text 00000028 exit +0800225e w F .text 00000002 I2C2_ER_IRQHandler +08002232 w F .text 00000002 DMA1_Channel2_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stdout +080023d4 g F .text 00000008 BootComCheckActivationRequest +08002246 w F .text 00000002 CAN1_SCE_IRQHandler +08002222 w F .text 00000002 FLASH_IRQHandler +08002858 w F .text 00000002 _exit +0800220c w F .text 00000002 BusFault_Handler +08002264 w F .text 00000002 USART1_IRQHandler +0800225a w F .text 00000002 I2C1_ER_IRQHandler +080025a8 g F .text 0000000c TimerGet +00000000 w *UND* 00000000 _Jv_RegisterClasses +0800257c g F .text 0000002c TimerInit +00000000 w *UND* 00000000 __register_frame_info +0800226e w F .text 00000002 USBWakeUp_IRQHandler + + diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.srec b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.srec index c667da5f..cb8049a9 100644 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.srec +++ b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/bin/demoprog_nucleo_stm32f103rb.srec @@ -1,154 +1,155 @@ S027000062696E2F64656D6F70726F675F6E75636C656F5F73746D33326631303372622E737265636D -S3150800200000500020B9210008FF210008012200081D -S315080020100322000805220008072200080000000025 -S31508002020000000000000000000000000092200086F -S315080020300B220008000000000D22000831290008C4 -S315080020401322000815220008172200081922000882 -S315080020501B2200081D2200081F2200082122000852 -S315080020602322000825220008272200082922000822 -S315080020702B2200082D2200082F22000831220008F2 -S3150800208033220008352200083722000839220008C2 -S315080020903B2200083D2200083F2200084122000892 -S315080020A04322000845220008472200084922000862 -S315080020B04B2200084D2200084F2200085122000832 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+S315080029380000000000000000000000000000000081 +S315080029480000000000000000000000000000000071 +S315080029580000000000000000000000000000000061 +S315080029680000000000000000000000000000000051 +S311080029780000000015210008F1200008EE S70508002000D2 diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/cmd/build.bat b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/cmd/build.bat deleted file mode 100644 index 6cdb041e..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/cmd/build.bat +++ /dev/null @@ -1,2 +0,0 @@ -@echo off -cs-make --directory=../ all diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/cmd/clean.bat b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/cmd/clean.bat deleted file mode 100644 index 025aaea0..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/cmd/clean.bat +++ /dev/null @@ -1,2 +0,0 @@ -@echo off -cs-make --directory=../ clean diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/ide/DemoProg.project b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/ide/DemoProg.project deleted file mode 100644 index f90d469b..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/ide/DemoProg.project +++ /dev/null @@ -1,168 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - break main -continue - - - - - - - make clean - make - - - - None - $(WorkspacePath)/.. - - - - - - - - - - - - - - - - - - - - - - - make clean - make - - - - None - $(WorkspacePath) - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/ide/DemoProg.workspace b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/ide/DemoProg.workspace deleted file mode 100644 index 4060139b..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/ide/DemoProg.workspace +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/ide/readme.txt b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/ide/readme.txt deleted file mode 100644 index 8a340a19..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/ide/readme.txt +++ /dev/null @@ -1,4 +0,0 @@ -Integrated Development Environment ----------------------------------- -Codelite was used as the editor during the development of this software program. This directory contains the Codelite -workspace and project files. Codelite is a cross platform open source C/C++ IDE, available at http://www.codelite.org/. \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/lib/newlib/_exit.c b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/lib/newlib/_exit.c new file mode 100644 index 00000000..4ae9532c --- /dev/null +++ b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/lib/newlib/_exit.c @@ -0,0 +1,38 @@ +// ---------------------------------------------------------------------------- + +#include + +// ---------------------------------------------------------------------------- + +// Forward declaration + +void +_exit(int code); + +// ---------------------------------------------------------------------------- + +// We just enter an infinite loop, to be used as landmark when halting +// the debugger. +// +// It can be redefined in the application, if more functionality +// is required. + +void +__attribute__((weak)) +_exit(int code __attribute__((unused))) +{ + // TODO: write on trace + while (1) + ; +} + +// ---------------------------------------------------------------------------- + +void +__attribute__((weak,noreturn)) +abort(void) +{ + _exit(1); +} + +// ---------------------------------------------------------------------------- diff --git a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/makefile b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/makefile index a78731d6..df9240d4 100644 --- a/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/makefile +++ b/Target/Demo/ARMCM3_STM32F1_Nucleo_F103RB_GCC/Prog/makefile @@ -34,7 +34,7 @@ PROJ_NAME=demoprog_nucleo_stm32f103rb #|--------------------------------------------------------------------------------------| #| Configure tool path | #|--------------------------------------------------------------------------------------| -TOOL_PATH= +TOOL_PATH=/opt/gcc-arm-none-eabi-5_4-2016q3/bin/ #|--------------------------------------------------------------------------------------| @@ -54,7 +54,7 @@ PROJ_FILES = $(call rwildcard, , *.c *.h *.S) #|--------------------------------------------------------------------------------------| #| Toolchain binaries | #|--------------------------------------------------------------------------------------| -RM = cs-rm +RM = rm CC = $(TOOL_PATH)arm-none-eabi-gcc LN = $(TOOL_PATH)arm-none-eabi-gcc OC = $(TOOL_PATH)arm-none-eabi-objcopy @@ -97,7 +97,7 @@ AFLAGS = $(CFLAGS) LFLAGS = $(STDFLAGS) $(OPTFLAGS) LFLAGS += -Wl,--defsym=__HEAP_SIZE=$(HEAP_SIZE) -Wl,--defsym=__STACK_SIZE=$(STACK_SIZE) LFLAGS += -Wl,-script="stm32f103rb_flash.ld" -Wl,-Map=$(BIN_PATH)/$(PROJ_NAME).map -LFLAGS += -Wl,--gc-sections $(LIB_PATH) +LFLAGS += -specs=nano.specs -Wl,--gc-sections $(LIB_PATH) OFLAGS = -O srec ODFLAGS = -x SZFLAGS = -B -d diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/bin/openblt_olimex_stm32h103.elf b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/bin/openblt_olimex_stm32h103.elf index e54a5d3087b310ea24ae0046ac003672b2066d7d..f63599d87e5f839bae0de04315f2a650389cc295 100644 GIT binary patch literal 508456 zcmeFa31F1fxjufrWoEvaBxJGxA#9UOg26yCfuJaagb)HGL6%@;(Gr$OqAVdS21+Fb zw20n{Qd`8db*-&i0mVucr7dl3ueVLqd#||M#@1i8#kSFc2_l*Q^PKOS$t1XSyVraF zXY|aR^Pcy8&wHNpp7lHV*gCbUT+=iW`RF1?I4P?T#P+8>Lg>O(C<4MjUVo9y{D#!? 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zvm5&4%z0_d(uCq>S=fmDbd*j`@<@+#0Li>>P|Mo8mo@ibU=2Mjm+Ktp&#m)kV)K42 zQAehqty~f+KsJCXPJ*HU#-bvirk)fZ@kyZBgUJHbG_p zLjknsrIjZJ0%?5(&4hW+EgS60p#psOmfJW@7O6>8x_7`72_~1?E-wGg2Q4=0Wu9hUjiKEna1f6}7$gd~zK26I>$i zExuPU3++yph-f-`2zHpq!oY|Fvsr;y<>W3}hlQb^_7>xYdjQYOw2pnOrj|wEyF%!n rJ~lr9h6yx!`Xy8HdQt5k?8~Dm4P31^Gcs_aQC!-5b^D4wThRXpX%lVv diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/bin/openblt_olimex_stm32h103.map b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/bin/openblt_olimex_stm32h103.map index e215a877..62f0053b 100644 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/bin/openblt_olimex_stm32h103.map +++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/bin/openblt_olimex_stm32h103.map @@ -1,390 +1,416 @@ - -bin/openblt_olimex_stm32h103.elf: file format elf32-littlearm -bin/openblt_olimex_stm32h103.elf -architecture: arm, flags 0x00000112: -EXEC_P, HAS_SYMS, D_PAGED -start address 0x08000000 - -Program Header: - LOAD off 0x00008000 vaddr 0x08000000 paddr 0x08000000 align 2**15 - filesz 0x00002a64 memsz 0x00002a64 flags r-x - LOAD off 0x00010000 vaddr 0x20000000 paddr 0x08002a64 align 2**15 - filesz 0x000000f8 memsz 0x00000778 flags rw- -private flags = 5000202: [Version5 EABI] [soft-float ABI] [has entry point] - -Sections: -Idx Name Size VMA LMA File off Algn - 0 .text 00002a64 08000000 08000000 00008000 2**2 - CONTENTS, ALLOC, LOAD, READONLY, CODE - 1 .data 000000f8 20000000 08002a64 00010000 2**2 - CONTENTS, ALLOC, LOAD, DATA - 2 .bss 00000680 200000f8 08002b5c 000100f8 2**2 - ALLOC - 3 .heap 00000800 20000778 20000778 000100f8 2**3 - CONTENTS, READONLY - 4 .stack_dummy 00000800 20000778 20000778 000108f8 2**3 - CONTENTS, READONLY - 5 .ARM.attributes 00000027 00000000 00000000 000110f8 2**0 - CONTENTS, READONLY - 6 .comment 00000030 00000000 00000000 0001111f 2**0 - CONTENTS, READONLY - 7 .debug_line 00005019 00000000 00000000 0001114f 2**0 - CONTENTS, READONLY, DEBUGGING - 8 .debug_info 000065f0 00000000 00000000 00016168 2**0 - CONTENTS, READONLY, DEBUGGING - 9 .debug_abbrev 00001e8e 00000000 00000000 0001c758 2**0 - CONTENTS, READONLY, DEBUGGING - 10 .debug_aranges 000008c8 00000000 00000000 0001e5e8 2**3 - CONTENTS, READONLY, DEBUGGING - 11 .debug_ranges 00000740 00000000 00000000 0001eeb0 2**0 - CONTENTS, READONLY, DEBUGGING - 12 .debug_macro 0000af2b 00000000 00000000 0001f5f0 2**0 - CONTENTS, READONLY, DEBUGGING - 13 .debug_str 00036622 00000000 00000000 0002a51b 2**0 - CONTENTS, READONLY, DEBUGGING - 14 .debug_frame 00001248 00000000 00000000 00060b40 2**2 - CONTENTS, READONLY, DEBUGGING - 15 .debug_loc 00002b1d 00000000 00000000 00061d88 2**0 - CONTENTS, READONLY, DEBUGGING -SYMBOL TABLE: -08000000 l d .text 00000000 .text -20000000 l d .data 00000000 .data -200000f8 l d .bss 00000000 .bss -20000778 l d .heap 00000000 .heap -20000778 l d .stack_dummy 00000000 .stack_dummy -00000000 l d .ARM.attributes 00000000 .ARM.attributes -00000000 l d .comment 00000000 .comment -00000000 l d .debug_line 00000000 .debug_line -00000000 l d .debug_info 00000000 .debug_info -00000000 l d .debug_abbrev 00000000 .debug_abbrev -00000000 l d .debug_aranges 00000000 .debug_aranges -00000000 l d .debug_ranges 00000000 .debug_ranges -00000000 l d .debug_macro 00000000 .debug_macro -00000000 l d .debug_str 00000000 .debug_str -00000000 l d .debug_frame 00000000 .debug_frame -00000000 l d .debug_loc 00000000 .debug_loc -00000000 l df *ABS* 00000000 obj/startup_stm32f10x_md.o -00000800 l *ABS* 00000000 Stack_Size -00000800 l *ABS* 00000000 Heap_Size -080001be l .text 00000000 .flash_to_ram_loop -080001f0 l .text 00000000 .fill_zero_bss -080001ec l .text 00000000 .loop_zero_bss -00000000 l df *ABS* 00000000 crtstuff.c -08002a60 l O .text 00000000 __EH_FRAME_BEGIN__ -080000ec l F .text 00000000 deregister_tm_clones -08000114 l F .text 00000000 register_tm_clones -08000144 l F .text 00000000 __do_global_dtors_aux -200000f8 l .bss 00000000 completed.7922 -200000f4 l O .data 00000000 __do_global_dtors_aux_fini_array_entry -08000174 l F .text 00000000 frame_dummy -200000fc l .bss 00000000 object.7927 -200000f0 l O .data 00000000 __frame_dummy_init_array_entry -00000000 l df *ABS* 00000000 hooks.c -20000114 l O .bss 00000001 initialized.5008 -00000000 l df *ABS* 00000000 usb_core.c -08000414 l F .text 000000d2 DataStageIn -080004e8 l F .text 00000282 Data_Setup0 -0800076c l F .text 000000ca DataStageOut -08000ac0 l F .text 00000120 NoData_Setup0 -00000000 l df *ABS* 00000000 usb_init.c -00000000 l df *ABS* 00000000 usb_int.c -00000000 l df *ABS* 00000000 usb_mem.c -00000000 l df *ABS* 00000000 usb_regs.c -00000000 l df *ABS* 00000000 usb_sil.c -00000000 l df *ABS* 00000000 main.c -08001428 l F .text 0000015e Init -00000000 l df *ABS* 00000000 usb_endp.c -00000000 l df *ABS* 00000000 usb_istr.c -00000000 l df *ABS* 00000000 usb_prop.c -00000000 l df *ABS* 00000000 usb_pwr.c -00000000 l df *ABS* 00000000 assert.c -00000000 l df *ABS* 00000000 backdoor.c -2000011c l O .bss 00000001 backdoorOpen -20000120 l O .bss 00000004 backdoorOpenTime -00000000 l df *ABS* 00000000 boot.c -00000000 l df *ABS* 00000000 com.c -20000124 l O .bss 0000003f xcpCtoReqPacket.4168 -200000ec l O .data 00000001 comActiveInterface -00000000 l df *ABS* 00000000 cop.c -00000000 l df *ABS* 00000000 xcp.c -080019cc l F .text 00000020 XcpComputeChecksum -080019ec l F .text 0000000e XcpProtectResources -080019fc l F .text 00000016 XcpSetCtoError -08001a14 l F .text 0000001e XcpCmdDisconnect -08001a34 l F .text 00000022 XcpCmdGetStatus -08001a58 l F .text 0000000a XcpCmdSynch -08001a64 l F .text 00000030 XcpCmdGetId -08001a94 l F .text 00000018 XcpCmdSetMta -08001aac l F .text 00000028 XcpCmdBuildCheckSum -08001ad4 l F .text 0000000a XcpCmdProgramPrepare -08001ae0 l F .text 00000028 XcpCmdProgramStart -08001b08 l F .text 00000044 XcpCmdConnect -08001b4c l F .text 00000040 XcpCmdUpload -08001b8c l F .text 00000042 XcpCmdShortUpload -08001bd0 l F .text 00000046 XcpCmdProgramMax -08001c18 l F .text 00000068 XcpCmdProgram -08001c80 l F .text 00000030 XcpCmdProgramClear -08001cb0 l F .text 0000001a XcpCmdProgramReset -08001ccc l F .text 0000000a XcpTransmitPacket -08002988 l O .text 00000008 xcpStationId -20000164 l O .bss 0000004c xcpInfo -00000000 l df *ABS* 00000000 cpu.c -00000000 l df *ABS* 00000000 flash.c -08001e74 l F .text 00000022 FlashUnlock -08001e98 l F .text 00000012 FlashLock -08001eac l F .text 00000050 FlashGetSector -08001efc l F .text 000000b6 FlashWriteBlock -08001fb4 l F .text 00000042 FlashGetSectorBaseAddr -08001ff8 l F .text 00000042 FlashGetSectorSize -0800203c l F .text 000000b0 FlashEraseSectors -080020ec l F .text 00000026 FlashInitBlock -08002114 l F .text 0000004e FlashSwitchBlock -08002164 l F .text 00000082 FlashAddToBlock -08002990 l O .text 000000a8 flashLayout -200001b0 l O .bss 00000204 bootBlockInfo -200003b4 l O .bss 00000204 blockInfo -00000000 l df *ABS* 00000000 nvm.c -00000000 l df *ABS* 00000000 timer.c -200005b8 l O .bss 00000004 millisecond_counter -00000000 l df *ABS* 00000000 usb.c -08002448 l F .text 0000002a IntToUnicode -08002474 l F .text 0000003a UsbFifoMgrInit -080024b0 l F .text 00000038 UsbFifoMgrCreate -080024e8 l F .text 0000007c UsbFifoMgrWrite -08002564 l F .text 00000014 UsbTransmitByte -08002578 l F .text 00000076 UsbFifoMgrRead -080025f0 l F .text 00000014 UsbReceiveByte -08002604 l F .text 0000002c UsbFifoMgrScan -200005bc l O .bss 00000040 xcpCtoReqPacket.5488 -200005fc l O .bss 00000001 xcpCtoRxInProgress.5490 -200005fd l O .bss 00000001 xcpCtoRxLength.5489 -20000600 l O .bss 00000004 fifoCtrlFree -20000604 l O .bss 00000030 fifoCtrl -20000634 l O .bss 00000041 fifoPipeBulkOUT -20000678 l O .bss 00000040 USB_Rx_Buffer.5520 -200006b8 l O .bss 00000040 USB_Tx_Buffer.5509 -200006f8 l O .bss 00000041 fifoPipeBulkIN -00000000 l df *ABS* 00000000 cpu_comp.c -00000000 l df *ABS* 00000000 c:/users/frank voorburg/mentorgraphics/sourcery_codebench_lite_for_arm_eabi/bin/../lib/gcc/arm-none-eabi/4.8.1/thumb2/crti.o -00000000 l df *ABS* 00000000 c:/users/frank voorburg/mentorgraphics/sourcery_codebench_lite_for_arm_eabi/bin/../lib/gcc/arm-none-eabi/4.8.1/thumb2/crtn.o -00000000 l df *ABS* 00000000 usb_desc.c -00000000 l df *ABS* 00000000 crtstuff.c -08002a60 l O .text 00000000 __FRAME_END__ -00000000 l df *ABS* 00000000 -00000800 l *ABS* 00000000 __HEAP_SIZE -08002a64 l .text 00000000 __exidx_end -08002a64 l .text 00000000 __exidx_start -00000800 l *ABS* 00000000 __STACK_SIZE -0800190c g F .text 00000018 ComInit -08001220 g F .text 00000022 SetEPRxValid -20000772 g O .bss 00000002 SaveRState -08002204 g F .text 00000050 FlashWrite -0800021e w F .text 00000002 EXTI2_IRQHandler -20000778 g .heap 00000800 __HeapBase -080013ac g F .text 00000024 GetEPRxCount -08001870 g F .text 00000008 AssertFailure -080015a8 g F .text 00000016 SOF_Callback -08000206 w F .text 00000002 DebugMon_Handler -08002410 g F .text 00000022 TimerUpdate -08001d08 g F .text 00000010 XcpPacketTransmitted -20000000 g .data 00000000 __data_start__ -080009f8 g F .text 0000009e Standard_SetEndPointFeature -08000df4 g F .text 00000042 USB_Init -08000244 w F .text 00000002 TIM1_CC_IRQHandler -080013d0 g F .text 0000000a ByteSwap -08001924 g F .text 0000002c ComTask -080001fc w F .text 00000002 HardFault_Handler -08001300 g F .text 0000001e GetEPTxAddr -0800020a w F .text 00000002 SysTick_Handler -08000210 w F .text 00000002 PVD_IRQHandler -08001708 g F .text 00000028 Bulk_Init -080018dc g F .text 0000001c BootInit -08000208 w F .text 00000002 PendSV_Handler -080001fa w F .text 00000002 NMI_Handler -08000220 w F .text 00000002 EXTI3_IRQHandler -080018b8 g F .text 00000022 BackDoorInit -08001340 g F .text 00000020 SetEPTxCount -08002a64 g .text 00000000 __etext -20000740 g O .bss 00000002 SaveState -200000b8 g O .data 00000008 Device_Descriptor -080019c8 g F .text 00000002 CopService -080016f8 g F .text 00000010 Bulk_Get_Interface_Setting -080028b8 g F .text 00000004 CpuIrqDisable -0800118c g F .text 00000036 SetEPTxStatus -20000038 g O .data 0000001c pEpInt_OUT -08000a98 g F .text 00000026 Standard_SetDeviceFeature -0800238c g F .text 0000000a FlashGetUserProgBaseAddress -200000f8 g O .data 00000000 .hidden __TMC_END__ -080015a0 g F .text 00000008 EP1_OUT_Callback -080023d4 g F .text 0000000e TimerReset -080008dc g F .text 0000011c Standard_ClearFeature -0800021a w F .text 00000002 EXTI0_IRQHandler -08001404 g F .text 00000024 USB_SIL_Read -08000250 w F .text 00000002 I2C2_EV_IRQHandler -08001694 g F .text 00000002 Bulk_Status_In -08000c44 g F .text 0000008c Setup0_Process -080018f8 g F .text 00000014 BootTask -08002280 g F .text 00000058 FlashWriteChecksum -08000202 w F .text 00000002 UsageFault_Handler -08001958 g F .text 0000001c ComTransmitPacket -08000232 w F .text 00000002 ADC1_2_IRQHandler -08002878 g F .text 00000040 UsbGetSerialNum -20000f78 g .heap 00000000 __HeapLimit -200000f8 g .bss 00000000 __bss_start__ -08002920 g O .text 00000020 Bulk_ConfigDescriptor -08000254 w F .text 00000002 SPI1_IRQHandler -08001698 g F .text 00000002 Bulk_Status_Out -20000776 g O .bss 00000002 wIstr -08000212 w F .text 00000002 TAMPER_IRQHandler -20000744 g O .bss 00000004 pProperty -08000838 g F .text 00000044 Standard_SetConfiguration -2000001c g O .data 0000001c pEpInt_IN -0800022a w F .text 00000002 DMA1_Channel4_IRQHandler -20000748 g O .bss 00000001 EPindex -2000005c g O .data 00000030 Device_Property -08002940 g O .text 0000001a Bulk_StringVendor -08001cf4 g F .text 00000012 XcpIsConnected -080028c0 g F .text 00000000 _init -08000334 g F .text 000000e0 Standard_GetStatus -08002398 g F .text 00000008 NvmInit -080028e0 g O .text 00000012 Bulk_DeviceDescriptor -080021e8 g F .text 0000001a FlashInit -080023b8 g F .text 00000008 NvmGetUserProgBaseAddress -200000c0 g O .data 00000028 String_Descriptor -08001264 g F .text 00000026 ClearDTOG_RX -0800025c w F .text 00000002 USART3_IRQHandler -08000214 w F .text 00000002 RTC_IRQHandler -08000df0 g F .text 00000002 NOP_Process -08000230 w F .text 00000002 DMA1_Channel7_IRQHandler -080001b4 g F .text 00000030 Reset_Handler -08000238 w F .text 00000002 CAN1_RX1_IRQHandler -0800087c g F .text 00000060 Standard_SetInterface -08001360 g F .text 0000004a SetEPRxCount -080013dc g F .text 00000026 USB_SIL_Init -08001950 g F .text 00000008 ComFree -0800183c g F .text 00000034 PowerOn -0800024a w F .text 00000002 TIM4_IRQHandler -20000000 g O .data 0000001c Bulk_StringSerial -08000e38 g F .text 000002da CTR_LP -00000000 w *UND* 00000000 __deregister_frame_info -20000778 g .heap 00000000 end -0800024c w F .text 00000002 I2C1_EV_IRQHandler -20000774 g O .bss 00000002 SaveTState -200000f8 g .data 00000000 __data_end__ -08001160 g F .text 00000012 SetBTABLE -00000000 w *UND* 00000000 _ITM_registerTMCloneTable -0800281c g F .text 0000005a UsbReceivePipeBulkOUT -080023a8 g F .text 00000008 NvmErase -080002c4 g F .text 00000010 CpuUserProgramStartHook -2000008c g O .data 00000024 User_Standard_Requests -0800022e w F .text 00000002 DMA1_Channel6_IRQHandler -20000778 g .bss 00000000 __bss_end__ -08001730 g F .text 000000b4 Bulk_Reset -08000248 w F .text 00000002 TIM3_IRQHandler -08000218 w F .text 00000002 RCC_IRQHandler -2000074c g O .bss 0000001c Device_Info -08000242 w F .text 00000002 TIM1_TRG_COM_IRQHandler -08000224 w F .text 00000002 DMA1_Channel1_IRQHandler -08001684 g F .text 0000000e Bulk_SetDeviceAddress -080002d4 g F .text 00000030 Standard_GetConfiguration -0800020c w F .text 00000002 Default_Handler -080001e4 w F .text 00000016 _start -08001d18 g F .text 000000f6 XcpPacketReceived -08001e10 g F .text 00000008 CpuInit -20000768 g O .bss 00000004 pUser_Standard_Requests -0800025e w F .text 00000002 EXTI15_10_IRQHandler -08002340 g F .text 0000004c FlashDone -08000d30 g F .text 00000048 SetDeviceAddress -08001140 g F .text 00000020 PMAToUserBufferCopy -080012d8 g F .text 00000026 SetEPRxAddr -20000116 g O .bss 00000001 bIntPackSOF -08002684 g F .text 00000064 UsbTransmitPacket -08000d78 g F .text 00000076 In0_Process -0800026c g F .text 00000056 UsbConnectHook -0800169c g F .text 00000058 Bulk_Data_Setup -0800023c w F .text 00000002 EXTI9_5_IRQHandler -2000073c g O .bss 00000002 StatusInfo -2000076c g O .bss 00000004 pInformation -08001174 g F .text 00000018 SetEPType -08001cd8 g F .text 0000001c XcpInit -00000000 w *UND* 00000000 _ITM_deregisterTMCloneTable -08002630 g F .text 00000048 UsbInit -08000256 w F .text 00000002 SPI2_IRQHandler -08002678 g F .text 0000000a UsbFree -08002254 g F .text 0000002a FlashErase -080001fe w F .text 00000002 MemManage_Handler -08000000 g .text 000000ec __isr_vector -08001588 g F .text 00000010 main -08000304 g F .text 00000030 Standard_GetInterface -08000204 w F .text 00000002 SVC_Handler -080023c0 g F .text 00000012 NvmDone -080023b0 g F .text 00000008 NvmVerifyChecksum -08001e54 g F .text 00000020 CpuMemCopy -20000778 g .heap 00000000 __end__ -0800022c w F .text 00000002 DMA1_Channel5_IRQHandler -08000222 w F .text 00000002 EXTI4_IRQHandler -08000236 w F .text 00000002 USB_LP_CAN1_RX0_IRQHandler -200000b0 g O .data 00000008 Bulk_Descriptor -080028cc g F .text 00000000 _fini -08000234 w F .text 00000002 USB_HP_CAN1_TX_IRQHandler -080016f4 g F .text 00000004 Bulk_NoData_Setup -08001998 g F .text 00000022 ComGetActiveInterfaceMaxTxLen -080017e4 g F .text 00000010 Bulk_GetDeviceDescriptor -080028bc g F .text 00000004 CpuIrqEnable -08000228 w F .text 00000002 DMA1_Channel3_IRQHandler -20005000 g *ABS* 00000000 __StackTop -08000240 w F .text 00000002 TIM1_UP_IRQHandler -08000be0 g F .text 0000001c Standard_GetDescriptorData -080028f8 g O .text 00000026 Bulk_StringProduct -08000cd0 g F .text 00000060 Out0_Process -0800020e w F .text 00000002 WWDG_IRQHandler -080028f4 g O .text 00000004 Bulk_StringLangID -080019c4 g F .text 00000002 CopInit -08001598 g F .text 00000008 EP1_IN_Callback -08000246 w F .text 00000002 TIM2_IRQHandler -080011fc g F .text 00000022 SetEPTxValid -08001804 g F .text 00000028 Bulk_GetStringDescriptor -080023a0 g F .text 00000008 NvmWrite -08001e18 g F .text 0000003a CpuStartUserProgram -0800023e w F .text 00000002 TIM1_BRK_IRQHandler -080026e8 g F .text 000000ac UsbReceivePacket -0800021c w F .text 00000002 EXTI1_IRQHandler -080022d8 g F .text 00000068 FlashVerifyChecksum -20000115 g O .bss 00000001 Data_Mul_MaxPacketSize -0800182c g F .text 00000010 Bulk_GetBulkDescriptor -08000bfc g F .text 00000048 Post0_Process -08000260 w F .text 00000002 RTCAlarm_IRQHandler -080015c0 g F .text 000000a6 USB_Istr -080011c4 g F .text 00000036 SetEPRxStatus -20004800 g *ABS* 00000800 __StackLimit -0800025a w F .text 00000002 USART2_IRQHandler -0800128c g F .text 00000026 ClearDTOG_TX -080012b4 g F .text 00000024 SetEPTxAddr -08000252 w F .text 00000002 I2C2_ER_IRQHandler -080019bc g F .text 00000008 ComIsConnected -08000226 w F .text 00000002 DMA1_Channel2_IRQHandler -20000054 g O .data 00000008 Config_Descriptor -08001244 g F .text 0000001e Clear_Status_Out -0800023a w F .text 00000002 CAN1_SCE_IRQHandler -08000216 w F .text 00000002 FLASH_IRQHandler -08001114 g F .text 0000002c UserToPMABufferCopy -08001974 g F .text 00000022 ComGetActiveInterfaceMaxRxLen -08000200 w F .text 00000002 BusFault_Handler -08000258 w F .text 00000002 USART1_IRQHandler -08001878 g F .text 00000040 BackDoorCheck -08001668 g F .text 0000001a Bulk_SetConfiguration -0800024e w F .text 00000002 I2C1_ER_IRQHandler -20000118 g O .bss 00000004 bDeviceState -08002434 g F .text 00000012 TimerGet -200000e8 g O .data 00000002 Device_Table -08002794 g F .text 00000088 UsbTransmitPipeBulkIN -00000000 w *UND* 00000000 _Jv_RegisterClasses -080017f4 g F .text 00000010 Bulk_GetConfigDescriptor -0800295c g O .text 0000002c Bulk_StringInterface -080023e4 g F .text 0000002c TimerInit -00000000 w *UND* 00000000 __register_frame_info -20000770 g O .bss 00000002 wInterrupt_Mask -08001320 g F .text 00000020 GetEPRxAddr -08000262 w F .text 00000002 USBWakeUp_IRQHandler - - + +bin/openblt_olimex_stm32h103.elf: file format elf32-littlearm +bin/openblt_olimex_stm32h103.elf +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x08000000 + +Program Header: +0x70000001 off 0x00012714 vaddr 0x08002714 paddr 0x08002714 align 2**2 + filesz 0x00000008 memsz 0x00000008 flags r-- + LOAD off 0x00010000 vaddr 0x08000000 paddr 0x08000000 align 2**16 + filesz 0x0000271c memsz 0x0000271c flags r-x + LOAD off 0x00020000 vaddr 0x20000000 paddr 0x0800271c align 2**16 + filesz 0x00000158 memsz 0x000007d6 flags rw- +private flags = 5000200: [Version5 EABI] [soft-float ABI] + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00002714 08000000 08000000 00010000 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .ARM.exidx 00000008 08002714 08002714 00012714 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .data 00000158 20000000 0800271c 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 3 .bss 0000067e 20000158 08002874 00020158 2**2 + ALLOC + 4 .heap 00000800 200007d8 200007d8 00020158 2**3 + CONTENTS, READONLY + 5 .stack_dummy 00000800 200007d8 200007d8 00020958 2**3 + CONTENTS, READONLY + 6 .ARM.attributes 00000029 00000000 00000000 00021158 2**0 + CONTENTS, READONLY + 7 .comment 0000006e 00000000 00000000 00021181 2**0 + CONTENTS, READONLY + 8 .debug_line 00004a4f 00000000 00000000 000211ef 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_info 00006729 00000000 00000000 00025c3e 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 00001d0d 00000000 00000000 0002c367 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_aranges 000008f0 00000000 00000000 0002e078 2**3 + CONTENTS, READONLY, DEBUGGING + 12 .debug_macro 0000ba58 00000000 00000000 0002e968 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_str 0003922c 00000000 00000000 0003a3c0 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_ranges 00000748 00000000 00000000 000735ec 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_frame 00001324 00000000 00000000 00073d34 2**2 + CONTENTS, READONLY, DEBUGGING + 16 .debug_loc 00002c1e 00000000 00000000 00075058 2**0 + CONTENTS, READONLY, DEBUGGING +SYMBOL TABLE: +08000000 l d .text 00000000 .text +08002714 l d .ARM.exidx 00000000 .ARM.exidx +20000000 l d .data 00000000 .data +20000158 l d .bss 00000000 .bss +200007d8 l d .heap 00000000 .heap +200007d8 l d .stack_dummy 00000000 .stack_dummy +00000000 l d .ARM.attributes 00000000 .ARM.attributes +00000000 l d .comment 00000000 .comment +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_macro 00000000 .debug_macro +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .debug_ranges 00000000 .debug_ranges +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l df *ABS* 00000000 obj/startup_stm32f10x_md.o +00000800 l *ABS* 00000000 Stack_Size +00000800 l *ABS* 00000000 Heap_Size +080001c6 l .text 00000000 .flash_to_ram_loop +080001f8 l .text 00000000 .fill_zero_bss +080001f4 l .text 00000000 .loop_zero_bss +00000000 l df *ABS* 00000000 crtstuff.c +08002710 l O .text 00000000 __EH_FRAME_BEGIN__ +080000ec l F .text 00000000 __do_global_dtors_aux +20000158 l .bss 00000000 completed.8603 +20000154 l O .data 00000000 __do_global_dtors_aux_fini_array_entry +08000110 l F .text 00000000 frame_dummy +2000015c l .bss 00000000 object.8608 +20000150 l O .data 00000000 __frame_dummy_init_array_entry +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m/crt0.o +00000000 l df *ABS* 00000000 usb_endp.c +00000000 l df *ABS* 00000000 usb_prop.c +00000000 l df *ABS* 00000000 main.c +0800044c l F .text 00000134 Init +00000000 l df *ABS* 00000000 hooks.c +20000174 l O .bss 00000001 initialized.5134 +00000000 l df *ABS* 00000000 usb_istr.c +00000000 l df *ABS* 00000000 _exit.c +00000000 l df *ABS* 00000000 usb_mem.c +00000000 l df *ABS* 00000000 usb_init.c +00000000 l df *ABS* 00000000 usb_sil.c +00000000 l df *ABS* 00000000 usb_regs.c +00000000 l df *ABS* 00000000 usb_core.c +08000aa8 l F .text 000000b0 DataStageIn +08000b58 l F .text 00000218 Data_Setup0 +08000d70 l F .text 000000a8 DataStageOut +080010c4 l F .text 00000114 NoData_Setup0 +00000000 l df *ABS* 00000000 usb_int.c +00000000 l df *ABS* 00000000 usb_pwr.c +00000000 l df *ABS* 00000000 xcp.c +08001664 l F .text 0000001e XcpComputeChecksum +08001684 l F .text 0000000c XcpProtectResources +08001690 l F .text 00000014 XcpSetCtoError +080016a4 l F .text 0000001c XcpCmdDisconnect +080016c0 l F .text 00000020 XcpCmdGetStatus +080016e0 l F .text 0000000a XcpCmdSynch +080016ec l F .text 0000002c XcpCmdGetId +08001718 l F .text 00000018 XcpCmdSetMta +08001730 l F .text 00000028 XcpCmdBuildCheckSum +08001758 l F .text 0000000a XcpCmdProgramPrepare +08001764 l F .text 00000028 XcpCmdProgramStart +0800178c l F .text 00000044 XcpCmdConnect +080017d0 l F .text 00000040 XcpCmdUpload +08001810 l F .text 00000040 XcpCmdShortUpload +08001850 l F .text 00000040 XcpCmdProgramMax +08001890 l F .text 0000005c XcpCmdProgram +080018ec l F .text 00000028 XcpCmdProgramClear +08001914 l F .text 00000018 XcpCmdProgramReset +0800192c l F .text 0000000a XcpTransmitPacket +08002634 l O .text 00000008 xcpStationId +2000017c l O .bss 0000004c xcpInfo +00000000 l df *ABS* 00000000 com.c +200001c8 l O .bss 0000003f xcpCtoReqPacket.4276 +200000ec l O .data 00000001 comActiveInterface +00000000 l df *ABS* 00000000 backdoor.c +20000207 l O .bss 00000001 backdoorOpen +20000208 l O .bss 00000004 backdoorOpenTime +00000000 l df *ABS* 00000000 boot.c +00000000 l df *ABS* 00000000 cop.c +00000000 l df *ABS* 00000000 assert.c +00000000 l df *ABS* 00000000 nvm.c +00000000 l df *ABS* 00000000 usb.c +08001bc0 l F .text 00000030 IntToUnicode +08001bf0 l F .text 00000030 UsbFifoMgrInit +08001c20 l F .text 00000030 UsbFifoMgrCreate +08001c50 l F .text 0000006c UsbFifoMgrWrite +08001cbc l F .text 00000014 UsbTransmitByte +08001cd0 l F .text 00000068 UsbFifoMgrRead +08001d38 l F .text 00000014 UsbReceiveByte +08001d4c l F .text 00000028 UsbFifoMgrScan +2000020c l O .bss 00000040 USB_Rx_Buffer.5646 +2000024c l O .bss 00000004 fifoCtrlFree +20000250 l O .bss 00000030 fifoCtrl +20000280 l O .bss 00000041 fifoPipeBulkOUT +200002c4 l O .bss 00000040 xcpCtoReqPacket.5614 +20000304 l O .bss 00000040 USB_Tx_Buffer.5635 +20000344 l O .bss 00000001 xcpCtoRxLength.5615 +20000345 l O .bss 00000001 xcpCtoRxInProgress.5616 +20000348 l O .bss 00000041 fifoPipeBulkIN +00000000 l df *ABS* 00000000 cpu.c +00000000 l df *ABS* 00000000 flash.c +08001fe4 l F .text 0000001c FlashUnlock +08002000 l F .text 00000010 FlashLock +08002010 l F .text 00000048 FlashGetSector +08002058 l F .text 000000a4 FlashWriteBlock +080020fc l F .text 00000038 FlashGetSectorBaseAddr +08002134 l F .text 00000038 FlashGetSectorSize +0800216c l F .text 000000a4 FlashEraseSectors +08002210 l F .text 00000026 FlashInitBlock +08002238 l F .text 00000040 FlashSwitchBlock +08002278 l F .text 0000007a FlashAddToBlock +08002664 l O .text 000000a8 flashLayout +2000038c l O .bss 00000204 bootBlockInfo +20000590 l O .bss 00000204 blockInfo +00000000 l df *ABS* 00000000 timer.c +20000794 l O .bss 00000004 millisecond_counter +00000000 l df *ABS* 00000000 cpu_comp.c +00000000 l df *ABS* 00000000 exit.c +00000000 l df *ABS* 00000000 init.c +00000000 l df *ABS* 00000000 memset.c +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crti.o +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o +00000000 l df *ABS* 00000000 usb_desc.c +00000000 l df *ABS* 00000000 impure.c +200000f0 l O .data 00000060 impure_data +00000000 l df *ABS* 00000000 crtstuff.c +08002710 l O .text 00000000 __FRAME_END__ +00000000 l df *ABS* 00000000 +20000154 l .data 00000000 __init_array_end +20000150 l .data 00000000 __preinit_array_end +20000150 l .data 00000000 __init_array_start +20000150 l .data 00000000 __preinit_array_start +08001a54 g F .text 00000018 ComInit +200007d2 g O .bss 00000002 SaveRState +08000804 g F .text 00000026 SetEPRxValid +0800230c g F .text 0000005c FlashWrite +08000226 w F .text 00000002 EXTI2_IRQHandler +200007d8 g .heap 00000800 __HeapBase +08000974 g F .text 00000020 GetEPRxCount +08001b7c g F .text 00000008 AssertFailure +08000284 g F .text 00000014 SOF_Callback +0800020e w F .text 00000002 DebugMon_Handler +00000800 g *ABS* 00000000 __HEAP_SIZE +080024b4 g F .text 0000001c TimerUpdate +08001964 g F .text 00000010 XcpPacketTransmitted +20000000 g .data 00000000 __data_start__ +08000fdc g F .text 000000c4 Standard_SetEndPointFeature +080006bc g F .text 00000038 USB_Init +0800024c w F .text 00000002 TIM1_CC_IRQHandler +08000994 g F .text 0000000a ByteSwap +08001a6c g F .text 00000024 ComTask +08000204 w F .text 00000002 HardFault_Handler +080008dc g F .text 0000001c GetEPTxAddr +08000212 w F .text 00000002 SysTick_Handler +08000218 w F .text 00000002 PVD_IRQHandler +08000328 g F .text 00000024 Bulk_Init +08001b44 g F .text 0000001c BootInit +08000210 w F .text 00000002 PendSV_Handler +08000202 w F .text 00000002 NMI_Handler +0800271c g .ARM.exidx 00000000 __exidx_end +08000228 w F .text 00000002 EXTI3_IRQHandler +08001b24 g F .text 00000020 BackDoorInit +08000914 g F .text 0000001c SetEPTxCount +0800271c g .ARM.exidx 00000000 __etext +2000079c g O .bss 00000002 SaveState +20000080 g O .data 00000008 Device_Descriptor +08001b78 g F .text 00000002 CopService +08000318 g F .text 00000010 Bulk_Get_Interface_Setting +080024e0 g F .text 00000004 CpuIrqDisable +08000764 g F .text 0000003c SetEPTxStatus +200000d0 g O .data 0000001c pEpInt_OUT +080010a0 g F .text 00000024 Standard_SetDeviceFeature +08002478 g F .text 00000008 FlashGetUserProgBaseAddress +0800027c g F .text 00000008 EP1_OUT_Callback +08002480 g F .text 0000000c TimerReset +08000eb4 g F .text 00000128 Standard_ClearFeature +08000222 w F .text 00000002 EXTI0_IRQHandler +08000714 g F .text 00000024 USB_SIL_Read +08000258 w F .text 00000002 I2C2_EV_IRQHandler +080002bc g F .text 00000002 Bulk_Status_In +08001234 g F .text 0000007c Setup0_Process +08001b60 g F .text 00000014 BootTask +08002398 g F .text 00000050 FlashWriteChecksum +0800020a w F .text 00000002 UsageFault_Handler +08001a98 g F .text 0000001c ComTransmitPacket +0800023a w F .text 00000002 ADC1_2_IRQHandler +08001f4c g F .text 00000038 UsbGetSerialNum +20000fd8 g .heap 00000000 __HeapLimit +20000158 g .bss 00000000 __bss_start__ +080025c4 g O .text 00000020 Bulk_ConfigDescriptor +0800025c w F .text 00000002 SPI1_IRQHandler +080002c0 g F .text 00000002 Bulk_Status_Out +20000798 g O .bss 00000002 wIstr +0800021a w F .text 00000002 TAMPER_IRQHandler +200007a0 g O .bss 00000004 pProperty +08000e18 g F .text 00000040 Standard_SetConfiguration +08002714 g .text 00000000 __exidx_start +200000b4 g O .data 0000001c pEpInt_IN +0800270c g O .text 00000004 _global_impure_ptr +08002510 g F .text 0000004c __libc_init_array +08000232 w F .text 00000002 DMA1_Channel4_IRQHandler +08000148 g F .text 00000000 _mainCRTStartup +200007a4 g O .bss 00000001 EPindex +20000024 g O .data 00000030 Device_Property +080025e4 g O .text 0000001a Bulk_StringVendor +08001954 g F .text 00000010 XcpIsConnected +0800256c g F .text 00000000 _init +080009f0 g F .text 000000b8 Standard_GetStatus +08001b84 g F .text 00000008 NvmInit +08002584 g O .text 00000012 Bulk_DeviceDescriptor +080022f4 g F .text 00000018 FlashInit +08001ba4 g F .text 00000008 NvmGetUserProgBaseAddress +20000088 g O .data 00000028 String_Descriptor +0800084c g F .text 00000028 ClearDTOG_RX +08000264 w F .text 00000002 USART3_IRQHandler +00000000 w *UND* 00000000 __libc_fini_array +0800021c w F .text 00000002 RTC_IRQHandler +080013b0 g F .text 00000002 NOP_Process +08000238 w F .text 00000002 DMA1_Channel7_IRQHandler +080001bc g F .text 00000030 Reset_Handler +08000240 w F .text 00000002 CAN1_RX1_IRQHandler +08000e58 g F .text 0000005c Standard_SetInterface +08000930 g F .text 00000044 SetEPRxCount +080006f4 g F .text 00000020 USB_SIL_Init +08001a90 g F .text 00000008 ComFree +08001634 g F .text 00000030 PowerOn +08000252 w F .text 00000002 TIM4_IRQHandler +20000000 g O .data 0000001c Bulk_StringSerial +080013b4 g F .text 00000280 CTR_LP +00000000 w *UND* 00000000 __sf_fake_stderr +00000000 w *UND* 00000000 __deregister_frame_info +200007d8 g .heap 00000000 end +08000254 w F .text 00000002 I2C1_EV_IRQHandler +200007d4 g O .bss 00000002 SaveTState +20000158 g .data 00000000 __data_end__ +08000738 g F .text 00000010 SetBTABLE +08001f04 g F .text 00000048 UsbReceivePipeBulkOUT +08001b94 g F .text 00000008 NvmErase +080005dc g F .text 00000018 CpuUserProgramStartHook +20000054 g O .data 00000024 User_Standard_Requests +08000236 w F .text 00000002 DMA1_Channel6_IRQHandler +200007d6 g .bss 00000000 __bss_end__ +00000800 g *ABS* 00000000 __STACK_SIZE +0800034c g F .text 000000ac Bulk_Reset +08000250 w F .text 00000002 TIM3_IRQHandler +08000220 w F .text 00000002 RCC_IRQHandler +200007a8 g O .bss 0000001c Device_Info +0800024a w F .text 00000002 TIM1_TRG_COM_IRQHandler +00000000 w *UND* 00000000 __call_exitprocs +0800022c w F .text 00000002 DMA1_Channel1_IRQHandler +080002b0 g F .text 0000000c Bulk_SetDeviceAddress +080009a0 g F .text 00000028 Standard_GetConfiguration +08000214 w F .text 00000002 Default_Handler +08000148 g F .text 00000000 _start +08001974 g F .text 000000e0 XcpPacketReceived +08001f84 g F .text 00000008 CpuInit +200007c4 g O .bss 00000004 pUser_Standard_Requests +08000266 w F .text 00000002 EXTI15_10_IRQHandler +08002438 g F .text 00000040 FlashDone +08001304 g F .text 00000048 SetDeviceAddress +0800069c g F .text 00000020 PMAToUserBufferCopy +00000000 w *UND* 00000000 software_init_hook +080008bc g F .text 00000020 SetEPRxAddr +20000175 g O .bss 00000001 bIntPackSOF +08001dc4 g F .text 00000050 UsbTransmitPacket +0800134c g F .text 00000064 In0_Process +08000590 g F .text 0000004c UsbConnectHook +080002c4 g F .text 00000050 Bulk_Data_Setup +08000244 w F .text 00000002 EXTI9_5_IRQHandler +200007d0 g O .bss 00000002 StatusInfo +200007c8 g O .bss 00000004 pInformation +08000748 g F .text 0000001c SetEPType +08001938 g F .text 0000001c XcpInit +08001d74 g F .text 00000044 UsbInit +0800025e w F .text 00000002 SPI2_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stdin +08001db8 g F .text 0000000a UsbFree +08002368 g F .text 0000002e FlashErase +0800255c g F .text 00000010 memset +08000206 w F .text 00000002 MemManage_Handler +08000000 g .text 000000ec __isr_vector +08000580 g F .text 00000010 main +080009c8 g F .text 00000028 Standard_GetInterface +0800020c w F .text 00000002 SVC_Handler +08001bac g F .text 00000014 NvmDone +08001b9c g F .text 00000008 NvmVerifyChecksum +00000000 w *UND* 00000000 hardware_init_hook +08001fc4 g F .text 00000020 CpuMemCopy +200007d8 g .heap 00000000 __end__ +08000234 w F .text 00000002 DMA1_Channel5_IRQHandler +0800022a w F .text 00000002 EXTI4_IRQHandler +0800023e w F .text 00000002 USB_LP_CAN1_RX0_IRQHandler +20000078 g O .data 00000008 Bulk_Descriptor +08002578 g F .text 00000000 _fini +0800023c w F .text 00000002 USB_HP_CAN1_TX_IRQHandler +08000314 g F .text 00000004 Bulk_NoData_Setup +08001acc g F .text 00000018 ComGetActiveInterfaceMaxTxLen +00000000 w *UND* 00000000 atexit +080003f8 g F .text 00000010 Bulk_GetDeviceDescriptor +080024e4 g F .text 00000004 CpuIrqEnable +08000230 w F .text 00000002 DMA1_Channel3_IRQHandler +20005000 g .bss 00000000 __StackTop +08000248 w F .text 00000002 TIM1_UP_IRQHandler +080011d8 g F .text 0000001c Standard_GetDescriptorData +0800259c g O .text 00000026 Bulk_StringProduct +080012b0 g F .text 00000054 Out0_Process +08000216 w F .text 00000002 WWDG_IRQHandler +08002598 g O .text 00000004 Bulk_StringLangID +08001b74 g F .text 00000002 CopInit +08000274 g F .text 00000008 EP1_IN_Callback +0800024e w F .text 00000002 TIM2_IRQHandler +080007dc g F .text 00000026 SetEPTxValid +08000418 g F .text 00000024 Bulk_GetStringDescriptor +08001b8c g F .text 00000008 NvmWrite +08001f8c g F .text 00000038 CpuStartUserProgram +08000246 w F .text 00000002 TIM1_BRK_IRQHandler +08001e14 g F .text 00000080 UsbReceivePacket +20005000 g *ABS* 00000000 __stack +08000224 w F .text 00000002 EXTI1_IRQHandler +080023e8 g F .text 00000050 FlashVerifyChecksum +20000176 g O .bss 00000001 Data_Mul_MaxPacketSize +0800043c g F .text 00000010 Bulk_GetBulkDescriptor +080011f4 g F .text 00000040 Post0_Process +08000268 w F .text 00000002 RTCAlarm_IRQHandler +080005f4 g F .text 00000078 USB_Istr +080007a0 g F .text 0000003c SetEPRxStatus +20004800 g *ABS* 00000800 __StackLimit +08000262 w F .text 00000002 USART2_IRQHandler +080024e8 g F .text 00000028 exit +08000874 g F .text 00000028 ClearDTOG_TX +0800089c g F .text 00000020 SetEPTxAddr +0800025a w F .text 00000002 I2C2_ER_IRQHandler +08001ae4 g F .text 00000008 ComIsConnected +0800022e w F .text 00000002 DMA1_Channel2_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stdout +2000001c g O .data 00000008 Config_Descriptor +0800082c g F .text 00000020 Clear_Status_Out +08000242 w F .text 00000002 CAN1_SCE_IRQHandler +0800021e w F .text 00000002 FLASH_IRQHandler +0800066c w F .text 00000002 _exit +08000670 g F .text 0000002a UserToPMABufferCopy +08001ab4 g F .text 00000018 ComGetActiveInterfaceMaxRxLen +08000208 w F .text 00000002 BusFault_Handler +08000260 w F .text 00000002 USART1_IRQHandler +08001aec g F .text 00000038 BackDoorCheck +08000298 g F .text 00000018 Bulk_SetConfiguration +08000256 w F .text 00000002 I2C1_ER_IRQHandler +20000178 g O .bss 00000004 bDeviceState +080024d0 g F .text 00000010 TimerGet +200000b0 g O .data 00000002 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+S3150800279C8425000812000000982500080400000093 +S315080027ACE42500081A0000009C25000826000000F5 +S315080027BC000000201C000000002600082C00000069 +S315080027CC0301000075020008B1130008B1130008D4 +S315080027DCB1130008B1130008B1130008B1130008AF +S315080027EC7D020008B1130008B1130008B1130008E4 +S315080027FCB1130008B1130008B11300080400000057 +S3150800280C00000000000000000000000000000000AE +S3150800281C000000000000000000000000000000009E +S3150800282C000000000000000000000000000000008E +S3150800283C000000000000000000000000000000007E +S3150800284C000000000000000000000000000000006E +S3150800285C000000000000000000000000000000005E +S30D0800286C11010008ED00000847 S70508000000F2 diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/build.bat b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/build.bat deleted file mode 100644 index 6cdb041e..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/build.bat +++ /dev/null @@ -1,2 +0,0 @@ -@echo off -cs-make --directory=../ all diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/clean.bat b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/clean.bat deleted file mode 100644 index 025aaea0..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/clean.bat +++ /dev/null @@ -1,2 +0,0 @@ -@echo off -cs-make --directory=../ clean diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/debug.bat b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/debug.bat deleted file mode 100644 index 377cdde6..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/debug.bat +++ /dev/null @@ -1 +0,0 @@ -"C:\Program Files (x86)\OpenOCD\0.4.0\bin\openocd.exe" -f debug.cfg \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/debug.cfg b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/debug.cfg deleted file mode 100644 index 741aecbd..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/debug.cfg +++ /dev/null @@ -1,15 +0,0 @@ -### -# Description: starts the OpenOCD GDB server (localhost:3333) -# once started use arm-elf-insight .elf to start the debug session -# Usage: openocd.exe" -f debug.cfg -### -source [find interface/olimex-arm-usb-tiny-h.cfg] -source [find board/olimex_stm32_h103.cfg] - -jtag_khz 1000 -init -reset -halt - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/flash.bat b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/flash.bat deleted file mode 100644 index 876b4a5d..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/flash.bat +++ /dev/null @@ -1 +0,0 @@ -"C:\Program Files (x86)\OpenOCD\0.4.0\bin\openocd.exe" -f flash.cfg \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/flash.cfg b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/flash.cfg deleted file mode 100644 index ad447ab2..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/cmd/flash.cfg +++ /dev/null @@ -1,21 +0,0 @@ -### -# Description: mass erases and flashes the binary with OpenOCD -# Usage: openocd.exe" -f flash.cfg -### - -source [find interface/olimex-arm-usb-tiny-h.cfg] -source [find board/olimex_stm32_h103.cfg] - -jtag_khz 1000 - -init -reset -sleep 500 -halt -stm32x mass_erase 0 -flash write_image ..\\bin\\openblt_olimex_stm32h103.elf -#flash write_image erase ..\\bin\\openblt_olimex_stm32h103.elf -reset run -shutdown - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/ide/DemoBoot.project b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/ide/DemoBoot.project deleted file mode 100644 index c55d0b69..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/ide/DemoBoot.project +++ /dev/null @@ -1,181 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - break main -continue - - - - - - - make clean - make - - - - None - $(WorkspacePath)/.. - - - - - - - - - - - - - - - - - - - - - - - make clean - make - - - - None - $(WorkspacePath) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/ide/DemoBoot.workspace b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/ide/DemoBoot.workspace deleted file mode 100644 index 7957a1d7..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/ide/DemoBoot.workspace +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/ide/readme.txt b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/ide/readme.txt deleted file mode 100644 index 8a340a19..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/ide/readme.txt +++ /dev/null @@ -1,4 +0,0 @@ -Integrated Development Environment ----------------------------------- -Codelite was used as the editor during the development of this software program. This directory contains the Codelite -workspace and project files. Codelite is a cross platform open source C/C++ IDE, available at http://www.codelite.org/. \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/lib/newlib/_exit.c b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/lib/newlib/_exit.c new file mode 100644 index 00000000..4ae9532c --- /dev/null +++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/lib/newlib/_exit.c @@ -0,0 +1,38 @@ +// ---------------------------------------------------------------------------- + +#include + +// ---------------------------------------------------------------------------- + +// Forward declaration + +void +_exit(int code); + +// ---------------------------------------------------------------------------- + +// We just enter an infinite loop, to be used as landmark when halting +// the debugger. +// +// It can be redefined in the application, if more functionality +// is required. + +void +__attribute__((weak)) +_exit(int code __attribute__((unused))) +{ + // TODO: write on trace + while (1) + ; +} + +// ---------------------------------------------------------------------------- + +void +__attribute__((weak,noreturn)) +abort(void) +{ + _exit(1); +} + +// ---------------------------------------------------------------------------- diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/makefile b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/makefile index 54f6bb41..072f5284 100644 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/makefile +++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Boot/makefile @@ -34,7 +34,7 @@ PROJ_NAME=openblt_olimex_stm32h103 #|--------------------------------------------------------------------------------------| #| Configure tool path | #|--------------------------------------------------------------------------------------| -TOOL_PATH= +TOOL_PATH=/opt/gcc-arm-none-eabi-5_4-2016q3/bin/ #|--------------------------------------------------------------------------------------| @@ -64,7 +64,7 @@ PROJ_FILES += $(wildcard ../../../Source/ARMCM3_STM32F1/GCC/*.h) #|--------------------------------------------------------------------------------------| #| Toolchain binaries | #|--------------------------------------------------------------------------------------| -RM = cs-rm +RM = rm CC = $(TOOL_PATH)arm-none-eabi-gcc LN = $(TOOL_PATH)arm-none-eabi-gcc OC = $(TOOL_PATH)arm-none-eabi-objcopy @@ -107,7 +107,7 @@ AFLAGS = $(CFLAGS) LFLAGS = $(STDFLAGS) $(OPTFLAGS) LFLAGS += -Wl,--defsym=__HEAP_SIZE=$(HEAP_SIZE) -Wl,--defsym=__STACK_SIZE=$(STACK_SIZE) LFLAGS += -Wl,-script="stm32f103rb_flash.ld" -Wl,-Map=$(BIN_PATH)/$(PROJ_NAME).map -LFLAGS += -Wl,--gc-sections $(LIB_PATH) +LFLAGS += -specs=nano.specs -Wl,--gc-sections $(LIB_PATH) OFLAGS = -O srec ODFLAGS = -x SZFLAGS = -B -d diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Prog/bin/demoprog_olimex_stm32h103.elf b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Prog/bin/demoprog_olimex_stm32h103.elf index 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zqbGM8YWDb(HLP`qH7$bFrDPm6B6F~~FDtJbaaD1LIpEFCbSgtG;&jtn6oV-R4_@l?W^GH5WVO$MUTcE+mR%2ZI z>V=w`w^(9biBcz;X-tZM+&r&2%@`%+f|_PgOV#k@vC*#L0MAthzOLy96KqH+TY)nM zXDg-BnM?_e!~|m}(9#lXU8Yf*mznaSv!+jBh&~Vt9^L;A?g@5HAkshQ$?GlBoz`* z?xq>QhFS5|XNx0Iwsy17tFV)0$RIv)xf^$xOnNgIPK=+S@-zu~Ggnn6vkW diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/bin/openblt_olimex_stm32p103.map b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/bin/openblt_olimex_stm32p103.map index 0c39ee06..11ec51bb 100644 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/bin/openblt_olimex_stm32p103.map +++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/bin/openblt_olimex_stm32p103.map @@ -1,405 +1,437 @@ - -bin/openblt_olimex_stm32p103.elf: file format elf32-littlearm -bin/openblt_olimex_stm32p103.elf -architecture: arm, flags 0x00000112: -EXEC_P, HAS_SYMS, D_PAGED -start address 0x08000000 - -Program Header: - LOAD off 0x00008000 vaddr 0x08000000 paddr 0x08000000 align 2**15 - filesz 0x00005210 memsz 0x00005210 flags r-x - LOAD off 0x00010000 vaddr 0x20000000 paddr 0x08005210 align 2**15 - filesz 0x00000010 memsz 0x00000f7c flags rw- -private flags = 5000202: [Version5 EABI] [soft-float ABI] [has entry point] - -Sections: -Idx Name Size VMA LMA File off Algn - 0 .text 00005210 08000000 08000000 00008000 2**2 - CONTENTS, ALLOC, LOAD, READONLY, CODE - 1 .data 00000010 20000000 08005210 00010000 2**2 - CONTENTS, ALLOC, LOAD, DATA - 2 .bss 00000f6c 20000010 08005220 00010010 2**2 - ALLOC - 3 .heap 00000800 20000f80 20000f80 00010010 2**3 - CONTENTS, READONLY - 4 .stack_dummy 00000800 20000f80 20000f80 00010810 2**3 - CONTENTS, READONLY - 5 .ARM.attributes 00000027 00000000 00000000 00011010 2**0 - CONTENTS, READONLY - 6 .comment 00000030 00000000 00000000 00011037 2**0 - CONTENTS, READONLY - 7 .debug_line 00005746 00000000 00000000 00011067 2**0 - CONTENTS, READONLY, DEBUGGING - 8 .debug_info 0000b80d 00000000 00000000 000167ad 2**0 - CONTENTS, READONLY, DEBUGGING - 9 .debug_abbrev 00002103 00000000 00000000 00021fba 2**0 - CONTENTS, READONLY, DEBUGGING - 10 .debug_aranges 00000af8 00000000 00000000 000240c0 2**3 - CONTENTS, READONLY, DEBUGGING - 11 .debug_loc 00007b66 00000000 00000000 00024bb8 2**0 - CONTENTS, READONLY, DEBUGGING - 12 .debug_ranges 00000980 00000000 00000000 0002c71e 2**0 - CONTENTS, READONLY, DEBUGGING - 13 .debug_macro 0000cff9 00000000 00000000 0002d09e 2**0 - CONTENTS, READONLY, DEBUGGING - 14 .debug_str 000401c1 00000000 00000000 0003a097 2**0 - CONTENTS, READONLY, DEBUGGING - 15 .debug_frame 00001a74 00000000 00000000 0007a258 2**2 - CONTENTS, READONLY, DEBUGGING -SYMBOL TABLE: -08000000 l d .text 00000000 .text -20000000 l d .data 00000000 .data -20000010 l d .bss 00000000 .bss -20000f80 l d .heap 00000000 .heap -20000f80 l d .stack_dummy 00000000 .stack_dummy -00000000 l d .ARM.attributes 00000000 .ARM.attributes -00000000 l d .comment 00000000 .comment -00000000 l d .debug_line 00000000 .debug_line -00000000 l d .debug_info 00000000 .debug_info -00000000 l d .debug_abbrev 00000000 .debug_abbrev -00000000 l d .debug_aranges 00000000 .debug_aranges -00000000 l d .debug_loc 00000000 .debug_loc -00000000 l d .debug_ranges 00000000 .debug_ranges -00000000 l d .debug_macro 00000000 .debug_macro -00000000 l d .debug_str 00000000 .debug_str -00000000 l d .debug_frame 00000000 .debug_frame -00000000 l df *ABS* 00000000 obj/startup_stm32f10x_md.o -00000800 l *ABS* 00000000 Stack_Size -00000800 l *ABS* 00000000 Heap_Size -080001be l .text 00000000 .flash_to_ram_loop -080001f0 l .text 00000000 .fill_zero_bss -080001ec l .text 00000000 .loop_zero_bss -00000000 l df *ABS* 00000000 crtstuff.c -0800520c l O .text 00000000 __EH_FRAME_BEGIN__ -080000ec l F .text 00000000 deregister_tm_clones -08000114 l F .text 00000000 register_tm_clones -08000144 l F .text 00000000 __do_global_dtors_aux -20000010 l .bss 00000000 completed.7922 -2000000c l O .data 00000000 __do_global_dtors_aux_fini_array_entry -08000174 l F .text 00000000 frame_dummy -20000014 l .bss 00000000 object.7927 -20000008 l O .data 00000000 __frame_dummy_init_array_entry -00000000 l df *ABS* 00000000 hooks.c -080049a0 l O .text 00000020 firmwareFilename -2000002c l O .bss 0000022c logfile -00000000 l df *ABS* 00000000 stm32f10x_gpio.c -00000000 l df *ABS* 00000000 stm32f10x_rcc.c -00000000 l df *ABS* 00000000 stm32f10x_spi.c -00000000 l df *ABS* 00000000 stm32f10x_usart.c -00000000 l df *ABS* 00000000 mmc.c -08000568 l F .text 00000012 power_off -0800057c l F .text 00000062 set_max_speed -080005e0 l F .text 0000009e send_initial_clock_train -08000680 l F .text 000000d0 power_on -08000750 l F .text 00000036 xchg_spi -08000788 l F .text 0000002a wait_ready -080007b4 l F .text 0000001a deselect -080007d0 l F .text 0000002c select -080007fc l F .text 00000084 send_cmd -08000880 l F .text 0000000e rcvr_spi_m -08000890 l F .text 00000054 rcvr_datablock -080008e4 l F .text 0000005a xmit_datablock -20000258 l O .bss 00000004 CardType -20000000 l O .data 00000001 Stat -00000000 l df *ABS* 00000000 main.c -08000ec4 l F .text 000001b4 Init -00000000 l df *ABS* 00000000 assert.c -00000000 l df *ABS* 00000000 backdoor.c -2000025c l O .bss 00000001 backdoorOpen -20000260 l O .bss 00000004 backdoorOpenTime -00000000 l df *ABS* 00000000 boot.c -00000000 l df *ABS* 00000000 com.c -20000264 l O .bss 00000040 xcpCtoReqPacket.4398 -20000001 l O .data 00000001 comActiveInterface -00000000 l df *ABS* 00000000 cop.c -00000000 l df *ABS* 00000000 file.c -0800123c l F .text 0000002e FileLibByteNibbleToChar -0800126c l F .text 00000020 FileLibByteToHexString -0800128c l F .text 00000046 FileLibLongToIntString -080012d4 l F .text 00000066 FileLibHexStringToByte -200002a4 l O .bss 00000040 loggingStr -200002e4 l O .bss 00000001 firmwareUpdateState -200002e8 l O .bss 00000008 eraseInfo -200002f0 l O .bss 00000458 fatFsObjects -20000748 l O .bss 00000184 lineParseObject -00000000 l df *ABS* 00000000 xcp.c -08001b00 l F .text 00000020 XcpComputeChecksum -08001b20 l F .text 0000000e XcpProtectResources -08001b30 l F .text 00000016 XcpSetCtoError -08001b48 l F .text 0000001e XcpCmdDisconnect -08001b68 l F .text 00000022 XcpCmdGetStatus -08001b8c l F .text 0000000a XcpCmdSynch -08001b98 l F .text 00000030 XcpCmdGetId -08001bc8 l F .text 00000018 XcpCmdSetMta -08001be0 l F .text 00000028 XcpCmdBuildCheckSum -08001c08 l F .text 0000000a XcpCmdProgramPrepare -08001c14 l F .text 00000028 XcpCmdProgramStart -08001c3c l F .text 00000052 XcpCmdConnect -08001c90 l F .text 00000040 XcpCmdUpload -08001cd0 l F .text 00000042 XcpCmdShortUpload -08001d14 l F .text 00000046 XcpCmdProgramMax -08001d5c l F .text 00000068 XcpCmdProgram -08001dc4 l F .text 00000030 XcpCmdProgramClear -08001df4 l F .text 0000001a XcpCmdProgramReset -08001e10 l F .text 0000000a XcpTransmitPacket -08004b9c l O .text 00000008 xcpStationId -200008cc l O .bss 0000004c xcpInfo -00000000 l df *ABS* 00000000 can.c -08001f54 l F .text 00000060 CanGetSpeedConfig -08004bcc l O .text 00000024 canTiming -00000000 l df *ABS* 00000000 cpu.c -00000000 l df *ABS* 00000000 flash.c -08002268 l F .text 00000022 FlashUnlock -0800228c l F .text 00000012 FlashLock -080022a0 l F .text 00000050 FlashGetSector -080022f0 l F .text 000000b6 FlashWriteBlock -080023a8 l F .text 00000042 FlashGetSectorBaseAddr -080023ec l F .text 00000042 FlashGetSectorSize -08002430 l F .text 000000b0 FlashEraseSectors -080024e0 l F .text 00000026 FlashInitBlock -08002508 l F .text 0000004e FlashSwitchBlock -08002558 l F .text 00000082 FlashAddToBlock -08004bf0 l O .text 0000009c flashLayout -20000918 l O .bss 00000204 bootBlockInfo -20000b1c l O .bss 00000204 blockInfo -00000000 l df *ABS* 00000000 nvm.c -00000000 l df *ABS* 00000000 timer.c -20000d20 l O .bss 00000004 millisecond_counter -00000000 l df *ABS* 00000000 uart.c -0800283c l F .text 00000026 UartReceiveByte -08002864 l F .text 00000040 UartTransmitByte -20000d24 l O .bss 00000001 xcpCtoRxInProgress.4416 -20000d28 l O .bss 00000004 xcpCtoRxStartTime.4417 -20000d2c l O .bss 00000041 xcpCtoReqPacket.4414 -20000d70 l O .bss 00000001 xcpCtoRxLength.4415 -00000000 l df *ABS* 00000000 cpu_comp.c -00000000 l df *ABS* 00000000 ff.c -08002a14 l F .text 0000000a ld_word -08002a20 l F .text 00000016 ld_dword -08002a38 l F .text 00000008 st_word -08002a40 l F .text 00000014 st_dword -08002a54 l F .text 00000012 mem_cpy -08002a68 l F .text 0000000c mem_set -08002a74 l F .text 0000001e mem_cmp -08002a94 l F .text 00000010 chk_chr -08002aa4 l F .text 00000016 clust2sect -08002abc l F .text 00000024 ld_clust -08002ae0 l F .text 00000024 st_clust -08002b04 l F .text 0000008e pick_lfn -08002b94 l F .text 00000074 put_lfn -08002c08 l F .text 000000a6 gen_numname -08002cb0 l F .text 0000001c sum_sfn -08002ccc l F .text 0000004e get_ldnumber -08002d1c l F .text 00000034 validate -08002d50 l F .text 00000062 sync_window -08002db4 l F .text 0000003c move_window -08002df0 l F .text 00000066 check_fs -08002e58 l F .text 000002d4 find_volume -0800312c l F .text 000000ce get_fat -080031fc l F .text 000000b0 dir_sdi -080032ac l F .text 0000010c put_fat -080033b8 l F .text 000000ce create_chain -08003488 l F .text 00000094 remove_chain -0800351c l F .text 00000122 dir_next -08003640 l F .text 00000056 dir_alloc -08003698 l F .text 000000c8 dir_read -08003760 l F .text 0000005e dir_remove -080037c0 l F .text 0000022c create_name -080039ec l F .text 000000ea get_fileinfo -08003ad8 l F .text 000000a4 cmp_lfn -08003b7c l F .text 000000e6 dir_find -08003c64 l F .text 00000090 follow_path -08003cf4 l F .text 00000140 dir_register -08003e34 l F .text 00000090 sync_fs -080043d0 l F .text 00000048 putc_bfd -20000d74 l O .bss 00000200 LfnBuf -20000f74 l O .bss 00000002 Fsid -08004cc8 l O .text 00000080 ExCvt -08004d48 l O .text 0000000d LfnOfs -20000f78 l O .bss 00000004 FatFs -00000000 l df *ABS* 00000000 unicode.c -08004d58 l O .text 000000bc cvt2.4272 -08004e14 l O .text 00000100 Tbl -08004f14 l O .text 000001f2 cvt1.4271 -00000000 l df *ABS* 00000000 memset.c -00000000 l df *ABS* 00000000 c:/users/frank voorburg/mentorgraphics/sourcery_codebench_lite_for_arm_eabi/bin/../lib/gcc/arm-none-eabi/4.8.1/thumb2/crti.o -00000000 l df *ABS* 00000000 c:/users/frank voorburg/mentorgraphics/sourcery_codebench_lite_for_arm_eabi/bin/../lib/gcc/arm-none-eabi/4.8.1/thumb2/crtn.o -00000000 l df *ABS* 00000000 ctype_.c -00000000 l df *ABS* 00000000 crtstuff.c -0800520c l O .text 00000000 __FRAME_END__ -00000000 l df *ABS* 00000000 -00000800 l *ABS* 00000000 __HEAP_SIZE -08005210 l .text 00000000 __exidx_end -08005210 l .text 00000000 __exidx_start -00000800 l *ABS* 00000000 __STACK_SIZE -08001138 g F .text 00000020 ComInit -080025f8 g F .text 00000050 FlashWrite -0800021e w F .text 00000002 EXTI2_IRQHandler -20000f80 g .heap 00000800 __HeapBase -08004760 g F .text 00000054 f_gets -08001088 g F .text 00000008 AssertFailure -08000206 w F .text 00000002 DebugMon_Handler -08002184 g F .text 00000088 CanReceivePacket -08002804 g F .text 00000022 TimerUpdate -08001e4c g F .text 00000010 XcpPacketTransmitted -20000000 g .data 00000000 __data_start__ -08000244 w F .text 00000002 TIM1_CC_IRQHandler -08000520 g F .text 00000004 SPI_I2S_SendData -08001158 g F .text 00000054 ComTask -080001fc w F .text 00000002 HardFault_Handler -0800020a w F .text 00000002 SysTick_Handler -08000210 w F .text 00000002 PVD_IRQHandler -08001100 g F .text 00000020 BootInit -08001408 g F .text 00000038 FileSrecVerifyChecksum -08000524 g F .text 00000006 SPI_I2S_ReceiveData -08000208 w F .text 00000002 PendSV_Handler -080001fa w F .text 00000002 NMI_Handler -08000220 w F .text 00000002 EXTI3_IRQHandler -080010dc g F .text 00000022 BackDoorInit -08005210 g .text 00000000 __etext -0800055c g F .text 0000000c USART_GetFlagStatus -08001238 g F .text 00000002 CopService -08002a0c g F .text 00000004 CpuIrqDisable -08004844 g F .text 000000a2 ff_wtoupper -08002780 g F .text 0000000a FlashGetUserProgBaseAddress -080015a4 g F .text 0000055c FileTask -20000010 g O .data 00000000 .hidden __TMC_END__ -080027c8 g F .text 0000000e TimerReset -0800021a w F .text 00000002 EXTI0_IRQHandler -08000250 w F .text 00000002 I2C2_EV_IRQHandler -08000940 g F .text 00000182 disk_initialize -08001120 g F .text 00000018 BootTask -08002674 g F .text 00000058 FlashWriteChecksum -0800052c g F .text 0000001c SPI_CalculateCRC -08000202 w F .text 00000002 UsageFault_Handler -0800046c g F .text 00000024 RCC_APB2PeriphClockCmd -080011b0 g F .text 00000034 ComTransmitPacket -08000232 w F .text 00000002 ADC1_2_IRQHandler -080003b8 g F .text 000000aa GPIO_Init -08000ac4 g F .text 00000014 disk_status -20001780 g .heap 00000000 __HeapLimit -20000010 g .bss 00000000 __bss_start__ -08001440 g F .text 00000164 FileSrecParseLine -08000254 w F .text 00000002 SPI1_IRQHandler -08000212 w F .text 00000002 TAMPER_IRQHandler -08000c34 g F .text 0000028e disk_ioctl -08001384 g F .text 00000036 FileHandleFirmwareUpdateRequest -08000490 g F .text 00000024 RCC_APB1PeriphClockCmd -08000548 g F .text 0000000c SPI_I2S_GetFlagStatus -0800022a w F .text 00000002 DMA1_Channel4_IRQHandler -080002e4 g F .text 00000054 FileFirmwareUpdateCompletedHook -08001e38 g F .text 00000012 XcpIsConnected -08004690 g F .text 000000ce f_unlink -08004988 g F .text 00000000 _init -0800278c g F .text 00000008 NvmInit -080025dc g F .text 0000001a FlashInit -080027ac g F .text 00000008 NvmGetUserProgBaseAddress -0800025c w F .text 00000002 USART3_IRQHandler -08000214 w F .text 00000002 RTC_IRQHandler -08000230 w F .text 00000002 DMA1_Channel7_IRQHandler -080001b4 g F .text 00000030 Reset_Handler -080047b4 g F .text 00000050 f_puts -08000238 w F .text 00000002 CAN1_RX1_IRQHandler -080011ac g F .text 00000002 ComFree -08000464 g F .text 00000004 GPIO_SetBits -0800024a w F .text 00000002 TIM4_IRQHandler -00000000 w *UND* 00000000 __deregister_frame_info -20000f80 g .heap 00000000 end -0800024c w F .text 00000002 I2C1_EV_IRQHandler -080028a4 g F .text 0000002a UartInit -20000010 g .data 00000000 __data_end__ -00000000 w *UND* 00000000 _ITM_registerTMCloneTable -0800279c g F .text 00000008 NvmErase -0800022e w F .text 00000002 DMA1_Channel6_IRQHandler -20000f7c g .bss 00000000 __bss_end__ -08000248 w F .text 00000002 TIM3_IRQHandler -08000218 w F .text 00000002 RCC_IRQHandler -08000242 w F .text 00000002 TIM1_TRG_COM_IRQHandler -08000224 w F .text 00000002 DMA1_Channel1_IRQHandler -080044b8 g F .text 00000024 f_close -0800020c w F .text 00000002 Default_Handler -080001e4 w F .text 00000016 _start -08001e5c g F .text 000000f6 XcpPacketReceived -0800220c g F .text 00000008 CpuInit -0800025e w F .text 00000002 EXTI15_10_IRQHandler -080040b0 g F .text 00000172 f_read -08002734 g F .text 0000004c FlashDone -08000468 g F .text 00000004 GPIO_ResetBits -080020e0 g F .text 000000a2 CanTransmitPacket -0800023c w F .text 00000002 EXTI9_5_IRQHandler -08001e1c g F .text 0000001c XcpInit -0800133c g F .text 00000034 FileInit -00000000 w *UND* 00000000 _ITM_deregisterTMCloneTable -08000256 w F .text 00000002 SPI2_IRQHandler -08002648 g F .text 0000002a FlashErase -080048e8 g F .text 0000009e memset -08000338 g F .text 00000020 FileFirmwareUpdateErrorHook -080001fe w F .text 00000002 MemManage_Handler -08000000 g .text 000000ec __isr_vector -08001078 g F .text 00000010 main -08004418 g F .text 0000009e f_sync -08000204 w F .text 00000002 SVC_Handler -080013bc g F .text 0000004c FileSrecGetLineType -080027b4 g F .text 00000012 NvmDone -08003ec4 g F .text 0000006a f_mount -080028d0 g F .text 00000064 UartTransmitPacket -080027a4 g F .text 00000008 NvmVerifyChecksum -08002248 g F .text 00000020 CpuMemCopy -20000f80 g .heap 00000000 __end__ -0800022c w F .text 00000002 DMA1_Channel5_IRQHandler -08000222 w F .text 00000002 EXTI4_IRQHandler -08000236 w F .text 00000002 USB_LP_CAN1_RX0_IRQHandler -08000504 g F .text 0000001c SPI_Cmd -08004994 g F .text 00000000 _fini -080044dc g F .text 00000160 f_lseek -08000234 w F .text 00000002 USB_HP_CAN1_TX_IRQHandler -08001208 g F .text 00000024 ComGetActiveInterfaceMaxTxLen -08002934 g F .text 000000d8 UartReceivePacket -080002a8 g F .text 0000000a FileGetFirmwareFilenameHook -08002a10 g F .text 00000004 CpuIrqEnable -08000228 w F .text 00000002 DMA1_Channel3_IRQHandler -20005000 g *ABS* 00000000 __StackTop -08000240 w F .text 00000002 TIM1_UP_IRQHandler -0800020e w F .text 00000002 WWDG_IRQHandler -0800463c g F .text 00000054 f_stat -08001234 g F .text 00000002 CopInit -08000246 w F .text 00000002 TIM2_IRQHandler -08001fb4 g F .text 0000012c CanInit -08002794 g F .text 00000008 NvmWrite -08002214 g F .text 00000034 CpuStartUserProgram -0800023e w F .text 00000002 TIM1_BRK_IRQHandler -08000554 g F .text 00000008 USART_SendData -0800021c w F .text 00000002 EXTI1_IRQHandler -080026cc g F .text 00000068 FlashVerifyChecksum -08001370 g F .text 00000014 FileIsIdle -08004224 g F .text 000001ac f_write -08000260 w F .text 00000002 RTCAlarm_IRQHandler -20004800 g *ABS* 00000800 __StackLimit -0800025a w F .text 00000002 USART2_IRQHandler -08003f30 g F .text 0000017e f_open -08000b74 g F .text 000000c0 disk_write -08000358 g F .text 00000060 FileFirmwareUpdateLogHook -20000004 g O .data 00000004 __ctype_ptr__ -08000252 w F .text 00000002 I2C2_ER_IRQHandler -0800122c g F .text 00000008 ComIsConnected -08000226 w F .text 00000002 DMA1_Channel2_IRQHandler -08005108 g O .text 00000101 _ctype_ -0800026c g F .text 0000003c FileIsFirmwareUpdateRequestedHook -0800023a w F .text 00000002 CAN1_SCE_IRQHandler -08000216 w F .text 00000002 FLASH_IRQHandler -080011e4 g F .text 00000024 ComGetActiveInterfaceMaxRxLen -08000200 w F .text 00000002 BusFault_Handler -08000258 w F .text 00000002 USART1_IRQHandler -08000ad8 g F .text 0000009a disk_read -08001090 g F .text 0000004c BackDoorCheck -0800024e w F .text 00000002 I2C1_ER_IRQHandler -080004b4 g F .text 0000004e SPI_Init -08004804 g F .text 00000040 ff_convert -08002828 g F .text 00000012 TimerGet -00000000 w *UND* 00000000 _Jv_RegisterClasses -080027d8 g F .text 0000002c TimerInit -00000000 w *UND* 00000000 __register_frame_info -08000262 w F .text 00000002 USBWakeUp_IRQHandler -080002b4 g F .text 00000030 FileFirmwareUpdateStartedHook - - + +bin/openblt_olimex_stm32p103.elf: file format elf32-littlearm +bin/openblt_olimex_stm32p103.elf +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x08000000 + +Program Header: +0x70000001 off 0x00014d24 vaddr 0x08004d24 paddr 0x08004d24 align 2**2 + filesz 0x00000008 memsz 0x00000008 flags r-- + LOAD off 0x00010000 vaddr 0x08000000 paddr 0x08000000 align 2**16 + filesz 0x00004d2c memsz 0x00004d2c flags r-x + LOAD off 0x00020000 vaddr 0x20000000 paddr 0x08004d2c align 2**16 + filesz 0x000001dc memsz 0x00001140 flags rw- +private flags = 5000200: [Version5 EABI] [soft-float ABI] + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00004d24 08000000 08000000 00010000 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .ARM.exidx 00000008 08004d24 08004d24 00014d24 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .data 000001dc 20000000 08004d2c 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 3 .bss 00000f64 200001dc 08004f08 000201dc 2**2 + ALLOC + 4 .heap 00000800 20001140 20001140 000201e0 2**3 + CONTENTS, READONLY + 5 .stack_dummy 00000800 20001140 20001140 000209e0 2**3 + CONTENTS, READONLY + 6 .ARM.attributes 00000029 00000000 00000000 000211e0 2**0 + CONTENTS, READONLY + 7 .comment 0000006e 00000000 00000000 00021209 2**0 + CONTENTS, READONLY + 8 .debug_line 00005597 00000000 00000000 00021277 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_info 0000b76e 00000000 00000000 0002680e 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 00001f52 00000000 00000000 00031f7c 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_aranges 00000b20 00000000 00000000 00033ed0 2**3 + CONTENTS, READONLY, DEBUGGING + 12 .debug_ranges 00000980 00000000 00000000 000349f0 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_macro 0000d480 00000000 00000000 00035370 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_str 00040b80 00000000 00000000 000427f0 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_frame 00001d00 00000000 00000000 00083370 2**2 + CONTENTS, READONLY, DEBUGGING + 16 .debug_loc 0000827a 00000000 00000000 00085070 2**0 + CONTENTS, READONLY, DEBUGGING +SYMBOL TABLE: +08000000 l d .text 00000000 .text +08004d24 l d .ARM.exidx 00000000 .ARM.exidx +20000000 l d .data 00000000 .data +200001dc l d .bss 00000000 .bss +20001140 l d .heap 00000000 .heap +20001140 l d .stack_dummy 00000000 .stack_dummy +00000000 l d .ARM.attributes 00000000 .ARM.attributes +00000000 l d .comment 00000000 .comment +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_ranges 00000000 .debug_ranges +00000000 l d .debug_macro 00000000 .debug_macro +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l df *ABS* 00000000 obj/startup_stm32f10x_md.o +00000800 l *ABS* 00000000 Stack_Size +00000800 l *ABS* 00000000 Heap_Size +080001c6 l .text 00000000 .flash_to_ram_loop +080001f8 l .text 00000000 .fill_zero_bss +080001f4 l .text 00000000 .loop_zero_bss +00000000 l df *ABS* 00000000 crtstuff.c +08004d20 l O .text 00000000 __EH_FRAME_BEGIN__ +080000ec l F .text 00000000 __do_global_dtors_aux +200001dc l .bss 00000000 completed.8603 +200001d8 l O .data 00000000 __do_global_dtors_aux_fini_array_entry +08000110 l F .text 00000000 frame_dummy +200001e0 l .bss 00000000 object.8608 +200001d4 l O .data 00000000 __frame_dummy_init_array_entry +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m/crt0.o +00000000 l df *ABS* 00000000 main.c +08000274 l F .text 00000184 Init +00000000 l df *ABS* 00000000 hooks.c +080044b0 l O .text 00000020 firmwareFilename +200001f8 l O .bss 0000022c logfile +00000000 l df *ABS* 00000000 mmc.c +08000520 l F .text 00000010 power_off +08000530 l F .text 00000060 set_max_speed +08000590 l F .text 00000088 send_initial_clock_train +08000618 l F .text 000000c8 power_on +080006e0 l F .text 00000024 xchg_spi +08000704 l F .text 00000028 wait_ready +0800072c l F .text 00000018 deselect +08000744 l F .text 0000002c select +08000770 l F .text 00000082 send_cmd +080007f4 l F .text 0000000e rcvr_spi_m +08000804 l F .text 0000004e rcvr_datablock +08000854 l F .text 0000005a xmit_datablock +20000424 l O .bss 00000004 CardType +20000000 l O .data 00000001 Stat +00000000 l df *ABS* 00000000 stm32f10x_rcc.c +00000000 l df *ABS* 00000000 stm32f10x_usart.c +00000000 l df *ABS* 00000000 stm32f10x_spi.c +00000000 l df *ABS* 00000000 stm32f10x_gpio.c +00000000 l df *ABS* 00000000 _exit.c +00000000 l df *ABS* 00000000 xcp.c +08000f64 l F .text 0000001e XcpComputeChecksum +08000f84 l F .text 0000000c XcpProtectResources +08000f90 l F .text 00000014 XcpSetCtoError +08000fa4 l F .text 0000001c XcpCmdDisconnect +08000fc0 l F .text 00000020 XcpCmdGetStatus +08000fe0 l F .text 0000000a XcpCmdSynch +08000fec l F .text 0000002c XcpCmdGetId +08001018 l F .text 00000018 XcpCmdSetMta +08001030 l F .text 00000028 XcpCmdBuildCheckSum +08001058 l F .text 0000000a XcpCmdProgramPrepare +08001064 l F .text 00000028 XcpCmdProgramStart +0800108c l F .text 00000050 XcpCmdConnect +080010dc l F .text 00000040 XcpCmdUpload +0800111c l F .text 00000040 XcpCmdShortUpload +0800115c l F .text 00000040 XcpCmdProgramMax +0800119c l F .text 0000005c XcpCmdProgram +080011f8 l F .text 00000028 XcpCmdProgramClear +08001220 l F .text 00000018 XcpCmdProgramReset +08001238 l F .text 0000000a XcpTransmitPacket +080044e0 l O .text 00000008 xcpStationId +20000428 l O .bss 0000004c xcpInfo +00000000 l df *ABS* 00000000 com.c +20000001 l O .data 00000001 comActiveInterface +20000474 l O .bss 00000040 xcpCtoReqPacket.4506 +00000000 l df *ABS* 00000000 backdoor.c +200004b4 l O .bss 00000001 backdoorOpen +200004b8 l O .bss 00000004 backdoorOpenTime +00000000 l df *ABS* 00000000 boot.c +00000000 l df *ABS* 00000000 cop.c +00000000 l df *ABS* 00000000 file.c +080014dc l F .text 0000003c FileLibLongToIntString +08001518 l F .text 0000002a FileLibByteNibbleToChar +08001544 l F .text 00000020 FileLibByteToHexString +08001564 l F .text 00000058 FileLibHexStringToByte +200004bc l O .bss 00000040 loggingStr +200004fc l O .bss 00000001 firmwareUpdateState +20000500 l O .bss 00000008 eraseInfo +20000508 l O .bss 00000458 fatFsObjects +20000960 l O .bss 00000184 lineParseObject +00000000 l df *ABS* 00000000 assert.c +00000000 l df *ABS* 00000000 uart.c +08001c1c l F .text 00000020 UartReceiveByte +08001c3c l F .text 00000034 UartTransmitByte +20000ae4 l O .bss 00000004 xcpCtoRxStartTime.4525 +20000ae8 l O .bss 00000041 xcpCtoReqPacket.4522 +20000b29 l O .bss 00000001 xcpCtoRxLength.4523 +20000b2a l O .bss 00000001 xcpCtoRxInProgress.4524 +00000000 l df *ABS* 00000000 nvm.c +00000000 l df *ABS* 00000000 cpu.c +00000000 l df *ABS* 00000000 flash.c +08001e20 l F .text 0000001c FlashUnlock +08001e3c l F .text 00000010 FlashLock +08001e4c l F .text 00000048 FlashGetSector +08001e94 l F .text 000000a4 FlashWriteBlock +08001f38 l F .text 00000038 FlashGetSectorBaseAddr +08001f70 l F .text 00000038 FlashGetSectorSize +08001fa8 l F .text 000000a4 FlashEraseSectors +0800204c l F .text 00000026 FlashInitBlock +08002074 l F .text 00000040 FlashSwitchBlock +080020b4 l F .text 0000007a FlashAddToBlock +080046d4 l O .text 0000009c flashLayout +20000b2c l O .bss 00000204 bootBlockInfo +20000d30 l O .bss 00000204 blockInfo +00000000 l df *ABS* 00000000 can.c +080022bc l F .text 00000058 CanGetSpeedConfig +08004798 l O .text 00000024 canTiming +00000000 l df *ABS* 00000000 timer.c +20000f34 l O .bss 00000004 millisecond_counter +00000000 l df *ABS* 00000000 cpu_comp.c +00000000 l df *ABS* 00000000 ff.c +0800258c l F .text 0000000a ld_word +08002598 l F .text 00000016 ld_dword +080025b0 l F .text 00000008 st_word +080025b8 l F .text 00000014 st_dword +080025cc l F .text 00000012 mem_cpy +080025e0 l F .text 0000000a mem_set +080025ec l F .text 0000001e mem_cmp +0800260c l F .text 00000010 chk_chr +0800261c l F .text 00000018 clust2sect +08002634 l F .text 00000024 ld_clust +08002658 l F .text 00000024 st_clust +0800267c l F .text 0000008c pick_lfn +08002708 l F .text 00000070 put_lfn +08002778 l F .text 000000a0 gen_numname +08002818 l F .text 0000001c sum_sfn +08002834 l F .text 00000052 get_ldnumber +08002888 l F .text 00000034 validate +080028bc l F .text 00000054 sync_window +08002910 l F .text 00000034 move_window +08002944 l F .text 00000060 check_fs +080029a4 l F .text 000002d4 find_volume +08002c78 l F .text 000000d0 get_fat +08002d48 l F .text 000000b2 dir_sdi +08002dfc l F .text 0000010c put_fat +08002f08 l F .text 000000ce create_chain +08002fd8 l F .text 0000007c remove_chain +08003054 l F .text 00000126 dir_next +0800317c l F .text 0000004c dir_alloc +080031c8 l F .text 000000c4 dir_read +0800328c l F .text 00000050 dir_remove +080032dc l F .text 00000228 create_name +08003504 l F .text 000000e2 get_fileinfo +080035e8 l F .text 000000ac cmp_lfn +08003694 l F .text 000000e8 dir_find +0800377c l F .text 0000008c follow_path +08003808 l F .text 0000013c dir_register +08003944 l F .text 0000008c sync_fs +08003eb0 l F .text 0000004a putc_bfd +20000f38 l O .bss 00000200 LfnBuf +20001138 l O .bss 00000002 Fsid +080047d0 l O .text 00000080 ExCvt +08004850 l O .text 0000000d LfnOfs +2000113c l O .bss 00000004 FatFs +00000000 l df *ABS* 00000000 unicode.c +08004860 l O .text 000000bc cvt2.4380 +0800491c l O .text 00000100 Tbl +08004a1c l O .text 000001f2 cvt1.4379 +00000000 l df *ABS* 00000000 exit.c +00000000 l df *ABS* 00000000 init.c +00000000 l df *ABS* 00000000 locale.c +08004414 l F .text 00000018 __get_current_locale +00000000 l df *ABS* 00000000 mbtowc_r.c +00000000 l df *ABS* 00000000 memset.c +00000000 l df *ABS* 00000000 wctomb_r.c +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crti.o +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o +00000000 l df *ABS* 00000000 impure.c +20000004 l O .data 00000060 impure_data +00000000 l df *ABS* 00000000 ctype_.c +00000000 l df *ABS* 00000000 crtstuff.c +08004d20 l O .text 00000000 __FRAME_END__ +00000000 l df *ABS* 00000000 +200001d8 l .data 00000000 __init_array_end +200001d4 l .data 00000000 __preinit_array_end +200001d4 l .data 00000000 __init_array_start +200001d4 l .data 00000000 __preinit_array_start +08001360 g F .text 00000020 ComInit +08002148 g F .text 0000005c FlashWrite +08000226 w F .text 00000002 EXTI2_IRQHandler +20001140 g .heap 00000800 __HeapBase +0800422c g F .text 00000054 f_gets +08001c14 g F .text 00000008 AssertFailure +0800020e w F .text 00000002 DebugMon_Handler +080024b0 g F .text 00000074 CanReceivePacket +00000800 g *ABS* 00000000 __HEAP_SIZE +08002558 g F .text 0000001c TimerUpdate +08001270 g F .text 00000010 XcpPacketTransmitted +20000000 g .data 00000000 __data_start__ +0800024c w F .text 00000002 TIM1_CC_IRQHandler +08000e84 g F .text 00000004 SPI_I2S_SendData +08001380 g F .text 00000038 ComTask +08000204 w F .text 00000002 HardFault_Handler +08000212 w F .text 00000002 SysTick_Handler +08000218 w F .text 00000002 PVD_IRQHandler +0800149c g F .text 00000020 BootInit +0800167c g F .text 0000003a FileSrecVerifyChecksum +08000e88 g F .text 00000006 SPI_I2S_ReceiveData +08000210 w F .text 00000002 PendSV_Handler +0800442c g F .text 00000014 __locale_ctype_ptr +08000202 w F .text 00000002 NMI_Handler +08004d2c g .ARM.exidx 00000000 __exidx_end +08000228 w F .text 00000002 EXTI3_IRQHandler +0800147c g F .text 00000020 BackDoorInit +08004d2c g .ARM.exidx 00000000 __etext +08000e0c g F .text 0000000e USART_GetFlagStatus +080014d8 g F .text 00000002 CopService +08002584 g F .text 00000004 CpuIrqDisable +0800430c g F .text 00000094 ff_wtoupper +080022b4 g F .text 00000008 FlashGetUserProgBaseAddress +08001804 g F .text 00000410 FileTask +08002524 g F .text 0000000c TimerReset +08000222 w F .text 00000002 EXTI0_IRQHandler +08000258 w F .text 00000002 I2C2_EV_IRQHandler +080008b0 g F .text 00000160 disk_initialize +080014bc g F .text 00000018 BootTask +080021d4 g F .text 00000050 FlashWriteChecksum +08000e90 g F .text 0000001c SPI_CalculateCRC +0800020a w F .text 00000002 UsageFault_Handler +08000dcc g F .text 0000001c RCC_APB2PeriphClockCmd +080013bc g F .text 0000002c ComTransmitPacket +0800023a w F .text 00000002 ADC1_2_IRQHandler +08000ebc g F .text 0000009a GPIO_Init +08000a10 g F .text 00000014 disk_status +20001940 g .heap 00000000 __HeapLimit +200001dc g .bss 00000000 __bss_start__ +080016b8 g F .text 0000014c FileSrecParseLine +0800025c w F .text 00000002 SPI1_IRQHandler +0800021a w F .text 00000002 TAMPER_IRQHandler +08000b58 g F .text 00000274 disk_ioctl +080015fc g F .text 00000030 FileHandleFirmwareUpdateRequest +08000de8 g F .text 0000001c RCC_APB1PeriphClockCmd +08004d24 g .text 00000000 __exidx_start +08004c10 g O .text 00000004 _global_impure_ptr +080043c8 g F .text 0000004c __libc_init_array +08000eac g F .text 0000000e SPI_I2S_GetFlagStatus +08000232 w F .text 00000002 DMA1_Channel4_IRQHandler +08000148 g F .text 00000000 _mainCRTStartup +08000478 g F .text 00000044 FileFirmwareUpdateCompletedHook +08001260 g F .text 00000010 XcpIsConnected +08004170 g F .text 000000bc f_unlink +08004490 g F .text 00000000 _init +08001d88 g F .text 00000008 NvmInit +08002130 g F .text 00000018 FlashInit +08001da8 g F .text 00000008 NvmGetUserProgBaseAddress +08000264 w F .text 00000002 USART3_IRQHandler +00000000 w *UND* 00000000 __libc_fini_array +0800021c w F .text 00000002 RTC_IRQHandler +08000238 w F .text 00000002 DMA1_Channel7_IRQHandler +080001bc g F .text 00000030 Reset_Handler +08004280 g F .text 00000050 f_puts +08000240 w F .text 00000002 CAN1_RX1_IRQHandler +080013b8 g F .text 00000002 ComFree +08000f58 g F .text 00000004 GPIO_SetBits +08000252 w F .text 00000002 TIM4_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stderr +00000000 w *UND* 00000000 __deregister_frame_info +20001140 g .heap 00000000 end +08000254 w F .text 00000002 I2C1_EV_IRQHandler +08001c70 g F .text 00000028 UartInit +200001dc g .data 00000000 __data_end__ +08001d98 g F .text 00000008 NvmErase +08000236 w F .text 00000002 DMA1_Channel6_IRQHandler +20001140 g .bss 00000000 __bss_end__ +00000800 g *ABS* 00000000 __STACK_SIZE +08000250 w F .text 00000002 TIM3_IRQHandler +08000220 w F .text 00000002 RCC_IRQHandler +0800024a w F .text 00000002 TIM1_TRG_COM_IRQHandler +00000000 w *UND* 00000000 __call_exitprocs +0800022c w F .text 00000002 DMA1_Channel1_IRQHandler +08003f98 g F .text 00000024 f_close +08000214 w F .text 00000002 Default_Handler +08000148 g F .text 00000000 _start +08001280 g F .text 000000e0 XcpPacketReceived +08001dc4 g F .text 00000008 CpuInit +08000266 w F .text 00000002 EXTI15_10_IRQHandler +08003ba0 g F .text 0000016c f_read +08002274 g F .text 00000040 FlashDone +00000000 w *UND* 00000000 software_init_hook +08000f5c g F .text 00000004 GPIO_ResetBits +0800241c g F .text 00000094 CanTransmitPacket +08000244 w F .text 00000002 EXTI9_5_IRQHandler +08001244 g F .text 0000001c XcpInit +080015bc g F .text 0000002c FileInit +0800025e w F .text 00000002 SPI2_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stdin +080021a4 g F .text 0000002e FlashErase +08004464 g F .text 00000010 memset +080004bc g F .text 00000018 FileFirmwareUpdateErrorHook +08000206 w F .text 00000002 MemManage_Handler +08000000 g .text 000000ec __isr_vector +080003f8 g F .text 00000010 main +08003efc g F .text 0000009c f_sync +0800020c w F .text 00000002 SVC_Handler +0800162c g F .text 00000050 FileSrecGetLineType +08004474 g F .text 0000001a __ascii_wctomb +08001db0 g F .text 00000014 NvmDone +080039d0 g F .text 00000058 f_mount +08001c98 g F .text 00000050 UartTransmitPacket +08001da0 g F .text 00000008 NvmVerifyChecksum +00000000 w *UND* 00000000 hardware_init_hook +08001e00 g F .text 00000020 CpuMemCopy +20001140 g .heap 00000000 __end__ +08000234 w F .text 00000002 DMA1_Channel5_IRQHandler +0800022a w F .text 00000002 EXTI4_IRQHandler +0800023e w F .text 00000002 USB_LP_CAN1_RX0_IRQHandler +08000e68 g F .text 0000001c SPI_Cmd +0800449c g F .text 00000000 _fini +08003fbc g F .text 00000168 f_lseek +0800023c w F .text 00000002 USB_HP_CAN1_TX_IRQHandler +0800140c g F .text 00000024 ComGetActiveInterfaceMaxTxLen +00000000 w *UND* 00000000 atexit +08001ce8 g F .text 000000a0 UartReceivePacket +08000448 g F .text 00000008 FileGetFirmwareFilenameHook +08002588 g F .text 00000004 CpuIrqEnable +08000230 w F .text 00000002 DMA1_Channel3_IRQHandler +20005000 g .bss 00000000 __StackTop +20000064 g O .data 00000004 _impure_ptr +08000248 w F .text 00000002 TIM1_UP_IRQHandler +08000216 w F .text 00000002 WWDG_IRQHandler +08004440 g F .text 00000024 __ascii_mbtowc +08004124 g F .text 0000004c f_stat +080014d4 g F .text 00000002 CopInit +0800024e w F .text 00000002 TIM2_IRQHandler +08002314 g F .text 00000108 CanInit +08001d90 g F .text 00000008 NvmWrite +08001dcc g F .text 00000034 CpuStartUserProgram +08000246 w F .text 00000002 TIM1_BRK_IRQHandler +08000e04 g F .text 00000008 USART_SendData +20005000 g *ABS* 00000000 __stack +08000224 w F .text 00000002 EXTI1_IRQHandler +08002224 g F .text 00000050 FlashVerifyChecksum +080015e8 g F .text 00000014 FileIsIdle +08003d0c g F .text 000001a4 f_write +08000268 w F .text 00000002 RTCAlarm_IRQHandler +20004800 g *ABS* 00000800 __StackLimit +08000262 w F .text 00000002 USART2_IRQHandler +08003a28 g F .text 00000178 f_open +08000aac g F .text 000000ac disk_write +080043a0 g F .text 00000028 exit +080004d4 g F .text 0000004c FileFirmwareUpdateLogHook +0800025a w F .text 00000002 I2C2_ER_IRQHandler +08001430 g F .text 00000008 ComIsConnected +0800022e w F .text 00000002 DMA1_Channel2_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stdout +08004c1e g O .text 00000101 _ctype_ +08000408 g F .text 00000040 FileIsFirmwareUpdateRequestedHook +08000242 w F .text 00000002 CAN1_SCE_IRQHandler +0800021e w F .text 00000002 FLASH_IRQHandler +08000f60 w F .text 00000002 _exit +080013e8 g F .text 00000024 ComGetActiveInterfaceMaxRxLen +08000208 w F .text 00000002 BusFault_Handler +08000260 w F .text 00000002 USART1_IRQHandler +08000a24 g F .text 00000088 disk_read +08001438 g F .text 00000044 BackDoorCheck +08000256 w F .text 00000002 I2C1_ER_IRQHandler +08000e1c g F .text 0000004c SPI_Init +080042d0 g F .text 0000003c ff_convert +08002574 g F .text 00000010 TimerGet +00000000 w *UND* 00000000 _Jv_RegisterClasses +08002530 g F .text 00000028 TimerInit +00000000 w *UND* 00000000 __register_frame_info +20000068 g O .data 0000016c __global_locale +0800026a w F .text 00000002 USBWakeUp_IRQHandler +08000450 g F .text 00000028 FileFirmwareUpdateStartedHook + + diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/bin/openblt_olimex_stm32p103.srec b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/bin/openblt_olimex_stm32p103.srec index b8b5498b..190429c2 100644 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/bin/openblt_olimex_stm32p103.srec +++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/bin/openblt_olimex_stm32p103.srec @@ -1,1316 +1,1268 @@ S024000062696E2F6F70656E626C745F6F6C696D65785F73746D3332703130332E737265639B -S3150800000000500020B5010008FB010008FD010008AA -S31508000010FF010008010200080302000800000000B2 -S3150800002000000000000000000000000005020008B3 -S315080000300702000800000000090200080B02000879 -S315080000400F02000811020008130200081502000832 -S3150800005017020008190200081B0200081D02000802 -S315080000601F020008210200082302000825020008D2 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+S31508004EACFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000F6 +S31508004EBC010041534349490000000000000000006E +S31508004ECC00000000000000000000000000000000C8 +S31508004EDC000041534349490000000000000000004F +S31508004EEC00000000000000000000000000000000A8 +S31108004EFC0000000011010008ED0000088D S70508000000F2 diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/build.bat b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/build.bat deleted file mode 100644 index 6cdb041e..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/build.bat +++ /dev/null @@ -1,2 +0,0 @@ -@echo off -cs-make --directory=../ all diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/clean.bat b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/clean.bat deleted file mode 100644 index 025aaea0..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/clean.bat +++ /dev/null @@ -1,2 +0,0 @@ -@echo off -cs-make --directory=../ clean diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/debug.bat b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/debug.bat deleted file mode 100644 index 377cdde6..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/debug.bat +++ /dev/null @@ -1 +0,0 @@ -"C:\Program Files (x86)\OpenOCD\0.4.0\bin\openocd.exe" -f debug.cfg \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/debug.cfg b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/debug.cfg deleted file mode 100644 index 741aecbd..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/debug.cfg +++ /dev/null @@ -1,15 +0,0 @@ -### -# Description: starts the OpenOCD GDB server (localhost:3333) -# once started use arm-elf-insight .elf to start the debug session -# Usage: openocd.exe" -f debug.cfg -### -source [find interface/olimex-arm-usb-tiny-h.cfg] -source [find board/olimex_stm32_h103.cfg] - -jtag_khz 1000 -init -reset -halt - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/flash.bat b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/flash.bat deleted file mode 100644 index 876b4a5d..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/flash.bat +++ /dev/null @@ -1 +0,0 @@ -"C:\Program Files (x86)\OpenOCD\0.4.0\bin\openocd.exe" -f flash.cfg \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/flash.cfg b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/flash.cfg deleted file mode 100644 index 9e5fad03..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/cmd/flash.cfg +++ /dev/null @@ -1,21 +0,0 @@ -### -# Description: mass erases and flashes the binary with OpenOCD -# Usage: openocd.exe" -f flash.cfg -### - -source [find interface/olimex-arm-usb-tiny-h.cfg] -source [find board/olimex_stm32_h103.cfg] - -jtag_khz 1000 - -init -reset -sleep 500 -halt -stm32x mass_erase 0 -flash write_image ..\\bin\\openblt_olimex_stm32p103.elf -#flash write_image erase ..\\bin\\openblt_olimex_stm32p103.elf -reset run -shutdown - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/ide/DemoBoot.project b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/ide/DemoBoot.project deleted file mode 100644 index 63a6eba8..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/ide/DemoBoot.project +++ /dev/null @@ -1,288 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - break main -continue - - - - - - - make clean - make - - - - None - $(WorkspacePath)/.. - - - - - - - - - - - - - - - - - - - - - - - make clean - make - - - - None - $(WorkspacePath) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/ide/DemoBoot.workspace b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/ide/DemoBoot.workspace deleted file mode 100644 index 7957a1d7..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/ide/DemoBoot.workspace +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/ide/readme.txt b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/ide/readme.txt deleted file mode 100644 index 8a340a19..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/ide/readme.txt +++ /dev/null @@ -1,4 +0,0 @@ -Integrated Development Environment ----------------------------------- -Codelite was used as the editor during the development of this software program. This directory contains the Codelite -workspace and project files. Codelite is a cross platform open source C/C++ IDE, available at http://www.codelite.org/. \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/lib/newlib/_exit.c b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/lib/newlib/_exit.c new file mode 100644 index 00000000..4ae9532c --- /dev/null +++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/lib/newlib/_exit.c @@ -0,0 +1,38 @@ +// ---------------------------------------------------------------------------- + +#include + +// ---------------------------------------------------------------------------- + +// Forward declaration + +void +_exit(int code); + +// ---------------------------------------------------------------------------- + +// We just enter an infinite loop, to be used as landmark when halting +// the debugger. +// +// It can be redefined in the application, if more functionality +// is required. + +void +__attribute__((weak)) +_exit(int code __attribute__((unused))) +{ + // TODO: write on trace + while (1) + ; +} + +// ---------------------------------------------------------------------------- + +void +__attribute__((weak,noreturn)) +abort(void) +{ + _exit(1); +} + +// ---------------------------------------------------------------------------- diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/makefile b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/makefile index c6f55e83..5370ec11 100644 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/makefile +++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/makefile @@ -34,7 +34,7 @@ PROJ_NAME=openblt_olimex_stm32p103 #|--------------------------------------------------------------------------------------| #| Configure tool path | #|--------------------------------------------------------------------------------------| -TOOL_PATH= +TOOL_PATH=/opt/gcc-arm-none-eabi-5_4-2016q3/bin/ #|--------------------------------------------------------------------------------------| @@ -68,7 +68,7 @@ PROJ_FILES += ../../../Source/third_party/fatfs/src/option/unicode.c #|--------------------------------------------------------------------------------------| #| Toolchain binaries | #|--------------------------------------------------------------------------------------| -RM = cs-rm +RM = rm CC = $(TOOL_PATH)arm-none-eabi-gcc LN = $(TOOL_PATH)arm-none-eabi-gcc OC = $(TOOL_PATH)arm-none-eabi-objcopy @@ -111,7 +111,7 @@ AFLAGS = $(CFLAGS) LFLAGS = $(STDFLAGS) $(OPTFLAGS) LFLAGS += -Wl,--defsym=__HEAP_SIZE=$(HEAP_SIZE) -Wl,--defsym=__STACK_SIZE=$(STACK_SIZE) LFLAGS += -Wl,-script="stm32f103rb_flash.ld" -Wl,-Map=$(BIN_PATH)/$(PROJ_NAME).map -LFLAGS += -Wl,--gc-sections $(LIB_PATH) +LFLAGS += -specs=nano.specs -Wl,--gc-sections $(LIB_PATH) OFLAGS = -O srec ODFLAGS = -x SZFLAGS = -B -d diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/bin/demoprog_olimex_stm32p103.elf b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/bin/demoprog_olimex_stm32p103.elf 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..\obj\lib\spl\src\stm32f10x_usart.o -LOAD ..\obj\lib\spl\src\stm32f10x_wwdg.o -LOAD ..\obj\lib\system_stm32f10x.o -LOAD ..\obj\lib\usb_fs_device\src\usb_core.o -LOAD ..\obj\lib\usb_fs_device\src\usb_init.o -LOAD ..\obj\lib\usb_fs_device\src\usb_int.o -LOAD ..\obj\lib\usb_fs_device\src\usb_mem.o -LOAD ..\obj\lib\usb_fs_device\src\usb_regs.o -LOAD ..\obj\lib\usb_fs_device\src\usb_sil.o -LOAD ..\obj\main.o -LOAD ..\obj\startup_stm32f10x_md.o -LOAD ..\obj\usb_desc.o -LOAD ..\obj\usb_endp.o -LOAD ..\obj\usb_istr.o -LOAD ..\obj\usb_prop.o -LOAD ..\obj\usb_pwr.o -LOAD ..\obj\~#\~#\~#\source\armcm3_stm32f1\can.o -LOAD ..\obj\~#\~#\~#\source\armcm3_stm32f1\cpu.o -LOAD ..\obj\~#\~#\~#\source\armcm3_stm32f1\flash.o -LOAD ..\obj\~#\~#\~#\source\armcm3_stm32f1\gcc\cpu_comp.o -LOAD ..\obj\~#\~#\~#\source\armcm3_stm32f1\nvm.o -LOAD ..\obj\~#\~#\~#\source\armcm3_stm32f1\timer.o -LOAD ..\obj\~#\~#\~#\source\armcm3_stm32f1\uart.o -LOAD ..\obj\~#\~#\~#\source\armcm3_stm32f1\usb.o -LOAD ..\obj\~#\~#\~#\source\assert.o -LOAD ..\obj\~#\~#\~#\source\backdoor.o -LOAD ..\obj\~#\~#\~#\source\boot.o -LOAD ..\obj\~#\~#\~#\source\com.o -LOAD ..\obj\~#\~#\~#\source\cop.o -LOAD ..\obj\~#\~#\~#\source\file.o -LOAD ..\obj\~#\~#\~#\source\net.o -LOAD ..\obj\~#\~#\~#\source\third_party\fatfs\src\ff.o -LOAD ..\obj\~#\~#\~#\source\third_party\fatfs\src\option\unicode.o -LOAD ..\obj\~#\~#\~#\source\xcp.o -START GROUP -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m\libgcc.a -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libc_n.a -END GROUP -START GROUP -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m\libgcc.a -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libc_n.a -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libnosys_s.a -END GROUP -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtend.o -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o -OUTPUT(..\bin\openblt_olimexino_stm32.elf elf32-littlearm) - -.ARM.attributes - 0x00000000 0x29 - .ARM.attributes - 0x00000000 0x1d c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crti.o - .ARM.attributes - 0x0000001d 0x2d c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtbegin.o - .ARM.attributes - 0x0000004a 0x1b c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m/crt0.o - .ARM.attributes - 0x00000065 0x33 ..\obj\hooks.o - .ARM.attributes - 0x00000098 0x33 ..\obj\led.o - .ARM.attributes - 0x000000cb 0x33 ..\obj\lib\fatfs\mmc.o - .ARM.attributes - 0x000000fe 0x33 ..\obj\lib\spl\src\stm32f10x_gpio.o - .ARM.attributes - 0x00000131 0x33 ..\obj\lib\spl\src\stm32f10x_rcc.o - .ARM.attributes - 0x00000164 0x33 ..\obj\lib\spl\src\stm32f10x_spi.o - .ARM.attributes - 0x00000197 0x33 ..\obj\lib\usb_fs_device\src\usb_core.o - .ARM.attributes - 0x000001ca 0x33 ..\obj\lib\usb_fs_device\src\usb_init.o - .ARM.attributes - 0x000001fd 0x33 ..\obj\lib\usb_fs_device\src\usb_int.o - .ARM.attributes - 0x00000230 0x33 ..\obj\lib\usb_fs_device\src\usb_mem.o - .ARM.attributes - 0x00000263 0x33 ..\obj\lib\usb_fs_device\src\usb_regs.o - .ARM.attributes - 0x00000296 0x33 ..\obj\lib\usb_fs_device\src\usb_sil.o - .ARM.attributes - 0x000002c9 0x33 ..\obj\main.o - .ARM.attributes - 0x000002fc 0x1b ..\obj\startup_stm32f10x_md.o - .ARM.attributes - 0x00000317 0x33 ..\obj\usb_desc.o - .ARM.attributes - 0x0000034a 0x33 ..\obj\usb_endp.o - .ARM.attributes - 0x0000037d 0x33 ..\obj\usb_istr.o - .ARM.attributes - 0x000003b0 0x33 ..\obj\usb_prop.o - .ARM.attributes - 0x000003e3 0x33 ..\obj\usb_pwr.o - .ARM.attributes - 0x00000416 0x33 ..\obj\~#\~#\~#\source\armcm3_stm32f1\cpu.o - .ARM.attributes - 0x00000449 0x33 ..\obj\~#\~#\~#\source\armcm3_stm32f1\flash.o - .ARM.attributes - 0x0000047c 0x33 ..\obj\~#\~#\~#\source\armcm3_stm32f1\gcc\cpu_comp.o - .ARM.attributes - 0x000004af 0x33 ..\obj\~#\~#\~#\source\armcm3_stm32f1\nvm.o - .ARM.attributes - 0x000004e2 0x33 ..\obj\~#\~#\~#\source\armcm3_stm32f1\timer.o - .ARM.attributes - 0x00000515 0x33 ..\obj\~#\~#\~#\source\armcm3_stm32f1\usb.o - .ARM.attributes - 0x00000548 0x33 ..\obj\~#\~#\~#\source\assert.o - .ARM.attributes - 0x0000057b 0x33 ..\obj\~#\~#\~#\source\backdoor.o - .ARM.attributes - 0x000005ae 0x33 ..\obj\~#\~#\~#\source\boot.o - .ARM.attributes - 0x000005e1 0x33 ..\obj\~#\~#\~#\source\com.o - .ARM.attributes - 0x00000614 0x33 ..\obj\~#\~#\~#\source\cop.o - .ARM.attributes - 0x00000647 0x33 ..\obj\~#\~#\~#\source\file.o - .ARM.attributes - 0x0000067a 0x33 ..\obj\~#\~#\~#\source\third_party\fatfs\src\ff.o - .ARM.attributes - 0x000006ad 0x33 ..\obj\~#\~#\~#\source\third_party\fatfs\src\option\unicode.o - .ARM.attributes - 0x000006e0 0x33 ..\obj\~#\~#\~#\source\xcp.o - .ARM.attributes - 0x00000713 0x2d c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-ctype_.o) - .ARM.attributes - 0x00000740 0x2d c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-exit.o) - .ARM.attributes - 0x0000076d 0x2d c:/program files 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(x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libnosys_s.a(_exit.o) + +bin/openblt_olimexino_stm32.elf: file format elf32-littlearm +bin/openblt_olimexino_stm32.elf +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x08000000 + +Program Header: +0x70000001 off 0x00015c8c vaddr 0x08005c8c paddr 0x08005c8c align 2**2 + filesz 0x00000008 memsz 0x00000008 flags r-- + LOAD off 0x00010000 vaddr 0x08000000 paddr 0x08000000 align 2**16 + filesz 0x00005c94 memsz 0x00005c94 flags r-x + LOAD off 0x00020000 vaddr 0x20000000 paddr 0x08005c94 align 2**16 + filesz 0x000002c8 memsz 0x000013b2 flags rw- +private flags = 5000200: [Version5 EABI] [soft-float ABI] + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00005c8c 08000000 08000000 00010000 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .ARM.exidx 00000008 08005c8c 08005c8c 00015c8c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .data 000002c8 20000000 08005c94 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 3 .bss 000010ea 200002c8 08005f5c 000202c8 2**2 + ALLOC + 4 .heap 00000800 200013b8 200013b8 000202c8 2**3 + CONTENTS, READONLY + 5 .stack_dummy 00000800 200013b8 200013b8 00020ac8 2**3 + CONTENTS, READONLY + 6 .ARM.attributes 00000029 00000000 00000000 000212c8 2**0 + CONTENTS, READONLY + 7 .comment 0000006e 00000000 00000000 000212f1 2**0 + CONTENTS, READONLY + 8 .debug_line 0000a150 00000000 00000000 0002135f 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_info 0000ffc5 00000000 00000000 0002b4af 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 0000353f 00000000 00000000 0003b474 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_aranges 00000cd0 00000000 00000000 0003e9b8 2**3 + CONTENTS, READONLY, DEBUGGING + 12 .debug_macro 00011f8c 00000000 00000000 0003f688 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_str 0005a2dc 00000000 00000000 00051614 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_ranges 00001788 00000000 00000000 000ab8f0 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_frame 00002224 00000000 00000000 000ad078 2**2 + CONTENTS, READONLY, DEBUGGING + 16 .debug_loc 0000beb9 00000000 00000000 000af29c 2**0 + CONTENTS, READONLY, DEBUGGING +SYMBOL TABLE: +08000000 l d .text 00000000 .text +08005c8c l d .ARM.exidx 00000000 .ARM.exidx +20000000 l d .data 00000000 .data +200002c8 l d .bss 00000000 .bss +200013b8 l d .heap 00000000 .heap +200013b8 l d .stack_dummy 00000000 .stack_dummy +00000000 l d .ARM.attributes 00000000 .ARM.attributes +00000000 l d .comment 00000000 .comment +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_macro 00000000 .debug_macro +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .debug_ranges 00000000 .debug_ranges +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l df *ABS* 00000000 obj/startup_stm32f10x_md.o +00000800 l *ABS* 00000000 Stack_Size +00000800 l *ABS* 00000000 Heap_Size +080001c6 l .text 00000000 .flash_to_ram_loop +080001f8 l .text 00000000 .fill_zero_bss +080001f4 l .text 00000000 .loop_zero_bss +00000000 l df *ABS* 00000000 crtstuff.c +08005c88 l O .text 00000000 __EH_FRAME_BEGIN__ +080000ec l F .text 00000000 __do_global_dtors_aux +200002c8 l .bss 00000000 completed.8603 +200002c4 l O .data 00000000 __do_global_dtors_aux_fini_array_entry +08000110 l F .text 00000000 frame_dummy +200002cc l .bss 00000000 object.8608 +200002c0 l O .data 00000000 __frame_dummy_init_array_entry +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m/crt0.o +00000000 l df *ABS* 00000000 usb_endp.c +00000000 l df *ABS* 00000000 usb_prop.c +00000000 l df *ABS* 00000000 main.c +00000000 l df *ABS* 00000000 hooks.c +0800545c l O .text 0000001f firmwareFilename +200002e4 l O .bss 0000022c logfile +20000510 l O .bss 00000001 initialized.7005 +00000000 l df *ABS* 00000000 led.c +20000511 l O .bss 00000001 ledOn.7009 +20000512 l O .bss 00000002 ledBlinkIntervalMs +20000514 l O .bss 00000004 nextBlinkEvent.7010 +00000000 l df *ABS* 00000000 usb_istr.c +00000000 l df *ABS* 00000000 mmc.c +080007bc l F .text 00000024 xchg_spi +080007e0 l F .text 00000026 wait_ready +08000808 l F .text 00000034 select +0800083c l F .text 0000009c send_cmd +080008d8 l F .text 00000058 rcvr_datablock +08000930 l F .text 0000005a xmit_datablock +2000051c l O .bss 00000004 CardType +200000ec l O .data 00000001 Stat +00000000 l df *ABS* 00000000 _exit.c +00000000 l df *ABS* 00000000 stm32f10x_rcc.c +00000000 l df *ABS* 00000000 stm32f10x_spi.c +00000000 l df *ABS* 00000000 stm32f10x_gpio.c +00000000 l df *ABS* 00000000 usb_mem.c +00000000 l df *ABS* 00000000 usb_init.c +00000000 l df *ABS* 00000000 usb_sil.c +00000000 l df *ABS* 00000000 usb_regs.c +00000000 l df *ABS* 00000000 usb_core.c +080015b8 l F .text 000000b0 DataStageIn +00000000 l df *ABS* 00000000 usb_int.c +00000000 l df *ABS* 00000000 usb_pwr.c +00000000 l df *ABS* 00000000 xcp.c +0800548c l O .text 00000008 xcpStationId +20000528 l O .bss 0000004c xcpInfo +00000000 l df *ABS* 00000000 com.c +200000ed l O .data 00000001 comActiveInterface +08005494 l O .text 00000008 CSWTCH.10 +20000574 l O .bss 0000003f xcpCtoReqPacket.4507 +00000000 l df *ABS* 00000000 backdoor.c +200005b3 l O .bss 00000001 backdoorOpen +200005b4 l O .bss 00000004 backdoorOpenTime +00000000 l df *ABS* 00000000 boot.c +00000000 l df *ABS* 00000000 cop.c +00000000 l df *ABS* 00000000 file.c +0800242c l F .text 0000002e FileLibByteNibbleToChar +0800245c l F .text 00000020 FileLibByteToHexString +0800247c l F .text 0000004e FileLibHexStringToByte +200005b8 l O .bss 00000040 loggingStr +200005f8 l O .bss 00000001 firmwareUpdateState +200005fc l O .bss 00000008 eraseInfo +20000604 l O .bss 00000458 fatFsObjects +20000a5c l O .bss 00000184 lineParseObject +00000000 l df *ABS* 00000000 assert.c +00000000 l df *ABS* 00000000 nvm.c +00000000 l df *ABS* 00000000 usb.c +08002bc4 l F .text 00000032 IntToUnicode +08002bf8 l F .text 00000054 UsbFifoMgrWrite +08002c4c l F .text 00000050 UsbFifoMgrRead +20000be0 l O .bss 00000040 xcpCtoReqPacket.7479 +20000c20 l O .bss 00000001 xcpCtoRxInProgress.7481 +20000c24 l O .bss 00000040 USB_Tx_Buffer.7500 +20000c64 l O .bss 00000004 fifoCtrlFree +20000c68 l O .bss 00000030 fifoCtrl +20000c98 l O .bss 00000041 fifoPipeBulkOUT +20000cdc l O .bss 00000040 USB_Rx_Buffer.7511 +20000d1c l O .bss 00000041 fifoPipeBulkIN +20000d5d l O .bss 00000001 xcpCtoRxLength.7480 +00000000 l df *ABS* 00000000 cpu.c +00000000 l df *ABS* 00000000 flash.c +08002f60 l F .text 00000048 FlashGetSector +08002fa8 l F .text 000000b0 FlashWriteBlock +08003058 l F .text 00000050 FlashSwitchBlock +080030a8 l F .text 00000096 FlashAddToBlock +08005688 l O .text 0000009c flashLayout +20000d60 l O .bss 00000204 bootBlockInfo +20000f64 l O .bss 00000204 blockInfo +00000000 l df *ABS* 00000000 timer.c +20001168 l O .bss 00000004 millisecond_counter +00000000 l df *ABS* 00000000 cpu_comp.c +00000000 l df *ABS* 00000000 ff.c +0800344c l F .text 00000048 get_ldnumber +08003494 l F .text 00000040 validate +080034d4 l F .text 00000012 mem_cpy.part.0 +080034e8 l F .text 0000004a sync_window.part.3 +08003534 l F .text 0000003e move_window +08003574 l F .text 000000c0 sync_fs +08003634 l F .text 00000074 check_fs +080036a8 l F .text 00000334 find_volume +080039dc l F .text 000000c8 get_fat.isra.5 +08003aa4 l F .text 000000aa dir_sdi +08003b50 l F .text 0000012a put_fat.part.6 +08003c7c l F .text 000000ce create_chain +08003d4c l F .text 00000130 dir_next +08003e7c l F .text 00000050 dir_remove +08003ecc l F .text 0000019c dir_find +08004068 l F .text 000002d0 dir_register +08004338 l F .text 0000008a remove_chain +080043c4 l F .text 000002d0 follow_path +08004694 l F .text 000000ec get_fileinfo.part.8 +08004780 l F .text 00000124 dir_read.constprop.9 +08004d80 l F .text 0000004a putc_bfd +2000116c l O .bss 00000200 LfnBuf +2000136c l O .bss 00000002 Fsid +08005738 l O .text 00000080 ExCvt +080057b8 l O .text 0000000d LfnOfs +20001370 l O .bss 00000004 FatFs +00000000 l df *ABS* 00000000 unicode.c +080057c8 l O .text 000000bc cvt2.4380 +08005884 l O .text 00000100 Tbl +08005984 l O .text 000001f2 cvt1.4379 +00000000 l df *ABS* 00000000 exit.c +00000000 l df *ABS* 00000000 init.c +00000000 l df *ABS* 00000000 locale.c +08005318 l F .text 00000018 __get_current_locale +00000000 l df *ABS* 00000000 mbtowc_r.c +00000000 l df *ABS* 00000000 memset.c +00000000 l df *ABS* 00000000 wctomb_r.c +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crti.o +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o +00000000 l df *ABS* 00000000 usb_desc.c +00000000 l df *ABS* 00000000 impure.c +200000f0 l O .data 00000060 impure_data +00000000 l df *ABS* 00000000 ctype_.c +00000000 l df *ABS* 00000000 crtstuff.c +08005c88 l O .text 00000000 __FRAME_END__ +00000000 l df *ABS* 00000000 +200002c4 l .data 00000000 __init_array_end +200002c0 l .data 00000000 __preinit_array_end +200002c0 l .data 00000000 __init_array_start +200002c0 l .data 00000000 __preinit_array_start +080022f0 g F .text 00000018 ComInit +200013ae g O .bss 00000002 SaveRState +08001330 g F .text 00000026 SetEPRxValid +0800315c g F .text 00000054 FlashWrite +08000226 w F .text 00000002 EXTI2_IRQHandler +200013b8 g .heap 00000800 __HeapBase +08005118 g F .text 00000052 f_gets +080014cc g F .text 00000004 GetEPRxCount +08002b94 g F .text 00000008 AssertFailure +0800027c g F .text 00000014 SOF_Callback +0800020e w F .text 00000002 DebugMon_Handler +00000800 g *ABS* 00000000 __HEAP_SIZE +0800340c g F .text 0000001c TimerUpdate +08001ff4 g F .text 00000010 XcpPacketTransmitted +20000000 g .data 00000000 __data_start__ +080017cc g F .text 00000098 Standard_SetEndPointFeature +080011f4 g F .text 00000038 USB_Init +0800024c w F .text 00000002 TIM1_CC_IRQHandler +080014d0 g F .text 0000000a ByteSwap +08001098 g F .text 00000004 SPI_I2S_SendData +08002308 g F .text 00000028 ComTask +08000204 w F .text 00000002 HardFault_Handler +08001358 g F .text 0000001e ClearEPDoubleBuff +08001488 g F .text 00000004 GetEPTxAddr +08000212 w F .text 00000002 SysTick_Handler +08000218 w F .text 00000002 PVD_IRQHandler +0800030c g F .text 00000024 Bulk_Init +080023e4 g F .text 00000022 BootInit +0800257c g F .text 0000003a FileSrecVerifyChecksum +0800109c g F .text 00000006 SPI_I2S_ReceiveData +08000210 w F .text 00000002 PendSV_Handler +08005330 g F .text 00000014 __locale_ctype_ptr +08000202 w F .text 00000002 NMI_Handler +08005c94 g .ARM.exidx 00000000 __exidx_end +08000228 w F .text 00000002 EXTI3_IRQHandler +080023c4 g F .text 00000020 BackDoorInit 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00000002 Bulk_Status_In +080018c4 g F .text 0000037c Setup0_Process +08002408 g F .text 0000001a BootTask +08003304 g F .text 00000048 FlashWriteChecksum +080010a4 g F .text 0000001a SPI_CalculateCRC +0800020a w F .text 00000002 UsageFault_Handler +08001004 g F .text 0000001c RCC_APB2PeriphClockCmd +08002334 g F .text 00000024 ComTransmitPacket +0800023a w F .text 00000002 ADC1_2_IRQHandler +08002eb8 g F .text 00000040 UsbGetSerialNum +080010cc g F .text 000000cc GPIO_Init +08000c5c g F .text 00000014 disk_status +20001bb8 g .heap 00000000 __HeapLimit +200002c8 g .bss 00000000 __bss_start__ +080025b8 g F .text 0000015c FileSrecParseLine +080053ec g O .text 00000020 Bulk_ConfigDescriptor +0800025c w F .text 00000002 SPI1_IRQHandler +080002b4 g F .text 00000002 Bulk_Status_Out +20001374 g O .bss 00000002 wIstr +0800021a w F .text 00000002 TAMPER_IRQHandler +08000de0 g F .text 00000220 disk_ioctl +2000137c g O .bss 00000004 pProperty +08001668 g F .text 0000003c Standard_SetConfiguration +08002510 g F .text 00000024 FileHandleFirmwareUpdateRequest +08001020 g F .text 0000001c RCC_APB1PeriphClockCmd +08005c8c g .text 00000000 __exidx_start +200000b4 g O .data 0000001c pEpInt_IN +08005b78 g O .text 00000004 _global_impure_ptr +080052cc g F .text 0000004c __libc_init_array +080010c0 g F .text 0000000c SPI_I2S_GetFlagStatus +08000232 w F .text 00000002 DMA1_Channel4_IRQHandler +08000148 g F .text 00000000 _mainCRTStartup +0800146c g F .text 0000001c GetEPDblBuf0Addr +20001380 g O .bss 00000001 EPindex +08000678 g F .text 0000002c FileFirmwareUpdateCompletedHook +20000024 g O .data 00000030 Device_Property +0800540c g O .text 0000001a Bulk_StringVendor +08001fe4 g F .text 00000010 XcpIsConnected +08005064 g F .text 000000b4 f_unlink +08005394 g F .text 00000000 _init +0800152c g F .text 0000008c Standard_GetStatus +08002b9c g F .text 00000004 NvmInit +080053ac g O .text 00000012 Bulk_DeviceDescriptor +08003158 g F .text 00000004 FlashInit +08002bac g F .text 00000004 NvmGetUserProgBaseAddress +08001448 g F .text 00000020 SetEPDblBuf1Addr +20000088 g O .data 00000028 String_Descriptor +0800137c g F .text 00000024 ClearDTOG_RX +08000264 w F .text 00000002 USART3_IRQHandler +00000000 w *UND* 00000000 __libc_fini_array +0800021c w F .text 00000002 RTC_IRQHandler +08001e04 g F .text 00000002 NOP_Process +08000238 w F .text 00000002 DMA1_Channel7_IRQHandler +080001bc g F .text 00000030 Reset_Handler +0800516c g F .text 0000004e f_puts +08000240 w F .text 00000002 CAN1_RX1_IRQHandler +080016a4 g F .text 00000050 Standard_SetInterface +080013e0 g F .text 00000044 SetEPRxCount +0800122c g F .text 00000024 USB_SIL_Init +08002330 g F .text 00000004 ComFree +080011a4 g F .text 00000004 GPIO_SetBits +08001f98 g F .text 00000030 PowerOn +08000252 w F .text 00000002 TIM4_IRQHandler +20000000 g O .data 0000001c Bulk_StringSerial +08001e08 g F .text 00000190 CTR_LP +00000000 w *UND* 00000000 __sf_fake_stderr +00000000 w *UND* 00000000 __deregister_frame_info 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.text 00000002 Default_Handler +08000148 g F .text 00000000 _start +08002004 g F .text 000002ec XcpPacketReceived +08002ef8 g F .text 00000004 CpuInit +200013a0 g O .bss 00000004 pUser_Standard_Requests +08001424 g F .text 00000020 SetEPDblBuf0Addr +080006e4 g F .text 0000000c LedBlinkInit +08000266 w F .text 00000002 EXTI15_10_IRQHandler +08004a8c g F .text 0000015a f_read +0800339c g F .text 00000034 FlashDone +08001dc4 g F .text 00000040 SetDeviceAddress +080011d4 g F .text 00000020 PMAToUserBufferCopy +00000000 w *UND* 00000000 software_init_hook +080006f0 g F .text 0000004c LedBlinkTask +08001468 g F .text 00000004 SetEPRxAddr +080011a8 g F .text 00000004 GPIO_ResetBits +20000518 g O .bss 00000001 bIntPackSOF +08002d08 g F .text 00000060 UsbTransmitPacket +08001d1c g F .text 000000a8 In0_Process +08000588 g F .text 00000060 UsbConnectHook +080002b8 g F .text 00000040 Bulk_Data_Setup +08000244 w F .text 00000002 EXTI9_5_IRQHandler +200013ac g O .bss 00000002 StatusInfo +200013a4 g O .bss 00000004 pInformation +08001284 g F .text 0000001c SetEPType +08001fc8 g F .text 0000001c XcpInit +080024cc g F .text 00000034 FileInit +08002c9c g F .text 00000064 UsbInit +0800025e w F .text 00000002 SPI2_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stdin +08002d00 g F .text 00000006 UsbFree +080031b0 g F .text 00000154 FlashErase +08005368 g F .text 00000010 memset +080006a4 g F .text 00000014 FileFirmwareUpdateErrorHook +0800073c g F .text 0000000c LedBlinkExit +08000206 w F .text 00000002 MemManage_Handler +08000000 g .text 000000ec __isr_vector +08000424 g F .text 00000164 main +08004dcc g F .text 000000b0 f_sync +08001504 g F .text 00000028 Standard_GetInterface +0800020c w F .text 00000002 SVC_Handler +08002534 g F .text 00000046 FileSrecGetLineType +08005378 g F .text 0000001a __ascii_wctomb +08002bb0 g F .text 00000012 NvmDone +080048a4 g F .text 00000064 f_mount +08002ba8 g F .text 00000004 NvmVerifyChecksum +00000000 w *UND* 00000000 hardware_init_hook +08002f3c g F .text 00000022 CpuMemCopy +200013b8 g .heap 00000000 __end__ +08000234 w F .text 00000002 DMA1_Channel5_IRQHandler +0800022a w F .text 00000002 EXTI4_IRQHandler +0800023e w F .text 00000002 USB_LP_CAN1_RX0_IRQHandler +0800107c g F .text 0000001a SPI_Cmd +20000078 g O .data 00000008 Bulk_Descriptor +080053a0 g F .text 00000000 _fini +08004ea0 g F .text 00000162 f_lseek +0800023c w F .text 00000002 USB_HP_CAN1_TX_IRQHandler +080002f8 g F .text 00000004 Bulk_NoData_Setup +08002358 g F .text 0000001c ComGetActiveInterfaceMaxTxLen +00000000 w *UND* 00000000 atexit +08000648 g F .text 00000008 FileGetFirmwareFilenameHook +080003dc g F .text 0000000c Bulk_GetDeviceDescriptor +08003448 g F .text 00000004 CpuIrqEnable +08000230 w F .text 00000002 DMA1_Channel3_IRQHandler +20005000 g .bss 00000000 __StackTop +20000150 g O .data 00000004 _impure_ptr +08000248 w F .text 00000002 TIM1_UP_IRQHandler +08001864 g F .text 0000001c Standard_GetDescriptorData +080053c4 g O .text 00000026 Bulk_StringProduct +08001c40 g F .text 000000dc Out0_Process +08000216 w F .text 00000002 WWDG_IRQHandler +08005344 g F .text 00000024 __ascii_mbtowc +080053c0 g O .text 00000004 Bulk_StringLangID +08005004 g F .text 00000060 f_stat +08002424 g F .text 00000004 CopInit +08000274 g F .text 00000004 EP1_IN_Callback +0800024e w F .text 00000002 TIM2_IRQHandler +08001308 g F .text 00000026 SetEPTxValid +080003f4 g F .text 00000020 Bulk_GetStringDescriptor +08002ba0 g F .text 00000004 NvmWrite +08002efc g F .text 00000040 CpuStartUserProgram +08000246 w F .text 00000002 TIM1_BRK_IRQHandler +08002d68 g F .text 00000078 UsbReceivePacket +20005000 g *ABS* 00000000 __stack +08000224 w F .text 00000002 EXTI1_IRQHandler +0800334c g F .text 00000050 FlashVerifyChecksum +20000520 g O .bss 00000001 Data_Mul_MaxPacketSize +08002500 g F .text 00000010 FileIsIdle +08000414 g F .text 0000000c Bulk_GetBulkDescriptor +08001880 g F .text 00000044 Post0_Process +08004be8 g F .text 00000198 f_write +08000268 w F .text 00000002 RTCAlarm_IRQHandler +08000748 g F .text 00000074 USB_Istr +080012d4 g F .text 00000032 SetEPRxStatus +20004800 g *ABS* 00000800 __StackLimit +08000262 w F .text 00000002 USART2_IRQHandler +08004908 g F .text 00000184 f_open +08000d14 g F .text 000000cc disk_write +080052a4 g F .text 00000028 exit +080013a0 g F .text 00000024 ClearDTOG_TX +080006b8 g F .text 0000002c FileFirmwareUpdateLogHook +08001444 g F .text 00000004 SetEPTxAddr +0800025a w F .text 00000002 I2C2_ER_IRQHandler +08002378 g F .text 00000004 ComIsConnected +0800022e w F .text 00000002 DMA1_Channel2_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stdout +08005b86 g O .text 00000101 _ctype_ +0800060c g F .text 0000003c FileIsFirmwareUpdateRequestedHook +2000001c g O .data 00000008 Config_Descriptor +08001378 g F .text 00000004 Clear_Status_Out +08000242 w F .text 00000002 CAN1_SCE_IRQHandler +0800021e w F .text 00000002 FLASH_IRQHandler +08001000 w F .text 00000002 _exit +080011ac g F .text 00000026 UserToPMABufferCopy +08002374 g F .text 00000004 ComGetActiveInterfaceMaxRxLen +08000208 w F .text 00000002 BusFault_Handler +08000260 w F .text 00000002 USART1_IRQHandler +08000600 g F .text 00000006 CopInitHook +08000c70 g F .text 000000a4 disk_read +0800237c g F .text 00000048 BackDoorCheck +08000290 g F .text 00000018 Bulk_SetConfiguration +08000256 w F .text 00000002 I2C1_ER_IRQHandler +0800103c g F .text 00000040 SPI_Init +20000524 g O .bss 00000004 bDeviceState +080051bc g F .text 00000044 ff_convert +08003428 g F .text 0000001c TimerGet +200000b0 g O .data 00000002 Device_Table +08002de0 g F .text 0000008c UsbTransmitPipeBulkIN +00000000 w *UND* 00000000 _Jv_RegisterClasses +080003e8 g F .text 0000000c Bulk_GetConfigDescriptor +08005428 g O .text 0000002c Bulk_StringInterface +08001198 g F .text 0000000c GPIO_ReadInputDataBit +080033d8 g F .text 00000028 TimerInit +00000000 w *UND* 00000000 __register_frame_info +08000608 g F .text 00000004 CopServiceHook +200013a8 g O .bss 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0x20 - 0x0 - 0xFFFFFFFF - - - FSMC - Flexible static memory controller - FSMC - 0xA0000000 - - 0x0 - 0x1000 - registers - - - FSMC - FSMC global interrupt - 48 - - - - BCR1 - BCR1 - SRAM/NOR-Flash chip-select control register - 1 - 0x0 - 0x20 - read-write - 0x000030D0 - - - CBURSTRW - CBURSTRW - 19 - 1 - - - ASYNCWAIT - ASYNCWAIT - 15 - 1 - - - EXTMOD - EXTMOD - 14 - 1 - - - WAITEN - WAITEN - 13 - 1 - - - WREN - WREN - 12 - 1 - - - WAITCFG - WAITCFG - 11 - 1 - - - WAITPOL - WAITPOL - 9 - 1 - - - BURSTEN - BURSTEN - 8 - 1 - - - FACCEN - FACCEN - 6 - 1 - - - MWID - MWID - 4 - 2 - - - MTYP - MTYP - 2 - 2 - - - MUXEN - MUXEN - 1 - 1 - - - MBKEN - MBKEN - 0 - 1 - - - - - BTR1 - BTR1 - SRAM/NOR-Flash chip-select timing register - 1 - 0x4 - 0x20 - read-write - 0xFFFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - BUSTURN - BUSTURN - 16 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - BCR2 - BCR2 - SRAM/NOR-Flash chip-select control register - 2 - 0x8 - 0x20 - read-write - 0x000030D0 - - - CBURSTRW - CBURSTRW - 19 - 1 - - - ASYNCWAIT - ASYNCWAIT - 15 - 1 - - - EXTMOD - EXTMOD - 14 - 1 - - - WAITEN - WAITEN - 13 - 1 - - - WREN - WREN - 12 - 1 - - - WAITCFG - WAITCFG - 11 - 1 - - - WRAPMOD - WRAPMOD - 10 - 1 - - - WAITPOL - WAITPOL - 9 - 1 - - - BURSTEN - BURSTEN - 8 - 1 - - - FACCEN - FACCEN - 6 - 1 - - - MWID - MWID - 4 - 2 - - - MTYP - MTYP - 2 - 2 - - - MUXEN - MUXEN - 1 - 1 - - - MBKEN - MBKEN - 0 - 1 - - - - - BTR2 - BTR2 - SRAM/NOR-Flash chip-select timing register - 2 - 0xC - 0x20 - read-write - 0xFFFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - BUSTURN - BUSTURN - 16 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - BCR3 - BCR3 - SRAM/NOR-Flash chip-select control register - 3 - 0x10 - 0x20 - read-write - 0x000030D0 - - - CBURSTRW - CBURSTRW - 19 - 1 - - - ASYNCWAIT - ASYNCWAIT - 15 - 1 - - - EXTMOD - EXTMOD - 14 - 1 - - - WAITEN - WAITEN - 13 - 1 - - - WREN - WREN - 12 - 1 - - - WAITCFG - WAITCFG - 11 - 1 - - - WRAPMOD - WRAPMOD - 10 - 1 - - - WAITPOL - WAITPOL - 9 - 1 - - - BURSTEN - BURSTEN - 8 - 1 - - - FACCEN - FACCEN - 6 - 1 - - - MWID - MWID - 4 - 2 - - - MTYP - MTYP - 2 - 2 - - - MUXEN - MUXEN - 1 - 1 - - - MBKEN - MBKEN - 0 - 1 - - - - - BTR3 - BTR3 - SRAM/NOR-Flash chip-select timing register - 3 - 0x14 - 0x20 - read-write - 0xFFFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - BUSTURN - BUSTURN - 16 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - BCR4 - BCR4 - SRAM/NOR-Flash chip-select control register - 4 - 0x18 - 0x20 - read-write - 0x000030D0 - - - CBURSTRW - CBURSTRW - 19 - 1 - - - ASYNCWAIT - ASYNCWAIT - 15 - 1 - - - EXTMOD - EXTMOD - 14 - 1 - - - WAITEN - WAITEN - 13 - 1 - - - WREN - WREN - 12 - 1 - - - WAITCFG - WAITCFG - 11 - 1 - - - WRAPMOD - WRAPMOD - 10 - 1 - - - WAITPOL - WAITPOL - 9 - 1 - - - BURSTEN - BURSTEN - 8 - 1 - - - FACCEN - FACCEN - 6 - 1 - - - MWID - MWID - 4 - 2 - - - MTYP - MTYP - 2 - 2 - - - MUXEN - MUXEN - 1 - 1 - - - MBKEN - MBKEN - 0 - 1 - - - - - BTR4 - BTR4 - SRAM/NOR-Flash chip-select timing register - 4 - 0x1C - 0x20 - read-write - 0xFFFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - BUSTURN - BUSTURN - 16 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - PCR2 - PCR2 - PC Card/NAND Flash control register - 2 - 0x60 - 0x20 - read-write - 0x00000018 - - - ECCPS - ECCPS - 17 - 3 - - - TAR - TAR - 13 - 4 - - - TCLR - TCLR - 9 - 4 - - - ECCEN - ECCEN - 6 - 1 - - - PWID - PWID - 4 - 2 - - - PTYP - PTYP - 3 - 1 - - - PBKEN - PBKEN - 2 - 1 - - - PWAITEN - PWAITEN - 1 - 1 - - - - - SR2 - SR2 - FIFO status and interrupt register - 2 - 0x64 - 0x20 - 0x00000040 - - - FEMPT - FEMPT - 6 - 1 - read-only - - - IFEN - IFEN - 5 - 1 - read-write - - - ILEN - ILEN - 4 - 1 - read-write - - - IREN - IREN - 3 - 1 - read-write - - - IFS - IFS - 2 - 1 - read-write - - - ILS - ILS - 1 - 1 - read-write - - - IRS - IRS - 0 - 1 - read-write - - - - - PMEM2 - PMEM2 - Common memory space timing register - 2 - 0x68 - 0x20 - read-write - 0xFCFCFCFC - - - MEMHIZx - MEMHIZx - 24 - 8 - - - MEMHOLDx - MEMHOLDx - 16 - 8 - - - MEMWAITx - MEMWAITx - 8 - 8 - - - MEMSETx - MEMSETx - 0 - 8 - - - - - PATT2 - PATT2 - Attribute memory space timing register - 2 - 0x6C - 0x20 - read-write - 0xFCFCFCFC - - - ATTHIZx - Attribute memory x databus HiZ - time - 24 - 8 - - - ATTHOLDx - Attribute memory x hold - time - 16 - 8 - - - ATTWAITx - Attribute memory x wait - time - 8 - 8 - - - ATTSETx - Attribute memory x setup - time - 0 - 8 - - - - - ECCR2 - ECCR2 - ECC result register 2 - 0x74 - 0x20 - read-only - 0x00000000 - - - ECCx - ECC result - 0 - 32 - - - - - PCR3 - PCR3 - PC Card/NAND Flash control register - 3 - 0x80 - 0x20 - read-write - 0x00000018 - - - ECCPS - ECCPS - 17 - 3 - - - TAR - TAR - 13 - 4 - - - TCLR - TCLR - 9 - 4 - - - ECCEN - ECCEN - 6 - 1 - - - PWID - PWID - 4 - 2 - - - PTYP - PTYP - 3 - 1 - - - PBKEN - PBKEN - 2 - 1 - - - PWAITEN - PWAITEN - 1 - 1 - - - - - SR3 - SR3 - FIFO status and interrupt register - 3 - 0x84 - 0x20 - 0x00000040 - - - FEMPT - FEMPT - 6 - 1 - read-only - - - IFEN - IFEN - 5 - 1 - read-write - - - ILEN - ILEN - 4 - 1 - read-write - - - IREN - IREN - 3 - 1 - read-write - - - IFS - IFS - 2 - 1 - read-write - - - ILS - ILS - 1 - 1 - read-write - - - IRS - IRS - 0 - 1 - read-write - - - - - PMEM3 - PMEM3 - Common memory space timing register - 3 - 0x88 - 0x20 - read-write - 0xFCFCFCFC - - - MEMHIZx - MEMHIZx - 24 - 8 - - - MEMHOLDx - MEMHOLDx - 16 - 8 - - - MEMWAITx - MEMWAITx - 8 - 8 - - - MEMSETx - MEMSETx - 0 - 8 - - - - - PATT3 - PATT3 - Attribute memory space timing register - 3 - 0x8C - 0x20 - read-write - 0xFCFCFCFC - - - ATTHIZx - ATTHIZx - 24 - 8 - - - ATTHOLDx - ATTHOLDx - 16 - 8 - - - ATTWAITx - ATTWAITx - 8 - 8 - - - ATTSETx - ATTSETx - 0 - 8 - - - - - ECCR3 - ECCR3 - ECC result register 3 - 0x94 - 0x20 - read-only - 0x00000000 - - - ECCx - ECCx - 0 - 32 - - - - - PCR4 - PCR4 - PC Card/NAND Flash control register - 4 - 0xA0 - 0x20 - read-write - 0x00000018 - - - ECCPS - ECCPS - 17 - 3 - - - TAR - TAR - 13 - 4 - - - TCLR - TCLR - 9 - 4 - - - ECCEN - ECCEN - 6 - 1 - - - PWID - PWID - 4 - 2 - - - PTYP - PTYP - 3 - 1 - - - PBKEN - PBKEN - 2 - 1 - - - PWAITEN - PWAITEN - 1 - 1 - - - - - SR4 - SR4 - FIFO status and interrupt register - 4 - 0xA4 - 0x20 - 0x00000040 - - - FEMPT - FEMPT - 6 - 1 - read-only - - - IFEN - IFEN - 5 - 1 - read-write - - - ILEN - ILEN - 4 - 1 - read-write - - - IREN - IREN - 3 - 1 - read-write - - - IFS - IFS - 2 - 1 - read-write - - - ILS - ILS - 1 - 1 - read-write - - - IRS - IRS - 0 - 1 - read-write - - - - - PMEM4 - PMEM4 - Common memory space timing register - 4 - 0xA8 - 0x20 - read-write - 0xFCFCFCFC - - - MEMHIZx - MEMHIZx - 24 - 8 - - - MEMHOLDx - MEMHOLDx - 16 - 8 - - - MEMWAITx - MEMWAITx - 8 - 8 - - - MEMSETx - MEMSETx - 0 - 8 - - - - - PATT4 - PATT4 - Attribute memory space timing register - 4 - 0xAC - 0x20 - read-write - 0xFCFCFCFC - - - ATTHIZx - ATTHIZx - 24 - 8 - - - ATTHOLDx - ATTHOLDx - 16 - 8 - - - ATTWAITx - ATTWAITx - 8 - 8 - - - ATTSETx - ATTSETx - 0 - 8 - - - - - PIO4 - PIO4 - I/O space timing register 4 - 0xB0 - 0x20 - read-write - 0xFCFCFCFC - - - IOHIZx - IOHIZx - 24 - 8 - - - IOHOLDx - IOHOLDx - 16 - 8 - - - IOWAITx - IOWAITx - 8 - 8 - - - IOSETx - IOSETx - 0 - 8 - - - - - BWTR1 - BWTR1 - SRAM/NOR-Flash write timing registers - 1 - 0x104 - 0x20 - read-write - 0x0FFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - BWTR2 - BWTR2 - SRAM/NOR-Flash write timing registers - 2 - 0x10C - 0x20 - read-write - 0x0FFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - BWTR3 - BWTR3 - SRAM/NOR-Flash write timing registers - 3 - 0x114 - 0x20 - read-write - 0x0FFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - BWTR4 - BWTR4 - SRAM/NOR-Flash write timing registers - 4 - 0x11C - 0x20 - read-write - 0x0FFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - - - PWR - Power control - PWR - 0x40007000 - - 0x0 - 0x400 - registers - - - PVD - PVD through EXTI line detection - interrupt - 1 - - - - CR - CR - Power control register - (PWR_CR) - 0x0 - 0x20 - read-write - 0x00000000 - - - LPDS - Low Power Deep Sleep - 0 - 1 - - - PDDS - Power Down Deep Sleep - 1 - 1 - - - CWUF - Clear Wake-up Flag - 2 - 1 - - - CSBF - Clear STANDBY Flag - 3 - 1 - - - PVDE - Power Voltage Detector - Enable - 4 - 1 - - - PLS - PVD Level Selection - 5 - 3 - - - DBP - Disable Backup Domain write - protection - 8 - 1 - - - - - CSR - CSR - Power control register - (PWR_CR) - 0x4 - 0x20 - 0x00000000 - - - WUF - Wake-Up Flag - 0 - 1 - read-only - - - SBF - STANDBY Flag - 1 - 1 - read-only - - - PVDO - PVD Output - 2 - 1 - read-only - - - EWUP - Enable WKUP pin - 8 - 1 - read-write - - - - - - - RCC - Reset and clock control - RCC - 0x40021000 - - 0x0 - 0x400 - registers - - - RCC - RCC global interrupt - 5 - - - - CR - CR - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HSION - Internal High Speed clock - enable - 0 - 1 - read-write - - - HSIRDY - Internal High Speed clock ready - flag - 1 - 1 - read-only - - - HSITRIM - Internal High Speed clock - trimming - 3 - 5 - read-write - - - HSICAL - Internal High Speed clock - Calibration - 8 - 8 - read-only - - - HSEON - External High Speed clock - enable - 16 - 1 - read-write - - - HSERDY - External High Speed clock ready - flag - 17 - 1 - read-only - - - HSEBYP - External High Speed clock - Bypass - 18 - 1 - read-write - - - CSSON - Clock Security System - enable - 19 - 1 - read-write - - - PLLON - PLL enable - 24 - 1 - read-write - - - PLLRDY - PLL clock ready flag - 25 - 1 - read-only - - - - - CFGR - CFGR - Clock configuration register - (RCC_CFGR) - 0x4 - 0x20 - 0x00000000 - - - SW - System clock Switch - 0 - 2 - read-write - - - SWS - System Clock Switch Status - 2 - 2 - read-only - - - HPRE - AHB prescaler - 4 - 4 - read-write - - - PPRE1 - APB Low speed prescaler - (APB1) - 8 - 3 - read-write - - - PPRE2 - APB High speed prescaler - (APB2) - 11 - 3 - read-write - - - ADCPRE - ADC prescaler - 14 - 2 - read-write - - - PLLSRC - PLL entry clock source - 16 - 1 - read-write - - - PLLXTPRE - HSE divider for PLL entry - 17 - 1 - read-write - - - PLLMUL - PLL Multiplication Factor - 18 - 4 - read-write - - - OTGFSPRE - USB OTG FS prescaler - 22 - 1 - read-write - - - MCO - Microcontroller clock - output - 24 - 3 - read-write - - - - - CIR - CIR - Clock interrupt register - (RCC_CIR) - 0x8 - 0x20 - 0x00000000 - - - LSIRDYF - LSI Ready Interrupt flag - 0 - 1 - read-only - - - LSERDYF - LSE Ready Interrupt flag - 1 - 1 - read-only - - - HSIRDYF - HSI Ready Interrupt flag - 2 - 1 - read-only - - - HSERDYF - HSE Ready Interrupt flag - 3 - 1 - read-only - - - PLLRDYF - PLL Ready Interrupt flag - 4 - 1 - read-only - - - CSSF - Clock Security System Interrupt - flag - 7 - 1 - read-only - - - LSIRDYIE - LSI Ready Interrupt Enable - 8 - 1 - read-write - - - LSERDYIE - LSE Ready Interrupt Enable - 9 - 1 - read-write - - - HSIRDYIE - HSI Ready Interrupt Enable - 10 - 1 - read-write - - - HSERDYIE - HSE Ready Interrupt Enable - 11 - 1 - read-write - - - PLLRDYIE - PLL Ready Interrupt Enable - 12 - 1 - read-write - - - LSIRDYC - LSI Ready Interrupt Clear - 16 - 1 - write-only - - - LSERDYC - LSE Ready Interrupt Clear - 17 - 1 - write-only - - - HSIRDYC - HSI Ready Interrupt Clear - 18 - 1 - write-only - - - HSERDYC - HSE Ready Interrupt Clear - 19 - 1 - write-only - - - PLLRDYC - PLL Ready Interrupt Clear - 20 - 1 - write-only - - - CSSC - Clock security system interrupt - clear - 23 - 1 - write-only - - - - - APB2RSTR - APB2RSTR - APB2 peripheral reset register - (RCC_APB2RSTR) - 0xC - 0x20 - read-write - 0x000000000 - - - AFIORST - Alternate function I/O - reset - 0 - 1 - - - IOPARST - IO port A reset - 2 - 1 - - - IOPBRST - IO port B reset - 3 - 1 - - - IOPCRST - IO port C reset - 4 - 1 - - - IOPDRST - IO port D reset - 5 - 1 - - - IOPERST - IO port E reset - 6 - 1 - - - IOPFRST - IO port F reset - 7 - 1 - - - IOPGRST - IO port G reset - 8 - 1 - - - ADC1RST - ADC 1 interface reset - 9 - 1 - - - ADC2RST - ADC 2 interface reset - 10 - 1 - - - TIM1RST - TIM1 timer reset - 11 - 1 - - - SPI1RST - SPI 1 reset - 12 - 1 - - - TIM8RST - TIM8 timer reset - 13 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - ADC3RST - ADC 3 interface reset - 15 - 1 - - - TIM9RST - TIM9 timer reset - 19 - 1 - - - TIM10RST - TIM10 timer reset - 20 - 1 - - - TIM11RST - TIM11 timer reset - 21 - 1 - - - - - APB1RSTR - APB1RSTR - APB1 peripheral reset register - (RCC_APB1RSTR) - 0x10 - 0x20 - read-write - 0x00000000 - - - TIM2RST - Timer 2 reset - 0 - 1 - - - TIM3RST - Timer 3 reset - 1 - 1 - - - TIM4RST - Timer 4 reset - 2 - 1 - - - TIM5RST - Timer 5 reset - 3 - 1 - - - TIM6RST - Timer 6 reset - 4 - 1 - - - TIM7RST - Timer 7 reset - 5 - 1 - - - TIM12RST - Timer 12 reset - 6 - 1 - - - TIM13RST - Timer 13 reset - 7 - 1 - - - TIM14RST - Timer 14 reset - 8 - 1 - - - WWDGRST - Window watchdog reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - SPI3RST - SPI3 reset - 15 - 1 - - - USART2RST - USART 2 reset - 17 - 1 - - - USART3RST - USART 3 reset - 18 - 1 - - - UART4RST - UART 4 reset - 19 - 1 - - - UART5RST - UART 5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - USBRST - USB reset - 23 - 1 - - - CANRST - CAN reset - 25 - 1 - - - BKPRST - Backup interface reset - 27 - 1 - - - PWRRST - Power interface reset - 28 - 1 - - - DACRST - DAC interface reset - 29 - 1 - - - - - AHBENR - AHBENR - AHB Peripheral Clock enable register - (RCC_AHBENR) - 0x14 - 0x20 - read-write - 0x00000014 - - - DMA1EN - DMA1 clock enable - 0 - 1 - - - DMA2EN - DMA2 clock enable - 1 - 1 - - - SRAMEN - SRAM interface clock - enable - 2 - 1 - - - FLITFEN - FLITF clock enable - 4 - 1 - - - CRCEN - CRC clock enable - 6 - 1 - - - FSMCEN - FSMC clock enable - 8 - 1 - - - SDIOEN - SDIO clock enable - 10 - 1 - - - - - APB2ENR - APB2ENR - APB2 peripheral clock enable register - (RCC_APB2ENR) - 0x18 - 0x20 - read-write - 0x00000000 - - - AFIOEN - Alternate function I/O clock - enable - 0 - 1 - - - IOPAEN - I/O port A clock enable - 2 - 1 - - - IOPBEN - I/O port B clock enable - 3 - 1 - - - IOPCEN - I/O port C clock enable - 4 - 1 - - - IOPDEN - I/O port D clock enable - 5 - 1 - - - IOPEEN - I/O port E clock enable - 6 - 1 - - - IOPFEN - I/O port F clock enable - 7 - 1 - - - IOPGEN - I/O port G clock enable - 8 - 1 - - - ADC1EN - ADC 1 interface clock - enable - 9 - 1 - - - ADC2EN - ADC 2 interface clock - enable - 10 - 1 - - - TIM1EN - TIM1 Timer clock enable - 11 - 1 - - - SPI1EN - SPI 1 clock enable - 12 - 1 - - - TIM8EN - TIM8 Timer clock enable - 13 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - ADC3EN - ADC3 interface clock - enable - 15 - 1 - - - TIM9EN - TIM9 Timer clock enable - 19 - 1 - - - TIM10EN - TIM10 Timer clock enable - 20 - 1 - - - TIM11EN - TIM11 Timer clock enable - 21 - 1 - - - - - APB1ENR - APB1ENR - APB1 peripheral clock enable register - (RCC_APB1ENR) - 0x1C - 0x20 - read-write - 0x00000000 - - - TIM2EN - Timer 2 clock enable - 0 - 1 - - - TIM3EN - Timer 3 clock enable - 1 - 1 - - - TIM4EN - Timer 4 clock enable - 2 - 1 - - - TIM5EN - Timer 5 clock enable - 3 - 1 - - - TIM6EN - Timer 6 clock enable - 4 - 1 - - - TIM7EN - Timer 7 clock enable - 5 - 1 - - - TIM12EN - Timer 12 clock enable - 6 - 1 - - - TIM13EN - Timer 13 clock enable - 7 - 1 - - - TIM14EN - Timer 14 clock enable - 8 - 1 - - - WWDGEN - Window watchdog clock - enable - 11 - 1 - - - SPI2EN - SPI 2 clock enable - 14 - 1 - - - SPI3EN - SPI 3 clock enable - 15 - 1 - - - USART2EN - USART 2 clock enable - 17 - 1 - - - USART3EN - USART 3 clock enable - 18 - 1 - - - UART4EN - UART 4 clock enable - 19 - 1 - - - UART5EN - UART 5 clock enable - 20 - 1 - - - I2C1EN - I2C 1 clock enable - 21 - 1 - - - I2C2EN - I2C 2 clock enable - 22 - 1 - - - USBEN - USB clock enable - 23 - 1 - - - CANEN - CAN clock enable - 25 - 1 - - - BKPEN - Backup interface clock - enable - 27 - 1 - - - PWREN - Power interface clock - enable - 28 - 1 - - - DACEN - DAC interface clock enable - 29 - 1 - - - - - BDCR - BDCR - Backup domain control register - (RCC_BDCR) - 0x20 - 0x20 - 0x00000000 - - - LSEON - External Low Speed oscillator - enable - 0 - 1 - read-write - - - LSERDY - External Low Speed oscillator - ready - 1 - 1 - read-only - - - LSEBYP - External Low Speed oscillator - bypass - 2 - 1 - read-write - - - RTCSEL - RTC clock source selection - 8 - 2 - read-write - - - RTCEN - RTC clock enable - 15 - 1 - read-write - - - BDRST - Backup domain software - reset - 16 - 1 - read-write - - - - - CSR - CSR - Control/status register - (RCC_CSR) - 0x24 - 0x20 - 0x0C000000 - - - LSION - Internal low speed oscillator - enable - 0 - 1 - read-write - - - LSIRDY - Internal low speed oscillator - ready - 1 - 1 - read-only - - - RMVF - Remove reset flag - 24 - 1 - read-write - - - PINRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/PDR reset flag - 27 - 1 - read-write - - - SFTRSTF - Software reset flag - 28 - 1 - read-write - - - IWDGRSTF - Independent watchdog reset - flag - 29 - 1 - read-write - - - WWDGRSTF - Window watchdog reset flag - 30 - 1 - read-write - - - LPWRRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - - - GPIOA - General purpose I/O - GPIO - 0x40010800 - - 0x0 - 0x400 - registers - - - - CRL - CRL - Port configuration register low - (GPIOn_CRL) - 0x0 - 0x20 - read-write - 0x44444444 - - - MODE0 - Port n.0 mode bits - 0 - 2 - - - CNF0 - Port n.0 configuration - bits - 2 - 2 - - - MODE1 - Port n.1 mode bits - 4 - 2 - - - CNF1 - Port n.1 configuration - bits - 6 - 2 - - - MODE2 - Port n.2 mode bits - 8 - 2 - - - CNF2 - Port n.2 configuration - bits - 10 - 2 - - - MODE3 - Port n.3 mode bits - 12 - 2 - - - CNF3 - Port n.3 configuration - bits - 14 - 2 - - - MODE4 - Port n.4 mode bits - 16 - 2 - - - CNF4 - Port n.4 configuration - bits - 18 - 2 - - - MODE5 - Port n.5 mode bits - 20 - 2 - - - CNF5 - Port n.5 configuration - bits - 22 - 2 - - - MODE6 - Port n.6 mode bits - 24 - 2 - - - CNF6 - Port n.6 configuration - bits - 26 - 2 - - - MODE7 - Port n.7 mode bits - 28 - 2 - - - CNF7 - Port n.7 configuration - bits - 30 - 2 - - - - - CRH - CRH - Port configuration register high - (GPIOn_CRL) - 0x4 - 0x20 - read-write - 0x44444444 - - - MODE8 - Port n.8 mode bits - 0 - 2 - - - CNF8 - Port n.8 configuration - bits - 2 - 2 - - - MODE9 - Port n.9 mode bits - 4 - 2 - - - CNF9 - Port n.9 configuration - bits - 6 - 2 - - - MODE10 - Port n.10 mode bits - 8 - 2 - - - CNF10 - Port n.10 configuration - bits - 10 - 2 - - - MODE11 - Port n.11 mode bits - 12 - 2 - - - CNF11 - Port n.11 configuration - bits - 14 - 2 - - - MODE12 - Port n.12 mode bits - 16 - 2 - - - CNF12 - Port n.12 configuration - bits - 18 - 2 - - - MODE13 - Port n.13 mode bits - 20 - 2 - - - CNF13 - Port n.13 configuration - bits - 22 - 2 - - - MODE14 - Port n.14 mode bits - 24 - 2 - - - CNF14 - Port n.14 configuration - bits - 26 - 2 - - - MODE15 - Port n.15 mode bits - 28 - 2 - - - CNF15 - Port n.15 configuration - bits - 30 - 2 - - - - - IDR - IDR - Port input data register - (GPIOn_IDR) - 0x8 - 0x20 - read-only - 0x00000000 - - - IDR0 - Port input data - 0 - 1 - - - IDR1 - Port input data - 1 - 1 - - - IDR2 - Port input data - 2 - 1 - - - IDR3 - Port input data - 3 - 1 - - - IDR4 - Port input data - 4 - 1 - - - IDR5 - Port input data - 5 - 1 - - - IDR6 - Port input data - 6 - 1 - - - IDR7 - Port input data - 7 - 1 - - - IDR8 - Port input data - 8 - 1 - - - IDR9 - Port input data - 9 - 1 - - - IDR10 - Port input data - 10 - 1 - - - IDR11 - Port input data - 11 - 1 - - - IDR12 - Port input data - 12 - 1 - - - IDR13 - Port input data - 13 - 1 - - - IDR14 - Port input data - 14 - 1 - - - IDR15 - Port input data - 15 - 1 - - - - - ODR - ODR - Port output data register - (GPIOn_ODR) - 0xC - 0x20 - read-write - 0x00000000 - - - ODR0 - Port output data - 0 - 1 - - - ODR1 - Port output data - 1 - 1 - - - ODR2 - Port output data - 2 - 1 - - - ODR3 - Port output data - 3 - 1 - - - ODR4 - Port output data - 4 - 1 - - - ODR5 - Port output data - 5 - 1 - - - ODR6 - Port output data - 6 - 1 - - - ODR7 - Port output data - 7 - 1 - - - ODR8 - Port output data - 8 - 1 - - - ODR9 - Port output data - 9 - 1 - - - ODR10 - Port output data - 10 - 1 - - - ODR11 - Port output data - 11 - 1 - - - ODR12 - Port output data - 12 - 1 - - - ODR13 - Port output data - 13 - 1 - - - ODR14 - Port output data - 14 - 1 - - - ODR15 - Port output data - 15 - 1 - - - - - BSRR - BSRR - Port bit set/reset register - (GPIOn_BSRR) - 0x10 - 0x20 - write-only - 0x00000000 - - - BS0 - Set bit 0 - 0 - 1 - - - BS1 - Set bit 1 - 1 - 1 - - - BS2 - Set bit 1 - 2 - 1 - - - BS3 - Set bit 3 - 3 - 1 - - - BS4 - Set bit 4 - 4 - 1 - - - BS5 - Set bit 5 - 5 - 1 - - - BS6 - Set bit 6 - 6 - 1 - - - BS7 - Set bit 7 - 7 - 1 - - - BS8 - Set bit 8 - 8 - 1 - - - BS9 - Set bit 9 - 9 - 1 - - - BS10 - Set bit 10 - 10 - 1 - - - BS11 - Set bit 11 - 11 - 1 - - - BS12 - Set bit 12 - 12 - 1 - - - BS13 - Set bit 13 - 13 - 1 - - - BS14 - Set bit 14 - 14 - 1 - - - BS15 - Set bit 15 - 15 - 1 - - - BR0 - Reset bit 0 - 16 - 1 - - - BR1 - Reset bit 1 - 17 - 1 - - - BR2 - Reset bit 2 - 18 - 1 - - - BR3 - Reset bit 3 - 19 - 1 - - - BR4 - Reset bit 4 - 20 - 1 - - - BR5 - Reset bit 5 - 21 - 1 - - - BR6 - Reset bit 6 - 22 - 1 - - - BR7 - Reset bit 7 - 23 - 1 - - - BR8 - Reset bit 8 - 24 - 1 - - - BR9 - Reset bit 9 - 25 - 1 - - - BR10 - Reset bit 10 - 26 - 1 - - - BR11 - Reset bit 11 - 27 - 1 - - - BR12 - Reset bit 12 - 28 - 1 - - - BR13 - Reset bit 13 - 29 - 1 - - - BR14 - Reset bit 14 - 30 - 1 - - - BR15 - Reset bit 15 - 31 - 1 - - - - - BRR - BRR - Port bit reset register - (GPIOn_BRR) - 0x14 - 0x20 - write-only - 0x00000000 - - - BR0 - Reset bit 0 - 0 - 1 - - - BR1 - Reset bit 1 - 1 - 1 - - - BR2 - Reset bit 1 - 2 - 1 - - - BR3 - Reset bit 3 - 3 - 1 - - - BR4 - Reset bit 4 - 4 - 1 - - - BR5 - Reset bit 5 - 5 - 1 - - - BR6 - Reset bit 6 - 6 - 1 - - - BR7 - Reset bit 7 - 7 - 1 - - - BR8 - Reset bit 8 - 8 - 1 - - - BR9 - Reset bit 9 - 9 - 1 - - - BR10 - Reset bit 10 - 10 - 1 - - - BR11 - Reset bit 11 - 11 - 1 - - - BR12 - Reset bit 12 - 12 - 1 - - - BR13 - Reset bit 13 - 13 - 1 - - - BR14 - Reset bit 14 - 14 - 1 - - - BR15 - Reset bit 15 - 15 - 1 - - - - - LCKR - LCKR - Port configuration lock - register - 0x18 - 0x20 - read-write - 0x00000000 - - - LCK0 - Port A Lock bit 0 - 0 - 1 - - - LCK1 - Port A Lock bit 1 - 1 - 1 - - - LCK2 - Port A Lock bit 2 - 2 - 1 - - - LCK3 - Port A Lock bit 3 - 3 - 1 - - - LCK4 - Port A Lock bit 4 - 4 - 1 - - - LCK5 - Port A Lock bit 5 - 5 - 1 - - - LCK6 - Port A Lock bit 6 - 6 - 1 - - - LCK7 - Port A Lock bit 7 - 7 - 1 - - - LCK8 - Port A Lock bit 8 - 8 - 1 - - - LCK9 - Port A Lock bit 9 - 9 - 1 - - - LCK10 - Port A Lock bit 10 - 10 - 1 - - - LCK11 - Port A Lock bit 11 - 11 - 1 - - - LCK12 - Port A Lock bit 12 - 12 - 1 - - - LCK13 - Port A Lock bit 13 - 13 - 1 - - - LCK14 - Port A Lock bit 14 - 14 - 1 - - - LCK15 - Port A Lock bit 15 - 15 - 1 - - - LCKK - Lock key - 16 - 1 - - - - - - - GPIOB - 0x40010C00 - - - GPIOC - 0x40011000 - - - GPIOD - 0x40011400 - - - GPIOE - 0x40011800 - - - GPIOF - 0x40011C00 - - - GPIOG - 0x40012000 - - - AFIO - Alternate function I/O - AFIO - 0x40010000 - - 0x0 - 0x400 - registers - - - - EVCR - EVCR - Event Control Register - (AFIO_EVCR) - 0x0 - 0x20 - read-write - 0x00000000 - - - PIN - Pin selection - 0 - 4 - - - PORT - Port selection - 4 - 3 - - - EVOE - Event Output Enable - 7 - 1 - - - - - MAPR - MAPR - AF remap and debug I/O configuration - register (AFIO_MAPR) - 0x4 - 0x20 - 0x00000000 - - - SPI1_REMAP - SPI1 remapping - 0 - 1 - read-write - - - I2C1_REMAP - I2C1 remapping - 1 - 1 - read-write - - - USART1_REMAP - USART1 remapping - 2 - 1 - read-write - - - USART2_REMAP - USART2 remapping - 3 - 1 - read-write - - - USART3_REMAP - USART3 remapping - 4 - 2 - read-write - - - TIM1_REMAP - TIM1 remapping - 6 - 2 - read-write - - - TIM2_REMAP - TIM2 remapping - 8 - 2 - read-write - - - TIM3_REMAP - TIM3 remapping - 10 - 2 - read-write - - - TIM4_REMAP - TIM4 remapping - 12 - 1 - read-write - - - CAN_REMAP - CAN1 remapping - 13 - 2 - read-write - - - PD01_REMAP - Port D0/Port D1 mapping on - OSCIN/OSCOUT - 15 - 1 - read-write - - - TIM5CH4_IREMAP - Set and cleared by - software - 16 - 1 - read-write - - - ADC1_ETRGINJ_REMAP - ADC 1 External trigger injected - conversion remapping - 17 - 1 - read-write - - - ADC1_ETRGREG_REMAP - ADC 1 external trigger regular - conversion remapping - 18 - 1 - read-write - - - ADC2_ETRGINJ_REMAP - ADC 2 external trigger injected - conversion remapping - 19 - 1 - read-write - - - ADC2_ETRGREG_REMAP - ADC 2 external trigger regular - conversion remapping - 20 - 1 - read-write - - - SWJ_CFG - Serial wire JTAG - configuration - 24 - 3 - write-only - - - - - EXTICR1 - EXTICR1 - External interrupt configuration register 1 - (AFIO_EXTICR1) - 0x8 - 0x20 - read-write - 0x00000000 - - - EXTI0 - EXTI0 configuration - 0 - 4 - - - EXTI1 - EXTI1 configuration - 4 - 4 - - - EXTI2 - EXTI2 configuration - 8 - 4 - - - EXTI3 - EXTI3 configuration - 12 - 4 - - - - - EXTICR2 - EXTICR2 - External interrupt configuration register 2 - (AFIO_EXTICR2) - 0xC - 0x20 - read-write - 0x00000000 - - - EXTI4 - EXTI4 configuration - 0 - 4 - - - EXTI5 - EXTI5 configuration - 4 - 4 - - - EXTI6 - EXTI6 configuration - 8 - 4 - - - EXTI7 - EXTI7 configuration - 12 - 4 - - - - - EXTICR3 - EXTICR3 - External interrupt configuration register 3 - (AFIO_EXTICR3) - 0x10 - 0x20 - read-write - 0x00000000 - - - EXTI8 - EXTI8 configuration - 0 - 4 - - - EXTI9 - EXTI9 configuration - 4 - 4 - - - EXTI10 - EXTI10 configuration - 8 - 4 - - - EXTI11 - EXTI11 configuration - 12 - 4 - - - - - EXTICR4 - EXTICR4 - External interrupt configuration register 4 - (AFIO_EXTICR4) - 0x14 - 0x20 - read-write - 0x00000000 - - - EXTI12 - EXTI12 configuration - 0 - 4 - - - EXTI13 - EXTI13 configuration - 4 - 4 - - - EXTI14 - EXTI14 configuration - 8 - 4 - - - EXTI15 - EXTI15 configuration - 12 - 4 - - - - - MAPR2 - MAPR2 - AF remap and debug I/O configuration - register - 0x1C - 0x20 - read-write - 0x00000000 - - - TIM9_REMAP - TIM9 remapping - 5 - 1 - - - TIM10_REMAP - TIM10 remapping - 6 - 1 - - - TIM11_REMAP - TIM11 remapping - 7 - 1 - - - TIM13_REMAP - TIM13 remapping - 8 - 1 - - - TIM14_REMAP - TIM14 remapping - 9 - 1 - - - FSMC_NADV - NADV connect/disconnect - 10 - 1 - - - - - - - EXTI - EXTI - EXTI - 0x40010400 - - 0x0 - 0x400 - registers - - - TAMPER - Tamper interrupt - 2 - - - EXTI0 - EXTI Line0 interrupt - 6 - - - EXTI1 - EXTI Line1 interrupt - 7 - - - EXTI2 - EXTI Line2 interrupt - 8 - - - EXTI3 - EXTI Line3 interrupt - 9 - - - EXTI4 - EXTI Line4 interrupt - 10 - - - EXTI9_5 - EXTI Line[9:5] interrupts - 23 - - - EXTI15_10 - EXTI Line[15:10] interrupts - 40 - - - - IMR - IMR - Interrupt mask register - (EXTI_IMR) - 0x0 - 0x20 - read-write - 0x00000000 - - - MR0 - Interrupt Mask on line 0 - 0 - 1 - - - MR1 - Interrupt Mask on line 1 - 1 - 1 - - - MR2 - Interrupt Mask on line 2 - 2 - 1 - - - MR3 - Interrupt Mask on line 3 - 3 - 1 - - - MR4 - Interrupt Mask on line 4 - 4 - 1 - - - MR5 - Interrupt Mask on line 5 - 5 - 1 - - - MR6 - Interrupt Mask on line 6 - 6 - 1 - - - MR7 - Interrupt Mask on line 7 - 7 - 1 - - - MR8 - Interrupt Mask on line 8 - 8 - 1 - - - MR9 - Interrupt Mask on line 9 - 9 - 1 - - - MR10 - Interrupt Mask on line 10 - 10 - 1 - - - MR11 - Interrupt Mask on line 11 - 11 - 1 - - - MR12 - Interrupt Mask on line 12 - 12 - 1 - - - MR13 - Interrupt Mask on line 13 - 13 - 1 - - - MR14 - Interrupt Mask on line 14 - 14 - 1 - - - MR15 - Interrupt Mask on line 15 - 15 - 1 - - - MR16 - Interrupt Mask on line 16 - 16 - 1 - - - MR17 - Interrupt Mask on line 17 - 17 - 1 - - - MR18 - Interrupt Mask on line 18 - 18 - 1 - - - - - EMR - EMR - Event mask register (EXTI_EMR) - 0x4 - 0x20 - read-write - 0x00000000 - - - MR0 - Event Mask on line 0 - 0 - 1 - - - MR1 - Event Mask on line 1 - 1 - 1 - - - MR2 - Event Mask on line 2 - 2 - 1 - - - MR3 - Event Mask on line 3 - 3 - 1 - - - MR4 - Event Mask on line 4 - 4 - 1 - - - MR5 - Event Mask on line 5 - 5 - 1 - - - MR6 - Event Mask on line 6 - 6 - 1 - - - MR7 - Event Mask on line 7 - 7 - 1 - - - MR8 - Event Mask on line 8 - 8 - 1 - - - MR9 - Event Mask on line 9 - 9 - 1 - - - MR10 - Event Mask on line 10 - 10 - 1 - - - MR11 - Event Mask on line 11 - 11 - 1 - - - MR12 - Event Mask on line 12 - 12 - 1 - - - MR13 - Event Mask on line 13 - 13 - 1 - - - MR14 - Event Mask on line 14 - 14 - 1 - - - MR15 - Event Mask on line 15 - 15 - 1 - - - MR16 - Event Mask on line 16 - 16 - 1 - - - MR17 - Event Mask on line 17 - 17 - 1 - - - MR18 - Event Mask on line 18 - 18 - 1 - - - - - RTSR - RTSR - Rising Trigger selection register - (EXTI_RTSR) - 0x8 - 0x20 - read-write - 0x00000000 - - - TR0 - Rising trigger event configuration of - line 0 - 0 - 1 - - - TR1 - Rising trigger event configuration of - line 1 - 1 - 1 - - - TR2 - Rising trigger event configuration of - line 2 - 2 - 1 - - - TR3 - Rising trigger event configuration of - line 3 - 3 - 1 - - - TR4 - Rising trigger event configuration of - line 4 - 4 - 1 - - - TR5 - Rising trigger event configuration of - line 5 - 5 - 1 - - - TR6 - Rising trigger event configuration of - line 6 - 6 - 1 - - - TR7 - Rising trigger event configuration of - line 7 - 7 - 1 - - - TR8 - Rising trigger event configuration of - line 8 - 8 - 1 - - - TR9 - Rising trigger event configuration of - line 9 - 9 - 1 - - - TR10 - Rising trigger event configuration of - line 10 - 10 - 1 - - - TR11 - Rising trigger event configuration of - line 11 - 11 - 1 - - - TR12 - Rising trigger event configuration of - line 12 - 12 - 1 - - - TR13 - Rising trigger event configuration of - line 13 - 13 - 1 - - - TR14 - Rising trigger event configuration of - line 14 - 14 - 1 - - - TR15 - Rising trigger event configuration of - line 15 - 15 - 1 - - - TR16 - Rising trigger event configuration of - line 16 - 16 - 1 - - - TR17 - Rising trigger event configuration of - line 17 - 17 - 1 - - - TR18 - Rising trigger event configuration of - line 18 - 18 - 1 - - - - - FTSR - FTSR - Falling Trigger selection register - (EXTI_FTSR) - 0xC - 0x20 - read-write - 0x00000000 - - - TR0 - Falling trigger event configuration of - line 0 - 0 - 1 - - - TR1 - Falling trigger event configuration of - line 1 - 1 - 1 - - - TR2 - Falling trigger event configuration of - line 2 - 2 - 1 - - - TR3 - Falling trigger event configuration of - line 3 - 3 - 1 - - - TR4 - Falling trigger event configuration of - line 4 - 4 - 1 - - - TR5 - Falling trigger event configuration of - line 5 - 5 - 1 - - - TR6 - Falling trigger event configuration of - line 6 - 6 - 1 - - - TR7 - Falling trigger event configuration of - line 7 - 7 - 1 - - - TR8 - Falling trigger event configuration of - line 8 - 8 - 1 - - - TR9 - Falling trigger event configuration of - line 9 - 9 - 1 - - - TR10 - Falling trigger event configuration of - line 10 - 10 - 1 - - - TR11 - Falling trigger event configuration of - line 11 - 11 - 1 - - - TR12 - Falling trigger event configuration of - line 12 - 12 - 1 - - - TR13 - Falling trigger event configuration of - line 13 - 13 - 1 - - - TR14 - Falling trigger event configuration of - line 14 - 14 - 1 - - - TR15 - Falling trigger event configuration of - line 15 - 15 - 1 - - - TR16 - Falling trigger event configuration of - line 16 - 16 - 1 - - - TR17 - Falling trigger event configuration of - line 17 - 17 - 1 - - - TR18 - Falling trigger event configuration of - line 18 - 18 - 1 - - - - - SWIER - SWIER - Software interrupt event register - (EXTI_SWIER) - 0x10 - 0x20 - read-write - 0x00000000 - - - SWIER0 - Software Interrupt on line - 0 - 0 - 1 - - - SWIER1 - Software Interrupt on line - 1 - 1 - 1 - - - SWIER2 - Software Interrupt on line - 2 - 2 - 1 - - - SWIER3 - Software Interrupt on line - 3 - 3 - 1 - - - SWIER4 - Software Interrupt on line - 4 - 4 - 1 - - - SWIER5 - Software Interrupt on line - 5 - 5 - 1 - - - SWIER6 - Software Interrupt on line - 6 - 6 - 1 - - - SWIER7 - Software Interrupt on line - 7 - 7 - 1 - - - SWIER8 - Software Interrupt on line - 8 - 8 - 1 - - - SWIER9 - Software Interrupt on line - 9 - 9 - 1 - - - SWIER10 - Software Interrupt on line - 10 - 10 - 1 - - - SWIER11 - Software Interrupt on line - 11 - 11 - 1 - - - SWIER12 - Software Interrupt on line - 12 - 12 - 1 - - - SWIER13 - Software Interrupt on line - 13 - 13 - 1 - - - SWIER14 - Software Interrupt on line - 14 - 14 - 1 - - - SWIER15 - Software Interrupt on line - 15 - 15 - 1 - - - SWIER16 - Software Interrupt on line - 16 - 16 - 1 - - - SWIER17 - Software Interrupt on line - 17 - 17 - 1 - - - SWIER18 - Software Interrupt on line - 18 - 18 - 1 - - - - - PR - PR - Pending register (EXTI_PR) - 0x14 - 0x20 - read-write - 0x00000000 - - - PR0 - Pending bit 0 - 0 - 1 - - - PR1 - Pending bit 1 - 1 - 1 - - - PR2 - Pending bit 2 - 2 - 1 - - - PR3 - Pending bit 3 - 3 - 1 - - - PR4 - Pending bit 4 - 4 - 1 - - - PR5 - Pending bit 5 - 5 - 1 - - - PR6 - Pending bit 6 - 6 - 1 - - - PR7 - Pending bit 7 - 7 - 1 - - - PR8 - Pending bit 8 - 8 - 1 - - - PR9 - Pending bit 9 - 9 - 1 - - - PR10 - Pending bit 10 - 10 - 1 - - - PR11 - Pending bit 11 - 11 - 1 - - - PR12 - Pending bit 12 - 12 - 1 - - - PR13 - Pending bit 13 - 13 - 1 - - - PR14 - Pending bit 14 - 14 - 1 - - - PR15 - Pending bit 15 - 15 - 1 - - - PR16 - Pending bit 16 - 16 - 1 - - - PR17 - Pending bit 17 - 17 - 1 - - - PR18 - Pending bit 18 - 18 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 11 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 12 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 13 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 14 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 15 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 16 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 17 - - - - ISR - ISR - DMA interrupt status register - (DMA_ISR) - 0x0 - 0x20 - read-only - 0x00000000 - - - GIF1 - Channel 1 Global interrupt - flag - 0 - 1 - - - TCIF1 - Channel 1 Transfer Complete - flag - 1 - 1 - - - HTIF1 - Channel 1 Half Transfer Complete - flag - 2 - 1 - - - TEIF1 - Channel 1 Transfer Error - flag - 3 - 1 - - - GIF2 - Channel 2 Global interrupt - flag - 4 - 1 - - - TCIF2 - Channel 2 Transfer Complete - flag - 5 - 1 - - - HTIF2 - Channel 2 Half Transfer Complete - flag - 6 - 1 - - - TEIF2 - Channel 2 Transfer Error - flag - 7 - 1 - - - GIF3 - Channel 3 Global interrupt - flag - 8 - 1 - - - TCIF3 - Channel 3 Transfer Complete - flag - 9 - 1 - - - HTIF3 - Channel 3 Half Transfer Complete - flag - 10 - 1 - - - TEIF3 - Channel 3 Transfer Error - flag - 11 - 1 - - - GIF4 - Channel 4 Global interrupt - flag - 12 - 1 - - - TCIF4 - Channel 4 Transfer Complete - flag - 13 - 1 - - - HTIF4 - Channel 4 Half Transfer Complete - flag - 14 - 1 - - - TEIF4 - Channel 4 Transfer Error - flag - 15 - 1 - - - GIF5 - Channel 5 Global interrupt - flag - 16 - 1 - - - TCIF5 - Channel 5 Transfer Complete - flag - 17 - 1 - - - HTIF5 - Channel 5 Half Transfer Complete - flag - 18 - 1 - - - TEIF5 - Channel 5 Transfer Error - flag - 19 - 1 - - - GIF6 - Channel 6 Global interrupt - flag - 20 - 1 - - - TCIF6 - Channel 6 Transfer Complete - flag - 21 - 1 - - - HTIF6 - Channel 6 Half Transfer Complete - flag - 22 - 1 - - - TEIF6 - Channel 6 Transfer Error - flag - 23 - 1 - - - GIF7 - Channel 7 Global interrupt - flag - 24 - 1 - - - TCIF7 - Channel 7 Transfer Complete - flag - 25 - 1 - - - HTIF7 - Channel 7 Half Transfer Complete - flag - 26 - 1 - - - TEIF7 - Channel 7 Transfer Error - flag - 27 - 1 - - - - - IFCR - IFCR - DMA interrupt flag clear register - (DMA_IFCR) - 0x4 - 0x20 - write-only - 0x00000000 - - - CGIF1 - Channel 1 Global interrupt - clear - 0 - 1 - - - CGIF2 - Channel 2 Global interrupt - clear - 4 - 1 - - - CGIF3 - Channel 3 Global interrupt - clear - 8 - 1 - - - CGIF4 - Channel 4 Global interrupt - clear - 12 - 1 - - - CGIF5 - Channel 5 Global interrupt - clear - 16 - 1 - - - CGIF6 - Channel 6 Global interrupt - clear - 20 - 1 - - - CGIF7 - Channel 7 Global interrupt - clear - 24 - 1 - - - CTCIF1 - Channel 1 Transfer Complete - clear - 1 - 1 - - - CTCIF2 - Channel 2 Transfer Complete - clear - 5 - 1 - - - CTCIF3 - Channel 3 Transfer Complete - clear - 9 - 1 - - - CTCIF4 - Channel 4 Transfer Complete - clear - 13 - 1 - - - CTCIF5 - Channel 5 Transfer Complete - clear - 17 - 1 - - - CTCIF6 - Channel 6 Transfer Complete - clear - 21 - 1 - - - CTCIF7 - Channel 7 Transfer Complete - clear - 25 - 1 - - - CHTIF1 - Channel 1 Half Transfer - clear - 2 - 1 - - - CHTIF2 - Channel 2 Half Transfer - clear - 6 - 1 - - - CHTIF3 - Channel 3 Half Transfer - clear - 10 - 1 - - - CHTIF4 - Channel 4 Half Transfer - clear - 14 - 1 - - - CHTIF5 - Channel 5 Half Transfer - clear - 18 - 1 - - - CHTIF6 - Channel 6 Half Transfer - clear - 22 - 1 - - - CHTIF7 - Channel 7 Half Transfer - clear - 26 - 1 - - - CTEIF1 - Channel 1 Transfer Error - clear - 3 - 1 - - - CTEIF2 - Channel 2 Transfer Error - clear - 7 - 1 - - - CTEIF3 - Channel 3 Transfer Error - clear - 11 - 1 - - - CTEIF4 - Channel 4 Transfer Error - clear - 15 - 1 - - - CTEIF5 - Channel 5 Transfer Error - clear - 19 - 1 - - - CTEIF6 - Channel 6 Transfer Error - clear - 23 - 1 - - - CTEIF7 - Channel 7 Transfer Error - clear - 27 - 1 - - - - - CCR1 - CCR1 - DMA channel configuration register - (DMA_CCR) - 0x8 - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR1 - CNDTR1 - DMA channel 1 number of data - register - 0xC - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR1 - CPAR1 - DMA channel 1 peripheral address - register - 0x10 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR1 - CMAR1 - DMA channel 1 memory address - register - 0x14 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR2 - CCR2 - DMA channel configuration register - (DMA_CCR) - 0x1C - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR2 - CNDTR2 - DMA channel 2 number of data - register - 0x20 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR2 - CPAR2 - DMA channel 2 peripheral address - register - 0x24 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR2 - CMAR2 - DMA channel 2 memory address - register - 0x28 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR3 - CCR3 - DMA channel configuration register - (DMA_CCR) - 0x30 - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR3 - CNDTR3 - DMA channel 3 number of data - register - 0x34 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR3 - CPAR3 - DMA channel 3 peripheral address - register - 0x38 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR3 - CMAR3 - DMA channel 3 memory address - register - 0x3C - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR4 - CCR4 - DMA channel configuration register - (DMA_CCR) - 0x44 - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR4 - CNDTR4 - DMA channel 4 number of data - register - 0x48 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR4 - CPAR4 - DMA channel 4 peripheral address - register - 0x4C - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR4 - CMAR4 - DMA channel 4 memory address - register - 0x50 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR5 - CCR5 - DMA channel configuration register - (DMA_CCR) - 0x58 - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR5 - CNDTR5 - DMA channel 5 number of data - register - 0x5C - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR5 - CPAR5 - DMA channel 5 peripheral address - register - 0x60 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR5 - CMAR5 - DMA channel 5 memory address - register - 0x64 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR6 - CCR6 - DMA channel configuration register - (DMA_CCR) - 0x6C - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR6 - CNDTR6 - DMA channel 6 number of data - register - 0x70 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR6 - CPAR6 - DMA channel 6 peripheral address - register - 0x74 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR6 - CMAR6 - DMA channel 6 memory address - register - 0x78 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR7 - CCR7 - DMA channel configuration register - (DMA_CCR) - 0x80 - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR7 - CNDTR7 - DMA channel 7 number of data - register - 0x84 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR7 - CPAR7 - DMA channel 7 peripheral address - register - 0x88 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR7 - CMAR7 - DMA channel 7 memory address - register - 0x8C - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - - - DMA2 - 0x40020400 - - DMA2_Channel1 - DMA2 Channel1 global interrupt - 56 - - - DMA2_Channel2 - DMA2 Channel2 global interrupt - 57 - - - DMA2_Channel3 - DMA2 Channel3 global interrupt - 58 - - - DMA2_Channel4_5 - DMA2 Channel4 and DMA2 Channel5 global - interrupt - 59 - - - - SDIO - Secure digital input/output - interface - SDIO - 0x40018000 - - 0x0 - 0x400 - registers - - - SDIO - SDIO global interrupt - 49 - - - - POWER - POWER - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PWRCTRL - PWRCTRL - 0 - 2 - - - - - CLKCR - CLKCR - SDI clock control register - (SDIO_CLKCR) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKDIV - Clock divide factor - 0 - 8 - - - CLKEN - Clock enable bit - 8 - 1 - - - PWRSAV - Power saving configuration - bit - 9 - 1 - - - BYPASS - Clock divider bypass enable - bit - 10 - 1 - - - WIDBUS - Wide bus mode enable bit - 11 - 2 - - - NEGEDGE - SDIO_CK dephasing selection - bit - 13 - 1 - - - HWFC_EN - HW Flow Control enable - 14 - 1 - - - - - ARG - ARG - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - CMDARG - Command argument - 0 - 32 - - - - - CMD - CMD - SDIO command register - (SDIO_CMD) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDINDEX - CMDINDEX - 0 - 6 - - - WAITRESP - WAITRESP - 6 - 2 - - - WAITINT - WAITINT - 8 - 1 - - - WAITPEND - WAITPEND - 9 - 1 - - - CPSMEN - CPSMEN - 10 - 1 - - - SDIOSuspend - SDIOSuspend - 11 - 1 - - - ENCMDcompl - ENCMDcompl - 12 - 1 - - - nIEN - nIEN - 13 - 1 - - - CE_ATACMD - CE_ATACMD - 14 - 1 - - - - - RESPCMD - RESPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RESPCMD - RESPCMD - 0 - 6 - - - - - RESPI1 - RESPI1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTATUS1 - CARDSTATUS1 - 0 - 32 - - - - - RESP2 - RESP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTATUS2 - CARDSTATUS2 - 0 - 32 - - - - - RESP3 - RESP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTATUS3 - CARDSTATUS3 - 0 - 32 - - - - - RESP4 - RESP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTATUS4 - CARDSTATUS4 - 0 - 32 - - - - - DTIMER - DTIMER - Bits 31:0 = DATATIME: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - DATATIME - Data timeout period - 0 - 32 - - - - - DLEN - DLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DATALENGTH - Data length value - 0 - 25 - - - - - DCTRL - DCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - DTEN - DTEN - 0 - 1 - - - DTDIR - DTDIR - 1 - 1 - - - DTMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - DBLOCKSIZE - DBLOCKSIZE - 4 - 4 - - - PWSTART - PWSTART - 8 - 1 - - - PWSTOP - PWSTOP - 9 - 1 - - - RWMOD - RWMOD - 10 - 1 - - - SDIOEN - SDIOEN - 11 - 1 - - - - - DCOUNT - DCOUNT - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - DATACOUNT - Data count value - 0 - 25 - - - - - STA - STA - SDIO status register - (SDIO_STA) - 0x34 - 0x20 - read-only - 0x00000000 - - - CCRCFAIL - CCRCFAIL - 0 - 1 - - - DCRCFAIL - DCRCFAIL - 1 - 1 - - - CTIMEOUT - CTIMEOUT - 2 - 1 - - - DTIMEOUT - DTIMEOUT - 3 - 1 - - - TXUNDERR - TXUNDERR - 4 - 1 - - - RXOVERR - RXOVERR - 5 - 1 - - - CMDREND - CMDREND - 6 - 1 - - - CMDSENT - CMDSENT - 7 - 1 - - - DATAEND - DATAEND - 8 - 1 - - - STBITERR - STBITERR - 9 - 1 - - - DBCKEND - DBCKEND - 10 - 1 - - - CMDACT - CMDACT - 11 - 1 - - - TXACT - TXACT - 12 - 1 - - - RXACT - RXACT - 13 - 1 - - - TXFIFOHE - TXFIFOHE - 14 - 1 - - - RXFIFOHF - RXFIFOHF - 15 - 1 - - - TXFIFOF - TXFIFOF - 16 - 1 - - - RXFIFOF - RXFIFOF - 17 - 1 - - - TXFIFOE - TXFIFOE - 18 - 1 - - - RXFIFOE - RXFIFOE - 19 - 1 - - - TXDAVL - TXDAVL - 20 - 1 - - - RXDAVL - RXDAVL - 21 - 1 - - - SDIOIT - SDIOIT - 22 - 1 - - - CEATAEND - CEATAEND - 23 - 1 - - - - - ICR - ICR - SDIO interrupt clear register - (SDIO_ICR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CCRCFAILC - CCRCFAILC - 0 - 1 - - - DCRCFAILC - DCRCFAILC - 1 - 1 - - - CTIMEOUTC - CTIMEOUTC - 2 - 1 - - - DTIMEOUTC - DTIMEOUTC - 3 - 1 - - - TXUNDERRC - TXUNDERRC - 4 - 1 - - - RXOVERRC - RXOVERRC - 5 - 1 - - - CMDRENDC - CMDRENDC - 6 - 1 - - - CMDSENTC - CMDSENTC - 7 - 1 - - - DATAENDC - DATAENDC - 8 - 1 - - - STBITERRC - STBITERRC - 9 - 1 - - - DBCKENDC - DBCKENDC - 10 - 1 - - - SDIOITC - SDIOITC - 22 - 1 - - - CEATAENDC - CEATAENDC - 23 - 1 - - - - - MASK - MASK - SDIO mask register (SDIO_MASK) - 0x3C - 0x20 - read-write - 0x00000000 - - - CCRCFAILIE - CCRCFAILIE - 0 - 1 - - - DCRCFAILIE - DCRCFAILIE - 1 - 1 - - - CTIMEOUTIE - CTIMEOUTIE - 2 - 1 - - - DTIMEOUTIE - DTIMEOUTIE - 3 - 1 - - - TXUNDERRIE - TXUNDERRIE - 4 - 1 - - - RXOVERRIE - RXOVERRIE - 5 - 1 - - - CMDRENDIE - CMDRENDIE - 6 - 1 - - - CMDSENTIE - CMDSENTIE - 7 - 1 - - - DATAENDIE - DATAENDIE - 8 - 1 - - - STBITERRIE - STBITERRIE - 9 - 1 - - - DBACKENDIE - DBACKENDIE - 10 - 1 - - - CMDACTIE - CMDACTIE - 11 - 1 - - - TXACTIE - TXACTIE - 12 - 1 - - - RXACTIE - RXACTIE - 13 - 1 - - - TXFIFOHEIE - TXFIFOHEIE - 14 - 1 - - - RXFIFOHFIE - RXFIFOHFIE - 15 - 1 - - - TXFIFOFIE - TXFIFOFIE - 16 - 1 - - - RXFIFOFIE - RXFIFOFIE - 17 - 1 - - - TXFIFOEIE - TXFIFOEIE - 18 - 1 - - - RXFIFOEIE - RXFIFOEIE - 19 - 1 - - - TXDAVLIE - TXDAVLIE - 20 - 1 - - - RXDAVLIE - RXDAVLIE - 21 - 1 - - - SDIOITIE - SDIOITIE - 22 - 1 - - - CEATENDIE - CEATENDIE - 23 - 1 - - - - - FIFOCNT - FIFOCNT - Bits 23:0 = FIFOCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - FIF0COUNT - FIF0COUNT - 0 - 24 - - - - - FIFO - FIFO - bits 31:0 = FIFOData: Receive and transmit - FIFO data - 0x80 - 0x20 - read-write - 0x00000000 - - - FIFOData - FIFOData - 0 - 32 - - - - - - - RTC - Real time clock - RTC - 0x40002800 - - 0x0 - 0x400 - registers - - - RTC - RTC global interrupt - 3 - - - RTCAlarm - RTC Alarms through EXTI line - interrupt - 41 - - - - CRH - CRH - RTC Control Register High - 0x0 - 0x20 - read-write - 0x00000000 - - - SECIE - Second interrupt Enable - 0 - 1 - - - ALRIE - Alarm interrupt Enable - 1 - 1 - - - OWIE - Overflow interrupt Enable - 2 - 1 - - - - - CRL - CRL - RTC Control Register Low - 0x4 - 0x20 - 0x00000020 - - - SECF - Second Flag - 0 - 1 - read-write - - - ALRF - Alarm Flag - 1 - 1 - read-write - - - OWF - Overflow Flag - 2 - 1 - read-write - - - RSF - Registers Synchronized - Flag - 3 - 1 - read-write - - - CNF - Configuration Flag - 4 - 1 - read-write - - - RTOFF - RTC operation OFF - 5 - 1 - read-only - - - - - PRLH - PRLH - RTC Prescaler Load Register - High - 0x8 - 0x20 - write-only - 0x00000000 - - - PRLH - RTC Prescaler Load Register - High - 0 - 4 - - - - - PRLL - PRLL - RTC Prescaler Load Register - Low - 0xC - 0x20 - write-only - 0x8000 - - - PRLL - RTC Prescaler Divider Register - Low - 0 - 16 - - - - - DIVH - DIVH - RTC Prescaler Divider Register - High - 0x10 - 0x20 - read-only - 0x00000000 - - - DIVH - RTC prescaler divider register - high - 0 - 4 - - - - - DIVL - DIVL - RTC Prescaler Divider Register - Low - 0x14 - 0x20 - read-only - 0x8000 - - - DIVL - RTC prescaler divider register - Low - 0 - 16 - - - - - CNTH - CNTH - RTC Counter Register High - 0x18 - 0x20 - read-write - 0x00000000 - - - CNTH - RTC counter register high - 0 - 16 - - - - - CNTL - CNTL - RTC Counter Register Low - 0x1C - 0x20 - read-write - 0x00000000 - - - CNTL - RTC counter register Low - 0 - 16 - - - - - ALRH - ALRH - RTC Alarm Register High - 0x20 - 0x20 - write-only - 0xFFFF - - - ALRH - RTC alarm register high - 0 - 16 - - - - - ALRL - ALRL - RTC Alarm Register Low - 0x24 - 0x20 - write-only - 0xFFFF - - - ALRL - RTC alarm register low - 0 - 16 - - - - - - - BKP - Backup registers - BKP - 0x40006C04 - - 0x0 - 0x400 - registers - - - - DR1 - DR1 - Backup data register (BKP_DR) - 0x0 - 0x20 - read-write - 0x00000000 - - - D1 - Backup data - 0 - 16 - - - - - DR2 - DR2 - Backup data register (BKP_DR) - 0x4 - 0x20 - read-write - 0x00000000 - - - D2 - Backup data - 0 - 16 - - - - - DR3 - DR3 - Backup data register (BKP_DR) - 0x8 - 0x20 - read-write - 0x00000000 - - - D3 - Backup data - 0 - 16 - - - - - DR4 - DR4 - Backup data register (BKP_DR) - 0xC - 0x20 - read-write - 0x00000000 - - - D4 - Backup data - 0 - 16 - - - - - DR5 - DR5 - Backup data register (BKP_DR) - 0x10 - 0x20 - read-write - 0x00000000 - - - D5 - Backup data - 0 - 16 - - - - - DR6 - DR6 - Backup data register (BKP_DR) - 0x14 - 0x20 - read-write - 0x00000000 - - - D6 - Backup data - 0 - 16 - - - - - DR7 - DR7 - Backup data register (BKP_DR) - 0x18 - 0x20 - read-write - 0x00000000 - - - D7 - Backup data - 0 - 16 - - - - - DR8 - DR8 - Backup data register (BKP_DR) - 0x1C - 0x20 - read-write - 0x00000000 - - - D8 - Backup data - 0 - 16 - - - - - DR9 - DR9 - Backup data register (BKP_DR) - 0x20 - 0x20 - read-write - 0x00000000 - - - D9 - Backup data - 0 - 16 - - - - - DR10 - DR10 - Backup data register (BKP_DR) - 0x24 - 0x20 - read-write - 0x00000000 - - - D10 - Backup data - 0 - 16 - - - - - DR11 - DR11 - Backup data register (BKP_DR) - 0x3C - 0x20 - read-write - 0x00000000 - - - DR11 - Backup data - 0 - 16 - - - - - DR12 - DR12 - Backup data register (BKP_DR) - 0x40 - 0x20 - read-write - 0x00000000 - - - DR12 - Backup data - 0 - 16 - - - - - DR13 - DR13 - Backup data register (BKP_DR) - 0x44 - 0x20 - read-write - 0x00000000 - - - DR13 - Backup data - 0 - 16 - - - - - DR14 - DR14 - Backup data register (BKP_DR) - 0x48 - 0x20 - read-write - 0x00000000 - - - D14 - Backup data - 0 - 16 - - - - - DR15 - DR15 - Backup data register (BKP_DR) - 0x4C - 0x20 - read-write - 0x00000000 - - - D15 - Backup data - 0 - 16 - - - - - DR16 - DR16 - Backup data register (BKP_DR) - 0x50 - 0x20 - read-write - 0x00000000 - - - D16 - Backup data - 0 - 16 - - - - - DR17 - DR17 - Backup data register (BKP_DR) - 0x54 - 0x20 - read-write - 0x00000000 - - - D17 - Backup data - 0 - 16 - - - - - DR18 - DR18 - Backup data register (BKP_DR) - 0x58 - 0x20 - read-write - 0x00000000 - - - D18 - Backup data - 0 - 16 - - - - - DR19 - DR19 - Backup data register (BKP_DR) - 0x5C - 0x20 - read-write - 0x00000000 - - - D19 - Backup data - 0 - 16 - - - - - DR20 - DR20 - Backup data register (BKP_DR) - 0x60 - 0x20 - read-write - 0x00000000 - - - D20 - Backup data - 0 - 16 - - - - - DR21 - DR21 - Backup data register (BKP_DR) - 0x64 - 0x20 - read-write - 0x00000000 - - - D21 - Backup data - 0 - 16 - - - - - DR22 - DR22 - Backup data register (BKP_DR) - 0x68 - 0x20 - read-write - 0x00000000 - - - D22 - Backup data - 0 - 16 - - - - - DR23 - DR23 - Backup data register (BKP_DR) - 0x6C - 0x20 - read-write - 0x00000000 - - - D23 - Backup data - 0 - 16 - - - - - DR24 - DR24 - Backup data register (BKP_DR) - 0x70 - 0x20 - read-write - 0x00000000 - - - D24 - Backup data - 0 - 16 - - - - - DR25 - DR25 - Backup data register (BKP_DR) - 0x74 - 0x20 - read-write - 0x00000000 - - - D25 - Backup data - 0 - 16 - - - - - DR26 - DR26 - Backup data register (BKP_DR) - 0x78 - 0x20 - read-write - 0x00000000 - - - D26 - Backup data - 0 - 16 - - - - - DR27 - DR27 - Backup data register (BKP_DR) - 0x7C - 0x20 - read-write - 0x00000000 - - - D27 - Backup data - 0 - 16 - - - - - DR28 - DR28 - Backup data register (BKP_DR) - 0x80 - 0x20 - read-write - 0x00000000 - - - D28 - Backup data - 0 - 16 - - - - - DR29 - DR29 - Backup data register (BKP_DR) - 0x84 - 0x20 - read-write - 0x00000000 - - - D29 - Backup data - 0 - 16 - - - - - DR30 - DR30 - Backup data register (BKP_DR) - 0x88 - 0x20 - read-write - 0x00000000 - - - D30 - Backup data - 0 - 16 - - - - - DR31 - DR31 - Backup data register (BKP_DR) - 0x8C - 0x20 - read-write - 0x00000000 - - - D31 - Backup data - 0 - 16 - - - - - DR32 - DR32 - Backup data register (BKP_DR) - 0x90 - 0x20 - read-write - 0x00000000 - - - D32 - Backup data - 0 - 16 - - - - - DR33 - DR33 - Backup data register (BKP_DR) - 0x94 - 0x20 - read-write - 0x00000000 - - - D33 - Backup data - 0 - 16 - - - - - DR34 - DR34 - Backup data register (BKP_DR) - 0x98 - 0x20 - read-write - 0x00000000 - - - D34 - Backup data - 0 - 16 - - - - - DR35 - DR35 - Backup data register (BKP_DR) - 0x9C - 0x20 - read-write - 0x00000000 - - - D35 - Backup data - 0 - 16 - - - - - DR36 - DR36 - Backup data register (BKP_DR) - 0xA0 - 0x20 - read-write - 0x00000000 - - - D36 - Backup data - 0 - 16 - - - - - DR37 - DR37 - Backup data register (BKP_DR) - 0xA4 - 0x20 - read-write - 0x00000000 - - - D37 - Backup data - 0 - 16 - - - - - DR38 - DR38 - Backup data register (BKP_DR) - 0xA8 - 0x20 - read-write - 0x00000000 - - - D38 - Backup data - 0 - 16 - - - - - DR39 - DR39 - Backup data register (BKP_DR) - 0xAC - 0x20 - read-write - 0x00000000 - - - D39 - Backup data - 0 - 16 - - - - - DR40 - DR40 - Backup data register (BKP_DR) - 0xB0 - 0x20 - read-write - 0x00000000 - - - D40 - Backup data - 0 - 16 - - - - - DR41 - DR41 - Backup data register (BKP_DR) - 0xB4 - 0x20 - read-write - 0x00000000 - - - D41 - Backup data - 0 - 16 - - - - - DR42 - DR42 - Backup data register (BKP_DR) - 0xB8 - 0x20 - read-write - 0x00000000 - - - D42 - Backup data - 0 - 16 - - - - - RTCCR - RTCCR - RTC clock calibration register - (BKP_RTCCR) - 0x28 - 0x20 - read-write - 0x00000000 - - - CAL - Calibration value - 0 - 7 - - - CCO - Calibration Clock Output - 7 - 1 - - - ASOE - Alarm or second output - enable - 8 - 1 - - - ASOS - Alarm or second output - selection - 9 - 1 - - - - - CR - CR - Backup control register - (BKP_CR) - 0x2C - 0x20 - read-write - 0x00000000 - - - TPE - Tamper pin enable - 0 - 1 - - - TPAL - Tamper pin active level - 1 - 1 - - - - - CSR - CSR - BKP_CSR control/status register - (BKP_CSR) - 0x30 - 0x20 - 0x00000000 - - - CTE - Clear Tamper event - 0 - 1 - write-only - - - CTI - Clear Tamper Interrupt - 1 - 1 - write-only - - - TPIE - Tamper Pin interrupt - enable - 2 - 1 - read-write - - - TEF - Tamper Event Flag - 8 - 1 - read-only - - - TIF - Tamper Interrupt Flag - 9 - 1 - read-only - - - - - - - IWDG - Independent watchdog - IWDG - 0x40003000 - - 0x0 - 0x400 - registers - - - - KR - KR - Key register (IWDG_KR) - 0x0 - 0x20 - write-only - 0x00000000 - - - KEY - Key value - 0 - 16 - - - - - PR - PR - Prescaler register (IWDG_PR) - 0x4 - 0x20 - read-write - 0x00000000 - - - PR - Prescaler divider - 0 - 3 - - - - - RLR - RLR - Reload register (IWDG_RLR) - 0x8 - 0x20 - read-write - 0x00000FFF - - - RL - Watchdog counter reload - value - 0 - 12 - - - - - SR - SR - Status register (IWDG_SR) - 0xC - 0x20 - read-only - 0x00000000 - - - PVU - Watchdog prescaler value - update - 0 - 1 - - - RVU - Watchdog counter reload value - update - 1 - 1 - - - - - - - WWDG - Window watchdog - WWDG - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDG - Window Watchdog interrupt - 0 - - - - CR - CR - Control register (WWDG_CR) - 0x0 - 0x20 - read-write - 0x0000007F - - - T - 7-bit counter (MSB to LSB) - 0 - 7 - - - WDGA - Activation bit - 7 - 1 - - - - - CFR - CFR - Configuration register - (WWDG_CFR) - 0x4 - 0x20 - read-write - 0x0000007F - - - W - 7-bit window value - 0 - 7 - - - WDGTB - Timer Base - 7 - 2 - - - EWI - Early Wakeup Interrupt - 9 - 1 - - - - - SR - SR - Status register (WWDG_SR) - 0x8 - 0x20 - read-write - 0x00000000 - - - EWI - Early Wakeup Interrupt - 0 - 1 - - - - - - - TIM1 - Advanced timer - TIM - 0x40012C00 - - 0x0 - 0x400 - registers - - - TIM1_BRK_TIM9 - TIM1 Break interrupt and TIM9 global - interrupt - 24 - - - TIM1_UP_TIM10 - TIM1 Update interrupt and TIM10 global - interrupt - 25 - - - TIM1_TRG_COM_TIM11 - TIM1 Trigger and Commutation interrupts and - TIM11 global interrupt - 26 - - - TIM1_CC - TIM1 Capture Compare interrupt - 27 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Clock division - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - CMS - Center-aligned mode - selection - 5 - 2 - - - DIR - Direction - 4 - 1 - - - OPM - One-pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - OIS4 - Output Idle state 4 - 14 - 1 - - - OIS3N - Output Idle state 3 - 13 - 1 - - - OIS3 - Output Idle state 3 - 12 - 1 - - - OIS2N - Output Idle state 2 - 11 - 1 - - - OIS2 - Output Idle state 2 - 10 - 1 - - - OIS1N - Output Idle state 1 - 9 - 1 - - - OIS1 - Output Idle state 1 - 8 - 1 - - - TI1S - TI1 selection - 7 - 1 - - - MMS - Master mode selection - 4 - 3 - - - CCDS - Capture/compare DMA - selection - 3 - 1 - - - CCUS - Capture/compare control update - selection - 2 - 1 - - - CCPC - Capture/compare preloaded - control - 0 - 1 - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x0000 - - - ETP - External trigger polarity - 15 - 1 - - - ECE - External clock enable - 14 - 1 - - - ETPS - External trigger prescaler - 12 - 2 - - - ETF - External trigger filter - 8 - 4 - - - MSM - Master/Slave mode - 7 - 1 - - - TS - Trigger selection - 4 - 3 - - - SMS - Slave mode selection - 0 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDE - Trigger DMA request enable - 14 - 1 - - - COMDE - COM DMA request enable - 13 - 1 - - - CC4DE - Capture/Compare 4 DMA request - enable - 12 - 1 - - - CC3DE - Capture/Compare 3 DMA request - enable - 11 - 1 - - - CC2DE - Capture/Compare 2 DMA request - enable - 10 - 1 - - - CC1DE - Capture/Compare 1 DMA request - enable - 9 - 1 - - - UDE - Update DMA request enable - 8 - 1 - - - TIE - Trigger interrupt enable - 6 - 1 - - - CC4IE - Capture/Compare 4 interrupt - enable - 4 - 1 - - - CC3IE - Capture/Compare 3 interrupt - enable - 3 - 1 - - - CC2IE - Capture/Compare 2 interrupt - enable - 2 - 1 - - - CC1IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - BIE - Break interrupt enable - 7 - 1 - - - COMIE - COM interrupt enable - 5 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC4OF - Capture/Compare 4 overcapture - flag - 12 - 1 - - - CC3OF - Capture/Compare 3 overcapture - flag - 11 - 1 - - - CC2OF - Capture/compare 2 overcapture - flag - 10 - 1 - - - CC1OF - Capture/Compare 1 overcapture - flag - 9 - 1 - - - BIF - Break interrupt flag - 7 - 1 - - - TIF - Trigger interrupt flag - 6 - 1 - - - COMIF - COM interrupt flag - 5 - 1 - - - CC4IF - Capture/Compare 4 interrupt - flag - 4 - 1 - - - CC3IF - Capture/Compare 3 interrupt - flag - 3 - 1 - - - CC2IF - Capture/Compare 2 interrupt - flag - 2 - 1 - - - CC1IF - Capture/compare 1 interrupt - flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - BG - Break generation - 7 - 1 - - - TG - Trigger generation - 6 - 1 - - - COMG - Capture/Compare control update - generation - 5 - 1 - - - CC4G - Capture/compare 4 - generation - 4 - 1 - - - CC3G - Capture/compare 3 - generation - 3 - 1 - - - CC2G - Capture/compare 2 - generation - 2 - 1 - - - CC1G - Capture/compare 1 - generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2CE - Output Compare 2 clear - enable - 15 - 1 - - - OC2M - Output Compare 2 mode - 12 - 3 - - - OC2PE - Output Compare 2 preload - enable - 11 - 1 - - - OC2FE - Output Compare 2 fast - enable - 10 - 1 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - OC1CE - Output Compare 1 clear - enable - 7 - 1 - - - OC1M - Output Compare 1 mode - 4 - 3 - - - OC1PE - Output Compare 1 preload - enable - 3 - 1 - - - OC1FE - Output Compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - IC2PCS - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - IC1F - Input capture 1 filter - 4 - 4 - - - ICPCS - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR2_Output - CCMR2_Output - capture/compare mode register (output - mode) - 0x1C - 0x20 - read-write - 0x00000000 - - - OC4CE - Output compare 4 clear - enable - 15 - 1 - - - OC4M - Output compare 4 mode - 12 - 3 - - - OC4PE - Output compare 4 preload - enable - 11 - 1 - - - OC4FE - Output compare 4 fast - enable - 10 - 1 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - OC3CE - Output compare 3 clear - enable - 7 - 1 - - - OC3M - Output compare 3 mode - 4 - 3 - - - OC3PE - Output compare 3 preload - enable - 3 - 1 - - - OC3FE - Output compare 3 fast - enable - 2 - 1 - - - CC3S - Capture/Compare 3 - selection - 0 - 2 - - - - - CCMR2_Input - CCMR2_Input - capture/compare mode register 2 (input - mode) - CCMR2_Output - 0x1C - 0x20 - read-write - 0x00000000 - - - IC4F - Input capture 4 filter - 12 - 4 - - - IC4PSC - Input capture 4 prescaler - 10 - 2 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - IC3F - Input capture 3 filter - 4 - 4 - - - IC3PSC - Input capture 3 prescaler - 2 - 2 - - - CC3S - Capture/compare 3 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC4P - Capture/Compare 3 output - Polarity - 13 - 1 - - - CC4E - Capture/Compare 4 output - enable - 12 - 1 - - - CC3NP - Capture/Compare 3 output - Polarity - 11 - 1 - - - CC3NE - Capture/Compare 3 complementary output - enable - 10 - 1 - - - CC3P - Capture/Compare 3 output - Polarity - 9 - 1 - - - CC3E - Capture/Compare 3 output - enable - 8 - 1 - - - CC2NP - Capture/Compare 2 output - Polarity - 7 - 1 - - - CC2NE - Capture/Compare 2 complementary output - enable - 6 - 1 - - - CC2P - Capture/Compare 2 output - Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output - enable - 4 - 1 - - - CC1NP - Capture/Compare 1 output - Polarity - 3 - 1 - - - CC1NE - Capture/Compare 1 complementary output - enable - 2 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - CCR2 - CCR2 - capture/compare register 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - CCR2 - Capture/Compare 2 value - 0 - 16 - - - - - CCR3 - CCR3 - capture/compare register 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - CCR3 - Capture/Compare value - 0 - 16 - - - - - CCR4 - CCR4 - capture/compare register 4 - 0x40 - 0x20 - read-write - 0x00000000 - - - CCR4 - Capture/Compare value - 0 - 16 - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DBL - DMA burst length - 8 - 5 - - - DBA - DMA base address - 0 - 5 - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x0000 - - - DMAB - DMA register for burst - accesses - 0 - 16 - - - - - RCR - RCR - repetition counter register - 0x30 - 0x20 - read-write - 0x0000 - - - REP - Repetition counter value - 0 - 8 - - - - - BDTR - BDTR - break and dead-time register - 0x44 - 0x20 - read-write - 0x0000 - - - MOE - Main output enable - 15 - 1 - - - AOE - Automatic output enable - 14 - 1 - - - BKP - Break polarity - 13 - 1 - - - BKE - Break enable - 12 - 1 - - - OSSR - Off-state selection for Run - mode - 11 - 1 - - - OSSI - Off-state selection for Idle - mode - 10 - 1 - - - LOCK - Lock configuration - 8 - 2 - - - DTG - Dead-time generator setup - 0 - 8 - - - - - - - TIM8 - 0x40013400 - - TIM8_BRK_TIM12 - TIM8 Break interrupt and TIM12 global - interrupt - 43 - - - TIM8_UP_TIM13 - TIM8 Update interrupt and TIM13 global - interrupt - 44 - - - TIM8_TRG_COM_TIM14 - TIM8 Trigger and Commutation interrupts and - TIM14 global interrupt - 45 - - - TIM8_CC - TIM8 Capture Compare interrupt - 46 - - - - TIM2 - General purpose timer - TIM - 0x40000000 - - 0x0 - 0x400 - registers - - - TIM2 - TIM2 global interrupt - 28 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Clock division - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - CMS - Center-aligned mode - selection - 5 - 2 - - - DIR - Direction - 4 - 1 - - - OPM - One-pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TI1S - TI1 selection - 7 - 1 - - - MMS - Master mode selection - 4 - 3 - - - CCDS - Capture/compare DMA - selection - 3 - 1 - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x0000 - - - ETP - External trigger polarity - 15 - 1 - - - ECE - External clock enable - 14 - 1 - - - ETPS - External trigger prescaler - 12 - 2 - - - ETF - External trigger filter - 8 - 4 - - - MSM - Master/Slave mode - 7 - 1 - - - TS - Trigger selection - 4 - 3 - - - SMS - Slave mode selection - 0 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDE - Trigger DMA request enable - 14 - 1 - - - CC4DE - Capture/Compare 4 DMA request - enable - 12 - 1 - - - CC3DE - Capture/Compare 3 DMA request - enable - 11 - 1 - - - CC2DE - Capture/Compare 2 DMA request - enable - 10 - 1 - - - CC1DE - Capture/Compare 1 DMA request - enable - 9 - 1 - - - UDE - Update DMA request enable - 8 - 1 - - - TIE - Trigger interrupt enable - 6 - 1 - - - CC4IE - Capture/Compare 4 interrupt - enable - 4 - 1 - - - CC3IE - Capture/Compare 3 interrupt - enable - 3 - 1 - - - CC2IE - Capture/Compare 2 interrupt - enable - 2 - 1 - - - CC1IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC4OF - Capture/Compare 4 overcapture - flag - 12 - 1 - - - CC3OF - Capture/Compare 3 overcapture - flag - 11 - 1 - - - CC2OF - Capture/compare 2 overcapture - flag - 10 - 1 - - - CC1OF - Capture/Compare 1 overcapture - flag - 9 - 1 - - - TIF - Trigger interrupt flag - 6 - 1 - - - CC4IF - Capture/Compare 4 interrupt - flag - 4 - 1 - - - CC3IF - Capture/Compare 3 interrupt - flag - 3 - 1 - - - CC2IF - Capture/Compare 2 interrupt - flag - 2 - 1 - - - CC1IF - Capture/compare 1 interrupt - flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - TG - Trigger generation - 6 - 1 - - - CC4G - Capture/compare 4 - generation - 4 - 1 - - - CC3G - Capture/compare 3 - generation - 3 - 1 - - - CC2G - Capture/compare 2 - generation - 2 - 1 - - - CC1G - Capture/compare 1 - generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register 1 (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2CE - Output compare 2 clear - enable - 15 - 1 - - - OC2M - Output compare 2 mode - 12 - 3 - - - OC2PE - Output compare 2 preload - enable - 11 - 1 - - - OC2FE - Output compare 2 fast - enable - 10 - 1 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - OC1CE - Output compare 1 clear - enable - 7 - 1 - - - OC1M - Output compare 1 mode - 4 - 3 - - - OC1PE - Output compare 1 preload - enable - 3 - 1 - - - OC1FE - Output compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/compare 2 - selection - 8 - 2 - - - IC1F - Input capture 1 filter - 4 - 4 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR2_Output - CCMR2_Output - capture/compare mode register 2 (output - mode) - 0x1C - 0x20 - read-write - 0x00000000 - - - O24CE - Output compare 4 clear - enable - 15 - 1 - - - OC4M - Output compare 4 mode - 12 - 3 - - - OC4PE - Output compare 4 preload - enable - 11 - 1 - - - OC4FE - Output compare 4 fast - enable - 10 - 1 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - OC3CE - Output compare 3 clear - enable - 7 - 1 - - - OC3M - Output compare 3 mode - 4 - 3 - - - OC3PE - Output compare 3 preload - enable - 3 - 1 - - - OC3FE - Output compare 3 fast - enable - 2 - 1 - - - CC3S - Capture/Compare 3 - selection - 0 - 2 - - - - - CCMR2_Input - CCMR2_Input - capture/compare mode register 2 (input - mode) - CCMR2_Output - 0x1C - 0x20 - read-write - 0x00000000 - - - IC4F - Input capture 4 filter - 12 - 4 - - - IC4PSC - Input capture 4 prescaler - 10 - 2 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - IC3F - Input capture 3 filter - 4 - 4 - - - IC3PSC - Input capture 3 prescaler - 2 - 2 - - - CC3S - Capture/Compare 3 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC4P - Capture/Compare 3 output - Polarity - 13 - 1 - - - CC4E - Capture/Compare 4 output - enable - 12 - 1 - - - CC3P - Capture/Compare 3 output - Polarity - 9 - 1 - - - CC3E - Capture/Compare 3 output - enable - 8 - 1 - - - CC2P - Capture/Compare 2 output - Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output - enable - 4 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - CCR2 - CCR2 - capture/compare register 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - CCR2 - Capture/Compare 2 value - 0 - 16 - - - - - CCR3 - CCR3 - capture/compare register 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - CCR3 - Capture/Compare value - 0 - 16 - - - - - CCR4 - CCR4 - capture/compare register 4 - 0x40 - 0x20 - read-write - 0x00000000 - - - CCR4 - Capture/Compare value - 0 - 16 - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DBL - DMA burst length - 8 - 5 - - - DBA - DMA base address - 0 - 5 - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x0000 - - - DMAB - DMA register for burst - accesses - 0 - 16 - - - - - - - TIM3 - 0x40000400 - - TIM3 - TIM3 global interrupt - 29 - - - - TIM4 - 0x40000800 - - TIM4 - TIM4 global interrupt - 30 - - - - TIM5 - 0x40000C00 - - TIM5 - TIM5 global interrupt - 50 - - - - TIM9 - General purpose timer - TIM - 0x40014C00 - - 0x0 - 0x400 - registers - - - TIM1_BRK_TIM9 - TIM1 Break interrupt and TIM9 global - interrupt - 24 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Clock division - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - OPM - One-pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MMS - Master mode selection - 4 - 3 - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x0000 - - - MSM - Master/Slave mode - 7 - 1 - - - TS - Trigger selection - 4 - 3 - - - SMS - Slave mode selection - 0 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - TIE - Trigger interrupt enable - 6 - 1 - - - CC2IE - Capture/Compare 2 interrupt - enable - 2 - 1 - - - CC1IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC2OF - Capture/compare 2 overcapture - flag - 10 - 1 - - - CC1OF - Capture/Compare 1 overcapture - flag - 9 - 1 - - - TIF - Trigger interrupt flag - 6 - 1 - - - CC2IF - Capture/Compare 2 interrupt - flag - 2 - 1 - - - CC1IF - Capture/compare 1 interrupt - flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - TG - Trigger generation - 6 - 1 - - - CC2G - Capture/compare 2 - generation - 2 - 1 - - - CC1G - Capture/compare 1 - generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register 1 (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2M - Output Compare 2 mode - 12 - 3 - - - OC2PE - Output Compare 2 preload - enable - 11 - 1 - - - OC2FE - Output Compare 2 fast - enable - 10 - 1 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - OC1M - Output Compare 1 mode - 4 - 3 - - - OC1PE - Output Compare 1 preload - enable - 3 - 1 - - - OC1FE - Output Compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - IC1F - Input capture 1 filter - 4 - 4 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC2NP - Capture/Compare 2 output - Polarity - 7 - 1 - - - CC2P - Capture/Compare 2 output - Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output - enable - 4 - 1 - - - CC1NP - Capture/Compare 1 output - Polarity - 3 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - CCR2 - CCR2 - capture/compare register 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - CCR2 - Capture/Compare 2 value - 0 - 16 - - - - - - - TIM12 - 0x40001800 - - TIM8_BRK_TIM12 - TIM8 Break interrupt and TIM12 global - interrupt - 43 - - - - TIM10 - General purpose timer - TIM - 0x40015000 - - 0x0 - 0x400 - registers - - - TIM1_UP_TIM10 - TIM1 Update interrupt and TIM10 global - interrupt - 25 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Clock division - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MMS - Master mode selection - 4 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - CC1IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC1OF - Capture/Compare 1 overcapture - flag - 9 - 1 - - - CC1IF - Capture/compare 1 interrupt - flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - CC1G - Capture/compare 1 - generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC1M - Output Compare 1 mode - 4 - 3 - - - OC1PE - Output Compare 1 preload - enable - 3 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC1F - Input capture 1 filter - 4 - 4 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC1NP - Capture/Compare 1 output - Polarity - 3 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - - - TIM11 - 0x40015400 - - TIM1_TRG_COM_TIM11 - TIM1 Trigger and Commutation interrupts and - TIM11 global interrupt - 26 - - - - TIM13 - 0x40001C00 - - TIM8_UP_TIM13 - TIM8 Update interrupt and TIM13 global - interrupt - 44 - - - - TIM14 - 0x40002000 - - TIM8_TRG_COM_TIM14 - TIM8 Trigger and Commutation interrupts and - TIM14 global interrupt - 45 - - - - TIM6 - Basic timer - TIM - 0x40001000 - - 0x0 - 0x400 - registers - - - TIM6 - TIM6 global interrupt - 54 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - OPM - One-pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MMS - Master mode selection - 4 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - UDE - Update DMA request enable - 8 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - UG - Update generation - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - Low counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Low Auto-reload value - 0 - 16 - - - - - - - TIM7 - 0x40001400 - - TIM7 - TIM7 global interrupt - 55 - - - - I2C1 - Inter integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EV - I2C1 event interrupt - 31 - - - I2C1_ER - I2C1 error interrupt - 32 - - - - CR1 - CR1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SWRST - Software reset - 15 - 1 - - - ALERT - SMBus alert - 13 - 1 - - - PEC - Packet error checking - 12 - 1 - - - POS - Acknowledge/PEC Position (for data - reception) - 11 - 1 - - - ACK - Acknowledge enable - 10 - 1 - - - STOP - Stop generation - 9 - 1 - - - START - Start generation - 8 - 1 - - - NOSTRETCH - Clock stretching disable (Slave - mode) - 7 - 1 - - - ENGC - General call enable - 6 - 1 - - - ENPEC - PEC enable - 5 - 1 - - - ENARP - ARP enable - 4 - 1 - - - SMBTYPE - SMBus type - 3 - 1 - - - SMBUS - SMBus mode - 1 - 1 - - - PE - Peripheral enable - 0 - 1 - - - - - CR2 - CR2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - LAST - DMA last transfer - 12 - 1 - - - DMAEN - DMA requests enable - 11 - 1 - - - ITBUFEN - Buffer interrupt enable - 10 - 1 - - - ITEVTEN - Event interrupt enable - 9 - 1 - - - ITERREN - Error interrupt enable - 8 - 1 - - - FREQ - Peripheral clock frequency - 0 - 6 - - - - - OAR1 - OAR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - ADDMODE - Addressing mode (slave - mode) - 15 - 1 - - - ADD10 - Interface address - 8 - 2 - - - ADD7 - Interface address - 1 - 7 - - - ADD0 - Interface address - 0 - 1 - - - - - OAR2 - OAR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x0000 - - - ADD2 - Interface address - 1 - 7 - - - ENDUAL - Dual addressing mode - enable - 0 - 1 - - - - - DR - DR - Data register - 0x10 - 0x20 - read-write - 0x0000 - - - DR - 8-bit data register - 0 - 8 - - - - - SR1 - SR1 - Status register 1 - 0x14 - 0x20 - 0x0000 - - - SMBALERT - SMBus alert - 15 - 1 - read-write - - - TIMEOUT - Timeout or Tlow error - 14 - 1 - read-write - - - PECERR - PEC Error in reception - 12 - 1 - read-write - - - OVR - Overrun/Underrun - 11 - 1 - read-write - - - AF - Acknowledge failure - 10 - 1 - read-write - - - ARLO - Arbitration lost (master - mode) - 9 - 1 - read-write - - - BERR - Bus error - 8 - 1 - read-write - - - TxE - Data register empty - (transmitters) - 7 - 1 - read-only - - - RxNE - Data register not empty - (receivers) - 6 - 1 - read-only - - - STOPF - Stop detection (slave - mode) - 4 - 1 - read-only - - - ADD10 - 10-bit header sent (Master - mode) - 3 - 1 - read-only - - - BTF - Byte transfer finished - 2 - 1 - read-only - - - ADDR - Address sent (master mode)/matched - (slave mode) - 1 - 1 - read-only - - - SB - Start bit (Master mode) - 0 - 1 - read-only - - - - - SR2 - SR2 - Status register 2 - 0x18 - 0x20 - read-only - 0x0000 - - - PEC - acket error checking - register - 8 - 8 - - - DUALF - Dual flag (Slave mode) - 7 - 1 - - - SMBHOST - SMBus host header (Slave - mode) - 6 - 1 - - - SMBDEFAULT - SMBus device default address (Slave - mode) - 5 - 1 - - - GENCALL - General call address (Slave - mode) - 4 - 1 - - - TRA - Transmitter/receiver - 2 - 1 - - - BUSY - Bus busy - 1 - 1 - - - MSL - Master/slave - 0 - 1 - - - - - CCR - CCR - Clock control register - 0x1C - 0x20 - read-write - 0x0000 - - - F_S - I2C master mode selection - 15 - 1 - - - DUTY - Fast mode duty cycle - 14 - 1 - - - CCR - Clock control register in Fast/Standard - mode (Master mode) - 0 - 12 - - - - - TRISE - TRISE - TRISE register - 0x20 - 0x20 - read-write - 0x0002 - - - TRISE - Maximum rise time in Fast/Standard mode - (Master mode) - 0 - 6 - - - - - - - I2C2 - 0x40005800 - - I2C2_EV - I2C2 event interrupt - 33 - - - I2C2_ER - I2C2 error interrupt - 34 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - BIDIMODE - Bidirectional data mode - enable - 15 - 1 - - - BIDIOE - Output enable in bidirectional - mode - 14 - 1 - - - CRCEN - Hardware CRC calculation - enable - 13 - 1 - - - CRCNEXT - CRC transfer next - 12 - 1 - - - DFF - Data frame format - 11 - 1 - - - RXONLY - Receive only - 10 - 1 - - - SSM - Software slave management - 9 - 1 - - - SSI - Internal slave select - 8 - 1 - - - LSBFIRST - Frame format - 7 - 1 - - - SPE - SPI enable - 6 - 1 - - - BR - Baud rate control - 3 - 3 - - - MSTR - Master selection - 2 - 1 - - - CPOL - Clock polarity - 1 - 1 - - - CPHA - Clock phase - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TXEIE - Tx buffer empty interrupt - enable - 7 - 1 - - - RXNEIE - RX buffer not empty interrupt - enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - SSOE - SS output enable - 2 - 1 - - - TXDMAEN - Tx buffer DMA enable - 1 - 1 - - - RXDMAEN - Rx buffer DMA enable - 0 - 1 - - - - - SR - SR - status register - 0x8 - 0x20 - 0x0002 - - - BSY - Busy flag - 7 - 1 - read-only - - - OVR - Overrun flag - 6 - 1 - read-only - - - MODF - Mode fault - 5 - 1 - read-only - - - CRCERR - CRC error flag - 4 - 1 - read-write - - - UDR - Underrun flag - 3 - 1 - read-only - - - CHSIDE - Channel side - 2 - 1 - read-only - - - TXE - Transmit buffer empty - 1 - 1 - read-only - - - RXNE - Receive buffer not empty - 0 - 1 - read-only - - - - - DR - DR - data register - 0xC - 0x20 - read-write - 0x0000 - - - DR - Data register - 0 - 16 - - - - - CRCPR - CRCPR - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CRCPOLY - CRC polynomial register - 0 - 16 - - - - - RXCRCR - RXCRCR - RX CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RxCRC - Rx CRC register - 0 - 16 - - - - - TXCRCR - TXCRCR - TX CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TxCRC - Tx CRC register - 0 - 16 - - - - - I2SCFGR - I2SCFGR - I2S configuration register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMOD - I2S mode selection - 11 - 1 - - - I2SE - I2S Enable - 10 - 1 - - - I2SCFG - I2S configuration mode - 8 - 2 - - - PCMSYNC - PCM frame synchronization - 7 - 1 - - - I2SSTD - I2S standard selection - 4 - 2 - - - CKPOL - Steady state clock - polarity - 3 - 1 - - - DATLEN - Data length to be - transferred - 1 - 2 - - - CHLEN - Channel length (number of bits per audio - channel) - 0 - 1 - - - - - I2SPR - I2SPR - I2S prescaler register - 0x20 - 0x20 - read-write - 00000010 - - - MCKOE - Master clock output enable - 9 - 1 - - - ODD - Odd factor for the - prescaler - 8 - 1 - - - I2SDIV - I2S Linear prescaler - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - SPI3 - 0x40003C00 - - SPI3 - SPI3 global interrupt - 51 - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - SR - SR - Status register - 0x0 - 0x20 - 0x00C0 - - - CTS - CTS flag - 9 - 1 - read-write - - - LBD - LIN break detection flag - 8 - 1 - read-write - - - TXE - Transmit data register - empty - 7 - 1 - read-only - - - TC - Transmission complete - 6 - 1 - read-write - - - RXNE - Read data register not - empty - 5 - 1 - read-write - - - IDLE - IDLE line detected - 4 - 1 - read-only - - - ORE - Overrun error - 3 - 1 - read-only - - - NE - Noise error flag - 2 - 1 - read-only - - - FE - Framing error - 1 - 1 - read-only - - - PE - Parity error - 0 - 1 - read-only - - - - - DR - DR - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DR - Data value - 0 - 9 - - - - - BRR - BRR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV_Mantissa - mantissa of USARTDIV - 4 - 12 - - - DIV_Fraction - fraction of USARTDIV - 0 - 4 - - - - - CR1 - CR1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - UE - USART enable - 13 - 1 - - - M - Word length - 12 - 1 - - - WAKE - Wakeup method - 11 - 1 - - - PCE - Parity control enable - 10 - 1 - - - PS - Parity selection - 9 - 1 - - - PEIE - PE interrupt enable - 8 - 1 - - - TXEIE - TXE interrupt enable - 7 - 1 - - - TCIE - Transmission complete interrupt - enable - 6 - 1 - - - RXNEIE - RXNE interrupt enable - 5 - 1 - - - IDLEIE - IDLE interrupt enable - 4 - 1 - - - TE - Transmitter enable - 3 - 1 - - - RE - Receiver enable - 2 - 1 - - - RWU - Receiver wakeup - 1 - 1 - - - SBK - Send break - 0 - 1 - - - - - CR2 - CR2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - LINEN - LIN mode enable - 14 - 1 - - - STOP - STOP bits - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CPOL - Clock polarity - 10 - 1 - - - CPHA - Clock phase - 9 - 1 - - - LBCL - Last bit clock pulse - 8 - 1 - - - LBDIE - LIN break detection interrupt - enable - 6 - 1 - - - LBDL - lin break detection length - 5 - 1 - - - ADD - Address of the USART node - 0 - 4 - - - - - CR3 - CR3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - CTSIE - CTS interrupt enable - 10 - 1 - - - CTSE - CTS enable - 9 - 1 - - - RTSE - RTS enable - 8 - 1 - - - DMAT - DMA enable transmitter - 7 - 1 - - - DMAR - DMA enable receiver - 6 - 1 - - - SCEN - Smartcard mode enable - 5 - 1 - - - NACK - Smartcard NACK enable - 4 - 1 - - - HDSEL - Half-duplex selection - 3 - 1 - - - IRLP - IrDA low-power - 2 - 1 - - - IREN - IrDA mode enable - 1 - 1 - - - EIE - Error interrupt enable - 0 - 1 - - - - - GTPR - GTPR - Guard time and prescaler - register - 0x18 - 0x20 - read-write - 0x0000 - - - GT - Guard time value - 8 - 8 - - - PSC - Prescaler value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - ADC1 - Analog to digital converter - ADC - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC - ADC1 global interrupt - 18 - - - - SR - SR - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - STRT - Regular channel start flag - 4 - 1 - - - JSTRT - Injected channel start - flag - 3 - 1 - - - JEOC - Injected channel end of - conversion - 2 - 1 - - - EOC - Regular channel end of - conversion - 1 - 1 - - - AWD - Analog watchdog flag - 0 - 1 - - - - - CR1 - CR1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - AWDEN - Analog watchdog enable on regular - channels - 23 - 1 - - - JAWDEN - Analog watchdog enable on injected - channels - 22 - 1 - - - DUALMOD - Dual mode selection - 16 - 4 - - - DISCNUM - Discontinuous mode channel - count - 13 - 3 - - - JDISCEN - Discontinuous mode on injected - channels - 12 - 1 - - - DISCEN - Discontinuous mode on regular - channels - 11 - 1 - - - JAUTO - Automatic injected group - conversion - 10 - 1 - - - AWDSGL - Enable the watchdog on a single channel - in scan mode - 9 - 1 - - - SCAN - Scan mode - 8 - 1 - - - JEOCIE - Interrupt enable for injected - channels - 7 - 1 - - - AWDIE - Analog watchdog interrupt - enable - 6 - 1 - - - EOCIE - Interrupt enable for EOC - 5 - 1 - - - AWDCH - Analog watchdog channel select - bits - 0 - 5 - - - - - CR2 - CR2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - TSVREFE - Temperature sensor and VREFINT - enable - 23 - 1 - - - SWSTART - Start conversion of regular - channels - 22 - 1 - - - JSWSTART - Start conversion of injected - channels - 21 - 1 - - - EXTTRIG - External trigger conversion mode for - regular channels - 20 - 1 - - - EXTSEL - External event select for regular - group - 17 - 3 - - - JEXTTRIG - External trigger conversion mode for - injected channels - 15 - 1 - - - JEXTSEL - External event select for injected - group - 12 - 3 - - - ALIGN - Data alignment - 11 - 1 - - - DMA - Direct memory access mode - 8 - 1 - - - RSTCAL - Reset calibration - 3 - 1 - - - CAL - A/D calibration - 2 - 1 - - - CONT - Continuous conversion - 1 - 1 - - - ADON - A/D converter ON / OFF - 0 - 1 - - - - - SMPR1 - SMPR1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - SMP10 - Channel 10 sample time - selection - 0 - 3 - - - SMP11 - Channel 11 sample time - selection - 3 - 3 - - - SMP12 - Channel 12 sample time - selection - 6 - 3 - - - SMP13 - Channel 13 sample time - selection - 9 - 3 - - - SMP14 - Channel 14 sample time - selection - 12 - 3 - - - SMP15 - Channel 15 sample time - selection - 15 - 3 - - - SMP16 - Channel 16 sample time - selection - 18 - 3 - - - SMP17 - Channel 17 sample time - selection - 21 - 3 - - - - - SMPR2 - SMPR2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - SMP0 - Channel 0 sample time - selection - 0 - 3 - - - SMP1 - Channel 1 sample time - selection - 3 - 3 - - - SMP2 - Channel 2 sample time - selection - 6 - 3 - - - SMP3 - Channel 3 sample time - selection - 9 - 3 - - - SMP4 - Channel 4 sample time - selection - 12 - 3 - - - SMP5 - Channel 5 sample time - selection - 15 - 3 - - - SMP6 - Channel 6 sample time - selection - 18 - 3 - - - SMP7 - Channel 7 sample time - selection - 21 - 3 - - - SMP8 - Channel 8 sample time - selection - 24 - 3 - - - SMP9 - Channel 9 sample time - selection - 27 - 3 - - - - - JOFR1 - JOFR1 - injected channel data offset register - x - 0x14 - 0x20 - read-write - 0x00000000 - - - JOFFSET1 - Data offset for injected channel - x - 0 - 12 - - - - - JOFR2 - JOFR2 - injected channel data offset register - x - 0x18 - 0x20 - read-write - 0x00000000 - - - JOFFSET2 - Data offset for injected channel - x - 0 - 12 - - - - - JOFR3 - JOFR3 - injected channel data offset register - x - 0x1C - 0x20 - read-write - 0x00000000 - - - JOFFSET3 - Data offset for injected channel - x - 0 - 12 - - - - - JOFR4 - JOFR4 - injected channel data offset register - x - 0x20 - 0x20 - read-write - 0x00000000 - - - JOFFSET4 - Data offset for injected channel - x - 0 - 12 - - - - - HTR - HTR - watchdog higher threshold - register - 0x24 - 0x20 - read-write - 0x00000FFF - - - HT - Analog watchdog higher - threshold - 0 - 12 - - - - - LTR - LTR - watchdog lower threshold - register - 0x28 - 0x20 - read-write - 0x00000000 - - - LT - Analog watchdog lower - threshold - 0 - 12 - - - - - SQR1 - SQR1 - regular sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - L - Regular channel sequence - length - 20 - 4 - - - SQ16 - 16th conversion in regular - sequence - 15 - 5 - - - SQ15 - 15th conversion in regular - sequence - 10 - 5 - - - SQ14 - 14th conversion in regular - sequence - 5 - 5 - - - SQ13 - 13th conversion in regular - sequence - 0 - 5 - - - - - SQR2 - SQR2 - regular sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - SQ12 - 12th conversion in regular - sequence - 25 - 5 - - - SQ11 - 11th conversion in regular - sequence - 20 - 5 - - - SQ10 - 10th conversion in regular - sequence - 15 - 5 - - - SQ9 - 9th conversion in regular - sequence - 10 - 5 - - - SQ8 - 8th conversion in regular - sequence - 5 - 5 - - - SQ7 - 7th conversion in regular - sequence - 0 - 5 - - - - - SQR3 - SQR3 - regular sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - SQ6 - 6th conversion in regular - sequence - 25 - 5 - - - SQ5 - 5th conversion in regular - sequence - 20 - 5 - - - SQ4 - 4th conversion in regular - sequence - 15 - 5 - - - SQ3 - 3rd conversion in regular - sequence - 10 - 5 - - - SQ2 - 2nd conversion in regular - sequence - 5 - 5 - - - SQ1 - 1st conversion in regular - sequence - 0 - 5 - - - - - JSQR - JSQR - injected sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - JL - Injected sequence length - 20 - 2 - - - JSQ4 - 4th conversion in injected - sequence - 15 - 5 - - - JSQ3 - 3rd conversion in injected - sequence - 10 - 5 - - - JSQ2 - 2nd conversion in injected - sequence - 5 - 5 - - - JSQ1 - 1st conversion in injected - sequence - 0 - 5 - - - - - JDR1 - JDR1 - injected data register x - 0x3C - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - JDR2 - JDR2 - injected data register x - 0x40 - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - JDR3 - JDR3 - injected data register x - 0x44 - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - JDR4 - JDR4 - injected data register x - 0x48 - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - DR - DR - regular data register - 0x4C - 0x20 - read-only - 0x00000000 - - - DATA - Regular data - 0 - 16 - - - ADC2DATA - ADC2 data - 16 - 16 - - - - - - - ADC2 - Analog to digital converter - ADC - 0x40012800 - - 0x0 - 0x400 - registers - - - ADC - ADC2 global interrupt - 18 - - - - SR - SR - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - STRT - Regular channel start flag - 4 - 1 - - - JSTRT - Injected channel start - flag - 3 - 1 - - - JEOC - Injected channel end of - conversion - 2 - 1 - - - EOC - Regular channel end of - conversion - 1 - 1 - - - AWD - Analog watchdog flag - 0 - 1 - - - - - CR1 - CR1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - AWDEN - Analog watchdog enable on regular - channels - 23 - 1 - - - JAWDEN - Analog watchdog enable on injected - channels - 22 - 1 - - - DISCNUM - Discontinuous mode channel - count - 13 - 3 - - - JDISCEN - Discontinuous mode on injected - channels - 12 - 1 - - - DISCEN - Discontinuous mode on regular - channels - 11 - 1 - - - JAUTO - Automatic injected group - conversion - 10 - 1 - - - AWDSGL - Enable the watchdog on a single channel - in scan mode - 9 - 1 - - - SCAN - Scan mode - 8 - 1 - - - JEOCIE - Interrupt enable for injected - channels - 7 - 1 - - - AWDIE - Analog watchdog interrupt - enable - 6 - 1 - - - EOCIE - Interrupt enable for EOC - 5 - 1 - - - AWDCH - Analog watchdog channel select - bits - 0 - 5 - - - - - CR2 - CR2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - TSVREFE - Temperature sensor and VREFINT - enable - 23 - 1 - - - SWSTART - Start conversion of regular - channels - 22 - 1 - - - JSWSTART - Start conversion of injected - channels - 21 - 1 - - - EXTTRIG - External trigger conversion mode for - regular channels - 20 - 1 - - - EXTSEL - External event select for regular - group - 17 - 3 - - - JEXTTRIG - External trigger conversion mode for - injected channels - 15 - 1 - - - JEXTSEL - External event select for injected - group - 12 - 3 - - - ALIGN - Data alignment - 11 - 1 - - - DMA - Direct memory access mode - 8 - 1 - - - RSTCAL - Reset calibration - 3 - 1 - - - CAL - A/D calibration - 2 - 1 - - - CONT - Continuous conversion - 1 - 1 - - - ADON - A/D converter ON / OFF - 0 - 1 - - - - - SMPR1 - SMPR1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - SMP10 - Channel 10 sample time - selection - 0 - 3 - - - SMP11 - Channel 11 sample time - selection - 3 - 3 - - - SMP12 - Channel 12 sample time - selection - 6 - 3 - - - SMP13 - Channel 13 sample time - selection - 9 - 3 - - - SMP14 - Channel 14 sample time - selection - 12 - 3 - - - SMP15 - Channel 15 sample time - selection - 15 - 3 - - - SMP16 - Channel 16 sample time - selection - 18 - 3 - - - SMP17 - Channel 17 sample time - selection - 21 - 3 - - - - - SMPR2 - SMPR2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - SMP0 - Channel 0 sample time - selection - 0 - 3 - - - SMP1 - Channel 1 sample time - selection - 3 - 3 - - - SMP2 - Channel 2 sample time - selection - 6 - 3 - - - SMP3 - Channel 3 sample time - selection - 9 - 3 - - - SMP4 - Channel 4 sample time - selection - 12 - 3 - - - SMP5 - Channel 5 sample time - selection - 15 - 3 - - - SMP6 - Channel 6 sample time - selection - 18 - 3 - - - SMP7 - Channel 7 sample time - selection - 21 - 3 - - - SMP8 - Channel 8 sample time - selection - 24 - 3 - - - SMP9 - Channel 9 sample time - selection - 27 - 3 - - - - - JOFR1 - JOFR1 - injected channel data offset register - x - 0x14 - 0x20 - read-write - 0x00000000 - - - JOFFSET1 - Data offset for injected channel - x - 0 - 12 - - - - - JOFR2 - JOFR2 - injected channel data offset register - x - 0x18 - 0x20 - read-write - 0x00000000 - - - JOFFSET2 - Data offset for injected channel - x - 0 - 12 - - - - - JOFR3 - JOFR3 - injected channel data offset register - x - 0x1C - 0x20 - read-write - 0x00000000 - - - JOFFSET3 - Data offset for injected channel - x - 0 - 12 - - - - - JOFR4 - JOFR4 - injected channel data offset register - x - 0x20 - 0x20 - read-write - 0x00000000 - - - JOFFSET4 - Data offset for injected channel - x - 0 - 12 - - - - - HTR - HTR - watchdog higher threshold - register - 0x24 - 0x20 - read-write - 0x00000FFF - - - HT - Analog watchdog higher - threshold - 0 - 12 - - - - - LTR - LTR - watchdog lower threshold - register - 0x28 - 0x20 - read-write - 0x00000000 - - - LT - Analog watchdog lower - threshold - 0 - 12 - - - - - SQR1 - SQR1 - regular sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - L - Regular channel sequence - length - 20 - 4 - - - SQ16 - 16th conversion in regular - sequence - 15 - 5 - - - SQ15 - 15th conversion in regular - sequence - 10 - 5 - - - SQ14 - 14th conversion in regular - sequence - 5 - 5 - - - SQ13 - 13th conversion in regular - sequence - 0 - 5 - - - - - SQR2 - SQR2 - regular sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - SQ12 - 12th conversion in regular - sequence - 25 - 5 - - - SQ11 - 11th conversion in regular - sequence - 20 - 5 - - - SQ10 - 10th conversion in regular - sequence - 15 - 5 - - - SQ9 - 9th conversion in regular - sequence - 10 - 5 - - - SQ8 - 8th conversion in regular - sequence - 5 - 5 - - - SQ7 - 7th conversion in regular - sequence - 0 - 5 - - - - - SQR3 - SQR3 - regular sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - SQ6 - 6th conversion in regular - sequence - 25 - 5 - - - SQ5 - 5th conversion in regular - sequence - 20 - 5 - - - SQ4 - 4th conversion in regular - sequence - 15 - 5 - - - SQ3 - 3rd conversion in regular - sequence - 10 - 5 - - - SQ2 - 2nd conversion in regular - sequence - 5 - 5 - - - SQ1 - 1st conversion in regular - sequence - 0 - 5 - - - - - JSQR - JSQR - injected sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - JL - Injected sequence length - 20 - 2 - - - JSQ4 - 4th conversion in injected - sequence - 15 - 5 - - - JSQ3 - 3rd conversion in injected - sequence - 10 - 5 - - - JSQ2 - 2nd conversion in injected - sequence - 5 - 5 - - - JSQ1 - 1st conversion in injected - sequence - 0 - 5 - - - - - JDR1 - JDR1 - injected data register x - 0x3C - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - JDR2 - JDR2 - injected data register x - 0x40 - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - JDR3 - JDR3 - injected data register x - 0x44 - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - JDR4 - JDR4 - injected data register x - 0x48 - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - DR - DR - regular data register - 0x4C - 0x20 - read-only - 0x00000000 - - - DATA - Regular data - 0 - 16 - - - - - - - ADC3 - 0x40013C00 - - ADC3 - ADC3 global interrupt - 47 - - - - CAN - Controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN1_TX - CAN1 TX interrupts - 19 - - - CAN1_RX0 - CAN1 RX0 interrupts - 20 - - - CAN1_RX1 - CAN1 RX1 interrupt - 21 - - - CAN1_SCE - CAN1 SCE interrupt - 22 - - - - CAN_MCR - CAN_MCR - CAN_MCR - 0x0 - 0x20 - read-write - 0x00000000 - - - DBF - DBF - 16 - 1 - - - RESET - RESET - 15 - 1 - - - TTCM - TTCM - 7 - 1 - - - ABOM - ABOM - 6 - 1 - - - AWUM - AWUM - 5 - 1 - - - NART - NART - 4 - 1 - - - RFLM - RFLM - 3 - 1 - - - TXFP - TXFP - 2 - 1 - - - SLEEP - SLEEP - 1 - 1 - - - INRQ - INRQ - 0 - 1 - - - - - CAN_MSR - CAN_MSR - CAN_MSR - 0x4 - 0x20 - 0x00000000 - - - RX - RX - 11 - 1 - read-only - - - SAMP - SAMP - 10 - 1 - read-only - - - RXM - RXM - 9 - 1 - read-only - - - TXM - TXM - 8 - 1 - read-only - - - SLAKI - SLAKI - 4 - 1 - read-write - - - WKUI - WKUI - 3 - 1 - read-write - - - ERRI - ERRI - 2 - 1 - read-write - - - SLAK - SLAK - 1 - 1 - read-only - - - INAK - INAK - 0 - 1 - read-only - - - - - CAN_TSR - CAN_TSR - CAN_TSR - 0x8 - 0x20 - 0x00000000 - - - LOW2 - Lowest priority flag for mailbox - 2 - 31 - 1 - read-only - - - LOW1 - Lowest priority flag for mailbox - 1 - 30 - 1 - read-only - - - LOW0 - Lowest priority flag for mailbox - 0 - 29 - 1 - read-only - - - TME2 - Lowest priority flag for mailbox - 2 - 28 - 1 - read-only - - - TME1 - Lowest priority flag for mailbox - 1 - 27 - 1 - read-only - - - TME0 - Lowest priority flag for mailbox - 0 - 26 - 1 - read-only - - - CODE - CODE - 24 - 2 - read-only - - - ABRQ2 - ABRQ2 - 23 - 1 - read-write - - - TERR2 - TERR2 - 19 - 1 - read-write - - - ALST2 - ALST2 - 18 - 1 - read-write - - - TXOK2 - TXOK2 - 17 - 1 - read-write - - - RQCP2 - RQCP2 - 16 - 1 - read-write - - - ABRQ1 - ABRQ1 - 15 - 1 - read-write - - - TERR1 - TERR1 - 11 - 1 - read-write - - - ALST1 - ALST1 - 10 - 1 - read-write - - - TXOK1 - TXOK1 - 9 - 1 - read-write - - - RQCP1 - RQCP1 - 8 - 1 - read-write - - - ABRQ0 - ABRQ0 - 7 - 1 - read-write - - - TERR0 - TERR0 - 3 - 1 - read-write - - - ALST0 - ALST0 - 2 - 1 - read-write - - - TXOK0 - TXOK0 - 1 - 1 - read-write - - - RQCP0 - RQCP0 - 0 - 1 - read-write - - - - - CAN_RF0R - CAN_RF0R - CAN_RF0R - 0xC - 0x20 - 0x00000000 - - - RFOM0 - RFOM0 - 5 - 1 - read-write - - - FOVR0 - FOVR0 - 4 - 1 - read-write - - - FULL0 - FULL0 - 3 - 1 - read-write - - - FMP0 - FMP0 - 0 - 2 - read-only - - - - - CAN_RF1R - CAN_RF1R - CAN_RF1R - 0x10 - 0x20 - 0x00000000 - - - RFOM1 - RFOM1 - 5 - 1 - read-write - - - FOVR1 - FOVR1 - 4 - 1 - read-write - - - FULL1 - FULL1 - 3 - 1 - read-write - - - FMP1 - FMP1 - 0 - 2 - read-only - - - - - CAN_IER - CAN_IER - CAN_IER - 0x14 - 0x20 - read-write - 0x00000000 - - - SLKIE - SLKIE - 17 - 1 - - - WKUIE - WKUIE - 16 - 1 - - - ERRIE - ERRIE - 15 - 1 - - - LECIE - LECIE - 11 - 1 - - - BOFIE - BOFIE - 10 - 1 - - - EPVIE - EPVIE - 9 - 1 - - - EWGIE - EWGIE - 8 - 1 - - - FOVIE1 - FOVIE1 - 6 - 1 - - - FFIE1 - FFIE1 - 5 - 1 - - - FMPIE1 - FMPIE1 - 4 - 1 - - - FOVIE0 - FOVIE0 - 3 - 1 - - - FFIE0 - FFIE0 - 2 - 1 - - - FMPIE0 - FMPIE0 - 1 - 1 - - - TMEIE - TMEIE - 0 - 1 - - - - - CAN_ESR - CAN_ESR - CAN_ESR - 0x18 - 0x20 - 0x00000000 - - - REC - REC - 24 - 8 - read-only - - - TEC - TEC - 16 - 8 - read-only - - - LEC - LEC - 4 - 3 - read-write - - - BOFF - BOFF - 2 - 1 - read-only - - - EPVF - EPVF - 1 - 1 - read-only - - - EWGF - EWGF - 0 - 1 - read-only - - - - - CAN_BTR - CAN_BTR - CAN_BTR - 0x1C - 0x20 - read-write - 0x00000000 - - - SILM - SILM - 31 - 1 - - - LBKM - LBKM - 30 - 1 - - - SJW - SJW - 24 - 2 - - - TS2 - TS2 - 20 - 3 - - - TS1 - TS1 - 16 - 4 - - - BRP - BRP - 0 - 10 - - - - - CAN_TI0R - CAN_TI0R - CAN_TI0R - 0x180 - 0x20 - read-write - 0x00000000 - - - STID - STID - 21 - 11 - - - EXID - EXID - 3 - 18 - - - IDE - IDE - 2 - 1 - - - RTR - RTR - 1 - 1 - - - TXRQ - TXRQ - 0 - 1 - - - - - CAN_TDT0R - CAN_TDT0R - CAN_TDT0R - 0x184 - 0x20 - read-write - 0x00000000 - - - TIME - TIME - 16 - 16 - - - TGT - TGT - 8 - 1 - - - DLC - DLC - 0 - 4 - - - - - CAN_TDL0R - CAN_TDL0R - CAN_TDL0R - 0x188 - 0x20 - read-write - 0x00000000 - - - DATA3 - DATA3 - 24 - 8 - - - DATA2 - DATA2 - 16 - 8 - - - DATA1 - DATA1 - 8 - 8 - - - DATA0 - DATA0 - 0 - 8 - - - - - CAN_TDH0R - CAN_TDH0R - CAN_TDH0R - 0x18C - 0x20 - read-write - 0x00000000 - - - DATA7 - DATA7 - 24 - 8 - - - DATA6 - DATA6 - 16 - 8 - - - DATA5 - DATA5 - 8 - 8 - - - DATA4 - DATA4 - 0 - 8 - - - - - CAN_TI1R - CAN_TI1R - CAN_TI1R - 0x190 - 0x20 - read-write - 0x00000000 - - - STID - STID - 21 - 11 - - - EXID - EXID - 3 - 18 - - - IDE - IDE - 2 - 1 - - - RTR - RTR - 1 - 1 - - - TXRQ - TXRQ - 0 - 1 - - - - - CAN_TDT1R - CAN_TDT1R - CAN_TDT1R - 0x194 - 0x20 - read-write - 0x00000000 - - - TIME - TIME - 16 - 16 - - - TGT - TGT - 8 - 1 - - - DLC - DLC - 0 - 4 - - - - - CAN_TDL1R - CAN_TDL1R - CAN_TDL1R - 0x198 - 0x20 - read-write - 0x00000000 - - - DATA3 - DATA3 - 24 - 8 - - - DATA2 - DATA2 - 16 - 8 - - - DATA1 - DATA1 - 8 - 8 - - - DATA0 - DATA0 - 0 - 8 - - - - - CAN_TDH1R - CAN_TDH1R - CAN_TDH1R - 0x19C - 0x20 - read-write - 0x00000000 - - - DATA7 - DATA7 - 24 - 8 - - - DATA6 - DATA6 - 16 - 8 - - - DATA5 - DATA5 - 8 - 8 - - - DATA4 - DATA4 - 0 - 8 - - - - - CAN_TI2R - CAN_TI2R - CAN_TI2R - 0x1A0 - 0x20 - read-write - 0x00000000 - - - STID - STID - 21 - 11 - - - EXID - EXID - 3 - 18 - - - IDE - IDE - 2 - 1 - - - RTR - RTR - 1 - 1 - - - TXRQ - TXRQ - 0 - 1 - - - - - CAN_TDT2R - CAN_TDT2R - CAN_TDT2R - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TIME - TIME - 16 - 16 - - - TGT - TGT - 8 - 1 - - - DLC - DLC - 0 - 4 - - - - - CAN_TDL2R - CAN_TDL2R - CAN_TDL2R - 0x1A8 - 0x20 - read-write - 0x00000000 - - - DATA3 - DATA3 - 24 - 8 - - - DATA2 - DATA2 - 16 - 8 - - - DATA1 - DATA1 - 8 - 8 - - - DATA0 - DATA0 - 0 - 8 - - - - - CAN_TDH2R - CAN_TDH2R - CAN_TDH2R - 0x1AC - 0x20 - read-write - 0x00000000 - - - DATA7 - DATA7 - 24 - 8 - - - DATA6 - DATA6 - 16 - 8 - - - DATA5 - DATA5 - 8 - 8 - - - DATA4 - DATA4 - 0 - 8 - - - - - CAN_RI0R - CAN_RI0R - CAN_RI0R - 0x1B0 - 0x20 - read-only - 0x00000000 - - - STID - STID - 21 - 11 - - - EXID - EXID - 3 - 18 - - - IDE - IDE - 2 - 1 - - - RTR - RTR - 1 - 1 - - - - - CAN_RDT0R - CAN_RDT0R - CAN_RDT0R - 0x1B4 - 0x20 - read-only - 0x00000000 - - - TIME - TIME - 16 - 16 - - - FMI - FMI - 8 - 8 - - - DLC - DLC - 0 - 4 - - - - - CAN_RDL0R - CAN_RDL0R - CAN_RDL0R - 0x1B8 - 0x20 - read-only - 0x00000000 - - - DATA3 - DATA3 - 24 - 8 - - - DATA2 - DATA2 - 16 - 8 - - - DATA1 - DATA1 - 8 - 8 - - - DATA0 - DATA0 - 0 - 8 - - - - - CAN_RDH0R - CAN_RDH0R - CAN_RDH0R - 0x1BC - 0x20 - read-only - 0x00000000 - - - DATA7 - DATA7 - 24 - 8 - - - DATA6 - DATA6 - 16 - 8 - - - DATA5 - DATA5 - 8 - 8 - - - DATA4 - DATA4 - 0 - 8 - - - - - CAN_RI1R - CAN_RI1R - CAN_RI1R - 0x1C0 - 0x20 - read-only - 0x00000000 - - - STID - STID - 21 - 11 - - - EXID - EXID - 3 - 18 - - - IDE - IDE - 2 - 1 - - - RTR - RTR - 1 - 1 - - - - - CAN_RDT1R - CAN_RDT1R - CAN_RDT1R - 0x1C4 - 0x20 - read-only - 0x00000000 - - - TIME - TIME - 16 - 16 - - - FMI - FMI - 8 - 8 - - - DLC - DLC - 0 - 4 - - - - - CAN_RDL1R - CAN_RDL1R - CAN_RDL1R - 0x1C8 - 0x20 - read-only - 0x00000000 - - - DATA3 - DATA3 - 24 - 8 - - - DATA2 - DATA2 - 16 - 8 - - - DATA1 - DATA1 - 8 - 8 - - - DATA0 - DATA0 - 0 - 8 - - - - - CAN_RDH1R - CAN_RDH1R - CAN_RDH1R - 0x1CC - 0x20 - read-only - 0x00000000 - - - DATA7 - DATA7 - 24 - 8 - - - DATA6 - DATA6 - 16 - 8 - - - DATA5 - DATA5 - 8 - 8 - - - DATA4 - DATA4 - 0 - 8 - - - - - CAN_FMR - CAN_FMR - CAN_FMR - 0x200 - 0x20 - read-write - 0x00000000 - - - FINIT - FINIT - 0 - 1 - - - - - CAN_FM1R - CAN_FM1R - CAN_FM1R - 0x204 - 0x20 - read-write - 0x00000000 - - - FBM0 - Filter mode - 0 - 1 - - - FBM1 - Filter mode - 1 - 1 - - - FBM2 - Filter mode - 2 - 1 - - - FBM3 - Filter mode - 3 - 1 - - - FBM4 - Filter mode - 4 - 1 - - - FBM5 - Filter mode - 5 - 1 - - - FBM6 - Filter mode - 6 - 1 - - - FBM7 - Filter mode - 7 - 1 - - - FBM8 - Filter mode - 8 - 1 - - - FBM9 - Filter mode - 9 - 1 - - - FBM10 - Filter mode - 10 - 1 - - - FBM11 - Filter mode - 11 - 1 - - - FBM12 - Filter mode - 12 - 1 - - - FBM13 - Filter mode - 13 - 1 - - - - - CAN_FS1R - CAN_FS1R - CAN_FS1R - 0x20C - 0x20 - read-write - 0x00000000 - - - FSC0 - Filter scale configuration - 0 - 1 - - - FSC1 - Filter scale configuration - 1 - 1 - - - FSC2 - Filter scale configuration - 2 - 1 - - - FSC3 - Filter scale configuration - 3 - 1 - - - FSC4 - Filter scale configuration - 4 - 1 - - - FSC5 - Filter scale configuration - 5 - 1 - - - FSC6 - Filter scale configuration - 6 - 1 - - - FSC7 - Filter scale configuration - 7 - 1 - - - FSC8 - Filter scale configuration - 8 - 1 - - - FSC9 - Filter scale configuration - 9 - 1 - - - FSC10 - Filter scale configuration - 10 - 1 - - - FSC11 - Filter scale configuration - 11 - 1 - - - FSC12 - Filter scale configuration - 12 - 1 - - - FSC13 - Filter scale configuration - 13 - 1 - - - - - CAN_FFA1R - CAN_FFA1R - CAN_FFA1R - 0x214 - 0x20 - read-write - 0x00000000 - - - FFA0 - Filter FIFO assignment for filter - 0 - 0 - 1 - - - FFA1 - Filter FIFO assignment for filter - 1 - 1 - 1 - - - FFA2 - Filter FIFO assignment for filter - 2 - 2 - 1 - - - FFA3 - Filter FIFO assignment for filter - 3 - 3 - 1 - - - FFA4 - Filter FIFO assignment for filter - 4 - 4 - 1 - - - FFA5 - Filter FIFO assignment for filter - 5 - 5 - 1 - - - FFA6 - Filter FIFO assignment for filter - 6 - 6 - 1 - - - FFA7 - Filter FIFO assignment for filter - 7 - 7 - 1 - - - FFA8 - Filter FIFO assignment for filter - 8 - 8 - 1 - - - FFA9 - Filter FIFO assignment for filter - 9 - 9 - 1 - - - FFA10 - Filter FIFO assignment for filter - 10 - 10 - 1 - - - FFA11 - Filter FIFO assignment for filter - 11 - 11 - 1 - - - FFA12 - Filter FIFO assignment for filter - 12 - 12 - 1 - - - FFA13 - Filter FIFO assignment for filter - 13 - 13 - 1 - - - - - CAN_FA1R - CAN_FA1R - CAN_FA1R - 0x21C - 0x20 - read-write - 0x00000000 - - - FACT0 - Filter active - 0 - 1 - - - FACT1 - Filter active - 1 - 1 - - - FACT2 - Filter active - 2 - 1 - - - FACT3 - Filter active - 3 - 1 - - - FACT4 - Filter active - 4 - 1 - - - FACT5 - Filter active - 5 - 1 - - - FACT6 - Filter active - 6 - 1 - - - FACT7 - Filter active - 7 - 1 - - - FACT8 - Filter active - 8 - 1 - - - FACT9 - Filter active - 9 - 1 - - - FACT10 - Filter active - 10 - 1 - - - FACT11 - Filter active - 11 - 1 - - - FACT12 - Filter active - 12 - 1 - - - FACT13 - Filter active - 13 - 1 - - - - - F0R1 - F0R1 - Filter bank 0 register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F0R2 - F0R2 - Filter bank 0 register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F1R1 - F1R1 - Filter bank 1 register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F1R2 - F1R2 - Filter bank 1 register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F2R1 - F2R1 - Filter bank 2 register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F2R2 - F2R2 - Filter bank 2 register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F3R1 - F3R1 - Filter bank 3 register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F3R2 - F3R2 - Filter bank 3 register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F4R1 - F4R1 - Filter bank 4 register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F4R2 - F4R2 - Filter bank 4 register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F5R1 - F5R1 - Filter bank 5 register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F5R2 - F5R2 - Filter bank 5 register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F6R1 - F6R1 - Filter bank 6 register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F6R2 - F6R2 - Filter bank 6 register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - - F7R1 - F7R1 - Filter bank 7 register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F7R2 - F7R2 - Filter bank 7 register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F8R1 - F8R1 - Filter bank 8 register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F8R2 - F8R2 - Filter bank 8 register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F9R1 - F9R1 - Filter bank 9 register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F9R2 - F9R2 - Filter bank 9 register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F10R1 - F10R1 - Filter bank 10 register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F10R2 - F10R2 - Filter bank 10 register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F11R1 - F11R1 - Filter bank 11 register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F11R2 - F11R2 - Filter bank 11 register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F12R1 - F12R1 - Filter bank 4 register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F12R2 - F12R2 - Filter bank 12 register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F13R1 - F13R1 - Filter bank 13 register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F13R2 - F13R2 - Filter bank 13 register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - - - DAC - Digital to analog converter - DAC - 0x40007400 - - 0x0 - 0x400 - registers - - - - CR - CR - Control register (DAC_CR) - 0x0 - 0x20 - read-write - 0x00000000 - - - EN1 - DAC channel1 enable - 0 - 1 - - - BOFF1 - DAC channel1 output buffer - disable - 1 - 1 - - - TEN1 - DAC channel1 trigger - enable - 2 - 1 - - - TSEL1 - DAC channel1 trigger - selection - 3 - 3 - - - WAVE1 - DAC channel1 noise/triangle wave - generation enable - 6 - 2 - - - MAMP1 - DAC channel1 mask/amplitude - selector - 8 - 4 - - - DMAEN1 - DAC channel1 DMA enable - 12 - 1 - - - EN2 - DAC channel2 enable - 16 - 1 - - - BOFF2 - DAC channel2 output buffer - disable - 17 - 1 - - - TEN2 - DAC channel2 trigger - enable - 18 - 1 - - - TSEL2 - DAC channel2 trigger - selection - 19 - 3 - - - WAVE2 - DAC channel2 noise/triangle wave - generation enable - 22 - 2 - - - MAMP2 - DAC channel2 mask/amplitude - selector - 24 - 4 - - - DMAEN2 - DAC channel2 DMA enable - 28 - 1 - - - - - SWTRIGR - SWTRIGR - DAC software trigger register - (DAC_SWTRIGR) - 0x4 - 0x20 - write-only - 0x00000000 - - - SWTRIG1 - DAC channel1 software - trigger - 0 - 1 - - - SWTRIG2 - DAC channel2 software - trigger - 1 - 1 - - - - - DHR12R1 - DHR12R1 - DAC channel1 12-bit right-aligned data - holding register(DAC_DHR12R1) - 0x8 - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 12-bit right-aligned - data - 0 - 12 - - - - - DHR12L1 - DHR12L1 - DAC channel1 12-bit left aligned data - holding register (DAC_DHR12L1) - 0xC - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 12-bit left-aligned - data - 4 - 12 - - - - - DHR8R1 - DHR8R1 - DAC channel1 8-bit right aligned data - holding register (DAC_DHR8R1) - 0x10 - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 8-bit right-aligned - data - 0 - 8 - - - - - DHR12R2 - DHR12R2 - DAC channel2 12-bit right aligned data - holding register (DAC_DHR12R2) - 0x14 - 0x20 - read-write - 0x00000000 - - - DACC2DHR - DAC channel2 12-bit right-aligned - data - 0 - 12 - - - - - DHR12L2 - DHR12L2 - DAC channel2 12-bit left aligned data - holding register (DAC_DHR12L2) - 0x18 - 0x20 - read-write - 0x00000000 - - - DACC2DHR - DAC channel2 12-bit left-aligned - data - 4 - 12 - - - - - DHR8R2 - DHR8R2 - DAC channel2 8-bit right-aligned data - holding register (DAC_DHR8R2) - 0x1C - 0x20 - read-write - 0x00000000 - - - DACC2DHR - DAC channel2 8-bit right-aligned - data - 0 - 8 - - - - - DHR12RD - DHR12RD - Dual DAC 12-bit right-aligned data holding - register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 - Reserved - 0x20 - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 12-bit right-aligned - data - 0 - 12 - - - DACC2DHR - DAC channel2 12-bit right-aligned - data - 16 - 12 - - - - - DHR12LD - DHR12LD - DUAL DAC 12-bit left aligned data holding - register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 - Reserved - 0x24 - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 12-bit left-aligned - data - 4 - 12 - - - DACC2DHR - DAC channel2 12-bit right-aligned - data - 20 - 12 - - - - - DHR8RD - DHR8RD - DUAL DAC 8-bit right aligned data holding - register (DAC_DHR8RD), Bits 31:16 Reserved - 0x28 - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 8-bit right-aligned - data - 0 - 8 - - - DACC2DHR - DAC channel2 8-bit right-aligned - data - 8 - 8 - - - - - DOR1 - DOR1 - DAC channel1 data output register - (DAC_DOR1) - 0x2C - 0x20 - read-only - 0x00000000 - - - DACC1DOR - DAC channel1 data output - 0 - 12 - - - - - DOR2 - DOR2 - DAC channel2 data output register - (DAC_DOR2) - 0x30 - 0x20 - read-only - 0x00000000 - - - DACC2DOR - DAC channel2 data output - 0 - 12 - - - - - - - DBG - Debug support - DBG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DBGMCU_IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - DEV_ID - DEV_ID - 0 - 12 - - - REV_ID - REV_ID - 16 - 16 - - - - - CR - CR - DBGMCU_CR - 0x4 - 0x20 - read-write - 0x0 - - - DBG_SLEEP - DBG_SLEEP - 0 - 1 - - - DBG_STOP - DBG_STOP - 1 - 1 - - - DBG_STANDBY - DBG_STANDBY - 2 - 1 - - - TRACE_IOEN - TRACE_IOEN - 5 - 1 - - - TRACE_MODE - TRACE_MODE - 6 - 2 - - - DBG_IWDG_STOP - DBG_IWDG_STOP - 8 - 1 - - - DBG_WWDG_STOP - DBG_WWDG_STOP - 9 - 1 - - - DBG_TIM1_STOP - DBG_TIM1_STOP - 10 - 1 - - - DBG_TIM2_STOP - DBG_TIM2_STOP - 11 - 1 - - - DBG_TIM3_STOP - DBG_TIM3_STOP - 12 - 1 - - - DBG_TIM4_STOP - DBG_TIM4_STOP - 13 - 1 - - - DBG_CAN1_STOP - DBG_CAN1_STOP - 14 - 1 - - - DBG_I2C1_SMBUS_TIMEOUT - DBG_I2C1_SMBUS_TIMEOUT - 15 - 1 - - - DBG_I2C2_SMBUS_TIMEOUT - DBG_I2C2_SMBUS_TIMEOUT - 16 - 1 - - - DBG_TIM8_STOP - DBG_TIM8_STOP - 17 - 1 - - - DBG_TIM5_STOP - DBG_TIM5_STOP - 18 - 1 - - - DBG_TIM6_STOP - DBG_TIM6_STOP - 19 - 1 - - - DBG_TIM7_STOP - DBG_TIM7_STOP - 20 - 1 - - - DBG_CAN2_STOP - DBG_CAN2_STOP - 21 - 1 - - - - - - - UART4 - Universal asynchronous receiver - transmitter - USART - 0x40004C00 - - 0x0 - 0x400 - registers - - - UART4 - UART4 global interrupt - 52 - - - - SR - SR - UART4_SR - 0x0 - 0x20 - 0x0 - - - PE - Parity error - 0 - 1 - read-only - - - FE - Framing error - 1 - 1 - read-only - - - NE - Noise error flag - 2 - 1 - read-only - - - ORE - Overrun error - 3 - 1 - read-only - - - IDLE - IDLE line detected - 4 - 1 - read-only - - - RXNE - Read data register not - empty - 5 - 1 - read-write - - - TC - Transmission complete - 6 - 1 - read-write - - - TXE - Transmit data register - empty - 7 - 1 - read-only - - - LBD - LIN break detection flag - 8 - 1 - read-write - - - - - DR - DR - UART4_DR - 0x4 - 0x20 - read-write - 0x0 - - - DR - DR - 0 - 9 - - - - - BRR - BRR - UART4_BRR - 0x8 - 0x20 - read-write - 0x0 - - - DIV_Fraction - DIV_Fraction - 0 - 4 - - - DIV_Mantissa - DIV_Mantissa - 4 - 12 - - - - - CR1 - CR1 - UART4_CR1 - 0xC - 0x20 - read-write - 0x0 - - - SBK - Send break - 0 - 1 - - - RWU - Receiver wakeup - 1 - 1 - - - RE - Receiver enable - 2 - 1 - - - TE - Transmitter enable - 3 - 1 - - - IDLEIE - IDLE interrupt enable - 4 - 1 - - - RXNEIE - RXNE interrupt enable - 5 - 1 - - - TCIE - Transmission complete interrupt - enable - 6 - 1 - - - TXEIE - TXE interrupt enable - 7 - 1 - - - PEIE - PE interrupt enable - 8 - 1 - - - PS - Parity selection - 9 - 1 - - - PCE - Parity control enable - 10 - 1 - - - WAKE - Wakeup method - 11 - 1 - - - M - Word length - 12 - 1 - - - UE - USART enable - 13 - 1 - - - - - CR2 - CR2 - UART4_CR2 - 0x10 - 0x20 - read-write - 0x0 - - - ADD - Address of the USART node - 0 - 4 - - - LBDL - lin break detection length - 5 - 1 - - - LBDIE - LIN break detection interrupt - enable - 6 - 1 - - - STOP - STOP bits - 12 - 2 - - - LINEN - LIN mode enable - 14 - 1 - - - - - CR3 - CR3 - UART4_CR3 - 0x14 - 0x20 - read-write - 0x0 - - - EIE - Error interrupt enable - 0 - 1 - - - IREN - IrDA mode enable - 1 - 1 - - - IRLP - IrDA low-power - 2 - 1 - - - HDSEL - Half-duplex selection - 3 - 1 - - - DMAR - DMA enable receiver - 6 - 1 - - - DMAT - DMA enable transmitter - 7 - 1 - - - - - - - UART5 - Universal asynchronous receiver - transmitter - USART - 0x40005000 - - 0x0 - 0x400 - registers - - - UART5 - UART5 global interrupt - 53 - - - - SR - SR - UART4_SR - 0x0 - 0x20 - 0x0 - - - PE - PE - 0 - 1 - read-only - - - FE - FE - 1 - 1 - read-only - - - NE - NE - 2 - 1 - read-only - - - ORE - ORE - 3 - 1 - read-only - - - IDLE - IDLE - 4 - 1 - read-only - - - RXNE - RXNE - 5 - 1 - read-write - - - TC - TC - 6 - 1 - read-write - - - TXE - TXE - 7 - 1 - read-only - - - LBD - LBD - 8 - 1 - read-write - - - - - DR - DR - UART4_DR - 0x4 - 0x20 - read-write - 0x0 - - - DR - DR - 0 - 9 - - - - - BRR - BRR - UART4_BRR - 0x8 - 0x20 - read-write - 0x0 - - - DIV_Fraction - DIV_Fraction - 0 - 4 - - - DIV_Mantissa - DIV_Mantissa - 4 - 12 - - - - - CR1 - CR1 - UART4_CR1 - 0xC - 0x20 - read-write - 0x0 - - - SBK - SBK - 0 - 1 - - - RWU - RWU - 1 - 1 - - - RE - RE - 2 - 1 - - - TE - TE - 3 - 1 - - - IDLEIE - IDLEIE - 4 - 1 - - - RXNEIE - RXNEIE - 5 - 1 - - - TCIE - TCIE - 6 - 1 - - - TXEIE - TXEIE - 7 - 1 - - - PEIE - PEIE - 8 - 1 - - - PS - PS - 9 - 1 - - - PCE - PCE - 10 - 1 - - - WAKE - WAKE - 11 - 1 - - - M - M - 12 - 1 - - - UE - UE - 13 - 1 - - - - - CR2 - CR2 - UART4_CR2 - 0x10 - 0x20 - read-write - 0x0 - - - ADD - ADD - 0 - 4 - - - LBDL - LBDL - 5 - 1 - - - LBDIE - LBDIE - 6 - 1 - - - STOP - STOP - 12 - 2 - - - LINEN - LINEN - 14 - 1 - - - - - CR3 - CR3 - UART4_CR3 - 0x14 - 0x20 - read-write - 0x0 - - - EIE - Error interrupt enable - 0 - 1 - - - IREN - IrDA mode enable - 1 - 1 - - - IRLP - IrDA low-power - 2 - 1 - - - HDSEL - Half-duplex selection - 3 - 1 - - - DMAT - DMA enable transmitter - 7 - 1 - - - - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DR - DR - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DR - Data Register - 0 - 32 - - - - - IDR - IDR - Independent Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - IDR - Independent Data register - 0 - 8 - - - - - CR - CR - Control register - 0x8 - 0x20 - write-only - 0x00000000 - - - RESET - Reset bit - 0 - 1 - - - - - - - FLASH - FLASH - FLASH - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - ACR - ACR - Flash access control register - 0x0 - 0x20 - 0x00000030 - - - LATENCY - Latency - 0 - 3 - read-write - - - HLFCYA - Flash half cycle access - enable - 3 - 1 - read-write - - - PRFTBE - Prefetch buffer enable - 4 - 1 - read-write - - - PRFTBS - Prefetch buffer status - 5 - 1 - read-only - - - - - KEYR - KEYR - Flash key register - 0x4 - 0x20 - write-only - 0x00000000 - - - KEY - FPEC key - 0 - 32 - - - - - OPTKEYR - OPTKEYR - Flash option key register - 0x8 - 0x20 - write-only - 0x00000000 - - - OPTKEY - Option byte key - 0 - 32 - - - - - SR - SR - Status register - 0xC - 0x20 - 0x00000000 - - - EOP - End of operation - 5 - 1 - read-write - - - WRPRTERR - Write protection error - 4 - 1 - read-write - - - PGERR - Programming error - 2 - 1 - read-write - - - BSY - Busy - 0 - 1 - read-only - - - - - CR - CR - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - PG - Programming - 0 - 1 - - - PER - Page Erase - 1 - 1 - - - MER - Mass Erase - 2 - 1 - - - OPTPG - Option byte programming - 4 - 1 - - - OPTER - Option byte erase - 5 - 1 - - - STRT - Start - 6 - 1 - - - LOCK - Lock - 7 - 1 - - - OPTWRE - Option bytes write enable - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - EOPIE - End of operation interrupt - enable - 12 - 1 - - - - - AR - AR - Flash address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FAR - Flash Address - 0 - 32 - - - - - OBR - OBR - Option byte register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - OPTERR - Option byte error - 0 - 1 - - - RDPRT - Read protection - 1 - 1 - - - WDG_SW - WDG_SW - 2 - 1 - - - nRST_STOP - nRST_STOP - 3 - 1 - - - nRST_STDBY - nRST_STDBY - 4 - 1 - - - Data0 - Data0 - 10 - 8 - - - Data1 - Data1 - 18 - 8 - - - - - WRPR - WRPR - Write protection register - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - WRP - Write protect - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - USB - Universal serial bus full-speed device - interface - USB - 0x40005C00 - - 0x0 - 0x400 - registers - - - USB_FS_WKUP - USB Device FS Wakeup through EXTI line - interrupt - 42 - - - - EP0R - EP0R - endpoint 0 register - 0x0 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP1R - EP1R - endpoint 1 register - 0x4 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP2R - EP2R - endpoint 2 register - 0x8 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP3R - EP3R - endpoint 3 register - 0xC - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP4R - EP4R - endpoint 4 register - 0x10 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP5R - EP5R - endpoint 5 register - 0x14 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP6R - EP6R - endpoint 6 register - 0x18 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP7R - EP7R - endpoint 7 register - 0x1C - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - CNTR - USB_CNTR - control register - 0x40 - 0x20 - read-write - 0x00000003 - - - FRES - Force USB Reset - 0 - 1 - - - PDWN - Power down - 1 - 1 - - - LPMODE - Low-power mode - 2 - 1 - - - FSUSP - Force suspend - 3 - 1 - - - RESUME - Resume request - 4 - 1 - - - ESOFM - Expected start of frame interrupt - mask - 8 - 1 - - - SOFM - Start of frame interrupt - mask - 9 - 1 - - - RESETM - USB reset interrupt mask - 10 - 1 - - - SUSPM - Suspend mode interrupt - mask - 11 - 1 - - - WKUPM - Wakeup interrupt mask - 12 - 1 - - - ERRM - Error interrupt mask - 13 - 1 - - - PMAOVRM - Packet memory area over / underrun - interrupt mask - 14 - 1 - - - CTRM - Correct transfer interrupt - mask - 15 - 1 - - - - - ISTR - ISTR - interrupt status register - 0x44 - 0x20 - read-write - 0x00000000 - - - EP_ID - Endpoint Identifier - 0 - 4 - - - DIR - Direction of transaction - 4 - 1 - - - ESOF - Expected start frame - 8 - 1 - - - SOF - start of frame - 9 - 1 - - - RESET - reset request - 10 - 1 - - - SUSP - Suspend mode request - 11 - 1 - - - WKUP - Wakeup - 12 - 1 - - - ERR - Error - 13 - 1 - - - PMAOVR - Packet memory area over / - underrun - 14 - 1 - - - CTR - Correct transfer - 15 - 1 - - - - - FNR - FNR - frame number register - 0x48 - 0x20 - read-only - 0x0000 - - - FN - Frame number - 0 - 11 - - - LSOF - Lost SOF - 11 - 2 - - - LCK - Locked - 13 - 1 - - - RXDM - Receive data - line status - 14 - 1 - - - RXDP - Receive data + line status - 15 - 1 - - - - - DADDR - DADDR - device address - 0x4C - 0x20 - read-write - 0x0000 - - - ADD - Device address - 0 - 7 - - - EF - Enable function - 7 - 1 - - - - - BTABLE - BTABLE - Buffer table address - 0x50 - 0x20 - read-write - 0x0000 - - - BTABLE - Buffer table - 3 - 13 - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/ide/olimexino.depend b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/ide/olimexino.depend deleted file mode 100644 index a04504f7..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/ide/olimexino.depend +++ /dev/null @@ -1,474 +0,0 @@ -# depslib dependency file v1.0 -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\led.c - "boot.h" - "led.h" - "stm32f10x.h" - -1499159026 c:\work\software\openblt\target\source\boot.h - "types.h" - "assert.h" - "blt_conf.h" - "plausibility.h" - "cpu.h" - "cop.h" - "nvm.h" - "timer.h" - "backdoor.h" - "file.h" - "com.h" - -1495810634 c:\work\software\openblt\target\source\armcm3_stm32f1\types.h - -1495810634 c:\work\software\openblt\target\source\assert.h - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\blt_conf.h - -1495810634 c:\work\software\openblt\target\source\plausibility.h - -1495810632 c:\work\software\openblt\target\source\cpu.h - -1495810633 c:\work\software\openblt\target\source\cop.h - -1495810632 c:\work\software\openblt\target\source\nvm.h - -1495810633 c:\work\software\openblt\target\source\timer.h - -1495810633 c:\work\software\openblt\target\source\backdoor.h - -1495810634 c:\work\software\openblt\target\source\file.h - "ff.h" - -1495810633 c:\work\software\openblt\target\source\com.h - "xcp.h" - -1495810633 c:\work\software\openblt\target\source\xcp.h - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\led.h - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\stm32f10x.h - "core_cm3.h" - "system_stm32f10x.h" - - "stm32f10x_conf.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\cmsis\core_cm3.h - - - - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\cmsis\core_cminstr.h - - - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\cmsis\core_cmfunc.h - - - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\system_stm32f10x.h - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\stm32f10x_conf.h - "stm32f10x_adc.h" - "stm32f10x_bkp.h" - "stm32f10x_can.h" - "stm32f10x_cec.h" - "stm32f10x_crc.h" - "stm32f10x_dac.h" - "stm32f10x_dbgmcu.h" - "stm32f10x_dma.h" - "stm32f10x_exti.h" - "stm32f10x_flash.h" - "stm32f10x_fsmc.h" - "stm32f10x_gpio.h" - "stm32f10x_i2c.h" - "stm32f10x_iwdg.h" - "stm32f10x_pwr.h" - "stm32f10x_rcc.h" - "stm32f10x_rtc.h" - "stm32f10x_sdio.h" - "stm32f10x_spi.h" - "stm32f10x_tim.h" - "stm32f10x_usart.h" - "stm32f10x_wwdg.h" - "misc.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_adc.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_bkp.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_can.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_cec.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_crc.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_dac.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_dbgmcu.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_dma.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_exti.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_flash.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_fsmc.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_gpio.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_i2c.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_iwdg.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_pwr.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_rcc.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_rtc.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_sdio.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_spi.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_tim.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_usart.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_wwdg.h - "stm32f10x.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\misc.h - "stm32f10x.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\misc.c - "misc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_adc.c - "stm32f10x_adc.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_bkp.c - "stm32f10x_bkp.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_can.c - "stm32f10x_can.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_cec.c - "stm32f10x_cec.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_crc.c - "stm32f10x_crc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_dac.c - "stm32f10x_dac.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_dbgmcu.c - "stm32f10x_dbgmcu.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_dma.c - "stm32f10x_dma.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_exti.c - "stm32f10x_exti.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_flash.c - "stm32f10x_flash.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_fsmc.c - "stm32f10x_fsmc.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_gpio.c - "stm32f10x_gpio.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\hooks.c - "boot.h" - "stm32f10x.h" - "led.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_i2c.c - "stm32f10x_i2c.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_iwdg.c - "stm32f10x_iwdg.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_pwr.c - "stm32f10x_pwr.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_rcc.c - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_rtc.c - "stm32f10x_rtc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_sdio.c - "stm32f10x_sdio.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_spi.c - "stm32f10x_spi.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_tim.c - "stm32f10x_tim.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_usart.c - "stm32f10x_usart.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\src\stm32f10x_wwdg.c - "stm32f10x_wwdg.h" - "stm32f10x_rcc.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\system_stm32f10x.c - "stm32f10x.h" - -1502957013 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\startup_stm32f10x_md.s - -1495810634 source:c:\work\software\openblt\target\source\armcm3_stm32f1\can.c - "boot.h" - -1495810634 source:c:\work\software\openblt\target\source\armcm3_stm32f1\cpu.c - "boot.h" - -1495810634 source:c:\work\software\openblt\target\source\armcm3_stm32f1\flash.c - "boot.h" - "flash_layout.c" - -1477586072 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\flash_layout.c - -1495810634 source:c:\work\software\openblt\target\source\armcm3_stm32f1\gcc\cpu_comp.c - "boot.h" - -1495810634 source:c:\work\software\openblt\target\source\armcm3_stm32f1\nvm.c - "boot.h" - "flash.h" - -1495810634 c:\work\software\openblt\target\source\armcm3_stm32f1\flash.h - -1495810634 source:c:\work\software\openblt\target\source\armcm3_stm32f1\timer.c - "boot.h" - -1495810634 source:c:\work\software\openblt\target\source\armcm3_stm32f1\uart.c - "boot.h" - -1495810634 source:c:\work\software\openblt\target\source\armcm3_stm32f1\usb.c - "boot.h" - "usb_lib.h" - "usb_desc.h" - "usb_pwr.h" - "usb_istr.h" - -1495810634 source:c:\work\software\openblt\target\source\assert.c - "boot.h" - -1495810633 source:c:\work\software\openblt\target\source\backdoor.c - "boot.h" - -1495810634 source:c:\work\software\openblt\target\source\boot.c - "boot.h" - -1495810633 source:c:\work\software\openblt\target\source\com.c - "boot.h" - "can.h" - "uart.h" - "usb.h" - "net.h" - -1495810632 c:\work\software\openblt\target\source\can.h - -1495810634 c:\work\software\openblt\target\source\uart.h - -1495810633 c:\work\software\openblt\target\source\usb.h - -1495810633 c:\work\software\openblt\target\source\net.h - -1495810633 source:c:\work\software\openblt\target\source\cop.c - "boot.h" - -1495810634 source:c:\work\software\openblt\target\source\file.c - "boot.h" - - - -1495810633 source:c:\work\software\openblt\target\source\net.c - "boot.h" - "netdev.h" - "uip.h" - "uip_arp.h" - -1495810633 source:c:\work\software\openblt\target\source\xcp.c - "boot.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\main.c - "boot.h" - "stm32f10x.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\src\usb_core.c - "usb_lib.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\inc\usb_lib.h - "stm32l1xx.h" - "stm32f10x.h" - "usb_type.h" - "usb_regs.h" - "usb_def.h" - "usb_core.h" - "usb_init.h" - "usb_mem.h" - "usb_int.h" - "usb_sil.h" - "otgd_fs_cal.h" - "otgd_fs_pcd.h" - "otgd_fs_dev.h" - "otgd_fs_int.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\inc\usb_type.h - "usb_conf.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\usb_conf.h - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\inc\usb_regs.h - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\inc\usb_def.h - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\inc\usb_core.h - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\inc\usb_init.h - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\inc\usb_mem.h - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\inc\usb_int.h - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\inc\usb_sil.h - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\src\usb_init.c - "usb_lib.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\src\usb_int.c - "usb_lib.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\src\usb_mem.c - "usb_lib.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\src\usb_regs.c - "usb_lib.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\usb_fs_device\src\usb_sil.c - "usb_lib.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\usb_desc.c - "usb_lib.h" - "usb_desc.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\usb_desc.h - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\usb_endp.c - "usb_lib.h" - "usb_desc.h" - "usb_mem.h" - "usb_istr.h" - "usb_pwr.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\usb_istr.h - "usb_conf.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\usb_pwr.h - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\usb_istr.c - "usb_lib.h" - "usb_prop.h" - "usb_pwr.h" - "usb_istr.h" - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\usb_prop.h - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\usb_prop.c - "usb_lib.h" - "usb_conf.h" - "usb_prop.h" - "usb_desc.h" - "usb_pwr.h" - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\usb_pwr.c - "stm32f10x.h" - "usb_lib.h" - "usb_conf.h" - "usb_pwr.h" - "types.h" - -1495810633 c:\work\software\openblt\target\source\third_party\fatfs\src\ff.h - "integer.h" - "ffconf.h" - -1495810633 c:\work\software\openblt\target\source\third_party\fatfs\src\integer.h - - - -1495810637 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\fatfs\ffconf.h - -1495810637 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\fatfs\mmc.c - "diskio.h" - "stm32f10x.h" - "boot.h" - -1495810633 c:\work\software\openblt\target\source\third_party\fatfs\src\diskio.h - "integer.h" - -1495810633 source:c:\work\software\openblt\target\source\third_party\fatfs\src\ff.c - "ff.h" - "diskio.h" - - -1495810633 source:c:\work\software\openblt\target\source\third_party\fatfs\src\option\unicode.c - "../ff.h" - "cc932.c" - "cc936.c" - "cc949.c" - "cc950.c" - "ccsbcs.c" - -1495810633 c:\work\software\openblt\target\source\third_party\fatfs\src\option\cc932.c - "../ff.h" - -1495810633 c:\work\software\openblt\target\source\third_party\fatfs\src\option\cc936.c - "../ff.h" - -1495810633 c:\work\software\openblt\target\source\third_party\fatfs\src\option\cc949.c - "../ff.h" - -1495810633 c:\work\software\openblt\target\source\third_party\fatfs\src\option\cc950.c - "../ff.h" - -1495810633 c:\work\software\openblt\target\source\third_party\fatfs\src\option\ccsbcs.c - "../ff.h" - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/ide/olimexino.ebp b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/ide/olimexino.ebp deleted file mode 100644 index 163f97ae..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/ide/olimexino.ebp +++ /dev/null @@ -1,515 +0,0 @@ - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/ide/olimexino.elay b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/ide/olimexino.elay deleted file mode 100644 index e216e53b..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/ide/olimexino.elay +++ /dev/null @@ -1,64 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/lib/newlib/_exit.c b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/lib/newlib/_exit.c new file mode 100644 index 00000000..4ae9532c --- /dev/null +++ b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/lib/newlib/_exit.c @@ -0,0 +1,38 @@ +// ---------------------------------------------------------------------------- + +#include + +// ---------------------------------------------------------------------------- + +// Forward declaration + +void +_exit(int code); + +// ---------------------------------------------------------------------------- + +// We just enter an infinite loop, to be used as landmark when halting +// the debugger. +// +// It can be redefined in the application, if more functionality +// is required. + +void +__attribute__((weak)) +_exit(int code __attribute__((unused))) +{ + // TODO: write on trace + while (1) + ; +} + +// ---------------------------------------------------------------------------- + +void +__attribute__((weak,noreturn)) +abort(void) +{ + _exit(1); +} + +// ---------------------------------------------------------------------------- diff --git a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/makefile b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/makefile new file mode 100644 index 00000000..41acd9fb --- /dev/null +++ b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/makefile @@ -0,0 +1,178 @@ +#**************************************************************************************** +#| Description: Makefile for GNU ARM Embedded toolchain. +#| File Name: makefile +#| +#|--------------------------------------------------------------------------------------- +#| C O P Y R I G H T +#|--------------------------------------------------------------------------------------- +#| Copyright (c) 2017 by Feaser http://www.feaser.com All rights reserved +#| +#|--------------------------------------------------------------------------------------- +#| L I C E N S E +#|--------------------------------------------------------------------------------------- +#| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +#| modify it under the terms of the GNU General Public License as published by the Free +#| Software Foundation, either version 3 of the License, or (at your option) any later +#| version. +#| +#| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +#| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +#| PURPOSE. See the GNU General Public License for more details. +#| +#| You have received a copy of the GNU General Public License along with OpenBLT. It +#| should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +#| +#**************************************************************************************** +SHELL = sh + +#|--------------------------------------------------------------------------------------| +#| Configure project name | +#|--------------------------------------------------------------------------------------| +PROJ_NAME=openblt_olimexino_stm32 + + +#|--------------------------------------------------------------------------------------| +#| Configure tool path | +#|--------------------------------------------------------------------------------------| +TOOL_PATH=/opt/gcc-arm-none-eabi-5_4-2016q3/bin/ + + +#|--------------------------------------------------------------------------------------| +#| Collect project files | +#|--------------------------------------------------------------------------------------| +# Recursive wildcard function implementation. Example usages: +# $(call rwildcard, , *.c *.h) +# --> Returns all *.c and *.h files in the current directory and below +# $(call rwildcard, /lib/, *.c) +# --> Returns all *.c files in the /lib directory and below +rwildcard = $(strip $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d))) + +# Collect all application files in the current directory and its subdirectories, but +# exclude flash-layout.c as this one is directly included in a source file, when used. +PROJ_FILES = $(filter-out flash_layout.c, $(call rwildcard, , *.c *.h *.S)) +# Collect bootloader core files +PROJ_FILES += $(wildcard ../../../Source/*.c) +PROJ_FILES += $(wildcard ../../../Source/*.h) +# Collect bootloader port files +PROJ_FILES += $(wildcard ../../../Source/ARMCM3_STM32F1/*.c) +PROJ_FILES += $(wildcard ../../../Source/ARMCM3_STM32F1/*.h) +# Collect bootloader port compiler specific files +PROJ_FILES += $(wildcard ../../../Source/ARMCM3_STM32F1/GCC/*.c) +PROJ_FILES += $(wildcard ../../../Source/ARMCM3_STM32F1/GCC/*.h) +# Collect FatFS third party library files +PROJ_FILES += $(wildcard ../../../Source/third_party/fatfs/src/*.c) +PROJ_FILES += $(wildcard ../../../Source/third_party/fatfs/src/*.h) +PROJ_FILES += ../../../Source/third_party/fatfs/src/option/unicode.c + + +#|--------------------------------------------------------------------------------------| +#| Toolchain binaries | +#|--------------------------------------------------------------------------------------| +RM = rm +CC = $(TOOL_PATH)arm-none-eabi-gcc +LN = $(TOOL_PATH)arm-none-eabi-gcc +OC = $(TOOL_PATH)arm-none-eabi-objcopy +OD = $(TOOL_PATH)arm-none-eabi-objdump +AS = $(TOOL_PATH)arm-none-eabi-gcc +SZ = $(TOOL_PATH)arm-none-eabi-size + + +#|--------------------------------------------------------------------------------------| +#| Filter project files +#|--------------------------------------------------------------------------------------| +PROJ_ASRCS = $(filter %.S,$(foreach file,$(PROJ_FILES),$(notdir $(file)))) +PROJ_CSRCS = $(filter %.c,$(foreach file,$(PROJ_FILES),$(notdir $(file)))) +PROJ_CHDRS = $(filter %.h,$(foreach file,$(PROJ_FILES),$(notdir $(file)))) + + +#|--------------------------------------------------------------------------------------| +#| Set important path variables | +#|--------------------------------------------------------------------------------------| +VPATH = $(foreach path,$(sort $(foreach file,$(PROJ_FILES),$(dir $(file)))) $(subst \,/,$(OBJ_PATH)),$(path) :) +OBJ_PATH = obj +BIN_PATH = bin +INC_PATH = $(patsubst %/,%,$(patsubst %,-I%,$(sort $(foreach file,$(filter %.h,$(PROJ_FILES)),$(dir $(file)))))) +LIB_PATH = + + +#|--------------------------------------------------------------------------------------| +#| Options for toolchain binaries | +#|--------------------------------------------------------------------------------------| +HEAP_SIZE = 0x0800 +STACK_SIZE = 0x0800 +STDFLAGS = -mcpu=cortex-m3 -mthumb -fno-strict-aliasing -Wno-maybe-uninitialized +STDFLAGS += -fdata-sections -ffunction-sections -Wall -g3 +OPTFLAGS = -O2 +CFLAGS = $(STDFLAGS) $(OPTFLAGS) +CFLAGS += -DSTM32F10X_MD -DUSE_STDPERIPH_DRIVER -DVECT_TAB_FLASH -DGCC_ARMCM3 +CFLAGS += -D__HEAP_SIZE=$(HEAP_SIZE) -D__STACK_SIZE=$(STACK_SIZE) +CFLAGS += $(INC_PATH) +AFLAGS = $(CFLAGS) +LFLAGS = $(STDFLAGS) $(OPTFLAGS) +LFLAGS += -Wl,--defsym=__HEAP_SIZE=$(HEAP_SIZE) -Wl,--defsym=__STACK_SIZE=$(STACK_SIZE) +LFLAGS += -Wl,-script="stm32f103rb_flash.ld" -Wl,-Map=$(BIN_PATH)/$(PROJ_NAME).map +LFLAGS += -specs=nano.specs -Wl,--gc-sections $(LIB_PATH) +OFLAGS = -O srec +ODFLAGS = -x +SZFLAGS = -B -d +RMFLAGS = -f + + +#|--------------------------------------------------------------------------------------| +#| Specify library files | +#|--------------------------------------------------------------------------------------| +LIBS = + + +#|--------------------------------------------------------------------------------------| +#| Define targets | +#|--------------------------------------------------------------------------------------| +AOBJS = $(patsubst %.S,%.o,$(PROJ_ASRCS)) +COBJS = $(patsubst %.c,%.o,$(PROJ_CSRCS)) + + +#|--------------------------------------------------------------------------------------| +#| Make ALL | +#|--------------------------------------------------------------------------------------| +.PHONY: all +all: $(BIN_PATH)/$(PROJ_NAME).srec + + +$(BIN_PATH)/$(PROJ_NAME).srec : $(BIN_PATH)/$(PROJ_NAME).elf + @$(OC) $< $(OFLAGS) $@ + @$(OD) $(ODFLAGS) $< > $(BIN_PATH)/$(PROJ_NAME).map + @echo +++ Summary of memory consumption: + @$(SZ) $(SZFLAGS) $< + @echo +++ Build complete [$(notdir $@)] + +$(BIN_PATH)/$(PROJ_NAME).elf : $(AOBJS) $(COBJS) + @echo +++ Linking [$(notdir $@)] + @$(LN) $(LFLAGS) -o $@ $(patsubst %.o,$(OBJ_PATH)/%.o,$(^F)) $(LIBS) + + +#|--------------------------------------------------------------------------------------| +#| Compile and assemble | +#|--------------------------------------------------------------------------------------| +$(AOBJS): %.o: %.S $(PROJ_CHDRS) + @echo +++ Assembling [$(notdir $<)] + @$(AS) $(AFLAGS) -c $< -o $(OBJ_PATH)/$(@F) + +$(COBJS): %.o: %.c $(PROJ_CHDRS) + @echo +++ Compiling [$(notdir $<)] + @$(CC) $(CFLAGS) -c $< -o $(OBJ_PATH)/$(@F) + + +#|--------------------------------------------------------------------------------------| +#| Make CLEAN | +#|--------------------------------------------------------------------------------------| +.PHONY: clean +clean: + @echo +++ Cleaning build environment + @$(RM) $(RMFLAGS) $(foreach file,$(AOBJS),$(OBJ_PATH)/$(file)) + @$(RM) $(RMFLAGS) $(foreach file,$(COBJS),$(OBJ_PATH)/$(file)) + @$(RM) $(RMFLAGS) $(patsubst %.o,%.lst,$(foreach file,$(COBJS),$(OBJ_PATH)/$(file))) + @$(RM) $(RMFLAGS) $(BIN_PATH)/$(PROJ_NAME).elf $(BIN_PATH)/$(PROJ_NAME).map + @$(RM) $(RMFLAGS) $(BIN_PATH)/$(PROJ_NAME).srec + @echo +++ Clean complete + + diff --git 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- .text 0x00000000 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o - .data 0x00000000 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o - .bss 0x00000000 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o - -Memory Configuration - -Name Origin Length Attributes -ROM 0x08006000 0x0001a000 xr -RAM 0x20000000 0x00005000 xrw -*default* 0x00000000 0xffffffff - -Linker script and memory map - -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crti.o -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtbegin.o -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m/crt0.o - 0x00000000 __HEAP_SIZE = 0x0 - 0x00000400 __STACK_SIZE = 0x400 - -.text 0x08006000 0x4f4 - *(.isr_vector) - .isr_vector 0x08006000 0xf0 ..\obj\startup_stm32f10x_md.o - 0x08006000 __isr_vector - *(.text*) - .text 0x080060f0 0x5c c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtbegin.o - .text 0x0800614c 0x74 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m/crt0.o - 0x0800614c _start - 0x0800614c _mainCRTStartup - .text.BootComInit - 0x080061c0 0x4 ..\obj\boot.o - 0x080061c0 BootComInit - .text.BootComCheckActivationRequest - 0x080061c4 0x4 ..\obj\boot.o - 0x080061c4 BootComCheckActivationRequest - .text.LedInit 0x080061c8 0x38 ..\obj\led.o - 0x080061c8 LedInit - .text.LedToggle - 0x08006200 0x4c ..\obj\led.o - 0x08006200 LedToggle - .text.GPIO_Init - 0x0800624c 0x9c ..\obj\lib\spl\src\stm32f10x_gpio.o - 0x0800624c GPIO_Init - .text.GPIO_SetBits - 0x080062e8 0x4 ..\obj\lib\spl\src\stm32f10x_gpio.o - 0x080062e8 GPIO_SetBits - .text.GPIO_ResetBits - 0x080062ec 0x4 ..\obj\lib\spl\src\stm32f10x_gpio.o - 0x080062ec GPIO_ResetBits - .text.RCC_APB2PeriphClockCmd - 0x080062f0 0x1c ..\obj\lib\spl\src\stm32f10x_rcc.o - 0x080062f0 RCC_APB2PeriphClockCmd - .text.Init 0x0800630c 0xc ..\obj\main.o - .text.main 0x08006318 0x14 ..\obj\main.o - 0x08006318 main - .text 0x0800632c 0xb8 ..\obj\startup_stm32f10x_md.o - 0x0800632c Reset_Handler - 0x08006372 NMI_Handler - 0x08006374 HardFault_Handler - 0x08006376 MemManage_Handler - 0x08006378 BusFault_Handler - 0x0800637a UsageFault_Handler - 0x0800637c SVC_Handler - 0x0800637e DebugMon_Handler - 0x08006380 PendSV_Handler - 0x08006384 Default_Handler - 0x08006386 WWDG_IRQHandler - 0x08006388 PVD_IRQHandler - 0x0800638a TAMPER_IRQHandler - 0x0800638c RTC_IRQHandler - 0x0800638e FLASH_IRQHandler - 0x08006390 RCC_IRQHandler - 0x08006392 EXTI0_IRQHandler - 0x08006394 EXTI1_IRQHandler - 0x08006396 EXTI2_IRQHandler - 0x08006398 EXTI3_IRQHandler - 0x0800639a EXTI4_IRQHandler - 0x0800639c DMA1_Channel1_IRQHandler - 0x0800639e DMA1_Channel2_IRQHandler - 0x080063a0 DMA1_Channel3_IRQHandler - 0x080063a2 DMA1_Channel4_IRQHandler - 0x080063a4 DMA1_Channel5_IRQHandler - 0x080063a6 DMA1_Channel6_IRQHandler - 0x080063a8 DMA1_Channel7_IRQHandler - 0x080063aa ADC1_2_IRQHandler - 0x080063ac USB_HP_CAN1_TX_IRQHandler - 0x080063ae USB_LP_CAN1_RX0_IRQHandler - 0x080063b0 CAN1_RX1_IRQHandler - 0x080063b2 CAN1_SCE_IRQHandler - 0x080063b4 EXTI9_5_IRQHandler - 0x080063b6 TIM1_BRK_IRQHandler - 0x080063b8 TIM1_UP_IRQHandler - 0x080063ba TIM1_TRG_COM_IRQHandler - 0x080063bc TIM1_CC_IRQHandler - 0x080063be TIM2_IRQHandler - 0x080063c0 TIM3_IRQHandler - 0x080063c2 TIM4_IRQHandler - 0x080063c4 I2C1_EV_IRQHandler - 0x080063c6 I2C1_ER_IRQHandler - 0x080063c8 I2C2_EV_IRQHandler - 0x080063ca I2C2_ER_IRQHandler - 0x080063cc SPI1_IRQHandler - 0x080063ce SPI2_IRQHandler - 0x080063d0 USART1_IRQHandler - 0x080063d2 USART2_IRQHandler - 0x080063d4 USART3_IRQHandler - 0x080063d6 EXTI15_10_IRQHandler - 0x080063d8 RTCAlarm_IRQHandler - 0x080063da USBWakeUp_IRQHandler - .text.TimerSet - 0x080063e4 0xc ..\obj\timer.o - 0x080063e4 TimerSet - .text.TimerInit - 0x080063f0 0x3c ..\obj\timer.o - 0x080063f0 TimerInit - .text.TimerGet - 0x0800642c 0xc ..\obj\timer.o - 0x0800642c TimerGet - .text.SysTick_Handler - 0x08006438 0x10 ..\obj\timer.o - 0x08006438 SysTick_Handler - .text.exit 0x08006448 0x28 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-exit.o) - 0x08006448 exit - .text.__libc_init_array - 0x08006470 0x4c c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-init.o) - 0x08006470 __libc_init_array - .text.memset 0x080064bc 0x10 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-memset.o) - 0x080064bc memset - .text._exit 0x080064cc 0x2 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libnosys_s.a(_exit.o) - 0x080064cc _exit - *(.init) - *fill* 0x080064ce 0x2 - .init 0x080064d0 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crti.o - 0x080064d0 _init - .init 0x080064d4 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o - *(.fini) - .fini 0x080064dc 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crti.o - 0x080064dc _fini - .fini 0x080064e0 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend.o *crtend?.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - *(.rodata*) - .rodata.str1.1 - 0x080064e8 0x2 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-impure.o) - *fill* 0x080064ea 0x2 - .rodata._global_impure_ptr - 0x080064ec 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-impure.o) - 0x080064ec _global_impure_ptr - *(.eh_frame*) - .eh_frame 0x080064f0 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtbegin.o - .eh_frame 0x080064f0 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtend.o - -.glue_7 0x080064f4 0x0 - .glue_7 0x080064f4 0x0 linker stubs - -.glue_7t 0x080064f4 0x0 - .glue_7t 0x080064f4 0x0 linker stubs - -.vfp11_veneer 0x080064f4 0x0 - .vfp11_veneer 0x080064f4 0x0 linker stubs - -.v4_bx 0x080064f4 0x0 - .v4_bx 0x080064f4 0x0 linker stubs - -.iplt 0x080064f4 0x0 - .iplt 0x080064f4 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtbegin.o - -.ARM.extab - *(.ARM.extab* .gnu.linkonce.armextab.*) - 0x080064f4 __exidx_start = . - -.ARM.exidx 0x080064f4 0x8 - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - .ARM.exidx 0x080064f4 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m/crt0.o - 0x080064fc __exidx_end = . - 0x080064fc __etext = . - -.rel.dyn 0x080064fc 0x0 - .rel.iplt 0x080064fc 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtbegin.o - -.data 0x20000000 0x6c load address 0x080064fc - 0x20000000 __data_start__ = . - *(vtable) - *(.data*) - .data.SystemCoreClock - 0x20000000 0x4 ..\obj\lib\system_stm32f10x.o - 0x20000000 SystemCoreClock - .data.impure_data - 0x20000004 0x60 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-impure.o) - 0x20000064 . = ALIGN (0x4) - 0x20000064 PROVIDE (__preinit_array_start, .) - *(.preinit_array) - 0x20000064 PROVIDE (__preinit_array_end, .) - 0x20000064 . = ALIGN (0x4) - 0x20000064 PROVIDE (__init_array_start, .) - *(SORT(.init_array.*)) - *(.init_array) - .init_array 0x20000064 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtbegin.o - 0x20000068 PROVIDE (__init_array_end, .) - 0x20000068 . = ALIGN (0x4) - [!provide] PROVIDE (__fini_array_start, .) - *(SORT(.fini_array.*)) - *(.fini_array) - .fini_array 0x20000068 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtbegin.o - [!provide] PROVIDE (__fini_array_end, .) - 0x2000006c . = ALIGN (0x4) - 0x2000006c __data_end__ = . - -.jcr 0x2000006c 0x0 load address 0x08006568 - .jcr 0x2000006c 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtbegin.o - -.igot.plt 0x2000006c 0x0 load address 0x08006568 - .igot.plt 0x2000006c 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtbegin.o - -.bss 0x2000006c 0x28 load address 0x08006568 - 0x2000006c __bss_start__ = . - *(.bss*) - .bss 0x2000006c 0x1c c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtbegin.o - .bss.timer_counter_last.6700 - 0x20000088 0x4 ..\obj\led.o - .bss.led_toggle_state.6699 - 0x2000008c 0x1 ..\obj\led.o - *fill* 0x2000008d 0x3 - .bss.millisecond_counter - 0x20000090 0x4 ..\obj\timer.o - *(COMMON) - 0x20000094 __bss_end__ = . - -.heap 0x20000098 0x0 - 0x20000098 __end__ = . - 0x20000098 end = __end__ - *(.heap*) - .heap 0x20000098 0x0 ..\obj\startup_stm32f10x_md.o - 0x20000098 __HeapLimit = . - -.stack_dummy 0x20000098 0x400 - *(.stack) - .stack 0x20000098 0x400 ..\obj\startup_stm32f10x_md.o - 0x20005000 __StackTop = (ORIGIN (RAM) + LENGTH (RAM)) - 0x20004c00 __StackLimit = (__StackTop - SIZEOF (.stack_dummy)) - 0x20005000 PROVIDE (__stack, __StackTop) - 0x00000001 ASSERT ((__StackLimit >= __HeapLimit), region RAM overflowed with stack) -LOAD ..\obj\boot.o -LOAD ..\obj\led.o -LOAD ..\obj\lib\spl\src\misc.o -LOAD ..\obj\lib\spl\src\stm32f10x_adc.o -LOAD ..\obj\lib\spl\src\stm32f10x_bkp.o -LOAD ..\obj\lib\spl\src\stm32f10x_can.o -LOAD ..\obj\lib\spl\src\stm32f10x_cec.o -LOAD ..\obj\lib\spl\src\stm32f10x_crc.o -LOAD ..\obj\lib\spl\src\stm32f10x_dac.o -LOAD ..\obj\lib\spl\src\stm32f10x_dbgmcu.o -LOAD ..\obj\lib\spl\src\stm32f10x_dma.o -LOAD ..\obj\lib\spl\src\stm32f10x_exti.o -LOAD ..\obj\lib\spl\src\stm32f10x_flash.o -LOAD ..\obj\lib\spl\src\stm32f10x_fsmc.o -LOAD ..\obj\lib\spl\src\stm32f10x_gpio.o -LOAD ..\obj\lib\spl\src\stm32f10x_i2c.o -LOAD ..\obj\lib\spl\src\stm32f10x_iwdg.o -LOAD ..\obj\lib\spl\src\stm32f10x_pwr.o -LOAD ..\obj\lib\spl\src\stm32f10x_rcc.o -LOAD ..\obj\lib\spl\src\stm32f10x_rtc.o -LOAD ..\obj\lib\spl\src\stm32f10x_sdio.o -LOAD ..\obj\lib\spl\src\stm32f10x_spi.o -LOAD ..\obj\lib\spl\src\stm32f10x_tim.o -LOAD ..\obj\lib\spl\src\stm32f10x_usart.o -LOAD ..\obj\lib\spl\src\stm32f10x_wwdg.o -LOAD ..\obj\lib\system_stm32f10x.o -LOAD ..\obj\main.o -LOAD ..\obj\startup_stm32f10x_md.o -LOAD ..\obj\timer.o -START GROUP -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m\libgcc.a -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libc_n.a -END GROUP -START GROUP -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m\libgcc.a -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libc_n.a -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libnosys_s.a -END GROUP -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtend.o -LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o -OUTPUT(..\bin\demoprog_olimexino_stm32.elf elf32-littlearm) - -.ARM.attributes - 0x00000000 0x29 - .ARM.attributes - 0x00000000 0x1d c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crti.o - .ARM.attributes - 0x0000001d 0x2d c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtbegin.o - .ARM.attributes - 0x0000004a 0x1b c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m/crt0.o - .ARM.attributes - 0x00000065 0x33 ..\obj\boot.o - .ARM.attributes - 0x00000098 0x33 ..\obj\led.o - .ARM.attributes - 0x000000cb 0x33 ..\obj\lib\spl\src\stm32f10x_gpio.o - .ARM.attributes - 0x000000fe 0x33 ..\obj\lib\spl\src\stm32f10x_rcc.o - .ARM.attributes - 0x00000131 0x33 ..\obj\lib\system_stm32f10x.o - .ARM.attributes - 0x00000164 0x33 ..\obj\main.o - .ARM.attributes - 0x00000197 0x1b ..\obj\startup_stm32f10x_md.o - .ARM.attributes - 0x000001b2 0x33 ..\obj\timer.o - .ARM.attributes - 0x000001e5 0x2d c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-exit.o) - .ARM.attributes - 0x00000212 0x2d c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-impure.o) - .ARM.attributes - 0x0000023f 0x2d c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-init.o) - .ARM.attributes - 0x0000026c 0x2d c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-memset.o) - .ARM.attributes - 0x00000299 0x2d c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libnosys_s.a(_exit.o) - .ARM.attributes - 0x000002c6 0x2d c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtend.o - .ARM.attributes - 0x000002f3 0x1d c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o - -.comment 0x00000000 0x6e - .comment 0x00000000 0x6e ..\obj\boot.o - 0x6f (size before relaxing) - .comment 0x0000006e 0x6f ..\obj\led.o - .comment 0x0000006e 0x6f ..\obj\lib\spl\src\stm32f10x_gpio.o - .comment 0x0000006e 0x6f ..\obj\lib\spl\src\stm32f10x_rcc.o - .comment 0x0000006e 0x6f ..\obj\lib\system_stm32f10x.o - .comment 0x0000006e 0x6f ..\obj\main.o - .comment 0x0000006e 0x6f ..\obj\timer.o - -.debug_info 0x00000000 0x22e1 - .debug_info 0x00000000 0x2ed ..\obj\boot.o - .debug_info 0x000002ed 0x331 ..\obj\led.o - .debug_info 0x0000061e 0x897 ..\obj\lib\spl\src\stm32f10x_gpio.o - .debug_info 0x00000eb5 0x8dd ..\obj\lib\spl\src\stm32f10x_rcc.o - .debug_info 0x00001792 0x31f ..\obj\lib\system_stm32f10x.o - .debug_info 0x00001ab1 0x13b ..\obj\main.o - .debug_info 0x00001bec 0x93 ..\obj\startup_stm32f10x_md.o - .debug_info 0x00001c7f 0x662 ..\obj\timer.o - -.debug_abbrev 0x00000000 0xa3e - .debug_abbrev 0x00000000 0x117 ..\obj\boot.o - .debug_abbrev 0x00000117 0x156 ..\obj\led.o - .debug_abbrev 0x0000026d 0x1f2 ..\obj\lib\spl\src\stm32f10x_gpio.o - .debug_abbrev 0x0000045f 0x1e7 ..\obj\lib\spl\src\stm32f10x_rcc.o - .debug_abbrev 0x00000646 0x159 ..\obj\lib\system_stm32f10x.o - .debug_abbrev 0x0000079f 0xa5 ..\obj\main.o - .debug_abbrev 0x00000844 0x14 ..\obj\startup_stm32f10x_md.o - .debug_abbrev 0x00000858 0x1e6 ..\obj\timer.o - -.debug_aranges 0x00000000 0x2d8 - .debug_aranges - 0x00000000 0x30 ..\obj\boot.o - .debug_aranges - 0x00000030 0x28 ..\obj\led.o - .debug_aranges - 0x00000058 0xa8 ..\obj\lib\spl\src\stm32f10x_gpio.o - .debug_aranges - 0x00000100 0x118 ..\obj\lib\spl\src\stm32f10x_rcc.o - .debug_aranges - 0x00000218 0x38 ..\obj\lib\system_stm32f10x.o - .debug_aranges - 0x00000250 0x28 ..\obj\main.o - .debug_aranges - 0x00000278 0x20 ..\obj\startup_stm32f10x_md.o - .debug_aranges - 0x00000298 0x40 ..\obj\timer.o - -.debug_ranges 0x00000000 0x248 - .debug_ranges 0x00000000 0x20 ..\obj\boot.o - .debug_ranges 0x00000020 0x18 ..\obj\led.o - .debug_ranges 0x00000038 0x98 ..\obj\lib\spl\src\stm32f10x_gpio.o - .debug_ranges 0x000000d0 0x108 ..\obj\lib\spl\src\stm32f10x_rcc.o - .debug_ranges 0x000001d8 0x28 ..\obj\lib\system_stm32f10x.o - .debug_ranges 0x00000200 0x18 ..\obj\main.o - .debug_ranges 0x00000218 0x30 ..\obj\timer.o - -.debug_macro 0x00000000 0xd9cc - .debug_macro 0x00000000 0x1bf ..\obj\boot.o - .debug_macro 0x000001bf 0x886 ..\obj\boot.o - .debug_macro 0x00000a45 0xb8 ..\obj\boot.o - .debug_macro 0x00000afd 0x5d ..\obj\boot.o - .debug_macro 0x00000b5a 0x3a ..\obj\boot.o - .debug_macro 0x00000b94 0x22 ..\obj\boot.o - .debug_macro 0x00000bb6 0x87 ..\obj\boot.o - .debug_macro 0x00000c3d 0x44 ..\obj\boot.o - .debug_macro 0x00000c81 0xfd ..\obj\boot.o - .debug_macro 0x00000d7e 0x5e ..\obj\boot.o - .debug_macro 0x00000ddc 0x1df ..\obj\boot.o - .debug_macro 0x00000fbb 0x18 ..\obj\boot.o - .debug_macro 0x00000fd3 0xa36 ..\obj\boot.o - .debug_macro 0x00001a09 0x7eb3 ..\obj\boot.o - .debug_macro 0x000098bc 0x2df ..\obj\boot.o - .debug_macro 0x00009b9b 0x144 ..\obj\boot.o - .debug_macro 0x00009cdf 0x3cf ..\obj\boot.o - .debug_macro 0x0000a0ae 0xc8 ..\obj\boot.o - .debug_macro 0x0000a176 0x17a ..\obj\boot.o - .debug_macro 0x0000a2f0 0xac ..\obj\boot.o - .debug_macro 0x0000a39c 0x3ad ..\obj\boot.o - .debug_macro 0x0000a749 0x9a ..\obj\boot.o - .debug_macro 0x0000a7e3 0x2cf ..\obj\boot.o - .debug_macro 0x0000aab2 0x279 ..\obj\boot.o - .debug_macro 0x0000ad2b 0x2ac ..\obj\boot.o - .debug_macro 0x0000afd7 0x2b1 ..\obj\boot.o - .debug_macro 0x0000b288 0x64 ..\obj\boot.o - .debug_macro 0x0000b2ec 0x82 ..\obj\boot.o - .debug_macro 0x0000b36e 0x3e2 ..\obj\boot.o - .debug_macro 0x0000b750 0x58 ..\obj\boot.o - .debug_macro 0x0000b7a8 0x341 ..\obj\boot.o - .debug_macro 0x0000bae9 0x2c4 ..\obj\boot.o - .debug_macro 0x0000bdad 0x711 ..\obj\boot.o - .debug_macro 0x0000c4be 0x220 ..\obj\boot.o - .debug_macro 0x0000c6de 0x34 ..\obj\boot.o - .debug_macro 0x0000c712 0x8b ..\obj\boot.o - .debug_macro 0x0000c79d 0x35 ..\obj\boot.o - .debug_macro 0x0000c7d2 0x1c5 ..\obj\led.o - .debug_macro 0x0000c997 0x1e6 ..\obj\lib\spl\src\stm32f10x_gpio.o - .debug_macro 0x0000cb7d 0x2a6 ..\obj\lib\spl\src\stm32f10x_gpio.o - .debug_macro 0x0000ce23 0x2b4 ..\obj\lib\spl\src\stm32f10x_rcc.o - .debug_macro 0x0000d0d7 0x3dc ..\obj\lib\spl\src\stm32f10x_rcc.o - .debug_macro 0x0000d4b3 0x19b ..\obj\lib\system_stm32f10x.o - .debug_macro 0x0000d64e 0x1bf ..\obj\main.o - .debug_macro 0x0000d80d 0x1bf ..\obj\timer.o - -.debug_line 0x00000000 0x24bc - .debug_line 0x00000000 0x4a7 ..\obj\boot.o - .debug_line 0x000004a7 0x493 ..\obj\led.o - .debug_line 0x0000093a 0x5e2 ..\obj\lib\spl\src\stm32f10x_gpio.o - .debug_line 0x00000f1c 0x6cb ..\obj\lib\spl\src\stm32f10x_rcc.o - .debug_line 0x000015e7 0x4c8 ..\obj\lib\system_stm32f10x.o - .debug_line 0x00001aaf 0x493 ..\obj\main.o - .debug_line 0x00001f42 0xab ..\obj\startup_stm32f10x_md.o - .debug_line 0x00001fed 0x4cf ..\obj\timer.o - -.debug_str 0x00000000 0x4ff2e - .debug_str 0x00000000 0x4e8f0 ..\obj\boot.o - 0x4ea64 (size before relaxing) - .debug_str 0x0004e8f0 0x1ec ..\obj\led.o - 0x4eb91 (size before relaxing) - .debug_str 0x0004eadc 0x499 ..\obj\lib\spl\src\stm32f10x_gpio.o - 0x4ec50 (size before relaxing) - .debug_str 0x0004ef75 0xb22 ..\obj\lib\spl\src\stm32f10x_rcc.o - 0x4f21f (size before relaxing) - .debug_str 0x0004fa97 0xba ..\obj\lib\system_stm32f10x.o - 0x4e798 (size before relaxing) - .debug_str 0x0004fb51 0x19 ..\obj\main.o - 0x4e9e2 (size before relaxing) - .debug_str 0x0004fb6a 0x3c4 ..\obj\timer.o - 0x4edf8 (size before relaxing) - -.debug_frame 0x00000000 0x5c0 - .debug_frame 0x00000000 0x40 ..\obj\boot.o - .debug_frame 0x00000040 0x48 ..\obj\led.o - .debug_frame 0x00000088 0x16c ..\obj\lib\spl\src\stm32f10x_gpio.o - .debug_frame 0x000001f4 0x228 ..\obj\lib\spl\src\stm32f10x_rcc.o - .debug_frame 0x0000041c 0x68 ..\obj\lib\system_stm32f10x.o - .debug_frame 0x00000484 0x40 ..\obj\main.o - .debug_frame 0x000004c4 0x68 ..\obj\timer.o - .debug_frame 0x0000052c 0x28 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-exit.o) - .debug_frame 0x00000554 0x2c c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-init.o) - .debug_frame 0x00000580 0x20 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-memset.o) - .debug_frame 0x000005a0 0x20 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m\libnosys_s.a(_exit.o) - -.debug_loc 0x00000000 0xd4f - .debug_loc 0x00000000 0x34 ..\obj\led.o - .debug_loc 0x00000034 0x542 ..\obj\lib\spl\src\stm32f10x_gpio.o - .debug_loc 0x00000576 0x692 ..\obj\lib\spl\src\stm32f10x_rcc.o - .debug_loc 0x00000c08 0xdf ..\obj\lib\system_stm32f10x.o - .debug_loc 0x00000ce7 0x68 ..\obj\timer.o + +bin/demoprog_olimexino_stm32.elf: file format elf32-littlearm +bin/demoprog_olimexino_stm32.elf +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x08006000 + +Program Header: +0x70000001 off 0x000064f0 vaddr 0x080064f0 paddr 0x080064f0 align 2**2 + filesz 0x00000008 memsz 0x00000008 flags r-- + LOAD off 0x00000000 vaddr 0x08000000 paddr 0x08000000 align 2**16 + filesz 0x000064f8 memsz 0x000064f8 flags r-x + LOAD off 0x00010000 vaddr 0x20000000 paddr 0x080064f8 align 2**16 + filesz 0x0000006c memsz 0x00000094 flags rw- +private flags = 5000200: [Version5 EABI] [soft-float ABI] + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000004f0 08006000 08006000 00006000 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .ARM.exidx 00000008 080064f0 080064f0 000064f0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .data 0000006c 20000000 080064f8 00010000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 3 .bss 00000028 2000006c 08006564 0001006c 2**2 + ALLOC + 4 .heap 00000800 20000098 20000098 00010070 2**3 + CONTENTS, READONLY + 5 .stack_dummy 00000800 20000098 20000098 00010870 2**3 + CONTENTS, READONLY + 6 .ARM.attributes 00000029 00000000 00000000 00011070 2**0 + CONTENTS, READONLY + 7 .comment 0000006e 00000000 00000000 00011099 2**0 + CONTENTS, READONLY + 8 .debug_line 0000245c 00000000 00000000 00011107 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_info 000023ad 00000000 00000000 00013563 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 00000ac9 00000000 00000000 00015910 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_aranges 00000300 00000000 00000000 000163e0 2**3 + CONTENTS, READONLY, DEBUGGING + 12 .debug_ranges 00000260 00000000 00000000 000166e0 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_macro 0000e415 00000000 00000000 00016940 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_str 00052945 00000000 00000000 00024d55 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_frame 000005d8 00000000 00000000 0007769c 2**2 + CONTENTS, READONLY, DEBUGGING + 16 .debug_loc 00000d4f 00000000 00000000 00077c74 2**0 + CONTENTS, READONLY, DEBUGGING +SYMBOL TABLE: +08006000 l d .text 00000000 .text +080064f0 l d .ARM.exidx 00000000 .ARM.exidx +20000000 l d .data 00000000 .data +2000006c l d .bss 00000000 .bss +20000098 l d .heap 00000000 .heap +20000098 l d .stack_dummy 00000000 .stack_dummy +00000000 l d .ARM.attributes 00000000 .ARM.attributes +00000000 l d .comment 00000000 .comment +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_ranges 00000000 .debug_ranges +00000000 l d .debug_macro 00000000 .debug_macro +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l df *ABS* 00000000 obj/startup_stm32f10x_md.o +00000800 l *ABS* 00000000 Stack_Size +00000800 l *ABS* 00000000 Heap_Size +080061ca l .text 00000000 .flash_to_ram_loop +080061fc l .text 00000000 .fill_zero_bss +080061f8 l .text 00000000 .loop_zero_bss +00000000 l df *ABS* 00000000 crtstuff.c +080064ec l O .text 00000000 __EH_FRAME_BEGIN__ +080060f0 l F .text 00000000 __do_global_dtors_aux +2000006c l .bss 00000000 completed.8603 +20000068 l O .data 00000000 __do_global_dtors_aux_fini_array_entry +08006114 l F .text 00000000 frame_dummy +20000070 l .bss 00000000 object.8608 +20000064 l O .data 00000000 __frame_dummy_init_array_entry +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m/crt0.o +00000000 l df *ABS* 00000000 boot.c +00000000 l df *ABS* 00000000 main.c +08006280 l F .text 0000000c Init +00000000 l df *ABS* 00000000 led.c +20000088 l O .bss 00000004 timer_counter_last.6700 +2000008c l O .bss 00000001 led_toggle_state.6699 +00000000 l df *ABS* 00000000 timer.c +20000090 l O .bss 00000004 millisecond_counter +00000000 l df *ABS* 00000000 _exit.c +00000000 l df *ABS* 00000000 stm32f10x_rcc.c +00000000 l df *ABS* 00000000 stm32f10x_gpio.c +00000000 l df *ABS* 00000000 exit.c +00000000 l df *ABS* 00000000 init.c +00000000 l df *ABS* 00000000 memset.c +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crti.o +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o +00000000 l df *ABS* 00000000 impure.c +20000004 l O .data 00000060 impure_data +00000000 l df *ABS* 00000000 crtstuff.c +080064ec l O .text 00000000 __FRAME_END__ +00000000 l df *ABS* 00000000 system_stm32f10x.c +00000000 l df *ABS* 00000000 +20000068 l .data 00000000 __init_array_end +20000064 l .data 00000000 __preinit_array_end +20000064 l .data 00000000 __init_array_start +20000064 l .data 00000000 __preinit_array_start +0800622a w F .text 00000002 EXTI2_IRQHandler +20000098 g .heap 00000800 __HeapBase +08006212 w F .text 00000002 DebugMon_Handler +00000800 g *ABS* 00000000 __HEAP_SIZE +20000000 g .data 00000000 __data_start__ +08006250 w F .text 00000002 TIM1_CC_IRQHandler +08006208 w F .text 00000002 HardFault_Handler +08006378 g F .text 00000010 SysTick_Handler +0800621c w F .text 00000002 PVD_IRQHandler +08006214 w F .text 00000002 PendSV_Handler +08006206 w F .text 00000002 NMI_Handler +080064f8 g .ARM.exidx 00000000 __exidx_end +0800622c w F .text 00000002 EXTI3_IRQHandler +080064f8 g .ARM.exidx 00000000 __etext +08006226 w F .text 00000002 EXTI0_IRQHandler +0800625c w F .text 00000002 I2C2_EV_IRQHandler +20000000 g O .data 00000004 SystemCoreClock +0800620e w F .text 00000002 UsageFault_Handler +0800638c g F .text 0000001c RCC_APB2PeriphClockCmd +0800623e w F .text 00000002 ADC1_2_IRQHandler +080063a8 g F .text 0000009a GPIO_Init +20000898 g .heap 00000000 __HeapLimit +2000006c g .bss 00000000 __bss_start__ +08006260 w F .text 00000002 SPI1_IRQHandler +0800621e w F .text 00000002 TAMPER_IRQHandler +080064f0 g .text 00000000 __exidx_start +080064e8 g O .text 00000004 _global_impure_ptr +08006474 g F .text 0000004c __libc_init_array +08006236 w F .text 00000002 DMA1_Channel4_IRQHandler +0800614c g F .text 00000000 _mainCRTStartup +080064d0 g F .text 00000000 _init +08006268 w F .text 00000002 USART3_IRQHandler +00000000 w *UND* 00000000 __libc_fini_array +08006220 w F .text 00000002 RTC_IRQHandler +0800623c w F .text 00000002 DMA1_Channel7_IRQHandler +080061c0 g F .text 00000030 Reset_Handler +08006244 w F .text 00000002 CAN1_RX1_IRQHandler +080062a0 g F .text 00000038 LedInit +08006444 g F .text 00000004 GPIO_SetBits +08006256 w F .text 00000002 TIM4_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stderr +00000000 w *UND* 00000000 __deregister_frame_info +20000098 g .heap 00000000 end +08006258 w F .text 00000002 I2C1_EV_IRQHandler +2000006c g .data 00000000 __data_end__ +0800623a w F .text 00000002 DMA1_Channel6_IRQHandler +20000094 g .bss 00000000 __bss_end__ +00000800 g *ABS* 00000000 __STACK_SIZE +08006254 w F .text 00000002 TIM3_IRQHandler +08006224 w F .text 00000002 RCC_IRQHandler +0800624e w F .text 00000002 TIM1_TRG_COM_IRQHandler +00000000 w *UND* 00000000 __call_exitprocs +08006230 w F .text 00000002 DMA1_Channel1_IRQHandler +08006218 w F .text 00000002 Default_Handler +0800614c g F .text 00000000 _start +0800626a w F .text 00000002 EXTI15_10_IRQHandler +00000000 w *UND* 00000000 software_init_hook +08006448 g F .text 00000004 GPIO_ResetBits +08006248 w F .text 00000002 EXTI9_5_IRQHandler +08006262 w F .text 00000002 SPI2_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stdin +080064c0 g F .text 00000010 memset +0800620a w F .text 00000002 MemManage_Handler +08006000 g .text 000000f0 __isr_vector +0800628c g F .text 00000014 main +08006210 w F .text 00000002 SVC_Handler +00000000 w *UND* 00000000 hardware_init_hook +20000098 g .heap 00000000 __end__ +08006238 w F .text 00000002 DMA1_Channel5_IRQHandler +0800622e w F .text 00000002 EXTI4_IRQHandler +08006324 g F .text 0000000c TimerSet +08006242 w F .text 00000002 USB_LP_CAN1_RX0_IRQHandler +08006278 g F .text 00000002 BootComInit +080064dc g F .text 00000000 _fini +08006240 w F .text 00000002 USB_HP_CAN1_TX_IRQHandler +00000000 w *UND* 00000000 atexit +08006234 w F .text 00000002 DMA1_Channel3_IRQHandler +20005000 g .bss 00000000 __StackTop +0800624c w F .text 00000002 TIM1_UP_IRQHandler +0800621a w F .text 00000002 WWDG_IRQHandler +080062d8 g F .text 0000004c LedToggle +08006252 w F .text 00000002 TIM2_IRQHandler +0800624a w F .text 00000002 TIM1_BRK_IRQHandler +20005000 g *ABS* 00000000 __stack +08006228 w F .text 00000002 EXTI1_IRQHandler +0800626c w F .text 00000002 RTCAlarm_IRQHandler +20004800 g *ABS* 00000800 __StackLimit +08006266 w F .text 00000002 USART2_IRQHandler +0800644c g F .text 00000028 exit +0800625e w F .text 00000002 I2C2_ER_IRQHandler +08006232 w F .text 00000002 DMA1_Channel2_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stdout +0800627c g F .text 00000002 BootComCheckActivationRequest +08006246 w F .text 00000002 CAN1_SCE_IRQHandler +08006222 w F .text 00000002 FLASH_IRQHandler +08006388 w F .text 00000002 _exit +0800620c w F .text 00000002 BusFault_Handler +08006264 w F .text 00000002 USART1_IRQHandler +0800625a w F .text 00000002 I2C1_ER_IRQHandler +0800636c g F .text 0000000c TimerGet +00000000 w *UND* 00000000 _Jv_RegisterClasses +08006330 g F .text 0000003c TimerInit +00000000 w *UND* 00000000 __register_frame_info +0800626e w F .text 00000002 USBWakeUp_IRQHandler + + diff --git a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/bin/demoprog_olimexino_stm32.srec b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/bin/demoprog_olimexino_stm32.srec index 6d584569..8f8ec3d4 100644 --- a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/bin/demoprog_olimexino_stm32.srec +++ b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/bin/demoprog_olimexino_stm32.srec @@ -1,90 +1,89 @@ -S02700002E2E5C62696E5C64656D6F70726F675F6F6C696D6578696E6F5F73746D33322E7372656308 -S31508006000005000202D6300087363000875630008BC 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+S315080065380000000000000000000000000000000045 +S315080065480000000000000000000000000000000035 +S311080065580000000015610008F160000852 S7050800600092 diff --git a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/cfg/STM32F103xx.svd b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/cfg/STM32F103xx.svd deleted file mode 100644 index 1348869b..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/cfg/STM32F103xx.svd +++ /dev/null @@ -1,24923 +0,0 @@ - - - STM32F103xx - 1.3 - STM32F103xx - - - 8 - - 32 - - 0x20 - 0x0 - 0xFFFFFFFF - - - FSMC - Flexible static memory controller - FSMC - 0xA0000000 - - 0x0 - 0x1000 - registers - - - FSMC - FSMC global interrupt - 48 - - - - BCR1 - BCR1 - SRAM/NOR-Flash chip-select control register - 1 - 0x0 - 0x20 - read-write - 0x000030D0 - - - CBURSTRW - CBURSTRW - 19 - 1 - - - ASYNCWAIT - ASYNCWAIT - 15 - 1 - - - EXTMOD - EXTMOD - 14 - 1 - - - WAITEN - WAITEN - 13 - 1 - - - WREN - WREN - 12 - 1 - - - WAITCFG - WAITCFG - 11 - 1 - - - WAITPOL - WAITPOL - 9 - 1 - - - BURSTEN - BURSTEN - 8 - 1 - - - FACCEN - FACCEN - 6 - 1 - - - MWID - MWID - 4 - 2 - - - MTYP - MTYP - 2 - 2 - - - MUXEN - MUXEN - 1 - 1 - - - MBKEN - MBKEN - 0 - 1 - - - - - BTR1 - BTR1 - SRAM/NOR-Flash chip-select timing register - 1 - 0x4 - 0x20 - read-write - 0xFFFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - BUSTURN - BUSTURN - 16 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - BCR2 - BCR2 - SRAM/NOR-Flash chip-select control register - 2 - 0x8 - 0x20 - read-write - 0x000030D0 - - - CBURSTRW - CBURSTRW - 19 - 1 - - - ASYNCWAIT - ASYNCWAIT - 15 - 1 - - - EXTMOD - EXTMOD - 14 - 1 - - - WAITEN - WAITEN - 13 - 1 - - - WREN - WREN - 12 - 1 - - - WAITCFG - WAITCFG - 11 - 1 - - - WRAPMOD - WRAPMOD - 10 - 1 - - - WAITPOL - WAITPOL - 9 - 1 - - - BURSTEN - BURSTEN - 8 - 1 - - - FACCEN - FACCEN - 6 - 1 - - - MWID - MWID - 4 - 2 - - - MTYP - MTYP - 2 - 2 - - - MUXEN - MUXEN - 1 - 1 - - - MBKEN - MBKEN - 0 - 1 - - - - - BTR2 - BTR2 - SRAM/NOR-Flash chip-select timing register - 2 - 0xC - 0x20 - read-write - 0xFFFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - BUSTURN - BUSTURN - 16 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - BCR3 - BCR3 - SRAM/NOR-Flash chip-select control register - 3 - 0x10 - 0x20 - read-write - 0x000030D0 - - - CBURSTRW - CBURSTRW - 19 - 1 - - - ASYNCWAIT - ASYNCWAIT - 15 - 1 - - - EXTMOD - EXTMOD - 14 - 1 - - - WAITEN - WAITEN - 13 - 1 - - - WREN - WREN - 12 - 1 - - - WAITCFG - WAITCFG - 11 - 1 - - - WRAPMOD - WRAPMOD - 10 - 1 - - - WAITPOL - WAITPOL - 9 - 1 - - - BURSTEN - BURSTEN - 8 - 1 - - - FACCEN - FACCEN - 6 - 1 - - - MWID - MWID - 4 - 2 - - - MTYP - MTYP - 2 - 2 - - - MUXEN - MUXEN - 1 - 1 - - - MBKEN - MBKEN - 0 - 1 - - - - - BTR3 - BTR3 - SRAM/NOR-Flash chip-select timing register - 3 - 0x14 - 0x20 - read-write - 0xFFFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - BUSTURN - BUSTURN - 16 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - BCR4 - BCR4 - SRAM/NOR-Flash chip-select control register - 4 - 0x18 - 0x20 - read-write - 0x000030D0 - - - CBURSTRW - CBURSTRW - 19 - 1 - - - ASYNCWAIT - ASYNCWAIT - 15 - 1 - - - EXTMOD - EXTMOD - 14 - 1 - - - WAITEN - WAITEN - 13 - 1 - - - WREN - WREN - 12 - 1 - - - WAITCFG - WAITCFG - 11 - 1 - - - WRAPMOD - WRAPMOD - 10 - 1 - - - WAITPOL - WAITPOL - 9 - 1 - - - BURSTEN - BURSTEN - 8 - 1 - - - FACCEN - FACCEN - 6 - 1 - - - MWID - MWID - 4 - 2 - - - MTYP - MTYP - 2 - 2 - - - MUXEN - MUXEN - 1 - 1 - - - MBKEN - MBKEN - 0 - 1 - - - - - BTR4 - BTR4 - SRAM/NOR-Flash chip-select timing register - 4 - 0x1C - 0x20 - read-write - 0xFFFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - BUSTURN - BUSTURN - 16 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - PCR2 - PCR2 - PC Card/NAND Flash control register - 2 - 0x60 - 0x20 - read-write - 0x00000018 - - - ECCPS - ECCPS - 17 - 3 - - - TAR - TAR - 13 - 4 - - - TCLR - TCLR - 9 - 4 - - - ECCEN - ECCEN - 6 - 1 - - - PWID - PWID - 4 - 2 - - - PTYP - PTYP - 3 - 1 - - - PBKEN - PBKEN - 2 - 1 - - - PWAITEN - PWAITEN - 1 - 1 - - - - - SR2 - SR2 - FIFO status and interrupt register - 2 - 0x64 - 0x20 - 0x00000040 - - - FEMPT - FEMPT - 6 - 1 - read-only - - - IFEN - IFEN - 5 - 1 - read-write - - - ILEN - ILEN - 4 - 1 - read-write - - - IREN - IREN - 3 - 1 - read-write - - - IFS - IFS - 2 - 1 - read-write - - - ILS - ILS - 1 - 1 - read-write - - - IRS - IRS - 0 - 1 - read-write - - - - - PMEM2 - PMEM2 - Common memory space timing register - 2 - 0x68 - 0x20 - read-write - 0xFCFCFCFC - - - MEMHIZx - MEMHIZx - 24 - 8 - - - MEMHOLDx - MEMHOLDx - 16 - 8 - - - MEMWAITx - MEMWAITx - 8 - 8 - - - MEMSETx - MEMSETx - 0 - 8 - - - - - PATT2 - PATT2 - Attribute memory space timing register - 2 - 0x6C - 0x20 - read-write - 0xFCFCFCFC - - - ATTHIZx - Attribute memory x databus HiZ - time - 24 - 8 - - - ATTHOLDx - Attribute memory x hold - time - 16 - 8 - - - ATTWAITx - Attribute memory x wait - time - 8 - 8 - - - ATTSETx - Attribute memory x setup - time - 0 - 8 - - - - - ECCR2 - ECCR2 - ECC result register 2 - 0x74 - 0x20 - read-only - 0x00000000 - - - ECCx - ECC result - 0 - 32 - - - - - PCR3 - PCR3 - PC Card/NAND Flash control register - 3 - 0x80 - 0x20 - read-write - 0x00000018 - - - ECCPS - ECCPS - 17 - 3 - - - TAR - TAR - 13 - 4 - - - TCLR - TCLR - 9 - 4 - - - ECCEN - ECCEN - 6 - 1 - - - PWID - PWID - 4 - 2 - - - PTYP - PTYP - 3 - 1 - - - PBKEN - PBKEN - 2 - 1 - - - PWAITEN - PWAITEN - 1 - 1 - - - - - SR3 - SR3 - FIFO status and interrupt register - 3 - 0x84 - 0x20 - 0x00000040 - - - FEMPT - FEMPT - 6 - 1 - read-only - - - IFEN - IFEN - 5 - 1 - read-write - - - ILEN - ILEN - 4 - 1 - read-write - - - IREN - IREN - 3 - 1 - read-write - - - IFS - IFS - 2 - 1 - read-write - - - ILS - ILS - 1 - 1 - read-write - - - IRS - IRS - 0 - 1 - read-write - - - - - PMEM3 - PMEM3 - Common memory space timing register - 3 - 0x88 - 0x20 - read-write - 0xFCFCFCFC - - - MEMHIZx - MEMHIZx - 24 - 8 - - - MEMHOLDx - MEMHOLDx - 16 - 8 - - - MEMWAITx - MEMWAITx - 8 - 8 - - - MEMSETx - MEMSETx - 0 - 8 - - - - - PATT3 - PATT3 - Attribute memory space timing register - 3 - 0x8C - 0x20 - read-write - 0xFCFCFCFC - - - ATTHIZx - ATTHIZx - 24 - 8 - - - ATTHOLDx - ATTHOLDx - 16 - 8 - - - ATTWAITx - ATTWAITx - 8 - 8 - - - ATTSETx - ATTSETx - 0 - 8 - - - - - ECCR3 - ECCR3 - ECC result register 3 - 0x94 - 0x20 - read-only - 0x00000000 - - - ECCx - ECCx - 0 - 32 - - - - - PCR4 - PCR4 - PC Card/NAND Flash control register - 4 - 0xA0 - 0x20 - read-write - 0x00000018 - - - ECCPS - ECCPS - 17 - 3 - - - TAR - TAR - 13 - 4 - - - TCLR - TCLR - 9 - 4 - - - ECCEN - ECCEN - 6 - 1 - - - PWID - PWID - 4 - 2 - - - PTYP - PTYP - 3 - 1 - - - PBKEN - PBKEN - 2 - 1 - - - PWAITEN - PWAITEN - 1 - 1 - - - - - SR4 - SR4 - FIFO status and interrupt register - 4 - 0xA4 - 0x20 - 0x00000040 - - - FEMPT - FEMPT - 6 - 1 - read-only - - - IFEN - IFEN - 5 - 1 - read-write - - - ILEN - ILEN - 4 - 1 - read-write - - - IREN - IREN - 3 - 1 - read-write - - - IFS - IFS - 2 - 1 - read-write - - - ILS - ILS - 1 - 1 - read-write - - - IRS - IRS - 0 - 1 - read-write - - - - - PMEM4 - PMEM4 - Common memory space timing register - 4 - 0xA8 - 0x20 - read-write - 0xFCFCFCFC - - - MEMHIZx - MEMHIZx - 24 - 8 - - - MEMHOLDx - MEMHOLDx - 16 - 8 - - - MEMWAITx - MEMWAITx - 8 - 8 - - - MEMSETx - MEMSETx - 0 - 8 - - - - - PATT4 - PATT4 - Attribute memory space timing register - 4 - 0xAC - 0x20 - read-write - 0xFCFCFCFC - - - ATTHIZx - ATTHIZx - 24 - 8 - - - ATTHOLDx - ATTHOLDx - 16 - 8 - - - ATTWAITx - ATTWAITx - 8 - 8 - - - ATTSETx - ATTSETx - 0 - 8 - - - - - PIO4 - PIO4 - I/O space timing register 4 - 0xB0 - 0x20 - read-write - 0xFCFCFCFC - - - IOHIZx - IOHIZx - 24 - 8 - - - IOHOLDx - IOHOLDx - 16 - 8 - - - IOWAITx - IOWAITx - 8 - 8 - - - IOSETx - IOSETx - 0 - 8 - - - - - BWTR1 - BWTR1 - SRAM/NOR-Flash write timing registers - 1 - 0x104 - 0x20 - read-write - 0x0FFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - BWTR2 - BWTR2 - SRAM/NOR-Flash write timing registers - 2 - 0x10C - 0x20 - read-write - 0x0FFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - BWTR3 - BWTR3 - SRAM/NOR-Flash write timing registers - 3 - 0x114 - 0x20 - read-write - 0x0FFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - BWTR4 - BWTR4 - SRAM/NOR-Flash write timing registers - 4 - 0x11C - 0x20 - read-write - 0x0FFFFFFF - - - ACCMOD - ACCMOD - 28 - 2 - - - DATLAT - DATLAT - 24 - 4 - - - CLKDIV - CLKDIV - 20 - 4 - - - DATAST - DATAST - 8 - 8 - - - ADDHLD - ADDHLD - 4 - 4 - - - ADDSET - ADDSET - 0 - 4 - - - - - - - PWR - Power control - PWR - 0x40007000 - - 0x0 - 0x400 - registers - - - PVD - PVD through EXTI line detection - interrupt - 1 - - - - CR - CR - Power control register - (PWR_CR) - 0x0 - 0x20 - read-write - 0x00000000 - - - LPDS - Low Power Deep Sleep - 0 - 1 - - - PDDS - Power Down Deep Sleep - 1 - 1 - - - CWUF - Clear Wake-up Flag - 2 - 1 - - - CSBF - Clear STANDBY Flag - 3 - 1 - - - PVDE - Power Voltage Detector - Enable - 4 - 1 - - - PLS - PVD Level Selection - 5 - 3 - - - DBP - Disable Backup Domain write - protection - 8 - 1 - - - - - CSR - CSR - Power control register - (PWR_CR) - 0x4 - 0x20 - 0x00000000 - - - WUF - Wake-Up Flag - 0 - 1 - read-only - - - SBF - STANDBY Flag - 1 - 1 - read-only - - - PVDO - PVD Output - 2 - 1 - read-only - - - EWUP - Enable WKUP pin - 8 - 1 - read-write - - - - - - - RCC - Reset and clock control - RCC - 0x40021000 - - 0x0 - 0x400 - registers - - - RCC - RCC global interrupt - 5 - - - - CR - CR - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HSION - Internal High Speed clock - enable - 0 - 1 - read-write - - - HSIRDY - Internal High Speed clock ready - flag - 1 - 1 - read-only - - - HSITRIM - Internal High Speed clock - trimming - 3 - 5 - read-write - - - HSICAL - Internal High Speed clock - Calibration - 8 - 8 - read-only - - - HSEON - External High Speed clock - enable - 16 - 1 - read-write - - - HSERDY - External High Speed clock ready - flag - 17 - 1 - read-only - - - HSEBYP - External High Speed clock - Bypass - 18 - 1 - read-write - - - CSSON - Clock Security System - enable - 19 - 1 - read-write - - - PLLON - PLL enable - 24 - 1 - read-write - - - PLLRDY - PLL clock ready flag - 25 - 1 - read-only - - - - - CFGR - CFGR - Clock configuration register - (RCC_CFGR) - 0x4 - 0x20 - 0x00000000 - - - SW - System clock Switch - 0 - 2 - read-write - - - SWS - System Clock Switch Status - 2 - 2 - read-only - - - HPRE - AHB prescaler - 4 - 4 - read-write - - - PPRE1 - APB Low speed prescaler - (APB1) - 8 - 3 - read-write - - - PPRE2 - APB High speed prescaler - (APB2) - 11 - 3 - read-write - - - ADCPRE - ADC prescaler - 14 - 2 - read-write - - - PLLSRC - PLL entry clock source - 16 - 1 - read-write - - - PLLXTPRE - HSE divider for PLL entry - 17 - 1 - read-write - - - PLLMUL - PLL Multiplication Factor - 18 - 4 - read-write - - - OTGFSPRE - USB OTG FS prescaler - 22 - 1 - read-write - - - MCO - Microcontroller clock - output - 24 - 3 - read-write - - - - - CIR - CIR - Clock interrupt register - (RCC_CIR) - 0x8 - 0x20 - 0x00000000 - - - LSIRDYF - LSI Ready Interrupt flag - 0 - 1 - read-only - - - LSERDYF - LSE Ready Interrupt flag - 1 - 1 - read-only - - - HSIRDYF - HSI Ready Interrupt flag - 2 - 1 - read-only - - - HSERDYF - HSE Ready Interrupt flag - 3 - 1 - read-only - - - PLLRDYF - PLL Ready Interrupt flag - 4 - 1 - read-only - - - CSSF - Clock Security System Interrupt - flag - 7 - 1 - read-only - - - LSIRDYIE - LSI Ready Interrupt Enable - 8 - 1 - read-write - - - LSERDYIE - LSE Ready Interrupt Enable - 9 - 1 - read-write - - - HSIRDYIE - HSI Ready Interrupt Enable - 10 - 1 - read-write - - - HSERDYIE - HSE Ready Interrupt Enable - 11 - 1 - read-write - - - PLLRDYIE - PLL Ready Interrupt Enable - 12 - 1 - read-write - - - LSIRDYC - LSI Ready Interrupt Clear - 16 - 1 - write-only - - - LSERDYC - LSE Ready Interrupt Clear - 17 - 1 - write-only - - - HSIRDYC - HSI Ready Interrupt Clear - 18 - 1 - write-only - - - HSERDYC - HSE Ready Interrupt Clear - 19 - 1 - write-only - - - PLLRDYC - PLL Ready Interrupt Clear - 20 - 1 - write-only - - - CSSC - Clock security system interrupt - clear - 23 - 1 - write-only - - - - - APB2RSTR - APB2RSTR - APB2 peripheral reset register - (RCC_APB2RSTR) - 0xC - 0x20 - read-write - 0x000000000 - - - AFIORST - Alternate function I/O - reset - 0 - 1 - - - IOPARST - IO port A reset - 2 - 1 - - - IOPBRST - IO port B reset - 3 - 1 - - - IOPCRST - IO port C reset - 4 - 1 - - - IOPDRST - IO port D reset - 5 - 1 - - - IOPERST - IO port E reset - 6 - 1 - - - IOPFRST - IO port F reset - 7 - 1 - - - IOPGRST - IO port G reset - 8 - 1 - - - ADC1RST - ADC 1 interface reset - 9 - 1 - - - ADC2RST - ADC 2 interface reset - 10 - 1 - - - TIM1RST - TIM1 timer reset - 11 - 1 - - - SPI1RST - SPI 1 reset - 12 - 1 - - - TIM8RST - TIM8 timer reset - 13 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - ADC3RST - ADC 3 interface reset - 15 - 1 - - - TIM9RST - TIM9 timer reset - 19 - 1 - - - TIM10RST - TIM10 timer reset - 20 - 1 - - - TIM11RST - TIM11 timer reset - 21 - 1 - - - - - APB1RSTR - APB1RSTR - APB1 peripheral reset register - (RCC_APB1RSTR) - 0x10 - 0x20 - read-write - 0x00000000 - - - TIM2RST - Timer 2 reset - 0 - 1 - - - TIM3RST - Timer 3 reset - 1 - 1 - - - TIM4RST - Timer 4 reset - 2 - 1 - - - TIM5RST - Timer 5 reset - 3 - 1 - - - TIM6RST - Timer 6 reset - 4 - 1 - - - TIM7RST - Timer 7 reset - 5 - 1 - - - TIM12RST - Timer 12 reset - 6 - 1 - - - TIM13RST - Timer 13 reset - 7 - 1 - - - TIM14RST - Timer 14 reset - 8 - 1 - - - WWDGRST - Window watchdog reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - SPI3RST - SPI3 reset - 15 - 1 - - - USART2RST - USART 2 reset - 17 - 1 - - - USART3RST - USART 3 reset - 18 - 1 - - - UART4RST - UART 4 reset - 19 - 1 - - - UART5RST - UART 5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - USBRST - USB reset - 23 - 1 - - - CANRST - CAN reset - 25 - 1 - - - BKPRST - Backup interface reset - 27 - 1 - - - PWRRST - Power interface reset - 28 - 1 - - - DACRST - DAC interface reset - 29 - 1 - - - - - AHBENR - AHBENR - AHB Peripheral Clock enable register - (RCC_AHBENR) - 0x14 - 0x20 - read-write - 0x00000014 - - - DMA1EN - DMA1 clock enable - 0 - 1 - - - DMA2EN - DMA2 clock enable - 1 - 1 - - - SRAMEN - SRAM interface clock - enable - 2 - 1 - - - FLITFEN - FLITF clock enable - 4 - 1 - - - CRCEN - CRC clock enable - 6 - 1 - - - FSMCEN - FSMC clock enable - 8 - 1 - - - SDIOEN - SDIO clock enable - 10 - 1 - - - - - APB2ENR - APB2ENR - APB2 peripheral clock enable register - (RCC_APB2ENR) - 0x18 - 0x20 - read-write - 0x00000000 - - - AFIOEN - Alternate function I/O clock - enable - 0 - 1 - - - IOPAEN - I/O port A clock enable - 2 - 1 - - - IOPBEN - I/O port B clock enable - 3 - 1 - - - IOPCEN - I/O port C clock enable - 4 - 1 - - - IOPDEN - I/O port D clock enable - 5 - 1 - - - IOPEEN - I/O port E clock enable - 6 - 1 - - - IOPFEN - I/O port F clock enable - 7 - 1 - - - IOPGEN - I/O port G clock enable - 8 - 1 - - - ADC1EN - ADC 1 interface clock - enable - 9 - 1 - - - ADC2EN - ADC 2 interface clock - enable - 10 - 1 - - - TIM1EN - TIM1 Timer clock enable - 11 - 1 - - - SPI1EN - SPI 1 clock enable - 12 - 1 - - - TIM8EN - TIM8 Timer clock enable - 13 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - ADC3EN - ADC3 interface clock - enable - 15 - 1 - - - TIM9EN - TIM9 Timer clock enable - 19 - 1 - - - TIM10EN - TIM10 Timer clock enable - 20 - 1 - - - TIM11EN - TIM11 Timer clock enable - 21 - 1 - - - - - APB1ENR - APB1ENR - APB1 peripheral clock enable register - (RCC_APB1ENR) - 0x1C - 0x20 - read-write - 0x00000000 - - - TIM2EN - Timer 2 clock enable - 0 - 1 - - - TIM3EN - Timer 3 clock enable - 1 - 1 - - - TIM4EN - Timer 4 clock enable - 2 - 1 - - - TIM5EN - Timer 5 clock enable - 3 - 1 - - - TIM6EN - Timer 6 clock enable - 4 - 1 - - - TIM7EN - Timer 7 clock enable - 5 - 1 - - - TIM12EN - Timer 12 clock enable - 6 - 1 - - - TIM13EN - Timer 13 clock enable - 7 - 1 - - - TIM14EN - Timer 14 clock enable - 8 - 1 - - - WWDGEN - Window watchdog clock - enable - 11 - 1 - - - SPI2EN - SPI 2 clock enable - 14 - 1 - - - SPI3EN - SPI 3 clock enable - 15 - 1 - - - USART2EN - USART 2 clock enable - 17 - 1 - - - USART3EN - USART 3 clock enable - 18 - 1 - - - UART4EN - UART 4 clock enable - 19 - 1 - - - UART5EN - UART 5 clock enable - 20 - 1 - - - I2C1EN - I2C 1 clock enable - 21 - 1 - - - I2C2EN - I2C 2 clock enable - 22 - 1 - - - USBEN - USB clock enable - 23 - 1 - - - CANEN - CAN clock enable - 25 - 1 - - - BKPEN - Backup interface clock - enable - 27 - 1 - - - PWREN - Power interface clock - enable - 28 - 1 - - - DACEN - DAC interface clock enable - 29 - 1 - - - - - BDCR - BDCR - Backup domain control register - (RCC_BDCR) - 0x20 - 0x20 - 0x00000000 - - - LSEON - External Low Speed oscillator - enable - 0 - 1 - read-write - - - LSERDY - External Low Speed oscillator - ready - 1 - 1 - read-only - - - LSEBYP - External Low Speed oscillator - bypass - 2 - 1 - read-write - - - RTCSEL - RTC clock source selection - 8 - 2 - read-write - - - RTCEN - RTC clock enable - 15 - 1 - read-write - - - BDRST - Backup domain software - reset - 16 - 1 - read-write - - - - - CSR - CSR - Control/status register - (RCC_CSR) - 0x24 - 0x20 - 0x0C000000 - - - LSION - Internal low speed oscillator - enable - 0 - 1 - read-write - - - LSIRDY - Internal low speed oscillator - ready - 1 - 1 - read-only - - - RMVF - Remove reset flag - 24 - 1 - read-write - - - PINRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/PDR reset flag - 27 - 1 - read-write - - - SFTRSTF - Software reset flag - 28 - 1 - read-write - - - IWDGRSTF - Independent watchdog reset - flag - 29 - 1 - read-write - - - WWDGRSTF - Window watchdog reset flag - 30 - 1 - read-write - - - LPWRRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - - - GPIOA - General purpose I/O - GPIO - 0x40010800 - - 0x0 - 0x400 - registers - - - - CRL - CRL - Port configuration register low - (GPIOn_CRL) - 0x0 - 0x20 - read-write - 0x44444444 - - - MODE0 - Port n.0 mode bits - 0 - 2 - - - CNF0 - Port n.0 configuration - bits - 2 - 2 - - - MODE1 - Port n.1 mode bits - 4 - 2 - - - CNF1 - Port n.1 configuration - bits - 6 - 2 - - - MODE2 - Port n.2 mode bits - 8 - 2 - - - CNF2 - Port n.2 configuration - bits - 10 - 2 - - - MODE3 - Port n.3 mode bits - 12 - 2 - - - CNF3 - Port n.3 configuration - bits - 14 - 2 - - - MODE4 - Port n.4 mode bits - 16 - 2 - - - CNF4 - Port n.4 configuration - bits - 18 - 2 - - - MODE5 - Port n.5 mode bits - 20 - 2 - - - CNF5 - Port n.5 configuration - bits - 22 - 2 - - - MODE6 - Port n.6 mode bits - 24 - 2 - - - CNF6 - Port n.6 configuration - bits - 26 - 2 - - - MODE7 - Port n.7 mode bits - 28 - 2 - - - CNF7 - Port n.7 configuration - bits - 30 - 2 - - - - - CRH - CRH - Port configuration register high - (GPIOn_CRL) - 0x4 - 0x20 - read-write - 0x44444444 - - - MODE8 - Port n.8 mode bits - 0 - 2 - - - CNF8 - Port n.8 configuration - bits - 2 - 2 - - - MODE9 - Port n.9 mode bits - 4 - 2 - - - CNF9 - Port n.9 configuration - bits - 6 - 2 - - - MODE10 - Port n.10 mode bits - 8 - 2 - - - CNF10 - Port n.10 configuration - bits - 10 - 2 - - - MODE11 - Port n.11 mode bits - 12 - 2 - - - CNF11 - Port n.11 configuration - bits - 14 - 2 - - - MODE12 - Port n.12 mode bits - 16 - 2 - - - CNF12 - Port n.12 configuration - bits - 18 - 2 - - - MODE13 - Port n.13 mode bits - 20 - 2 - - - CNF13 - Port n.13 configuration - bits - 22 - 2 - - - MODE14 - Port n.14 mode bits - 24 - 2 - - - CNF14 - Port n.14 configuration - bits - 26 - 2 - - - MODE15 - Port n.15 mode bits - 28 - 2 - - - CNF15 - Port n.15 configuration - bits - 30 - 2 - - - - - IDR - IDR - Port input data register - (GPIOn_IDR) - 0x8 - 0x20 - read-only - 0x00000000 - - - IDR0 - Port input data - 0 - 1 - - - IDR1 - Port input data - 1 - 1 - - - IDR2 - Port input data - 2 - 1 - - - IDR3 - Port input data - 3 - 1 - - - IDR4 - Port input data - 4 - 1 - - - IDR5 - Port input data - 5 - 1 - - - IDR6 - Port input data - 6 - 1 - - - IDR7 - Port input data - 7 - 1 - - - IDR8 - Port input data - 8 - 1 - - - IDR9 - Port input data - 9 - 1 - - - IDR10 - Port input data - 10 - 1 - - - IDR11 - Port input data - 11 - 1 - - - IDR12 - Port input data - 12 - 1 - - - IDR13 - Port input data - 13 - 1 - - - IDR14 - Port input data - 14 - 1 - - - IDR15 - Port input data - 15 - 1 - - - - - ODR - ODR - Port output data register - (GPIOn_ODR) - 0xC - 0x20 - read-write - 0x00000000 - - - ODR0 - Port output data - 0 - 1 - - - ODR1 - Port output data - 1 - 1 - - - ODR2 - Port output data - 2 - 1 - - - ODR3 - Port output data - 3 - 1 - - - ODR4 - Port output data - 4 - 1 - - - ODR5 - Port output data - 5 - 1 - - - ODR6 - Port output data - 6 - 1 - - - ODR7 - Port output data - 7 - 1 - - - ODR8 - Port output data - 8 - 1 - - - ODR9 - Port output data - 9 - 1 - - - ODR10 - Port output data - 10 - 1 - - - ODR11 - Port output data - 11 - 1 - - - ODR12 - Port output data - 12 - 1 - - - ODR13 - Port output data - 13 - 1 - - - ODR14 - Port output data - 14 - 1 - - - ODR15 - Port output data - 15 - 1 - - - - - BSRR - BSRR - Port bit set/reset register - (GPIOn_BSRR) - 0x10 - 0x20 - write-only - 0x00000000 - - - BS0 - Set bit 0 - 0 - 1 - - - BS1 - Set bit 1 - 1 - 1 - - - BS2 - Set bit 1 - 2 - 1 - - - BS3 - Set bit 3 - 3 - 1 - - - BS4 - Set bit 4 - 4 - 1 - - - BS5 - Set bit 5 - 5 - 1 - - - BS6 - Set bit 6 - 6 - 1 - - - BS7 - Set bit 7 - 7 - 1 - - - BS8 - Set bit 8 - 8 - 1 - - - BS9 - Set bit 9 - 9 - 1 - - - BS10 - Set bit 10 - 10 - 1 - - - BS11 - Set bit 11 - 11 - 1 - - - BS12 - Set bit 12 - 12 - 1 - - - BS13 - Set bit 13 - 13 - 1 - - - BS14 - Set bit 14 - 14 - 1 - - - BS15 - Set bit 15 - 15 - 1 - - - BR0 - Reset bit 0 - 16 - 1 - - - BR1 - Reset bit 1 - 17 - 1 - - - BR2 - Reset bit 2 - 18 - 1 - - - BR3 - Reset bit 3 - 19 - 1 - - - BR4 - Reset bit 4 - 20 - 1 - - - BR5 - Reset bit 5 - 21 - 1 - - - BR6 - Reset bit 6 - 22 - 1 - - - BR7 - Reset bit 7 - 23 - 1 - - - BR8 - Reset bit 8 - 24 - 1 - - - BR9 - Reset bit 9 - 25 - 1 - - - BR10 - Reset bit 10 - 26 - 1 - - - BR11 - Reset bit 11 - 27 - 1 - - - BR12 - Reset bit 12 - 28 - 1 - - - BR13 - Reset bit 13 - 29 - 1 - - - BR14 - Reset bit 14 - 30 - 1 - - - BR15 - Reset bit 15 - 31 - 1 - - - - - BRR - BRR - Port bit reset register - (GPIOn_BRR) - 0x14 - 0x20 - write-only - 0x00000000 - - - BR0 - Reset bit 0 - 0 - 1 - - - BR1 - Reset bit 1 - 1 - 1 - - - BR2 - Reset bit 1 - 2 - 1 - - - BR3 - Reset bit 3 - 3 - 1 - - - BR4 - Reset bit 4 - 4 - 1 - - - BR5 - Reset bit 5 - 5 - 1 - - - BR6 - Reset bit 6 - 6 - 1 - - - BR7 - Reset bit 7 - 7 - 1 - - - BR8 - Reset bit 8 - 8 - 1 - - - BR9 - Reset bit 9 - 9 - 1 - - - BR10 - Reset bit 10 - 10 - 1 - - - BR11 - Reset bit 11 - 11 - 1 - - - BR12 - Reset bit 12 - 12 - 1 - - - BR13 - Reset bit 13 - 13 - 1 - - - BR14 - Reset bit 14 - 14 - 1 - - - BR15 - Reset bit 15 - 15 - 1 - - - - - LCKR - LCKR - Port configuration lock - register - 0x18 - 0x20 - read-write - 0x00000000 - - - LCK0 - Port A Lock bit 0 - 0 - 1 - - - LCK1 - Port A Lock bit 1 - 1 - 1 - - - LCK2 - Port A Lock bit 2 - 2 - 1 - - - LCK3 - Port A Lock bit 3 - 3 - 1 - - - LCK4 - Port A Lock bit 4 - 4 - 1 - - - LCK5 - Port A Lock bit 5 - 5 - 1 - - - LCK6 - Port A Lock bit 6 - 6 - 1 - - - LCK7 - Port A Lock bit 7 - 7 - 1 - - - LCK8 - Port A Lock bit 8 - 8 - 1 - - - LCK9 - Port A Lock bit 9 - 9 - 1 - - - LCK10 - Port A Lock bit 10 - 10 - 1 - - - LCK11 - Port A Lock bit 11 - 11 - 1 - - - LCK12 - Port A Lock bit 12 - 12 - 1 - - - LCK13 - Port A Lock bit 13 - 13 - 1 - - - LCK14 - Port A Lock bit 14 - 14 - 1 - - - LCK15 - Port A Lock bit 15 - 15 - 1 - - - LCKK - Lock key - 16 - 1 - - - - - - - GPIOB - 0x40010C00 - - - GPIOC - 0x40011000 - - - GPIOD - 0x40011400 - - - GPIOE - 0x40011800 - - - GPIOF - 0x40011C00 - - - GPIOG - 0x40012000 - - - AFIO - Alternate function I/O - AFIO - 0x40010000 - - 0x0 - 0x400 - registers - - - - EVCR - EVCR - Event Control Register - (AFIO_EVCR) - 0x0 - 0x20 - read-write - 0x00000000 - - - PIN - Pin selection - 0 - 4 - - - PORT - Port selection - 4 - 3 - - - EVOE - Event Output Enable - 7 - 1 - - - - - MAPR - MAPR - AF remap and debug I/O configuration - register (AFIO_MAPR) - 0x4 - 0x20 - 0x00000000 - - - SPI1_REMAP - SPI1 remapping - 0 - 1 - read-write - - - I2C1_REMAP - I2C1 remapping - 1 - 1 - read-write - - - USART1_REMAP - USART1 remapping - 2 - 1 - read-write - - - USART2_REMAP - USART2 remapping - 3 - 1 - read-write - - - USART3_REMAP - USART3 remapping - 4 - 2 - read-write - - - TIM1_REMAP - TIM1 remapping - 6 - 2 - read-write - - - TIM2_REMAP - TIM2 remapping - 8 - 2 - read-write - - - TIM3_REMAP - TIM3 remapping - 10 - 2 - read-write - - - TIM4_REMAP - TIM4 remapping - 12 - 1 - read-write - - - CAN_REMAP - CAN1 remapping - 13 - 2 - read-write - - - PD01_REMAP - Port D0/Port D1 mapping on - OSCIN/OSCOUT - 15 - 1 - read-write - - - TIM5CH4_IREMAP - Set and cleared by - software - 16 - 1 - read-write - - - ADC1_ETRGINJ_REMAP - ADC 1 External trigger injected - conversion remapping - 17 - 1 - read-write - - - ADC1_ETRGREG_REMAP - ADC 1 external trigger regular - conversion remapping - 18 - 1 - read-write - - - ADC2_ETRGINJ_REMAP - ADC 2 external trigger injected - conversion remapping - 19 - 1 - read-write - - - ADC2_ETRGREG_REMAP - ADC 2 external trigger regular - conversion remapping - 20 - 1 - read-write - - - SWJ_CFG - Serial wire JTAG - configuration - 24 - 3 - write-only - - - - - EXTICR1 - EXTICR1 - External interrupt configuration register 1 - (AFIO_EXTICR1) - 0x8 - 0x20 - read-write - 0x00000000 - - - EXTI0 - EXTI0 configuration - 0 - 4 - - - EXTI1 - EXTI1 configuration - 4 - 4 - - - EXTI2 - EXTI2 configuration - 8 - 4 - - - EXTI3 - EXTI3 configuration - 12 - 4 - - - - - EXTICR2 - EXTICR2 - External interrupt configuration register 2 - (AFIO_EXTICR2) - 0xC - 0x20 - read-write - 0x00000000 - - - EXTI4 - EXTI4 configuration - 0 - 4 - - - EXTI5 - EXTI5 configuration - 4 - 4 - - - EXTI6 - EXTI6 configuration - 8 - 4 - - - EXTI7 - EXTI7 configuration - 12 - 4 - - - - - EXTICR3 - EXTICR3 - External interrupt configuration register 3 - (AFIO_EXTICR3) - 0x10 - 0x20 - read-write - 0x00000000 - - - EXTI8 - EXTI8 configuration - 0 - 4 - - - EXTI9 - EXTI9 configuration - 4 - 4 - - - EXTI10 - EXTI10 configuration - 8 - 4 - - - EXTI11 - EXTI11 configuration - 12 - 4 - - - - - EXTICR4 - EXTICR4 - External interrupt configuration register 4 - (AFIO_EXTICR4) - 0x14 - 0x20 - read-write - 0x00000000 - - - EXTI12 - EXTI12 configuration - 0 - 4 - - - EXTI13 - EXTI13 configuration - 4 - 4 - - - EXTI14 - EXTI14 configuration - 8 - 4 - - - EXTI15 - EXTI15 configuration - 12 - 4 - - - - - MAPR2 - MAPR2 - AF remap and debug I/O configuration - register - 0x1C - 0x20 - read-write - 0x00000000 - - - TIM9_REMAP - TIM9 remapping - 5 - 1 - - - TIM10_REMAP - TIM10 remapping - 6 - 1 - - - TIM11_REMAP - TIM11 remapping - 7 - 1 - - - TIM13_REMAP - TIM13 remapping - 8 - 1 - - - TIM14_REMAP - TIM14 remapping - 9 - 1 - - - FSMC_NADV - NADV connect/disconnect - 10 - 1 - - - - - - - EXTI - EXTI - EXTI - 0x40010400 - - 0x0 - 0x400 - registers - - - TAMPER - Tamper interrupt - 2 - - - EXTI0 - EXTI Line0 interrupt - 6 - - - EXTI1 - EXTI Line1 interrupt - 7 - - - EXTI2 - EXTI Line2 interrupt - 8 - - - EXTI3 - EXTI Line3 interrupt - 9 - - - EXTI4 - EXTI Line4 interrupt - 10 - - - EXTI9_5 - EXTI Line[9:5] interrupts - 23 - - - EXTI15_10 - EXTI Line[15:10] interrupts - 40 - - - - IMR - IMR - Interrupt mask register - (EXTI_IMR) - 0x0 - 0x20 - read-write - 0x00000000 - - - MR0 - Interrupt Mask on line 0 - 0 - 1 - - - MR1 - Interrupt Mask on line 1 - 1 - 1 - - - MR2 - Interrupt Mask on line 2 - 2 - 1 - - - MR3 - Interrupt Mask on line 3 - 3 - 1 - - - MR4 - Interrupt Mask on line 4 - 4 - 1 - - - MR5 - Interrupt Mask on line 5 - 5 - 1 - - - MR6 - Interrupt Mask on line 6 - 6 - 1 - - - MR7 - Interrupt Mask on line 7 - 7 - 1 - - - MR8 - Interrupt Mask on line 8 - 8 - 1 - - - MR9 - Interrupt Mask on line 9 - 9 - 1 - - - MR10 - Interrupt Mask on line 10 - 10 - 1 - - - MR11 - Interrupt Mask on line 11 - 11 - 1 - - - MR12 - Interrupt Mask on line 12 - 12 - 1 - - - MR13 - Interrupt Mask on line 13 - 13 - 1 - - - MR14 - Interrupt Mask on line 14 - 14 - 1 - - - MR15 - Interrupt Mask on line 15 - 15 - 1 - - - MR16 - Interrupt Mask on line 16 - 16 - 1 - - - MR17 - Interrupt Mask on line 17 - 17 - 1 - - - MR18 - Interrupt Mask on line 18 - 18 - 1 - - - - - EMR - EMR - Event mask register (EXTI_EMR) - 0x4 - 0x20 - read-write - 0x00000000 - - - MR0 - Event Mask on line 0 - 0 - 1 - - - MR1 - Event Mask on line 1 - 1 - 1 - - - MR2 - Event Mask on line 2 - 2 - 1 - - - MR3 - Event Mask on line 3 - 3 - 1 - - - MR4 - Event Mask on line 4 - 4 - 1 - - - MR5 - Event Mask on line 5 - 5 - 1 - - - MR6 - Event Mask on line 6 - 6 - 1 - - - MR7 - Event Mask on line 7 - 7 - 1 - - - MR8 - Event Mask on line 8 - 8 - 1 - - - MR9 - Event Mask on line 9 - 9 - 1 - - - MR10 - Event Mask on line 10 - 10 - 1 - - - MR11 - Event Mask on line 11 - 11 - 1 - - - MR12 - Event Mask on line 12 - 12 - 1 - - - MR13 - Event Mask on line 13 - 13 - 1 - - - MR14 - Event Mask on line 14 - 14 - 1 - - - MR15 - Event Mask on line 15 - 15 - 1 - - - MR16 - Event Mask on line 16 - 16 - 1 - - - MR17 - Event Mask on line 17 - 17 - 1 - - - MR18 - Event Mask on line 18 - 18 - 1 - - - - - RTSR - RTSR - Rising Trigger selection register - (EXTI_RTSR) - 0x8 - 0x20 - read-write - 0x00000000 - - - TR0 - Rising trigger event configuration of - line 0 - 0 - 1 - - - TR1 - Rising trigger event configuration of - line 1 - 1 - 1 - - - TR2 - Rising trigger event configuration of - line 2 - 2 - 1 - - - TR3 - Rising trigger event configuration of - line 3 - 3 - 1 - - - TR4 - Rising trigger event configuration of - line 4 - 4 - 1 - - - TR5 - Rising trigger event configuration of - line 5 - 5 - 1 - - - TR6 - Rising trigger event configuration of - line 6 - 6 - 1 - - - TR7 - Rising trigger event configuration of - line 7 - 7 - 1 - - - TR8 - Rising trigger event configuration of - line 8 - 8 - 1 - - - TR9 - Rising trigger event configuration of - line 9 - 9 - 1 - - - TR10 - Rising trigger event configuration of - line 10 - 10 - 1 - - - TR11 - Rising trigger event configuration of - line 11 - 11 - 1 - - - TR12 - Rising trigger event configuration of - line 12 - 12 - 1 - - - TR13 - Rising trigger event configuration of - line 13 - 13 - 1 - - - TR14 - Rising trigger event configuration of - line 14 - 14 - 1 - - - TR15 - Rising trigger event configuration of - line 15 - 15 - 1 - - - TR16 - Rising trigger event configuration of - line 16 - 16 - 1 - - - TR17 - Rising trigger event configuration of - line 17 - 17 - 1 - - - TR18 - Rising trigger event configuration of - line 18 - 18 - 1 - - - - - FTSR - FTSR - Falling Trigger selection register - (EXTI_FTSR) - 0xC - 0x20 - read-write - 0x00000000 - - - TR0 - Falling trigger event configuration of - line 0 - 0 - 1 - - - TR1 - Falling trigger event configuration of - line 1 - 1 - 1 - - - TR2 - Falling trigger event configuration of - line 2 - 2 - 1 - - - TR3 - Falling trigger event configuration of - line 3 - 3 - 1 - - - TR4 - Falling trigger event configuration of - line 4 - 4 - 1 - - - TR5 - Falling trigger event configuration of - line 5 - 5 - 1 - - - TR6 - Falling trigger event configuration of - line 6 - 6 - 1 - - - TR7 - Falling trigger event configuration of - line 7 - 7 - 1 - - - TR8 - Falling trigger event configuration of - line 8 - 8 - 1 - - - TR9 - Falling trigger event configuration of - line 9 - 9 - 1 - - - TR10 - Falling trigger event configuration of - line 10 - 10 - 1 - - - TR11 - Falling trigger event configuration of - line 11 - 11 - 1 - - - TR12 - Falling trigger event configuration of - line 12 - 12 - 1 - - - TR13 - Falling trigger event configuration of - line 13 - 13 - 1 - - - TR14 - Falling trigger event configuration of - line 14 - 14 - 1 - - - TR15 - Falling trigger event configuration of - line 15 - 15 - 1 - - - TR16 - Falling trigger event configuration of - line 16 - 16 - 1 - - - TR17 - Falling trigger event configuration of - line 17 - 17 - 1 - - - TR18 - Falling trigger event configuration of - line 18 - 18 - 1 - - - - - SWIER - SWIER - Software interrupt event register - (EXTI_SWIER) - 0x10 - 0x20 - read-write - 0x00000000 - - - SWIER0 - Software Interrupt on line - 0 - 0 - 1 - - - SWIER1 - Software Interrupt on line - 1 - 1 - 1 - - - SWIER2 - Software Interrupt on line - 2 - 2 - 1 - - - SWIER3 - Software Interrupt on line - 3 - 3 - 1 - - - SWIER4 - Software Interrupt on line - 4 - 4 - 1 - - - SWIER5 - Software Interrupt on line - 5 - 5 - 1 - - - SWIER6 - Software Interrupt on line - 6 - 6 - 1 - - - SWIER7 - Software Interrupt on line - 7 - 7 - 1 - - - SWIER8 - Software Interrupt on line - 8 - 8 - 1 - - - SWIER9 - Software Interrupt on line - 9 - 9 - 1 - - - SWIER10 - Software Interrupt on line - 10 - 10 - 1 - - - SWIER11 - Software Interrupt on line - 11 - 11 - 1 - - - SWIER12 - Software Interrupt on line - 12 - 12 - 1 - - - SWIER13 - Software Interrupt on line - 13 - 13 - 1 - - - SWIER14 - Software Interrupt on line - 14 - 14 - 1 - - - SWIER15 - Software Interrupt on line - 15 - 15 - 1 - - - SWIER16 - Software Interrupt on line - 16 - 16 - 1 - - - SWIER17 - Software Interrupt on line - 17 - 17 - 1 - - - SWIER18 - Software Interrupt on line - 18 - 18 - 1 - - - - - PR - PR - Pending register (EXTI_PR) - 0x14 - 0x20 - read-write - 0x00000000 - - - PR0 - Pending bit 0 - 0 - 1 - - - PR1 - Pending bit 1 - 1 - 1 - - - PR2 - Pending bit 2 - 2 - 1 - - - PR3 - Pending bit 3 - 3 - 1 - - - PR4 - Pending bit 4 - 4 - 1 - - - PR5 - Pending bit 5 - 5 - 1 - - - PR6 - Pending bit 6 - 6 - 1 - - - PR7 - Pending bit 7 - 7 - 1 - - - PR8 - Pending bit 8 - 8 - 1 - - - PR9 - Pending bit 9 - 9 - 1 - - - PR10 - Pending bit 10 - 10 - 1 - - - PR11 - Pending bit 11 - 11 - 1 - - - PR12 - Pending bit 12 - 12 - 1 - - - PR13 - Pending bit 13 - 13 - 1 - - - PR14 - Pending bit 14 - 14 - 1 - - - PR15 - Pending bit 15 - 15 - 1 - - - PR16 - Pending bit 16 - 16 - 1 - - - PR17 - Pending bit 17 - 17 - 1 - - - PR18 - Pending bit 18 - 18 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 11 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 12 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 13 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 14 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 15 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 16 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 17 - - - - ISR - ISR - DMA interrupt status register - (DMA_ISR) - 0x0 - 0x20 - read-only - 0x00000000 - - - GIF1 - Channel 1 Global interrupt - flag - 0 - 1 - - - TCIF1 - Channel 1 Transfer Complete - flag - 1 - 1 - - - HTIF1 - Channel 1 Half Transfer Complete - flag - 2 - 1 - - - TEIF1 - Channel 1 Transfer Error - flag - 3 - 1 - - - GIF2 - Channel 2 Global interrupt - flag - 4 - 1 - - - TCIF2 - Channel 2 Transfer Complete - flag - 5 - 1 - - - HTIF2 - Channel 2 Half Transfer Complete - flag - 6 - 1 - - - TEIF2 - Channel 2 Transfer Error - flag - 7 - 1 - - - GIF3 - Channel 3 Global interrupt - flag - 8 - 1 - - - TCIF3 - Channel 3 Transfer Complete - flag - 9 - 1 - - - HTIF3 - Channel 3 Half Transfer Complete - flag - 10 - 1 - - - TEIF3 - Channel 3 Transfer Error - flag - 11 - 1 - - - GIF4 - Channel 4 Global interrupt - flag - 12 - 1 - - - TCIF4 - Channel 4 Transfer Complete - flag - 13 - 1 - - - HTIF4 - Channel 4 Half Transfer Complete - flag - 14 - 1 - - - TEIF4 - Channel 4 Transfer Error - flag - 15 - 1 - - - GIF5 - Channel 5 Global interrupt - flag - 16 - 1 - - - TCIF5 - Channel 5 Transfer Complete - flag - 17 - 1 - - - HTIF5 - Channel 5 Half Transfer Complete - flag - 18 - 1 - - - TEIF5 - Channel 5 Transfer Error - flag - 19 - 1 - - - GIF6 - Channel 6 Global interrupt - flag - 20 - 1 - - - TCIF6 - Channel 6 Transfer Complete - flag - 21 - 1 - - - HTIF6 - Channel 6 Half Transfer Complete - flag - 22 - 1 - - - TEIF6 - Channel 6 Transfer Error - flag - 23 - 1 - - - GIF7 - Channel 7 Global interrupt - flag - 24 - 1 - - - TCIF7 - Channel 7 Transfer Complete - flag - 25 - 1 - - - HTIF7 - Channel 7 Half Transfer Complete - flag - 26 - 1 - - - TEIF7 - Channel 7 Transfer Error - flag - 27 - 1 - - - - - IFCR - IFCR - DMA interrupt flag clear register - (DMA_IFCR) - 0x4 - 0x20 - write-only - 0x00000000 - - - CGIF1 - Channel 1 Global interrupt - clear - 0 - 1 - - - CGIF2 - Channel 2 Global interrupt - clear - 4 - 1 - - - CGIF3 - Channel 3 Global interrupt - clear - 8 - 1 - - - CGIF4 - Channel 4 Global interrupt - clear - 12 - 1 - - - CGIF5 - Channel 5 Global interrupt - clear - 16 - 1 - - - CGIF6 - Channel 6 Global interrupt - clear - 20 - 1 - - - CGIF7 - Channel 7 Global interrupt - clear - 24 - 1 - - - CTCIF1 - Channel 1 Transfer Complete - clear - 1 - 1 - - - CTCIF2 - Channel 2 Transfer Complete - clear - 5 - 1 - - - CTCIF3 - Channel 3 Transfer Complete - clear - 9 - 1 - - - CTCIF4 - Channel 4 Transfer Complete - clear - 13 - 1 - - - CTCIF5 - Channel 5 Transfer Complete - clear - 17 - 1 - - - CTCIF6 - Channel 6 Transfer Complete - clear - 21 - 1 - - - CTCIF7 - Channel 7 Transfer Complete - clear - 25 - 1 - - - CHTIF1 - Channel 1 Half Transfer - clear - 2 - 1 - - - CHTIF2 - Channel 2 Half Transfer - clear - 6 - 1 - - - CHTIF3 - Channel 3 Half Transfer - clear - 10 - 1 - - - CHTIF4 - Channel 4 Half Transfer - clear - 14 - 1 - - - CHTIF5 - Channel 5 Half Transfer - clear - 18 - 1 - - - CHTIF6 - Channel 6 Half Transfer - clear - 22 - 1 - - - CHTIF7 - Channel 7 Half Transfer - clear - 26 - 1 - - - CTEIF1 - Channel 1 Transfer Error - clear - 3 - 1 - - - CTEIF2 - Channel 2 Transfer Error - clear - 7 - 1 - - - CTEIF3 - Channel 3 Transfer Error - clear - 11 - 1 - - - CTEIF4 - Channel 4 Transfer Error - clear - 15 - 1 - - - CTEIF5 - Channel 5 Transfer Error - clear - 19 - 1 - - - CTEIF6 - Channel 6 Transfer Error - clear - 23 - 1 - - - CTEIF7 - Channel 7 Transfer Error - clear - 27 - 1 - - - - - CCR1 - CCR1 - DMA channel configuration register - (DMA_CCR) - 0x8 - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR1 - CNDTR1 - DMA channel 1 number of data - register - 0xC - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR1 - CPAR1 - DMA channel 1 peripheral address - register - 0x10 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR1 - CMAR1 - DMA channel 1 memory address - register - 0x14 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR2 - CCR2 - DMA channel configuration register - (DMA_CCR) - 0x1C - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR2 - CNDTR2 - DMA channel 2 number of data - register - 0x20 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR2 - CPAR2 - DMA channel 2 peripheral address - register - 0x24 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR2 - CMAR2 - DMA channel 2 memory address - register - 0x28 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR3 - CCR3 - DMA channel configuration register - (DMA_CCR) - 0x30 - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR3 - CNDTR3 - DMA channel 3 number of data - register - 0x34 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR3 - CPAR3 - DMA channel 3 peripheral address - register - 0x38 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR3 - CMAR3 - DMA channel 3 memory address - register - 0x3C - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR4 - CCR4 - DMA channel configuration register - (DMA_CCR) - 0x44 - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR4 - CNDTR4 - DMA channel 4 number of data - register - 0x48 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR4 - CPAR4 - DMA channel 4 peripheral address - register - 0x4C - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR4 - CMAR4 - DMA channel 4 memory address - register - 0x50 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR5 - CCR5 - DMA channel configuration register - (DMA_CCR) - 0x58 - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR5 - CNDTR5 - DMA channel 5 number of data - register - 0x5C - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR5 - CPAR5 - DMA channel 5 peripheral address - register - 0x60 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR5 - CMAR5 - DMA channel 5 memory address - register - 0x64 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR6 - CCR6 - DMA channel configuration register - (DMA_CCR) - 0x6C - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR6 - CNDTR6 - DMA channel 6 number of data - register - 0x70 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR6 - CPAR6 - DMA channel 6 peripheral address - register - 0x74 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR6 - CMAR6 - DMA channel 6 memory address - register - 0x78 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR7 - CCR7 - DMA channel configuration register - (DMA_CCR) - 0x80 - 0x20 - read-write - 0x00000000 - - - EN - Channel enable - 0 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - CIRC - Circular mode - 5 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - MINC - Memory increment mode - 7 - 1 - - - PSIZE - Peripheral size - 8 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PL - Channel Priority level - 12 - 2 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - - - CNDTR7 - CNDTR7 - DMA channel 7 number of data - register - 0x84 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR7 - CPAR7 - DMA channel 7 peripheral address - register - 0x88 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR7 - CMAR7 - DMA channel 7 memory address - register - 0x8C - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - - - DMA2 - 0x40020400 - - DMA2_Channel1 - DMA2 Channel1 global interrupt - 56 - - - DMA2_Channel2 - DMA2 Channel2 global interrupt - 57 - - - DMA2_Channel3 - DMA2 Channel3 global interrupt - 58 - - - DMA2_Channel4_5 - DMA2 Channel4 and DMA2 Channel5 global - interrupt - 59 - - - - SDIO - Secure digital input/output - interface - SDIO - 0x40018000 - - 0x0 - 0x400 - registers - - - SDIO - SDIO global interrupt - 49 - - - - POWER - POWER - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PWRCTRL - PWRCTRL - 0 - 2 - - - - - CLKCR - CLKCR - SDI clock control register - (SDIO_CLKCR) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKDIV - Clock divide factor - 0 - 8 - - - CLKEN - Clock enable bit - 8 - 1 - - - PWRSAV - Power saving configuration - bit - 9 - 1 - - - BYPASS - Clock divider bypass enable - bit - 10 - 1 - - - WIDBUS - Wide bus mode enable bit - 11 - 2 - - - NEGEDGE - SDIO_CK dephasing selection - bit - 13 - 1 - - - HWFC_EN - HW Flow Control enable - 14 - 1 - - - - - ARG - ARG - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - CMDARG - Command argument - 0 - 32 - - - - - CMD - CMD - SDIO command register - (SDIO_CMD) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDINDEX - CMDINDEX - 0 - 6 - - - WAITRESP - WAITRESP - 6 - 2 - - - WAITINT - WAITINT - 8 - 1 - - - WAITPEND - WAITPEND - 9 - 1 - - - CPSMEN - CPSMEN - 10 - 1 - - - SDIOSuspend - SDIOSuspend - 11 - 1 - - - ENCMDcompl - ENCMDcompl - 12 - 1 - - - nIEN - nIEN - 13 - 1 - - - CE_ATACMD - CE_ATACMD - 14 - 1 - - - - - RESPCMD - RESPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RESPCMD - RESPCMD - 0 - 6 - - - - - RESPI1 - RESPI1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTATUS1 - CARDSTATUS1 - 0 - 32 - - - - - RESP2 - RESP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTATUS2 - CARDSTATUS2 - 0 - 32 - - - - - RESP3 - RESP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTATUS3 - CARDSTATUS3 - 0 - 32 - - - - - RESP4 - RESP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTATUS4 - CARDSTATUS4 - 0 - 32 - - - - - DTIMER - DTIMER - Bits 31:0 = DATATIME: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - DATATIME - Data timeout period - 0 - 32 - - - - - DLEN - DLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DATALENGTH - Data length value - 0 - 25 - - - - - DCTRL - DCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - DTEN - DTEN - 0 - 1 - - - DTDIR - DTDIR - 1 - 1 - - - DTMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - DBLOCKSIZE - DBLOCKSIZE - 4 - 4 - - - PWSTART - PWSTART - 8 - 1 - - - PWSTOP - PWSTOP - 9 - 1 - - - RWMOD - RWMOD - 10 - 1 - - - SDIOEN - SDIOEN - 11 - 1 - - - - - DCOUNT - DCOUNT - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - DATACOUNT - Data count value - 0 - 25 - - - - - STA - STA - SDIO status register - (SDIO_STA) - 0x34 - 0x20 - read-only - 0x00000000 - - - CCRCFAIL - CCRCFAIL - 0 - 1 - - - DCRCFAIL - DCRCFAIL - 1 - 1 - - - CTIMEOUT - CTIMEOUT - 2 - 1 - - - DTIMEOUT - DTIMEOUT - 3 - 1 - - - TXUNDERR - TXUNDERR - 4 - 1 - - - RXOVERR - RXOVERR - 5 - 1 - - - CMDREND - CMDREND - 6 - 1 - - - CMDSENT - CMDSENT - 7 - 1 - - - DATAEND - DATAEND - 8 - 1 - - - STBITERR - STBITERR - 9 - 1 - - - DBCKEND - DBCKEND - 10 - 1 - - - CMDACT - CMDACT - 11 - 1 - - - TXACT - TXACT - 12 - 1 - - - RXACT - RXACT - 13 - 1 - - - TXFIFOHE - TXFIFOHE - 14 - 1 - - - RXFIFOHF - RXFIFOHF - 15 - 1 - - - TXFIFOF - TXFIFOF - 16 - 1 - - - RXFIFOF - RXFIFOF - 17 - 1 - - - TXFIFOE - TXFIFOE - 18 - 1 - - - RXFIFOE - RXFIFOE - 19 - 1 - - - TXDAVL - TXDAVL - 20 - 1 - - - RXDAVL - RXDAVL - 21 - 1 - - - SDIOIT - SDIOIT - 22 - 1 - - - CEATAEND - CEATAEND - 23 - 1 - - - - - ICR - ICR - SDIO interrupt clear register - (SDIO_ICR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CCRCFAILC - CCRCFAILC - 0 - 1 - - - DCRCFAILC - DCRCFAILC - 1 - 1 - - - CTIMEOUTC - CTIMEOUTC - 2 - 1 - - - DTIMEOUTC - DTIMEOUTC - 3 - 1 - - - TXUNDERRC - TXUNDERRC - 4 - 1 - - - RXOVERRC - RXOVERRC - 5 - 1 - - - CMDRENDC - CMDRENDC - 6 - 1 - - - CMDSENTC - CMDSENTC - 7 - 1 - - - DATAENDC - DATAENDC - 8 - 1 - - - STBITERRC - STBITERRC - 9 - 1 - - - DBCKENDC - DBCKENDC - 10 - 1 - - - SDIOITC - SDIOITC - 22 - 1 - - - CEATAENDC - CEATAENDC - 23 - 1 - - - - - MASK - MASK - SDIO mask register (SDIO_MASK) - 0x3C - 0x20 - read-write - 0x00000000 - - - CCRCFAILIE - CCRCFAILIE - 0 - 1 - - - DCRCFAILIE - DCRCFAILIE - 1 - 1 - - - CTIMEOUTIE - CTIMEOUTIE - 2 - 1 - - - DTIMEOUTIE - DTIMEOUTIE - 3 - 1 - - - TXUNDERRIE - TXUNDERRIE - 4 - 1 - - - RXOVERRIE - RXOVERRIE - 5 - 1 - - - CMDRENDIE - CMDRENDIE - 6 - 1 - - - CMDSENTIE - CMDSENTIE - 7 - 1 - - - DATAENDIE - DATAENDIE - 8 - 1 - - - STBITERRIE - STBITERRIE - 9 - 1 - - - DBACKENDIE - DBACKENDIE - 10 - 1 - - - CMDACTIE - CMDACTIE - 11 - 1 - - - TXACTIE - TXACTIE - 12 - 1 - - - RXACTIE - RXACTIE - 13 - 1 - - - TXFIFOHEIE - TXFIFOHEIE - 14 - 1 - - - RXFIFOHFIE - RXFIFOHFIE - 15 - 1 - - - TXFIFOFIE - TXFIFOFIE - 16 - 1 - - - RXFIFOFIE - RXFIFOFIE - 17 - 1 - - - TXFIFOEIE - TXFIFOEIE - 18 - 1 - - - RXFIFOEIE - RXFIFOEIE - 19 - 1 - - - TXDAVLIE - TXDAVLIE - 20 - 1 - - - RXDAVLIE - RXDAVLIE - 21 - 1 - - - SDIOITIE - SDIOITIE - 22 - 1 - - - CEATENDIE - CEATENDIE - 23 - 1 - - - - - FIFOCNT - FIFOCNT - Bits 23:0 = FIFOCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - FIF0COUNT - FIF0COUNT - 0 - 24 - - - - - FIFO - FIFO - bits 31:0 = FIFOData: Receive and transmit - FIFO data - 0x80 - 0x20 - read-write - 0x00000000 - - - FIFOData - FIFOData - 0 - 32 - - - - - - - RTC - Real time clock - RTC - 0x40002800 - - 0x0 - 0x400 - registers - - - RTC - RTC global interrupt - 3 - - - RTCAlarm - RTC Alarms through EXTI line - interrupt - 41 - - - - CRH - CRH - RTC Control Register High - 0x0 - 0x20 - read-write - 0x00000000 - - - SECIE - Second interrupt Enable - 0 - 1 - - - ALRIE - Alarm interrupt Enable - 1 - 1 - - - OWIE - Overflow interrupt Enable - 2 - 1 - - - - - CRL - CRL - RTC Control Register Low - 0x4 - 0x20 - 0x00000020 - - - SECF - Second Flag - 0 - 1 - read-write - - - ALRF - Alarm Flag - 1 - 1 - read-write - - - OWF - Overflow Flag - 2 - 1 - read-write - - - RSF - Registers Synchronized - Flag - 3 - 1 - read-write - - - CNF - Configuration Flag - 4 - 1 - read-write - - - RTOFF - RTC operation OFF - 5 - 1 - read-only - - - - - PRLH - PRLH - RTC Prescaler Load Register - High - 0x8 - 0x20 - write-only - 0x00000000 - - - PRLH - RTC Prescaler Load Register - High - 0 - 4 - - - - - PRLL - PRLL - RTC Prescaler Load Register - Low - 0xC - 0x20 - write-only - 0x8000 - - - PRLL - RTC Prescaler Divider Register - Low - 0 - 16 - - - - - DIVH - DIVH - RTC Prescaler Divider Register - High - 0x10 - 0x20 - read-only - 0x00000000 - - - DIVH - RTC prescaler divider register - high - 0 - 4 - - - - - DIVL - DIVL - RTC Prescaler Divider Register - Low - 0x14 - 0x20 - read-only - 0x8000 - - - DIVL - RTC prescaler divider register - Low - 0 - 16 - - - - - CNTH - CNTH - RTC Counter Register High - 0x18 - 0x20 - read-write - 0x00000000 - - - CNTH - RTC counter register high - 0 - 16 - - - - - CNTL - CNTL - RTC Counter Register Low - 0x1C - 0x20 - read-write - 0x00000000 - - - CNTL - RTC counter register Low - 0 - 16 - - - - - ALRH - ALRH - RTC Alarm Register High - 0x20 - 0x20 - write-only - 0xFFFF - - - ALRH - RTC alarm register high - 0 - 16 - - - - - ALRL - ALRL - RTC Alarm Register Low - 0x24 - 0x20 - write-only - 0xFFFF - - - ALRL - RTC alarm register low - 0 - 16 - - - - - - - BKP - Backup registers - BKP - 0x40006C04 - - 0x0 - 0x400 - registers - - - - DR1 - DR1 - Backup data register (BKP_DR) - 0x0 - 0x20 - read-write - 0x00000000 - - - D1 - Backup data - 0 - 16 - - - - - DR2 - DR2 - Backup data register (BKP_DR) - 0x4 - 0x20 - read-write - 0x00000000 - - - D2 - Backup data - 0 - 16 - - - - - DR3 - DR3 - Backup data register (BKP_DR) - 0x8 - 0x20 - read-write - 0x00000000 - - - D3 - Backup data - 0 - 16 - - - - - DR4 - DR4 - Backup data register (BKP_DR) - 0xC - 0x20 - read-write - 0x00000000 - - - D4 - Backup data - 0 - 16 - - - - - DR5 - DR5 - Backup data register (BKP_DR) - 0x10 - 0x20 - read-write - 0x00000000 - - - D5 - Backup data - 0 - 16 - - - - - DR6 - DR6 - Backup data register (BKP_DR) - 0x14 - 0x20 - read-write - 0x00000000 - - - D6 - Backup data - 0 - 16 - - - - - DR7 - DR7 - Backup data register (BKP_DR) - 0x18 - 0x20 - read-write - 0x00000000 - - - D7 - Backup data - 0 - 16 - - - - - DR8 - DR8 - Backup data register (BKP_DR) - 0x1C - 0x20 - read-write - 0x00000000 - - - D8 - Backup data - 0 - 16 - - - - - DR9 - DR9 - Backup data register (BKP_DR) - 0x20 - 0x20 - read-write - 0x00000000 - - - D9 - Backup data - 0 - 16 - - - - - DR10 - DR10 - Backup data register (BKP_DR) - 0x24 - 0x20 - read-write - 0x00000000 - - - D10 - Backup data - 0 - 16 - - - - - DR11 - DR11 - Backup data register (BKP_DR) - 0x3C - 0x20 - read-write - 0x00000000 - - - DR11 - Backup data - 0 - 16 - - - - - DR12 - DR12 - Backup data register (BKP_DR) - 0x40 - 0x20 - read-write - 0x00000000 - - - DR12 - Backup data - 0 - 16 - - - - - DR13 - DR13 - Backup data register (BKP_DR) - 0x44 - 0x20 - read-write - 0x00000000 - - - DR13 - Backup data - 0 - 16 - - - - - DR14 - DR14 - Backup data register (BKP_DR) - 0x48 - 0x20 - read-write - 0x00000000 - - - D14 - Backup data - 0 - 16 - - - - - DR15 - DR15 - Backup data register (BKP_DR) - 0x4C - 0x20 - read-write - 0x00000000 - - - D15 - Backup data - 0 - 16 - - - - - DR16 - DR16 - Backup data register (BKP_DR) - 0x50 - 0x20 - read-write - 0x00000000 - - - D16 - Backup data - 0 - 16 - - - - - DR17 - DR17 - Backup data register (BKP_DR) - 0x54 - 0x20 - read-write - 0x00000000 - - - D17 - Backup data - 0 - 16 - - - - - DR18 - DR18 - Backup data register (BKP_DR) - 0x58 - 0x20 - read-write - 0x00000000 - - - D18 - Backup data - 0 - 16 - - - - - DR19 - DR19 - Backup data register (BKP_DR) - 0x5C - 0x20 - read-write - 0x00000000 - - - D19 - Backup data - 0 - 16 - - - - - DR20 - DR20 - Backup data register (BKP_DR) - 0x60 - 0x20 - read-write - 0x00000000 - - - D20 - Backup data - 0 - 16 - - - - - DR21 - DR21 - Backup data register (BKP_DR) - 0x64 - 0x20 - read-write - 0x00000000 - - - D21 - Backup data - 0 - 16 - - - - - DR22 - DR22 - Backup data register (BKP_DR) - 0x68 - 0x20 - read-write - 0x00000000 - - - D22 - Backup data - 0 - 16 - - - - - DR23 - DR23 - Backup data register (BKP_DR) - 0x6C - 0x20 - read-write - 0x00000000 - - - D23 - Backup data - 0 - 16 - - - - - DR24 - DR24 - Backup data register (BKP_DR) - 0x70 - 0x20 - read-write - 0x00000000 - - - D24 - Backup data - 0 - 16 - - - - - DR25 - DR25 - Backup data register (BKP_DR) - 0x74 - 0x20 - read-write - 0x00000000 - - - D25 - Backup data - 0 - 16 - - - - - DR26 - DR26 - Backup data register (BKP_DR) - 0x78 - 0x20 - read-write - 0x00000000 - - - D26 - Backup data - 0 - 16 - - - - - DR27 - DR27 - Backup data register (BKP_DR) - 0x7C - 0x20 - read-write - 0x00000000 - - - D27 - Backup data - 0 - 16 - - - - - DR28 - DR28 - Backup data register (BKP_DR) - 0x80 - 0x20 - read-write - 0x00000000 - - - D28 - Backup data - 0 - 16 - - - - - DR29 - DR29 - Backup data register (BKP_DR) - 0x84 - 0x20 - read-write - 0x00000000 - - - D29 - Backup data - 0 - 16 - - - - - DR30 - DR30 - Backup data register (BKP_DR) - 0x88 - 0x20 - read-write - 0x00000000 - - - D30 - Backup data - 0 - 16 - - - - - DR31 - DR31 - Backup data register (BKP_DR) - 0x8C - 0x20 - read-write - 0x00000000 - - - D31 - Backup data - 0 - 16 - - - - - DR32 - DR32 - Backup data register (BKP_DR) - 0x90 - 0x20 - read-write - 0x00000000 - - - D32 - Backup data - 0 - 16 - - - - - DR33 - DR33 - Backup data register (BKP_DR) - 0x94 - 0x20 - read-write - 0x00000000 - - - D33 - Backup data - 0 - 16 - - - - - DR34 - DR34 - Backup data register (BKP_DR) - 0x98 - 0x20 - read-write - 0x00000000 - - - D34 - Backup data - 0 - 16 - - - - - DR35 - DR35 - Backup data register (BKP_DR) - 0x9C - 0x20 - read-write - 0x00000000 - - - D35 - Backup data - 0 - 16 - - - - - DR36 - DR36 - Backup data register (BKP_DR) - 0xA0 - 0x20 - read-write - 0x00000000 - - - D36 - Backup data - 0 - 16 - - - - - DR37 - DR37 - Backup data register (BKP_DR) - 0xA4 - 0x20 - read-write - 0x00000000 - - - D37 - Backup data - 0 - 16 - - - - - DR38 - DR38 - Backup data register (BKP_DR) - 0xA8 - 0x20 - read-write - 0x00000000 - - - D38 - Backup data - 0 - 16 - - - - - DR39 - DR39 - Backup data register (BKP_DR) - 0xAC - 0x20 - read-write - 0x00000000 - - - D39 - Backup data - 0 - 16 - - - - - DR40 - DR40 - Backup data register (BKP_DR) - 0xB0 - 0x20 - read-write - 0x00000000 - - - D40 - Backup data - 0 - 16 - - - - - DR41 - DR41 - Backup data register (BKP_DR) - 0xB4 - 0x20 - read-write - 0x00000000 - - - D41 - Backup data - 0 - 16 - - - - - DR42 - DR42 - Backup data register (BKP_DR) - 0xB8 - 0x20 - read-write - 0x00000000 - - - D42 - Backup data - 0 - 16 - - - - - RTCCR - RTCCR - RTC clock calibration register - (BKP_RTCCR) - 0x28 - 0x20 - read-write - 0x00000000 - - - CAL - Calibration value - 0 - 7 - - - CCO - Calibration Clock Output - 7 - 1 - - - ASOE - Alarm or second output - enable - 8 - 1 - - - ASOS - Alarm or second output - selection - 9 - 1 - - - - - CR - CR - Backup control register - (BKP_CR) - 0x2C - 0x20 - read-write - 0x00000000 - - - TPE - Tamper pin enable - 0 - 1 - - - TPAL - Tamper pin active level - 1 - 1 - - - - - CSR - CSR - BKP_CSR control/status register - (BKP_CSR) - 0x30 - 0x20 - 0x00000000 - - - CTE - Clear Tamper event - 0 - 1 - write-only - - - CTI - Clear Tamper Interrupt - 1 - 1 - write-only - - - TPIE - Tamper Pin interrupt - enable - 2 - 1 - read-write - - - TEF - Tamper Event Flag - 8 - 1 - read-only - - - TIF - Tamper Interrupt Flag - 9 - 1 - read-only - - - - - - - IWDG - Independent watchdog - IWDG - 0x40003000 - - 0x0 - 0x400 - registers - - - - KR - KR - Key register (IWDG_KR) - 0x0 - 0x20 - write-only - 0x00000000 - - - KEY - Key value - 0 - 16 - - - - - PR - PR - Prescaler register (IWDG_PR) - 0x4 - 0x20 - read-write - 0x00000000 - - - PR - Prescaler divider - 0 - 3 - - - - - RLR - RLR - Reload register (IWDG_RLR) - 0x8 - 0x20 - read-write - 0x00000FFF - - - RL - Watchdog counter reload - value - 0 - 12 - - - - - SR - SR - Status register (IWDG_SR) - 0xC - 0x20 - read-only - 0x00000000 - - - PVU - Watchdog prescaler value - update - 0 - 1 - - - RVU - Watchdog counter reload value - update - 1 - 1 - - - - - - - WWDG - Window watchdog - WWDG - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDG - Window Watchdog interrupt - 0 - - - - CR - CR - Control register (WWDG_CR) - 0x0 - 0x20 - read-write - 0x0000007F - - - T - 7-bit counter (MSB to LSB) - 0 - 7 - - - WDGA - Activation bit - 7 - 1 - - - - - CFR - CFR - Configuration register - (WWDG_CFR) - 0x4 - 0x20 - read-write - 0x0000007F - - - W - 7-bit window value - 0 - 7 - - - WDGTB - Timer Base - 7 - 2 - - - EWI - Early Wakeup Interrupt - 9 - 1 - - - - - SR - SR - Status register (WWDG_SR) - 0x8 - 0x20 - read-write - 0x00000000 - - - EWI - Early Wakeup Interrupt - 0 - 1 - - - - - - - TIM1 - Advanced timer - TIM - 0x40012C00 - - 0x0 - 0x400 - registers - - - TIM1_BRK_TIM9 - TIM1 Break interrupt and TIM9 global - interrupt - 24 - - - TIM1_UP_TIM10 - TIM1 Update interrupt and TIM10 global - interrupt - 25 - - - TIM1_TRG_COM_TIM11 - TIM1 Trigger and Commutation interrupts and - TIM11 global interrupt - 26 - - - TIM1_CC - TIM1 Capture Compare interrupt - 27 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Clock division - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - CMS - Center-aligned mode - selection - 5 - 2 - - - DIR - Direction - 4 - 1 - - - OPM - One-pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - OIS4 - Output Idle state 4 - 14 - 1 - - - OIS3N - Output Idle state 3 - 13 - 1 - - - OIS3 - Output Idle state 3 - 12 - 1 - - - OIS2N - Output Idle state 2 - 11 - 1 - - - OIS2 - Output Idle state 2 - 10 - 1 - - - OIS1N - Output Idle state 1 - 9 - 1 - - - OIS1 - Output Idle state 1 - 8 - 1 - - - TI1S - TI1 selection - 7 - 1 - - - MMS - Master mode selection - 4 - 3 - - - CCDS - Capture/compare DMA - selection - 3 - 1 - - - CCUS - Capture/compare control update - selection - 2 - 1 - - - CCPC - Capture/compare preloaded - control - 0 - 1 - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x0000 - - - ETP - External trigger polarity - 15 - 1 - - - ECE - External clock enable - 14 - 1 - - - ETPS - External trigger prescaler - 12 - 2 - - - ETF - External trigger filter - 8 - 4 - - - MSM - Master/Slave mode - 7 - 1 - - - TS - Trigger selection - 4 - 3 - - - SMS - Slave mode selection - 0 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDE - Trigger DMA request enable - 14 - 1 - - - COMDE - COM DMA request enable - 13 - 1 - - - CC4DE - Capture/Compare 4 DMA request - enable - 12 - 1 - - - CC3DE - Capture/Compare 3 DMA request - enable - 11 - 1 - - - CC2DE - Capture/Compare 2 DMA request - enable - 10 - 1 - - - CC1DE - Capture/Compare 1 DMA request - enable - 9 - 1 - - - UDE - Update DMA request enable - 8 - 1 - - - TIE - Trigger interrupt enable - 6 - 1 - - - CC4IE - Capture/Compare 4 interrupt - enable - 4 - 1 - - - CC3IE - Capture/Compare 3 interrupt - enable - 3 - 1 - - - CC2IE - Capture/Compare 2 interrupt - enable - 2 - 1 - - - CC1IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - BIE - Break interrupt enable - 7 - 1 - - - COMIE - COM interrupt enable - 5 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC4OF - Capture/Compare 4 overcapture - flag - 12 - 1 - - - CC3OF - Capture/Compare 3 overcapture - flag - 11 - 1 - - - CC2OF - Capture/compare 2 overcapture - flag - 10 - 1 - - - CC1OF - Capture/Compare 1 overcapture - flag - 9 - 1 - - - BIF - Break interrupt flag - 7 - 1 - - - TIF - Trigger interrupt flag - 6 - 1 - - - COMIF - COM interrupt flag - 5 - 1 - - - CC4IF - Capture/Compare 4 interrupt - flag - 4 - 1 - - - CC3IF - Capture/Compare 3 interrupt - flag - 3 - 1 - - - CC2IF - Capture/Compare 2 interrupt - flag - 2 - 1 - - - CC1IF - Capture/compare 1 interrupt - flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - BG - Break generation - 7 - 1 - - - TG - Trigger generation - 6 - 1 - - - COMG - Capture/Compare control update - generation - 5 - 1 - - - CC4G - Capture/compare 4 - generation - 4 - 1 - - - CC3G - Capture/compare 3 - generation - 3 - 1 - - - CC2G - Capture/compare 2 - generation - 2 - 1 - - - CC1G - Capture/compare 1 - generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2CE - Output Compare 2 clear - enable - 15 - 1 - - - OC2M - Output Compare 2 mode - 12 - 3 - - - OC2PE - Output Compare 2 preload - enable - 11 - 1 - - - OC2FE - Output Compare 2 fast - enable - 10 - 1 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - OC1CE - Output Compare 1 clear - enable - 7 - 1 - - - OC1M - Output Compare 1 mode - 4 - 3 - - - OC1PE - Output Compare 1 preload - enable - 3 - 1 - - - OC1FE - Output Compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - IC2PCS - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - IC1F - Input capture 1 filter - 4 - 4 - - - ICPCS - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR2_Output - CCMR2_Output - capture/compare mode register (output - mode) - 0x1C - 0x20 - read-write - 0x00000000 - - - OC4CE - Output compare 4 clear - enable - 15 - 1 - - - OC4M - Output compare 4 mode - 12 - 3 - - - OC4PE - Output compare 4 preload - enable - 11 - 1 - - - OC4FE - Output compare 4 fast - enable - 10 - 1 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - OC3CE - Output compare 3 clear - enable - 7 - 1 - - - OC3M - Output compare 3 mode - 4 - 3 - - - OC3PE - Output compare 3 preload - enable - 3 - 1 - - - OC3FE - Output compare 3 fast - enable - 2 - 1 - - - CC3S - Capture/Compare 3 - selection - 0 - 2 - - - - - CCMR2_Input - CCMR2_Input - capture/compare mode register 2 (input - mode) - CCMR2_Output - 0x1C - 0x20 - read-write - 0x00000000 - - - IC4F - Input capture 4 filter - 12 - 4 - - - IC4PSC - Input capture 4 prescaler - 10 - 2 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - IC3F - Input capture 3 filter - 4 - 4 - - - IC3PSC - Input capture 3 prescaler - 2 - 2 - - - CC3S - Capture/compare 3 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC4P - Capture/Compare 3 output - Polarity - 13 - 1 - - - CC4E - Capture/Compare 4 output - enable - 12 - 1 - - - CC3NP - Capture/Compare 3 output - Polarity - 11 - 1 - - - CC3NE - Capture/Compare 3 complementary output - enable - 10 - 1 - - - CC3P - Capture/Compare 3 output - Polarity - 9 - 1 - - - CC3E - Capture/Compare 3 output - enable - 8 - 1 - - - CC2NP - Capture/Compare 2 output - Polarity - 7 - 1 - - - CC2NE - Capture/Compare 2 complementary output - enable - 6 - 1 - - - CC2P - Capture/Compare 2 output - Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output - enable - 4 - 1 - - - CC1NP - Capture/Compare 1 output - Polarity - 3 - 1 - - - CC1NE - Capture/Compare 1 complementary output - enable - 2 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - CCR2 - CCR2 - capture/compare register 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - CCR2 - Capture/Compare 2 value - 0 - 16 - - - - - CCR3 - CCR3 - capture/compare register 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - CCR3 - Capture/Compare value - 0 - 16 - - - - - CCR4 - CCR4 - capture/compare register 4 - 0x40 - 0x20 - read-write - 0x00000000 - - - CCR4 - Capture/Compare value - 0 - 16 - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DBL - DMA burst length - 8 - 5 - - - DBA - DMA base address - 0 - 5 - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x0000 - - - DMAB - DMA register for burst - accesses - 0 - 16 - - - - - RCR - RCR - repetition counter register - 0x30 - 0x20 - read-write - 0x0000 - - - REP - Repetition counter value - 0 - 8 - - - - - BDTR - BDTR - break and dead-time register - 0x44 - 0x20 - read-write - 0x0000 - - - MOE - Main output enable - 15 - 1 - - - AOE - Automatic output enable - 14 - 1 - - - BKP - Break polarity - 13 - 1 - - - BKE - Break enable - 12 - 1 - - - OSSR - Off-state selection for Run - mode - 11 - 1 - - - OSSI - Off-state selection for Idle - mode - 10 - 1 - - - LOCK - Lock configuration - 8 - 2 - - - DTG - Dead-time generator setup - 0 - 8 - - - - - - - TIM8 - 0x40013400 - - TIM8_BRK_TIM12 - TIM8 Break interrupt and TIM12 global - interrupt - 43 - - - TIM8_UP_TIM13 - TIM8 Update interrupt and TIM13 global - interrupt - 44 - - - TIM8_TRG_COM_TIM14 - TIM8 Trigger and Commutation interrupts and - TIM14 global interrupt - 45 - - - TIM8_CC - TIM8 Capture Compare interrupt - 46 - - - - TIM2 - General purpose timer - TIM - 0x40000000 - - 0x0 - 0x400 - registers - - - TIM2 - TIM2 global interrupt - 28 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Clock division - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - CMS - Center-aligned mode - selection - 5 - 2 - - - DIR - Direction - 4 - 1 - - - OPM - One-pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TI1S - TI1 selection - 7 - 1 - - - MMS - Master mode selection - 4 - 3 - - - CCDS - Capture/compare DMA - selection - 3 - 1 - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x0000 - - - ETP - External trigger polarity - 15 - 1 - - - ECE - External clock enable - 14 - 1 - - - ETPS - External trigger prescaler - 12 - 2 - - - ETF - External trigger filter - 8 - 4 - - - MSM - Master/Slave mode - 7 - 1 - - - TS - Trigger selection - 4 - 3 - - - SMS - Slave mode selection - 0 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDE - Trigger DMA request enable - 14 - 1 - - - CC4DE - Capture/Compare 4 DMA request - enable - 12 - 1 - - - CC3DE - Capture/Compare 3 DMA request - enable - 11 - 1 - - - CC2DE - Capture/Compare 2 DMA request - enable - 10 - 1 - - - CC1DE - Capture/Compare 1 DMA request - enable - 9 - 1 - - - UDE - Update DMA request enable - 8 - 1 - - - TIE - Trigger interrupt enable - 6 - 1 - - - CC4IE - Capture/Compare 4 interrupt - enable - 4 - 1 - - - CC3IE - Capture/Compare 3 interrupt - enable - 3 - 1 - - - CC2IE - Capture/Compare 2 interrupt - enable - 2 - 1 - - - CC1IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC4OF - Capture/Compare 4 overcapture - flag - 12 - 1 - - - CC3OF - Capture/Compare 3 overcapture - flag - 11 - 1 - - - CC2OF - Capture/compare 2 overcapture - flag - 10 - 1 - - - CC1OF - Capture/Compare 1 overcapture - flag - 9 - 1 - - - TIF - Trigger interrupt flag - 6 - 1 - - - CC4IF - Capture/Compare 4 interrupt - flag - 4 - 1 - - - CC3IF - Capture/Compare 3 interrupt - flag - 3 - 1 - - - CC2IF - Capture/Compare 2 interrupt - flag - 2 - 1 - - - CC1IF - Capture/compare 1 interrupt - flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - TG - Trigger generation - 6 - 1 - - - CC4G - Capture/compare 4 - generation - 4 - 1 - - - CC3G - Capture/compare 3 - generation - 3 - 1 - - - CC2G - Capture/compare 2 - generation - 2 - 1 - - - CC1G - Capture/compare 1 - generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register 1 (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2CE - Output compare 2 clear - enable - 15 - 1 - - - OC2M - Output compare 2 mode - 12 - 3 - - - OC2PE - Output compare 2 preload - enable - 11 - 1 - - - OC2FE - Output compare 2 fast - enable - 10 - 1 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - OC1CE - Output compare 1 clear - enable - 7 - 1 - - - OC1M - Output compare 1 mode - 4 - 3 - - - OC1PE - Output compare 1 preload - enable - 3 - 1 - - - OC1FE - Output compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/compare 2 - selection - 8 - 2 - - - IC1F - Input capture 1 filter - 4 - 4 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR2_Output - CCMR2_Output - capture/compare mode register 2 (output - mode) - 0x1C - 0x20 - read-write - 0x00000000 - - - O24CE - Output compare 4 clear - enable - 15 - 1 - - - OC4M - Output compare 4 mode - 12 - 3 - - - OC4PE - Output compare 4 preload - enable - 11 - 1 - - - OC4FE - Output compare 4 fast - enable - 10 - 1 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - OC3CE - Output compare 3 clear - enable - 7 - 1 - - - OC3M - Output compare 3 mode - 4 - 3 - - - OC3PE - Output compare 3 preload - enable - 3 - 1 - - - OC3FE - Output compare 3 fast - enable - 2 - 1 - - - CC3S - Capture/Compare 3 - selection - 0 - 2 - - - - - CCMR2_Input - CCMR2_Input - capture/compare mode register 2 (input - mode) - CCMR2_Output - 0x1C - 0x20 - read-write - 0x00000000 - - - IC4F - Input capture 4 filter - 12 - 4 - - - IC4PSC - Input capture 4 prescaler - 10 - 2 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - IC3F - Input capture 3 filter - 4 - 4 - - - IC3PSC - Input capture 3 prescaler - 2 - 2 - - - CC3S - Capture/Compare 3 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC4P - Capture/Compare 3 output - Polarity - 13 - 1 - - - CC4E - Capture/Compare 4 output - enable - 12 - 1 - - - CC3P - Capture/Compare 3 output - Polarity - 9 - 1 - - - CC3E - Capture/Compare 3 output - enable - 8 - 1 - - - CC2P - Capture/Compare 2 output - Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output - enable - 4 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - CCR2 - CCR2 - capture/compare register 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - CCR2 - Capture/Compare 2 value - 0 - 16 - - - - - CCR3 - CCR3 - capture/compare register 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - CCR3 - Capture/Compare value - 0 - 16 - - - - - CCR4 - CCR4 - capture/compare register 4 - 0x40 - 0x20 - read-write - 0x00000000 - - - CCR4 - Capture/Compare value - 0 - 16 - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DBL - DMA burst length - 8 - 5 - - - DBA - DMA base address - 0 - 5 - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x0000 - - - DMAB - DMA register for burst - accesses - 0 - 16 - - - - - - - TIM3 - 0x40000400 - - TIM3 - TIM3 global interrupt - 29 - - - - TIM4 - 0x40000800 - - TIM4 - TIM4 global interrupt - 30 - - - - TIM5 - 0x40000C00 - - TIM5 - TIM5 global interrupt - 50 - - - - TIM9 - General purpose timer - TIM - 0x40014C00 - - 0x0 - 0x400 - registers - - - TIM1_BRK_TIM9 - TIM1 Break interrupt and TIM9 global - interrupt - 24 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Clock division - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - OPM - One-pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MMS - Master mode selection - 4 - 3 - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x0000 - - - MSM - Master/Slave mode - 7 - 1 - - - TS - Trigger selection - 4 - 3 - - - SMS - Slave mode selection - 0 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - TIE - Trigger interrupt enable - 6 - 1 - - - CC2IE - Capture/Compare 2 interrupt - enable - 2 - 1 - - - CC1IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC2OF - Capture/compare 2 overcapture - flag - 10 - 1 - - - CC1OF - Capture/Compare 1 overcapture - flag - 9 - 1 - - - TIF - Trigger interrupt flag - 6 - 1 - - - CC2IF - Capture/Compare 2 interrupt - flag - 2 - 1 - - - CC1IF - Capture/compare 1 interrupt - flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - TG - Trigger generation - 6 - 1 - - - CC2G - Capture/compare 2 - generation - 2 - 1 - - - CC1G - Capture/compare 1 - generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register 1 (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2M - Output Compare 2 mode - 12 - 3 - - - OC2PE - Output Compare 2 preload - enable - 11 - 1 - - - OC2FE - Output Compare 2 fast - enable - 10 - 1 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - OC1M - Output Compare 1 mode - 4 - 3 - - - OC1PE - Output Compare 1 preload - enable - 3 - 1 - - - OC1FE - Output Compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - IC1F - Input capture 1 filter - 4 - 4 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC2NP - Capture/Compare 2 output - Polarity - 7 - 1 - - - CC2P - Capture/Compare 2 output - Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output - enable - 4 - 1 - - - CC1NP - Capture/Compare 1 output - Polarity - 3 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - CCR2 - CCR2 - capture/compare register 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - CCR2 - Capture/Compare 2 value - 0 - 16 - - - - - - - TIM12 - 0x40001800 - - TIM8_BRK_TIM12 - TIM8 Break interrupt and TIM12 global - interrupt - 43 - - - - TIM10 - General purpose timer - TIM - 0x40015000 - - 0x0 - 0x400 - registers - - - TIM1_UP_TIM10 - TIM1 Update interrupt and TIM10 global - interrupt - 25 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Clock division - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MMS - Master mode selection - 4 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - CC1IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC1OF - Capture/Compare 1 overcapture - flag - 9 - 1 - - - CC1IF - Capture/compare 1 interrupt - flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - CC1G - Capture/compare 1 - generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC1M - Output Compare 1 mode - 4 - 3 - - - OC1PE - Output Compare 1 preload - enable - 3 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC1F - Input capture 1 filter - 4 - 4 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC1NP - Capture/Compare 1 output - Polarity - 3 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - - - TIM11 - 0x40015400 - - TIM1_TRG_COM_TIM11 - TIM1 Trigger and Commutation interrupts and - TIM11 global interrupt - 26 - - - - TIM13 - 0x40001C00 - - TIM8_UP_TIM13 - TIM8 Update interrupt and TIM13 global - interrupt - 44 - - - - TIM14 - 0x40002000 - - TIM8_TRG_COM_TIM14 - TIM8 Trigger and Commutation interrupts and - TIM14 global interrupt - 45 - - - - TIM6 - Basic timer - TIM - 0x40001000 - - 0x0 - 0x400 - registers - - - TIM6 - TIM6 global interrupt - 54 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - OPM - One-pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MMS - Master mode selection - 4 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - UDE - Update DMA request enable - 8 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - UG - Update generation - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - Low counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Low Auto-reload value - 0 - 16 - - - - - - - TIM7 - 0x40001400 - - TIM7 - TIM7 global interrupt - 55 - - - - I2C1 - Inter integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EV - I2C1 event interrupt - 31 - - - I2C1_ER - I2C1 error interrupt - 32 - - - - CR1 - CR1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SWRST - Software reset - 15 - 1 - - - ALERT - SMBus alert - 13 - 1 - - - PEC - Packet error checking - 12 - 1 - - - POS - Acknowledge/PEC Position (for data - reception) - 11 - 1 - - - ACK - Acknowledge enable - 10 - 1 - - - STOP - Stop generation - 9 - 1 - - - START - Start generation - 8 - 1 - - - NOSTRETCH - Clock stretching disable (Slave - mode) - 7 - 1 - - - ENGC - General call enable - 6 - 1 - - - ENPEC - PEC enable - 5 - 1 - - - ENARP - ARP enable - 4 - 1 - - - SMBTYPE - SMBus type - 3 - 1 - - - SMBUS - SMBus mode - 1 - 1 - - - PE - Peripheral enable - 0 - 1 - - - - - CR2 - CR2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - LAST - DMA last transfer - 12 - 1 - - - DMAEN - DMA requests enable - 11 - 1 - - - ITBUFEN - Buffer interrupt enable - 10 - 1 - - - ITEVTEN - Event interrupt enable - 9 - 1 - - - ITERREN - Error interrupt enable - 8 - 1 - - - FREQ - Peripheral clock frequency - 0 - 6 - - - - - OAR1 - OAR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - ADDMODE - Addressing mode (slave - mode) - 15 - 1 - - - ADD10 - Interface address - 8 - 2 - - - ADD7 - Interface address - 1 - 7 - - - ADD0 - Interface address - 0 - 1 - - - - - OAR2 - OAR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x0000 - - - ADD2 - Interface address - 1 - 7 - - - ENDUAL - Dual addressing mode - enable - 0 - 1 - - - - - DR - DR - Data register - 0x10 - 0x20 - read-write - 0x0000 - - - DR - 8-bit data register - 0 - 8 - - - - - SR1 - SR1 - Status register 1 - 0x14 - 0x20 - 0x0000 - - - SMBALERT - SMBus alert - 15 - 1 - read-write - - - TIMEOUT - Timeout or Tlow error - 14 - 1 - read-write - - - PECERR - PEC Error in reception - 12 - 1 - read-write - - - OVR - Overrun/Underrun - 11 - 1 - read-write - - - AF - Acknowledge failure - 10 - 1 - read-write - - - ARLO - Arbitration lost (master - mode) - 9 - 1 - read-write - - - BERR - Bus error - 8 - 1 - read-write - - - TxE - Data register empty - (transmitters) - 7 - 1 - read-only - - - RxNE - Data register not empty - (receivers) - 6 - 1 - read-only - - - STOPF - Stop detection (slave - mode) - 4 - 1 - read-only - - - ADD10 - 10-bit header sent (Master - mode) - 3 - 1 - read-only - - - BTF - Byte transfer finished - 2 - 1 - read-only - - - ADDR - Address sent (master mode)/matched - (slave mode) - 1 - 1 - read-only - - - SB - Start bit (Master mode) - 0 - 1 - read-only - - - - - SR2 - SR2 - Status register 2 - 0x18 - 0x20 - read-only - 0x0000 - - - PEC - acket error checking - register - 8 - 8 - - - DUALF - Dual flag (Slave mode) - 7 - 1 - - - SMBHOST - SMBus host header (Slave - mode) - 6 - 1 - - - SMBDEFAULT - SMBus device default address (Slave - mode) - 5 - 1 - - - GENCALL - General call address (Slave - mode) - 4 - 1 - - - TRA - Transmitter/receiver - 2 - 1 - - - BUSY - Bus busy - 1 - 1 - - - MSL - Master/slave - 0 - 1 - - - - - CCR - CCR - Clock control register - 0x1C - 0x20 - read-write - 0x0000 - - - F_S - I2C master mode selection - 15 - 1 - - - DUTY - Fast mode duty cycle - 14 - 1 - - - CCR - Clock control register in Fast/Standard - mode (Master mode) - 0 - 12 - - - - - TRISE - TRISE - TRISE register - 0x20 - 0x20 - read-write - 0x0002 - - - TRISE - Maximum rise time in Fast/Standard mode - (Master mode) - 0 - 6 - - - - - - - I2C2 - 0x40005800 - - I2C2_EV - I2C2 event interrupt - 33 - - - I2C2_ER - I2C2 error interrupt - 34 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - BIDIMODE - Bidirectional data mode - enable - 15 - 1 - - - BIDIOE - Output enable in bidirectional - mode - 14 - 1 - - - CRCEN - Hardware CRC calculation - enable - 13 - 1 - - - CRCNEXT - CRC transfer next - 12 - 1 - - - DFF - Data frame format - 11 - 1 - - - RXONLY - Receive only - 10 - 1 - - - SSM - Software slave management - 9 - 1 - - - SSI - Internal slave select - 8 - 1 - - - LSBFIRST - Frame format - 7 - 1 - - - SPE - SPI enable - 6 - 1 - - - BR - Baud rate control - 3 - 3 - - - MSTR - Master selection - 2 - 1 - - - CPOL - Clock polarity - 1 - 1 - - - CPHA - Clock phase - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TXEIE - Tx buffer empty interrupt - enable - 7 - 1 - - - RXNEIE - RX buffer not empty interrupt - enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - SSOE - SS output enable - 2 - 1 - - - TXDMAEN - Tx buffer DMA enable - 1 - 1 - - - RXDMAEN - Rx buffer DMA enable - 0 - 1 - - - - - SR - SR - status register - 0x8 - 0x20 - 0x0002 - - - BSY - Busy flag - 7 - 1 - read-only - - - OVR - Overrun flag - 6 - 1 - read-only - - - MODF - Mode fault - 5 - 1 - read-only - - - CRCERR - CRC error flag - 4 - 1 - read-write - - - UDR - Underrun flag - 3 - 1 - read-only - - - CHSIDE - Channel side - 2 - 1 - read-only - - - TXE - Transmit buffer empty - 1 - 1 - read-only - - - RXNE - Receive buffer not empty - 0 - 1 - read-only - - - - - DR - DR - data register - 0xC - 0x20 - read-write - 0x0000 - - - DR - Data register - 0 - 16 - - - - - CRCPR - CRCPR - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CRCPOLY - CRC polynomial register - 0 - 16 - - - - - RXCRCR - RXCRCR - RX CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RxCRC - Rx CRC register - 0 - 16 - - - - - TXCRCR - TXCRCR - TX CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TxCRC - Tx CRC register - 0 - 16 - - - - - I2SCFGR - I2SCFGR - I2S configuration register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMOD - I2S mode selection - 11 - 1 - - - I2SE - I2S Enable - 10 - 1 - - - I2SCFG - I2S configuration mode - 8 - 2 - - - PCMSYNC - PCM frame synchronization - 7 - 1 - - - I2SSTD - I2S standard selection - 4 - 2 - - - CKPOL - Steady state clock - polarity - 3 - 1 - - - DATLEN - Data length to be - transferred - 1 - 2 - - - CHLEN - Channel length (number of bits per audio - channel) - 0 - 1 - - - - - I2SPR - I2SPR - I2S prescaler register - 0x20 - 0x20 - read-write - 00000010 - - - MCKOE - Master clock output enable - 9 - 1 - - - ODD - Odd factor for the - prescaler - 8 - 1 - - - I2SDIV - I2S Linear prescaler - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - SPI3 - 0x40003C00 - - SPI3 - SPI3 global interrupt - 51 - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - SR - SR - Status register - 0x0 - 0x20 - 0x00C0 - - - CTS - CTS flag - 9 - 1 - read-write - - - LBD - LIN break detection flag - 8 - 1 - read-write - - - TXE - Transmit data register - empty - 7 - 1 - read-only - - - TC - Transmission complete - 6 - 1 - read-write - - - RXNE - Read data register not - empty - 5 - 1 - read-write - - - IDLE - IDLE line detected - 4 - 1 - read-only - - - ORE - Overrun error - 3 - 1 - read-only - - - NE - Noise error flag - 2 - 1 - read-only - - - FE - Framing error - 1 - 1 - read-only - - - PE - Parity error - 0 - 1 - read-only - - - - - DR - DR - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DR - Data value - 0 - 9 - - - - - BRR - BRR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV_Mantissa - mantissa of USARTDIV - 4 - 12 - - - DIV_Fraction - fraction of USARTDIV - 0 - 4 - - - - - CR1 - CR1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - UE - USART enable - 13 - 1 - - - M - Word length - 12 - 1 - - - WAKE - Wakeup method - 11 - 1 - - - PCE - Parity control enable - 10 - 1 - - - PS - Parity selection - 9 - 1 - - - PEIE - PE interrupt enable - 8 - 1 - - - TXEIE - TXE interrupt enable - 7 - 1 - - - TCIE - Transmission complete interrupt - enable - 6 - 1 - - - RXNEIE - RXNE interrupt enable - 5 - 1 - - - IDLEIE - IDLE interrupt enable - 4 - 1 - - - TE - Transmitter enable - 3 - 1 - - - RE - Receiver enable - 2 - 1 - - - RWU - Receiver wakeup - 1 - 1 - - - SBK - Send break - 0 - 1 - - - - - CR2 - CR2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - LINEN - LIN mode enable - 14 - 1 - - - STOP - STOP bits - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CPOL - Clock polarity - 10 - 1 - - - CPHA - Clock phase - 9 - 1 - - - LBCL - Last bit clock pulse - 8 - 1 - - - LBDIE - LIN break detection interrupt - enable - 6 - 1 - - - LBDL - lin break detection length - 5 - 1 - - - ADD - Address of the USART node - 0 - 4 - - - - - CR3 - CR3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - CTSIE - CTS interrupt enable - 10 - 1 - - - CTSE - CTS enable - 9 - 1 - - - RTSE - RTS enable - 8 - 1 - - - DMAT - DMA enable transmitter - 7 - 1 - - - DMAR - DMA enable receiver - 6 - 1 - - - SCEN - Smartcard mode enable - 5 - 1 - - - NACK - Smartcard NACK enable - 4 - 1 - - - HDSEL - Half-duplex selection - 3 - 1 - - - IRLP - IrDA low-power - 2 - 1 - - - IREN - IrDA mode enable - 1 - 1 - - - EIE - Error interrupt enable - 0 - 1 - - - - - GTPR - GTPR - Guard time and prescaler - register - 0x18 - 0x20 - read-write - 0x0000 - - - GT - Guard time value - 8 - 8 - - - PSC - Prescaler value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - ADC1 - Analog to digital converter - ADC - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC - ADC1 global interrupt - 18 - - - - SR - SR - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - STRT - Regular channel start flag - 4 - 1 - - - JSTRT - Injected channel start - flag - 3 - 1 - - - JEOC - Injected channel end of - conversion - 2 - 1 - - - EOC - Regular channel end of - conversion - 1 - 1 - - - AWD - Analog watchdog flag - 0 - 1 - - - - - CR1 - CR1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - AWDEN - Analog watchdog enable on regular - channels - 23 - 1 - - - JAWDEN - Analog watchdog enable on injected - channels - 22 - 1 - - - DUALMOD - Dual mode selection - 16 - 4 - - - DISCNUM - Discontinuous mode channel - count - 13 - 3 - - - JDISCEN - Discontinuous mode on injected - channels - 12 - 1 - - - DISCEN - Discontinuous mode on regular - channels - 11 - 1 - - - JAUTO - Automatic injected group - conversion - 10 - 1 - - - AWDSGL - Enable the watchdog on a single channel - in scan mode - 9 - 1 - - - SCAN - Scan mode - 8 - 1 - - - JEOCIE - Interrupt enable for injected - channels - 7 - 1 - - - AWDIE - Analog watchdog interrupt - enable - 6 - 1 - - - EOCIE - Interrupt enable for EOC - 5 - 1 - - - AWDCH - Analog watchdog channel select - bits - 0 - 5 - - - - - CR2 - CR2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - TSVREFE - Temperature sensor and VREFINT - enable - 23 - 1 - - - SWSTART - Start conversion of regular - channels - 22 - 1 - - - JSWSTART - Start conversion of injected - channels - 21 - 1 - - - EXTTRIG - External trigger conversion mode for - regular channels - 20 - 1 - - - EXTSEL - External event select for regular - group - 17 - 3 - - - JEXTTRIG - External trigger conversion mode for - injected channels - 15 - 1 - - - JEXTSEL - External event select for injected - group - 12 - 3 - - - ALIGN - Data alignment - 11 - 1 - - - DMA - Direct memory access mode - 8 - 1 - - - RSTCAL - Reset calibration - 3 - 1 - - - CAL - A/D calibration - 2 - 1 - - - CONT - Continuous conversion - 1 - 1 - - - ADON - A/D converter ON / OFF - 0 - 1 - - - - - SMPR1 - SMPR1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - SMP10 - Channel 10 sample time - selection - 0 - 3 - - - SMP11 - Channel 11 sample time - selection - 3 - 3 - - - SMP12 - Channel 12 sample time - selection - 6 - 3 - - - SMP13 - Channel 13 sample time - selection - 9 - 3 - - - SMP14 - Channel 14 sample time - selection - 12 - 3 - - - SMP15 - Channel 15 sample time - selection - 15 - 3 - - - SMP16 - Channel 16 sample time - selection - 18 - 3 - - - SMP17 - Channel 17 sample time - selection - 21 - 3 - - - - - SMPR2 - SMPR2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - SMP0 - Channel 0 sample time - selection - 0 - 3 - - - SMP1 - Channel 1 sample time - selection - 3 - 3 - - - SMP2 - Channel 2 sample time - selection - 6 - 3 - - - SMP3 - Channel 3 sample time - selection - 9 - 3 - - - SMP4 - Channel 4 sample time - selection - 12 - 3 - - - SMP5 - Channel 5 sample time - selection - 15 - 3 - - - SMP6 - Channel 6 sample time - selection - 18 - 3 - - - SMP7 - Channel 7 sample time - selection - 21 - 3 - - - SMP8 - Channel 8 sample time - selection - 24 - 3 - - - SMP9 - Channel 9 sample time - selection - 27 - 3 - - - - - JOFR1 - JOFR1 - injected channel data offset register - x - 0x14 - 0x20 - read-write - 0x00000000 - - - JOFFSET1 - Data offset for injected channel - x - 0 - 12 - - - - - JOFR2 - JOFR2 - injected channel data offset register - x - 0x18 - 0x20 - read-write - 0x00000000 - - - JOFFSET2 - Data offset for injected channel - x - 0 - 12 - - - - - JOFR3 - JOFR3 - injected channel data offset register - x - 0x1C - 0x20 - read-write - 0x00000000 - - - JOFFSET3 - Data offset for injected channel - x - 0 - 12 - - - - - JOFR4 - JOFR4 - injected channel data offset register - x - 0x20 - 0x20 - read-write - 0x00000000 - - - JOFFSET4 - Data offset for injected channel - x - 0 - 12 - - - - - HTR - HTR - watchdog higher threshold - register - 0x24 - 0x20 - read-write - 0x00000FFF - - - HT - Analog watchdog higher - threshold - 0 - 12 - - - - - LTR - LTR - watchdog lower threshold - register - 0x28 - 0x20 - read-write - 0x00000000 - - - LT - Analog watchdog lower - threshold - 0 - 12 - - - - - SQR1 - SQR1 - regular sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - L - Regular channel sequence - length - 20 - 4 - - - SQ16 - 16th conversion in regular - sequence - 15 - 5 - - - SQ15 - 15th conversion in regular - sequence - 10 - 5 - - - SQ14 - 14th conversion in regular - sequence - 5 - 5 - - - SQ13 - 13th conversion in regular - sequence - 0 - 5 - - - - - SQR2 - SQR2 - regular sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - SQ12 - 12th conversion in regular - sequence - 25 - 5 - - - SQ11 - 11th conversion in regular - sequence - 20 - 5 - - - SQ10 - 10th conversion in regular - sequence - 15 - 5 - - - SQ9 - 9th conversion in regular - sequence - 10 - 5 - - - SQ8 - 8th conversion in regular - sequence - 5 - 5 - - - SQ7 - 7th conversion in regular - sequence - 0 - 5 - - - - - SQR3 - SQR3 - regular sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - SQ6 - 6th conversion in regular - sequence - 25 - 5 - - - SQ5 - 5th conversion in regular - sequence - 20 - 5 - - - SQ4 - 4th conversion in regular - sequence - 15 - 5 - - - SQ3 - 3rd conversion in regular - sequence - 10 - 5 - - - SQ2 - 2nd conversion in regular - sequence - 5 - 5 - - - SQ1 - 1st conversion in regular - sequence - 0 - 5 - - - - - JSQR - JSQR - injected sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - JL - Injected sequence length - 20 - 2 - - - JSQ4 - 4th conversion in injected - sequence - 15 - 5 - - - JSQ3 - 3rd conversion in injected - sequence - 10 - 5 - - - JSQ2 - 2nd conversion in injected - sequence - 5 - 5 - - - JSQ1 - 1st conversion in injected - sequence - 0 - 5 - - - - - JDR1 - JDR1 - injected data register x - 0x3C - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - JDR2 - JDR2 - injected data register x - 0x40 - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - JDR3 - JDR3 - injected data register x - 0x44 - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - JDR4 - JDR4 - injected data register x - 0x48 - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - DR - DR - regular data register - 0x4C - 0x20 - read-only - 0x00000000 - - - DATA - Regular data - 0 - 16 - - - ADC2DATA - ADC2 data - 16 - 16 - - - - - - - ADC2 - Analog to digital converter - ADC - 0x40012800 - - 0x0 - 0x400 - registers - - - ADC - ADC2 global interrupt - 18 - - - - SR - SR - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - STRT - Regular channel start flag - 4 - 1 - - - JSTRT - Injected channel start - flag - 3 - 1 - - - JEOC - Injected channel end of - conversion - 2 - 1 - - - EOC - Regular channel end of - conversion - 1 - 1 - - - AWD - Analog watchdog flag - 0 - 1 - - - - - CR1 - CR1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - AWDEN - Analog watchdog enable on regular - channels - 23 - 1 - - - JAWDEN - Analog watchdog enable on injected - channels - 22 - 1 - - - DISCNUM - Discontinuous mode channel - count - 13 - 3 - - - JDISCEN - Discontinuous mode on injected - channels - 12 - 1 - - - DISCEN - Discontinuous mode on regular - channels - 11 - 1 - - - JAUTO - Automatic injected group - conversion - 10 - 1 - - - AWDSGL - Enable the watchdog on a single channel - in scan mode - 9 - 1 - - - SCAN - Scan mode - 8 - 1 - - - JEOCIE - Interrupt enable for injected - channels - 7 - 1 - - - AWDIE - Analog watchdog interrupt - enable - 6 - 1 - - - EOCIE - Interrupt enable for EOC - 5 - 1 - - - AWDCH - Analog watchdog channel select - bits - 0 - 5 - - - - - CR2 - CR2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - TSVREFE - Temperature sensor and VREFINT - enable - 23 - 1 - - - SWSTART - Start conversion of regular - channels - 22 - 1 - - - JSWSTART - Start conversion of injected - channels - 21 - 1 - - - EXTTRIG - External trigger conversion mode for - regular channels - 20 - 1 - - - EXTSEL - External event select for regular - group - 17 - 3 - - - JEXTTRIG - External trigger conversion mode for - injected channels - 15 - 1 - - - JEXTSEL - External event select for injected - group - 12 - 3 - - - ALIGN - Data alignment - 11 - 1 - - - DMA - Direct memory access mode - 8 - 1 - - - RSTCAL - Reset calibration - 3 - 1 - - - CAL - A/D calibration - 2 - 1 - - - CONT - Continuous conversion - 1 - 1 - - - ADON - A/D converter ON / OFF - 0 - 1 - - - - - SMPR1 - SMPR1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - SMP10 - Channel 10 sample time - selection - 0 - 3 - - - SMP11 - Channel 11 sample time - selection - 3 - 3 - - - SMP12 - Channel 12 sample time - selection - 6 - 3 - - - SMP13 - Channel 13 sample time - selection - 9 - 3 - - - SMP14 - Channel 14 sample time - selection - 12 - 3 - - - SMP15 - Channel 15 sample time - selection - 15 - 3 - - - SMP16 - Channel 16 sample time - selection - 18 - 3 - - - SMP17 - Channel 17 sample time - selection - 21 - 3 - - - - - SMPR2 - SMPR2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - SMP0 - Channel 0 sample time - selection - 0 - 3 - - - SMP1 - Channel 1 sample time - selection - 3 - 3 - - - SMP2 - Channel 2 sample time - selection - 6 - 3 - - - SMP3 - Channel 3 sample time - selection - 9 - 3 - - - SMP4 - Channel 4 sample time - selection - 12 - 3 - - - SMP5 - Channel 5 sample time - selection - 15 - 3 - - - SMP6 - Channel 6 sample time - selection - 18 - 3 - - - SMP7 - Channel 7 sample time - selection - 21 - 3 - - - SMP8 - Channel 8 sample time - selection - 24 - 3 - - - SMP9 - Channel 9 sample time - selection - 27 - 3 - - - - - JOFR1 - JOFR1 - injected channel data offset register - x - 0x14 - 0x20 - read-write - 0x00000000 - - - JOFFSET1 - Data offset for injected channel - x - 0 - 12 - - - - - JOFR2 - JOFR2 - injected channel data offset register - x - 0x18 - 0x20 - read-write - 0x00000000 - - - JOFFSET2 - Data offset for injected channel - x - 0 - 12 - - - - - JOFR3 - JOFR3 - injected channel data offset register - x - 0x1C - 0x20 - read-write - 0x00000000 - - - JOFFSET3 - Data offset for injected channel - x - 0 - 12 - - - - - JOFR4 - JOFR4 - injected channel data offset register - x - 0x20 - 0x20 - read-write - 0x00000000 - - - JOFFSET4 - Data offset for injected channel - x - 0 - 12 - - - - - HTR - HTR - watchdog higher threshold - register - 0x24 - 0x20 - read-write - 0x00000FFF - - - HT - Analog watchdog higher - threshold - 0 - 12 - - - - - LTR - LTR - watchdog lower threshold - register - 0x28 - 0x20 - read-write - 0x00000000 - - - LT - Analog watchdog lower - threshold - 0 - 12 - - - - - SQR1 - SQR1 - regular sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - L - Regular channel sequence - length - 20 - 4 - - - SQ16 - 16th conversion in regular - sequence - 15 - 5 - - - SQ15 - 15th conversion in regular - sequence - 10 - 5 - - - SQ14 - 14th conversion in regular - sequence - 5 - 5 - - - SQ13 - 13th conversion in regular - sequence - 0 - 5 - - - - - SQR2 - SQR2 - regular sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - SQ12 - 12th conversion in regular - sequence - 25 - 5 - - - SQ11 - 11th conversion in regular - sequence - 20 - 5 - - - SQ10 - 10th conversion in regular - sequence - 15 - 5 - - - SQ9 - 9th conversion in regular - sequence - 10 - 5 - - - SQ8 - 8th conversion in regular - sequence - 5 - 5 - - - SQ7 - 7th conversion in regular - sequence - 0 - 5 - - - - - SQR3 - SQR3 - regular sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - SQ6 - 6th conversion in regular - sequence - 25 - 5 - - - SQ5 - 5th conversion in regular - sequence - 20 - 5 - - - SQ4 - 4th conversion in regular - sequence - 15 - 5 - - - SQ3 - 3rd conversion in regular - sequence - 10 - 5 - - - SQ2 - 2nd conversion in regular - sequence - 5 - 5 - - - SQ1 - 1st conversion in regular - sequence - 0 - 5 - - - - - JSQR - JSQR - injected sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - JL - Injected sequence length - 20 - 2 - - - JSQ4 - 4th conversion in injected - sequence - 15 - 5 - - - JSQ3 - 3rd conversion in injected - sequence - 10 - 5 - - - JSQ2 - 2nd conversion in injected - sequence - 5 - 5 - - - JSQ1 - 1st conversion in injected - sequence - 0 - 5 - - - - - JDR1 - JDR1 - injected data register x - 0x3C - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - JDR2 - JDR2 - injected data register x - 0x40 - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - JDR3 - JDR3 - injected data register x - 0x44 - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - JDR4 - JDR4 - injected data register x - 0x48 - 0x20 - read-only - 0x00000000 - - - JDATA - Injected data - 0 - 16 - - - - - DR - DR - regular data register - 0x4C - 0x20 - read-only - 0x00000000 - - - DATA - Regular data - 0 - 16 - - - - - - - ADC3 - 0x40013C00 - - ADC3 - ADC3 global interrupt - 47 - - - - CAN - Controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN1_TX - CAN1 TX interrupts - 19 - - - CAN1_RX0 - CAN1 RX0 interrupts - 20 - - - CAN1_RX1 - CAN1 RX1 interrupt - 21 - - - CAN1_SCE - CAN1 SCE interrupt - 22 - - - - CAN_MCR - CAN_MCR - CAN_MCR - 0x0 - 0x20 - read-write - 0x00000000 - - - DBF - DBF - 16 - 1 - - - RESET - RESET - 15 - 1 - - - TTCM - TTCM - 7 - 1 - - - ABOM - ABOM - 6 - 1 - - - AWUM - AWUM - 5 - 1 - - - NART - NART - 4 - 1 - - - RFLM - RFLM - 3 - 1 - - - TXFP - TXFP - 2 - 1 - - - SLEEP - SLEEP - 1 - 1 - - - INRQ - INRQ - 0 - 1 - - - - - CAN_MSR - CAN_MSR - CAN_MSR - 0x4 - 0x20 - 0x00000000 - - - RX - RX - 11 - 1 - read-only - - - SAMP - SAMP - 10 - 1 - read-only - - - RXM - RXM - 9 - 1 - read-only - - - TXM - TXM - 8 - 1 - read-only - - - SLAKI - SLAKI - 4 - 1 - read-write - - - WKUI - WKUI - 3 - 1 - read-write - - - ERRI - ERRI - 2 - 1 - read-write - - - SLAK - SLAK - 1 - 1 - read-only - - - INAK - INAK - 0 - 1 - read-only - - - - - CAN_TSR - CAN_TSR - CAN_TSR - 0x8 - 0x20 - 0x00000000 - - - LOW2 - Lowest priority flag for mailbox - 2 - 31 - 1 - read-only - - - LOW1 - Lowest priority flag for mailbox - 1 - 30 - 1 - read-only - - - LOW0 - Lowest priority flag for mailbox - 0 - 29 - 1 - read-only - - - TME2 - Lowest priority flag for mailbox - 2 - 28 - 1 - read-only - - - TME1 - Lowest priority flag for mailbox - 1 - 27 - 1 - read-only - - - TME0 - Lowest priority flag for mailbox - 0 - 26 - 1 - read-only - - - CODE - CODE - 24 - 2 - read-only - - - ABRQ2 - ABRQ2 - 23 - 1 - read-write - - - TERR2 - TERR2 - 19 - 1 - read-write - - - ALST2 - ALST2 - 18 - 1 - read-write - - - TXOK2 - TXOK2 - 17 - 1 - read-write - - - RQCP2 - RQCP2 - 16 - 1 - read-write - - - ABRQ1 - ABRQ1 - 15 - 1 - read-write - - - TERR1 - TERR1 - 11 - 1 - read-write - - - ALST1 - ALST1 - 10 - 1 - read-write - - - TXOK1 - TXOK1 - 9 - 1 - read-write - - - RQCP1 - RQCP1 - 8 - 1 - read-write - - - ABRQ0 - ABRQ0 - 7 - 1 - read-write - - - TERR0 - TERR0 - 3 - 1 - read-write - - - ALST0 - ALST0 - 2 - 1 - read-write - - - TXOK0 - TXOK0 - 1 - 1 - read-write - - - RQCP0 - RQCP0 - 0 - 1 - read-write - - - - - CAN_RF0R - CAN_RF0R - CAN_RF0R - 0xC - 0x20 - 0x00000000 - - - RFOM0 - RFOM0 - 5 - 1 - read-write - - - FOVR0 - FOVR0 - 4 - 1 - read-write - - - FULL0 - FULL0 - 3 - 1 - read-write - - - FMP0 - FMP0 - 0 - 2 - read-only - - - - - CAN_RF1R - CAN_RF1R - CAN_RF1R - 0x10 - 0x20 - 0x00000000 - - - RFOM1 - RFOM1 - 5 - 1 - read-write - - - FOVR1 - FOVR1 - 4 - 1 - read-write - - - FULL1 - FULL1 - 3 - 1 - read-write - - - FMP1 - FMP1 - 0 - 2 - read-only - - - - - CAN_IER - CAN_IER - CAN_IER - 0x14 - 0x20 - read-write - 0x00000000 - - - SLKIE - SLKIE - 17 - 1 - - - WKUIE - WKUIE - 16 - 1 - - - ERRIE - ERRIE - 15 - 1 - - - LECIE - LECIE - 11 - 1 - - - BOFIE - BOFIE - 10 - 1 - - - EPVIE - EPVIE - 9 - 1 - - - EWGIE - EWGIE - 8 - 1 - - - FOVIE1 - FOVIE1 - 6 - 1 - - - FFIE1 - FFIE1 - 5 - 1 - - - FMPIE1 - FMPIE1 - 4 - 1 - - - FOVIE0 - FOVIE0 - 3 - 1 - - - FFIE0 - FFIE0 - 2 - 1 - - - FMPIE0 - FMPIE0 - 1 - 1 - - - TMEIE - TMEIE - 0 - 1 - - - - - CAN_ESR - CAN_ESR - CAN_ESR - 0x18 - 0x20 - 0x00000000 - - - REC - REC - 24 - 8 - read-only - - - TEC - TEC - 16 - 8 - read-only - - - LEC - LEC - 4 - 3 - read-write - - - BOFF - BOFF - 2 - 1 - read-only - - - EPVF - EPVF - 1 - 1 - read-only - - - EWGF - EWGF - 0 - 1 - read-only - - - - - CAN_BTR - CAN_BTR - CAN_BTR - 0x1C - 0x20 - read-write - 0x00000000 - - - SILM - SILM - 31 - 1 - - - LBKM - LBKM - 30 - 1 - - - SJW - SJW - 24 - 2 - - - TS2 - TS2 - 20 - 3 - - - TS1 - TS1 - 16 - 4 - - - BRP - BRP - 0 - 10 - - - - - CAN_TI0R - CAN_TI0R - CAN_TI0R - 0x180 - 0x20 - read-write - 0x00000000 - - - STID - STID - 21 - 11 - - - EXID - EXID - 3 - 18 - - - IDE - IDE - 2 - 1 - - - RTR - RTR - 1 - 1 - - - TXRQ - TXRQ - 0 - 1 - - - - - CAN_TDT0R - CAN_TDT0R - CAN_TDT0R - 0x184 - 0x20 - read-write - 0x00000000 - - - TIME - TIME - 16 - 16 - - - TGT - TGT - 8 - 1 - - - DLC - DLC - 0 - 4 - - - - - CAN_TDL0R - CAN_TDL0R - CAN_TDL0R - 0x188 - 0x20 - read-write - 0x00000000 - - - DATA3 - DATA3 - 24 - 8 - - - DATA2 - DATA2 - 16 - 8 - - - DATA1 - DATA1 - 8 - 8 - - - DATA0 - DATA0 - 0 - 8 - - - - - CAN_TDH0R - CAN_TDH0R - CAN_TDH0R - 0x18C - 0x20 - read-write - 0x00000000 - - - DATA7 - DATA7 - 24 - 8 - - - DATA6 - DATA6 - 16 - 8 - - - DATA5 - DATA5 - 8 - 8 - - - DATA4 - DATA4 - 0 - 8 - - - - - CAN_TI1R - CAN_TI1R - CAN_TI1R - 0x190 - 0x20 - read-write - 0x00000000 - - - STID - STID - 21 - 11 - - - EXID - EXID - 3 - 18 - - - IDE - IDE - 2 - 1 - - - RTR - RTR - 1 - 1 - - - TXRQ - TXRQ - 0 - 1 - - - - - CAN_TDT1R - CAN_TDT1R - CAN_TDT1R - 0x194 - 0x20 - read-write - 0x00000000 - - - TIME - TIME - 16 - 16 - - - TGT - TGT - 8 - 1 - - - DLC - DLC - 0 - 4 - - - - - CAN_TDL1R - CAN_TDL1R - CAN_TDL1R - 0x198 - 0x20 - read-write - 0x00000000 - - - DATA3 - DATA3 - 24 - 8 - - - DATA2 - DATA2 - 16 - 8 - - - DATA1 - DATA1 - 8 - 8 - - - DATA0 - DATA0 - 0 - 8 - - - - - CAN_TDH1R - CAN_TDH1R - CAN_TDH1R - 0x19C - 0x20 - read-write - 0x00000000 - - - DATA7 - DATA7 - 24 - 8 - - - DATA6 - DATA6 - 16 - 8 - - - DATA5 - DATA5 - 8 - 8 - - - DATA4 - DATA4 - 0 - 8 - - - - - CAN_TI2R - CAN_TI2R - CAN_TI2R - 0x1A0 - 0x20 - read-write - 0x00000000 - - - STID - STID - 21 - 11 - - - EXID - EXID - 3 - 18 - - - IDE - IDE - 2 - 1 - - - RTR - RTR - 1 - 1 - - - TXRQ - TXRQ - 0 - 1 - - - - - CAN_TDT2R - CAN_TDT2R - CAN_TDT2R - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TIME - TIME - 16 - 16 - - - TGT - TGT - 8 - 1 - - - DLC - DLC - 0 - 4 - - - - - CAN_TDL2R - CAN_TDL2R - CAN_TDL2R - 0x1A8 - 0x20 - read-write - 0x00000000 - - - DATA3 - DATA3 - 24 - 8 - - - DATA2 - DATA2 - 16 - 8 - - - DATA1 - DATA1 - 8 - 8 - - - DATA0 - DATA0 - 0 - 8 - - - - - CAN_TDH2R - CAN_TDH2R - CAN_TDH2R - 0x1AC - 0x20 - read-write - 0x00000000 - - - DATA7 - DATA7 - 24 - 8 - - - DATA6 - DATA6 - 16 - 8 - - - DATA5 - DATA5 - 8 - 8 - - - DATA4 - DATA4 - 0 - 8 - - - - - CAN_RI0R - CAN_RI0R - CAN_RI0R - 0x1B0 - 0x20 - read-only - 0x00000000 - - - STID - STID - 21 - 11 - - - EXID - EXID - 3 - 18 - - - IDE - IDE - 2 - 1 - - - RTR - RTR - 1 - 1 - - - - - CAN_RDT0R - CAN_RDT0R - CAN_RDT0R - 0x1B4 - 0x20 - read-only - 0x00000000 - - - TIME - TIME - 16 - 16 - - - FMI - FMI - 8 - 8 - - - DLC - DLC - 0 - 4 - - - - - CAN_RDL0R - CAN_RDL0R - CAN_RDL0R - 0x1B8 - 0x20 - read-only - 0x00000000 - - - DATA3 - DATA3 - 24 - 8 - - - DATA2 - DATA2 - 16 - 8 - - - DATA1 - DATA1 - 8 - 8 - - - DATA0 - DATA0 - 0 - 8 - - - - - CAN_RDH0R - CAN_RDH0R - CAN_RDH0R - 0x1BC - 0x20 - read-only - 0x00000000 - - - DATA7 - DATA7 - 24 - 8 - - - DATA6 - DATA6 - 16 - 8 - - - DATA5 - DATA5 - 8 - 8 - - - DATA4 - DATA4 - 0 - 8 - - - - - CAN_RI1R - CAN_RI1R - CAN_RI1R - 0x1C0 - 0x20 - read-only - 0x00000000 - - - STID - STID - 21 - 11 - - - EXID - EXID - 3 - 18 - - - IDE - IDE - 2 - 1 - - - RTR - RTR - 1 - 1 - - - - - CAN_RDT1R - CAN_RDT1R - CAN_RDT1R - 0x1C4 - 0x20 - read-only - 0x00000000 - - - TIME - TIME - 16 - 16 - - - FMI - FMI - 8 - 8 - - - DLC - DLC - 0 - 4 - - - - - CAN_RDL1R - CAN_RDL1R - CAN_RDL1R - 0x1C8 - 0x20 - read-only - 0x00000000 - - - DATA3 - DATA3 - 24 - 8 - - - DATA2 - DATA2 - 16 - 8 - - - DATA1 - DATA1 - 8 - 8 - - - DATA0 - DATA0 - 0 - 8 - - - - - CAN_RDH1R - CAN_RDH1R - CAN_RDH1R - 0x1CC - 0x20 - read-only - 0x00000000 - - - DATA7 - DATA7 - 24 - 8 - - - DATA6 - DATA6 - 16 - 8 - - - DATA5 - DATA5 - 8 - 8 - - - DATA4 - DATA4 - 0 - 8 - - - - - CAN_FMR - CAN_FMR - CAN_FMR - 0x200 - 0x20 - read-write - 0x00000000 - - - FINIT - FINIT - 0 - 1 - - - - - CAN_FM1R - CAN_FM1R - CAN_FM1R - 0x204 - 0x20 - read-write - 0x00000000 - - - FBM0 - Filter mode - 0 - 1 - - - FBM1 - Filter mode - 1 - 1 - - - FBM2 - Filter mode - 2 - 1 - - - FBM3 - Filter mode - 3 - 1 - - - FBM4 - Filter mode - 4 - 1 - - - FBM5 - Filter mode - 5 - 1 - - - FBM6 - Filter mode - 6 - 1 - - - FBM7 - Filter mode - 7 - 1 - - - FBM8 - Filter mode - 8 - 1 - - - FBM9 - Filter mode - 9 - 1 - - - FBM10 - Filter mode - 10 - 1 - - - FBM11 - Filter mode - 11 - 1 - - - FBM12 - Filter mode - 12 - 1 - - - FBM13 - Filter mode - 13 - 1 - - - - - CAN_FS1R - CAN_FS1R - CAN_FS1R - 0x20C - 0x20 - read-write - 0x00000000 - - - FSC0 - Filter scale configuration - 0 - 1 - - - FSC1 - Filter scale configuration - 1 - 1 - - - FSC2 - Filter scale configuration - 2 - 1 - - - FSC3 - Filter scale configuration - 3 - 1 - - - FSC4 - Filter scale configuration - 4 - 1 - - - FSC5 - Filter scale configuration - 5 - 1 - - - FSC6 - Filter scale configuration - 6 - 1 - - - FSC7 - Filter scale configuration - 7 - 1 - - - FSC8 - Filter scale configuration - 8 - 1 - - - FSC9 - Filter scale configuration - 9 - 1 - - - FSC10 - Filter scale configuration - 10 - 1 - - - FSC11 - Filter scale configuration - 11 - 1 - - - FSC12 - Filter scale configuration - 12 - 1 - - - FSC13 - Filter scale configuration - 13 - 1 - - - - - CAN_FFA1R - CAN_FFA1R - CAN_FFA1R - 0x214 - 0x20 - read-write - 0x00000000 - - - FFA0 - Filter FIFO assignment for filter - 0 - 0 - 1 - - - FFA1 - Filter FIFO assignment for filter - 1 - 1 - 1 - - - FFA2 - Filter FIFO assignment for filter - 2 - 2 - 1 - - - FFA3 - Filter FIFO assignment for filter - 3 - 3 - 1 - - - FFA4 - Filter FIFO assignment for filter - 4 - 4 - 1 - - - FFA5 - Filter FIFO assignment for filter - 5 - 5 - 1 - - - FFA6 - Filter FIFO assignment for filter - 6 - 6 - 1 - - - FFA7 - Filter FIFO assignment for filter - 7 - 7 - 1 - - - FFA8 - Filter FIFO assignment for filter - 8 - 8 - 1 - - - FFA9 - Filter FIFO assignment for filter - 9 - 9 - 1 - - - FFA10 - Filter FIFO assignment for filter - 10 - 10 - 1 - - - FFA11 - Filter FIFO assignment for filter - 11 - 11 - 1 - - - FFA12 - Filter FIFO assignment for filter - 12 - 12 - 1 - - - FFA13 - Filter FIFO assignment for filter - 13 - 13 - 1 - - - - - CAN_FA1R - CAN_FA1R - CAN_FA1R - 0x21C - 0x20 - read-write - 0x00000000 - - - FACT0 - Filter active - 0 - 1 - - - FACT1 - Filter active - 1 - 1 - - - FACT2 - Filter active - 2 - 1 - - - FACT3 - Filter active - 3 - 1 - - - FACT4 - Filter active - 4 - 1 - - - FACT5 - Filter active - 5 - 1 - - - FACT6 - Filter active - 6 - 1 - - - FACT7 - Filter active - 7 - 1 - - - FACT8 - Filter active - 8 - 1 - - - FACT9 - Filter active - 9 - 1 - - - FACT10 - Filter active - 10 - 1 - - - FACT11 - Filter active - 11 - 1 - - - FACT12 - Filter active - 12 - 1 - - - FACT13 - Filter active - 13 - 1 - - - - - F0R1 - F0R1 - Filter bank 0 register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F0R2 - F0R2 - Filter bank 0 register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F1R1 - F1R1 - Filter bank 1 register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F1R2 - F1R2 - Filter bank 1 register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F2R1 - F2R1 - Filter bank 2 register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F2R2 - F2R2 - Filter bank 2 register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F3R1 - F3R1 - Filter bank 3 register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F3R2 - F3R2 - Filter bank 3 register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F4R1 - F4R1 - Filter bank 4 register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F4R2 - F4R2 - Filter bank 4 register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F5R1 - F5R1 - Filter bank 5 register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F5R2 - F5R2 - Filter bank 5 register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F6R1 - F6R1 - Filter bank 6 register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F6R2 - F6R2 - Filter bank 6 register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - - F7R1 - F7R1 - Filter bank 7 register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F7R2 - F7R2 - Filter bank 7 register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F8R1 - F8R1 - Filter bank 8 register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F8R2 - F8R2 - Filter bank 8 register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F9R1 - F9R1 - Filter bank 9 register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F9R2 - F9R2 - Filter bank 9 register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F10R1 - F10R1 - Filter bank 10 register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F10R2 - F10R2 - Filter bank 10 register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F11R1 - F11R1 - Filter bank 11 register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F11R2 - F11R2 - Filter bank 11 register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F12R1 - F12R1 - Filter bank 4 register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F12R2 - F12R2 - Filter bank 12 register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F13R1 - F13R1 - Filter bank 13 register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - F13R2 - F13R2 - Filter bank 13 register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FB0 - Filter bits - 0 - 1 - - - FB1 - Filter bits - 1 - 1 - - - FB2 - Filter bits - 2 - 1 - - - FB3 - Filter bits - 3 - 1 - - - FB4 - Filter bits - 4 - 1 - - - FB5 - Filter bits - 5 - 1 - - - FB6 - Filter bits - 6 - 1 - - - FB7 - Filter bits - 7 - 1 - - - FB8 - Filter bits - 8 - 1 - - - FB9 - Filter bits - 9 - 1 - - - FB10 - Filter bits - 10 - 1 - - - FB11 - Filter bits - 11 - 1 - - - FB12 - Filter bits - 12 - 1 - - - FB13 - Filter bits - 13 - 1 - - - FB14 - Filter bits - 14 - 1 - - - FB15 - Filter bits - 15 - 1 - - - FB16 - Filter bits - 16 - 1 - - - FB17 - Filter bits - 17 - 1 - - - FB18 - Filter bits - 18 - 1 - - - FB19 - Filter bits - 19 - 1 - - - FB20 - Filter bits - 20 - 1 - - - FB21 - Filter bits - 21 - 1 - - - FB22 - Filter bits - 22 - 1 - - - FB23 - Filter bits - 23 - 1 - - - FB24 - Filter bits - 24 - 1 - - - FB25 - Filter bits - 25 - 1 - - - FB26 - Filter bits - 26 - 1 - - - FB27 - Filter bits - 27 - 1 - - - FB28 - Filter bits - 28 - 1 - - - FB29 - Filter bits - 29 - 1 - - - FB30 - Filter bits - 30 - 1 - - - FB31 - Filter bits - 31 - 1 - - - - - - - DAC - Digital to analog converter - DAC - 0x40007400 - - 0x0 - 0x400 - registers - - - - CR - CR - Control register (DAC_CR) - 0x0 - 0x20 - read-write - 0x00000000 - - - EN1 - DAC channel1 enable - 0 - 1 - - - BOFF1 - DAC channel1 output buffer - disable - 1 - 1 - - - TEN1 - DAC channel1 trigger - enable - 2 - 1 - - - TSEL1 - DAC channel1 trigger - selection - 3 - 3 - - - WAVE1 - DAC channel1 noise/triangle wave - generation enable - 6 - 2 - - - MAMP1 - DAC channel1 mask/amplitude - selector - 8 - 4 - - - DMAEN1 - DAC channel1 DMA enable - 12 - 1 - - - EN2 - DAC channel2 enable - 16 - 1 - - - BOFF2 - DAC channel2 output buffer - disable - 17 - 1 - - - TEN2 - DAC channel2 trigger - enable - 18 - 1 - - - TSEL2 - DAC channel2 trigger - selection - 19 - 3 - - - WAVE2 - DAC channel2 noise/triangle wave - generation enable - 22 - 2 - - - MAMP2 - DAC channel2 mask/amplitude - selector - 24 - 4 - - - DMAEN2 - DAC channel2 DMA enable - 28 - 1 - - - - - SWTRIGR - SWTRIGR - DAC software trigger register - (DAC_SWTRIGR) - 0x4 - 0x20 - write-only - 0x00000000 - - - SWTRIG1 - DAC channel1 software - trigger - 0 - 1 - - - SWTRIG2 - DAC channel2 software - trigger - 1 - 1 - - - - - DHR12R1 - DHR12R1 - DAC channel1 12-bit right-aligned data - holding register(DAC_DHR12R1) - 0x8 - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 12-bit right-aligned - data - 0 - 12 - - - - - DHR12L1 - DHR12L1 - DAC channel1 12-bit left aligned data - holding register (DAC_DHR12L1) - 0xC - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 12-bit left-aligned - data - 4 - 12 - - - - - DHR8R1 - DHR8R1 - DAC channel1 8-bit right aligned data - holding register (DAC_DHR8R1) - 0x10 - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 8-bit right-aligned - data - 0 - 8 - - - - - DHR12R2 - DHR12R2 - DAC channel2 12-bit right aligned data - holding register (DAC_DHR12R2) - 0x14 - 0x20 - read-write - 0x00000000 - - - DACC2DHR - DAC channel2 12-bit right-aligned - data - 0 - 12 - - - - - DHR12L2 - DHR12L2 - DAC channel2 12-bit left aligned data - holding register (DAC_DHR12L2) - 0x18 - 0x20 - read-write - 0x00000000 - - - DACC2DHR - DAC channel2 12-bit left-aligned - data - 4 - 12 - - - - - DHR8R2 - DHR8R2 - DAC channel2 8-bit right-aligned data - holding register (DAC_DHR8R2) - 0x1C - 0x20 - read-write - 0x00000000 - - - DACC2DHR - DAC channel2 8-bit right-aligned - data - 0 - 8 - - - - - DHR12RD - DHR12RD - Dual DAC 12-bit right-aligned data holding - register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 - Reserved - 0x20 - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 12-bit right-aligned - data - 0 - 12 - - - DACC2DHR - DAC channel2 12-bit right-aligned - data - 16 - 12 - - - - - DHR12LD - DHR12LD - DUAL DAC 12-bit left aligned data holding - register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 - Reserved - 0x24 - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 12-bit left-aligned - data - 4 - 12 - - - DACC2DHR - DAC channel2 12-bit right-aligned - data - 20 - 12 - - - - - DHR8RD - DHR8RD - DUAL DAC 8-bit right aligned data holding - register (DAC_DHR8RD), Bits 31:16 Reserved - 0x28 - 0x20 - read-write - 0x00000000 - - - DACC1DHR - DAC channel1 8-bit right-aligned - data - 0 - 8 - - - DACC2DHR - DAC channel2 8-bit right-aligned - data - 8 - 8 - - - - - DOR1 - DOR1 - DAC channel1 data output register - (DAC_DOR1) - 0x2C - 0x20 - read-only - 0x00000000 - - - DACC1DOR - DAC channel1 data output - 0 - 12 - - - - - DOR2 - DOR2 - DAC channel2 data output register - (DAC_DOR2) - 0x30 - 0x20 - read-only - 0x00000000 - - - DACC2DOR - DAC channel2 data output - 0 - 12 - - - - - - - DBG - Debug support - DBG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DBGMCU_IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - DEV_ID - DEV_ID - 0 - 12 - - - REV_ID - REV_ID - 16 - 16 - - - - - CR - CR - DBGMCU_CR - 0x4 - 0x20 - read-write - 0x0 - - - DBG_SLEEP - DBG_SLEEP - 0 - 1 - - - DBG_STOP - DBG_STOP - 1 - 1 - - - DBG_STANDBY - DBG_STANDBY - 2 - 1 - - - TRACE_IOEN - TRACE_IOEN - 5 - 1 - - - TRACE_MODE - TRACE_MODE - 6 - 2 - - - DBG_IWDG_STOP - DBG_IWDG_STOP - 8 - 1 - - - DBG_WWDG_STOP - DBG_WWDG_STOP - 9 - 1 - - - DBG_TIM1_STOP - DBG_TIM1_STOP - 10 - 1 - - - DBG_TIM2_STOP - DBG_TIM2_STOP - 11 - 1 - - - DBG_TIM3_STOP - DBG_TIM3_STOP - 12 - 1 - - - DBG_TIM4_STOP - DBG_TIM4_STOP - 13 - 1 - - - DBG_CAN1_STOP - DBG_CAN1_STOP - 14 - 1 - - - DBG_I2C1_SMBUS_TIMEOUT - DBG_I2C1_SMBUS_TIMEOUT - 15 - 1 - - - DBG_I2C2_SMBUS_TIMEOUT - DBG_I2C2_SMBUS_TIMEOUT - 16 - 1 - - - DBG_TIM8_STOP - DBG_TIM8_STOP - 17 - 1 - - - DBG_TIM5_STOP - DBG_TIM5_STOP - 18 - 1 - - - DBG_TIM6_STOP - DBG_TIM6_STOP - 19 - 1 - - - DBG_TIM7_STOP - DBG_TIM7_STOP - 20 - 1 - - - DBG_CAN2_STOP - DBG_CAN2_STOP - 21 - 1 - - - - - - - UART4 - Universal asynchronous receiver - transmitter - USART - 0x40004C00 - - 0x0 - 0x400 - registers - - - UART4 - UART4 global interrupt - 52 - - - - SR - SR - UART4_SR - 0x0 - 0x20 - 0x0 - - - PE - Parity error - 0 - 1 - read-only - - - FE - Framing error - 1 - 1 - read-only - - - NE - Noise error flag - 2 - 1 - read-only - - - ORE - Overrun error - 3 - 1 - read-only - - - IDLE - IDLE line detected - 4 - 1 - read-only - - - RXNE - Read data register not - empty - 5 - 1 - read-write - - - TC - Transmission complete - 6 - 1 - read-write - - - TXE - Transmit data register - empty - 7 - 1 - read-only - - - LBD - LIN break detection flag - 8 - 1 - read-write - - - - - DR - DR - UART4_DR - 0x4 - 0x20 - read-write - 0x0 - - - DR - DR - 0 - 9 - - - - - BRR - BRR - UART4_BRR - 0x8 - 0x20 - read-write - 0x0 - - - DIV_Fraction - DIV_Fraction - 0 - 4 - - - DIV_Mantissa - DIV_Mantissa - 4 - 12 - - - - - CR1 - CR1 - UART4_CR1 - 0xC - 0x20 - read-write - 0x0 - - - SBK - Send break - 0 - 1 - - - RWU - Receiver wakeup - 1 - 1 - - - RE - Receiver enable - 2 - 1 - - - TE - Transmitter enable - 3 - 1 - - - IDLEIE - IDLE interrupt enable - 4 - 1 - - - RXNEIE - RXNE interrupt enable - 5 - 1 - - - TCIE - Transmission complete interrupt - enable - 6 - 1 - - - TXEIE - TXE interrupt enable - 7 - 1 - - - PEIE - PE interrupt enable - 8 - 1 - - - PS - Parity selection - 9 - 1 - - - PCE - Parity control enable - 10 - 1 - - - WAKE - Wakeup method - 11 - 1 - - - M - Word length - 12 - 1 - - - UE - USART enable - 13 - 1 - - - - - CR2 - CR2 - UART4_CR2 - 0x10 - 0x20 - read-write - 0x0 - - - ADD - Address of the USART node - 0 - 4 - - - LBDL - lin break detection length - 5 - 1 - - - LBDIE - LIN break detection interrupt - enable - 6 - 1 - - - STOP - STOP bits - 12 - 2 - - - LINEN - LIN mode enable - 14 - 1 - - - - - CR3 - CR3 - UART4_CR3 - 0x14 - 0x20 - read-write - 0x0 - - - EIE - Error interrupt enable - 0 - 1 - - - IREN - IrDA mode enable - 1 - 1 - - - IRLP - IrDA low-power - 2 - 1 - - - HDSEL - Half-duplex selection - 3 - 1 - - - DMAR - DMA enable receiver - 6 - 1 - - - DMAT - DMA enable transmitter - 7 - 1 - - - - - - - UART5 - Universal asynchronous receiver - transmitter - USART - 0x40005000 - - 0x0 - 0x400 - registers - - - UART5 - UART5 global interrupt - 53 - - - - SR - SR - UART4_SR - 0x0 - 0x20 - 0x0 - - - PE - PE - 0 - 1 - read-only - - - FE - FE - 1 - 1 - read-only - - - NE - NE - 2 - 1 - read-only - - - ORE - ORE - 3 - 1 - read-only - - - IDLE - IDLE - 4 - 1 - read-only - - - RXNE - RXNE - 5 - 1 - read-write - - - TC - TC - 6 - 1 - read-write - - - TXE - TXE - 7 - 1 - read-only - - - LBD - LBD - 8 - 1 - read-write - - - - - DR - DR - UART4_DR - 0x4 - 0x20 - read-write - 0x0 - - - DR - DR - 0 - 9 - - - - - BRR - BRR - UART4_BRR - 0x8 - 0x20 - read-write - 0x0 - - - DIV_Fraction - DIV_Fraction - 0 - 4 - - - DIV_Mantissa - DIV_Mantissa - 4 - 12 - - - - - CR1 - CR1 - UART4_CR1 - 0xC - 0x20 - read-write - 0x0 - - - SBK - SBK - 0 - 1 - - - RWU - RWU - 1 - 1 - - - RE - RE - 2 - 1 - - - TE - TE - 3 - 1 - - - IDLEIE - IDLEIE - 4 - 1 - - - RXNEIE - RXNEIE - 5 - 1 - - - TCIE - TCIE - 6 - 1 - - - TXEIE - TXEIE - 7 - 1 - - - PEIE - PEIE - 8 - 1 - - - PS - PS - 9 - 1 - - - PCE - PCE - 10 - 1 - - - WAKE - WAKE - 11 - 1 - - - M - M - 12 - 1 - - - UE - UE - 13 - 1 - - - - - CR2 - CR2 - UART4_CR2 - 0x10 - 0x20 - read-write - 0x0 - - - ADD - ADD - 0 - 4 - - - LBDL - LBDL - 5 - 1 - - - LBDIE - LBDIE - 6 - 1 - - - STOP - STOP - 12 - 2 - - - LINEN - LINEN - 14 - 1 - - - - - CR3 - CR3 - UART4_CR3 - 0x14 - 0x20 - read-write - 0x0 - - - EIE - Error interrupt enable - 0 - 1 - - - IREN - IrDA mode enable - 1 - 1 - - - IRLP - IrDA low-power - 2 - 1 - - - HDSEL - Half-duplex selection - 3 - 1 - - - DMAT - DMA enable transmitter - 7 - 1 - - - - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DR - DR - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DR - Data Register - 0 - 32 - - - - - IDR - IDR - Independent Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - IDR - Independent Data register - 0 - 8 - - - - - CR - CR - Control register - 0x8 - 0x20 - write-only - 0x00000000 - - - RESET - Reset bit - 0 - 1 - - - - - - - FLASH - FLASH - FLASH - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - ACR - ACR - Flash access control register - 0x0 - 0x20 - 0x00000030 - - - LATENCY - Latency - 0 - 3 - read-write - - - HLFCYA - Flash half cycle access - enable - 3 - 1 - read-write - - - PRFTBE - Prefetch buffer enable - 4 - 1 - read-write - - - PRFTBS - Prefetch buffer status - 5 - 1 - read-only - - - - - KEYR - KEYR - Flash key register - 0x4 - 0x20 - write-only - 0x00000000 - - - KEY - FPEC key - 0 - 32 - - - - - OPTKEYR - OPTKEYR - Flash option key register - 0x8 - 0x20 - write-only - 0x00000000 - - - OPTKEY - Option byte key - 0 - 32 - - - - - SR - SR - Status register - 0xC - 0x20 - 0x00000000 - - - EOP - End of operation - 5 - 1 - read-write - - - WRPRTERR - Write protection error - 4 - 1 - read-write - - - PGERR - Programming error - 2 - 1 - read-write - - - BSY - Busy - 0 - 1 - read-only - - - - - CR - CR - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - PG - Programming - 0 - 1 - - - PER - Page Erase - 1 - 1 - - - MER - Mass Erase - 2 - 1 - - - OPTPG - Option byte programming - 4 - 1 - - - OPTER - Option byte erase - 5 - 1 - - - STRT - Start - 6 - 1 - - - LOCK - Lock - 7 - 1 - - - OPTWRE - Option bytes write enable - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - EOPIE - End of operation interrupt - enable - 12 - 1 - - - - - AR - AR - Flash address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FAR - Flash Address - 0 - 32 - - - - - OBR - OBR - Option byte register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - OPTERR - Option byte error - 0 - 1 - - - RDPRT - Read protection - 1 - 1 - - - WDG_SW - WDG_SW - 2 - 1 - - - nRST_STOP - nRST_STOP - 3 - 1 - - - nRST_STDBY - nRST_STDBY - 4 - 1 - - - Data0 - Data0 - 10 - 8 - - - Data1 - Data1 - 18 - 8 - - - - - WRPR - WRPR - Write protection register - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - WRP - Write protect - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - USB - Universal serial bus full-speed device - interface - USB - 0x40005C00 - - 0x0 - 0x400 - registers - - - USB_FS_WKUP - USB Device FS Wakeup through EXTI line - interrupt - 42 - - - - EP0R - EP0R - endpoint 0 register - 0x0 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP1R - EP1R - endpoint 1 register - 0x4 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP2R - EP2R - endpoint 2 register - 0x8 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP3R - EP3R - endpoint 3 register - 0xC - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP4R - EP4R - endpoint 4 register - 0x10 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP5R - EP5R - endpoint 5 register - 0x14 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP6R - EP6R - endpoint 6 register - 0x18 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP7R - EP7R - endpoint 7 register - 0x1C - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - CNTR - USB_CNTR - control register - 0x40 - 0x20 - read-write - 0x00000003 - - - FRES - Force USB Reset - 0 - 1 - - - PDWN - Power down - 1 - 1 - - - LPMODE - Low-power mode - 2 - 1 - - - FSUSP - Force suspend - 3 - 1 - - - RESUME - Resume request - 4 - 1 - - - ESOFM - Expected start of frame interrupt - mask - 8 - 1 - - - SOFM - Start of frame interrupt - mask - 9 - 1 - - - RESETM - USB reset interrupt mask - 10 - 1 - - - SUSPM - Suspend mode interrupt - mask - 11 - 1 - - - WKUPM - Wakeup interrupt mask - 12 - 1 - - - ERRM - Error interrupt mask - 13 - 1 - - - PMAOVRM - Packet memory area over / underrun - interrupt mask - 14 - 1 - - - CTRM - Correct transfer interrupt - mask - 15 - 1 - - - - - ISTR - ISTR - interrupt status register - 0x44 - 0x20 - read-write - 0x00000000 - - - EP_ID - Endpoint Identifier - 0 - 4 - - - DIR - Direction of transaction - 4 - 1 - - - ESOF - Expected start frame - 8 - 1 - - - SOF - start of frame - 9 - 1 - - - RESET - reset request - 10 - 1 - - - SUSP - Suspend mode request - 11 - 1 - - - WKUP - Wakeup - 12 - 1 - - - ERR - Error - 13 - 1 - - - PMAOVR - Packet memory area over / - underrun - 14 - 1 - - - CTR - Correct transfer - 15 - 1 - - - - - FNR - FNR - frame number register - 0x48 - 0x20 - read-only - 0x0000 - - - FN - Frame number - 0 - 11 - - - LSOF - Lost SOF - 11 - 2 - - - LCK - Locked - 13 - 1 - - - RXDM - Receive data - line status - 14 - 1 - - - RXDP - Receive data + line status - 15 - 1 - - - - - DADDR - DADDR - device address - 0x4C - 0x20 - read-write - 0x0000 - - - ADD - Device address - 0 - 7 - - - EF - Enable function - 7 - 1 - - - - - BTABLE - BTABLE - Buffer table address - 0x50 - 0x20 - read-write - 0x0000 - - - BTABLE - Buffer table - 3 - 13 - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/ide/olimexino.depend b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/ide/olimexino.depend deleted file mode 100644 index e9781673..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/ide/olimexino.depend +++ /dev/null @@ -1,564 +0,0 @@ -# depslib dependency file v1.0 -1477585707 source:c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\led.c - "boot.h" - "led.h" - "stm32f10x.h" - -1477219754 c:\work\software\openblt\target\source\boot.h - "types.h" - "assert.h" - "blt_conf.h" - "plausibility.h" - "cpu.h" - "cop.h" - "nvm.h" - "timer.h" - "backdoor.h" - "file.h" - "com.h" - -1477303562 c:\work\software\openblt\target\source\armcm3_stm32f1\types.h - -1469435361 c:\work\software\openblt\target\source\assert.h - -1477601331 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\blt_conf.h - -1469435361 c:\work\software\openblt\target\source\plausibility.h - -1476731768 c:\work\software\openblt\target\source\cpu.h - -1469435361 c:\work\software\openblt\target\source\cop.h - -1469435361 c:\work\software\openblt\target\source\nvm.h - -1469435361 c:\work\software\openblt\target\source\timer.h - -1469435361 c:\work\software\openblt\target\source\backdoor.h - -1469435361 c:\work\software\openblt\target\source\file.h - "ff.h" - -1469435361 c:\work\software\openblt\target\source\com.h - "xcp.h" - -1476787065 c:\work\software\openblt\target\source\xcp.h - -1477585605 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\led.h - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\stm32f10x.h - "core_cm3.h" - "system_stm32f10x.h" - - "stm32f10x_conf.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\cmsis\core_cm3.h - - - - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\cmsis\core_cminstr.h - - - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\cmsis\core_cmfunc.h - - - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\system_stm32f10x.h - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\stm32f10x_conf.h - "stm32f10x_adc.h" - "stm32f10x_bkp.h" - "stm32f10x_can.h" - "stm32f10x_cec.h" - "stm32f10x_crc.h" - "stm32f10x_dac.h" - "stm32f10x_dbgmcu.h" - "stm32f10x_dma.h" - "stm32f10x_exti.h" - "stm32f10x_flash.h" - "stm32f10x_fsmc.h" - "stm32f10x_gpio.h" - "stm32f10x_i2c.h" - "stm32f10x_iwdg.h" - "stm32f10x_pwr.h" - "stm32f10x_rcc.h" - "stm32f10x_rtc.h" - "stm32f10x_sdio.h" - "stm32f10x_spi.h" - "stm32f10x_tim.h" - "stm32f10x_usart.h" - "stm32f10x_wwdg.h" - "misc.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_adc.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_bkp.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_can.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_cec.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_crc.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_dac.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_dbgmcu.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_dma.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_exti.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_flash.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_fsmc.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_gpio.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_i2c.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_iwdg.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_pwr.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_rcc.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_rtc.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_sdio.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_spi.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_tim.h - "stm32f10x.h" - -1477584793 c:\work\software\openblt\target\demo\armcm3_stm32f1_olimexino_stm32_gcc\boot\lib\spl\inc\stm32f10x_usart.h - "stm32f10x.h" - -1477584793 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a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/ide/olimexino.ebp b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/ide/olimexino.ebp deleted file mode 100644 index b5b40749..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/ide/olimexino.ebp +++ /dev/null @@ -1,291 +0,0 @@ - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/ide/olimexino.elay b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/ide/olimexino.elay deleted file mode 100644 index b3fa8894..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/ide/olimexino.elay +++ /dev/null @@ -1,34 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/lib/newlib/_exit.c b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/lib/newlib/_exit.c new file mode 100644 index 00000000..4ae9532c --- /dev/null +++ b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/lib/newlib/_exit.c @@ -0,0 +1,38 @@ +// ---------------------------------------------------------------------------- + +#include + +// ---------------------------------------------------------------------------- + +// Forward declaration + +void +_exit(int code); + +// ---------------------------------------------------------------------------- + +// We just enter an infinite loop, to be used as landmark when halting +// the debugger. +// +// It can be redefined in the application, if more functionality +// is required. + +void +__attribute__((weak)) +_exit(int code __attribute__((unused))) +{ + // TODO: write on trace + while (1) + ; +} + +// ---------------------------------------------------------------------------- + +void +__attribute__((weak,noreturn)) +abort(void) +{ + _exit(1); +} + +// ---------------------------------------------------------------------------- diff --git a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/makefile b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/makefile new file mode 100644 index 00000000..1ade3732 --- /dev/null +++ b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/makefile @@ -0,0 +1,164 @@ +#**************************************************************************************** +#| Description: Makefile for GNU ARM Embedded toolchain. +#| File Name: makefile +#| +#|--------------------------------------------------------------------------------------- +#| C O P Y R I G H T +#|--------------------------------------------------------------------------------------- +#| Copyright (c) 2017 by Feaser http://www.feaser.com All rights reserved +#| +#|--------------------------------------------------------------------------------------- +#| L I C E N S E +#|--------------------------------------------------------------------------------------- +#| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +#| modify it under the terms of the GNU General Public License as published by the Free +#| Software Foundation, either version 3 of the License, or (at your option) any later +#| version. +#| +#| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +#| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +#| PURPOSE. See the GNU General Public License for more details. +#| +#| You have received a copy of the GNU General Public License along with OpenBLT. It +#| should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +#| +#**************************************************************************************** +SHELL = sh + +#|--------------------------------------------------------------------------------------| +#| Configure project name | +#|--------------------------------------------------------------------------------------| +PROJ_NAME=demoprog_olimexino_stm32 + + +#|--------------------------------------------------------------------------------------| +#| Configure tool path | +#|--------------------------------------------------------------------------------------| +TOOL_PATH=/opt/gcc-arm-none-eabi-5_4-2016q3/bin/ + + +#|--------------------------------------------------------------------------------------| +#| Collect project files | +#|--------------------------------------------------------------------------------------| +# Recursive wildcard function implementation. Example usages: +# $(call rwildcard, , *.c *.h) +# --> Returns all *.c and *.h files in the current directory and below +# $(call rwildcard, /lib/, *.c) +# --> Returns all *.c files in the /lib directory and below +rwildcard = $(strip $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d))) + +# Collect all application files in the current directory and its subdirectories +PROJ_FILES = $(call rwildcard, , *.c *.h *.S) + + +#|--------------------------------------------------------------------------------------| +#| Toolchain binaries | +#|--------------------------------------------------------------------------------------| +RM = rm +CC = $(TOOL_PATH)arm-none-eabi-gcc +LN = $(TOOL_PATH)arm-none-eabi-gcc +OC = $(TOOL_PATH)arm-none-eabi-objcopy +OD = $(TOOL_PATH)arm-none-eabi-objdump +AS = $(TOOL_PATH)arm-none-eabi-gcc +SZ = $(TOOL_PATH)arm-none-eabi-size + + +#|--------------------------------------------------------------------------------------| +#| Filter project files +#|--------------------------------------------------------------------------------------| +PROJ_ASRCS = $(filter %.S,$(foreach file,$(PROJ_FILES),$(notdir $(file)))) +PROJ_CSRCS = $(filter %.c,$(foreach file,$(PROJ_FILES),$(notdir $(file)))) +PROJ_CHDRS = $(filter %.h,$(foreach file,$(PROJ_FILES),$(notdir $(file)))) + + +#|--------------------------------------------------------------------------------------| +#| Set important path variables | +#|--------------------------------------------------------------------------------------| +VPATH = $(foreach path,$(sort $(foreach file,$(PROJ_FILES),$(dir $(file)))) $(subst \,/,$(OBJ_PATH)),$(path) :) +OBJ_PATH = obj +BIN_PATH = bin +INC_PATH = $(patsubst %/,%,$(patsubst %,-I%,$(sort $(foreach file,$(filter %.h,$(PROJ_FILES)),$(dir $(file)))))) +LIB_PATH = + + +#|--------------------------------------------------------------------------------------| +#| Options for toolchain binaries | +#|--------------------------------------------------------------------------------------| +HEAP_SIZE = 0x0800 +STACK_SIZE = 0x0800 +STDFLAGS = -mcpu=cortex-m3 -mthumb -fno-strict-aliasing +STDFLAGS += -fdata-sections -ffunction-sections -Wall -g3 +OPTFLAGS = -Og +CFLAGS = $(STDFLAGS) $(OPTFLAGS) +CFLAGS += -DSTM32F10X_MD -DUSE_STDPERIPH_DRIVER -DVECT_TAB_FLASH -DGCC_ARMCM3 +CFLAGS += -D__HEAP_SIZE=$(HEAP_SIZE) -D__STACK_SIZE=$(STACK_SIZE) +CFLAGS += $(INC_PATH) +AFLAGS = $(CFLAGS) +LFLAGS = $(STDFLAGS) $(OPTFLAGS) +LFLAGS += -Wl,--defsym=__HEAP_SIZE=$(HEAP_SIZE) -Wl,--defsym=__STACK_SIZE=$(STACK_SIZE) +LFLAGS += -Wl,-script="stm32f103rb_flash.ld" -Wl,-Map=$(BIN_PATH)/$(PROJ_NAME).map +LFLAGS += -specs=nano.specs -Wl,--gc-sections $(LIB_PATH) +OFLAGS = -O srec +ODFLAGS = -x +SZFLAGS = -B -d +RMFLAGS = -f + + +#|--------------------------------------------------------------------------------------| +#| Specify library files | +#|--------------------------------------------------------------------------------------| +LIBS = + + +#|--------------------------------------------------------------------------------------| +#| Define targets | +#|--------------------------------------------------------------------------------------| +AOBJS = $(patsubst %.S,%.o,$(PROJ_ASRCS)) +COBJS = $(patsubst %.c,%.o,$(PROJ_CSRCS)) + + +#|--------------------------------------------------------------------------------------| +#| Make ALL | +#|--------------------------------------------------------------------------------------| +.PHONY: all +all: $(BIN_PATH)/$(PROJ_NAME).srec + + +$(BIN_PATH)/$(PROJ_NAME).srec : $(BIN_PATH)/$(PROJ_NAME).elf + @$(OC) $< $(OFLAGS) $@ + @$(OD) $(ODFLAGS) $< > $(BIN_PATH)/$(PROJ_NAME).map + @echo +++ Summary of memory consumption: + @$(SZ) $(SZFLAGS) $< + @echo +++ Build complete [$(notdir $@)] + +$(BIN_PATH)/$(PROJ_NAME).elf : $(AOBJS) $(COBJS) + @echo +++ Linking [$(notdir $@)] + @$(LN) $(LFLAGS) -o $@ $(patsubst %.o,$(OBJ_PATH)/%.o,$(^F)) $(LIBS) + + +#|--------------------------------------------------------------------------------------| +#| Compile and assemble | +#|--------------------------------------------------------------------------------------| +$(AOBJS): %.o: %.S $(PROJ_CHDRS) + @echo +++ Assembling [$(notdir $<)] + @$(AS) $(AFLAGS) -c $< -o $(OBJ_PATH)/$(@F) + +$(COBJS): %.o: %.c $(PROJ_CHDRS) + @echo +++ Compiling [$(notdir $<)] + @$(CC) $(CFLAGS) -c $< -o $(OBJ_PATH)/$(@F) + + +#|--------------------------------------------------------------------------------------| +#| Make CLEAN | +#|--------------------------------------------------------------------------------------| +.PHONY: clean +clean: + @echo +++ Cleaning build environment + @$(RM) $(RMFLAGS) $(foreach file,$(AOBJS),$(OBJ_PATH)/$(file)) + @$(RM) $(RMFLAGS) $(foreach file,$(COBJS),$(OBJ_PATH)/$(file)) + @$(RM) $(RMFLAGS) $(patsubst %.o,%.lst,$(foreach file,$(COBJS),$(OBJ_PATH)/$(file))) + @$(RM) $(RMFLAGS) $(BIN_PATH)/$(PROJ_NAME).elf $(BIN_PATH)/$(PROJ_NAME).map + @$(RM) $(RMFLAGS) $(BIN_PATH)/$(PROJ_NAME).srec + @echo +++ Clean complete + + diff --git a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/cfg/stm32f103rb_flash.ld b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/stm32f103rb_flash.ld similarity index 100% rename from Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/cfg/stm32f103rb_flash.ld rename to Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Prog/stm32f103rb_flash.ld

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diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/bin/demoprog_olimex_stm32p103.map b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/bin/demoprog_olimex_stm32p103.map index 21d570c4..b7e077d9 100644 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/bin/demoprog_olimex_stm32p103.map +++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/bin/demoprog_olimex_stm32p103.map @@ -1,219 +1,245 @@ - -bin/demoprog_olimex_stm32p103.elf: file format elf32-littlearm -bin/demoprog_olimex_stm32p103.elf -architecture: arm, flags 0x00000112: -EXEC_P, HAS_SYMS, D_PAGED -start address 0x08006000 - -Program Header: - LOAD off 0x00000000 vaddr 0x08000000 paddr 0x08000000 align 2**15 - filesz 0x00006f00 memsz 0x00006f00 flags r-x - LOAD off 0x00008000 vaddr 0x20000000 paddr 0x08006f00 align 2**15 - filesz 0x0000001c memsz 0x00000090 flags rw- -private flags = 5000202: [Version5 EABI] [soft-float ABI] [has entry point] - -Sections: -Idx Name Size VMA LMA File off Algn - 0 .text 00000f00 08006000 08006000 00006000 2**2 - CONTENTS, ALLOC, LOAD, READONLY, CODE - 1 .data 0000001c 20000000 08006f00 00008000 2**2 - CONTENTS, ALLOC, LOAD, DATA - 2 .bss 00000074 2000001c 08006f1c 0000801c 2**2 - ALLOC - 3 .heap 00000800 20000090 20000090 00008020 2**3 - CONTENTS, READONLY - 4 .stack_dummy 00000800 20000090 20000090 00008820 2**3 - CONTENTS, READONLY - 5 .ARM.attributes 00000027 00000000 00000000 00009020 2**0 - CONTENTS, READONLY - 6 .comment 00000030 00000000 00000000 00009047 2**0 - CONTENTS, READONLY - 7 .debug_line 00003493 00000000 00000000 00009077 2**0 - CONTENTS, READONLY, DEBUGGING - 8 .debug_info 000043f9 00000000 00000000 0000c50a 2**0 - CONTENTS, READONLY, DEBUGGING - 9 .debug_abbrev 00000f38 00000000 00000000 00010903 2**0 - CONTENTS, READONLY, DEBUGGING - 10 .debug_aranges 000004b0 00000000 00000000 00011840 2**3 - CONTENTS, READONLY, DEBUGGING - 11 .debug_loc 00001dc0 00000000 00000000 00011cf0 2**0 - CONTENTS, READONLY, DEBUGGING - 12 .debug_ranges 00000410 00000000 00000000 00013ab0 2**0 - CONTENTS, READONLY, DEBUGGING - 13 .debug_macro 0000dc0c 00000000 00000000 00013ec0 2**0 - CONTENTS, READONLY, DEBUGGING - 14 .debug_str 0004f0bb 00000000 00000000 00021acc 2**0 - CONTENTS, READONLY, DEBUGGING - 15 .debug_frame 00000950 00000000 00000000 00070b88 2**2 - CONTENTS, READONLY, DEBUGGING -SYMBOL TABLE: -08006000 l d .text 00000000 .text -20000000 l d .data 00000000 .data -2000001c l d .bss 00000000 .bss -20000090 l d .heap 00000000 .heap -20000090 l d .stack_dummy 00000000 .stack_dummy -00000000 l d .ARM.attributes 00000000 .ARM.attributes -00000000 l d .comment 00000000 .comment -00000000 l d .debug_line 00000000 .debug_line -00000000 l d .debug_info 00000000 .debug_info -00000000 l d .debug_abbrev 00000000 .debug_abbrev -00000000 l d .debug_aranges 00000000 .debug_aranges -00000000 l d .debug_loc 00000000 .debug_loc -00000000 l d .debug_ranges 00000000 .debug_ranges -00000000 l d .debug_macro 00000000 .debug_macro -00000000 l d .debug_str 00000000 .debug_str -00000000 l d .debug_frame 00000000 .debug_frame -00000000 l df *ABS* 00000000 obj/startup_stm32f10x_md.o -00000800 l *ABS* 00000000 Stack_Size -00000800 l *ABS* 00000000 Heap_Size -080061c2 l .text 00000000 .flash_to_ram_loop -080061f4 l .text 00000000 .fill_zero_bss -080061f0 l .text 00000000 .loop_zero_bss -00000000 l df *ABS* 00000000 crtstuff.c -08006efc l O .text 00000000 __EH_FRAME_BEGIN__ -080060f0 l F .text 00000000 deregister_tm_clones -08006118 l F .text 00000000 register_tm_clones -08006148 l F .text 00000000 __do_global_dtors_aux -2000001c l .bss 00000000 completed.7922 -20000018 l O .data 00000000 __do_global_dtors_aux_fini_array_entry -08006178 l F .text 00000000 frame_dummy -20000020 l .bss 00000000 object.7927 -20000014 l O .data 00000000 __frame_dummy_init_array_entry -00000000 l df *ABS* 00000000 boot.c -08006270 l F .text 00000060 CanGetSpeedConfig -080062d0 l F .text 00000086 BootComUartInit -08006358 l F .text 000000fe BootComCanInit -08006458 l F .text 0000002c UartReceiveByte -080064b0 l F .text 000000d8 BootComUartCheckActivationRequest -08006588 l F .text 00000046 BootComCanCheckActivationRequest -20000038 l O .bss 00000004 xcpCtoRxStartTime.6448 -2000003c l O .bss 00000041 xcpCtoReqPacket.6445 -20000080 l O .bss 00000001 xcpCtoRxLength.6446 -20000081 l O .bss 00000001 xcpCtoRxInProgress.6447 -08006ed8 l O .text 00000024 canTiming -00000000 l df *ABS* 00000000 led.c -20000084 l O .bss 00000004 timer_counter_last.6426 -20000088 l O .bss 00000001 led_toggle_state.6425 -00000000 l df *ABS* 00000000 stm32f10x_can.c -00000000 l df *ABS* 00000000 stm32f10x_gpio.c -00000000 l df *ABS* 00000000 stm32f10x_rcc.c -20000000 l O .data 00000004 ADCPrescTable -20000004 l O .data 00000010 APBAHBPrescTable -00000000 l df *ABS* 00000000 stm32f10x_usart.c -00000000 l df *ABS* 00000000 main.c -08006d30 l F .text 00000122 Init -00000000 l df *ABS* 00000000 timer.c -2000008c l O .bss 00000004 millisecond_counter -00000000 l df *ABS* 00000000 c:/users/frank voorburg/mentorgraphics/sourcery_codebench_lite_for_arm_eabi/bin/../lib/gcc/arm-none-eabi/4.8.1/thumb2/crti.o -00000000 l df *ABS* 00000000 c:/users/frank voorburg/mentorgraphics/sourcery_codebench_lite_for_arm_eabi/bin/../lib/gcc/arm-none-eabi/4.8.1/thumb2/crtn.o -00000000 l df *ABS* 00000000 crtstuff.c -08006efc l O .text 00000000 __FRAME_END__ -00000000 l df *ABS* 00000000 -00000800 l *ABS* 00000000 __HEAP_SIZE -08006f00 l .text 00000000 __exidx_end -08006f00 l .text 00000000 __exidx_start -00000800 l *ABS* 00000000 __STACK_SIZE -08006222 w F .text 00000002 EXTI2_IRQHandler -20000090 g .heap 00000800 __HeapBase -0800620a w F .text 00000002 DebugMon_Handler -20000000 g .data 00000000 __data_start__ -08006248 w F .text 00000002 TIM1_CC_IRQHandler -08006200 w F .text 00000002 HardFault_Handler -080067b0 g F .text 00000126 CAN_FilterInit -08006eb0 g F .text 00000010 SysTick_Handler -08006214 w F .text 00000002 PVD_IRQHandler -0800620c w F .text 00000002 PendSV_Handler -080061fe w F .text 00000002 NMI_Handler -08006224 w F .text 00000002 EXTI3_IRQHandler -08006f00 g .text 00000000 __etext -08006d24 g F .text 0000000c USART_GetFlagStatus -2000001c g O .data 00000000 .hidden __TMC_END__ -08006a64 g F .text 00000072 GPIO_PinRemapConfig -0800621e w F .text 00000002 EXTI0_IRQHandler -08006254 w F .text 00000002 I2C2_EV_IRQHandler -08006d1c g F .text 00000008 USART_ReceiveData -08006206 w F .text 00000002 UsageFault_Handler -08006bc4 g F .text 00000024 RCC_APB2PeriphClockCmd -08006236 w F .text 00000002 ADC1_2_IRQHandler -080069b0 g F .text 000000aa GPIO_Init -20000890 g .heap 00000000 __HeapLimit -2000001c g .bss 00000000 __bss_start__ -08006258 w F .text 00000002 SPI1_IRQHandler -08006d00 g F .text 0000001c USART_Cmd -08006216 w F .text 00000002 TAMPER_IRQHandler -08006be8 g F .text 00000024 RCC_APB1PeriphClockCmd -0800622e w F .text 00000002 DMA1_Channel4_IRQHandler -08006684 g F .text 0000003a CAN_DeInit -08006ec0 g F .text 00000000 _init -08006490 g F .text 0000001e BootActivate -08006260 w F .text 00000002 USART3_IRQHandler -08006218 w F .text 00000002 RTC_IRQHandler -08006234 w F .text 00000002 DMA1_Channel7_IRQHandler -080061b8 g F .text 00000030 Reset_Handler -0800623c w F .text 00000002 CAN1_RX1_IRQHandler -080065dc g F .text 0000003a LedInit -08006a5c g F .text 00000004 GPIO_SetBits -0800624e w F .text 00000002 TIM4_IRQHandler -00000000 w *UND* 00000000 __deregister_frame_info -20000090 g .heap 00000000 end -08006250 w F .text 00000002 I2C1_EV_IRQHandler -2000001c g .data 00000000 __data_end__ -00000000 w *UND* 00000000 _ITM_registerTMCloneTable -08006ad8 g F .text 000000ea RCC_GetClocksFreq -08006232 w F .text 00000002 DMA1_Channel6_IRQHandler -08006c30 g F .text 000000d0 USART_Init -20000090 g .bss 00000000 __bss_end__ -0800624c w F .text 00000002 TIM3_IRQHandler -0800621c w F .text 00000002 RCC_IRQHandler -080068f8 g F .text 000000a0 CAN_Receive -08006246 w F .text 00000002 TIM1_TRG_COM_IRQHandler -080066c0 g F .text 000000ee CAN_Init -08006228 w F .text 00000002 DMA1_Channel1_IRQHandler -08006210 w F .text 00000002 Default_Handler -080061e8 w F .text 00000016 _start -080068d8 g F .text 00000020 CAN_StructInit -08006262 w F .text 00000002 EXTI15_10_IRQHandler -08006a60 g F .text 00000004 GPIO_ResetBits -08006240 w F .text 00000002 EXTI9_5_IRQHandler -00000000 w *UND* 00000000 _ITM_deregisterTMCloneTable -0800625a w F .text 00000002 SPI2_IRQHandler -08006202 w F .text 00000002 MemManage_Handler -08006000 g .text 000000f0 __isr_vector -08006e54 g F .text 00000014 main -08006208 w F .text 00000002 SVC_Handler -20000090 g .heap 00000000 __end__ -08006230 w F .text 00000002 DMA1_Channel5_IRQHandler -08006998 g F .text 00000018 CAN_MessagePending -08006226 w F .text 00000002 EXTI4_IRQHandler -08006e68 g F .text 0000000c TimerSet -0800623a w F .text 00000002 USB_LP_CAN1_RX0_IRQHandler -08006484 g F .text 0000000c BootComInit -08006ecc g F .text 00000000 _fini -08006238 w F .text 00000002 USB_HP_CAN1_TX_IRQHandler -0800622c w F .text 00000002 DMA1_Channel3_IRQHandler -20005000 g *ABS* 00000000 __StackTop -08006244 w F .text 00000002 TIM1_UP_IRQHandler -08006212 w F .text 00000002 WWDG_IRQHandler -08006c0c g F .text 00000024 RCC_APB1PeriphResetCmd -08006618 g F .text 0000006c LedToggle -0800624a w F .text 00000002 TIM2_IRQHandler -08006242 w F .text 00000002 TIM1_BRK_IRQHandler -08006220 w F .text 00000002 EXTI1_IRQHandler -08006264 w F .text 00000002 RTCAlarm_IRQHandler -20004800 g *ABS* 00000800 __StackLimit -0800625e w F .text 00000002 USART2_IRQHandler -08006256 w F .text 00000002 I2C2_ER_IRQHandler -0800622a w F .text 00000002 DMA1_Channel2_IRQHandler -080065d0 g F .text 0000000c BootComCheckActivationRequest -0800623e w F .text 00000002 CAN1_SCE_IRQHandler -0800621a w F .text 00000002 FLASH_IRQHandler -08006204 w F .text 00000002 BusFault_Handler -0800625c w F .text 00000002 USART1_IRQHandler -08006252 w F .text 00000002 I2C1_ER_IRQHandler -08006ea4 g F .text 0000000c TimerGet -00000000 w *UND* 00000000 _Jv_RegisterClasses -08006e74 g F .text 00000030 TimerInit -00000000 w *UND* 00000000 __register_frame_info -08006266 w F .text 00000002 USBWakeUp_IRQHandler - - + +bin/demoprog_olimex_stm32p103.elf: file format elf32-littlearm +bin/demoprog_olimex_stm32p103.elf +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x08006000 + +Program Header: +0x70000001 off 0x00006e7c vaddr 0x08006e7c paddr 0x08006e7c align 2**2 + filesz 0x00000008 memsz 0x00000008 flags r-- + LOAD off 0x00000000 vaddr 0x08000000 paddr 0x08000000 align 2**16 + filesz 0x00006e84 memsz 0x00006e84 flags r-x + LOAD off 0x00010000 vaddr 0x20000000 paddr 0x08006e84 align 2**16 + filesz 0x0000007c memsz 0x000000ec flags rw- +private flags = 5000200: [Version5 EABI] [soft-float ABI] + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00000e7c 08006000 08006000 00006000 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .ARM.exidx 00000008 08006e7c 08006e7c 00006e7c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .data 0000007c 20000000 08006e84 00010000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 3 .bss 00000070 2000007c 08006f00 0001007c 2**2 + ALLOC + 4 .heap 00000800 200000f0 200000f0 00010080 2**3 + CONTENTS, READONLY + 5 .stack_dummy 00000800 200000f0 200000f0 00010880 2**3 + CONTENTS, READONLY + 6 .ARM.attributes 00000029 00000000 00000000 00011080 2**0 + CONTENTS, READONLY + 7 .comment 0000006e 00000000 00000000 000110a9 2**0 + CONTENTS, READONLY + 8 .debug_line 00003224 00000000 00000000 00011117 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_info 0000452e 00000000 00000000 0001433b 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 00000faa 00000000 00000000 00018869 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_aranges 000004d8 00000000 00000000 00019818 2**3 + CONTENTS, READONLY, DEBUGGING + 12 .debug_loc 00002124 00000000 00000000 00019cf0 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_ranges 00000428 00000000 00000000 0001be14 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_macro 0000e746 00000000 00000000 0001c23c 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_str 00051cfc 00000000 00000000 0002a982 2**0 + CONTENTS, READONLY, DEBUGGING + 16 .debug_frame 00000a30 00000000 00000000 0007c680 2**2 + CONTENTS, READONLY, DEBUGGING +SYMBOL TABLE: +08006000 l d .text 00000000 .text +08006e7c l d .ARM.exidx 00000000 .ARM.exidx +20000000 l d .data 00000000 .data +2000007c l d .bss 00000000 .bss +200000f0 l d .heap 00000000 .heap +200000f0 l d .stack_dummy 00000000 .stack_dummy +00000000 l d .ARM.attributes 00000000 .ARM.attributes +00000000 l d .comment 00000000 .comment +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l d .debug_ranges 00000000 .debug_ranges +00000000 l d .debug_macro 00000000 .debug_macro +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l df *ABS* 00000000 obj/startup_stm32f10x_md.o +00000800 l *ABS* 00000000 Stack_Size +00000800 l *ABS* 00000000 Heap_Size +080061ca l .text 00000000 .flash_to_ram_loop +080061fc l .text 00000000 .fill_zero_bss +080061f8 l .text 00000000 .loop_zero_bss +00000000 l df *ABS* 00000000 crtstuff.c +08006e78 l O .text 00000000 __EH_FRAME_BEGIN__ +080060f0 l F .text 00000000 __do_global_dtors_aux +2000007c l .bss 00000000 completed.8603 +20000078 l O .data 00000000 __do_global_dtors_aux_fini_array_entry +08006114 l F .text 00000000 frame_dummy +20000080 l .bss 00000000 object.8608 +20000074 l O .data 00000000 __frame_dummy_init_array_entry +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7-m/crt0.o +00000000 l df *ABS* 00000000 boot.c +08006278 l F .text 00000058 CanGetSpeedConfig +080062d0 l F .text 00000080 BootComUartInit +08006350 l F .text 000000fc BootComCanInit +0800644c l F .text 00000024 UartReceiveByte +08006498 l F .text 00000094 BootComUartCheckActivationRequest +0800652c l F .text 00000040 BootComCanCheckActivationRequest +20000098 l O .bss 00000004 xcpCtoRxStartTime.6574 +2000009c l O .bss 00000041 xcpCtoReqPacket.6571 +200000dd l O .bss 00000001 xcpCtoRxLength.6572 +200000de l O .bss 00000001 xcpCtoRxInProgress.6573 +08006e50 l O .text 00000024 canTiming +00000000 l df *ABS* 00000000 main.c +08006578 l F .text 00000104 Init +00000000 l df *ABS* 00000000 led.c +200000e0 l O .bss 00000004 timer_counter_last.6552 +200000e4 l O .bss 00000001 led_toggle_state.6551 +00000000 l df *ABS* 00000000 timer.c +200000e8 l O .bss 00000004 millisecond_counter +00000000 l df *ABS* 00000000 stm32f10x_can.c +00000000 l df *ABS* 00000000 stm32f10x_rcc.c +20000000 l O .data 00000004 ADCPrescTable +20000004 l O .data 00000010 APBAHBPrescTable +00000000 l df *ABS* 00000000 stm32f10x_usart.c +00000000 l df *ABS* 00000000 stm32f10x_gpio.c +00000000 l df *ABS* 00000000 _exit.c +00000000 l df *ABS* 00000000 exit.c +00000000 l df *ABS* 00000000 init.c +00000000 l df *ABS* 00000000 memset.c +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crti.o +00000000 l df *ABS* 00000000 /opt/gcc-arm-none-eabi-5_4-2016q3/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7-m/crtn.o +00000000 l df *ABS* 00000000 impure.c +20000014 l O .data 00000060 impure_data +00000000 l df *ABS* 00000000 crtstuff.c +08006e78 l O .text 00000000 __FRAME_END__ +00000000 l df *ABS* 00000000 +20000078 l .data 00000000 __init_array_end +20000074 l .data 00000000 __preinit_array_end +20000074 l .data 00000000 __init_array_start +20000074 l .data 00000000 __preinit_array_start +0800622a w F .text 00000002 EXTI2_IRQHandler +200000f0 g .heap 00000800 __HeapBase +08006212 w F .text 00000002 DebugMon_Handler +00000800 g *ABS* 00000000 __HEAP_SIZE +20000000 g .data 00000000 __data_start__ +08006250 w F .text 00000002 TIM1_CC_IRQHandler +08006208 w F .text 00000002 HardFault_Handler +080068b8 g F .text 000000f4 CAN_FilterInit +08006760 g F .text 00000010 SysTick_Handler +0800621c w F .text 00000002 PVD_IRQHandler +08006214 w F .text 00000002 PendSV_Handler +08006206 w F .text 00000002 NMI_Handler +08006e84 g .ARM.exidx 00000000 __exidx_end +0800622c w F .text 00000002 EXTI3_IRQHandler +08006e84 g .ARM.exidx 00000000 __etext +08006c88 g F .text 0000000e USART_GetFlagStatus +08006d3c g F .text 00000074 GPIO_PinRemapConfig +08006226 w F .text 00000002 EXTI0_IRQHandler +0800625c w F .text 00000002 I2C2_EV_IRQHandler +08006c80 g F .text 00000008 USART_ReceiveData +0800620e w F .text 00000002 UsageFault_Handler +08006b48 g F .text 0000001c RCC_APB2PeriphClockCmd +0800623e w F .text 00000002 ADC1_2_IRQHandler +08006c98 g F .text 0000009a GPIO_Init +200008f0 g .heap 00000000 __HeapLimit +2000007c g .bss 00000000 __bss_start__ +08006260 w F .text 00000002 SPI1_IRQHandler +08006c64 g F .text 0000001c USART_Cmd +0800621e w F .text 00000002 TAMPER_IRQHandler +08006b64 g F .text 0000001c RCC_APB1PeriphClockCmd +08006e7c g .text 00000000 __exidx_start +08006e74 g O .text 00000004 _global_impure_ptr +08006ddc g F .text 0000004c __libc_init_array +08006236 w F .text 00000002 DMA1_Channel4_IRQHandler +0800614c g F .text 00000000 _mainCRTStartup +08006770 g F .text 00000038 CAN_DeInit +08006e38 g F .text 00000000 _init +0800647c g F .text 0000001c BootActivate +08006268 w F .text 00000002 USART3_IRQHandler +00000000 w *UND* 00000000 __libc_fini_array +08006220 w F .text 00000002 RTC_IRQHandler +0800623c w F .text 00000002 DMA1_Channel7_IRQHandler +080061c0 g F .text 00000030 Reset_Handler +08006244 w F .text 00000002 CAN1_RX1_IRQHandler +08006690 g F .text 0000003c LedInit +08006d34 g F .text 00000004 GPIO_SetBits +08006256 w F .text 00000002 TIM4_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stderr +00000000 w *UND* 00000000 __deregister_frame_info +200000f0 g .heap 00000000 end +08006258 w F .text 00000002 I2C1_EV_IRQHandler +2000007c g .data 00000000 __data_end__ +08006a8c g F .text 000000bc RCC_GetClocksFreq +0800623a w F .text 00000002 DMA1_Channel6_IRQHandler +08006b9c g F .text 000000c8 USART_Init +200000ec g .bss 00000000 __bss_end__ +00000800 g *ABS* 00000000 __STACK_SIZE +08006254 w F .text 00000002 TIM3_IRQHandler +08006224 w F .text 00000002 RCC_IRQHandler +080069cc g F .text 000000a4 CAN_Receive +0800624e w F .text 00000002 TIM1_TRG_COM_IRQHandler +00000000 w *UND* 00000000 __call_exitprocs +080067a8 g F .text 0000010e CAN_Init +08006230 w F .text 00000002 DMA1_Channel1_IRQHandler +08006218 w F .text 00000002 Default_Handler +0800614c g F .text 00000000 _start +080069ac g F .text 00000020 CAN_StructInit +0800626a w F .text 00000002 EXTI15_10_IRQHandler +00000000 w *UND* 00000000 software_init_hook +08006d38 g F .text 00000004 GPIO_ResetBits +08006248 w F .text 00000002 EXTI9_5_IRQHandler +08006262 w F .text 00000002 SPI2_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stdin +08006e28 g F .text 00000010 memset +0800620a w F .text 00000002 MemManage_Handler +08006000 g .text 000000f0 __isr_vector +0800667c g F .text 00000014 main +08006210 w F .text 00000002 SVC_Handler +00000000 w *UND* 00000000 hardware_init_hook +200000f0 g .heap 00000000 __end__ +08006238 w F .text 00000002 DMA1_Channel5_IRQHandler +08006a70 g F .text 0000001a CAN_MessagePending +0800622e w F .text 00000002 EXTI4_IRQHandler +0800671c g F .text 0000000c TimerSet +08006242 w F .text 00000002 USB_LP_CAN1_RX0_IRQHandler +08006470 g F .text 0000000c BootComInit +08006e44 g F .text 00000000 _fini +08006240 w F .text 00000002 USB_HP_CAN1_TX_IRQHandler +00000000 w *UND* 00000000 atexit +08006234 w F .text 00000002 DMA1_Channel3_IRQHandler +20005000 g .bss 00000000 __StackTop +0800624c w F .text 00000002 TIM1_UP_IRQHandler +0800621a w F .text 00000002 WWDG_IRQHandler +08006b80 g F .text 0000001c RCC_APB1PeriphResetCmd +080066cc g F .text 00000050 LedToggle +08006252 w F .text 00000002 TIM2_IRQHandler +0800624a w F .text 00000002 TIM1_BRK_IRQHandler +20005000 g *ABS* 00000000 __stack +08006228 w F .text 00000002 EXTI1_IRQHandler +0800626c w F .text 00000002 RTCAlarm_IRQHandler +20004800 g *ABS* 00000800 __StackLimit +08006266 w F .text 00000002 USART2_IRQHandler +08006db4 g F .text 00000028 exit +0800625e w F .text 00000002 I2C2_ER_IRQHandler +08006232 w F .text 00000002 DMA1_Channel2_IRQHandler +00000000 w *UND* 00000000 __sf_fake_stdout +0800656c g F .text 0000000c BootComCheckActivationRequest +08006246 w F .text 00000002 CAN1_SCE_IRQHandler +08006222 w F .text 00000002 FLASH_IRQHandler +08006db0 w F .text 00000002 _exit +0800620c w F .text 00000002 BusFault_Handler +08006264 w F .text 00000002 USART1_IRQHandler +0800625a w F .text 00000002 I2C1_ER_IRQHandler +08006754 g F .text 0000000c TimerGet +00000000 w *UND* 00000000 _Jv_RegisterClasses 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+S30D08006E7CD0F2FF7F01000000BF +S31508006E8402040608000000000102030401020304C8 +S31508006E9406070809000000000000000000000000C2 +S31508006EA400000000000000000000000000000000D0 +S31508006EB400000000000000000000000000000000C0 +S31508006EC400000000000000000000000000000000B0 +S31508006ED400000000000000000000000000000000A0 +S31508006EE40000000000000000000000000000000090 +S31108006EF40000000015610008F1600008AD S7050800600092 diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/cmd/build.bat b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/cmd/build.bat deleted file mode 100644 index 6cdb041e..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/cmd/build.bat +++ /dev/null @@ -1,2 +0,0 @@ -@echo off -cs-make --directory=../ all diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/cmd/clean.bat b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/cmd/clean.bat deleted file mode 100644 index 025aaea0..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/cmd/clean.bat +++ /dev/null @@ -1,2 +0,0 @@ -@echo off -cs-make --directory=../ clean diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/ide/DemoProg.project b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/ide/DemoProg.project deleted file mode 100644 index 82adcf28..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/ide/DemoProg.project +++ /dev/null @@ -1,168 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - break main -continue - - - - - - - make clean - make - - - - None - $(WorkspacePath)/.. - - - - - - - - - - - - - - - - - - - - - - - make clean - make - - - - None - $(WorkspacePath) - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/ide/DemoProg.workspace b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/ide/DemoProg.workspace deleted file mode 100644 index 4060139b..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/ide/DemoProg.workspace +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/ide/readme.txt b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/ide/readme.txt deleted file mode 100644 index 8a340a19..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/ide/readme.txt +++ /dev/null @@ -1,4 +0,0 @@ -Integrated Development Environment ----------------------------------- -Codelite was used as the editor during the development of this software program. This directory contains the Codelite -workspace and project files. Codelite is a cross platform open source C/C++ IDE, available at http://www.codelite.org/. \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/lib/newlib/_exit.c b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/lib/newlib/_exit.c new file mode 100644 index 00000000..4ae9532c --- /dev/null +++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/lib/newlib/_exit.c @@ -0,0 +1,38 @@ +// ---------------------------------------------------------------------------- + +#include + +// ---------------------------------------------------------------------------- + +// Forward declaration + +void +_exit(int code); + +// ---------------------------------------------------------------------------- + +// We just enter an infinite loop, to be used as landmark when halting +// the debugger. +// +// It can be redefined in the application, if more functionality +// is required. + +void +__attribute__((weak)) +_exit(int code __attribute__((unused))) +{ + // TODO: write on trace + while (1) + ; +} + +// ---------------------------------------------------------------------------- + +void +__attribute__((weak,noreturn)) +abort(void) +{ + _exit(1); +} + +// ---------------------------------------------------------------------------- diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/makefile b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/makefile index 5f7beb9a..f90d2188 100644 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/makefile +++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Prog/makefile @@ -34,7 +34,7 @@ PROJ_NAME=demoprog_olimex_stm32p103 #|--------------------------------------------------------------------------------------| #| Configure tool path | #|--------------------------------------------------------------------------------------| -TOOL_PATH= +TOOL_PATH=/opt/gcc-arm-none-eabi-5_4-2016q3/bin/ #|--------------------------------------------------------------------------------------| @@ -54,7 +54,7 @@ PROJ_FILES = $(call rwildcard, , *.c *.h *.S) #|--------------------------------------------------------------------------------------| #| Toolchain binaries | #|--------------------------------------------------------------------------------------| -RM = cs-rm +RM = rm CC = $(TOOL_PATH)arm-none-eabi-gcc LN = $(TOOL_PATH)arm-none-eabi-gcc OC = $(TOOL_PATH)arm-none-eabi-objcopy @@ -97,7 +97,7 @@ AFLAGS = $(CFLAGS) LFLAGS = $(STDFLAGS) $(OPTFLAGS) LFLAGS += -Wl,--defsym=__HEAP_SIZE=$(HEAP_SIZE) -Wl,--defsym=__STACK_SIZE=$(STACK_SIZE) LFLAGS += -Wl,-script="stm32f103rb_flash.ld" -Wl,-Map=$(BIN_PATH)/$(PROJ_NAME).map -LFLAGS += -Wl,--gc-sections $(LIB_PATH) +LFLAGS += -specs=nano.specs -Wl,--gc-sections $(LIB_PATH) OFLAGS = -O srec ODFLAGS = -x SZFLAGS = -B -d diff --git a/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/bin/openblt_olimexino_stm32.elf b/Target/Demo/ARMCM3_STM32F1_Olimexino_STM32_GCC/Boot/bin/openblt_olimexino_stm32.elf index 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a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Prog/ide/readme.txt b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Prog/ide/readme.txt deleted file mode 100644 index 8a340a19..00000000 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Prog/ide/readme.txt +++ /dev/null @@ -1,4 +0,0 @@ -Integrated Development Environment ----------------------------------- -Codelite was used as the editor during the development of this software program. This directory contains the Codelite -workspace and project files. Codelite is a cross platform open source C/C++ IDE, available at http://www.codelite.org/. \ No newline at end of file diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Prog/lib/newlib/_exit.c b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Prog/lib/newlib/_exit.c new file mode 100644 index 00000000..4ae9532c --- /dev/null +++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Prog/lib/newlib/_exit.c @@ -0,0 +1,38 @@ +// ---------------------------------------------------------------------------- + +#include + +// ---------------------------------------------------------------------------- + +// Forward declaration + +void +_exit(int code); + +// ---------------------------------------------------------------------------- + +// We just enter an infinite loop, to be used as landmark when halting +// the debugger. +// +// It can be redefined in the application, if more functionality +// is required. + +void +__attribute__((weak)) +_exit(int code __attribute__((unused))) +{ + // TODO: write on trace + while (1) + ; +} + +// ---------------------------------------------------------------------------- + +void +__attribute__((weak,noreturn)) +abort(void) +{ + _exit(1); +} + +// ---------------------------------------------------------------------------- diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Prog/makefile b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Prog/makefile index fc6c090d..448c6939 100644 --- a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Prog/makefile +++ b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32H103_GCC/Prog/makefile @@ -34,7 +34,7 @@ PROJ_NAME=demoprog_olimex_stm32h103 #|--------------------------------------------------------------------------------------| #| Configure tool path | #|--------------------------------------------------------------------------------------| -TOOL_PATH= +TOOL_PATH=/opt/gcc-arm-none-eabi-5_4-2016q3/bin/ #|--------------------------------------------------------------------------------------| @@ -54,7 +54,7 @@ PROJ_FILES = $(call rwildcard, , *.c *.h *.S) #|--------------------------------------------------------------------------------------| #| Toolchain binaries | #|--------------------------------------------------------------------------------------| -RM = cs-rm +RM = rm CC = $(TOOL_PATH)arm-none-eabi-gcc LN = $(TOOL_PATH)arm-none-eabi-gcc OC = $(TOOL_PATH)arm-none-eabi-objcopy @@ -97,7 +97,7 @@ AFLAGS = $(CFLAGS) LFLAGS = $(STDFLAGS) $(OPTFLAGS) LFLAGS += -Wl,--defsym=__HEAP_SIZE=$(HEAP_SIZE) -Wl,--defsym=__STACK_SIZE=$(STACK_SIZE) LFLAGS += -Wl,-script="stm32f103rb_flash.ld" -Wl,-Map=$(BIN_PATH)/$(PROJ_NAME).map -LFLAGS += -Wl,--gc-sections $(LIB_PATH) +LFLAGS += -specs=nano.specs -Wl,--gc-sections $(LIB_PATH) OFLAGS = -O srec ODFLAGS = -x SZFLAGS = -B -d diff --git a/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/bin/openblt_olimex_stm32p103.elf b/Target/Demo/ARMCM3_STM32F1_Olimex_STM32P103_GCC/Boot/bin/openblt_olimex_stm32p103.elf index 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